Commit | Line | Data |
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740a01ee MS |
1 | /* |
2 | * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd. | |
2a96536e KC |
3 | * http://www.samsung.com |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
11 | #define DEBUG | |
12 | #endif | |
13 | ||
2a96536e | 14 | #include <linux/clk.h> |
8ed55c81 | 15 | #include <linux/dma-mapping.h> |
2a96536e | 16 | #include <linux/err.h> |
312900c6 | 17 | #include <linux/io.h> |
2a96536e | 18 | #include <linux/iommu.h> |
312900c6 | 19 | #include <linux/interrupt.h> |
2a96536e | 20 | #include <linux/list.h> |
8ed55c81 MS |
21 | #include <linux/of.h> |
22 | #include <linux/of_iommu.h> | |
23 | #include <linux/of_platform.h> | |
312900c6 MS |
24 | #include <linux/platform_device.h> |
25 | #include <linux/pm_runtime.h> | |
26 | #include <linux/slab.h> | |
58c6f6a3 | 27 | #include <linux/dma-iommu.h> |
2a96536e | 28 | |
d09d78fc CK |
29 | typedef u32 sysmmu_iova_t; |
30 | typedef u32 sysmmu_pte_t; | |
31 | ||
f171abab | 32 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
33 | #define SECT_ORDER 20 |
34 | #define LPAGE_ORDER 16 | |
35 | #define SPAGE_ORDER 12 | |
36 | ||
37 | #define SECT_SIZE (1 << SECT_ORDER) | |
38 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
39 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
40 | ||
41 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
42 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
43 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
44 | ||
66a7ed84 CK |
45 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
46 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
47 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
48 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
49 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
50 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
51 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
52 | ||
53 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
54 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
55 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
56 | ||
6ae5343c BD |
57 | #ifdef CONFIG_BIG_ENDIAN |
58 | #warning "revisit driver if we can enable big-endian ptes" | |
59 | #endif | |
60 | ||
740a01ee MS |
61 | /* |
62 | * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces | |
63 | * v5.0 introduced support for 36bit physical address space by shifting | |
64 | * all page entry values by 4 bits. | |
65 | * All SYSMMU controllers in the system support the address spaces of the same | |
66 | * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper | |
67 | * value (0 or 4). | |
68 | */ | |
69 | static short PG_ENT_SHIFT = -1; | |
70 | #define SYSMMU_PG_ENT_SHIFT 0 | |
71 | #define SYSMMU_V5_PG_ENT_SHIFT 4 | |
72 | ||
1a0d8dac MS |
73 | static const sysmmu_pte_t *LV1_PROT; |
74 | static const sysmmu_pte_t SYSMMU_LV1_PROT[] = { | |
75 | ((0 << 15) | (0 << 10)), /* no access */ | |
76 | ((1 << 15) | (1 << 10)), /* IOMMU_READ only */ | |
77 | ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */ | |
78 | ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */ | |
79 | }; | |
80 | static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = { | |
81 | (0 << 4), /* no access */ | |
82 | (1 << 4), /* IOMMU_READ only */ | |
83 | (2 << 4), /* IOMMU_WRITE only */ | |
84 | (3 << 4), /* IOMMU_READ | IOMMU_WRITE */ | |
85 | }; | |
86 | ||
87 | static const sysmmu_pte_t *LV2_PROT; | |
88 | static const sysmmu_pte_t SYSMMU_LV2_PROT[] = { | |
89 | ((0 << 9) | (0 << 4)), /* no access */ | |
90 | ((1 << 9) | (1 << 4)), /* IOMMU_READ only */ | |
91 | ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */ | |
92 | ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */ | |
93 | }; | |
94 | static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = { | |
95 | (0 << 2), /* no access */ | |
96 | (1 << 2), /* IOMMU_READ only */ | |
97 | (2 << 2), /* IOMMU_WRITE only */ | |
98 | (3 << 2), /* IOMMU_READ | IOMMU_WRITE */ | |
99 | }; | |
100 | ||
101 | #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE) | |
102 | ||
740a01ee MS |
103 | #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT) |
104 | #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK) | |
105 | #define section_offs(iova) (iova & (SECT_SIZE - 1)) | |
106 | #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK) | |
107 | #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1)) | |
108 | #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK) | |
109 | #define spage_offs(iova) (iova & (SPAGE_SIZE - 1)) | |
2a96536e KC |
110 | |
111 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 112 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 113 | |
d09d78fc CK |
114 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
115 | { | |
116 | return iova >> SECT_ORDER; | |
117 | } | |
118 | ||
119 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
120 | { | |
121 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
122 | } | |
123 | ||
5e3435eb | 124 | #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) |
d09d78fc | 125 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) |
2a96536e KC |
126 | |
127 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
740a01ee | 128 | #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0)) |
2a96536e | 129 | |
1a0d8dac | 130 | #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2) |
740a01ee | 131 | #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1) |
1a0d8dac MS |
132 | #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1) |
133 | #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2) | |
2a96536e KC |
134 | |
135 | #define CTRL_ENABLE 0x5 | |
136 | #define CTRL_BLOCK 0x7 | |
137 | #define CTRL_DISABLE 0x0 | |
138 | ||
eeb5184b | 139 | #define CFG_LRU 0x1 |
1a0d8dac | 140 | #define CFG_EAP (1 << 2) |
eeb5184b | 141 | #define CFG_QOS(n) ((n & 0xF) << 7) |
eeb5184b CK |
142 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ |
143 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
144 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
145 | ||
740a01ee | 146 | /* common registers */ |
2a96536e KC |
147 | #define REG_MMU_CTRL 0x000 |
148 | #define REG_MMU_CFG 0x004 | |
149 | #define REG_MMU_STATUS 0x008 | |
740a01ee MS |
150 | #define REG_MMU_VERSION 0x034 |
151 | ||
152 | #define MMU_MAJ_VER(val) ((val) >> 7) | |
153 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
154 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
155 | ||
156 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
157 | ||
158 | /* v1.x - v3.x registers */ | |
2a96536e KC |
159 | #define REG_MMU_FLUSH 0x00C |
160 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
161 | #define REG_PT_BASE_ADDR 0x014 | |
162 | #define REG_INT_STATUS 0x018 | |
163 | #define REG_INT_CLEAR 0x01C | |
164 | ||
165 | #define REG_PAGE_FAULT_ADDR 0x024 | |
166 | #define REG_AW_FAULT_ADDR 0x028 | |
167 | #define REG_AR_FAULT_ADDR 0x02C | |
168 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
169 | ||
740a01ee MS |
170 | /* v5.x registers */ |
171 | #define REG_V5_PT_BASE_PFN 0x00C | |
172 | #define REG_V5_MMU_FLUSH_ALL 0x010 | |
173 | #define REG_V5_MMU_FLUSH_ENTRY 0x014 | |
174 | #define REG_V5_INT_STATUS 0x060 | |
175 | #define REG_V5_INT_CLEAR 0x064 | |
176 | #define REG_V5_FAULT_AR_VA 0x070 | |
177 | #define REG_V5_FAULT_AW_VA 0x080 | |
2a96536e | 178 | |
6b21a5db CK |
179 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
180 | ||
5e3435eb | 181 | static struct device *dma_dev; |
734c3c73 | 182 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
183 | static sysmmu_pte_t *zero_lv2_table; |
184 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 185 | |
d09d78fc | 186 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
187 | { |
188 | return pgtable + lv1ent_offset(iova); | |
189 | } | |
190 | ||
d09d78fc | 191 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 192 | { |
d09d78fc | 193 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 194 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
195 | } |
196 | ||
d093fc7e MS |
197 | /* |
198 | * IOMMU fault information register | |
199 | */ | |
200 | struct sysmmu_fault_info { | |
201 | unsigned int bit; /* bit number in STATUS register */ | |
202 | unsigned short addr_reg; /* register to read VA fault address */ | |
203 | const char *name; /* human readable fault name */ | |
204 | unsigned int type; /* fault type for report_iommu_fault */ | |
2a96536e KC |
205 | }; |
206 | ||
d093fc7e MS |
207 | static const struct sysmmu_fault_info sysmmu_faults[] = { |
208 | { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ }, | |
209 | { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ }, | |
210 | { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, | |
211 | { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ }, | |
212 | { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, | |
213 | { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, | |
214 | { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, | |
215 | { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, | |
2a96536e KC |
216 | }; |
217 | ||
740a01ee MS |
218 | static const struct sysmmu_fault_info sysmmu_v5_faults[] = { |
219 | { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ }, | |
220 | { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ }, | |
221 | { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ }, | |
222 | { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, | |
223 | { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, | |
224 | { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE }, | |
225 | { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE }, | |
226 | { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, | |
227 | { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, | |
228 | { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, | |
229 | }; | |
230 | ||
2860af3c MS |
231 | /* |
232 | * This structure is attached to dev.archdata.iommu of the master device | |
233 | * on device add, contains a list of SYSMMU controllers defined by device tree, | |
234 | * which are bound to given master device. It is usually referenced by 'owner' | |
235 | * pointer. | |
236 | */ | |
6b21a5db | 237 | struct exynos_iommu_owner { |
1b092054 | 238 | struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ |
5fa61cbf | 239 | struct iommu_domain *domain; /* domain this device is attached */ |
9b265536 | 240 | struct mutex rpm_lock; /* for runtime pm of all sysmmus */ |
6b21a5db CK |
241 | }; |
242 | ||
2860af3c MS |
243 | /* |
244 | * This structure exynos specific generalization of struct iommu_domain. | |
245 | * It contains list of SYSMMU controllers from all master devices, which has | |
246 | * been attached to this domain and page tables of IO address space defined by | |
247 | * it. It is usually referenced by 'domain' pointer. | |
248 | */ | |
2a96536e | 249 | struct exynos_iommu_domain { |
2860af3c MS |
250 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
251 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
252 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
253 | spinlock_t lock; /* lock for modyfying list of clients */ | |
254 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 255 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
256 | }; |
257 | ||
2860af3c MS |
258 | /* |
259 | * This structure hold all data of a single SYSMMU controller, this includes | |
260 | * hw resources like registers and clocks, pointers and list nodes to connect | |
261 | * it to all other structures, internal state and parameters read from device | |
262 | * tree. It is usually referenced by 'data' pointer. | |
263 | */ | |
2a96536e | 264 | struct sysmmu_drvdata { |
2860af3c MS |
265 | struct device *sysmmu; /* SYSMMU controller device */ |
266 | struct device *master; /* master device (owner) */ | |
267 | void __iomem *sfrbase; /* our registers */ | |
268 | struct clk *clk; /* SYSMMU's clock */ | |
740a01ee MS |
269 | struct clk *aclk; /* SYSMMU's aclk clock */ |
270 | struct clk *pclk; /* SYSMMU's pclk clock */ | |
2860af3c | 271 | struct clk *clk_master; /* master's device clock */ |
2860af3c | 272 | spinlock_t lock; /* lock for modyfying state */ |
47a574ff | 273 | bool active; /* current status */ |
2860af3c MS |
274 | struct exynos_iommu_domain *domain; /* domain we belong to */ |
275 | struct list_head domain_node; /* node for domain clients list */ | |
1b092054 | 276 | struct list_head owner_node; /* node for owner controllers list */ |
2860af3c MS |
277 | phys_addr_t pgtable; /* assigned page table structure */ |
278 | unsigned int version; /* our version */ | |
2a96536e KC |
279 | }; |
280 | ||
e1fd1eaa JR |
281 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
282 | { | |
283 | return container_of(dom, struct exynos_iommu_domain, domain); | |
284 | } | |
285 | ||
02cdc365 | 286 | static void sysmmu_unblock(struct sysmmu_drvdata *data) |
2a96536e | 287 | { |
84bd0428 | 288 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e KC |
289 | } |
290 | ||
02cdc365 | 291 | static bool sysmmu_block(struct sysmmu_drvdata *data) |
2a96536e KC |
292 | { |
293 | int i = 120; | |
294 | ||
84bd0428 MS |
295 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
296 | while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1)) | |
2a96536e KC |
297 | --i; |
298 | ||
84bd0428 | 299 | if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) { |
02cdc365 | 300 | sysmmu_unblock(data); |
2a96536e KC |
301 | return false; |
302 | } | |
303 | ||
304 | return true; | |
305 | } | |
306 | ||
02cdc365 | 307 | static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) |
2a96536e | 308 | { |
740a01ee | 309 | if (MMU_MAJ_VER(data->version) < 5) |
84bd0428 | 310 | writel(0x1, data->sfrbase + REG_MMU_FLUSH); |
740a01ee | 311 | else |
84bd0428 | 312 | writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL); |
2a96536e KC |
313 | } |
314 | ||
02cdc365 | 315 | static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
d09d78fc | 316 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 317 | { |
3ad6b7f3 | 318 | unsigned int i; |
365409db | 319 | |
3ad6b7f3 | 320 | for (i = 0; i < num_inv; i++) { |
740a01ee | 321 | if (MMU_MAJ_VER(data->version) < 5) |
84bd0428 | 322 | writel((iova & SPAGE_MASK) | 1, |
740a01ee MS |
323 | data->sfrbase + REG_MMU_FLUSH_ENTRY); |
324 | else | |
84bd0428 | 325 | writel((iova & SPAGE_MASK) | 1, |
740a01ee | 326 | data->sfrbase + REG_V5_MMU_FLUSH_ENTRY); |
3ad6b7f3 CK |
327 | iova += SPAGE_SIZE; |
328 | } | |
2a96536e KC |
329 | } |
330 | ||
02cdc365 | 331 | static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) |
2a96536e | 332 | { |
740a01ee | 333 | if (MMU_MAJ_VER(data->version) < 5) |
84bd0428 | 334 | writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); |
740a01ee | 335 | else |
84bd0428 | 336 | writel(pgd >> PAGE_SHIFT, |
740a01ee | 337 | data->sfrbase + REG_V5_PT_BASE_PFN); |
2a96536e | 338 | |
02cdc365 | 339 | __sysmmu_tlb_invalidate(data); |
2a96536e KC |
340 | } |
341 | ||
fecc49db MS |
342 | static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data) |
343 | { | |
344 | BUG_ON(clk_prepare_enable(data->clk_master)); | |
345 | BUG_ON(clk_prepare_enable(data->clk)); | |
346 | BUG_ON(clk_prepare_enable(data->pclk)); | |
347 | BUG_ON(clk_prepare_enable(data->aclk)); | |
348 | } | |
349 | ||
350 | static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data) | |
351 | { | |
352 | clk_disable_unprepare(data->aclk); | |
353 | clk_disable_unprepare(data->pclk); | |
354 | clk_disable_unprepare(data->clk); | |
355 | clk_disable_unprepare(data->clk_master); | |
356 | } | |
357 | ||
850d313e MS |
358 | static void __sysmmu_get_version(struct sysmmu_drvdata *data) |
359 | { | |
360 | u32 ver; | |
361 | ||
fecc49db | 362 | __sysmmu_enable_clocks(data); |
850d313e | 363 | |
84bd0428 | 364 | ver = readl(data->sfrbase + REG_MMU_VERSION); |
850d313e MS |
365 | |
366 | /* controllers on some SoCs don't report proper version */ | |
367 | if (ver == 0x80000001u) | |
368 | data->version = MAKE_MMU_VER(1, 0); | |
369 | else | |
370 | data->version = MMU_RAW_VER(ver); | |
371 | ||
372 | dev_dbg(data->sysmmu, "hardware version: %d.%d\n", | |
373 | MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); | |
374 | ||
fecc49db | 375 | __sysmmu_disable_clocks(data); |
850d313e MS |
376 | } |
377 | ||
d093fc7e MS |
378 | static void show_fault_information(struct sysmmu_drvdata *data, |
379 | const struct sysmmu_fault_info *finfo, | |
380 | sysmmu_iova_t fault_addr) | |
2a96536e | 381 | { |
d09d78fc | 382 | sysmmu_pte_t *ent; |
2a96536e | 383 | |
d093fc7e MS |
384 | dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n", |
385 | finfo->name, fault_addr, &data->pgtable); | |
386 | ent = section_entry(phys_to_virt(data->pgtable), fault_addr); | |
387 | dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent); | |
2a96536e KC |
388 | if (lv1ent_page(ent)) { |
389 | ent = page_entry(ent, fault_addr); | |
d093fc7e | 390 | dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent); |
2a96536e | 391 | } |
2a96536e KC |
392 | } |
393 | ||
394 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
395 | { | |
f171abab | 396 | /* SYSMMU is in blocked state when interrupt occurred. */ |
2a96536e | 397 | struct sysmmu_drvdata *data = dev_id; |
740a01ee MS |
398 | const struct sysmmu_fault_info *finfo; |
399 | unsigned int i, n, itype; | |
d093fc7e | 400 | sysmmu_iova_t fault_addr = -1; |
740a01ee | 401 | unsigned short reg_status, reg_clear; |
7222e8db | 402 | int ret = -ENOSYS; |
2a96536e | 403 | |
47a574ff | 404 | WARN_ON(!data->active); |
2a96536e | 405 | |
740a01ee MS |
406 | if (MMU_MAJ_VER(data->version) < 5) { |
407 | reg_status = REG_INT_STATUS; | |
408 | reg_clear = REG_INT_CLEAR; | |
409 | finfo = sysmmu_faults; | |
410 | n = ARRAY_SIZE(sysmmu_faults); | |
411 | } else { | |
412 | reg_status = REG_V5_INT_STATUS; | |
413 | reg_clear = REG_V5_INT_CLEAR; | |
414 | finfo = sysmmu_v5_faults; | |
415 | n = ARRAY_SIZE(sysmmu_v5_faults); | |
416 | } | |
417 | ||
9d4e7a24 CK |
418 | spin_lock(&data->lock); |
419 | ||
b398af21 | 420 | clk_enable(data->clk_master); |
9d4e7a24 | 421 | |
84bd0428 | 422 | itype = __ffs(readl(data->sfrbase + reg_status)); |
d093fc7e MS |
423 | for (i = 0; i < n; i++, finfo++) |
424 | if (finfo->bit == itype) | |
425 | break; | |
426 | /* unknown/unsupported fault */ | |
427 | BUG_ON(i == n); | |
428 | ||
429 | /* print debug message */ | |
84bd0428 | 430 | fault_addr = readl(data->sfrbase + finfo->addr_reg); |
d093fc7e | 431 | show_fault_information(data, finfo, fault_addr); |
2a96536e | 432 | |
d093fc7e MS |
433 | if (data->domain) |
434 | ret = report_iommu_fault(&data->domain->domain, | |
435 | data->master, fault_addr, finfo->type); | |
1fab7fa7 CK |
436 | /* fault is not recovered by fault handler */ |
437 | BUG_ON(ret != 0); | |
2a96536e | 438 | |
84bd0428 | 439 | writel(1 << itype, data->sfrbase + reg_clear); |
1fab7fa7 | 440 | |
02cdc365 | 441 | sysmmu_unblock(data); |
2a96536e | 442 | |
b398af21 | 443 | clk_disable(data->clk_master); |
70605870 | 444 | |
9d4e7a24 | 445 | spin_unlock(&data->lock); |
2a96536e KC |
446 | |
447 | return IRQ_HANDLED; | |
448 | } | |
449 | ||
47a574ff | 450 | static void __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 451 | { |
47a574ff MS |
452 | unsigned long flags; |
453 | ||
b398af21 | 454 | clk_enable(data->clk_master); |
70605870 | 455 | |
47a574ff | 456 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 MS |
457 | writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
458 | writel(0, data->sfrbase + REG_MMU_CFG); | |
47a574ff | 459 | data->active = false; |
6b21a5db CK |
460 | spin_unlock_irqrestore(&data->lock, flags); |
461 | ||
47a574ff | 462 | __sysmmu_disable_clocks(data); |
6b21a5db | 463 | } |
2a96536e | 464 | |
6b21a5db CK |
465 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
466 | { | |
83addecd MS |
467 | unsigned int cfg; |
468 | ||
83addecd MS |
469 | if (data->version <= MAKE_MMU_VER(3, 1)) |
470 | cfg = CFG_LRU | CFG_QOS(15); | |
471 | else if (data->version <= MAKE_MMU_VER(3, 2)) | |
472 | cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL; | |
473 | else | |
474 | cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN; | |
6b21a5db | 475 | |
1a0d8dac MS |
476 | cfg |= CFG_EAP; /* enable access protection bits check */ |
477 | ||
84bd0428 | 478 | writel(cfg, data->sfrbase + REG_MMU_CFG); |
6b21a5db CK |
479 | } |
480 | ||
47a574ff | 481 | static void __sysmmu_enable(struct sysmmu_drvdata *data) |
6b21a5db | 482 | { |
47a574ff MS |
483 | unsigned long flags; |
484 | ||
fecc49db | 485 | __sysmmu_enable_clocks(data); |
70605870 | 486 | |
47a574ff | 487 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 | 488 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 489 | __sysmmu_init_config(data); |
02cdc365 | 490 | __sysmmu_set_ptbase(data, data->pgtable); |
84bd0428 | 491 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
47a574ff MS |
492 | data->active = true; |
493 | spin_unlock_irqrestore(&data->lock, flags); | |
7222e8db | 494 | |
fecc49db MS |
495 | /* |
496 | * SYSMMU driver keeps master's clock enabled only for the short | |
497 | * time, while accessing the registers. For performing address | |
498 | * translation during DMA transaction it relies on the client | |
499 | * driver to enable it. | |
500 | */ | |
b398af21 | 501 | clk_disable(data->clk_master); |
6b21a5db | 502 | } |
70605870 | 503 | |
469acebe | 504 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
505 | sysmmu_iova_t iova) |
506 | { | |
507 | unsigned long flags; | |
66a7ed84 | 508 | |
66a7ed84 | 509 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 510 | if (data->active && data->version >= MAKE_MMU_VER(3, 3)) { |
01324ab2 MS |
511 | clk_enable(data->clk_master); |
512 | __sysmmu_tlb_invalidate_entry(data, iova, 1); | |
513 | clk_disable(data->clk_master); | |
d631ea98 | 514 | } |
66a7ed84 | 515 | spin_unlock_irqrestore(&data->lock, flags); |
66a7ed84 CK |
516 | } |
517 | ||
469acebe MS |
518 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
519 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
520 | { |
521 | unsigned long flags; | |
2a96536e | 522 | |
6b21a5db | 523 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 524 | if (data->active) { |
3ad6b7f3 | 525 | unsigned int num_inv = 1; |
70605870 | 526 | |
b398af21 | 527 | clk_enable(data->clk_master); |
70605870 | 528 | |
3ad6b7f3 CK |
529 | /* |
530 | * L2TLB invalidation required | |
531 | * 4KB page: 1 invalidation | |
f171abab SK |
532 | * 64KB page: 16 invalidations |
533 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
534 | * because it is set-associative TLB |
535 | * with 8-way and 64 sets. | |
536 | * 1MB page can be cached in one of all sets. | |
537 | * 64KB page can be one of 16 consecutive sets. | |
538 | */ | |
512bd0c6 | 539 | if (MMU_MAJ_VER(data->version) == 2) |
3ad6b7f3 CK |
540 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
541 | ||
02cdc365 MS |
542 | if (sysmmu_block(data)) { |
543 | __sysmmu_tlb_invalidate_entry(data, iova, num_inv); | |
544 | sysmmu_unblock(data); | |
2a96536e | 545 | } |
b398af21 | 546 | clk_disable(data->clk_master); |
2a96536e | 547 | } |
9d4e7a24 | 548 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
549 | } |
550 | ||
96f66557 MS |
551 | static struct iommu_ops exynos_iommu_ops; |
552 | ||
6b21a5db | 553 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 554 | { |
46c16d1e | 555 | int irq, ret; |
7222e8db | 556 | struct device *dev = &pdev->dev; |
2a96536e | 557 | struct sysmmu_drvdata *data; |
7222e8db | 558 | struct resource *res; |
2a96536e | 559 | |
46c16d1e CK |
560 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
561 | if (!data) | |
562 | return -ENOMEM; | |
2a96536e | 563 | |
7222e8db | 564 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
565 | data->sfrbase = devm_ioremap_resource(dev, res); |
566 | if (IS_ERR(data->sfrbase)) | |
567 | return PTR_ERR(data->sfrbase); | |
2a96536e | 568 | |
46c16d1e CK |
569 | irq = platform_get_irq(pdev, 0); |
570 | if (irq <= 0) { | |
0bf4e54d | 571 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 572 | return irq; |
2a96536e KC |
573 | } |
574 | ||
46c16d1e | 575 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
576 | dev_name(dev), data); |
577 | if (ret) { | |
46c16d1e CK |
578 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
579 | return ret; | |
2a96536e KC |
580 | } |
581 | ||
46c16d1e | 582 | data->clk = devm_clk_get(dev, "sysmmu"); |
0c2b063f | 583 | if (PTR_ERR(data->clk) == -ENOENT) |
740a01ee | 584 | data->clk = NULL; |
0c2b063f MS |
585 | else if (IS_ERR(data->clk)) |
586 | return PTR_ERR(data->clk); | |
740a01ee MS |
587 | |
588 | data->aclk = devm_clk_get(dev, "aclk"); | |
0c2b063f | 589 | if (PTR_ERR(data->aclk) == -ENOENT) |
740a01ee | 590 | data->aclk = NULL; |
0c2b063f MS |
591 | else if (IS_ERR(data->aclk)) |
592 | return PTR_ERR(data->aclk); | |
740a01ee MS |
593 | |
594 | data->pclk = devm_clk_get(dev, "pclk"); | |
0c2b063f | 595 | if (PTR_ERR(data->pclk) == -ENOENT) |
740a01ee | 596 | data->pclk = NULL; |
0c2b063f MS |
597 | else if (IS_ERR(data->pclk)) |
598 | return PTR_ERR(data->pclk); | |
740a01ee MS |
599 | |
600 | if (!data->clk && (!data->aclk || !data->pclk)) { | |
601 | dev_err(dev, "Failed to get device clock(s)!\n"); | |
602 | return -ENOSYS; | |
2a96536e KC |
603 | } |
604 | ||
70605870 | 605 | data->clk_master = devm_clk_get(dev, "master"); |
0c2b063f | 606 | if (PTR_ERR(data->clk_master) == -ENOENT) |
b398af21 | 607 | data->clk_master = NULL; |
0c2b063f MS |
608 | else if (IS_ERR(data->clk_master)) |
609 | return PTR_ERR(data->clk_master); | |
70605870 | 610 | |
2a96536e | 611 | data->sysmmu = dev; |
9d4e7a24 | 612 | spin_lock_init(&data->lock); |
2a96536e | 613 | |
7222e8db CK |
614 | platform_set_drvdata(pdev, data); |
615 | ||
850d313e | 616 | __sysmmu_get_version(data); |
740a01ee | 617 | if (PG_ENT_SHIFT < 0) { |
1a0d8dac | 618 | if (MMU_MAJ_VER(data->version) < 5) { |
740a01ee | 619 | PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; |
1a0d8dac MS |
620 | LV1_PROT = SYSMMU_LV1_PROT; |
621 | LV2_PROT = SYSMMU_LV2_PROT; | |
622 | } else { | |
740a01ee | 623 | PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT; |
1a0d8dac MS |
624 | LV1_PROT = SYSMMU_V5_LV1_PROT; |
625 | LV2_PROT = SYSMMU_V5_LV2_PROT; | |
626 | } | |
740a01ee MS |
627 | } |
628 | ||
f4723ec1 | 629 | pm_runtime_enable(dev); |
2a96536e | 630 | |
96f66557 MS |
631 | of_iommu_set_ops(dev->of_node, &exynos_iommu_ops); |
632 | ||
2a96536e | 633 | return 0; |
2a96536e KC |
634 | } |
635 | ||
9b265536 | 636 | static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) |
622015e4 MS |
637 | { |
638 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 639 | struct device *master = data->master; |
622015e4 | 640 | |
47a574ff | 641 | if (master) { |
9b265536 MS |
642 | struct exynos_iommu_owner *owner = master->archdata.iommu; |
643 | ||
644 | mutex_lock(&owner->rpm_lock); | |
92798b45 MS |
645 | if (data->domain) { |
646 | dev_dbg(data->sysmmu, "saving state\n"); | |
647 | __sysmmu_disable(data); | |
648 | } | |
9b265536 | 649 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
650 | } |
651 | return 0; | |
652 | } | |
653 | ||
9b265536 | 654 | static int __maybe_unused exynos_sysmmu_resume(struct device *dev) |
622015e4 MS |
655 | { |
656 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 657 | struct device *master = data->master; |
622015e4 | 658 | |
47a574ff | 659 | if (master) { |
9b265536 MS |
660 | struct exynos_iommu_owner *owner = master->archdata.iommu; |
661 | ||
662 | mutex_lock(&owner->rpm_lock); | |
92798b45 MS |
663 | if (data->domain) { |
664 | dev_dbg(data->sysmmu, "restoring state\n"); | |
665 | __sysmmu_enable(data); | |
666 | } | |
9b265536 | 667 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
668 | } |
669 | return 0; | |
670 | } | |
622015e4 MS |
671 | |
672 | static const struct dev_pm_ops sysmmu_pm_ops = { | |
9b265536 | 673 | SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL) |
2f5f44f2 MS |
674 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
675 | pm_runtime_force_resume) | |
622015e4 MS |
676 | }; |
677 | ||
6b21a5db CK |
678 | static const struct of_device_id sysmmu_of_match[] __initconst = { |
679 | { .compatible = "samsung,exynos-sysmmu", }, | |
680 | { }, | |
681 | }; | |
682 | ||
683 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
684 | .probe = exynos_sysmmu_probe, | |
685 | .driver = { | |
2a96536e | 686 | .name = "exynos-sysmmu", |
6b21a5db | 687 | .of_match_table = sysmmu_of_match, |
622015e4 | 688 | .pm = &sysmmu_pm_ops, |
b54b874f | 689 | .suppress_bind_attrs = true, |
2a96536e KC |
690 | } |
691 | }; | |
692 | ||
5e3435eb | 693 | static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) |
2a96536e | 694 | { |
5e3435eb MS |
695 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent), |
696 | DMA_TO_DEVICE); | |
6ae5343c | 697 | *ent = cpu_to_le32(val); |
5e3435eb MS |
698 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent), |
699 | DMA_TO_DEVICE); | |
2a96536e KC |
700 | } |
701 | ||
e1fd1eaa | 702 | static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) |
2a96536e | 703 | { |
bfa00489 | 704 | struct exynos_iommu_domain *domain; |
5e3435eb | 705 | dma_addr_t handle; |
66a7ed84 | 706 | int i; |
2a96536e | 707 | |
740a01ee MS |
708 | /* Check if correct PTE offsets are initialized */ |
709 | BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev); | |
e1fd1eaa | 710 | |
bfa00489 MS |
711 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
712 | if (!domain) | |
e1fd1eaa | 713 | return NULL; |
2a96536e | 714 | |
58c6f6a3 MS |
715 | if (type == IOMMU_DOMAIN_DMA) { |
716 | if (iommu_get_dma_cookie(&domain->domain) != 0) | |
717 | goto err_pgtable; | |
718 | } else if (type != IOMMU_DOMAIN_UNMANAGED) { | |
719 | goto err_pgtable; | |
720 | } | |
721 | ||
bfa00489 MS |
722 | domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
723 | if (!domain->pgtable) | |
58c6f6a3 | 724 | goto err_dma_cookie; |
2a96536e | 725 | |
bfa00489 MS |
726 | domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
727 | if (!domain->lv2entcnt) | |
2a96536e KC |
728 | goto err_counter; |
729 | ||
f171abab | 730 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
66a7ed84 | 731 | for (i = 0; i < NUM_LV1ENTRIES; i += 8) { |
bfa00489 MS |
732 | domain->pgtable[i + 0] = ZERO_LV2LINK; |
733 | domain->pgtable[i + 1] = ZERO_LV2LINK; | |
734 | domain->pgtable[i + 2] = ZERO_LV2LINK; | |
735 | domain->pgtable[i + 3] = ZERO_LV2LINK; | |
736 | domain->pgtable[i + 4] = ZERO_LV2LINK; | |
737 | domain->pgtable[i + 5] = ZERO_LV2LINK; | |
738 | domain->pgtable[i + 6] = ZERO_LV2LINK; | |
739 | domain->pgtable[i + 7] = ZERO_LV2LINK; | |
66a7ed84 CK |
740 | } |
741 | ||
5e3435eb MS |
742 | handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE, |
743 | DMA_TO_DEVICE); | |
744 | /* For mapping page table entries we rely on dma == phys */ | |
745 | BUG_ON(handle != virt_to_phys(domain->pgtable)); | |
2a96536e | 746 | |
bfa00489 MS |
747 | spin_lock_init(&domain->lock); |
748 | spin_lock_init(&domain->pgtablelock); | |
749 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 750 | |
bfa00489 MS |
751 | domain->domain.geometry.aperture_start = 0; |
752 | domain->domain.geometry.aperture_end = ~0UL; | |
753 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 754 | |
bfa00489 | 755 | return &domain->domain; |
2a96536e KC |
756 | |
757 | err_counter: | |
bfa00489 | 758 | free_pages((unsigned long)domain->pgtable, 2); |
58c6f6a3 MS |
759 | err_dma_cookie: |
760 | if (type == IOMMU_DOMAIN_DMA) | |
761 | iommu_put_dma_cookie(&domain->domain); | |
2a96536e | 762 | err_pgtable: |
bfa00489 | 763 | kfree(domain); |
e1fd1eaa | 764 | return NULL; |
2a96536e KC |
765 | } |
766 | ||
bfa00489 | 767 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 768 | { |
bfa00489 | 769 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 770 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
771 | unsigned long flags; |
772 | int i; | |
773 | ||
bfa00489 | 774 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 775 | |
bfa00489 | 776 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 777 | |
bfa00489 | 778 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
e1172300 | 779 | spin_lock(&data->lock); |
b0d4c861 | 780 | __sysmmu_disable(data); |
47a574ff MS |
781 | data->pgtable = 0; |
782 | data->domain = NULL; | |
469acebe | 783 | list_del_init(&data->domain_node); |
e1172300 | 784 | spin_unlock(&data->lock); |
2a96536e KC |
785 | } |
786 | ||
bfa00489 | 787 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 788 | |
58c6f6a3 MS |
789 | if (iommu_domain->type == IOMMU_DOMAIN_DMA) |
790 | iommu_put_dma_cookie(iommu_domain); | |
791 | ||
5e3435eb MS |
792 | dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE, |
793 | DMA_TO_DEVICE); | |
794 | ||
2a96536e | 795 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
5e3435eb MS |
796 | if (lv1ent_page(domain->pgtable + i)) { |
797 | phys_addr_t base = lv2table_base(domain->pgtable + i); | |
798 | ||
799 | dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, | |
800 | DMA_TO_DEVICE); | |
734c3c73 | 801 | kmem_cache_free(lv2table_kmem_cache, |
5e3435eb MS |
802 | phys_to_virt(base)); |
803 | } | |
2a96536e | 804 | |
bfa00489 MS |
805 | free_pages((unsigned long)domain->pgtable, 2); |
806 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
807 | kfree(domain); | |
2a96536e KC |
808 | } |
809 | ||
5fa61cbf MS |
810 | static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, |
811 | struct device *dev) | |
812 | { | |
813 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
814 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); | |
815 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); | |
816 | struct sysmmu_drvdata *data, *next; | |
817 | unsigned long flags; | |
5fa61cbf MS |
818 | |
819 | if (!has_sysmmu(dev) || owner->domain != iommu_domain) | |
820 | return; | |
821 | ||
9b265536 MS |
822 | mutex_lock(&owner->rpm_lock); |
823 | ||
824 | list_for_each_entry(data, &owner->controllers, owner_node) { | |
825 | pm_runtime_get_noresume(data->sysmmu); | |
826 | if (pm_runtime_active(data->sysmmu)) | |
827 | __sysmmu_disable(data); | |
e1172300 MS |
828 | pm_runtime_put(data->sysmmu); |
829 | } | |
830 | ||
5fa61cbf MS |
831 | spin_lock_irqsave(&domain->lock, flags); |
832 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { | |
e1172300 | 833 | spin_lock(&data->lock); |
47a574ff MS |
834 | data->pgtable = 0; |
835 | data->domain = NULL; | |
b0d4c861 | 836 | list_del_init(&data->domain_node); |
e1172300 | 837 | spin_unlock(&data->lock); |
5fa61cbf | 838 | } |
e1172300 | 839 | owner->domain = NULL; |
5fa61cbf MS |
840 | spin_unlock_irqrestore(&domain->lock, flags); |
841 | ||
9b265536 | 842 | mutex_unlock(&owner->rpm_lock); |
5fa61cbf | 843 | |
b0d4c861 MS |
844 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__, |
845 | &pagetable); | |
5fa61cbf MS |
846 | } |
847 | ||
bfa00489 | 848 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
849 | struct device *dev) |
850 | { | |
6b21a5db | 851 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
bfa00489 | 852 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 853 | struct sysmmu_drvdata *data; |
bfa00489 | 854 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 855 | unsigned long flags; |
2a96536e | 856 | |
469acebe MS |
857 | if (!has_sysmmu(dev)) |
858 | return -ENODEV; | |
2a96536e | 859 | |
5fa61cbf MS |
860 | if (owner->domain) |
861 | exynos_iommu_detach_device(owner->domain, dev); | |
862 | ||
9b265536 MS |
863 | mutex_lock(&owner->rpm_lock); |
864 | ||
e1172300 | 865 | spin_lock_irqsave(&domain->lock, flags); |
1b092054 | 866 | list_for_each_entry(data, &owner->controllers, owner_node) { |
e1172300 | 867 | spin_lock(&data->lock); |
47a574ff MS |
868 | data->pgtable = pagetable; |
869 | data->domain = domain; | |
e1172300 MS |
870 | list_add_tail(&data->domain_node, &domain->clients); |
871 | spin_unlock(&data->lock); | |
872 | } | |
873 | owner->domain = iommu_domain; | |
874 | spin_unlock_irqrestore(&domain->lock, flags); | |
875 | ||
9b265536 MS |
876 | list_for_each_entry(data, &owner->controllers, owner_node) { |
877 | pm_runtime_get_noresume(data->sysmmu); | |
878 | if (pm_runtime_active(data->sysmmu)) | |
879 | __sysmmu_enable(data); | |
880 | pm_runtime_put(data->sysmmu); | |
881 | } | |
882 | ||
883 | mutex_unlock(&owner->rpm_lock); | |
884 | ||
b0d4c861 MS |
885 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__, |
886 | &pagetable); | |
7222e8db | 887 | |
b0d4c861 | 888 | return 0; |
2a96536e KC |
889 | } |
890 | ||
bfa00489 | 891 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 892 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 893 | { |
61128f08 | 894 | if (lv1ent_section(sent)) { |
d09d78fc | 895 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
896 | return ERR_PTR(-EADDRINUSE); |
897 | } | |
898 | ||
2a96536e | 899 | if (lv1ent_fault(sent)) { |
d09d78fc | 900 | sysmmu_pte_t *pent; |
66a7ed84 | 901 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 902 | |
734c3c73 | 903 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
dbf6c6ef | 904 | BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 905 | if (!pent) |
61128f08 | 906 | return ERR_PTR(-ENOMEM); |
2a96536e | 907 | |
5e3435eb | 908 | update_pte(sent, mk_lv1ent_page(virt_to_phys(pent))); |
dc3814f4 | 909 | kmemleak_ignore(pent); |
2a96536e | 910 | *pgcounter = NUM_LV2ENTRIES; |
5e3435eb | 911 | dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE); |
66a7ed84 CK |
912 | |
913 | /* | |
f171abab SK |
914 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
915 | * FLPD cache may cache the address of zero_l2_table. This | |
916 | * function replaces the zero_l2_table with new L2 page table | |
917 | * to write valid mappings. | |
66a7ed84 | 918 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
919 | * cache may still cache zero_l2_table for the valid area |
920 | * instead of new L2 page table that has the mapping | |
921 | * information of the valid area. | |
66a7ed84 CK |
922 | * Thus any replacement of zero_l2_table with other valid L2 |
923 | * page table must involve FLPD cache invalidation for System | |
924 | * MMU v3.3. | |
925 | * FLPD cache invalidation is performed with TLB invalidation | |
926 | * by VPN without blocking. It is safe to invalidate TLB without | |
927 | * blocking because the target address of TLB invalidation is | |
928 | * not currently mapped. | |
929 | */ | |
930 | if (need_flush_flpd_cache) { | |
469acebe | 931 | struct sysmmu_drvdata *data; |
365409db | 932 | |
bfa00489 MS |
933 | spin_lock(&domain->lock); |
934 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 935 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 936 | spin_unlock(&domain->lock); |
66a7ed84 | 937 | } |
2a96536e KC |
938 | } |
939 | ||
940 | return page_entry(sent, iova); | |
941 | } | |
942 | ||
bfa00489 | 943 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 944 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
1a0d8dac | 945 | phys_addr_t paddr, int prot, short *pgcnt) |
2a96536e | 946 | { |
61128f08 | 947 | if (lv1ent_section(sent)) { |
d09d78fc | 948 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 949 | iova); |
2a96536e | 950 | return -EADDRINUSE; |
61128f08 | 951 | } |
2a96536e KC |
952 | |
953 | if (lv1ent_page(sent)) { | |
61128f08 | 954 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 955 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 956 | iova); |
2a96536e | 957 | return -EADDRINUSE; |
61128f08 | 958 | } |
2a96536e | 959 | |
734c3c73 | 960 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
961 | *pgcnt = 0; |
962 | } | |
963 | ||
1a0d8dac | 964 | update_pte(sent, mk_lv1ent_sect(paddr, prot)); |
2a96536e | 965 | |
bfa00489 | 966 | spin_lock(&domain->lock); |
66a7ed84 | 967 | if (lv1ent_page_zero(sent)) { |
469acebe | 968 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
969 | /* |
970 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
971 | * entry by speculative prefetch of SLPD which has no mapping. | |
972 | */ | |
bfa00489 | 973 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 974 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 975 | } |
bfa00489 | 976 | spin_unlock(&domain->lock); |
66a7ed84 | 977 | |
2a96536e KC |
978 | return 0; |
979 | } | |
980 | ||
d09d78fc | 981 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
1a0d8dac | 982 | int prot, short *pgcnt) |
2a96536e KC |
983 | { |
984 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 985 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
986 | return -EADDRINUSE; |
987 | ||
1a0d8dac | 988 | update_pte(pent, mk_lv2ent_spage(paddr, prot)); |
2a96536e KC |
989 | *pgcnt -= 1; |
990 | } else { /* size == LPAGE_SIZE */ | |
991 | int i; | |
5e3435eb | 992 | dma_addr_t pent_base = virt_to_phys(pent); |
365409db | 993 | |
5e3435eb MS |
994 | dma_sync_single_for_cpu(dma_dev, pent_base, |
995 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
996 | DMA_TO_DEVICE); | |
2a96536e | 997 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 998 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
999 | if (i > 0) |
1000 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
1001 | return -EADDRINUSE; |
1002 | } | |
1003 | ||
1a0d8dac | 1004 | *pent = mk_lv2ent_lpage(paddr, prot); |
2a96536e | 1005 | } |
5e3435eb MS |
1006 | dma_sync_single_for_device(dma_dev, pent_base, |
1007 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
1008 | DMA_TO_DEVICE); | |
2a96536e KC |
1009 | *pgcnt -= SPAGES_PER_LPAGE; |
1010 | } | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
66a7ed84 CK |
1015 | /* |
1016 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
1017 | * | |
f171abab | 1018 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 1019 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
1020 | * However, the logic has a bug that while caching faulty page table entries, |
1021 | * System MMU reports page fault if the cached fault entry is hit even though | |
1022 | * the fault entry is updated to a valid entry after the entry is cached. | |
1023 | * To prevent caching faulty page table entries which may be updated to valid | |
1024 | * entries later, the virtual memory manager should care about the workaround | |
1025 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
1026 | * |
1027 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 1028 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 1029 | * |
f171abab | 1030 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
1031 | * the following sizes for System MMU v3.1 and v3.2. |
1032 | * System MMU v3.1: 128KiB | |
1033 | * System MMU v3.2: 256KiB | |
1034 | * | |
1035 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
1036 | * more workarounds. |
1037 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
1038 | * than or equal to 128KiB. | |
66a7ed84 CK |
1039 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
1040 | */ | |
bfa00489 MS |
1041 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
1042 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
1043 | int prot) | |
2a96536e | 1044 | { |
bfa00489 | 1045 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1046 | sysmmu_pte_t *entry; |
1047 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
1048 | unsigned long flags; |
1049 | int ret = -ENOMEM; | |
1050 | ||
bfa00489 | 1051 | BUG_ON(domain->pgtable == NULL); |
1a0d8dac | 1052 | prot &= SYSMMU_SUPPORTED_PROT_BITS; |
2a96536e | 1053 | |
bfa00489 | 1054 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1055 | |
bfa00489 | 1056 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1057 | |
1058 | if (size == SECT_SIZE) { | |
1a0d8dac | 1059 | ret = lv1set_section(domain, entry, iova, paddr, prot, |
bfa00489 | 1060 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e | 1061 | } else { |
d09d78fc | 1062 | sysmmu_pte_t *pent; |
2a96536e | 1063 | |
bfa00489 MS |
1064 | pent = alloc_lv2entry(domain, entry, iova, |
1065 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 1066 | |
61128f08 CK |
1067 | if (IS_ERR(pent)) |
1068 | ret = PTR_ERR(pent); | |
2a96536e | 1069 | else |
1a0d8dac | 1070 | ret = lv2set_page(pent, paddr, size, prot, |
bfa00489 | 1071 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
1072 | } |
1073 | ||
61128f08 | 1074 | if (ret) |
0bf4e54d CK |
1075 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
1076 | __func__, ret, size, iova); | |
2a96536e | 1077 | |
bfa00489 | 1078 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1079 | |
1080 | return ret; | |
1081 | } | |
1082 | ||
bfa00489 MS |
1083 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
1084 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 1085 | { |
469acebe | 1086 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1087 | unsigned long flags; |
1088 | ||
bfa00489 | 1089 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 1090 | |
bfa00489 | 1091 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1092 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 1093 | |
bfa00489 | 1094 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
1095 | } |
1096 | ||
bfa00489 MS |
1097 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
1098 | unsigned long l_iova, size_t size) | |
2a96536e | 1099 | { |
bfa00489 | 1100 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1101 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
1102 | sysmmu_pte_t *ent; | |
61128f08 | 1103 | size_t err_pgsize; |
d09d78fc | 1104 | unsigned long flags; |
2a96536e | 1105 | |
bfa00489 | 1106 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 1107 | |
bfa00489 | 1108 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1109 | |
bfa00489 | 1110 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
1111 | |
1112 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1113 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1114 | err_pgsize = SECT_SIZE; |
1115 | goto err; | |
1116 | } | |
2a96536e | 1117 | |
f171abab | 1118 | /* workaround for h/w bug in System MMU v3.3 */ |
5e3435eb | 1119 | update_pte(ent, ZERO_LV2LINK); |
2a96536e KC |
1120 | size = SECT_SIZE; |
1121 | goto done; | |
1122 | } | |
1123 | ||
1124 | if (unlikely(lv1ent_fault(ent))) { | |
1125 | if (size > SECT_SIZE) | |
1126 | size = SECT_SIZE; | |
1127 | goto done; | |
1128 | } | |
1129 | ||
1130 | /* lv1ent_page(sent) == true here */ | |
1131 | ||
1132 | ent = page_entry(ent, iova); | |
1133 | ||
1134 | if (unlikely(lv2ent_fault(ent))) { | |
1135 | size = SPAGE_SIZE; | |
1136 | goto done; | |
1137 | } | |
1138 | ||
1139 | if (lv2ent_small(ent)) { | |
5e3435eb | 1140 | update_pte(ent, 0); |
2a96536e | 1141 | size = SPAGE_SIZE; |
bfa00489 | 1142 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1143 | goto done; |
1144 | } | |
1145 | ||
1146 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1147 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1148 | err_pgsize = LPAGE_SIZE; |
1149 | goto err; | |
1150 | } | |
2a96536e | 1151 | |
5e3435eb MS |
1152 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), |
1153 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1154 | DMA_TO_DEVICE); | |
2a96536e | 1155 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); |
5e3435eb MS |
1156 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), |
1157 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1158 | DMA_TO_DEVICE); | |
2a96536e | 1159 | size = LPAGE_SIZE; |
bfa00489 | 1160 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1161 | done: |
bfa00489 | 1162 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1163 | |
bfa00489 | 1164 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1165 | |
2a96536e | 1166 | return size; |
61128f08 | 1167 | err: |
bfa00489 | 1168 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1169 | |
0bf4e54d CK |
1170 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1171 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1172 | |
1173 | return 0; | |
2a96536e KC |
1174 | } |
1175 | ||
bfa00489 | 1176 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1177 | dma_addr_t iova) |
2a96536e | 1178 | { |
bfa00489 | 1179 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1180 | sysmmu_pte_t *entry; |
2a96536e KC |
1181 | unsigned long flags; |
1182 | phys_addr_t phys = 0; | |
1183 | ||
bfa00489 | 1184 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1185 | |
bfa00489 | 1186 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1187 | |
1188 | if (lv1ent_section(entry)) { | |
1189 | phys = section_phys(entry) + section_offs(iova); | |
1190 | } else if (lv1ent_page(entry)) { | |
1191 | entry = page_entry(entry, iova); | |
1192 | ||
1193 | if (lv2ent_large(entry)) | |
1194 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1195 | else if (lv2ent_small(entry)) | |
1196 | phys = spage_phys(entry) + spage_offs(iova); | |
1197 | } | |
1198 | ||
bfa00489 | 1199 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1200 | |
1201 | return phys; | |
1202 | } | |
1203 | ||
6c2ae7e2 MS |
1204 | static struct iommu_group *get_device_iommu_group(struct device *dev) |
1205 | { | |
1206 | struct iommu_group *group; | |
1207 | ||
1208 | group = iommu_group_get(dev); | |
1209 | if (!group) | |
1210 | group = iommu_group_alloc(); | |
1211 | ||
1212 | return group; | |
1213 | } | |
1214 | ||
bf4a1c92 AM |
1215 | static int exynos_iommu_add_device(struct device *dev) |
1216 | { | |
1217 | struct iommu_group *group; | |
bf4a1c92 | 1218 | |
06801db0 MS |
1219 | if (!has_sysmmu(dev)) |
1220 | return -ENODEV; | |
1221 | ||
6c2ae7e2 | 1222 | group = iommu_group_get_for_dev(dev); |
bf4a1c92 | 1223 | |
6c2ae7e2 MS |
1224 | if (IS_ERR(group)) |
1225 | return PTR_ERR(group); | |
bf4a1c92 | 1226 | |
bf4a1c92 AM |
1227 | iommu_group_put(group); |
1228 | ||
6c2ae7e2 | 1229 | return 0; |
bf4a1c92 AM |
1230 | } |
1231 | ||
1232 | static void exynos_iommu_remove_device(struct device *dev) | |
1233 | { | |
06801db0 MS |
1234 | if (!has_sysmmu(dev)) |
1235 | return; | |
1236 | ||
bf4a1c92 AM |
1237 | iommu_group_remove_device(dev); |
1238 | } | |
1239 | ||
aa759fd3 MS |
1240 | static int exynos_iommu_of_xlate(struct device *dev, |
1241 | struct of_phandle_args *spec) | |
1242 | { | |
1243 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
1244 | struct platform_device *sysmmu = of_find_device_by_node(spec->np); | |
1245 | struct sysmmu_drvdata *data; | |
1246 | ||
1247 | if (!sysmmu) | |
1248 | return -ENODEV; | |
1249 | ||
1250 | data = platform_get_drvdata(sysmmu); | |
1251 | if (!data) | |
1252 | return -ENODEV; | |
1253 | ||
1254 | if (!owner) { | |
1255 | owner = kzalloc(sizeof(*owner), GFP_KERNEL); | |
1256 | if (!owner) | |
1257 | return -ENOMEM; | |
1258 | ||
1259 | INIT_LIST_HEAD(&owner->controllers); | |
9b265536 | 1260 | mutex_init(&owner->rpm_lock); |
aa759fd3 MS |
1261 | dev->archdata.iommu = owner; |
1262 | } | |
1263 | ||
1264 | list_add_tail(&data->owner_node, &owner->controllers); | |
92798b45 | 1265 | data->master = dev; |
2f5f44f2 MS |
1266 | |
1267 | /* | |
1268 | * SYSMMU will be runtime activated via device link (dependency) to its | |
1269 | * master device, so there are no direct calls to pm_runtime_get/put | |
1270 | * in this driver. | |
1271 | */ | |
1272 | device_link_add(dev, data->sysmmu, DL_FLAG_PM_RUNTIME); | |
1273 | ||
aa759fd3 MS |
1274 | return 0; |
1275 | } | |
1276 | ||
8ed55c81 | 1277 | static struct iommu_ops exynos_iommu_ops = { |
e1fd1eaa JR |
1278 | .domain_alloc = exynos_iommu_domain_alloc, |
1279 | .domain_free = exynos_iommu_domain_free, | |
ba5fa6f6 BH |
1280 | .attach_dev = exynos_iommu_attach_device, |
1281 | .detach_dev = exynos_iommu_detach_device, | |
1282 | .map = exynos_iommu_map, | |
1283 | .unmap = exynos_iommu_unmap, | |
315786eb | 1284 | .map_sg = default_iommu_map_sg, |
ba5fa6f6 | 1285 | .iova_to_phys = exynos_iommu_iova_to_phys, |
6c2ae7e2 | 1286 | .device_group = get_device_iommu_group, |
ba5fa6f6 BH |
1287 | .add_device = exynos_iommu_add_device, |
1288 | .remove_device = exynos_iommu_remove_device, | |
2a96536e | 1289 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
aa759fd3 | 1290 | .of_xlate = exynos_iommu_of_xlate, |
2a96536e KC |
1291 | }; |
1292 | ||
8ed55c81 MS |
1293 | static bool init_done; |
1294 | ||
2a96536e KC |
1295 | static int __init exynos_iommu_init(void) |
1296 | { | |
1297 | int ret; | |
1298 | ||
734c3c73 CK |
1299 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1300 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1301 | if (!lv2table_kmem_cache) { | |
1302 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1303 | return -ENOMEM; | |
1304 | } | |
1305 | ||
2a96536e | 1306 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1307 | if (ret) { |
1308 | pr_err("%s: Failed to register driver\n", __func__); | |
1309 | goto err_reg_driver; | |
1310 | } | |
2a96536e | 1311 | |
66a7ed84 CK |
1312 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1313 | if (zero_lv2_table == NULL) { | |
1314 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1315 | __func__); | |
1316 | ret = -ENOMEM; | |
1317 | goto err_zero_lv2; | |
1318 | } | |
1319 | ||
734c3c73 CK |
1320 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1321 | if (ret) { | |
1322 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1323 | __func__); | |
1324 | goto err_set_iommu; | |
1325 | } | |
2a96536e | 1326 | |
8ed55c81 MS |
1327 | init_done = true; |
1328 | ||
734c3c73 CK |
1329 | return 0; |
1330 | err_set_iommu: | |
66a7ed84 CK |
1331 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
1332 | err_zero_lv2: | |
734c3c73 CK |
1333 | platform_driver_unregister(&exynos_sysmmu_driver); |
1334 | err_reg_driver: | |
1335 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1336 | return ret; |
1337 | } | |
8ed55c81 MS |
1338 | |
1339 | static int __init exynos_iommu_of_setup(struct device_node *np) | |
1340 | { | |
1341 | struct platform_device *pdev; | |
1342 | ||
1343 | if (!init_done) | |
1344 | exynos_iommu_init(); | |
1345 | ||
1346 | pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root); | |
423595e8 AKC |
1347 | if (!pdev) |
1348 | return -ENODEV; | |
8ed55c81 | 1349 | |
5e3435eb MS |
1350 | /* |
1351 | * use the first registered sysmmu device for performing | |
1352 | * dma mapping operations on iommu page tables (cpu cache flush) | |
1353 | */ | |
1354 | if (!dma_dev) | |
1355 | dma_dev = &pdev->dev; | |
1356 | ||
8ed55c81 MS |
1357 | return 0; |
1358 | } | |
1359 | ||
1360 | IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu", | |
1361 | exynos_iommu_of_setup); |