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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
740a01ee MS |
2 | /* |
3 | * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd. | |
2a96536e | 4 | * http://www.samsung.com |
2a96536e KC |
5 | */ |
6 | ||
7 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
8 | #define DEBUG | |
9 | #endif | |
10 | ||
2a96536e | 11 | #include <linux/clk.h> |
8ed55c81 | 12 | #include <linux/dma-mapping.h> |
2a96536e | 13 | #include <linux/err.h> |
312900c6 | 14 | #include <linux/io.h> |
2a96536e | 15 | #include <linux/iommu.h> |
312900c6 | 16 | #include <linux/interrupt.h> |
514c6032 | 17 | #include <linux/kmemleak.h> |
2a96536e | 18 | #include <linux/list.h> |
8ed55c81 | 19 | #include <linux/of.h> |
8ed55c81 | 20 | #include <linux/of_platform.h> |
312900c6 MS |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pm_runtime.h> | |
23 | #include <linux/slab.h> | |
2a96536e | 24 | |
d09d78fc CK |
25 | typedef u32 sysmmu_iova_t; |
26 | typedef u32 sysmmu_pte_t; | |
b3d14960 | 27 | static struct iommu_domain exynos_identity_domain; |
d09d78fc | 28 | |
f171abab | 29 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
30 | #define SECT_ORDER 20 |
31 | #define LPAGE_ORDER 16 | |
32 | #define SPAGE_ORDER 12 | |
33 | ||
34 | #define SECT_SIZE (1 << SECT_ORDER) | |
35 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
36 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
37 | ||
38 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
39 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
40 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
41 | ||
66a7ed84 CK |
42 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
43 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
44 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
45 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
46 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
47 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
48 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
49 | ||
50 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
51 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
52 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
53 | ||
740a01ee MS |
54 | /* |
55 | * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces | |
56 | * v5.0 introduced support for 36bit physical address space by shifting | |
57 | * all page entry values by 4 bits. | |
58 | * All SYSMMU controllers in the system support the address spaces of the same | |
59 | * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper | |
60 | * value (0 or 4). | |
61 | */ | |
62 | static short PG_ENT_SHIFT = -1; | |
63 | #define SYSMMU_PG_ENT_SHIFT 0 | |
64 | #define SYSMMU_V5_PG_ENT_SHIFT 4 | |
65 | ||
1a0d8dac MS |
66 | static const sysmmu_pte_t *LV1_PROT; |
67 | static const sysmmu_pte_t SYSMMU_LV1_PROT[] = { | |
68 | ((0 << 15) | (0 << 10)), /* no access */ | |
69 | ((1 << 15) | (1 << 10)), /* IOMMU_READ only */ | |
70 | ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */ | |
71 | ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */ | |
72 | }; | |
73 | static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = { | |
74 | (0 << 4), /* no access */ | |
75 | (1 << 4), /* IOMMU_READ only */ | |
76 | (2 << 4), /* IOMMU_WRITE only */ | |
77 | (3 << 4), /* IOMMU_READ | IOMMU_WRITE */ | |
78 | }; | |
79 | ||
80 | static const sysmmu_pte_t *LV2_PROT; | |
81 | static const sysmmu_pte_t SYSMMU_LV2_PROT[] = { | |
82 | ((0 << 9) | (0 << 4)), /* no access */ | |
83 | ((1 << 9) | (1 << 4)), /* IOMMU_READ only */ | |
84 | ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */ | |
85 | ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */ | |
86 | }; | |
87 | static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = { | |
88 | (0 << 2), /* no access */ | |
89 | (1 << 2), /* IOMMU_READ only */ | |
90 | (2 << 2), /* IOMMU_WRITE only */ | |
91 | (3 << 2), /* IOMMU_READ | IOMMU_WRITE */ | |
92 | }; | |
93 | ||
94 | #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE) | |
95 | ||
740a01ee MS |
96 | #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT) |
97 | #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK) | |
98 | #define section_offs(iova) (iova & (SECT_SIZE - 1)) | |
99 | #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK) | |
100 | #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1)) | |
101 | #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK) | |
102 | #define spage_offs(iova) (iova & (SPAGE_SIZE - 1)) | |
2a96536e KC |
103 | |
104 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 105 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 106 | |
d09d78fc CK |
107 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
108 | { | |
109 | return iova >> SECT_ORDER; | |
110 | } | |
111 | ||
112 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
113 | { | |
114 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
115 | } | |
116 | ||
5e3435eb | 117 | #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) |
d09d78fc | 118 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) |
2a96536e KC |
119 | |
120 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
740a01ee | 121 | #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0)) |
2a96536e | 122 | |
1a0d8dac | 123 | #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2) |
740a01ee | 124 | #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1) |
1a0d8dac MS |
125 | #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1) |
126 | #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2) | |
2a96536e KC |
127 | |
128 | #define CTRL_ENABLE 0x5 | |
129 | #define CTRL_BLOCK 0x7 | |
130 | #define CTRL_DISABLE 0x0 | |
131 | ||
eeb5184b | 132 | #define CFG_LRU 0x1 |
1a0d8dac | 133 | #define CFG_EAP (1 << 2) |
eeb5184b | 134 | #define CFG_QOS(n) ((n & 0xF) << 7) |
eeb5184b CK |
135 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ |
136 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
137 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
138 | ||
7fee5d6f SP |
139 | #define CTRL_VM_ENABLE BIT(0) |
140 | #define CTRL_VM_FAULT_MODE_STALL BIT(3) | |
0892c498 SP |
141 | #define CAPA0_CAPA1_EXIST BIT(11) |
142 | #define CAPA1_VCR_ENABLED BIT(14) | |
143 | ||
740a01ee | 144 | /* common registers */ |
2a96536e KC |
145 | #define REG_MMU_CTRL 0x000 |
146 | #define REG_MMU_CFG 0x004 | |
147 | #define REG_MMU_STATUS 0x008 | |
740a01ee MS |
148 | #define REG_MMU_VERSION 0x034 |
149 | ||
150 | #define MMU_MAJ_VER(val) ((val) >> 7) | |
151 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
152 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
153 | ||
154 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
155 | ||
156 | /* v1.x - v3.x registers */ | |
2a96536e KC |
157 | #define REG_PAGE_FAULT_ADDR 0x024 |
158 | #define REG_AW_FAULT_ADDR 0x028 | |
159 | #define REG_AR_FAULT_ADDR 0x02C | |
160 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
161 | ||
740a01ee | 162 | /* v5.x registers */ |
740a01ee MS |
163 | #define REG_V5_FAULT_AR_VA 0x070 |
164 | #define REG_V5_FAULT_AW_VA 0x080 | |
2a96536e | 165 | |
0892c498 SP |
166 | /* v7.x registers */ |
167 | #define REG_V7_CAPA0 0x870 | |
168 | #define REG_V7_CAPA1 0x874 | |
7fee5d6f | 169 | #define REG_V7_CTRL_VM 0x8000 |
0892c498 | 170 | |
0f45b04d | 171 | #define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) |
6b21a5db | 172 | |
5e3435eb | 173 | static struct device *dma_dev; |
734c3c73 | 174 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
175 | static sysmmu_pte_t *zero_lv2_table; |
176 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 177 | |
d09d78fc | 178 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
179 | { |
180 | return pgtable + lv1ent_offset(iova); | |
181 | } | |
182 | ||
d09d78fc | 183 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 184 | { |
d09d78fc | 185 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 186 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
187 | } |
188 | ||
c64074bf SP |
189 | struct sysmmu_fault { |
190 | sysmmu_iova_t addr; /* IOVA address that caused fault */ | |
191 | const char *name; /* human readable fault name */ | |
192 | unsigned int type; /* fault type for report_iommu_fault() */ | |
193 | }; | |
194 | ||
195 | struct sysmmu_v1_fault_info { | |
196 | unsigned short addr_reg; /* register to read IOVA fault address */ | |
d093fc7e MS |
197 | const char *name; /* human readable fault name */ |
198 | unsigned int type; /* fault type for report_iommu_fault */ | |
2a96536e KC |
199 | }; |
200 | ||
c64074bf SP |
201 | static const struct sysmmu_v1_fault_info sysmmu_v1_faults[] = { |
202 | { REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ }, | |
203 | { REG_AR_FAULT_ADDR, "MULTI-HIT", IOMMU_FAULT_READ }, | |
204 | { REG_AW_FAULT_ADDR, "MULTI-HIT", IOMMU_FAULT_WRITE }, | |
205 | { REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ }, | |
206 | { REG_AR_FAULT_ADDR, "SECURITY PROTECTION", IOMMU_FAULT_READ }, | |
207 | { REG_AR_FAULT_ADDR, "ACCESS PROTECTION", IOMMU_FAULT_READ }, | |
208 | { REG_AW_FAULT_ADDR, "SECURITY PROTECTION", IOMMU_FAULT_WRITE }, | |
209 | { REG_AW_FAULT_ADDR, "ACCESS PROTECTION", IOMMU_FAULT_WRITE }, | |
2a96536e KC |
210 | }; |
211 | ||
c64074bf SP |
212 | /* SysMMU v5 has the same faults for AR (0..4 bits) and AW (16..20 bits) */ |
213 | static const char * const sysmmu_v5_fault_names[] = { | |
214 | "PTW", | |
215 | "PAGE", | |
216 | "MULTI-HIT", | |
217 | "ACCESS PROTECTION", | |
218 | "SECURITY PROTECTION" | |
2a96536e KC |
219 | }; |
220 | ||
2f599c3f SP |
221 | static const char * const sysmmu_v7_fault_names[] = { |
222 | "PTW", | |
223 | "PAGE", | |
224 | "ACCESS PROTECTION", | |
225 | "RESERVED" | |
740a01ee MS |
226 | }; |
227 | ||
2860af3c | 228 | /* |
0f45b04d | 229 | * This structure is attached to dev->iommu->priv of the master device |
2860af3c MS |
230 | * on device add, contains a list of SYSMMU controllers defined by device tree, |
231 | * which are bound to given master device. It is usually referenced by 'owner' | |
232 | * pointer. | |
233 | */ | |
6b21a5db | 234 | struct exynos_iommu_owner { |
1b092054 | 235 | struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ |
5fa61cbf | 236 | struct iommu_domain *domain; /* domain this device is attached */ |
9b265536 | 237 | struct mutex rpm_lock; /* for runtime pm of all sysmmus */ |
6b21a5db CK |
238 | }; |
239 | ||
2860af3c MS |
240 | /* |
241 | * This structure exynos specific generalization of struct iommu_domain. | |
242 | * It contains list of SYSMMU controllers from all master devices, which has | |
243 | * been attached to this domain and page tables of IO address space defined by | |
244 | * it. It is usually referenced by 'domain' pointer. | |
245 | */ | |
2a96536e | 246 | struct exynos_iommu_domain { |
2860af3c MS |
247 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
248 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
249 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
250 | spinlock_t lock; /* lock for modyfying list of clients */ | |
251 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 252 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
253 | }; |
254 | ||
c64074bf SP |
255 | struct sysmmu_drvdata; |
256 | ||
2125afbe SP |
257 | /* |
258 | * SysMMU version specific data. Contains offsets for the registers which can | |
259 | * be found in different SysMMU variants, but have different offset values. | |
c64074bf | 260 | * Also contains version specific callbacks to abstract the hardware. |
2125afbe SP |
261 | */ |
262 | struct sysmmu_variant { | |
263 | u32 pt_base; /* page table base address (physical) */ | |
264 | u32 flush_all; /* invalidate all TLB entries */ | |
265 | u32 flush_entry; /* invalidate specific TLB entry */ | |
266 | u32 flush_range; /* invalidate TLB entries in specified range */ | |
267 | u32 flush_start; /* start address of range invalidation */ | |
268 | u32 flush_end; /* end address of range invalidation */ | |
269 | u32 int_status; /* interrupt status information */ | |
270 | u32 int_clear; /* clear the interrupt */ | |
2f599c3f SP |
271 | u32 fault_va; /* IOVA address that caused fault */ |
272 | u32 fault_info; /* fault transaction info */ | |
c64074bf SP |
273 | |
274 | int (*get_fault_info)(struct sysmmu_drvdata *data, unsigned int itype, | |
275 | struct sysmmu_fault *fault); | |
2125afbe SP |
276 | }; |
277 | ||
2860af3c MS |
278 | /* |
279 | * This structure hold all data of a single SYSMMU controller, this includes | |
280 | * hw resources like registers and clocks, pointers and list nodes to connect | |
281 | * it to all other structures, internal state and parameters read from device | |
282 | * tree. It is usually referenced by 'data' pointer. | |
283 | */ | |
2a96536e | 284 | struct sysmmu_drvdata { |
2860af3c MS |
285 | struct device *sysmmu; /* SYSMMU controller device */ |
286 | struct device *master; /* master device (owner) */ | |
7a974b29 | 287 | struct device_link *link; /* runtime PM link to master */ |
2860af3c MS |
288 | void __iomem *sfrbase; /* our registers */ |
289 | struct clk *clk; /* SYSMMU's clock */ | |
740a01ee MS |
290 | struct clk *aclk; /* SYSMMU's aclk clock */ |
291 | struct clk *pclk; /* SYSMMU's pclk clock */ | |
2860af3c | 292 | struct clk *clk_master; /* master's device clock */ |
2860af3c | 293 | spinlock_t lock; /* lock for modyfying state */ |
47a574ff | 294 | bool active; /* current status */ |
2860af3c MS |
295 | struct exynos_iommu_domain *domain; /* domain we belong to */ |
296 | struct list_head domain_node; /* node for domain clients list */ | |
1b092054 | 297 | struct list_head owner_node; /* node for owner controllers list */ |
2860af3c MS |
298 | phys_addr_t pgtable; /* assigned page table structure */ |
299 | unsigned int version; /* our version */ | |
d2c302b6 JR |
300 | |
301 | struct iommu_device iommu; /* IOMMU core handle */ | |
2125afbe | 302 | const struct sysmmu_variant *variant; /* version specific data */ |
0892c498 SP |
303 | |
304 | /* v7 fields */ | |
305 | bool has_vcr; /* virtual machine control register */ | |
2125afbe SP |
306 | }; |
307 | ||
308 | #define SYSMMU_REG(data, reg) ((data)->sfrbase + (data)->variant->reg) | |
309 | ||
c64074bf SP |
310 | static int exynos_sysmmu_v1_get_fault_info(struct sysmmu_drvdata *data, |
311 | unsigned int itype, | |
312 | struct sysmmu_fault *fault) | |
313 | { | |
314 | const struct sysmmu_v1_fault_info *finfo; | |
315 | ||
316 | if (itype >= ARRAY_SIZE(sysmmu_v1_faults)) | |
317 | return -ENXIO; | |
318 | ||
319 | finfo = &sysmmu_v1_faults[itype]; | |
320 | fault->addr = readl(data->sfrbase + finfo->addr_reg); | |
321 | fault->name = finfo->name; | |
322 | fault->type = finfo->type; | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int exynos_sysmmu_v5_get_fault_info(struct sysmmu_drvdata *data, | |
328 | unsigned int itype, | |
329 | struct sysmmu_fault *fault) | |
330 | { | |
331 | unsigned int addr_reg; | |
332 | ||
333 | if (itype < ARRAY_SIZE(sysmmu_v5_fault_names)) { | |
334 | fault->type = IOMMU_FAULT_READ; | |
335 | addr_reg = REG_V5_FAULT_AR_VA; | |
336 | } else if (itype >= 16 && itype <= 20) { | |
337 | fault->type = IOMMU_FAULT_WRITE; | |
338 | addr_reg = REG_V5_FAULT_AW_VA; | |
339 | itype -= 16; | |
340 | } else { | |
341 | return -ENXIO; | |
342 | } | |
343 | ||
344 | fault->name = sysmmu_v5_fault_names[itype]; | |
345 | fault->addr = readl(data->sfrbase + addr_reg); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
2f599c3f SP |
350 | static int exynos_sysmmu_v7_get_fault_info(struct sysmmu_drvdata *data, |
351 | unsigned int itype, | |
352 | struct sysmmu_fault *fault) | |
353 | { | |
354 | u32 info = readl(SYSMMU_REG(data, fault_info)); | |
355 | ||
356 | fault->addr = readl(SYSMMU_REG(data, fault_va)); | |
357 | fault->name = sysmmu_v7_fault_names[itype % 4]; | |
358 | fault->type = (info & BIT(20)) ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
2125afbe SP |
363 | /* SysMMU v1..v3 */ |
364 | static const struct sysmmu_variant sysmmu_v1_variant = { | |
365 | .flush_all = 0x0c, | |
366 | .flush_entry = 0x10, | |
367 | .pt_base = 0x14, | |
368 | .int_status = 0x18, | |
369 | .int_clear = 0x1c, | |
c64074bf SP |
370 | |
371 | .get_fault_info = exynos_sysmmu_v1_get_fault_info, | |
2125afbe SP |
372 | }; |
373 | ||
2f599c3f | 374 | /* SysMMU v5 */ |
2125afbe SP |
375 | static const struct sysmmu_variant sysmmu_v5_variant = { |
376 | .pt_base = 0x0c, | |
377 | .flush_all = 0x10, | |
378 | .flush_entry = 0x14, | |
379 | .flush_range = 0x18, | |
380 | .flush_start = 0x20, | |
381 | .flush_end = 0x24, | |
382 | .int_status = 0x60, | |
383 | .int_clear = 0x64, | |
c64074bf SP |
384 | |
385 | .get_fault_info = exynos_sysmmu_v5_get_fault_info, | |
2a96536e KC |
386 | }; |
387 | ||
2f599c3f SP |
388 | /* SysMMU v7: non-VM capable register layout */ |
389 | static const struct sysmmu_variant sysmmu_v7_variant = { | |
390 | .pt_base = 0x0c, | |
391 | .flush_all = 0x10, | |
392 | .flush_entry = 0x14, | |
393 | .flush_range = 0x18, | |
394 | .flush_start = 0x20, | |
395 | .flush_end = 0x24, | |
396 | .int_status = 0x60, | |
397 | .int_clear = 0x64, | |
398 | .fault_va = 0x70, | |
399 | .fault_info = 0x78, | |
400 | ||
401 | .get_fault_info = exynos_sysmmu_v7_get_fault_info, | |
402 | }; | |
403 | ||
404 | /* SysMMU v7: VM capable register layout */ | |
0892c498 SP |
405 | static const struct sysmmu_variant sysmmu_v7_vm_variant = { |
406 | .pt_base = 0x800c, | |
407 | .flush_all = 0x8010, | |
408 | .flush_entry = 0x8014, | |
409 | .flush_range = 0x8018, | |
410 | .flush_start = 0x8020, | |
411 | .flush_end = 0x8024, | |
412 | .int_status = 0x60, | |
413 | .int_clear = 0x64, | |
2f599c3f SP |
414 | .fault_va = 0x1000, |
415 | .fault_info = 0x1004, | |
c64074bf | 416 | |
2f599c3f | 417 | .get_fault_info = exynos_sysmmu_v7_get_fault_info, |
2a96536e KC |
418 | }; |
419 | ||
e1fd1eaa JR |
420 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
421 | { | |
422 | return container_of(dom, struct exynos_iommu_domain, domain); | |
423 | } | |
424 | ||
02cdc365 | 425 | static void sysmmu_unblock(struct sysmmu_drvdata *data) |
2a96536e | 426 | { |
84bd0428 | 427 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e KC |
428 | } |
429 | ||
02cdc365 | 430 | static bool sysmmu_block(struct sysmmu_drvdata *data) |
2a96536e KC |
431 | { |
432 | int i = 120; | |
433 | ||
84bd0428 MS |
434 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
435 | while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1)) | |
2a96536e KC |
436 | --i; |
437 | ||
84bd0428 | 438 | if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) { |
02cdc365 | 439 | sysmmu_unblock(data); |
2a96536e KC |
440 | return false; |
441 | } | |
442 | ||
443 | return true; | |
444 | } | |
445 | ||
02cdc365 | 446 | static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) |
2a96536e | 447 | { |
2125afbe | 448 | writel(0x1, SYSMMU_REG(data, flush_all)); |
2a96536e KC |
449 | } |
450 | ||
02cdc365 | 451 | static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
d09d78fc | 452 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 453 | { |
3ad6b7f3 | 454 | unsigned int i; |
365409db | 455 | |
2125afbe | 456 | if (MMU_MAJ_VER(data->version) < 5 || num_inv == 1) { |
d5bf739d | 457 | for (i = 0; i < num_inv; i++) { |
84bd0428 | 458 | writel((iova & SPAGE_MASK) | 1, |
2125afbe | 459 | SYSMMU_REG(data, flush_entry)); |
d5bf739d MS |
460 | iova += SPAGE_SIZE; |
461 | } | |
462 | } else { | |
2125afbe SP |
463 | writel(iova & SPAGE_MASK, SYSMMU_REG(data, flush_start)); |
464 | writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, | |
465 | SYSMMU_REG(data, flush_end)); | |
466 | writel(0x1, SYSMMU_REG(data, flush_range)); | |
3ad6b7f3 | 467 | } |
2a96536e KC |
468 | } |
469 | ||
02cdc365 | 470 | static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) |
2a96536e | 471 | { |
2125afbe SP |
472 | u32 pt_base; |
473 | ||
740a01ee | 474 | if (MMU_MAJ_VER(data->version) < 5) |
2125afbe | 475 | pt_base = pgd; |
740a01ee | 476 | else |
2125afbe | 477 | pt_base = pgd >> SPAGE_ORDER; |
2a96536e | 478 | |
2125afbe | 479 | writel(pt_base, SYSMMU_REG(data, pt_base)); |
02cdc365 | 480 | __sysmmu_tlb_invalidate(data); |
2a96536e KC |
481 | } |
482 | ||
fecc49db MS |
483 | static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data) |
484 | { | |
485 | BUG_ON(clk_prepare_enable(data->clk_master)); | |
486 | BUG_ON(clk_prepare_enable(data->clk)); | |
487 | BUG_ON(clk_prepare_enable(data->pclk)); | |
488 | BUG_ON(clk_prepare_enable(data->aclk)); | |
489 | } | |
490 | ||
491 | static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data) | |
492 | { | |
493 | clk_disable_unprepare(data->aclk); | |
494 | clk_disable_unprepare(data->pclk); | |
495 | clk_disable_unprepare(data->clk); | |
496 | clk_disable_unprepare(data->clk_master); | |
497 | } | |
498 | ||
0892c498 SP |
499 | static bool __sysmmu_has_capa1(struct sysmmu_drvdata *data) |
500 | { | |
501 | u32 capa0 = readl(data->sfrbase + REG_V7_CAPA0); | |
502 | ||
503 | return capa0 & CAPA0_CAPA1_EXIST; | |
504 | } | |
505 | ||
506 | static void __sysmmu_get_vcr(struct sysmmu_drvdata *data) | |
507 | { | |
508 | u32 capa1 = readl(data->sfrbase + REG_V7_CAPA1); | |
509 | ||
510 | data->has_vcr = capa1 & CAPA1_VCR_ENABLED; | |
511 | } | |
512 | ||
850d313e MS |
513 | static void __sysmmu_get_version(struct sysmmu_drvdata *data) |
514 | { | |
515 | u32 ver; | |
516 | ||
fecc49db | 517 | __sysmmu_enable_clocks(data); |
850d313e | 518 | |
84bd0428 | 519 | ver = readl(data->sfrbase + REG_MMU_VERSION); |
850d313e MS |
520 | |
521 | /* controllers on some SoCs don't report proper version */ | |
522 | if (ver == 0x80000001u) | |
523 | data->version = MAKE_MMU_VER(1, 0); | |
524 | else | |
525 | data->version = MMU_RAW_VER(ver); | |
526 | ||
527 | dev_dbg(data->sysmmu, "hardware version: %d.%d\n", | |
528 | MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); | |
529 | ||
0892c498 | 530 | if (MMU_MAJ_VER(data->version) < 5) { |
2125afbe | 531 | data->variant = &sysmmu_v1_variant; |
0892c498 | 532 | } else if (MMU_MAJ_VER(data->version) < 7) { |
2125afbe | 533 | data->variant = &sysmmu_v5_variant; |
0892c498 SP |
534 | } else { |
535 | if (__sysmmu_has_capa1(data)) | |
536 | __sysmmu_get_vcr(data); | |
537 | if (data->has_vcr) | |
538 | data->variant = &sysmmu_v7_vm_variant; | |
539 | else | |
2f599c3f | 540 | data->variant = &sysmmu_v7_variant; |
0892c498 | 541 | } |
2125afbe | 542 | |
fecc49db | 543 | __sysmmu_disable_clocks(data); |
850d313e MS |
544 | } |
545 | ||
d093fc7e | 546 | static void show_fault_information(struct sysmmu_drvdata *data, |
c64074bf | 547 | const struct sysmmu_fault *fault) |
2a96536e | 548 | { |
d09d78fc | 549 | sysmmu_pte_t *ent; |
2a96536e | 550 | |
c64074bf SP |
551 | dev_err(data->sysmmu, "%s: [%s] %s FAULT occurred at %#x\n", |
552 | dev_name(data->master), | |
553 | fault->type == IOMMU_FAULT_READ ? "READ" : "WRITE", | |
554 | fault->name, fault->addr); | |
ec5d241b | 555 | dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable); |
c64074bf | 556 | ent = section_entry(phys_to_virt(data->pgtable), fault->addr); |
ec5d241b | 557 | dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent); |
2a96536e | 558 | if (lv1ent_page(ent)) { |
c64074bf | 559 | ent = page_entry(ent, fault->addr); |
ec5d241b | 560 | dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent); |
2a96536e | 561 | } |
2a96536e KC |
562 | } |
563 | ||
564 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
565 | { | |
2a96536e | 566 | struct sysmmu_drvdata *data = dev_id; |
c64074bf SP |
567 | unsigned int itype; |
568 | struct sysmmu_fault fault; | |
7222e8db | 569 | int ret = -ENOSYS; |
2a96536e | 570 | |
47a574ff | 571 | WARN_ON(!data->active); |
2a96536e | 572 | |
9d4e7a24 | 573 | spin_lock(&data->lock); |
b398af21 | 574 | clk_enable(data->clk_master); |
9d4e7a24 | 575 | |
2125afbe | 576 | itype = __ffs(readl(SYSMMU_REG(data, int_status))); |
c64074bf SP |
577 | ret = data->variant->get_fault_info(data, itype, &fault); |
578 | if (ret) { | |
579 | dev_err(data->sysmmu, "Unhandled interrupt bit %u\n", itype); | |
580 | goto out; | |
581 | } | |
582 | show_fault_information(data, &fault); | |
2a96536e | 583 | |
c64074bf SP |
584 | if (data->domain) { |
585 | ret = report_iommu_fault(&data->domain->domain, data->master, | |
586 | fault.addr, fault.type); | |
587 | } | |
588 | if (ret) | |
589 | panic("Unrecoverable System MMU Fault!"); | |
590 | ||
591 | out: | |
2125afbe | 592 | writel(1 << itype, SYSMMU_REG(data, int_clear)); |
1fab7fa7 | 593 | |
c64074bf | 594 | /* SysMMU is in blocked state when interrupt occurred */ |
02cdc365 | 595 | sysmmu_unblock(data); |
b398af21 | 596 | clk_disable(data->clk_master); |
9d4e7a24 | 597 | spin_unlock(&data->lock); |
2a96536e KC |
598 | |
599 | return IRQ_HANDLED; | |
600 | } | |
601 | ||
47a574ff | 602 | static void __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 603 | { |
47a574ff MS |
604 | unsigned long flags; |
605 | ||
b398af21 | 606 | clk_enable(data->clk_master); |
70605870 | 607 | |
47a574ff | 608 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 MS |
609 | writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
610 | writel(0, data->sfrbase + REG_MMU_CFG); | |
47a574ff | 611 | data->active = false; |
6b21a5db CK |
612 | spin_unlock_irqrestore(&data->lock, flags); |
613 | ||
47a574ff | 614 | __sysmmu_disable_clocks(data); |
6b21a5db | 615 | } |
2a96536e | 616 | |
6b21a5db CK |
617 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
618 | { | |
83addecd MS |
619 | unsigned int cfg; |
620 | ||
83addecd MS |
621 | if (data->version <= MAKE_MMU_VER(3, 1)) |
622 | cfg = CFG_LRU | CFG_QOS(15); | |
623 | else if (data->version <= MAKE_MMU_VER(3, 2)) | |
624 | cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL; | |
625 | else | |
626 | cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN; | |
6b21a5db | 627 | |
1a0d8dac MS |
628 | cfg |= CFG_EAP; /* enable access protection bits check */ |
629 | ||
84bd0428 | 630 | writel(cfg, data->sfrbase + REG_MMU_CFG); |
6b21a5db CK |
631 | } |
632 | ||
7fee5d6f SP |
633 | static void __sysmmu_enable_vid(struct sysmmu_drvdata *data) |
634 | { | |
635 | u32 ctrl; | |
636 | ||
637 | if (MMU_MAJ_VER(data->version) < 7 || !data->has_vcr) | |
638 | return; | |
639 | ||
640 | ctrl = readl(data->sfrbase + REG_V7_CTRL_VM); | |
641 | ctrl |= CTRL_VM_ENABLE | CTRL_VM_FAULT_MODE_STALL; | |
642 | writel(ctrl, data->sfrbase + REG_V7_CTRL_VM); | |
643 | } | |
644 | ||
47a574ff | 645 | static void __sysmmu_enable(struct sysmmu_drvdata *data) |
6b21a5db | 646 | { |
47a574ff MS |
647 | unsigned long flags; |
648 | ||
fecc49db | 649 | __sysmmu_enable_clocks(data); |
70605870 | 650 | |
47a574ff | 651 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 | 652 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 653 | __sysmmu_init_config(data); |
02cdc365 | 654 | __sysmmu_set_ptbase(data, data->pgtable); |
7fee5d6f | 655 | __sysmmu_enable_vid(data); |
84bd0428 | 656 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
47a574ff MS |
657 | data->active = true; |
658 | spin_unlock_irqrestore(&data->lock, flags); | |
7222e8db | 659 | |
fecc49db MS |
660 | /* |
661 | * SYSMMU driver keeps master's clock enabled only for the short | |
662 | * time, while accessing the registers. For performing address | |
663 | * translation during DMA transaction it relies on the client | |
664 | * driver to enable it. | |
665 | */ | |
b398af21 | 666 | clk_disable(data->clk_master); |
6b21a5db | 667 | } |
70605870 | 668 | |
469acebe | 669 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
670 | sysmmu_iova_t iova) |
671 | { | |
672 | unsigned long flags; | |
66a7ed84 | 673 | |
66a7ed84 | 674 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 675 | if (data->active && data->version >= MAKE_MMU_VER(3, 3)) { |
01324ab2 | 676 | clk_enable(data->clk_master); |
7d2aa6b8 | 677 | if (sysmmu_block(data)) { |
cd37a296 MS |
678 | if (data->version >= MAKE_MMU_VER(5, 0)) |
679 | __sysmmu_tlb_invalidate(data); | |
680 | else | |
681 | __sysmmu_tlb_invalidate_entry(data, iova, 1); | |
7d2aa6b8 MS |
682 | sysmmu_unblock(data); |
683 | } | |
01324ab2 | 684 | clk_disable(data->clk_master); |
d631ea98 | 685 | } |
66a7ed84 | 686 | spin_unlock_irqrestore(&data->lock, flags); |
66a7ed84 CK |
687 | } |
688 | ||
469acebe MS |
689 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
690 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
691 | { |
692 | unsigned long flags; | |
2a96536e | 693 | |
6b21a5db | 694 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 695 | if (data->active) { |
3ad6b7f3 | 696 | unsigned int num_inv = 1; |
70605870 | 697 | |
b398af21 | 698 | clk_enable(data->clk_master); |
70605870 | 699 | |
3ad6b7f3 CK |
700 | /* |
701 | * L2TLB invalidation required | |
702 | * 4KB page: 1 invalidation | |
f171abab SK |
703 | * 64KB page: 16 invalidations |
704 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
705 | * because it is set-associative TLB |
706 | * with 8-way and 64 sets. | |
707 | * 1MB page can be cached in one of all sets. | |
708 | * 64KB page can be one of 16 consecutive sets. | |
709 | */ | |
512bd0c6 | 710 | if (MMU_MAJ_VER(data->version) == 2) |
bc0d9af2 | 711 | num_inv = min_t(unsigned int, size / SPAGE_SIZE, 64); |
3ad6b7f3 | 712 | |
02cdc365 MS |
713 | if (sysmmu_block(data)) { |
714 | __sysmmu_tlb_invalidate_entry(data, iova, num_inv); | |
715 | sysmmu_unblock(data); | |
2a96536e | 716 | } |
b398af21 | 717 | clk_disable(data->clk_master); |
2a96536e | 718 | } |
9d4e7a24 | 719 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
720 | } |
721 | ||
0b9a3694 | 722 | static const struct iommu_ops exynos_iommu_ops; |
96f66557 | 723 | |
7991eb39 | 724 | static int exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 725 | { |
46c16d1e | 726 | int irq, ret; |
7222e8db | 727 | struct device *dev = &pdev->dev; |
2a96536e | 728 | struct sysmmu_drvdata *data; |
7222e8db | 729 | struct resource *res; |
2a96536e | 730 | |
46c16d1e CK |
731 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
732 | if (!data) | |
733 | return -ENOMEM; | |
2a96536e | 734 | |
7222e8db | 735 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
736 | data->sfrbase = devm_ioremap_resource(dev, res); |
737 | if (IS_ERR(data->sfrbase)) | |
738 | return PTR_ERR(data->sfrbase); | |
2a96536e | 739 | |
46c16d1e | 740 | irq = platform_get_irq(pdev, 0); |
086f9efa | 741 | if (irq <= 0) |
46c16d1e | 742 | return irq; |
2a96536e | 743 | |
46c16d1e | 744 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
745 | dev_name(dev), data); |
746 | if (ret) { | |
46c16d1e CK |
747 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
748 | return ret; | |
2a96536e KC |
749 | } |
750 | ||
5e799a7c CJ |
751 | data->clk = devm_clk_get_optional(dev, "sysmmu"); |
752 | if (IS_ERR(data->clk)) | |
0c2b063f | 753 | return PTR_ERR(data->clk); |
740a01ee | 754 | |
5e799a7c CJ |
755 | data->aclk = devm_clk_get_optional(dev, "aclk"); |
756 | if (IS_ERR(data->aclk)) | |
0c2b063f | 757 | return PTR_ERR(data->aclk); |
740a01ee | 758 | |
5e799a7c CJ |
759 | data->pclk = devm_clk_get_optional(dev, "pclk"); |
760 | if (IS_ERR(data->pclk)) | |
0c2b063f | 761 | return PTR_ERR(data->pclk); |
740a01ee MS |
762 | |
763 | if (!data->clk && (!data->aclk || !data->pclk)) { | |
764 | dev_err(dev, "Failed to get device clock(s)!\n"); | |
765 | return -ENOSYS; | |
2a96536e KC |
766 | } |
767 | ||
5e799a7c CJ |
768 | data->clk_master = devm_clk_get_optional(dev, "master"); |
769 | if (IS_ERR(data->clk_master)) | |
0c2b063f | 770 | return PTR_ERR(data->clk_master); |
70605870 | 771 | |
2a96536e | 772 | data->sysmmu = dev; |
9d4e7a24 | 773 | spin_lock_init(&data->lock); |
2a96536e | 774 | |
2125afbe SP |
775 | __sysmmu_get_version(data); |
776 | ||
d2c302b6 JR |
777 | ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, |
778 | dev_name(data->sysmmu)); | |
779 | if (ret) | |
780 | return ret; | |
781 | ||
7222e8db CK |
782 | platform_set_drvdata(pdev, data); |
783 | ||
740a01ee | 784 | if (PG_ENT_SHIFT < 0) { |
1a0d8dac | 785 | if (MMU_MAJ_VER(data->version) < 5) { |
740a01ee | 786 | PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; |
1a0d8dac MS |
787 | LV1_PROT = SYSMMU_LV1_PROT; |
788 | LV2_PROT = SYSMMU_LV2_PROT; | |
789 | } else { | |
740a01ee | 790 | PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT; |
1a0d8dac MS |
791 | LV1_PROT = SYSMMU_V5_LV1_PROT; |
792 | LV2_PROT = SYSMMU_V5_LV2_PROT; | |
793 | } | |
740a01ee MS |
794 | } |
795 | ||
5f26ad58 SP |
796 | if (MMU_MAJ_VER(data->version) >= 5) { |
797 | ret = dma_set_mask(dev, DMA_BIT_MASK(36)); | |
798 | if (ret) { | |
799 | dev_err(dev, "Unable to set DMA mask: %d\n", ret); | |
800 | goto err_dma_set_mask; | |
801 | } | |
802 | } | |
803 | ||
928055a0 MS |
804 | /* |
805 | * use the first registered sysmmu device for performing | |
806 | * dma mapping operations on iommu page tables (cpu cache flush) | |
807 | */ | |
808 | if (!dma_dev) | |
809 | dma_dev = &pdev->dev; | |
810 | ||
f4723ec1 | 811 | pm_runtime_enable(dev); |
2a96536e | 812 | |
bbc4d205 MS |
813 | ret = iommu_device_register(&data->iommu, &exynos_iommu_ops, dev); |
814 | if (ret) | |
815 | goto err_dma_set_mask; | |
816 | ||
2a96536e | 817 | return 0; |
fce398d2 | 818 | |
5f26ad58 | 819 | err_dma_set_mask: |
fce398d2 SP |
820 | iommu_device_sysfs_remove(&data->iommu); |
821 | return ret; | |
2a96536e KC |
822 | } |
823 | ||
9b265536 | 824 | static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) |
622015e4 MS |
825 | { |
826 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 827 | struct device *master = data->master; |
622015e4 | 828 | |
47a574ff | 829 | if (master) { |
0f45b04d | 830 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); |
9b265536 MS |
831 | |
832 | mutex_lock(&owner->rpm_lock); | |
b3d14960 | 833 | if (&data->domain->domain != &exynos_identity_domain) { |
92798b45 MS |
834 | dev_dbg(data->sysmmu, "saving state\n"); |
835 | __sysmmu_disable(data); | |
836 | } | |
9b265536 | 837 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
838 | } |
839 | return 0; | |
840 | } | |
841 | ||
9b265536 | 842 | static int __maybe_unused exynos_sysmmu_resume(struct device *dev) |
622015e4 MS |
843 | { |
844 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 845 | struct device *master = data->master; |
622015e4 | 846 | |
47a574ff | 847 | if (master) { |
0f45b04d | 848 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); |
9b265536 MS |
849 | |
850 | mutex_lock(&owner->rpm_lock); | |
b3d14960 | 851 | if (&data->domain->domain != &exynos_identity_domain) { |
92798b45 MS |
852 | dev_dbg(data->sysmmu, "restoring state\n"); |
853 | __sysmmu_enable(data); | |
854 | } | |
9b265536 | 855 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
856 | } |
857 | return 0; | |
858 | } | |
622015e4 MS |
859 | |
860 | static const struct dev_pm_ops sysmmu_pm_ops = { | |
9b265536 | 861 | SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL) |
2f5f44f2 MS |
862 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
863 | pm_runtime_force_resume) | |
622015e4 MS |
864 | }; |
865 | ||
9d25e3cc | 866 | static const struct of_device_id sysmmu_of_match[] = { |
6b21a5db CK |
867 | { .compatible = "samsung,exynos-sysmmu", }, |
868 | { }, | |
869 | }; | |
870 | ||
871 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
872 | .probe = exynos_sysmmu_probe, | |
873 | .driver = { | |
2a96536e | 874 | .name = "exynos-sysmmu", |
6b21a5db | 875 | .of_match_table = sysmmu_of_match, |
622015e4 | 876 | .pm = &sysmmu_pm_ops, |
b54b874f | 877 | .suppress_bind_attrs = true, |
2a96536e KC |
878 | } |
879 | }; | |
880 | ||
9314006d | 881 | static inline void exynos_iommu_set_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) |
2a96536e | 882 | { |
5e3435eb MS |
883 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent), |
884 | DMA_TO_DEVICE); | |
6ae5343c | 885 | *ent = cpu_to_le32(val); |
5e3435eb MS |
886 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent), |
887 | DMA_TO_DEVICE); | |
2a96536e KC |
888 | } |
889 | ||
3529375e | 890 | static struct iommu_domain *exynos_iommu_domain_alloc_paging(struct device *dev) |
2a96536e | 891 | { |
bfa00489 | 892 | struct exynos_iommu_domain *domain; |
5e3435eb | 893 | dma_addr_t handle; |
66a7ed84 | 894 | int i; |
2a96536e | 895 | |
740a01ee MS |
896 | /* Check if correct PTE offsets are initialized */ |
897 | BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev); | |
e1fd1eaa | 898 | |
bfa00489 MS |
899 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
900 | if (!domain) | |
e1fd1eaa | 901 | return NULL; |
2a96536e | 902 | |
bfa00489 MS |
903 | domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
904 | if (!domain->pgtable) | |
4a376d4a | 905 | goto err_pgtable; |
2a96536e | 906 | |
bfa00489 MS |
907 | domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
908 | if (!domain->lv2entcnt) | |
2a96536e KC |
909 | goto err_counter; |
910 | ||
f171abab | 911 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
e7527663 MS |
912 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
913 | domain->pgtable[i] = ZERO_LV2LINK; | |
66a7ed84 | 914 | |
5e3435eb MS |
915 | handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE, |
916 | DMA_TO_DEVICE); | |
917 | /* For mapping page table entries we rely on dma == phys */ | |
918 | BUG_ON(handle != virt_to_phys(domain->pgtable)); | |
0d6d3da4 MS |
919 | if (dma_mapping_error(dma_dev, handle)) |
920 | goto err_lv2ent; | |
2a96536e | 921 | |
bfa00489 MS |
922 | spin_lock_init(&domain->lock); |
923 | spin_lock_init(&domain->pgtablelock); | |
924 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 925 | |
bfa00489 MS |
926 | domain->domain.geometry.aperture_start = 0; |
927 | domain->domain.geometry.aperture_end = ~0UL; | |
928 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 929 | |
bfa00489 | 930 | return &domain->domain; |
2a96536e | 931 | |
0d6d3da4 MS |
932 | err_lv2ent: |
933 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
2a96536e | 934 | err_counter: |
bfa00489 | 935 | free_pages((unsigned long)domain->pgtable, 2); |
2a96536e | 936 | err_pgtable: |
bfa00489 | 937 | kfree(domain); |
e1fd1eaa | 938 | return NULL; |
2a96536e KC |
939 | } |
940 | ||
bfa00489 | 941 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 942 | { |
bfa00489 | 943 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 944 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
945 | unsigned long flags; |
946 | int i; | |
947 | ||
bfa00489 | 948 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 949 | |
bfa00489 | 950 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 951 | |
bfa00489 | 952 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
e1172300 | 953 | spin_lock(&data->lock); |
b0d4c861 | 954 | __sysmmu_disable(data); |
47a574ff MS |
955 | data->pgtable = 0; |
956 | data->domain = NULL; | |
469acebe | 957 | list_del_init(&data->domain_node); |
e1172300 | 958 | spin_unlock(&data->lock); |
2a96536e KC |
959 | } |
960 | ||
bfa00489 | 961 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 962 | |
5e3435eb MS |
963 | dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE, |
964 | DMA_TO_DEVICE); | |
965 | ||
2a96536e | 966 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
5e3435eb MS |
967 | if (lv1ent_page(domain->pgtable + i)) { |
968 | phys_addr_t base = lv2table_base(domain->pgtable + i); | |
969 | ||
970 | dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, | |
971 | DMA_TO_DEVICE); | |
734c3c73 | 972 | kmem_cache_free(lv2table_kmem_cache, |
5e3435eb MS |
973 | phys_to_virt(base)); |
974 | } | |
2a96536e | 975 | |
bfa00489 MS |
976 | free_pages((unsigned long)domain->pgtable, 2); |
977 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
978 | kfree(domain); | |
2a96536e KC |
979 | } |
980 | ||
b3d14960 JG |
981 | static int exynos_iommu_identity_attach(struct iommu_domain *identity_domain, |
982 | struct device *dev) | |
5fa61cbf | 983 | { |
0f45b04d | 984 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); |
b3d14960 JG |
985 | struct exynos_iommu_domain *domain; |
986 | phys_addr_t pagetable; | |
5fa61cbf MS |
987 | struct sysmmu_drvdata *data, *next; |
988 | unsigned long flags; | |
5fa61cbf | 989 | |
b3d14960 JG |
990 | if (owner->domain == identity_domain) |
991 | return 0; | |
992 | ||
993 | domain = to_exynos_domain(owner->domain); | |
994 | pagetable = virt_to_phys(domain->pgtable); | |
5fa61cbf | 995 | |
9b265536 MS |
996 | mutex_lock(&owner->rpm_lock); |
997 | ||
998 | list_for_each_entry(data, &owner->controllers, owner_node) { | |
999 | pm_runtime_get_noresume(data->sysmmu); | |
1000 | if (pm_runtime_active(data->sysmmu)) | |
1001 | __sysmmu_disable(data); | |
e1172300 MS |
1002 | pm_runtime_put(data->sysmmu); |
1003 | } | |
1004 | ||
5fa61cbf MS |
1005 | spin_lock_irqsave(&domain->lock, flags); |
1006 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { | |
e1172300 | 1007 | spin_lock(&data->lock); |
47a574ff MS |
1008 | data->pgtable = 0; |
1009 | data->domain = NULL; | |
b0d4c861 | 1010 | list_del_init(&data->domain_node); |
e1172300 | 1011 | spin_unlock(&data->lock); |
5fa61cbf | 1012 | } |
b3d14960 | 1013 | owner->domain = identity_domain; |
5fa61cbf MS |
1014 | spin_unlock_irqrestore(&domain->lock, flags); |
1015 | ||
9b265536 | 1016 | mutex_unlock(&owner->rpm_lock); |
5fa61cbf | 1017 | |
b3d14960 JG |
1018 | dev_dbg(dev, "%s: Restored IOMMU to IDENTITY from pgtable %pa\n", |
1019 | __func__, &pagetable); | |
1020 | return 0; | |
5fa61cbf MS |
1021 | } |
1022 | ||
b3d14960 JG |
1023 | static struct iommu_domain_ops exynos_identity_ops = { |
1024 | .attach_dev = exynos_iommu_identity_attach, | |
1025 | }; | |
1026 | ||
1027 | static struct iommu_domain exynos_identity_domain = { | |
1028 | .type = IOMMU_DOMAIN_IDENTITY, | |
1029 | .ops = &exynos_identity_ops, | |
1030 | }; | |
1031 | ||
bfa00489 | 1032 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
1033 | struct device *dev) |
1034 | { | |
bfa00489 | 1035 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
0f45b04d | 1036 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); |
469acebe | 1037 | struct sysmmu_drvdata *data; |
bfa00489 | 1038 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 1039 | unsigned long flags; |
b3d14960 | 1040 | int err; |
2a96536e | 1041 | |
b3d14960 JG |
1042 | err = exynos_iommu_identity_attach(&exynos_identity_domain, dev); |
1043 | if (err) | |
1044 | return err; | |
5fa61cbf | 1045 | |
9b265536 MS |
1046 | mutex_lock(&owner->rpm_lock); |
1047 | ||
e1172300 | 1048 | spin_lock_irqsave(&domain->lock, flags); |
1b092054 | 1049 | list_for_each_entry(data, &owner->controllers, owner_node) { |
e1172300 | 1050 | spin_lock(&data->lock); |
47a574ff MS |
1051 | data->pgtable = pagetable; |
1052 | data->domain = domain; | |
e1172300 MS |
1053 | list_add_tail(&data->domain_node, &domain->clients); |
1054 | spin_unlock(&data->lock); | |
1055 | } | |
1056 | owner->domain = iommu_domain; | |
1057 | spin_unlock_irqrestore(&domain->lock, flags); | |
1058 | ||
9b265536 MS |
1059 | list_for_each_entry(data, &owner->controllers, owner_node) { |
1060 | pm_runtime_get_noresume(data->sysmmu); | |
1061 | if (pm_runtime_active(data->sysmmu)) | |
1062 | __sysmmu_enable(data); | |
1063 | pm_runtime_put(data->sysmmu); | |
1064 | } | |
1065 | ||
1066 | mutex_unlock(&owner->rpm_lock); | |
1067 | ||
b0d4c861 MS |
1068 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__, |
1069 | &pagetable); | |
7222e8db | 1070 | |
b0d4c861 | 1071 | return 0; |
2a96536e KC |
1072 | } |
1073 | ||
bfa00489 | 1074 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 1075 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 1076 | { |
61128f08 | 1077 | if (lv1ent_section(sent)) { |
d09d78fc | 1078 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
1079 | return ERR_PTR(-EADDRINUSE); |
1080 | } | |
1081 | ||
2a96536e | 1082 | if (lv1ent_fault(sent)) { |
0d6d3da4 | 1083 | dma_addr_t handle; |
d09d78fc | 1084 | sysmmu_pte_t *pent; |
66a7ed84 | 1085 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 1086 | |
734c3c73 | 1087 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
dbf6c6ef | 1088 | BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 1089 | if (!pent) |
61128f08 | 1090 | return ERR_PTR(-ENOMEM); |
2a96536e | 1091 | |
9314006d | 1092 | exynos_iommu_set_pte(sent, mk_lv1ent_page(virt_to_phys(pent))); |
dc3814f4 | 1093 | kmemleak_ignore(pent); |
2a96536e | 1094 | *pgcounter = NUM_LV2ENTRIES; |
0d6d3da4 MS |
1095 | handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE, |
1096 | DMA_TO_DEVICE); | |
1097 | if (dma_mapping_error(dma_dev, handle)) { | |
1098 | kmem_cache_free(lv2table_kmem_cache, pent); | |
1099 | return ERR_PTR(-EADDRINUSE); | |
1100 | } | |
66a7ed84 CK |
1101 | |
1102 | /* | |
f171abab SK |
1103 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
1104 | * FLPD cache may cache the address of zero_l2_table. This | |
1105 | * function replaces the zero_l2_table with new L2 page table | |
1106 | * to write valid mappings. | |
66a7ed84 | 1107 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
1108 | * cache may still cache zero_l2_table for the valid area |
1109 | * instead of new L2 page table that has the mapping | |
1110 | * information of the valid area. | |
66a7ed84 CK |
1111 | * Thus any replacement of zero_l2_table with other valid L2 |
1112 | * page table must involve FLPD cache invalidation for System | |
1113 | * MMU v3.3. | |
1114 | * FLPD cache invalidation is performed with TLB invalidation | |
1115 | * by VPN without blocking. It is safe to invalidate TLB without | |
1116 | * blocking because the target address of TLB invalidation is | |
1117 | * not currently mapped. | |
1118 | */ | |
1119 | if (need_flush_flpd_cache) { | |
469acebe | 1120 | struct sysmmu_drvdata *data; |
365409db | 1121 | |
bfa00489 MS |
1122 | spin_lock(&domain->lock); |
1123 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 1124 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 1125 | spin_unlock(&domain->lock); |
66a7ed84 | 1126 | } |
2a96536e KC |
1127 | } |
1128 | ||
1129 | return page_entry(sent, iova); | |
1130 | } | |
1131 | ||
bfa00489 | 1132 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 1133 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
1a0d8dac | 1134 | phys_addr_t paddr, int prot, short *pgcnt) |
2a96536e | 1135 | { |
61128f08 | 1136 | if (lv1ent_section(sent)) { |
d09d78fc | 1137 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 1138 | iova); |
2a96536e | 1139 | return -EADDRINUSE; |
61128f08 | 1140 | } |
2a96536e KC |
1141 | |
1142 | if (lv1ent_page(sent)) { | |
61128f08 | 1143 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 1144 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 1145 | iova); |
2a96536e | 1146 | return -EADDRINUSE; |
61128f08 | 1147 | } |
2a96536e | 1148 | |
734c3c73 | 1149 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
1150 | *pgcnt = 0; |
1151 | } | |
1152 | ||
9314006d | 1153 | exynos_iommu_set_pte(sent, mk_lv1ent_sect(paddr, prot)); |
2a96536e | 1154 | |
bfa00489 | 1155 | spin_lock(&domain->lock); |
66a7ed84 | 1156 | if (lv1ent_page_zero(sent)) { |
469acebe | 1157 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1158 | /* |
1159 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
1160 | * entry by speculative prefetch of SLPD which has no mapping. | |
1161 | */ | |
bfa00489 | 1162 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1163 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 1164 | } |
bfa00489 | 1165 | spin_unlock(&domain->lock); |
66a7ed84 | 1166 | |
2a96536e KC |
1167 | return 0; |
1168 | } | |
1169 | ||
d09d78fc | 1170 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
1a0d8dac | 1171 | int prot, short *pgcnt) |
2a96536e KC |
1172 | { |
1173 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 1174 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
1175 | return -EADDRINUSE; |
1176 | ||
9314006d | 1177 | exynos_iommu_set_pte(pent, mk_lv2ent_spage(paddr, prot)); |
2a96536e KC |
1178 | *pgcnt -= 1; |
1179 | } else { /* size == LPAGE_SIZE */ | |
1180 | int i; | |
5e3435eb | 1181 | dma_addr_t pent_base = virt_to_phys(pent); |
365409db | 1182 | |
5e3435eb MS |
1183 | dma_sync_single_for_cpu(dma_dev, pent_base, |
1184 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
1185 | DMA_TO_DEVICE); | |
2a96536e | 1186 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 1187 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
1188 | if (i > 0) |
1189 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
1190 | return -EADDRINUSE; |
1191 | } | |
1192 | ||
1a0d8dac | 1193 | *pent = mk_lv2ent_lpage(paddr, prot); |
2a96536e | 1194 | } |
5e3435eb MS |
1195 | dma_sync_single_for_device(dma_dev, pent_base, |
1196 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
1197 | DMA_TO_DEVICE); | |
2a96536e KC |
1198 | *pgcnt -= SPAGES_PER_LPAGE; |
1199 | } | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
66a7ed84 CK |
1204 | /* |
1205 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
1206 | * | |
f171abab | 1207 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 1208 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
1209 | * However, the logic has a bug that while caching faulty page table entries, |
1210 | * System MMU reports page fault if the cached fault entry is hit even though | |
1211 | * the fault entry is updated to a valid entry after the entry is cached. | |
1212 | * To prevent caching faulty page table entries which may be updated to valid | |
1213 | * entries later, the virtual memory manager should care about the workaround | |
1214 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
1215 | * |
1216 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 1217 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 1218 | * |
f171abab | 1219 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
1220 | * the following sizes for System MMU v3.1 and v3.2. |
1221 | * System MMU v3.1: 128KiB | |
1222 | * System MMU v3.2: 256KiB | |
1223 | * | |
1224 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
1225 | * more workarounds. |
1226 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
1227 | * than or equal to 128KiB. | |
66a7ed84 CK |
1228 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
1229 | */ | |
bfa00489 MS |
1230 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
1231 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
983efefa | 1232 | size_t count, int prot, gfp_t gfp, size_t *mapped) |
2a96536e | 1233 | { |
bfa00489 | 1234 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1235 | sysmmu_pte_t *entry; |
1236 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
1237 | unsigned long flags; |
1238 | int ret = -ENOMEM; | |
1239 | ||
bfa00489 | 1240 | BUG_ON(domain->pgtable == NULL); |
1a0d8dac | 1241 | prot &= SYSMMU_SUPPORTED_PROT_BITS; |
2a96536e | 1242 | |
bfa00489 | 1243 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1244 | |
bfa00489 | 1245 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1246 | |
1247 | if (size == SECT_SIZE) { | |
1a0d8dac | 1248 | ret = lv1set_section(domain, entry, iova, paddr, prot, |
bfa00489 | 1249 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e | 1250 | } else { |
d09d78fc | 1251 | sysmmu_pte_t *pent; |
2a96536e | 1252 | |
bfa00489 MS |
1253 | pent = alloc_lv2entry(domain, entry, iova, |
1254 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 1255 | |
61128f08 CK |
1256 | if (IS_ERR(pent)) |
1257 | ret = PTR_ERR(pent); | |
2a96536e | 1258 | else |
1a0d8dac | 1259 | ret = lv2set_page(pent, paddr, size, prot, |
bfa00489 | 1260 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
1261 | } |
1262 | ||
61128f08 | 1263 | if (ret) |
0bf4e54d CK |
1264 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
1265 | __func__, ret, size, iova); | |
983efefa RM |
1266 | else |
1267 | *mapped = size; | |
2a96536e | 1268 | |
bfa00489 | 1269 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1270 | |
1271 | return ret; | |
1272 | } | |
1273 | ||
bfa00489 MS |
1274 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
1275 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 1276 | { |
469acebe | 1277 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1278 | unsigned long flags; |
1279 | ||
bfa00489 | 1280 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 1281 | |
bfa00489 | 1282 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1283 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 1284 | |
bfa00489 | 1285 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
1286 | } |
1287 | ||
bfa00489 | 1288 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
983efefa | 1289 | unsigned long l_iova, size_t size, size_t count, |
56f8af5e | 1290 | struct iommu_iotlb_gather *gather) |
2a96536e | 1291 | { |
bfa00489 | 1292 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1293 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
1294 | sysmmu_pte_t *ent; | |
61128f08 | 1295 | size_t err_pgsize; |
d09d78fc | 1296 | unsigned long flags; |
2a96536e | 1297 | |
bfa00489 | 1298 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 1299 | |
bfa00489 | 1300 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1301 | |
bfa00489 | 1302 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
1303 | |
1304 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1305 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1306 | err_pgsize = SECT_SIZE; |
1307 | goto err; | |
1308 | } | |
2a96536e | 1309 | |
f171abab | 1310 | /* workaround for h/w bug in System MMU v3.3 */ |
9314006d | 1311 | exynos_iommu_set_pte(ent, ZERO_LV2LINK); |
2a96536e KC |
1312 | size = SECT_SIZE; |
1313 | goto done; | |
1314 | } | |
1315 | ||
1316 | if (unlikely(lv1ent_fault(ent))) { | |
1317 | if (size > SECT_SIZE) | |
1318 | size = SECT_SIZE; | |
1319 | goto done; | |
1320 | } | |
1321 | ||
1322 | /* lv1ent_page(sent) == true here */ | |
1323 | ||
1324 | ent = page_entry(ent, iova); | |
1325 | ||
1326 | if (unlikely(lv2ent_fault(ent))) { | |
1327 | size = SPAGE_SIZE; | |
1328 | goto done; | |
1329 | } | |
1330 | ||
1331 | if (lv2ent_small(ent)) { | |
9314006d | 1332 | exynos_iommu_set_pte(ent, 0); |
2a96536e | 1333 | size = SPAGE_SIZE; |
bfa00489 | 1334 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1335 | goto done; |
1336 | } | |
1337 | ||
1338 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1339 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1340 | err_pgsize = LPAGE_SIZE; |
1341 | goto err; | |
1342 | } | |
2a96536e | 1343 | |
5e3435eb MS |
1344 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), |
1345 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1346 | DMA_TO_DEVICE); | |
2a96536e | 1347 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); |
5e3435eb MS |
1348 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), |
1349 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1350 | DMA_TO_DEVICE); | |
2a96536e | 1351 | size = LPAGE_SIZE; |
bfa00489 | 1352 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1353 | done: |
bfa00489 | 1354 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1355 | |
bfa00489 | 1356 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1357 | |
2a96536e | 1358 | return size; |
61128f08 | 1359 | err: |
bfa00489 | 1360 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1361 | |
0bf4e54d CK |
1362 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1363 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1364 | |
1365 | return 0; | |
2a96536e KC |
1366 | } |
1367 | ||
bfa00489 | 1368 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1369 | dma_addr_t iova) |
2a96536e | 1370 | { |
bfa00489 | 1371 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1372 | sysmmu_pte_t *entry; |
2a96536e KC |
1373 | unsigned long flags; |
1374 | phys_addr_t phys = 0; | |
1375 | ||
bfa00489 | 1376 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1377 | |
bfa00489 | 1378 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1379 | |
1380 | if (lv1ent_section(entry)) { | |
1381 | phys = section_phys(entry) + section_offs(iova); | |
1382 | } else if (lv1ent_page(entry)) { | |
1383 | entry = page_entry(entry, iova); | |
1384 | ||
1385 | if (lv2ent_large(entry)) | |
1386 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1387 | else if (lv2ent_small(entry)) | |
1388 | phys = spage_phys(entry) + spage_offs(iova); | |
1389 | } | |
1390 | ||
bfa00489 | 1391 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1392 | |
1393 | return phys; | |
1394 | } | |
1395 | ||
3c51c054 | 1396 | static struct iommu_device *exynos_iommu_probe_device(struct device *dev) |
bf4a1c92 | 1397 | { |
0f45b04d | 1398 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); |
7a974b29 | 1399 | struct sysmmu_drvdata *data; |
bf4a1c92 | 1400 | |
06801db0 | 1401 | if (!has_sysmmu(dev)) |
3c51c054 | 1402 | return ERR_PTR(-ENODEV); |
bf4a1c92 | 1403 | |
7a974b29 MS |
1404 | list_for_each_entry(data, &owner->controllers, owner_node) { |
1405 | /* | |
1406 | * SYSMMU will be runtime activated via device link | |
1407 | * (dependency) to its master device, so there are no | |
1408 | * direct calls to pm_runtime_get/put in this driver. | |
1409 | */ | |
1410 | data->link = device_link_add(dev, data->sysmmu, | |
ea4f6400 | 1411 | DL_FLAG_STATELESS | |
7a974b29 MS |
1412 | DL_FLAG_PM_RUNTIME); |
1413 | } | |
bf4a1c92 | 1414 | |
66ae88e7 JR |
1415 | /* There is always at least one entry, see exynos_iommu_of_xlate() */ |
1416 | data = list_first_entry(&owner->controllers, | |
1417 | struct sysmmu_drvdata, owner_node); | |
66ae88e7 | 1418 | |
3c51c054 | 1419 | return &data->iommu; |
bf4a1c92 AM |
1420 | } |
1421 | ||
f91bf327 MS |
1422 | static void exynos_iommu_release_device(struct device *dev) |
1423 | { | |
1424 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); | |
1425 | struct sysmmu_drvdata *data; | |
1426 | ||
b3d14960 | 1427 | WARN_ON(exynos_iommu_identity_attach(&exynos_identity_domain, dev)); |
7a974b29 MS |
1428 | |
1429 | list_for_each_entry(data, &owner->controllers, owner_node) | |
1430 | device_link_del(data->link); | |
bf4a1c92 AM |
1431 | } |
1432 | ||
aa759fd3 MS |
1433 | static int exynos_iommu_of_xlate(struct device *dev, |
1434 | struct of_phandle_args *spec) | |
1435 | { | |
aa759fd3 | 1436 | struct platform_device *sysmmu = of_find_device_by_node(spec->np); |
0f45b04d | 1437 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); |
0bd5a0c7 | 1438 | struct sysmmu_drvdata *data, *entry; |
aa759fd3 MS |
1439 | |
1440 | if (!sysmmu) | |
1441 | return -ENODEV; | |
1442 | ||
1443 | data = platform_get_drvdata(sysmmu); | |
1a260449 YK |
1444 | if (!data) { |
1445 | put_device(&sysmmu->dev); | |
aa759fd3 | 1446 | return -ENODEV; |
1a260449 | 1447 | } |
aa759fd3 MS |
1448 | |
1449 | if (!owner) { | |
1450 | owner = kzalloc(sizeof(*owner), GFP_KERNEL); | |
1a260449 YK |
1451 | if (!owner) { |
1452 | put_device(&sysmmu->dev); | |
aa759fd3 | 1453 | return -ENOMEM; |
1a260449 | 1454 | } |
aa759fd3 MS |
1455 | |
1456 | INIT_LIST_HEAD(&owner->controllers); | |
9b265536 | 1457 | mutex_init(&owner->rpm_lock); |
b3d14960 | 1458 | owner->domain = &exynos_identity_domain; |
0f45b04d | 1459 | dev_iommu_priv_set(dev, owner); |
aa759fd3 MS |
1460 | } |
1461 | ||
0bd5a0c7 MS |
1462 | list_for_each_entry(entry, &owner->controllers, owner_node) |
1463 | if (entry == data) | |
1464 | return 0; | |
1465 | ||
aa759fd3 | 1466 | list_add_tail(&data->owner_node, &owner->controllers); |
92798b45 | 1467 | data->master = dev; |
2f5f44f2 | 1468 | |
aa759fd3 MS |
1469 | return 0; |
1470 | } | |
1471 | ||
0b9a3694 | 1472 | static const struct iommu_ops exynos_iommu_ops = { |
b3d14960 | 1473 | .identity_domain = &exynos_identity_domain, |
3529375e | 1474 | .domain_alloc_paging = exynos_iommu_domain_alloc_paging, |
6d7cf02a | 1475 | .device_group = generic_device_group, |
3c51c054 JR |
1476 | .probe_device = exynos_iommu_probe_device, |
1477 | .release_device = exynos_iommu_release_device, | |
2a96536e | 1478 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
aa759fd3 | 1479 | .of_xlate = exynos_iommu_of_xlate, |
9a630a4b LB |
1480 | .default_domain_ops = &(const struct iommu_domain_ops) { |
1481 | .attach_dev = exynos_iommu_attach_device, | |
983efefa RM |
1482 | .map_pages = exynos_iommu_map, |
1483 | .unmap_pages = exynos_iommu_unmap, | |
9a630a4b LB |
1484 | .iova_to_phys = exynos_iommu_iova_to_phys, |
1485 | .free = exynos_iommu_domain_free, | |
1486 | } | |
2a96536e KC |
1487 | }; |
1488 | ||
1489 | static int __init exynos_iommu_init(void) | |
1490 | { | |
dc98b848 | 1491 | struct device_node *np; |
2a96536e KC |
1492 | int ret; |
1493 | ||
dc98b848 RM |
1494 | np = of_find_matching_node(NULL, sysmmu_of_match); |
1495 | if (!np) | |
1496 | return 0; | |
1497 | ||
1498 | of_node_put(np); | |
1499 | ||
734c3c73 CK |
1500 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1501 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1502 | if (!lv2table_kmem_cache) { | |
1503 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1504 | return -ENOMEM; | |
1505 | } | |
1506 | ||
66a7ed84 CK |
1507 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1508 | if (zero_lv2_table == NULL) { | |
1509 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1510 | __func__); | |
1511 | ret = -ENOMEM; | |
1512 | goto err_zero_lv2; | |
1513 | } | |
1514 | ||
bbc4d205 MS |
1515 | ret = platform_driver_register(&exynos_sysmmu_driver); |
1516 | if (ret) { | |
1517 | pr_err("%s: Failed to register driver\n", __func__); | |
1518 | goto err_reg_driver; | |
1519 | } | |
1520 | ||
734c3c73 | 1521 | return 0; |
734c3c73 | 1522 | err_reg_driver: |
53719876 | 1523 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
bbc4d205 | 1524 | err_zero_lv2: |
734c3c73 | 1525 | kmem_cache_destroy(lv2table_kmem_cache); |
2a96536e KC |
1526 | return ret; |
1527 | } | |
928055a0 | 1528 | core_initcall(exynos_iommu_init); |