Commit | Line | Data |
---|---|---|
0db2e5d1 RM |
1 | /* |
2 | * A fairly generic DMA-API to IOMMU-API glue layer. | |
3 | * | |
4 | * Copyright (C) 2014-2015 ARM Ltd. | |
5 | * | |
6 | * based in part on arch/arm/mm/dma-mapping.c: | |
7 | * Copyright (C) 2000-2004 Russell King | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
f51dc892 | 22 | #include <linux/acpi_iort.h> |
0db2e5d1 RM |
23 | #include <linux/device.h> |
24 | #include <linux/dma-iommu.h> | |
5b11e9cd | 25 | #include <linux/gfp.h> |
0db2e5d1 RM |
26 | #include <linux/huge_mm.h> |
27 | #include <linux/iommu.h> | |
28 | #include <linux/iova.h> | |
44bb7e24 | 29 | #include <linux/irq.h> |
0db2e5d1 | 30 | #include <linux/mm.h> |
fade1ec0 | 31 | #include <linux/pci.h> |
5b11e9cd RM |
32 | #include <linux/scatterlist.h> |
33 | #include <linux/vmalloc.h> | |
0db2e5d1 | 34 | |
44bb7e24 RM |
35 | struct iommu_dma_msi_page { |
36 | struct list_head list; | |
37 | dma_addr_t iova; | |
38 | phys_addr_t phys; | |
39 | }; | |
40 | ||
fdbe574e RM |
41 | enum iommu_dma_cookie_type { |
42 | IOMMU_DMA_IOVA_COOKIE, | |
43 | IOMMU_DMA_MSI_COOKIE, | |
44 | }; | |
45 | ||
44bb7e24 | 46 | struct iommu_dma_cookie { |
fdbe574e RM |
47 | enum iommu_dma_cookie_type type; |
48 | union { | |
49 | /* Full allocator for IOMMU_DMA_IOVA_COOKIE */ | |
50 | struct iova_domain iovad; | |
51 | /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */ | |
52 | dma_addr_t msi_iova; | |
53 | }; | |
54 | struct list_head msi_page_list; | |
55 | spinlock_t msi_lock; | |
2da274cd ZL |
56 | |
57 | /* Domain for flush queue callback; NULL if flush queue not in use */ | |
58 | struct iommu_domain *fq_domain; | |
44bb7e24 RM |
59 | }; |
60 | ||
fdbe574e RM |
61 | static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie) |
62 | { | |
63 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE) | |
64 | return cookie->iovad.granule; | |
65 | return PAGE_SIZE; | |
66 | } | |
67 | ||
fdbe574e RM |
68 | static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type) |
69 | { | |
70 | struct iommu_dma_cookie *cookie; | |
71 | ||
72 | cookie = kzalloc(sizeof(*cookie), GFP_KERNEL); | |
73 | if (cookie) { | |
74 | spin_lock_init(&cookie->msi_lock); | |
75 | INIT_LIST_HEAD(&cookie->msi_page_list); | |
76 | cookie->type = type; | |
77 | } | |
78 | return cookie; | |
44bb7e24 RM |
79 | } |
80 | ||
0db2e5d1 RM |
81 | int iommu_dma_init(void) |
82 | { | |
83 | return iova_cache_get(); | |
84 | } | |
85 | ||
86 | /** | |
87 | * iommu_get_dma_cookie - Acquire DMA-API resources for a domain | |
88 | * @domain: IOMMU domain to prepare for DMA-API usage | |
89 | * | |
90 | * IOMMU drivers should normally call this from their domain_alloc | |
91 | * callback when domain->type == IOMMU_DOMAIN_DMA. | |
92 | */ | |
93 | int iommu_get_dma_cookie(struct iommu_domain *domain) | |
fdbe574e RM |
94 | { |
95 | if (domain->iova_cookie) | |
96 | return -EEXIST; | |
97 | ||
98 | domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE); | |
99 | if (!domain->iova_cookie) | |
100 | return -ENOMEM; | |
101 | ||
102 | return 0; | |
103 | } | |
104 | EXPORT_SYMBOL(iommu_get_dma_cookie); | |
105 | ||
106 | /** | |
107 | * iommu_get_msi_cookie - Acquire just MSI remapping resources | |
108 | * @domain: IOMMU domain to prepare | |
109 | * @base: Start address of IOVA region for MSI mappings | |
110 | * | |
111 | * Users who manage their own IOVA allocation and do not want DMA API support, | |
112 | * but would still like to take advantage of automatic MSI remapping, can use | |
113 | * this to initialise their own domain appropriately. Users should reserve a | |
114 | * contiguous IOVA region, starting at @base, large enough to accommodate the | |
115 | * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address | |
116 | * used by the devices attached to @domain. | |
117 | */ | |
118 | int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) | |
0db2e5d1 | 119 | { |
44bb7e24 | 120 | struct iommu_dma_cookie *cookie; |
0db2e5d1 | 121 | |
fdbe574e RM |
122 | if (domain->type != IOMMU_DOMAIN_UNMANAGED) |
123 | return -EINVAL; | |
124 | ||
0db2e5d1 RM |
125 | if (domain->iova_cookie) |
126 | return -EEXIST; | |
127 | ||
fdbe574e | 128 | cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE); |
44bb7e24 RM |
129 | if (!cookie) |
130 | return -ENOMEM; | |
0db2e5d1 | 131 | |
fdbe574e | 132 | cookie->msi_iova = base; |
44bb7e24 RM |
133 | domain->iova_cookie = cookie; |
134 | return 0; | |
0db2e5d1 | 135 | } |
fdbe574e | 136 | EXPORT_SYMBOL(iommu_get_msi_cookie); |
0db2e5d1 RM |
137 | |
138 | /** | |
139 | * iommu_put_dma_cookie - Release a domain's DMA mapping resources | |
fdbe574e RM |
140 | * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or |
141 | * iommu_get_msi_cookie() | |
0db2e5d1 RM |
142 | * |
143 | * IOMMU drivers should normally call this from their domain_free callback. | |
144 | */ | |
145 | void iommu_put_dma_cookie(struct iommu_domain *domain) | |
146 | { | |
44bb7e24 RM |
147 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
148 | struct iommu_dma_msi_page *msi, *tmp; | |
0db2e5d1 | 149 | |
44bb7e24 | 150 | if (!cookie) |
0db2e5d1 RM |
151 | return; |
152 | ||
fdbe574e | 153 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule) |
44bb7e24 RM |
154 | put_iova_domain(&cookie->iovad); |
155 | ||
156 | list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) { | |
157 | list_del(&msi->list); | |
158 | kfree(msi); | |
159 | } | |
160 | kfree(cookie); | |
0db2e5d1 RM |
161 | domain->iova_cookie = NULL; |
162 | } | |
163 | EXPORT_SYMBOL(iommu_put_dma_cookie); | |
164 | ||
273df963 RM |
165 | /** |
166 | * iommu_dma_get_resv_regions - Reserved region driver helper | |
167 | * @dev: Device from iommu_get_resv_regions() | |
168 | * @list: Reserved region list from iommu_get_resv_regions() | |
169 | * | |
170 | * IOMMU drivers can use this to implement their .get_resv_regions callback | |
cd2c9fcf SK |
171 | * for general non-IOMMU-specific reservations. Currently, this covers GICv3 |
172 | * ITS region reservation on ACPI based ARM platforms that may require HW MSI | |
173 | * reservation. | |
273df963 RM |
174 | */ |
175 | void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) | |
fade1ec0 | 176 | { |
fade1ec0 | 177 | |
98cc4f71 | 178 | if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode)) |
cd2c9fcf | 179 | iort_iommu_msi_get_resv_regions(dev, list); |
273df963 | 180 | |
fade1ec0 | 181 | } |
273df963 | 182 | EXPORT_SYMBOL(iommu_dma_get_resv_regions); |
fade1ec0 | 183 | |
7c1b058c RM |
184 | static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, |
185 | phys_addr_t start, phys_addr_t end) | |
186 | { | |
187 | struct iova_domain *iovad = &cookie->iovad; | |
188 | struct iommu_dma_msi_page *msi_page; | |
189 | int i, num_pages; | |
190 | ||
191 | start -= iova_offset(iovad, start); | |
192 | num_pages = iova_align(iovad, end - start) >> iova_shift(iovad); | |
193 | ||
194 | msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL); | |
195 | if (!msi_page) | |
196 | return -ENOMEM; | |
197 | ||
198 | for (i = 0; i < num_pages; i++) { | |
199 | msi_page[i].phys = start; | |
200 | msi_page[i].iova = start; | |
201 | INIT_LIST_HEAD(&msi_page[i].list); | |
202 | list_add(&msi_page[i].list, &cookie->msi_page_list); | |
203 | start += iovad->granule; | |
204 | } | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
cd2c9fcf SK |
209 | static void iova_reserve_pci_windows(struct pci_dev *dev, |
210 | struct iova_domain *iovad) | |
211 | { | |
212 | struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); | |
213 | struct resource_entry *window; | |
214 | unsigned long lo, hi; | |
215 | ||
216 | resource_list_for_each_entry(window, &bridge->windows) { | |
217 | if (resource_type(window->res) != IORESOURCE_MEM) | |
218 | continue; | |
219 | ||
220 | lo = iova_pfn(iovad, window->res->start - window->offset); | |
221 | hi = iova_pfn(iovad, window->res->end - window->offset); | |
222 | reserve_iova(iovad, lo, hi); | |
223 | } | |
224 | } | |
225 | ||
7c1b058c RM |
226 | static int iova_reserve_iommu_regions(struct device *dev, |
227 | struct iommu_domain *domain) | |
228 | { | |
229 | struct iommu_dma_cookie *cookie = domain->iova_cookie; | |
230 | struct iova_domain *iovad = &cookie->iovad; | |
231 | struct iommu_resv_region *region; | |
232 | LIST_HEAD(resv_regions); | |
233 | int ret = 0; | |
234 | ||
cd2c9fcf SK |
235 | if (dev_is_pci(dev)) |
236 | iova_reserve_pci_windows(to_pci_dev(dev), iovad); | |
237 | ||
7c1b058c RM |
238 | iommu_get_resv_regions(dev, &resv_regions); |
239 | list_for_each_entry(region, &resv_regions, list) { | |
240 | unsigned long lo, hi; | |
241 | ||
242 | /* We ARE the software that manages these! */ | |
243 | if (region->type == IOMMU_RESV_SW_MSI) | |
244 | continue; | |
245 | ||
246 | lo = iova_pfn(iovad, region->start); | |
247 | hi = iova_pfn(iovad, region->start + region->length - 1); | |
248 | reserve_iova(iovad, lo, hi); | |
249 | ||
250 | if (region->type == IOMMU_RESV_MSI) | |
251 | ret = cookie_init_hw_msi_region(cookie, region->start, | |
252 | region->start + region->length); | |
253 | if (ret) | |
254 | break; | |
255 | } | |
256 | iommu_put_resv_regions(dev, &resv_regions); | |
257 | ||
258 | return ret; | |
259 | } | |
260 | ||
2da274cd ZL |
261 | static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad) |
262 | { | |
263 | struct iommu_dma_cookie *cookie; | |
264 | struct iommu_domain *domain; | |
265 | ||
266 | cookie = container_of(iovad, struct iommu_dma_cookie, iovad); | |
267 | domain = cookie->fq_domain; | |
268 | /* | |
269 | * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE | |
270 | * implies that ops->flush_iotlb_all must be non-NULL. | |
271 | */ | |
272 | domain->ops->flush_iotlb_all(domain); | |
273 | } | |
274 | ||
0db2e5d1 RM |
275 | /** |
276 | * iommu_dma_init_domain - Initialise a DMA mapping domain | |
277 | * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() | |
278 | * @base: IOVA at which the mappable address space starts | |
279 | * @size: Size of IOVA space | |
fade1ec0 | 280 | * @dev: Device the domain is being initialised for |
0db2e5d1 RM |
281 | * |
282 | * @base and @size should be exact multiples of IOMMU page granularity to | |
283 | * avoid rounding surprises. If necessary, we reserve the page at address 0 | |
284 | * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but | |
285 | * any change which could make prior IOVAs invalid will fail. | |
286 | */ | |
fade1ec0 RM |
287 | int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, |
288 | u64 size, struct device *dev) | |
0db2e5d1 | 289 | { |
fdbe574e RM |
290 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
291 | struct iova_domain *iovad = &cookie->iovad; | |
c61a4633 | 292 | unsigned long order, base_pfn; |
2da274cd | 293 | int attr; |
0db2e5d1 | 294 | |
fdbe574e RM |
295 | if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE) |
296 | return -EINVAL; | |
0db2e5d1 RM |
297 | |
298 | /* Use the smallest supported page size for IOVA granularity */ | |
d16e0faa | 299 | order = __ffs(domain->pgsize_bitmap); |
0db2e5d1 | 300 | base_pfn = max_t(unsigned long, 1, base >> order); |
0db2e5d1 RM |
301 | |
302 | /* Check the domain allows at least some access to the device... */ | |
303 | if (domain->geometry.force_aperture) { | |
304 | if (base > domain->geometry.aperture_end || | |
305 | base + size <= domain->geometry.aperture_start) { | |
306 | pr_warn("specified DMA range outside IOMMU capability\n"); | |
307 | return -EFAULT; | |
308 | } | |
309 | /* ...then finally give it a kicking to make sure it fits */ | |
310 | base_pfn = max_t(unsigned long, base_pfn, | |
311 | domain->geometry.aperture_start >> order); | |
0db2e5d1 RM |
312 | } |
313 | ||
f51d7bb7 | 314 | /* start_pfn is always nonzero for an already-initialised domain */ |
0db2e5d1 RM |
315 | if (iovad->start_pfn) { |
316 | if (1UL << order != iovad->granule || | |
f51d7bb7 | 317 | base_pfn != iovad->start_pfn) { |
0db2e5d1 RM |
318 | pr_warn("Incompatible range for DMA domain\n"); |
319 | return -EFAULT; | |
320 | } | |
7c1b058c RM |
321 | |
322 | return 0; | |
0db2e5d1 | 323 | } |
7c1b058c | 324 | |
aa3ac946 | 325 | init_iova_domain(iovad, 1UL << order, base_pfn); |
2da274cd ZL |
326 | |
327 | if (!cookie->fq_domain && !iommu_domain_get_attr(domain, | |
328 | DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && attr) { | |
329 | cookie->fq_domain = domain; | |
330 | init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, NULL); | |
331 | } | |
332 | ||
7c1b058c RM |
333 | if (!dev) |
334 | return 0; | |
335 | ||
336 | return iova_reserve_iommu_regions(dev, domain); | |
0db2e5d1 RM |
337 | } |
338 | EXPORT_SYMBOL(iommu_dma_init_domain); | |
339 | ||
340 | /** | |
737c85ca MH |
341 | * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API |
342 | * page flags. | |
0db2e5d1 RM |
343 | * @dir: Direction of DMA transfer |
344 | * @coherent: Is the DMA master cache-coherent? | |
737c85ca | 345 | * @attrs: DMA attributes for the mapping |
0db2e5d1 RM |
346 | * |
347 | * Return: corresponding IOMMU API page protection flags | |
348 | */ | |
737c85ca MH |
349 | int dma_info_to_prot(enum dma_data_direction dir, bool coherent, |
350 | unsigned long attrs) | |
0db2e5d1 RM |
351 | { |
352 | int prot = coherent ? IOMMU_CACHE : 0; | |
353 | ||
737c85ca MH |
354 | if (attrs & DMA_ATTR_PRIVILEGED) |
355 | prot |= IOMMU_PRIV; | |
356 | ||
0db2e5d1 RM |
357 | switch (dir) { |
358 | case DMA_BIDIRECTIONAL: | |
359 | return prot | IOMMU_READ | IOMMU_WRITE; | |
360 | case DMA_TO_DEVICE: | |
361 | return prot | IOMMU_READ; | |
362 | case DMA_FROM_DEVICE: | |
363 | return prot | IOMMU_WRITE; | |
364 | default: | |
365 | return 0; | |
366 | } | |
367 | } | |
368 | ||
842fe519 RM |
369 | static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain, |
370 | size_t size, dma_addr_t dma_limit, struct device *dev) | |
0db2e5d1 | 371 | { |
a44e6657 RM |
372 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
373 | struct iova_domain *iovad = &cookie->iovad; | |
bb65a64c | 374 | unsigned long shift, iova_len, iova = 0; |
0db2e5d1 | 375 | |
a44e6657 RM |
376 | if (cookie->type == IOMMU_DMA_MSI_COOKIE) { |
377 | cookie->msi_iova += size; | |
378 | return cookie->msi_iova - size; | |
379 | } | |
380 | ||
381 | shift = iova_shift(iovad); | |
382 | iova_len = size >> shift; | |
bb65a64c RM |
383 | /* |
384 | * Freeing non-power-of-two-sized allocations back into the IOVA caches | |
385 | * will come back to bite us badly, so we have to waste a bit of space | |
386 | * rounding up anything cacheable to make sure that can't happen. The | |
387 | * order of the unadjusted size will still match upon freeing. | |
388 | */ | |
389 | if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1))) | |
390 | iova_len = roundup_pow_of_two(iova_len); | |
a44e6657 | 391 | |
03bfdc31 RM |
392 | if (dev->bus_dma_mask) |
393 | dma_limit &= dev->bus_dma_mask; | |
394 | ||
c987ff0d RM |
395 | if (domain->geometry.force_aperture) |
396 | dma_limit = min(dma_limit, domain->geometry.aperture_end); | |
122fac03 RM |
397 | |
398 | /* Try to get PCI devices a SAC address */ | |
399 | if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev)) | |
538d5b33 TN |
400 | iova = alloc_iova_fast(iovad, iova_len, |
401 | DMA_BIT_MASK(32) >> shift, false); | |
bb65a64c | 402 | |
122fac03 | 403 | if (!iova) |
538d5b33 TN |
404 | iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift, |
405 | true); | |
122fac03 | 406 | |
bb65a64c | 407 | return (dma_addr_t)iova << shift; |
0db2e5d1 RM |
408 | } |
409 | ||
842fe519 RM |
410 | static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie, |
411 | dma_addr_t iova, size_t size) | |
0db2e5d1 | 412 | { |
842fe519 | 413 | struct iova_domain *iovad = &cookie->iovad; |
0db2e5d1 | 414 | |
a44e6657 | 415 | /* The MSI case is only ever cleaning up its most recent allocation */ |
bb65a64c | 416 | if (cookie->type == IOMMU_DMA_MSI_COOKIE) |
a44e6657 | 417 | cookie->msi_iova -= size; |
2da274cd ZL |
418 | else if (cookie->fq_domain) /* non-strict mode */ |
419 | queue_iova(iovad, iova_pfn(iovad, iova), | |
420 | size >> iova_shift(iovad), 0); | |
bb65a64c | 421 | else |
1cc896ed RM |
422 | free_iova_fast(iovad, iova_pfn(iovad, iova), |
423 | size >> iova_shift(iovad)); | |
842fe519 RM |
424 | } |
425 | ||
426 | static void __iommu_dma_unmap(struct iommu_domain *domain, dma_addr_t dma_addr, | |
427 | size_t size) | |
428 | { | |
a44e6657 RM |
429 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
430 | struct iova_domain *iovad = &cookie->iovad; | |
842fe519 RM |
431 | size_t iova_off = iova_offset(iovad, dma_addr); |
432 | ||
433 | dma_addr -= iova_off; | |
434 | size = iova_align(iovad, size + iova_off); | |
435 | ||
2da274cd ZL |
436 | WARN_ON(iommu_unmap_fast(domain, dma_addr, size) != size); |
437 | if (!cookie->fq_domain) | |
438 | iommu_tlb_sync(domain); | |
a44e6657 | 439 | iommu_dma_free_iova(cookie, dma_addr, size); |
0db2e5d1 RM |
440 | } |
441 | ||
442 | static void __iommu_dma_free_pages(struct page **pages, int count) | |
443 | { | |
444 | while (count--) | |
445 | __free_page(pages[count]); | |
446 | kvfree(pages); | |
447 | } | |
448 | ||
c4b17afb GK |
449 | static struct page **__iommu_dma_alloc_pages(struct device *dev, |
450 | unsigned int count, unsigned long order_mask, gfp_t gfp) | |
0db2e5d1 RM |
451 | { |
452 | struct page **pages; | |
c4b17afb | 453 | unsigned int i = 0, nid = dev_to_node(dev); |
3b6b7e19 RM |
454 | |
455 | order_mask &= (2U << MAX_ORDER) - 1; | |
456 | if (!order_mask) | |
457 | return NULL; | |
0db2e5d1 | 458 | |
c4b17afb | 459 | pages = kvzalloc(count * sizeof(*pages), GFP_KERNEL); |
0db2e5d1 RM |
460 | if (!pages) |
461 | return NULL; | |
462 | ||
463 | /* IOMMU can map any pages, so himem can also be used here */ | |
464 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
465 | ||
466 | while (count) { | |
467 | struct page *page = NULL; | |
3b6b7e19 | 468 | unsigned int order_size; |
0db2e5d1 RM |
469 | |
470 | /* | |
471 | * Higher-order allocations are a convenience rather | |
472 | * than a necessity, hence using __GFP_NORETRY until | |
3b6b7e19 | 473 | * falling back to minimum-order allocations. |
0db2e5d1 | 474 | */ |
3b6b7e19 RM |
475 | for (order_mask &= (2U << __fls(count)) - 1; |
476 | order_mask; order_mask &= ~order_size) { | |
477 | unsigned int order = __fls(order_mask); | |
c4b17afb | 478 | gfp_t alloc_flags = gfp; |
3b6b7e19 RM |
479 | |
480 | order_size = 1U << order; | |
c4b17afb GK |
481 | if (order_mask > order_size) |
482 | alloc_flags |= __GFP_NORETRY; | |
483 | page = alloc_pages_node(nid, alloc_flags, order); | |
0db2e5d1 RM |
484 | if (!page) |
485 | continue; | |
3b6b7e19 RM |
486 | if (!order) |
487 | break; | |
488 | if (!PageCompound(page)) { | |
0db2e5d1 RM |
489 | split_page(page, order); |
490 | break; | |
3b6b7e19 RM |
491 | } else if (!split_huge_page(page)) { |
492 | break; | |
0db2e5d1 | 493 | } |
3b6b7e19 | 494 | __free_pages(page, order); |
0db2e5d1 | 495 | } |
0db2e5d1 RM |
496 | if (!page) { |
497 | __iommu_dma_free_pages(pages, i); | |
498 | return NULL; | |
499 | } | |
3b6b7e19 RM |
500 | count -= order_size; |
501 | while (order_size--) | |
0db2e5d1 RM |
502 | pages[i++] = page++; |
503 | } | |
504 | return pages; | |
505 | } | |
506 | ||
507 | /** | |
508 | * iommu_dma_free - Free a buffer allocated by iommu_dma_alloc() | |
509 | * @dev: Device which owns this buffer | |
510 | * @pages: Array of buffer pages as returned by iommu_dma_alloc() | |
511 | * @size: Size of buffer in bytes | |
512 | * @handle: DMA address of buffer | |
513 | * | |
514 | * Frees both the pages associated with the buffer, and the array | |
515 | * describing them | |
516 | */ | |
517 | void iommu_dma_free(struct device *dev, struct page **pages, size_t size, | |
518 | dma_addr_t *handle) | |
519 | { | |
43c5bf11 | 520 | __iommu_dma_unmap(iommu_get_dma_domain(dev), *handle, size); |
0db2e5d1 | 521 | __iommu_dma_free_pages(pages, PAGE_ALIGN(size) >> PAGE_SHIFT); |
cad34be7 | 522 | *handle = DMA_MAPPING_ERROR; |
0db2e5d1 RM |
523 | } |
524 | ||
525 | /** | |
526 | * iommu_dma_alloc - Allocate and map a buffer contiguous in IOVA space | |
527 | * @dev: Device to allocate memory for. Must be a real device | |
528 | * attached to an iommu_dma_domain | |
529 | * @size: Size of buffer in bytes | |
530 | * @gfp: Allocation flags | |
3b6b7e19 | 531 | * @attrs: DMA attributes for this allocation |
0db2e5d1 RM |
532 | * @prot: IOMMU mapping flags |
533 | * @handle: Out argument for allocated DMA handle | |
534 | * @flush_page: Arch callback which must ensure PAGE_SIZE bytes from the | |
535 | * given VA/PA are visible to the given non-coherent device. | |
536 | * | |
537 | * If @size is less than PAGE_SIZE, then a full CPU page will be allocated, | |
538 | * but an IOMMU which supports smaller pages might not map the whole thing. | |
539 | * | |
540 | * Return: Array of struct page pointers describing the buffer, | |
541 | * or NULL on failure. | |
542 | */ | |
3b6b7e19 | 543 | struct page **iommu_dma_alloc(struct device *dev, size_t size, gfp_t gfp, |
00085f1e | 544 | unsigned long attrs, int prot, dma_addr_t *handle, |
0db2e5d1 RM |
545 | void (*flush_page)(struct device *, const void *, phys_addr_t)) |
546 | { | |
43c5bf11 | 547 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
842fe519 RM |
548 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
549 | struct iova_domain *iovad = &cookie->iovad; | |
0db2e5d1 RM |
550 | struct page **pages; |
551 | struct sg_table sgt; | |
842fe519 | 552 | dma_addr_t iova; |
3b6b7e19 | 553 | unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap; |
0db2e5d1 | 554 | |
cad34be7 | 555 | *handle = DMA_MAPPING_ERROR; |
0db2e5d1 | 556 | |
3b6b7e19 RM |
557 | min_size = alloc_sizes & -alloc_sizes; |
558 | if (min_size < PAGE_SIZE) { | |
559 | min_size = PAGE_SIZE; | |
560 | alloc_sizes |= PAGE_SIZE; | |
561 | } else { | |
562 | size = ALIGN(size, min_size); | |
563 | } | |
00085f1e | 564 | if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES) |
3b6b7e19 RM |
565 | alloc_sizes = min_size; |
566 | ||
567 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c4b17afb GK |
568 | pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT, |
569 | gfp); | |
0db2e5d1 RM |
570 | if (!pages) |
571 | return NULL; | |
572 | ||
842fe519 RM |
573 | size = iova_align(iovad, size); |
574 | iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev); | |
0db2e5d1 RM |
575 | if (!iova) |
576 | goto out_free_pages; | |
577 | ||
0db2e5d1 RM |
578 | if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL)) |
579 | goto out_free_iova; | |
580 | ||
581 | if (!(prot & IOMMU_CACHE)) { | |
582 | struct sg_mapping_iter miter; | |
583 | /* | |
584 | * The CPU-centric flushing implied by SG_MITER_TO_SG isn't | |
585 | * sufficient here, so skip it by using the "wrong" direction. | |
586 | */ | |
587 | sg_miter_start(&miter, sgt.sgl, sgt.orig_nents, SG_MITER_FROM_SG); | |
588 | while (sg_miter_next(&miter)) | |
589 | flush_page(dev, miter.addr, page_to_phys(miter.page)); | |
590 | sg_miter_stop(&miter); | |
591 | } | |
592 | ||
842fe519 | 593 | if (iommu_map_sg(domain, iova, sgt.sgl, sgt.orig_nents, prot) |
0db2e5d1 RM |
594 | < size) |
595 | goto out_free_sg; | |
596 | ||
842fe519 | 597 | *handle = iova; |
0db2e5d1 RM |
598 | sg_free_table(&sgt); |
599 | return pages; | |
600 | ||
601 | out_free_sg: | |
602 | sg_free_table(&sgt); | |
603 | out_free_iova: | |
842fe519 | 604 | iommu_dma_free_iova(cookie, iova, size); |
0db2e5d1 RM |
605 | out_free_pages: |
606 | __iommu_dma_free_pages(pages, count); | |
607 | return NULL; | |
608 | } | |
609 | ||
610 | /** | |
611 | * iommu_dma_mmap - Map a buffer into provided user VMA | |
612 | * @pages: Array representing buffer from iommu_dma_alloc() | |
613 | * @size: Size of buffer in bytes | |
614 | * @vma: VMA describing requested userspace mapping | |
615 | * | |
616 | * Maps the pages of the buffer in @pages into @vma. The caller is responsible | |
617 | * for verifying the correct size and protection of @vma beforehand. | |
618 | */ | |
619 | ||
620 | int iommu_dma_mmap(struct page **pages, size_t size, struct vm_area_struct *vma) | |
621 | { | |
622 | unsigned long uaddr = vma->vm_start; | |
623 | unsigned int i, count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
624 | int ret = -ENXIO; | |
625 | ||
626 | for (i = vma->vm_pgoff; i < count && uaddr < vma->vm_end; i++) { | |
627 | ret = vm_insert_page(vma, uaddr, pages[i]); | |
628 | if (ret) | |
629 | break; | |
630 | uaddr += PAGE_SIZE; | |
631 | } | |
632 | return ret; | |
633 | } | |
634 | ||
51f8cc9e | 635 | static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys, |
43c5bf11 | 636 | size_t size, int prot, struct iommu_domain *domain) |
0db2e5d1 | 637 | { |
842fe519 | 638 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
1cc896ed | 639 | size_t iova_off = 0; |
842fe519 | 640 | dma_addr_t iova; |
0db2e5d1 | 641 | |
1cc896ed RM |
642 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE) { |
643 | iova_off = iova_offset(&cookie->iovad, phys); | |
644 | size = iova_align(&cookie->iovad, size + iova_off); | |
645 | } | |
646 | ||
842fe519 | 647 | iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev); |
0db2e5d1 | 648 | if (!iova) |
cad34be7 | 649 | return DMA_MAPPING_ERROR; |
0db2e5d1 | 650 | |
842fe519 RM |
651 | if (iommu_map(domain, iova, phys - iova_off, size, prot)) { |
652 | iommu_dma_free_iova(cookie, iova, size); | |
cad34be7 | 653 | return DMA_MAPPING_ERROR; |
0db2e5d1 | 654 | } |
842fe519 | 655 | return iova + iova_off; |
0db2e5d1 RM |
656 | } |
657 | ||
51f8cc9e RM |
658 | dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page, |
659 | unsigned long offset, size_t size, int prot) | |
660 | { | |
43c5bf11 RM |
661 | return __iommu_dma_map(dev, page_to_phys(page) + offset, size, prot, |
662 | iommu_get_dma_domain(dev)); | |
51f8cc9e RM |
663 | } |
664 | ||
0db2e5d1 | 665 | void iommu_dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size, |
00085f1e | 666 | enum dma_data_direction dir, unsigned long attrs) |
0db2e5d1 | 667 | { |
43c5bf11 | 668 | __iommu_dma_unmap(iommu_get_dma_domain(dev), handle, size); |
0db2e5d1 RM |
669 | } |
670 | ||
671 | /* | |
672 | * Prepare a successfully-mapped scatterlist to give back to the caller. | |
809eac54 RM |
673 | * |
674 | * At this point the segments are already laid out by iommu_dma_map_sg() to | |
675 | * avoid individually crossing any boundaries, so we merely need to check a | |
676 | * segment's start address to avoid concatenating across one. | |
0db2e5d1 RM |
677 | */ |
678 | static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents, | |
679 | dma_addr_t dma_addr) | |
680 | { | |
809eac54 RM |
681 | struct scatterlist *s, *cur = sg; |
682 | unsigned long seg_mask = dma_get_seg_boundary(dev); | |
683 | unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev); | |
684 | int i, count = 0; | |
0db2e5d1 RM |
685 | |
686 | for_each_sg(sg, s, nents, i) { | |
809eac54 RM |
687 | /* Restore this segment's original unaligned fields first */ |
688 | unsigned int s_iova_off = sg_dma_address(s); | |
0db2e5d1 | 689 | unsigned int s_length = sg_dma_len(s); |
809eac54 | 690 | unsigned int s_iova_len = s->length; |
0db2e5d1 | 691 | |
809eac54 | 692 | s->offset += s_iova_off; |
0db2e5d1 | 693 | s->length = s_length; |
cad34be7 | 694 | sg_dma_address(s) = DMA_MAPPING_ERROR; |
809eac54 RM |
695 | sg_dma_len(s) = 0; |
696 | ||
697 | /* | |
698 | * Now fill in the real DMA data. If... | |
699 | * - there is a valid output segment to append to | |
700 | * - and this segment starts on an IOVA page boundary | |
701 | * - but doesn't fall at a segment boundary | |
702 | * - and wouldn't make the resulting output segment too long | |
703 | */ | |
704 | if (cur_len && !s_iova_off && (dma_addr & seg_mask) && | |
705 | (cur_len + s_length <= max_len)) { | |
706 | /* ...then concatenate it with the previous one */ | |
707 | cur_len += s_length; | |
708 | } else { | |
709 | /* Otherwise start the next output segment */ | |
710 | if (i > 0) | |
711 | cur = sg_next(cur); | |
712 | cur_len = s_length; | |
713 | count++; | |
714 | ||
715 | sg_dma_address(cur) = dma_addr + s_iova_off; | |
716 | } | |
717 | ||
718 | sg_dma_len(cur) = cur_len; | |
719 | dma_addr += s_iova_len; | |
720 | ||
721 | if (s_length + s_iova_off < s_iova_len) | |
722 | cur_len = 0; | |
0db2e5d1 | 723 | } |
809eac54 | 724 | return count; |
0db2e5d1 RM |
725 | } |
726 | ||
727 | /* | |
728 | * If mapping failed, then just restore the original list, | |
729 | * but making sure the DMA fields are invalidated. | |
730 | */ | |
731 | static void __invalidate_sg(struct scatterlist *sg, int nents) | |
732 | { | |
733 | struct scatterlist *s; | |
734 | int i; | |
735 | ||
736 | for_each_sg(sg, s, nents, i) { | |
cad34be7 | 737 | if (sg_dma_address(s) != DMA_MAPPING_ERROR) |
07b48ac4 | 738 | s->offset += sg_dma_address(s); |
0db2e5d1 RM |
739 | if (sg_dma_len(s)) |
740 | s->length = sg_dma_len(s); | |
cad34be7 | 741 | sg_dma_address(s) = DMA_MAPPING_ERROR; |
0db2e5d1 RM |
742 | sg_dma_len(s) = 0; |
743 | } | |
744 | } | |
745 | ||
746 | /* | |
747 | * The DMA API client is passing in a scatterlist which could describe | |
748 | * any old buffer layout, but the IOMMU API requires everything to be | |
749 | * aligned to IOMMU pages. Hence the need for this complicated bit of | |
750 | * impedance-matching, to be able to hand off a suitably-aligned list, | |
751 | * but still preserve the original offsets and sizes for the caller. | |
752 | */ | |
753 | int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, | |
754 | int nents, int prot) | |
755 | { | |
43c5bf11 | 756 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
842fe519 RM |
757 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
758 | struct iova_domain *iovad = &cookie->iovad; | |
0db2e5d1 | 759 | struct scatterlist *s, *prev = NULL; |
842fe519 | 760 | dma_addr_t iova; |
0db2e5d1 | 761 | size_t iova_len = 0; |
809eac54 | 762 | unsigned long mask = dma_get_seg_boundary(dev); |
0db2e5d1 RM |
763 | int i; |
764 | ||
765 | /* | |
766 | * Work out how much IOVA space we need, and align the segments to | |
767 | * IOVA granules for the IOMMU driver to handle. With some clever | |
768 | * trickery we can modify the list in-place, but reversibly, by | |
809eac54 | 769 | * stashing the unaligned parts in the as-yet-unused DMA fields. |
0db2e5d1 RM |
770 | */ |
771 | for_each_sg(sg, s, nents, i) { | |
809eac54 | 772 | size_t s_iova_off = iova_offset(iovad, s->offset); |
0db2e5d1 | 773 | size_t s_length = s->length; |
809eac54 | 774 | size_t pad_len = (mask - iova_len + 1) & mask; |
0db2e5d1 | 775 | |
809eac54 | 776 | sg_dma_address(s) = s_iova_off; |
0db2e5d1 | 777 | sg_dma_len(s) = s_length; |
809eac54 RM |
778 | s->offset -= s_iova_off; |
779 | s_length = iova_align(iovad, s_length + s_iova_off); | |
0db2e5d1 RM |
780 | s->length = s_length; |
781 | ||
782 | /* | |
809eac54 RM |
783 | * Due to the alignment of our single IOVA allocation, we can |
784 | * depend on these assumptions about the segment boundary mask: | |
785 | * - If mask size >= IOVA size, then the IOVA range cannot | |
786 | * possibly fall across a boundary, so we don't care. | |
787 | * - If mask size < IOVA size, then the IOVA range must start | |
788 | * exactly on a boundary, therefore we can lay things out | |
789 | * based purely on segment lengths without needing to know | |
790 | * the actual addresses beforehand. | |
791 | * - The mask must be a power of 2, so pad_len == 0 if | |
792 | * iova_len == 0, thus we cannot dereference prev the first | |
793 | * time through here (i.e. before it has a meaningful value). | |
0db2e5d1 | 794 | */ |
809eac54 | 795 | if (pad_len && pad_len < s_length - 1) { |
0db2e5d1 RM |
796 | prev->length += pad_len; |
797 | iova_len += pad_len; | |
798 | } | |
799 | ||
800 | iova_len += s_length; | |
801 | prev = s; | |
802 | } | |
803 | ||
842fe519 | 804 | iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev); |
0db2e5d1 RM |
805 | if (!iova) |
806 | goto out_restore_sg; | |
807 | ||
808 | /* | |
809 | * We'll leave any physical concatenation to the IOMMU driver's | |
810 | * implementation - it knows better than we do. | |
811 | */ | |
842fe519 | 812 | if (iommu_map_sg(domain, iova, sg, nents, prot) < iova_len) |
0db2e5d1 RM |
813 | goto out_free_iova; |
814 | ||
842fe519 | 815 | return __finalise_sg(dev, sg, nents, iova); |
0db2e5d1 RM |
816 | |
817 | out_free_iova: | |
842fe519 | 818 | iommu_dma_free_iova(cookie, iova, iova_len); |
0db2e5d1 RM |
819 | out_restore_sg: |
820 | __invalidate_sg(sg, nents); | |
821 | return 0; | |
822 | } | |
823 | ||
824 | void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
00085f1e | 825 | enum dma_data_direction dir, unsigned long attrs) |
0db2e5d1 | 826 | { |
842fe519 RM |
827 | dma_addr_t start, end; |
828 | struct scatterlist *tmp; | |
829 | int i; | |
0db2e5d1 RM |
830 | /* |
831 | * The scatterlist segments are mapped into a single | |
832 | * contiguous IOVA allocation, so this is incredibly easy. | |
833 | */ | |
842fe519 RM |
834 | start = sg_dma_address(sg); |
835 | for_each_sg(sg_next(sg), tmp, nents - 1, i) { | |
836 | if (sg_dma_len(tmp) == 0) | |
837 | break; | |
838 | sg = tmp; | |
839 | } | |
840 | end = sg_dma_address(sg) + sg_dma_len(sg); | |
43c5bf11 | 841 | __iommu_dma_unmap(iommu_get_dma_domain(dev), start, end - start); |
0db2e5d1 RM |
842 | } |
843 | ||
51f8cc9e RM |
844 | dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys, |
845 | size_t size, enum dma_data_direction dir, unsigned long attrs) | |
846 | { | |
847 | return __iommu_dma_map(dev, phys, size, | |
43c5bf11 RM |
848 | dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO, |
849 | iommu_get_dma_domain(dev)); | |
51f8cc9e RM |
850 | } |
851 | ||
852 | void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, | |
853 | size_t size, enum dma_data_direction dir, unsigned long attrs) | |
854 | { | |
43c5bf11 | 855 | __iommu_dma_unmap(iommu_get_dma_domain(dev), handle, size); |
51f8cc9e RM |
856 | } |
857 | ||
44bb7e24 RM |
858 | static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev, |
859 | phys_addr_t msi_addr, struct iommu_domain *domain) | |
860 | { | |
861 | struct iommu_dma_cookie *cookie = domain->iova_cookie; | |
862 | struct iommu_dma_msi_page *msi_page; | |
842fe519 | 863 | dma_addr_t iova; |
44bb7e24 | 864 | int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; |
fdbe574e | 865 | size_t size = cookie_msi_granule(cookie); |
44bb7e24 | 866 | |
fdbe574e | 867 | msi_addr &= ~(phys_addr_t)(size - 1); |
44bb7e24 RM |
868 | list_for_each_entry(msi_page, &cookie->msi_page_list, list) |
869 | if (msi_page->phys == msi_addr) | |
870 | return msi_page; | |
871 | ||
872 | msi_page = kzalloc(sizeof(*msi_page), GFP_ATOMIC); | |
873 | if (!msi_page) | |
874 | return NULL; | |
875 | ||
43c5bf11 | 876 | iova = __iommu_dma_map(dev, msi_addr, size, prot, domain); |
cad34be7 | 877 | if (iova == DMA_MAPPING_ERROR) |
a44e6657 | 878 | goto out_free_page; |
44bb7e24 RM |
879 | |
880 | INIT_LIST_HEAD(&msi_page->list); | |
a44e6657 RM |
881 | msi_page->phys = msi_addr; |
882 | msi_page->iova = iova; | |
44bb7e24 RM |
883 | list_add(&msi_page->list, &cookie->msi_page_list); |
884 | return msi_page; | |
885 | ||
44bb7e24 RM |
886 | out_free_page: |
887 | kfree(msi_page); | |
888 | return NULL; | |
889 | } | |
890 | ||
891 | void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg) | |
892 | { | |
893 | struct device *dev = msi_desc_to_dev(irq_get_msi_desc(irq)); | |
894 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); | |
895 | struct iommu_dma_cookie *cookie; | |
896 | struct iommu_dma_msi_page *msi_page; | |
897 | phys_addr_t msi_addr = (u64)msg->address_hi << 32 | msg->address_lo; | |
898 | unsigned long flags; | |
899 | ||
900 | if (!domain || !domain->iova_cookie) | |
901 | return; | |
902 | ||
903 | cookie = domain->iova_cookie; | |
904 | ||
905 | /* | |
906 | * We disable IRQs to rule out a possible inversion against | |
907 | * irq_desc_lock if, say, someone tries to retarget the affinity | |
908 | * of an MSI from within an IPI handler. | |
909 | */ | |
910 | spin_lock_irqsave(&cookie->msi_lock, flags); | |
911 | msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain); | |
912 | spin_unlock_irqrestore(&cookie->msi_lock, flags); | |
913 | ||
914 | if (WARN_ON(!msi_page)) { | |
915 | /* | |
916 | * We're called from a void callback, so the best we can do is | |
917 | * 'fail' by filling the message with obviously bogus values. | |
918 | * Since we got this far due to an IOMMU being present, it's | |
919 | * not like the existing address would have worked anyway... | |
920 | */ | |
921 | msg->address_hi = ~0U; | |
922 | msg->address_lo = ~0U; | |
923 | msg->data = ~0U; | |
924 | } else { | |
925 | msg->address_hi = upper_32_bits(msi_page->iova); | |
fdbe574e | 926 | msg->address_lo &= cookie_msi_granule(cookie) - 1; |
44bb7e24 RM |
927 | msg->address_lo += lower_32_bits(msi_page->iova); |
928 | } | |
929 | } |