Commit | Line | Data |
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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0db2e5d1 RM |
2 | /* |
3 | * A fairly generic DMA-API to IOMMU-API glue layer. | |
4 | * | |
5 | * Copyright (C) 2014-2015 ARM Ltd. | |
6 | * | |
7 | * based in part on arch/arm/mm/dma-mapping.c: | |
8 | * Copyright (C) 2000-2004 Russell King | |
0db2e5d1 RM |
9 | */ |
10 | ||
f51dc892 | 11 | #include <linux/acpi_iort.h> |
0db2e5d1 | 12 | #include <linux/device.h> |
06d60728 | 13 | #include <linux/dma-contiguous.h> |
0db2e5d1 | 14 | #include <linux/dma-iommu.h> |
af751d43 | 15 | #include <linux/dma-noncoherent.h> |
5b11e9cd | 16 | #include <linux/gfp.h> |
0db2e5d1 RM |
17 | #include <linux/huge_mm.h> |
18 | #include <linux/iommu.h> | |
19 | #include <linux/iova.h> | |
44bb7e24 | 20 | #include <linux/irq.h> |
0db2e5d1 | 21 | #include <linux/mm.h> |
c1864790 | 22 | #include <linux/mutex.h> |
fade1ec0 | 23 | #include <linux/pci.h> |
5b11e9cd RM |
24 | #include <linux/scatterlist.h> |
25 | #include <linux/vmalloc.h> | |
795bbbb9 | 26 | #include <linux/crash_dump.h> |
0db2e5d1 | 27 | |
44bb7e24 RM |
28 | struct iommu_dma_msi_page { |
29 | struct list_head list; | |
30 | dma_addr_t iova; | |
31 | phys_addr_t phys; | |
32 | }; | |
33 | ||
fdbe574e RM |
34 | enum iommu_dma_cookie_type { |
35 | IOMMU_DMA_IOVA_COOKIE, | |
36 | IOMMU_DMA_MSI_COOKIE, | |
37 | }; | |
38 | ||
44bb7e24 | 39 | struct iommu_dma_cookie { |
fdbe574e RM |
40 | enum iommu_dma_cookie_type type; |
41 | union { | |
42 | /* Full allocator for IOMMU_DMA_IOVA_COOKIE */ | |
43 | struct iova_domain iovad; | |
44 | /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */ | |
45 | dma_addr_t msi_iova; | |
46 | }; | |
47 | struct list_head msi_page_list; | |
2da274cd ZL |
48 | |
49 | /* Domain for flush queue callback; NULL if flush queue not in use */ | |
50 | struct iommu_domain *fq_domain; | |
44bb7e24 RM |
51 | }; |
52 | ||
fdbe574e RM |
53 | static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie) |
54 | { | |
55 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE) | |
56 | return cookie->iovad.granule; | |
57 | return PAGE_SIZE; | |
58 | } | |
59 | ||
fdbe574e RM |
60 | static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type) |
61 | { | |
62 | struct iommu_dma_cookie *cookie; | |
63 | ||
64 | cookie = kzalloc(sizeof(*cookie), GFP_KERNEL); | |
65 | if (cookie) { | |
fdbe574e RM |
66 | INIT_LIST_HEAD(&cookie->msi_page_list); |
67 | cookie->type = type; | |
68 | } | |
69 | return cookie; | |
44bb7e24 RM |
70 | } |
71 | ||
0db2e5d1 RM |
72 | /** |
73 | * iommu_get_dma_cookie - Acquire DMA-API resources for a domain | |
74 | * @domain: IOMMU domain to prepare for DMA-API usage | |
75 | * | |
76 | * IOMMU drivers should normally call this from their domain_alloc | |
77 | * callback when domain->type == IOMMU_DOMAIN_DMA. | |
78 | */ | |
79 | int iommu_get_dma_cookie(struct iommu_domain *domain) | |
fdbe574e RM |
80 | { |
81 | if (domain->iova_cookie) | |
82 | return -EEXIST; | |
83 | ||
84 | domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE); | |
85 | if (!domain->iova_cookie) | |
86 | return -ENOMEM; | |
87 | ||
88 | return 0; | |
89 | } | |
90 | EXPORT_SYMBOL(iommu_get_dma_cookie); | |
91 | ||
92 | /** | |
93 | * iommu_get_msi_cookie - Acquire just MSI remapping resources | |
94 | * @domain: IOMMU domain to prepare | |
95 | * @base: Start address of IOVA region for MSI mappings | |
96 | * | |
97 | * Users who manage their own IOVA allocation and do not want DMA API support, | |
98 | * but would still like to take advantage of automatic MSI remapping, can use | |
99 | * this to initialise their own domain appropriately. Users should reserve a | |
100 | * contiguous IOVA region, starting at @base, large enough to accommodate the | |
101 | * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address | |
102 | * used by the devices attached to @domain. | |
103 | */ | |
104 | int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) | |
0db2e5d1 | 105 | { |
44bb7e24 | 106 | struct iommu_dma_cookie *cookie; |
0db2e5d1 | 107 | |
fdbe574e RM |
108 | if (domain->type != IOMMU_DOMAIN_UNMANAGED) |
109 | return -EINVAL; | |
110 | ||
0db2e5d1 RM |
111 | if (domain->iova_cookie) |
112 | return -EEXIST; | |
113 | ||
fdbe574e | 114 | cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE); |
44bb7e24 RM |
115 | if (!cookie) |
116 | return -ENOMEM; | |
0db2e5d1 | 117 | |
fdbe574e | 118 | cookie->msi_iova = base; |
44bb7e24 RM |
119 | domain->iova_cookie = cookie; |
120 | return 0; | |
0db2e5d1 | 121 | } |
fdbe574e | 122 | EXPORT_SYMBOL(iommu_get_msi_cookie); |
0db2e5d1 RM |
123 | |
124 | /** | |
125 | * iommu_put_dma_cookie - Release a domain's DMA mapping resources | |
fdbe574e RM |
126 | * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or |
127 | * iommu_get_msi_cookie() | |
0db2e5d1 RM |
128 | * |
129 | * IOMMU drivers should normally call this from their domain_free callback. | |
130 | */ | |
131 | void iommu_put_dma_cookie(struct iommu_domain *domain) | |
132 | { | |
44bb7e24 RM |
133 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
134 | struct iommu_dma_msi_page *msi, *tmp; | |
0db2e5d1 | 135 | |
44bb7e24 | 136 | if (!cookie) |
0db2e5d1 RM |
137 | return; |
138 | ||
fdbe574e | 139 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule) |
44bb7e24 RM |
140 | put_iova_domain(&cookie->iovad); |
141 | ||
142 | list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) { | |
143 | list_del(&msi->list); | |
144 | kfree(msi); | |
145 | } | |
146 | kfree(cookie); | |
0db2e5d1 RM |
147 | domain->iova_cookie = NULL; |
148 | } | |
149 | EXPORT_SYMBOL(iommu_put_dma_cookie); | |
150 | ||
273df963 RM |
151 | /** |
152 | * iommu_dma_get_resv_regions - Reserved region driver helper | |
153 | * @dev: Device from iommu_get_resv_regions() | |
154 | * @list: Reserved region list from iommu_get_resv_regions() | |
155 | * | |
156 | * IOMMU drivers can use this to implement their .get_resv_regions callback | |
cd2c9fcf SK |
157 | * for general non-IOMMU-specific reservations. Currently, this covers GICv3 |
158 | * ITS region reservation on ACPI based ARM platforms that may require HW MSI | |
159 | * reservation. | |
273df963 RM |
160 | */ |
161 | void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) | |
fade1ec0 | 162 | { |
fade1ec0 | 163 | |
98cc4f71 | 164 | if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode)) |
cd2c9fcf | 165 | iort_iommu_msi_get_resv_regions(dev, list); |
273df963 | 166 | |
fade1ec0 | 167 | } |
273df963 | 168 | EXPORT_SYMBOL(iommu_dma_get_resv_regions); |
fade1ec0 | 169 | |
7c1b058c RM |
170 | static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, |
171 | phys_addr_t start, phys_addr_t end) | |
172 | { | |
173 | struct iova_domain *iovad = &cookie->iovad; | |
174 | struct iommu_dma_msi_page *msi_page; | |
175 | int i, num_pages; | |
176 | ||
177 | start -= iova_offset(iovad, start); | |
178 | num_pages = iova_align(iovad, end - start) >> iova_shift(iovad); | |
179 | ||
180 | msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL); | |
181 | if (!msi_page) | |
182 | return -ENOMEM; | |
183 | ||
184 | for (i = 0; i < num_pages; i++) { | |
185 | msi_page[i].phys = start; | |
186 | msi_page[i].iova = start; | |
187 | INIT_LIST_HEAD(&msi_page[i].list); | |
188 | list_add(&msi_page[i].list, &cookie->msi_page_list); | |
189 | start += iovad->granule; | |
190 | } | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
aadad097 | 195 | static int iova_reserve_pci_windows(struct pci_dev *dev, |
cd2c9fcf SK |
196 | struct iova_domain *iovad) |
197 | { | |
198 | struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); | |
199 | struct resource_entry *window; | |
200 | unsigned long lo, hi; | |
aadad097 | 201 | phys_addr_t start = 0, end; |
cd2c9fcf SK |
202 | |
203 | resource_list_for_each_entry(window, &bridge->windows) { | |
204 | if (resource_type(window->res) != IORESOURCE_MEM) | |
205 | continue; | |
206 | ||
207 | lo = iova_pfn(iovad, window->res->start - window->offset); | |
208 | hi = iova_pfn(iovad, window->res->end - window->offset); | |
209 | reserve_iova(iovad, lo, hi); | |
210 | } | |
aadad097 SM |
211 | |
212 | /* Get reserved DMA windows from host bridge */ | |
213 | resource_list_for_each_entry(window, &bridge->dma_ranges) { | |
214 | end = window->res->start - window->offset; | |
215 | resv_iova: | |
216 | if (end > start) { | |
217 | lo = iova_pfn(iovad, start); | |
218 | hi = iova_pfn(iovad, end); | |
219 | reserve_iova(iovad, lo, hi); | |
220 | } else { | |
221 | /* dma_ranges list should be sorted */ | |
222 | dev_err(&dev->dev, "Failed to reserve IOVA\n"); | |
223 | return -EINVAL; | |
224 | } | |
225 | ||
226 | start = window->res->end - window->offset + 1; | |
227 | /* If window is last entry */ | |
228 | if (window->node.next == &bridge->dma_ranges && | |
29fcea8c AB |
229 | end != ~(phys_addr_t)0) { |
230 | end = ~(phys_addr_t)0; | |
aadad097 SM |
231 | goto resv_iova; |
232 | } | |
233 | } | |
234 | ||
235 | return 0; | |
cd2c9fcf SK |
236 | } |
237 | ||
7c1b058c RM |
238 | static int iova_reserve_iommu_regions(struct device *dev, |
239 | struct iommu_domain *domain) | |
240 | { | |
241 | struct iommu_dma_cookie *cookie = domain->iova_cookie; | |
242 | struct iova_domain *iovad = &cookie->iovad; | |
243 | struct iommu_resv_region *region; | |
244 | LIST_HEAD(resv_regions); | |
245 | int ret = 0; | |
246 | ||
aadad097 SM |
247 | if (dev_is_pci(dev)) { |
248 | ret = iova_reserve_pci_windows(to_pci_dev(dev), iovad); | |
249 | if (ret) | |
250 | return ret; | |
251 | } | |
cd2c9fcf | 252 | |
7c1b058c RM |
253 | iommu_get_resv_regions(dev, &resv_regions); |
254 | list_for_each_entry(region, &resv_regions, list) { | |
255 | unsigned long lo, hi; | |
256 | ||
257 | /* We ARE the software that manages these! */ | |
258 | if (region->type == IOMMU_RESV_SW_MSI) | |
259 | continue; | |
260 | ||
261 | lo = iova_pfn(iovad, region->start); | |
262 | hi = iova_pfn(iovad, region->start + region->length - 1); | |
263 | reserve_iova(iovad, lo, hi); | |
264 | ||
265 | if (region->type == IOMMU_RESV_MSI) | |
266 | ret = cookie_init_hw_msi_region(cookie, region->start, | |
267 | region->start + region->length); | |
268 | if (ret) | |
269 | break; | |
270 | } | |
271 | iommu_put_resv_regions(dev, &resv_regions); | |
272 | ||
273 | return ret; | |
274 | } | |
275 | ||
2da274cd ZL |
276 | static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad) |
277 | { | |
278 | struct iommu_dma_cookie *cookie; | |
279 | struct iommu_domain *domain; | |
280 | ||
281 | cookie = container_of(iovad, struct iommu_dma_cookie, iovad); | |
282 | domain = cookie->fq_domain; | |
283 | /* | |
284 | * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE | |
285 | * implies that ops->flush_iotlb_all must be non-NULL. | |
286 | */ | |
287 | domain->ops->flush_iotlb_all(domain); | |
288 | } | |
289 | ||
0db2e5d1 RM |
290 | /** |
291 | * iommu_dma_init_domain - Initialise a DMA mapping domain | |
292 | * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() | |
293 | * @base: IOVA at which the mappable address space starts | |
294 | * @size: Size of IOVA space | |
fade1ec0 | 295 | * @dev: Device the domain is being initialised for |
0db2e5d1 RM |
296 | * |
297 | * @base and @size should be exact multiples of IOMMU page granularity to | |
298 | * avoid rounding surprises. If necessary, we reserve the page at address 0 | |
299 | * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but | |
300 | * any change which could make prior IOVAs invalid will fail. | |
301 | */ | |
06d60728 | 302 | static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, |
fade1ec0 | 303 | u64 size, struct device *dev) |
0db2e5d1 | 304 | { |
fdbe574e | 305 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
c61a4633 | 306 | unsigned long order, base_pfn; |
6b0c54e7 | 307 | struct iova_domain *iovad; |
2da274cd | 308 | int attr; |
0db2e5d1 | 309 | |
fdbe574e RM |
310 | if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE) |
311 | return -EINVAL; | |
0db2e5d1 | 312 | |
6b0c54e7 YL |
313 | iovad = &cookie->iovad; |
314 | ||
0db2e5d1 | 315 | /* Use the smallest supported page size for IOVA granularity */ |
d16e0faa | 316 | order = __ffs(domain->pgsize_bitmap); |
0db2e5d1 | 317 | base_pfn = max_t(unsigned long, 1, base >> order); |
0db2e5d1 RM |
318 | |
319 | /* Check the domain allows at least some access to the device... */ | |
320 | if (domain->geometry.force_aperture) { | |
321 | if (base > domain->geometry.aperture_end || | |
322 | base + size <= domain->geometry.aperture_start) { | |
323 | pr_warn("specified DMA range outside IOMMU capability\n"); | |
324 | return -EFAULT; | |
325 | } | |
326 | /* ...then finally give it a kicking to make sure it fits */ | |
327 | base_pfn = max_t(unsigned long, base_pfn, | |
328 | domain->geometry.aperture_start >> order); | |
0db2e5d1 RM |
329 | } |
330 | ||
f51d7bb7 | 331 | /* start_pfn is always nonzero for an already-initialised domain */ |
0db2e5d1 RM |
332 | if (iovad->start_pfn) { |
333 | if (1UL << order != iovad->granule || | |
f51d7bb7 | 334 | base_pfn != iovad->start_pfn) { |
0db2e5d1 RM |
335 | pr_warn("Incompatible range for DMA domain\n"); |
336 | return -EFAULT; | |
337 | } | |
7c1b058c RM |
338 | |
339 | return 0; | |
0db2e5d1 | 340 | } |
7c1b058c | 341 | |
aa3ac946 | 342 | init_iova_domain(iovad, 1UL << order, base_pfn); |
2da274cd ZL |
343 | |
344 | if (!cookie->fq_domain && !iommu_domain_get_attr(domain, | |
345 | DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && attr) { | |
346 | cookie->fq_domain = domain; | |
347 | init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, NULL); | |
348 | } | |
349 | ||
7c1b058c RM |
350 | if (!dev) |
351 | return 0; | |
352 | ||
353 | return iova_reserve_iommu_regions(dev, domain); | |
0db2e5d1 | 354 | } |
0db2e5d1 | 355 | |
795bbbb9 TM |
356 | static int iommu_dma_deferred_attach(struct device *dev, |
357 | struct iommu_domain *domain) | |
358 | { | |
359 | const struct iommu_ops *ops = domain->ops; | |
360 | ||
361 | if (!is_kdump_kernel()) | |
362 | return 0; | |
363 | ||
364 | if (unlikely(ops->is_attach_deferred && | |
365 | ops->is_attach_deferred(domain, dev))) | |
366 | return iommu_attach_device(domain, dev); | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
0db2e5d1 | 371 | /** |
737c85ca MH |
372 | * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API |
373 | * page flags. | |
0db2e5d1 RM |
374 | * @dir: Direction of DMA transfer |
375 | * @coherent: Is the DMA master cache-coherent? | |
737c85ca | 376 | * @attrs: DMA attributes for the mapping |
0db2e5d1 RM |
377 | * |
378 | * Return: corresponding IOMMU API page protection flags | |
379 | */ | |
06d60728 | 380 | static int dma_info_to_prot(enum dma_data_direction dir, bool coherent, |
737c85ca | 381 | unsigned long attrs) |
0db2e5d1 RM |
382 | { |
383 | int prot = coherent ? IOMMU_CACHE : 0; | |
384 | ||
737c85ca MH |
385 | if (attrs & DMA_ATTR_PRIVILEGED) |
386 | prot |= IOMMU_PRIV; | |
387 | ||
0db2e5d1 RM |
388 | switch (dir) { |
389 | case DMA_BIDIRECTIONAL: | |
390 | return prot | IOMMU_READ | IOMMU_WRITE; | |
391 | case DMA_TO_DEVICE: | |
392 | return prot | IOMMU_READ; | |
393 | case DMA_FROM_DEVICE: | |
394 | return prot | IOMMU_WRITE; | |
395 | default: | |
396 | return 0; | |
397 | } | |
398 | } | |
399 | ||
842fe519 | 400 | static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain, |
bd036d2f | 401 | size_t size, u64 dma_limit, struct device *dev) |
0db2e5d1 | 402 | { |
a44e6657 RM |
403 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
404 | struct iova_domain *iovad = &cookie->iovad; | |
bb65a64c | 405 | unsigned long shift, iova_len, iova = 0; |
0db2e5d1 | 406 | |
a44e6657 RM |
407 | if (cookie->type == IOMMU_DMA_MSI_COOKIE) { |
408 | cookie->msi_iova += size; | |
409 | return cookie->msi_iova - size; | |
410 | } | |
411 | ||
412 | shift = iova_shift(iovad); | |
413 | iova_len = size >> shift; | |
bb65a64c RM |
414 | /* |
415 | * Freeing non-power-of-two-sized allocations back into the IOVA caches | |
416 | * will come back to bite us badly, so we have to waste a bit of space | |
417 | * rounding up anything cacheable to make sure that can't happen. The | |
418 | * order of the unadjusted size will still match upon freeing. | |
419 | */ | |
420 | if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1))) | |
421 | iova_len = roundup_pow_of_two(iova_len); | |
a44e6657 | 422 | |
a7ba70f1 | 423 | dma_limit = min_not_zero(dma_limit, dev->bus_dma_limit); |
03bfdc31 | 424 | |
c987ff0d | 425 | if (domain->geometry.force_aperture) |
bd036d2f | 426 | dma_limit = min(dma_limit, (u64)domain->geometry.aperture_end); |
122fac03 RM |
427 | |
428 | /* Try to get PCI devices a SAC address */ | |
429 | if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev)) | |
538d5b33 TN |
430 | iova = alloc_iova_fast(iovad, iova_len, |
431 | DMA_BIT_MASK(32) >> shift, false); | |
bb65a64c | 432 | |
122fac03 | 433 | if (!iova) |
538d5b33 TN |
434 | iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift, |
435 | true); | |
122fac03 | 436 | |
bb65a64c | 437 | return (dma_addr_t)iova << shift; |
0db2e5d1 RM |
438 | } |
439 | ||
842fe519 RM |
440 | static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie, |
441 | dma_addr_t iova, size_t size) | |
0db2e5d1 | 442 | { |
842fe519 | 443 | struct iova_domain *iovad = &cookie->iovad; |
0db2e5d1 | 444 | |
a44e6657 | 445 | /* The MSI case is only ever cleaning up its most recent allocation */ |
bb65a64c | 446 | if (cookie->type == IOMMU_DMA_MSI_COOKIE) |
a44e6657 | 447 | cookie->msi_iova -= size; |
2da274cd ZL |
448 | else if (cookie->fq_domain) /* non-strict mode */ |
449 | queue_iova(iovad, iova_pfn(iovad, iova), | |
450 | size >> iova_shift(iovad), 0); | |
bb65a64c | 451 | else |
1cc896ed RM |
452 | free_iova_fast(iovad, iova_pfn(iovad, iova), |
453 | size >> iova_shift(iovad)); | |
842fe519 RM |
454 | } |
455 | ||
b61d271e | 456 | static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr, |
842fe519 RM |
457 | size_t size) |
458 | { | |
b61d271e | 459 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
a44e6657 RM |
460 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
461 | struct iova_domain *iovad = &cookie->iovad; | |
842fe519 | 462 | size_t iova_off = iova_offset(iovad, dma_addr); |
a7d20dc1 WD |
463 | struct iommu_iotlb_gather iotlb_gather; |
464 | size_t unmapped; | |
842fe519 RM |
465 | |
466 | dma_addr -= iova_off; | |
467 | size = iova_align(iovad, size + iova_off); | |
a7d20dc1 WD |
468 | iommu_iotlb_gather_init(&iotlb_gather); |
469 | ||
470 | unmapped = iommu_unmap_fast(domain, dma_addr, size, &iotlb_gather); | |
471 | WARN_ON(unmapped != size); | |
842fe519 | 472 | |
2da274cd | 473 | if (!cookie->fq_domain) |
a7d20dc1 | 474 | iommu_tlb_sync(domain, &iotlb_gather); |
a44e6657 | 475 | iommu_dma_free_iova(cookie, dma_addr, size); |
0db2e5d1 RM |
476 | } |
477 | ||
92aec09c | 478 | static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys, |
bd036d2f | 479 | size_t size, int prot, u64 dma_mask) |
92aec09c | 480 | { |
b61d271e | 481 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
92aec09c | 482 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
8af23fad RM |
483 | struct iova_domain *iovad = &cookie->iovad; |
484 | size_t iova_off = iova_offset(iovad, phys); | |
92aec09c CH |
485 | dma_addr_t iova; |
486 | ||
795bbbb9 TM |
487 | if (unlikely(iommu_dma_deferred_attach(dev, domain))) |
488 | return DMA_MAPPING_ERROR; | |
489 | ||
8af23fad | 490 | size = iova_align(iovad, size + iova_off); |
92aec09c | 491 | |
6e235020 | 492 | iova = iommu_dma_alloc_iova(domain, size, dma_mask, dev); |
92aec09c CH |
493 | if (!iova) |
494 | return DMA_MAPPING_ERROR; | |
495 | ||
781ca2de | 496 | if (iommu_map_atomic(domain, iova, phys - iova_off, size, prot)) { |
92aec09c CH |
497 | iommu_dma_free_iova(cookie, iova, size); |
498 | return DMA_MAPPING_ERROR; | |
499 | } | |
500 | return iova + iova_off; | |
501 | } | |
502 | ||
0db2e5d1 RM |
503 | static void __iommu_dma_free_pages(struct page **pages, int count) |
504 | { | |
505 | while (count--) | |
506 | __free_page(pages[count]); | |
507 | kvfree(pages); | |
508 | } | |
509 | ||
c4b17afb GK |
510 | static struct page **__iommu_dma_alloc_pages(struct device *dev, |
511 | unsigned int count, unsigned long order_mask, gfp_t gfp) | |
0db2e5d1 RM |
512 | { |
513 | struct page **pages; | |
c4b17afb | 514 | unsigned int i = 0, nid = dev_to_node(dev); |
3b6b7e19 RM |
515 | |
516 | order_mask &= (2U << MAX_ORDER) - 1; | |
517 | if (!order_mask) | |
518 | return NULL; | |
0db2e5d1 | 519 | |
c4b17afb | 520 | pages = kvzalloc(count * sizeof(*pages), GFP_KERNEL); |
0db2e5d1 RM |
521 | if (!pages) |
522 | return NULL; | |
523 | ||
524 | /* IOMMU can map any pages, so himem can also be used here */ | |
525 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
526 | ||
527 | while (count) { | |
528 | struct page *page = NULL; | |
3b6b7e19 | 529 | unsigned int order_size; |
0db2e5d1 RM |
530 | |
531 | /* | |
532 | * Higher-order allocations are a convenience rather | |
533 | * than a necessity, hence using __GFP_NORETRY until | |
3b6b7e19 | 534 | * falling back to minimum-order allocations. |
0db2e5d1 | 535 | */ |
3b6b7e19 RM |
536 | for (order_mask &= (2U << __fls(count)) - 1; |
537 | order_mask; order_mask &= ~order_size) { | |
538 | unsigned int order = __fls(order_mask); | |
c4b17afb | 539 | gfp_t alloc_flags = gfp; |
3b6b7e19 RM |
540 | |
541 | order_size = 1U << order; | |
c4b17afb GK |
542 | if (order_mask > order_size) |
543 | alloc_flags |= __GFP_NORETRY; | |
544 | page = alloc_pages_node(nid, alloc_flags, order); | |
0db2e5d1 RM |
545 | if (!page) |
546 | continue; | |
3b6b7e19 RM |
547 | if (!order) |
548 | break; | |
549 | if (!PageCompound(page)) { | |
0db2e5d1 RM |
550 | split_page(page, order); |
551 | break; | |
3b6b7e19 RM |
552 | } else if (!split_huge_page(page)) { |
553 | break; | |
0db2e5d1 | 554 | } |
3b6b7e19 | 555 | __free_pages(page, order); |
0db2e5d1 | 556 | } |
0db2e5d1 RM |
557 | if (!page) { |
558 | __iommu_dma_free_pages(pages, i); | |
559 | return NULL; | |
560 | } | |
3b6b7e19 RM |
561 | count -= order_size; |
562 | while (order_size--) | |
0db2e5d1 RM |
563 | pages[i++] = page++; |
564 | } | |
565 | return pages; | |
566 | } | |
567 | ||
0db2e5d1 | 568 | /** |
21b95aaf | 569 | * iommu_dma_alloc_remap - Allocate and map a buffer contiguous in IOVA space |
0db2e5d1 RM |
570 | * @dev: Device to allocate memory for. Must be a real device |
571 | * attached to an iommu_dma_domain | |
572 | * @size: Size of buffer in bytes | |
21b95aaf | 573 | * @dma_handle: Out argument for allocated DMA handle |
0db2e5d1 | 574 | * @gfp: Allocation flags |
3b6b7e19 | 575 | * @attrs: DMA attributes for this allocation |
0db2e5d1 RM |
576 | * |
577 | * If @size is less than PAGE_SIZE, then a full CPU page will be allocated, | |
578 | * but an IOMMU which supports smaller pages might not map the whole thing. | |
579 | * | |
21b95aaf | 580 | * Return: Mapped virtual address, or NULL on failure. |
0db2e5d1 | 581 | */ |
21b95aaf CH |
582 | static void *iommu_dma_alloc_remap(struct device *dev, size_t size, |
583 | dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) | |
0db2e5d1 | 584 | { |
43c5bf11 | 585 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
842fe519 RM |
586 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
587 | struct iova_domain *iovad = &cookie->iovad; | |
21b95aaf CH |
588 | bool coherent = dev_is_dma_coherent(dev); |
589 | int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs); | |
33dcb37c | 590 | pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs); |
21b95aaf | 591 | unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap; |
0db2e5d1 RM |
592 | struct page **pages; |
593 | struct sg_table sgt; | |
842fe519 | 594 | dma_addr_t iova; |
21b95aaf | 595 | void *vaddr; |
0db2e5d1 | 596 | |
21b95aaf | 597 | *dma_handle = DMA_MAPPING_ERROR; |
0db2e5d1 | 598 | |
795bbbb9 TM |
599 | if (unlikely(iommu_dma_deferred_attach(dev, domain))) |
600 | return NULL; | |
601 | ||
3b6b7e19 RM |
602 | min_size = alloc_sizes & -alloc_sizes; |
603 | if (min_size < PAGE_SIZE) { | |
604 | min_size = PAGE_SIZE; | |
605 | alloc_sizes |= PAGE_SIZE; | |
606 | } else { | |
607 | size = ALIGN(size, min_size); | |
608 | } | |
00085f1e | 609 | if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES) |
3b6b7e19 RM |
610 | alloc_sizes = min_size; |
611 | ||
612 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c4b17afb GK |
613 | pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT, |
614 | gfp); | |
0db2e5d1 RM |
615 | if (!pages) |
616 | return NULL; | |
617 | ||
842fe519 RM |
618 | size = iova_align(iovad, size); |
619 | iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev); | |
0db2e5d1 RM |
620 | if (!iova) |
621 | goto out_free_pages; | |
622 | ||
0db2e5d1 RM |
623 | if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL)) |
624 | goto out_free_iova; | |
625 | ||
21b95aaf | 626 | if (!(ioprot & IOMMU_CACHE)) { |
23f88e0a CH |
627 | struct scatterlist *sg; |
628 | int i; | |
629 | ||
630 | for_each_sg(sgt.sgl, sg, sgt.orig_nents, i) | |
631 | arch_dma_prep_coherent(sg_page(sg), sg->length); | |
0db2e5d1 RM |
632 | } |
633 | ||
781ca2de | 634 | if (iommu_map_sg_atomic(domain, iova, sgt.sgl, sgt.orig_nents, ioprot) |
0db2e5d1 RM |
635 | < size) |
636 | goto out_free_sg; | |
637 | ||
51231740 | 638 | vaddr = dma_common_pages_remap(pages, size, prot, |
21b95aaf CH |
639 | __builtin_return_address(0)); |
640 | if (!vaddr) | |
641 | goto out_unmap; | |
642 | ||
643 | *dma_handle = iova; | |
0db2e5d1 | 644 | sg_free_table(&sgt); |
21b95aaf | 645 | return vaddr; |
0db2e5d1 | 646 | |
21b95aaf CH |
647 | out_unmap: |
648 | __iommu_dma_unmap(dev, iova, size); | |
0db2e5d1 RM |
649 | out_free_sg: |
650 | sg_free_table(&sgt); | |
651 | out_free_iova: | |
842fe519 | 652 | iommu_dma_free_iova(cookie, iova, size); |
0db2e5d1 RM |
653 | out_free_pages: |
654 | __iommu_dma_free_pages(pages, count); | |
655 | return NULL; | |
656 | } | |
657 | ||
658 | /** | |
06d60728 CH |
659 | * __iommu_dma_mmap - Map a buffer into provided user VMA |
660 | * @pages: Array representing buffer from __iommu_dma_alloc() | |
0db2e5d1 RM |
661 | * @size: Size of buffer in bytes |
662 | * @vma: VMA describing requested userspace mapping | |
663 | * | |
664 | * Maps the pages of the buffer in @pages into @vma. The caller is responsible | |
665 | * for verifying the correct size and protection of @vma beforehand. | |
666 | */ | |
06d60728 CH |
667 | static int __iommu_dma_mmap(struct page **pages, size_t size, |
668 | struct vm_area_struct *vma) | |
0db2e5d1 | 669 | { |
b0d0084f | 670 | return vm_map_pages(vma, pages, PAGE_ALIGN(size) >> PAGE_SHIFT); |
0db2e5d1 RM |
671 | } |
672 | ||
06d60728 CH |
673 | static void iommu_dma_sync_single_for_cpu(struct device *dev, |
674 | dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) | |
0db2e5d1 | 675 | { |
06d60728 | 676 | phys_addr_t phys; |
0db2e5d1 | 677 | |
06d60728 CH |
678 | if (dev_is_dma_coherent(dev)) |
679 | return; | |
1cc896ed | 680 | |
06d60728 | 681 | phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle); |
56e35f9c | 682 | arch_sync_dma_for_cpu(phys, size, dir); |
0db2e5d1 | 683 | } |
0db2e5d1 | 684 | |
06d60728 CH |
685 | static void iommu_dma_sync_single_for_device(struct device *dev, |
686 | dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) | |
0db2e5d1 | 687 | { |
06d60728 | 688 | phys_addr_t phys; |
0db2e5d1 | 689 | |
06d60728 CH |
690 | if (dev_is_dma_coherent(dev)) |
691 | return; | |
1cc896ed | 692 | |
06d60728 | 693 | phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle); |
56e35f9c | 694 | arch_sync_dma_for_device(phys, size, dir); |
06d60728 | 695 | } |
0db2e5d1 | 696 | |
06d60728 CH |
697 | static void iommu_dma_sync_sg_for_cpu(struct device *dev, |
698 | struct scatterlist *sgl, int nelems, | |
699 | enum dma_data_direction dir) | |
700 | { | |
701 | struct scatterlist *sg; | |
702 | int i; | |
703 | ||
704 | if (dev_is_dma_coherent(dev)) | |
705 | return; | |
706 | ||
707 | for_each_sg(sgl, sg, nelems, i) | |
56e35f9c | 708 | arch_sync_dma_for_cpu(sg_phys(sg), sg->length, dir); |
06d60728 CH |
709 | } |
710 | ||
711 | static void iommu_dma_sync_sg_for_device(struct device *dev, | |
712 | struct scatterlist *sgl, int nelems, | |
713 | enum dma_data_direction dir) | |
714 | { | |
715 | struct scatterlist *sg; | |
716 | int i; | |
717 | ||
718 | if (dev_is_dma_coherent(dev)) | |
719 | return; | |
720 | ||
721 | for_each_sg(sgl, sg, nelems, i) | |
56e35f9c | 722 | arch_sync_dma_for_device(sg_phys(sg), sg->length, dir); |
0db2e5d1 RM |
723 | } |
724 | ||
06d60728 CH |
725 | static dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page, |
726 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
727 | unsigned long attrs) | |
51f8cc9e | 728 | { |
06d60728 CH |
729 | phys_addr_t phys = page_to_phys(page) + offset; |
730 | bool coherent = dev_is_dma_coherent(dev); | |
b61d271e | 731 | int prot = dma_info_to_prot(dir, coherent, attrs); |
06d60728 CH |
732 | dma_addr_t dma_handle; |
733 | ||
6e235020 | 734 | dma_handle = __iommu_dma_map(dev, phys, size, prot, dma_get_mask(dev)); |
06d60728 CH |
735 | if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
736 | dma_handle != DMA_MAPPING_ERROR) | |
56e35f9c | 737 | arch_sync_dma_for_device(phys, size, dir); |
06d60728 | 738 | return dma_handle; |
51f8cc9e RM |
739 | } |
740 | ||
06d60728 CH |
741 | static void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle, |
742 | size_t size, enum dma_data_direction dir, unsigned long attrs) | |
0db2e5d1 | 743 | { |
06d60728 CH |
744 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
745 | iommu_dma_sync_single_for_cpu(dev, dma_handle, size, dir); | |
b61d271e | 746 | __iommu_dma_unmap(dev, dma_handle, size); |
0db2e5d1 RM |
747 | } |
748 | ||
749 | /* | |
750 | * Prepare a successfully-mapped scatterlist to give back to the caller. | |
809eac54 RM |
751 | * |
752 | * At this point the segments are already laid out by iommu_dma_map_sg() to | |
753 | * avoid individually crossing any boundaries, so we merely need to check a | |
754 | * segment's start address to avoid concatenating across one. | |
0db2e5d1 RM |
755 | */ |
756 | static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents, | |
757 | dma_addr_t dma_addr) | |
758 | { | |
809eac54 RM |
759 | struct scatterlist *s, *cur = sg; |
760 | unsigned long seg_mask = dma_get_seg_boundary(dev); | |
761 | unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev); | |
762 | int i, count = 0; | |
0db2e5d1 RM |
763 | |
764 | for_each_sg(sg, s, nents, i) { | |
809eac54 RM |
765 | /* Restore this segment's original unaligned fields first */ |
766 | unsigned int s_iova_off = sg_dma_address(s); | |
0db2e5d1 | 767 | unsigned int s_length = sg_dma_len(s); |
809eac54 | 768 | unsigned int s_iova_len = s->length; |
0db2e5d1 | 769 | |
809eac54 | 770 | s->offset += s_iova_off; |
0db2e5d1 | 771 | s->length = s_length; |
cad34be7 | 772 | sg_dma_address(s) = DMA_MAPPING_ERROR; |
809eac54 RM |
773 | sg_dma_len(s) = 0; |
774 | ||
775 | /* | |
776 | * Now fill in the real DMA data. If... | |
777 | * - there is a valid output segment to append to | |
778 | * - and this segment starts on an IOVA page boundary | |
779 | * - but doesn't fall at a segment boundary | |
780 | * - and wouldn't make the resulting output segment too long | |
781 | */ | |
782 | if (cur_len && !s_iova_off && (dma_addr & seg_mask) && | |
ab2cbeb0 | 783 | (max_len - cur_len >= s_length)) { |
809eac54 RM |
784 | /* ...then concatenate it with the previous one */ |
785 | cur_len += s_length; | |
786 | } else { | |
787 | /* Otherwise start the next output segment */ | |
788 | if (i > 0) | |
789 | cur = sg_next(cur); | |
790 | cur_len = s_length; | |
791 | count++; | |
792 | ||
793 | sg_dma_address(cur) = dma_addr + s_iova_off; | |
794 | } | |
795 | ||
796 | sg_dma_len(cur) = cur_len; | |
797 | dma_addr += s_iova_len; | |
798 | ||
799 | if (s_length + s_iova_off < s_iova_len) | |
800 | cur_len = 0; | |
0db2e5d1 | 801 | } |
809eac54 | 802 | return count; |
0db2e5d1 RM |
803 | } |
804 | ||
805 | /* | |
806 | * If mapping failed, then just restore the original list, | |
807 | * but making sure the DMA fields are invalidated. | |
808 | */ | |
809 | static void __invalidate_sg(struct scatterlist *sg, int nents) | |
810 | { | |
811 | struct scatterlist *s; | |
812 | int i; | |
813 | ||
814 | for_each_sg(sg, s, nents, i) { | |
cad34be7 | 815 | if (sg_dma_address(s) != DMA_MAPPING_ERROR) |
07b48ac4 | 816 | s->offset += sg_dma_address(s); |
0db2e5d1 RM |
817 | if (sg_dma_len(s)) |
818 | s->length = sg_dma_len(s); | |
cad34be7 | 819 | sg_dma_address(s) = DMA_MAPPING_ERROR; |
0db2e5d1 RM |
820 | sg_dma_len(s) = 0; |
821 | } | |
822 | } | |
823 | ||
824 | /* | |
825 | * The DMA API client is passing in a scatterlist which could describe | |
826 | * any old buffer layout, but the IOMMU API requires everything to be | |
827 | * aligned to IOMMU pages. Hence the need for this complicated bit of | |
828 | * impedance-matching, to be able to hand off a suitably-aligned list, | |
829 | * but still preserve the original offsets and sizes for the caller. | |
830 | */ | |
06d60728 CH |
831 | static int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, |
832 | int nents, enum dma_data_direction dir, unsigned long attrs) | |
0db2e5d1 | 833 | { |
43c5bf11 | 834 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
842fe519 RM |
835 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
836 | struct iova_domain *iovad = &cookie->iovad; | |
0db2e5d1 | 837 | struct scatterlist *s, *prev = NULL; |
06d60728 | 838 | int prot = dma_info_to_prot(dir, dev_is_dma_coherent(dev), attrs); |
842fe519 | 839 | dma_addr_t iova; |
0db2e5d1 | 840 | size_t iova_len = 0; |
809eac54 | 841 | unsigned long mask = dma_get_seg_boundary(dev); |
0db2e5d1 RM |
842 | int i; |
843 | ||
795bbbb9 TM |
844 | if (unlikely(iommu_dma_deferred_attach(dev, domain))) |
845 | return 0; | |
846 | ||
06d60728 CH |
847 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
848 | iommu_dma_sync_sg_for_device(dev, sg, nents, dir); | |
849 | ||
0db2e5d1 RM |
850 | /* |
851 | * Work out how much IOVA space we need, and align the segments to | |
852 | * IOVA granules for the IOMMU driver to handle. With some clever | |
853 | * trickery we can modify the list in-place, but reversibly, by | |
809eac54 | 854 | * stashing the unaligned parts in the as-yet-unused DMA fields. |
0db2e5d1 RM |
855 | */ |
856 | for_each_sg(sg, s, nents, i) { | |
809eac54 | 857 | size_t s_iova_off = iova_offset(iovad, s->offset); |
0db2e5d1 | 858 | size_t s_length = s->length; |
809eac54 | 859 | size_t pad_len = (mask - iova_len + 1) & mask; |
0db2e5d1 | 860 | |
809eac54 | 861 | sg_dma_address(s) = s_iova_off; |
0db2e5d1 | 862 | sg_dma_len(s) = s_length; |
809eac54 RM |
863 | s->offset -= s_iova_off; |
864 | s_length = iova_align(iovad, s_length + s_iova_off); | |
0db2e5d1 RM |
865 | s->length = s_length; |
866 | ||
867 | /* | |
809eac54 RM |
868 | * Due to the alignment of our single IOVA allocation, we can |
869 | * depend on these assumptions about the segment boundary mask: | |
870 | * - If mask size >= IOVA size, then the IOVA range cannot | |
871 | * possibly fall across a boundary, so we don't care. | |
872 | * - If mask size < IOVA size, then the IOVA range must start | |
873 | * exactly on a boundary, therefore we can lay things out | |
874 | * based purely on segment lengths without needing to know | |
875 | * the actual addresses beforehand. | |
876 | * - The mask must be a power of 2, so pad_len == 0 if | |
877 | * iova_len == 0, thus we cannot dereference prev the first | |
878 | * time through here (i.e. before it has a meaningful value). | |
0db2e5d1 | 879 | */ |
809eac54 | 880 | if (pad_len && pad_len < s_length - 1) { |
0db2e5d1 RM |
881 | prev->length += pad_len; |
882 | iova_len += pad_len; | |
883 | } | |
884 | ||
885 | iova_len += s_length; | |
886 | prev = s; | |
887 | } | |
888 | ||
842fe519 | 889 | iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev); |
0db2e5d1 RM |
890 | if (!iova) |
891 | goto out_restore_sg; | |
892 | ||
893 | /* | |
894 | * We'll leave any physical concatenation to the IOMMU driver's | |
895 | * implementation - it knows better than we do. | |
896 | */ | |
781ca2de | 897 | if (iommu_map_sg_atomic(domain, iova, sg, nents, prot) < iova_len) |
0db2e5d1 RM |
898 | goto out_free_iova; |
899 | ||
842fe519 | 900 | return __finalise_sg(dev, sg, nents, iova); |
0db2e5d1 RM |
901 | |
902 | out_free_iova: | |
842fe519 | 903 | iommu_dma_free_iova(cookie, iova, iova_len); |
0db2e5d1 RM |
904 | out_restore_sg: |
905 | __invalidate_sg(sg, nents); | |
906 | return 0; | |
907 | } | |
908 | ||
06d60728 CH |
909 | static void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, |
910 | int nents, enum dma_data_direction dir, unsigned long attrs) | |
0db2e5d1 | 911 | { |
842fe519 RM |
912 | dma_addr_t start, end; |
913 | struct scatterlist *tmp; | |
914 | int i; | |
06d60728 | 915 | |
1b961423 | 916 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
06d60728 CH |
917 | iommu_dma_sync_sg_for_cpu(dev, sg, nents, dir); |
918 | ||
0db2e5d1 RM |
919 | /* |
920 | * The scatterlist segments are mapped into a single | |
921 | * contiguous IOVA allocation, so this is incredibly easy. | |
922 | */ | |
842fe519 RM |
923 | start = sg_dma_address(sg); |
924 | for_each_sg(sg_next(sg), tmp, nents - 1, i) { | |
925 | if (sg_dma_len(tmp) == 0) | |
926 | break; | |
927 | sg = tmp; | |
928 | } | |
929 | end = sg_dma_address(sg) + sg_dma_len(sg); | |
b61d271e | 930 | __iommu_dma_unmap(dev, start, end - start); |
0db2e5d1 RM |
931 | } |
932 | ||
06d60728 | 933 | static dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys, |
51f8cc9e RM |
934 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
935 | { | |
936 | return __iommu_dma_map(dev, phys, size, | |
6e235020 TM |
937 | dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO, |
938 | dma_get_mask(dev)); | |
51f8cc9e RM |
939 | } |
940 | ||
06d60728 | 941 | static void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, |
51f8cc9e RM |
942 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
943 | { | |
b61d271e | 944 | __iommu_dma_unmap(dev, handle, size); |
51f8cc9e RM |
945 | } |
946 | ||
8553f6e6 | 947 | static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr) |
bcf4b9c4 RM |
948 | { |
949 | size_t alloc_size = PAGE_ALIGN(size); | |
950 | int count = alloc_size >> PAGE_SHIFT; | |
951 | struct page *page = NULL, **pages = NULL; | |
952 | ||
bcf4b9c4 | 953 | /* Non-coherent atomic allocation? Easy */ |
e6475eb0 CH |
954 | if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && |
955 | dma_free_from_pool(cpu_addr, alloc_size)) | |
bcf4b9c4 RM |
956 | return; |
957 | ||
e6475eb0 | 958 | if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) { |
bcf4b9c4 RM |
959 | /* |
960 | * If it the address is remapped, then it's either non-coherent | |
961 | * or highmem CMA, or an iommu_dma_alloc_remap() construction. | |
962 | */ | |
5cf45379 | 963 | pages = dma_common_find_pages(cpu_addr); |
bcf4b9c4 RM |
964 | if (!pages) |
965 | page = vmalloc_to_page(cpu_addr); | |
51231740 | 966 | dma_common_free_remap(cpu_addr, alloc_size); |
bcf4b9c4 RM |
967 | } else { |
968 | /* Lowmem means a coherent atomic or CMA allocation */ | |
969 | page = virt_to_page(cpu_addr); | |
970 | } | |
971 | ||
972 | if (pages) | |
973 | __iommu_dma_free_pages(pages, count); | |
591fcf3b NC |
974 | if (page) |
975 | dma_free_contiguous(dev, page, alloc_size); | |
bcf4b9c4 RM |
976 | } |
977 | ||
8553f6e6 RM |
978 | static void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr, |
979 | dma_addr_t handle, unsigned long attrs) | |
980 | { | |
981 | __iommu_dma_unmap(dev, handle, size); | |
982 | __iommu_dma_free(dev, size, cpu_addr); | |
983 | } | |
984 | ||
ee1ef05d CH |
985 | static void *iommu_dma_alloc_pages(struct device *dev, size_t size, |
986 | struct page **pagep, gfp_t gfp, unsigned long attrs) | |
06d60728 CH |
987 | { |
988 | bool coherent = dev_is_dma_coherent(dev); | |
9ad5d6ed | 989 | size_t alloc_size = PAGE_ALIGN(size); |
90ae409f | 990 | int node = dev_to_node(dev); |
9a4ab94a | 991 | struct page *page = NULL; |
9ad5d6ed | 992 | void *cpu_addr; |
06d60728 | 993 | |
591fcf3b | 994 | page = dma_alloc_contiguous(dev, alloc_size, gfp); |
90ae409f CH |
995 | if (!page) |
996 | page = alloc_pages_node(node, gfp, get_order(alloc_size)); | |
072bebc0 RM |
997 | if (!page) |
998 | return NULL; | |
999 | ||
e6475eb0 | 1000 | if (IS_ENABLED(CONFIG_DMA_REMAP) && (!coherent || PageHighMem(page))) { |
33dcb37c | 1001 | pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs); |
072bebc0 | 1002 | |
9ad5d6ed | 1003 | cpu_addr = dma_common_contiguous_remap(page, alloc_size, |
51231740 | 1004 | prot, __builtin_return_address(0)); |
9ad5d6ed | 1005 | if (!cpu_addr) |
ee1ef05d | 1006 | goto out_free_pages; |
8680aa5a RM |
1007 | |
1008 | if (!coherent) | |
9ad5d6ed | 1009 | arch_dma_prep_coherent(page, size); |
8680aa5a | 1010 | } else { |
9ad5d6ed | 1011 | cpu_addr = page_address(page); |
8680aa5a | 1012 | } |
ee1ef05d CH |
1013 | |
1014 | *pagep = page; | |
9ad5d6ed RM |
1015 | memset(cpu_addr, 0, alloc_size); |
1016 | return cpu_addr; | |
072bebc0 | 1017 | out_free_pages: |
591fcf3b | 1018 | dma_free_contiguous(dev, page, alloc_size); |
072bebc0 | 1019 | return NULL; |
06d60728 CH |
1020 | } |
1021 | ||
ee1ef05d CH |
1022 | static void *iommu_dma_alloc(struct device *dev, size_t size, |
1023 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) | |
1024 | { | |
1025 | bool coherent = dev_is_dma_coherent(dev); | |
1026 | int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs); | |
1027 | struct page *page = NULL; | |
1028 | void *cpu_addr; | |
1029 | ||
1030 | gfp |= __GFP_ZERO; | |
1031 | ||
e6475eb0 | 1032 | if (IS_ENABLED(CONFIG_DMA_REMAP) && gfpflags_allow_blocking(gfp) && |
ee1ef05d CH |
1033 | !(attrs & DMA_ATTR_FORCE_CONTIGUOUS)) |
1034 | return iommu_dma_alloc_remap(dev, size, handle, gfp, attrs); | |
1035 | ||
e6475eb0 CH |
1036 | if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && |
1037 | !gfpflags_allow_blocking(gfp) && !coherent) | |
ee1ef05d CH |
1038 | cpu_addr = dma_alloc_from_pool(PAGE_ALIGN(size), &page, gfp); |
1039 | else | |
1040 | cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs); | |
1041 | if (!cpu_addr) | |
1042 | return NULL; | |
1043 | ||
6e235020 TM |
1044 | *handle = __iommu_dma_map(dev, page_to_phys(page), size, ioprot, |
1045 | dev->coherent_dma_mask); | |
ee1ef05d CH |
1046 | if (*handle == DMA_MAPPING_ERROR) { |
1047 | __iommu_dma_free(dev, size, cpu_addr); | |
1048 | return NULL; | |
1049 | } | |
1050 | ||
1051 | return cpu_addr; | |
1052 | } | |
1053 | ||
06d60728 CH |
1054 | static int iommu_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
1055 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1056 | unsigned long attrs) | |
1057 | { | |
1058 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
efd9f10b | 1059 | unsigned long pfn, off = vma->vm_pgoff; |
06d60728 CH |
1060 | int ret; |
1061 | ||
33dcb37c | 1062 | vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs); |
06d60728 CH |
1063 | |
1064 | if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) | |
1065 | return ret; | |
1066 | ||
1067 | if (off >= nr_pages || vma_pages(vma) > nr_pages - off) | |
1068 | return -ENXIO; | |
1069 | ||
e6475eb0 | 1070 | if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) { |
5cf45379 | 1071 | struct page **pages = dma_common_find_pages(cpu_addr); |
06d60728 | 1072 | |
efd9f10b CH |
1073 | if (pages) |
1074 | return __iommu_dma_mmap(pages, size, vma); | |
1075 | pfn = vmalloc_to_pfn(cpu_addr); | |
1076 | } else { | |
1077 | pfn = page_to_pfn(virt_to_page(cpu_addr)); | |
06d60728 CH |
1078 | } |
1079 | ||
efd9f10b CH |
1080 | return remap_pfn_range(vma, vma->vm_start, pfn + off, |
1081 | vma->vm_end - vma->vm_start, | |
1082 | vma->vm_page_prot); | |
06d60728 CH |
1083 | } |
1084 | ||
06d60728 CH |
1085 | static int iommu_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
1086 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1087 | unsigned long attrs) | |
1088 | { | |
3fb3378b CH |
1089 | struct page *page; |
1090 | int ret; | |
06d60728 | 1091 | |
e6475eb0 | 1092 | if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) { |
5cf45379 | 1093 | struct page **pages = dma_common_find_pages(cpu_addr); |
06d60728 | 1094 | |
3fb3378b CH |
1095 | if (pages) { |
1096 | return sg_alloc_table_from_pages(sgt, pages, | |
1097 | PAGE_ALIGN(size) >> PAGE_SHIFT, | |
1098 | 0, size, GFP_KERNEL); | |
1099 | } | |
1100 | ||
1101 | page = vmalloc_to_page(cpu_addr); | |
1102 | } else { | |
1103 | page = virt_to_page(cpu_addr); | |
06d60728 CH |
1104 | } |
1105 | ||
3fb3378b CH |
1106 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); |
1107 | if (!ret) | |
1108 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
1109 | return ret; | |
06d60728 CH |
1110 | } |
1111 | ||
158a6d3c YS |
1112 | static unsigned long iommu_dma_get_merge_boundary(struct device *dev) |
1113 | { | |
1114 | struct iommu_domain *domain = iommu_get_dma_domain(dev); | |
1115 | ||
1116 | return (1UL << __ffs(domain->pgsize_bitmap)) - 1; | |
1117 | } | |
1118 | ||
06d60728 CH |
1119 | static const struct dma_map_ops iommu_dma_ops = { |
1120 | .alloc = iommu_dma_alloc, | |
1121 | .free = iommu_dma_free, | |
1122 | .mmap = iommu_dma_mmap, | |
1123 | .get_sgtable = iommu_dma_get_sgtable, | |
1124 | .map_page = iommu_dma_map_page, | |
1125 | .unmap_page = iommu_dma_unmap_page, | |
1126 | .map_sg = iommu_dma_map_sg, | |
1127 | .unmap_sg = iommu_dma_unmap_sg, | |
1128 | .sync_single_for_cpu = iommu_dma_sync_single_for_cpu, | |
1129 | .sync_single_for_device = iommu_dma_sync_single_for_device, | |
1130 | .sync_sg_for_cpu = iommu_dma_sync_sg_for_cpu, | |
1131 | .sync_sg_for_device = iommu_dma_sync_sg_for_device, | |
1132 | .map_resource = iommu_dma_map_resource, | |
1133 | .unmap_resource = iommu_dma_unmap_resource, | |
158a6d3c | 1134 | .get_merge_boundary = iommu_dma_get_merge_boundary, |
06d60728 CH |
1135 | }; |
1136 | ||
1137 | /* | |
1138 | * The IOMMU core code allocates the default DMA domain, which the underlying | |
1139 | * IOMMU driver needs to support via the dma-iommu layer. | |
1140 | */ | |
1141 | void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size) | |
1142 | { | |
1143 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); | |
1144 | ||
1145 | if (!domain) | |
1146 | goto out_err; | |
1147 | ||
1148 | /* | |
1149 | * The IOMMU core code allocates the default DMA domain, which the | |
1150 | * underlying IOMMU driver needs to support via the dma-iommu layer. | |
1151 | */ | |
1152 | if (domain->type == IOMMU_DOMAIN_DMA) { | |
1153 | if (iommu_dma_init_domain(domain, dma_base, size, dev)) | |
1154 | goto out_err; | |
1155 | dev->dma_ops = &iommu_dma_ops; | |
1156 | } | |
1157 | ||
1158 | return; | |
1159 | out_err: | |
1160 | pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n", | |
1161 | dev_name(dev)); | |
51f8cc9e RM |
1162 | } |
1163 | ||
44bb7e24 RM |
1164 | static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev, |
1165 | phys_addr_t msi_addr, struct iommu_domain *domain) | |
1166 | { | |
1167 | struct iommu_dma_cookie *cookie = domain->iova_cookie; | |
1168 | struct iommu_dma_msi_page *msi_page; | |
842fe519 | 1169 | dma_addr_t iova; |
44bb7e24 | 1170 | int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; |
fdbe574e | 1171 | size_t size = cookie_msi_granule(cookie); |
44bb7e24 | 1172 | |
fdbe574e | 1173 | msi_addr &= ~(phys_addr_t)(size - 1); |
44bb7e24 RM |
1174 | list_for_each_entry(msi_page, &cookie->msi_page_list, list) |
1175 | if (msi_page->phys == msi_addr) | |
1176 | return msi_page; | |
1177 | ||
c1864790 | 1178 | msi_page = kzalloc(sizeof(*msi_page), GFP_KERNEL); |
44bb7e24 RM |
1179 | if (!msi_page) |
1180 | return NULL; | |
1181 | ||
8af23fad RM |
1182 | iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev); |
1183 | if (!iova) | |
a44e6657 | 1184 | goto out_free_page; |
44bb7e24 | 1185 | |
8af23fad RM |
1186 | if (iommu_map(domain, iova, msi_addr, size, prot)) |
1187 | goto out_free_iova; | |
1188 | ||
44bb7e24 | 1189 | INIT_LIST_HEAD(&msi_page->list); |
a44e6657 RM |
1190 | msi_page->phys = msi_addr; |
1191 | msi_page->iova = iova; | |
44bb7e24 RM |
1192 | list_add(&msi_page->list, &cookie->msi_page_list); |
1193 | return msi_page; | |
1194 | ||
8af23fad RM |
1195 | out_free_iova: |
1196 | iommu_dma_free_iova(cookie, iova, size); | |
44bb7e24 RM |
1197 | out_free_page: |
1198 | kfree(msi_page); | |
1199 | return NULL; | |
1200 | } | |
1201 | ||
ece6e6f0 | 1202 | int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) |
44bb7e24 | 1203 | { |
ece6e6f0 | 1204 | struct device *dev = msi_desc_to_dev(desc); |
44bb7e24 | 1205 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); |
44bb7e24 | 1206 | struct iommu_dma_msi_page *msi_page; |
c1864790 | 1207 | static DEFINE_MUTEX(msi_prepare_lock); /* see below */ |
44bb7e24 | 1208 | |
ece6e6f0 JG |
1209 | if (!domain || !domain->iova_cookie) { |
1210 | desc->iommu_cookie = NULL; | |
1211 | return 0; | |
1212 | } | |
44bb7e24 | 1213 | |
44bb7e24 | 1214 | /* |
c1864790 RM |
1215 | * In fact the whole prepare operation should already be serialised by |
1216 | * irq_domain_mutex further up the callchain, but that's pretty subtle | |
1217 | * on its own, so consider this locking as failsafe documentation... | |
44bb7e24 | 1218 | */ |
c1864790 | 1219 | mutex_lock(&msi_prepare_lock); |
44bb7e24 | 1220 | msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain); |
c1864790 | 1221 | mutex_unlock(&msi_prepare_lock); |
44bb7e24 | 1222 | |
ece6e6f0 JG |
1223 | msi_desc_set_iommu_cookie(desc, msi_page); |
1224 | ||
1225 | if (!msi_page) | |
1226 | return -ENOMEM; | |
1227 | return 0; | |
1228 | } | |
1229 | ||
1230 | void iommu_dma_compose_msi_msg(struct msi_desc *desc, | |
1231 | struct msi_msg *msg) | |
1232 | { | |
1233 | struct device *dev = msi_desc_to_dev(desc); | |
1234 | const struct iommu_domain *domain = iommu_get_domain_for_dev(dev); | |
1235 | const struct iommu_dma_msi_page *msi_page; | |
1236 | ||
1237 | msi_page = msi_desc_get_iommu_cookie(desc); | |
1238 | ||
1239 | if (!domain || !domain->iova_cookie || WARN_ON(!msi_page)) | |
1240 | return; | |
1241 | ||
1242 | msg->address_hi = upper_32_bits(msi_page->iova); | |
1243 | msg->address_lo &= cookie_msi_granule(domain->iova_cookie) - 1; | |
1244 | msg->address_lo += lower_32_bits(msi_page->iova); | |
44bb7e24 | 1245 | } |
06d60728 CH |
1246 | |
1247 | static int iommu_dma_init(void) | |
1248 | { | |
1249 | return iova_cache_get(); | |
44bb7e24 | 1250 | } |
06d60728 | 1251 | arch_initcall(iommu_dma_init); |