Commit | Line | Data |
---|---|---|
0db2e5d1 RM |
1 | /* |
2 | * A fairly generic DMA-API to IOMMU-API glue layer. | |
3 | * | |
4 | * Copyright (C) 2014-2015 ARM Ltd. | |
5 | * | |
6 | * based in part on arch/arm/mm/dma-mapping.c: | |
7 | * Copyright (C) 2000-2004 Russell King | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
f51dc892 | 22 | #include <linux/acpi_iort.h> |
0db2e5d1 | 23 | #include <linux/device.h> |
06d60728 | 24 | #include <linux/dma-contiguous.h> |
0db2e5d1 | 25 | #include <linux/dma-iommu.h> |
af751d43 | 26 | #include <linux/dma-noncoherent.h> |
5b11e9cd | 27 | #include <linux/gfp.h> |
0db2e5d1 RM |
28 | #include <linux/huge_mm.h> |
29 | #include <linux/iommu.h> | |
30 | #include <linux/iova.h> | |
44bb7e24 | 31 | #include <linux/irq.h> |
0db2e5d1 | 32 | #include <linux/mm.h> |
fade1ec0 | 33 | #include <linux/pci.h> |
5b11e9cd RM |
34 | #include <linux/scatterlist.h> |
35 | #include <linux/vmalloc.h> | |
0db2e5d1 | 36 | |
44bb7e24 RM |
37 | struct iommu_dma_msi_page { |
38 | struct list_head list; | |
39 | dma_addr_t iova; | |
40 | phys_addr_t phys; | |
41 | }; | |
42 | ||
fdbe574e RM |
43 | enum iommu_dma_cookie_type { |
44 | IOMMU_DMA_IOVA_COOKIE, | |
45 | IOMMU_DMA_MSI_COOKIE, | |
46 | }; | |
47 | ||
44bb7e24 | 48 | struct iommu_dma_cookie { |
fdbe574e RM |
49 | enum iommu_dma_cookie_type type; |
50 | union { | |
51 | /* Full allocator for IOMMU_DMA_IOVA_COOKIE */ | |
52 | struct iova_domain iovad; | |
53 | /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */ | |
54 | dma_addr_t msi_iova; | |
55 | }; | |
56 | struct list_head msi_page_list; | |
57 | spinlock_t msi_lock; | |
2da274cd ZL |
58 | |
59 | /* Domain for flush queue callback; NULL if flush queue not in use */ | |
60 | struct iommu_domain *fq_domain; | |
44bb7e24 RM |
61 | }; |
62 | ||
fdbe574e RM |
63 | static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie) |
64 | { | |
65 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE) | |
66 | return cookie->iovad.granule; | |
67 | return PAGE_SIZE; | |
68 | } | |
69 | ||
fdbe574e RM |
70 | static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type) |
71 | { | |
72 | struct iommu_dma_cookie *cookie; | |
73 | ||
74 | cookie = kzalloc(sizeof(*cookie), GFP_KERNEL); | |
75 | if (cookie) { | |
76 | spin_lock_init(&cookie->msi_lock); | |
77 | INIT_LIST_HEAD(&cookie->msi_page_list); | |
78 | cookie->type = type; | |
79 | } | |
80 | return cookie; | |
44bb7e24 RM |
81 | } |
82 | ||
0db2e5d1 RM |
83 | /** |
84 | * iommu_get_dma_cookie - Acquire DMA-API resources for a domain | |
85 | * @domain: IOMMU domain to prepare for DMA-API usage | |
86 | * | |
87 | * IOMMU drivers should normally call this from their domain_alloc | |
88 | * callback when domain->type == IOMMU_DOMAIN_DMA. | |
89 | */ | |
90 | int iommu_get_dma_cookie(struct iommu_domain *domain) | |
fdbe574e RM |
91 | { |
92 | if (domain->iova_cookie) | |
93 | return -EEXIST; | |
94 | ||
95 | domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE); | |
96 | if (!domain->iova_cookie) | |
97 | return -ENOMEM; | |
98 | ||
99 | return 0; | |
100 | } | |
101 | EXPORT_SYMBOL(iommu_get_dma_cookie); | |
102 | ||
103 | /** | |
104 | * iommu_get_msi_cookie - Acquire just MSI remapping resources | |
105 | * @domain: IOMMU domain to prepare | |
106 | * @base: Start address of IOVA region for MSI mappings | |
107 | * | |
108 | * Users who manage their own IOVA allocation and do not want DMA API support, | |
109 | * but would still like to take advantage of automatic MSI remapping, can use | |
110 | * this to initialise their own domain appropriately. Users should reserve a | |
111 | * contiguous IOVA region, starting at @base, large enough to accommodate the | |
112 | * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address | |
113 | * used by the devices attached to @domain. | |
114 | */ | |
115 | int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) | |
0db2e5d1 | 116 | { |
44bb7e24 | 117 | struct iommu_dma_cookie *cookie; |
0db2e5d1 | 118 | |
fdbe574e RM |
119 | if (domain->type != IOMMU_DOMAIN_UNMANAGED) |
120 | return -EINVAL; | |
121 | ||
0db2e5d1 RM |
122 | if (domain->iova_cookie) |
123 | return -EEXIST; | |
124 | ||
fdbe574e | 125 | cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE); |
44bb7e24 RM |
126 | if (!cookie) |
127 | return -ENOMEM; | |
0db2e5d1 | 128 | |
fdbe574e | 129 | cookie->msi_iova = base; |
44bb7e24 RM |
130 | domain->iova_cookie = cookie; |
131 | return 0; | |
0db2e5d1 | 132 | } |
fdbe574e | 133 | EXPORT_SYMBOL(iommu_get_msi_cookie); |
0db2e5d1 RM |
134 | |
135 | /** | |
136 | * iommu_put_dma_cookie - Release a domain's DMA mapping resources | |
fdbe574e RM |
137 | * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or |
138 | * iommu_get_msi_cookie() | |
0db2e5d1 RM |
139 | * |
140 | * IOMMU drivers should normally call this from their domain_free callback. | |
141 | */ | |
142 | void iommu_put_dma_cookie(struct iommu_domain *domain) | |
143 | { | |
44bb7e24 RM |
144 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
145 | struct iommu_dma_msi_page *msi, *tmp; | |
0db2e5d1 | 146 | |
44bb7e24 | 147 | if (!cookie) |
0db2e5d1 RM |
148 | return; |
149 | ||
fdbe574e | 150 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule) |
44bb7e24 RM |
151 | put_iova_domain(&cookie->iovad); |
152 | ||
153 | list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) { | |
154 | list_del(&msi->list); | |
155 | kfree(msi); | |
156 | } | |
157 | kfree(cookie); | |
0db2e5d1 RM |
158 | domain->iova_cookie = NULL; |
159 | } | |
160 | EXPORT_SYMBOL(iommu_put_dma_cookie); | |
161 | ||
273df963 RM |
162 | /** |
163 | * iommu_dma_get_resv_regions - Reserved region driver helper | |
164 | * @dev: Device from iommu_get_resv_regions() | |
165 | * @list: Reserved region list from iommu_get_resv_regions() | |
166 | * | |
167 | * IOMMU drivers can use this to implement their .get_resv_regions callback | |
cd2c9fcf SK |
168 | * for general non-IOMMU-specific reservations. Currently, this covers GICv3 |
169 | * ITS region reservation on ACPI based ARM platforms that may require HW MSI | |
170 | * reservation. | |
273df963 RM |
171 | */ |
172 | void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) | |
fade1ec0 | 173 | { |
fade1ec0 | 174 | |
98cc4f71 | 175 | if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode)) |
cd2c9fcf | 176 | iort_iommu_msi_get_resv_regions(dev, list); |
273df963 | 177 | |
fade1ec0 | 178 | } |
273df963 | 179 | EXPORT_SYMBOL(iommu_dma_get_resv_regions); |
fade1ec0 | 180 | |
7c1b058c RM |
181 | static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, |
182 | phys_addr_t start, phys_addr_t end) | |
183 | { | |
184 | struct iova_domain *iovad = &cookie->iovad; | |
185 | struct iommu_dma_msi_page *msi_page; | |
186 | int i, num_pages; | |
187 | ||
188 | start -= iova_offset(iovad, start); | |
189 | num_pages = iova_align(iovad, end - start) >> iova_shift(iovad); | |
190 | ||
191 | msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL); | |
192 | if (!msi_page) | |
193 | return -ENOMEM; | |
194 | ||
195 | for (i = 0; i < num_pages; i++) { | |
196 | msi_page[i].phys = start; | |
197 | msi_page[i].iova = start; | |
198 | INIT_LIST_HEAD(&msi_page[i].list); | |
199 | list_add(&msi_page[i].list, &cookie->msi_page_list); | |
200 | start += iovad->granule; | |
201 | } | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
aadad097 | 206 | static int iova_reserve_pci_windows(struct pci_dev *dev, |
cd2c9fcf SK |
207 | struct iova_domain *iovad) |
208 | { | |
209 | struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); | |
210 | struct resource_entry *window; | |
211 | unsigned long lo, hi; | |
aadad097 | 212 | phys_addr_t start = 0, end; |
cd2c9fcf SK |
213 | |
214 | resource_list_for_each_entry(window, &bridge->windows) { | |
215 | if (resource_type(window->res) != IORESOURCE_MEM) | |
216 | continue; | |
217 | ||
218 | lo = iova_pfn(iovad, window->res->start - window->offset); | |
219 | hi = iova_pfn(iovad, window->res->end - window->offset); | |
220 | reserve_iova(iovad, lo, hi); | |
221 | } | |
aadad097 SM |
222 | |
223 | /* Get reserved DMA windows from host bridge */ | |
224 | resource_list_for_each_entry(window, &bridge->dma_ranges) { | |
225 | end = window->res->start - window->offset; | |
226 | resv_iova: | |
227 | if (end > start) { | |
228 | lo = iova_pfn(iovad, start); | |
229 | hi = iova_pfn(iovad, end); | |
230 | reserve_iova(iovad, lo, hi); | |
231 | } else { | |
232 | /* dma_ranges list should be sorted */ | |
233 | dev_err(&dev->dev, "Failed to reserve IOVA\n"); | |
234 | return -EINVAL; | |
235 | } | |
236 | ||
237 | start = window->res->end - window->offset + 1; | |
238 | /* If window is last entry */ | |
239 | if (window->node.next == &bridge->dma_ranges && | |
240 | end != ~(dma_addr_t)0) { | |
241 | end = ~(dma_addr_t)0; | |
242 | goto resv_iova; | |
243 | } | |
244 | } | |
245 | ||
246 | return 0; | |
cd2c9fcf SK |
247 | } |
248 | ||
7c1b058c RM |
249 | static int iova_reserve_iommu_regions(struct device *dev, |
250 | struct iommu_domain *domain) | |
251 | { | |
252 | struct iommu_dma_cookie *cookie = domain->iova_cookie; | |
253 | struct iova_domain *iovad = &cookie->iovad; | |
254 | struct iommu_resv_region *region; | |
255 | LIST_HEAD(resv_regions); | |
256 | int ret = 0; | |
257 | ||
aadad097 SM |
258 | if (dev_is_pci(dev)) { |
259 | ret = iova_reserve_pci_windows(to_pci_dev(dev), iovad); | |
260 | if (ret) | |
261 | return ret; | |
262 | } | |
cd2c9fcf | 263 | |
7c1b058c RM |
264 | iommu_get_resv_regions(dev, &resv_regions); |
265 | list_for_each_entry(region, &resv_regions, list) { | |
266 | unsigned long lo, hi; | |
267 | ||
268 | /* We ARE the software that manages these! */ | |
269 | if (region->type == IOMMU_RESV_SW_MSI) | |
270 | continue; | |
271 | ||
272 | lo = iova_pfn(iovad, region->start); | |
273 | hi = iova_pfn(iovad, region->start + region->length - 1); | |
274 | reserve_iova(iovad, lo, hi); | |
275 | ||
276 | if (region->type == IOMMU_RESV_MSI) | |
277 | ret = cookie_init_hw_msi_region(cookie, region->start, | |
278 | region->start + region->length); | |
279 | if (ret) | |
280 | break; | |
281 | } | |
282 | iommu_put_resv_regions(dev, &resv_regions); | |
283 | ||
284 | return ret; | |
285 | } | |
286 | ||
2da274cd ZL |
287 | static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad) |
288 | { | |
289 | struct iommu_dma_cookie *cookie; | |
290 | struct iommu_domain *domain; | |
291 | ||
292 | cookie = container_of(iovad, struct iommu_dma_cookie, iovad); | |
293 | domain = cookie->fq_domain; | |
294 | /* | |
295 | * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE | |
296 | * implies that ops->flush_iotlb_all must be non-NULL. | |
297 | */ | |
298 | domain->ops->flush_iotlb_all(domain); | |
299 | } | |
300 | ||
0db2e5d1 RM |
301 | /** |
302 | * iommu_dma_init_domain - Initialise a DMA mapping domain | |
303 | * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() | |
304 | * @base: IOVA at which the mappable address space starts | |
305 | * @size: Size of IOVA space | |
fade1ec0 | 306 | * @dev: Device the domain is being initialised for |
0db2e5d1 RM |
307 | * |
308 | * @base and @size should be exact multiples of IOMMU page granularity to | |
309 | * avoid rounding surprises. If necessary, we reserve the page at address 0 | |
310 | * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but | |
311 | * any change which could make prior IOVAs invalid will fail. | |
312 | */ | |
06d60728 | 313 | static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, |
fade1ec0 | 314 | u64 size, struct device *dev) |
0db2e5d1 | 315 | { |
fdbe574e RM |
316 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
317 | struct iova_domain *iovad = &cookie->iovad; | |
c61a4633 | 318 | unsigned long order, base_pfn; |
2da274cd | 319 | int attr; |
0db2e5d1 | 320 | |
fdbe574e RM |
321 | if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE) |
322 | return -EINVAL; | |
0db2e5d1 RM |
323 | |
324 | /* Use the smallest supported page size for IOVA granularity */ | |
d16e0faa | 325 | order = __ffs(domain->pgsize_bitmap); |
0db2e5d1 | 326 | base_pfn = max_t(unsigned long, 1, base >> order); |
0db2e5d1 RM |
327 | |
328 | /* Check the domain allows at least some access to the device... */ | |
329 | if (domain->geometry.force_aperture) { | |
330 | if (base > domain->geometry.aperture_end || | |
331 | base + size <= domain->geometry.aperture_start) { | |
332 | pr_warn("specified DMA range outside IOMMU capability\n"); | |
333 | return -EFAULT; | |
334 | } | |
335 | /* ...then finally give it a kicking to make sure it fits */ | |
336 | base_pfn = max_t(unsigned long, base_pfn, | |
337 | domain->geometry.aperture_start >> order); | |
0db2e5d1 RM |
338 | } |
339 | ||
f51d7bb7 | 340 | /* start_pfn is always nonzero for an already-initialised domain */ |
0db2e5d1 RM |
341 | if (iovad->start_pfn) { |
342 | if (1UL << order != iovad->granule || | |
f51d7bb7 | 343 | base_pfn != iovad->start_pfn) { |
0db2e5d1 RM |
344 | pr_warn("Incompatible range for DMA domain\n"); |
345 | return -EFAULT; | |
346 | } | |
7c1b058c RM |
347 | |
348 | return 0; | |
0db2e5d1 | 349 | } |
7c1b058c | 350 | |
aa3ac946 | 351 | init_iova_domain(iovad, 1UL << order, base_pfn); |
2da274cd ZL |
352 | |
353 | if (!cookie->fq_domain && !iommu_domain_get_attr(domain, | |
354 | DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && attr) { | |
355 | cookie->fq_domain = domain; | |
356 | init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, NULL); | |
357 | } | |
358 | ||
7c1b058c RM |
359 | if (!dev) |
360 | return 0; | |
361 | ||
362 | return iova_reserve_iommu_regions(dev, domain); | |
0db2e5d1 | 363 | } |
0db2e5d1 RM |
364 | |
365 | /** | |
737c85ca MH |
366 | * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API |
367 | * page flags. | |
0db2e5d1 RM |
368 | * @dir: Direction of DMA transfer |
369 | * @coherent: Is the DMA master cache-coherent? | |
737c85ca | 370 | * @attrs: DMA attributes for the mapping |
0db2e5d1 RM |
371 | * |
372 | * Return: corresponding IOMMU API page protection flags | |
373 | */ | |
06d60728 | 374 | static int dma_info_to_prot(enum dma_data_direction dir, bool coherent, |
737c85ca | 375 | unsigned long attrs) |
0db2e5d1 RM |
376 | { |
377 | int prot = coherent ? IOMMU_CACHE : 0; | |
378 | ||
737c85ca MH |
379 | if (attrs & DMA_ATTR_PRIVILEGED) |
380 | prot |= IOMMU_PRIV; | |
381 | ||
0db2e5d1 RM |
382 | switch (dir) { |
383 | case DMA_BIDIRECTIONAL: | |
384 | return prot | IOMMU_READ | IOMMU_WRITE; | |
385 | case DMA_TO_DEVICE: | |
386 | return prot | IOMMU_READ; | |
387 | case DMA_FROM_DEVICE: | |
388 | return prot | IOMMU_WRITE; | |
389 | default: | |
390 | return 0; | |
391 | } | |
392 | } | |
393 | ||
842fe519 RM |
394 | static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain, |
395 | size_t size, dma_addr_t dma_limit, struct device *dev) | |
0db2e5d1 | 396 | { |
a44e6657 RM |
397 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
398 | struct iova_domain *iovad = &cookie->iovad; | |
bb65a64c | 399 | unsigned long shift, iova_len, iova = 0; |
0db2e5d1 | 400 | |
a44e6657 RM |
401 | if (cookie->type == IOMMU_DMA_MSI_COOKIE) { |
402 | cookie->msi_iova += size; | |
403 | return cookie->msi_iova - size; | |
404 | } | |
405 | ||
406 | shift = iova_shift(iovad); | |
407 | iova_len = size >> shift; | |
bb65a64c RM |
408 | /* |
409 | * Freeing non-power-of-two-sized allocations back into the IOVA caches | |
410 | * will come back to bite us badly, so we have to waste a bit of space | |
411 | * rounding up anything cacheable to make sure that can't happen. The | |
412 | * order of the unadjusted size will still match upon freeing. | |
413 | */ | |
414 | if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1))) | |
415 | iova_len = roundup_pow_of_two(iova_len); | |
a44e6657 | 416 | |
03bfdc31 RM |
417 | if (dev->bus_dma_mask) |
418 | dma_limit &= dev->bus_dma_mask; | |
419 | ||
c987ff0d RM |
420 | if (domain->geometry.force_aperture) |
421 | dma_limit = min(dma_limit, domain->geometry.aperture_end); | |
122fac03 RM |
422 | |
423 | /* Try to get PCI devices a SAC address */ | |
424 | if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev)) | |
538d5b33 TN |
425 | iova = alloc_iova_fast(iovad, iova_len, |
426 | DMA_BIT_MASK(32) >> shift, false); | |
bb65a64c | 427 | |
122fac03 | 428 | if (!iova) |
538d5b33 TN |
429 | iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift, |
430 | true); | |
122fac03 | 431 | |
bb65a64c | 432 | return (dma_addr_t)iova << shift; |
0db2e5d1 RM |
433 | } |
434 | ||
842fe519 RM |
435 | static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie, |
436 | dma_addr_t iova, size_t size) | |
0db2e5d1 | 437 | { |
842fe519 | 438 | struct iova_domain *iovad = &cookie->iovad; |
0db2e5d1 | 439 | |
a44e6657 | 440 | /* The MSI case is only ever cleaning up its most recent allocation */ |
bb65a64c | 441 | if (cookie->type == IOMMU_DMA_MSI_COOKIE) |
a44e6657 | 442 | cookie->msi_iova -= size; |
2da274cd ZL |
443 | else if (cookie->fq_domain) /* non-strict mode */ |
444 | queue_iova(iovad, iova_pfn(iovad, iova), | |
445 | size >> iova_shift(iovad), 0); | |
bb65a64c | 446 | else |
1cc896ed RM |
447 | free_iova_fast(iovad, iova_pfn(iovad, iova), |
448 | size >> iova_shift(iovad)); | |
842fe519 RM |
449 | } |
450 | ||
b61d271e | 451 | static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr, |
842fe519 RM |
452 | size_t size) |
453 | { | |
b61d271e | 454 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
a44e6657 RM |
455 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
456 | struct iova_domain *iovad = &cookie->iovad; | |
842fe519 RM |
457 | size_t iova_off = iova_offset(iovad, dma_addr); |
458 | ||
459 | dma_addr -= iova_off; | |
460 | size = iova_align(iovad, size + iova_off); | |
461 | ||
2da274cd ZL |
462 | WARN_ON(iommu_unmap_fast(domain, dma_addr, size) != size); |
463 | if (!cookie->fq_domain) | |
464 | iommu_tlb_sync(domain); | |
a44e6657 | 465 | iommu_dma_free_iova(cookie, dma_addr, size); |
0db2e5d1 RM |
466 | } |
467 | ||
92aec09c | 468 | static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys, |
b61d271e | 469 | size_t size, int prot) |
92aec09c | 470 | { |
b61d271e | 471 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
92aec09c CH |
472 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
473 | size_t iova_off = 0; | |
474 | dma_addr_t iova; | |
475 | ||
476 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE) { | |
477 | iova_off = iova_offset(&cookie->iovad, phys); | |
478 | size = iova_align(&cookie->iovad, size + iova_off); | |
479 | } | |
480 | ||
481 | iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev); | |
482 | if (!iova) | |
483 | return DMA_MAPPING_ERROR; | |
484 | ||
485 | if (iommu_map(domain, iova, phys - iova_off, size, prot)) { | |
486 | iommu_dma_free_iova(cookie, iova, size); | |
487 | return DMA_MAPPING_ERROR; | |
488 | } | |
489 | return iova + iova_off; | |
490 | } | |
491 | ||
0db2e5d1 RM |
492 | static void __iommu_dma_free_pages(struct page **pages, int count) |
493 | { | |
494 | while (count--) | |
495 | __free_page(pages[count]); | |
496 | kvfree(pages); | |
497 | } | |
498 | ||
c4b17afb GK |
499 | static struct page **__iommu_dma_alloc_pages(struct device *dev, |
500 | unsigned int count, unsigned long order_mask, gfp_t gfp) | |
0db2e5d1 RM |
501 | { |
502 | struct page **pages; | |
c4b17afb | 503 | unsigned int i = 0, nid = dev_to_node(dev); |
3b6b7e19 RM |
504 | |
505 | order_mask &= (2U << MAX_ORDER) - 1; | |
506 | if (!order_mask) | |
507 | return NULL; | |
0db2e5d1 | 508 | |
c4b17afb | 509 | pages = kvzalloc(count * sizeof(*pages), GFP_KERNEL); |
0db2e5d1 RM |
510 | if (!pages) |
511 | return NULL; | |
512 | ||
513 | /* IOMMU can map any pages, so himem can also be used here */ | |
514 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
515 | ||
516 | while (count) { | |
517 | struct page *page = NULL; | |
3b6b7e19 | 518 | unsigned int order_size; |
0db2e5d1 RM |
519 | |
520 | /* | |
521 | * Higher-order allocations are a convenience rather | |
522 | * than a necessity, hence using __GFP_NORETRY until | |
3b6b7e19 | 523 | * falling back to minimum-order allocations. |
0db2e5d1 | 524 | */ |
3b6b7e19 RM |
525 | for (order_mask &= (2U << __fls(count)) - 1; |
526 | order_mask; order_mask &= ~order_size) { | |
527 | unsigned int order = __fls(order_mask); | |
c4b17afb | 528 | gfp_t alloc_flags = gfp; |
3b6b7e19 RM |
529 | |
530 | order_size = 1U << order; | |
c4b17afb GK |
531 | if (order_mask > order_size) |
532 | alloc_flags |= __GFP_NORETRY; | |
533 | page = alloc_pages_node(nid, alloc_flags, order); | |
0db2e5d1 RM |
534 | if (!page) |
535 | continue; | |
3b6b7e19 RM |
536 | if (!order) |
537 | break; | |
538 | if (!PageCompound(page)) { | |
0db2e5d1 RM |
539 | split_page(page, order); |
540 | break; | |
3b6b7e19 RM |
541 | } else if (!split_huge_page(page)) { |
542 | break; | |
0db2e5d1 | 543 | } |
3b6b7e19 | 544 | __free_pages(page, order); |
0db2e5d1 | 545 | } |
0db2e5d1 RM |
546 | if (!page) { |
547 | __iommu_dma_free_pages(pages, i); | |
548 | return NULL; | |
549 | } | |
3b6b7e19 RM |
550 | count -= order_size; |
551 | while (order_size--) | |
0db2e5d1 RM |
552 | pages[i++] = page++; |
553 | } | |
554 | return pages; | |
555 | } | |
556 | ||
4c360ace RM |
557 | static struct page **__iommu_dma_get_pages(void *cpu_addr) |
558 | { | |
559 | struct vm_struct *area = find_vm_area(cpu_addr); | |
560 | ||
561 | if (!area || !area->pages) | |
562 | return NULL; | |
563 | return area->pages; | |
564 | } | |
565 | ||
0db2e5d1 | 566 | /** |
21b95aaf | 567 | * iommu_dma_alloc_remap - Allocate and map a buffer contiguous in IOVA space |
0db2e5d1 RM |
568 | * @dev: Device to allocate memory for. Must be a real device |
569 | * attached to an iommu_dma_domain | |
570 | * @size: Size of buffer in bytes | |
21b95aaf | 571 | * @dma_handle: Out argument for allocated DMA handle |
0db2e5d1 | 572 | * @gfp: Allocation flags |
3b6b7e19 | 573 | * @attrs: DMA attributes for this allocation |
0db2e5d1 RM |
574 | * |
575 | * If @size is less than PAGE_SIZE, then a full CPU page will be allocated, | |
576 | * but an IOMMU which supports smaller pages might not map the whole thing. | |
577 | * | |
21b95aaf | 578 | * Return: Mapped virtual address, or NULL on failure. |
0db2e5d1 | 579 | */ |
21b95aaf CH |
580 | static void *iommu_dma_alloc_remap(struct device *dev, size_t size, |
581 | dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) | |
0db2e5d1 | 582 | { |
43c5bf11 | 583 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
842fe519 RM |
584 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
585 | struct iova_domain *iovad = &cookie->iovad; | |
21b95aaf CH |
586 | bool coherent = dev_is_dma_coherent(dev); |
587 | int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs); | |
588 | pgprot_t prot = arch_dma_mmap_pgprot(dev, PAGE_KERNEL, attrs); | |
589 | unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap; | |
0db2e5d1 RM |
590 | struct page **pages; |
591 | struct sg_table sgt; | |
842fe519 | 592 | dma_addr_t iova; |
21b95aaf | 593 | void *vaddr; |
0db2e5d1 | 594 | |
21b95aaf | 595 | *dma_handle = DMA_MAPPING_ERROR; |
0db2e5d1 | 596 | |
3b6b7e19 RM |
597 | min_size = alloc_sizes & -alloc_sizes; |
598 | if (min_size < PAGE_SIZE) { | |
599 | min_size = PAGE_SIZE; | |
600 | alloc_sizes |= PAGE_SIZE; | |
601 | } else { | |
602 | size = ALIGN(size, min_size); | |
603 | } | |
00085f1e | 604 | if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES) |
3b6b7e19 RM |
605 | alloc_sizes = min_size; |
606 | ||
607 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c4b17afb GK |
608 | pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT, |
609 | gfp); | |
0db2e5d1 RM |
610 | if (!pages) |
611 | return NULL; | |
612 | ||
842fe519 RM |
613 | size = iova_align(iovad, size); |
614 | iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev); | |
0db2e5d1 RM |
615 | if (!iova) |
616 | goto out_free_pages; | |
617 | ||
0db2e5d1 RM |
618 | if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL)) |
619 | goto out_free_iova; | |
620 | ||
21b95aaf | 621 | if (!(ioprot & IOMMU_CACHE)) { |
23f88e0a CH |
622 | struct scatterlist *sg; |
623 | int i; | |
624 | ||
625 | for_each_sg(sgt.sgl, sg, sgt.orig_nents, i) | |
626 | arch_dma_prep_coherent(sg_page(sg), sg->length); | |
0db2e5d1 RM |
627 | } |
628 | ||
21b95aaf | 629 | if (iommu_map_sg(domain, iova, sgt.sgl, sgt.orig_nents, ioprot) |
0db2e5d1 RM |
630 | < size) |
631 | goto out_free_sg; | |
632 | ||
21b95aaf CH |
633 | vaddr = dma_common_pages_remap(pages, size, VM_USERMAP, prot, |
634 | __builtin_return_address(0)); | |
635 | if (!vaddr) | |
636 | goto out_unmap; | |
637 | ||
638 | *dma_handle = iova; | |
0db2e5d1 | 639 | sg_free_table(&sgt); |
21b95aaf | 640 | return vaddr; |
0db2e5d1 | 641 | |
21b95aaf CH |
642 | out_unmap: |
643 | __iommu_dma_unmap(dev, iova, size); | |
0db2e5d1 RM |
644 | out_free_sg: |
645 | sg_free_table(&sgt); | |
646 | out_free_iova: | |
842fe519 | 647 | iommu_dma_free_iova(cookie, iova, size); |
0db2e5d1 RM |
648 | out_free_pages: |
649 | __iommu_dma_free_pages(pages, count); | |
650 | return NULL; | |
651 | } | |
652 | ||
653 | /** | |
06d60728 CH |
654 | * __iommu_dma_mmap - Map a buffer into provided user VMA |
655 | * @pages: Array representing buffer from __iommu_dma_alloc() | |
0db2e5d1 RM |
656 | * @size: Size of buffer in bytes |
657 | * @vma: VMA describing requested userspace mapping | |
658 | * | |
659 | * Maps the pages of the buffer in @pages into @vma. The caller is responsible | |
660 | * for verifying the correct size and protection of @vma beforehand. | |
661 | */ | |
06d60728 CH |
662 | static int __iommu_dma_mmap(struct page **pages, size_t size, |
663 | struct vm_area_struct *vma) | |
0db2e5d1 | 664 | { |
b0d0084f | 665 | return vm_map_pages(vma, pages, PAGE_ALIGN(size) >> PAGE_SHIFT); |
0db2e5d1 RM |
666 | } |
667 | ||
06d60728 CH |
668 | static void iommu_dma_sync_single_for_cpu(struct device *dev, |
669 | dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) | |
670 | { | |
671 | phys_addr_t phys; | |
672 | ||
673 | if (dev_is_dma_coherent(dev)) | |
674 | return; | |
675 | ||
676 | phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle); | |
677 | arch_sync_dma_for_cpu(dev, phys, size, dir); | |
678 | } | |
679 | ||
680 | static void iommu_dma_sync_single_for_device(struct device *dev, | |
681 | dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) | |
682 | { | |
683 | phys_addr_t phys; | |
684 | ||
685 | if (dev_is_dma_coherent(dev)) | |
686 | return; | |
687 | ||
688 | phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle); | |
689 | arch_sync_dma_for_device(dev, phys, size, dir); | |
690 | } | |
691 | ||
692 | static void iommu_dma_sync_sg_for_cpu(struct device *dev, | |
693 | struct scatterlist *sgl, int nelems, | |
694 | enum dma_data_direction dir) | |
695 | { | |
696 | struct scatterlist *sg; | |
697 | int i; | |
698 | ||
699 | if (dev_is_dma_coherent(dev)) | |
700 | return; | |
701 | ||
702 | for_each_sg(sgl, sg, nelems, i) | |
703 | arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir); | |
704 | } | |
705 | ||
706 | static void iommu_dma_sync_sg_for_device(struct device *dev, | |
707 | struct scatterlist *sgl, int nelems, | |
708 | enum dma_data_direction dir) | |
709 | { | |
710 | struct scatterlist *sg; | |
711 | int i; | |
712 | ||
713 | if (dev_is_dma_coherent(dev)) | |
714 | return; | |
715 | ||
716 | for_each_sg(sgl, sg, nelems, i) | |
717 | arch_sync_dma_for_device(dev, sg_phys(sg), sg->length, dir); | |
718 | } | |
719 | ||
06d60728 CH |
720 | static dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page, |
721 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
722 | unsigned long attrs) | |
723 | { | |
724 | phys_addr_t phys = page_to_phys(page) + offset; | |
725 | bool coherent = dev_is_dma_coherent(dev); | |
b61d271e | 726 | int prot = dma_info_to_prot(dir, coherent, attrs); |
06d60728 CH |
727 | dma_addr_t dma_handle; |
728 | ||
b61d271e | 729 | dma_handle =__iommu_dma_map(dev, phys, size, prot); |
06d60728 CH |
730 | if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
731 | dma_handle != DMA_MAPPING_ERROR) | |
732 | arch_sync_dma_for_device(dev, phys, size, dir); | |
733 | return dma_handle; | |
734 | } | |
735 | ||
736 | static void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle, | |
737 | size_t size, enum dma_data_direction dir, unsigned long attrs) | |
738 | { | |
739 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) | |
740 | iommu_dma_sync_single_for_cpu(dev, dma_handle, size, dir); | |
b61d271e | 741 | __iommu_dma_unmap(dev, dma_handle, size); |
06d60728 CH |
742 | } |
743 | ||
0db2e5d1 RM |
744 | /* |
745 | * Prepare a successfully-mapped scatterlist to give back to the caller. | |
809eac54 RM |
746 | * |
747 | * At this point the segments are already laid out by iommu_dma_map_sg() to | |
748 | * avoid individually crossing any boundaries, so we merely need to check a | |
749 | * segment's start address to avoid concatenating across one. | |
0db2e5d1 RM |
750 | */ |
751 | static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents, | |
752 | dma_addr_t dma_addr) | |
753 | { | |
809eac54 RM |
754 | struct scatterlist *s, *cur = sg; |
755 | unsigned long seg_mask = dma_get_seg_boundary(dev); | |
756 | unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev); | |
757 | int i, count = 0; | |
0db2e5d1 RM |
758 | |
759 | for_each_sg(sg, s, nents, i) { | |
809eac54 RM |
760 | /* Restore this segment's original unaligned fields first */ |
761 | unsigned int s_iova_off = sg_dma_address(s); | |
0db2e5d1 | 762 | unsigned int s_length = sg_dma_len(s); |
809eac54 | 763 | unsigned int s_iova_len = s->length; |
0db2e5d1 | 764 | |
809eac54 | 765 | s->offset += s_iova_off; |
0db2e5d1 | 766 | s->length = s_length; |
cad34be7 | 767 | sg_dma_address(s) = DMA_MAPPING_ERROR; |
809eac54 RM |
768 | sg_dma_len(s) = 0; |
769 | ||
770 | /* | |
771 | * Now fill in the real DMA data. If... | |
772 | * - there is a valid output segment to append to | |
773 | * - and this segment starts on an IOVA page boundary | |
774 | * - but doesn't fall at a segment boundary | |
775 | * - and wouldn't make the resulting output segment too long | |
776 | */ | |
777 | if (cur_len && !s_iova_off && (dma_addr & seg_mask) && | |
778 | (cur_len + s_length <= max_len)) { | |
779 | /* ...then concatenate it with the previous one */ | |
780 | cur_len += s_length; | |
781 | } else { | |
782 | /* Otherwise start the next output segment */ | |
783 | if (i > 0) | |
784 | cur = sg_next(cur); | |
785 | cur_len = s_length; | |
786 | count++; | |
787 | ||
788 | sg_dma_address(cur) = dma_addr + s_iova_off; | |
789 | } | |
790 | ||
791 | sg_dma_len(cur) = cur_len; | |
792 | dma_addr += s_iova_len; | |
793 | ||
794 | if (s_length + s_iova_off < s_iova_len) | |
795 | cur_len = 0; | |
0db2e5d1 | 796 | } |
809eac54 | 797 | return count; |
0db2e5d1 RM |
798 | } |
799 | ||
800 | /* | |
801 | * If mapping failed, then just restore the original list, | |
802 | * but making sure the DMA fields are invalidated. | |
803 | */ | |
804 | static void __invalidate_sg(struct scatterlist *sg, int nents) | |
805 | { | |
806 | struct scatterlist *s; | |
807 | int i; | |
808 | ||
809 | for_each_sg(sg, s, nents, i) { | |
cad34be7 | 810 | if (sg_dma_address(s) != DMA_MAPPING_ERROR) |
07b48ac4 | 811 | s->offset += sg_dma_address(s); |
0db2e5d1 RM |
812 | if (sg_dma_len(s)) |
813 | s->length = sg_dma_len(s); | |
cad34be7 | 814 | sg_dma_address(s) = DMA_MAPPING_ERROR; |
0db2e5d1 RM |
815 | sg_dma_len(s) = 0; |
816 | } | |
817 | } | |
818 | ||
819 | /* | |
820 | * The DMA API client is passing in a scatterlist which could describe | |
821 | * any old buffer layout, but the IOMMU API requires everything to be | |
822 | * aligned to IOMMU pages. Hence the need for this complicated bit of | |
823 | * impedance-matching, to be able to hand off a suitably-aligned list, | |
824 | * but still preserve the original offsets and sizes for the caller. | |
825 | */ | |
06d60728 CH |
826 | static int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, |
827 | int nents, enum dma_data_direction dir, unsigned long attrs) | |
0db2e5d1 | 828 | { |
43c5bf11 | 829 | struct iommu_domain *domain = iommu_get_dma_domain(dev); |
842fe519 RM |
830 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
831 | struct iova_domain *iovad = &cookie->iovad; | |
0db2e5d1 | 832 | struct scatterlist *s, *prev = NULL; |
06d60728 | 833 | int prot = dma_info_to_prot(dir, dev_is_dma_coherent(dev), attrs); |
842fe519 | 834 | dma_addr_t iova; |
0db2e5d1 | 835 | size_t iova_len = 0; |
809eac54 | 836 | unsigned long mask = dma_get_seg_boundary(dev); |
0db2e5d1 RM |
837 | int i; |
838 | ||
06d60728 CH |
839 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
840 | iommu_dma_sync_sg_for_device(dev, sg, nents, dir); | |
841 | ||
0db2e5d1 RM |
842 | /* |
843 | * Work out how much IOVA space we need, and align the segments to | |
844 | * IOVA granules for the IOMMU driver to handle. With some clever | |
845 | * trickery we can modify the list in-place, but reversibly, by | |
809eac54 | 846 | * stashing the unaligned parts in the as-yet-unused DMA fields. |
0db2e5d1 RM |
847 | */ |
848 | for_each_sg(sg, s, nents, i) { | |
809eac54 | 849 | size_t s_iova_off = iova_offset(iovad, s->offset); |
0db2e5d1 | 850 | size_t s_length = s->length; |
809eac54 | 851 | size_t pad_len = (mask - iova_len + 1) & mask; |
0db2e5d1 | 852 | |
809eac54 | 853 | sg_dma_address(s) = s_iova_off; |
0db2e5d1 | 854 | sg_dma_len(s) = s_length; |
809eac54 RM |
855 | s->offset -= s_iova_off; |
856 | s_length = iova_align(iovad, s_length + s_iova_off); | |
0db2e5d1 RM |
857 | s->length = s_length; |
858 | ||
859 | /* | |
809eac54 RM |
860 | * Due to the alignment of our single IOVA allocation, we can |
861 | * depend on these assumptions about the segment boundary mask: | |
862 | * - If mask size >= IOVA size, then the IOVA range cannot | |
863 | * possibly fall across a boundary, so we don't care. | |
864 | * - If mask size < IOVA size, then the IOVA range must start | |
865 | * exactly on a boundary, therefore we can lay things out | |
866 | * based purely on segment lengths without needing to know | |
867 | * the actual addresses beforehand. | |
868 | * - The mask must be a power of 2, so pad_len == 0 if | |
869 | * iova_len == 0, thus we cannot dereference prev the first | |
870 | * time through here (i.e. before it has a meaningful value). | |
0db2e5d1 | 871 | */ |
809eac54 | 872 | if (pad_len && pad_len < s_length - 1) { |
0db2e5d1 RM |
873 | prev->length += pad_len; |
874 | iova_len += pad_len; | |
875 | } | |
876 | ||
877 | iova_len += s_length; | |
878 | prev = s; | |
879 | } | |
880 | ||
842fe519 | 881 | iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev); |
0db2e5d1 RM |
882 | if (!iova) |
883 | goto out_restore_sg; | |
884 | ||
885 | /* | |
886 | * We'll leave any physical concatenation to the IOMMU driver's | |
887 | * implementation - it knows better than we do. | |
888 | */ | |
842fe519 | 889 | if (iommu_map_sg(domain, iova, sg, nents, prot) < iova_len) |
0db2e5d1 RM |
890 | goto out_free_iova; |
891 | ||
842fe519 | 892 | return __finalise_sg(dev, sg, nents, iova); |
0db2e5d1 RM |
893 | |
894 | out_free_iova: | |
842fe519 | 895 | iommu_dma_free_iova(cookie, iova, iova_len); |
0db2e5d1 RM |
896 | out_restore_sg: |
897 | __invalidate_sg(sg, nents); | |
898 | return 0; | |
899 | } | |
900 | ||
06d60728 CH |
901 | static void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, |
902 | int nents, enum dma_data_direction dir, unsigned long attrs) | |
0db2e5d1 | 903 | { |
842fe519 RM |
904 | dma_addr_t start, end; |
905 | struct scatterlist *tmp; | |
906 | int i; | |
06d60728 CH |
907 | |
908 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) | |
909 | iommu_dma_sync_sg_for_cpu(dev, sg, nents, dir); | |
910 | ||
0db2e5d1 RM |
911 | /* |
912 | * The scatterlist segments are mapped into a single | |
913 | * contiguous IOVA allocation, so this is incredibly easy. | |
914 | */ | |
842fe519 RM |
915 | start = sg_dma_address(sg); |
916 | for_each_sg(sg_next(sg), tmp, nents - 1, i) { | |
917 | if (sg_dma_len(tmp) == 0) | |
918 | break; | |
919 | sg = tmp; | |
920 | } | |
921 | end = sg_dma_address(sg) + sg_dma_len(sg); | |
b61d271e | 922 | __iommu_dma_unmap(dev, start, end - start); |
0db2e5d1 RM |
923 | } |
924 | ||
06d60728 | 925 | static dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys, |
51f8cc9e RM |
926 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
927 | { | |
928 | return __iommu_dma_map(dev, phys, size, | |
b61d271e | 929 | dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO); |
51f8cc9e RM |
930 | } |
931 | ||
06d60728 | 932 | static void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, |
51f8cc9e RM |
933 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
934 | { | |
b61d271e | 935 | __iommu_dma_unmap(dev, handle, size); |
51f8cc9e RM |
936 | } |
937 | ||
bcf4b9c4 RM |
938 | static void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr, |
939 | dma_addr_t handle, unsigned long attrs) | |
940 | { | |
941 | size_t alloc_size = PAGE_ALIGN(size); | |
942 | int count = alloc_size >> PAGE_SHIFT; | |
943 | struct page *page = NULL, **pages = NULL; | |
944 | ||
945 | __iommu_dma_unmap(dev, handle, size); | |
946 | ||
947 | /* Non-coherent atomic allocation? Easy */ | |
948 | if (dma_free_from_pool(cpu_addr, alloc_size)) | |
949 | return; | |
950 | ||
951 | if (is_vmalloc_addr(cpu_addr)) { | |
952 | /* | |
953 | * If it the address is remapped, then it's either non-coherent | |
954 | * or highmem CMA, or an iommu_dma_alloc_remap() construction. | |
955 | */ | |
956 | pages = __iommu_dma_get_pages(cpu_addr); | |
957 | if (!pages) | |
958 | page = vmalloc_to_page(cpu_addr); | |
959 | dma_common_free_remap(cpu_addr, alloc_size, VM_USERMAP); | |
960 | } else { | |
961 | /* Lowmem means a coherent atomic or CMA allocation */ | |
962 | page = virt_to_page(cpu_addr); | |
963 | } | |
964 | ||
965 | if (pages) | |
966 | __iommu_dma_free_pages(pages, count); | |
967 | if (page && !dma_release_from_contiguous(dev, page, count)) | |
968 | __free_pages(page, get_order(alloc_size)); | |
969 | } | |
970 | ||
06d60728 CH |
971 | static void *iommu_dma_alloc(struct device *dev, size_t size, |
972 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) | |
973 | { | |
974 | bool coherent = dev_is_dma_coherent(dev); | |
975 | int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs); | |
072bebc0 | 976 | pgprot_t prot = arch_dma_mmap_pgprot(dev, PAGE_KERNEL, attrs); |
06d60728 | 977 | size_t iosize = size; |
072bebc0 | 978 | struct page *page; |
06d60728 CH |
979 | void *addr; |
980 | ||
981 | size = PAGE_ALIGN(size); | |
982 | gfp |= __GFP_ZERO; | |
983 | ||
072bebc0 RM |
984 | if (gfpflags_allow_blocking(gfp) && |
985 | !(attrs & DMA_ATTR_FORCE_CONTIGUOUS)) | |
986 | return iommu_dma_alloc_remap(dev, iosize, handle, gfp, attrs); | |
987 | ||
06d60728 | 988 | if (!gfpflags_allow_blocking(gfp)) { |
06d60728 CH |
989 | /* |
990 | * In atomic context we can't remap anything, so we'll only | |
991 | * get the virtually contiguous buffer we need by way of a | |
992 | * physically contiguous allocation. | |
993 | */ | |
994 | if (coherent) { | |
995 | page = alloc_pages(gfp, get_order(size)); | |
996 | addr = page ? page_address(page) : NULL; | |
997 | } else { | |
998 | addr = dma_alloc_from_pool(size, &page, gfp); | |
999 | } | |
1000 | if (!addr) | |
1001 | return NULL; | |
1002 | ||
796a08cf RM |
1003 | *handle = __iommu_dma_map(dev, page_to_phys(page), iosize, |
1004 | ioprot); | |
06d60728 CH |
1005 | if (*handle == DMA_MAPPING_ERROR) { |
1006 | if (coherent) | |
1007 | __free_pages(page, get_order(size)); | |
1008 | else | |
1009 | dma_free_from_pool(addr, size); | |
06d60728 | 1010 | return NULL; |
06d60728 | 1011 | } |
072bebc0 | 1012 | return addr; |
06d60728 | 1013 | } |
072bebc0 RM |
1014 | |
1015 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, | |
1016 | get_order(size), gfp & __GFP_NOWARN); | |
1017 | if (!page) | |
1018 | return NULL; | |
1019 | ||
1020 | *handle = __iommu_dma_map(dev, page_to_phys(page), iosize, ioprot); | |
1021 | if (*handle == DMA_MAPPING_ERROR) | |
1022 | goto out_free_pages; | |
1023 | ||
1024 | addr = dma_common_contiguous_remap(page, size, VM_USERMAP, prot, | |
1025 | __builtin_return_address(0)); | |
1026 | if (!addr) | |
1027 | goto out_unmap; | |
1028 | ||
1029 | if (!coherent) | |
1030 | arch_dma_prep_coherent(page, iosize); | |
1031 | memset(addr, 0, size); | |
06d60728 | 1032 | return addr; |
072bebc0 RM |
1033 | out_unmap: |
1034 | __iommu_dma_unmap(dev, *handle, iosize); | |
1035 | out_free_pages: | |
1036 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); | |
1037 | return NULL; | |
06d60728 CH |
1038 | } |
1039 | ||
06d60728 CH |
1040 | static int __iommu_dma_mmap_pfn(struct vm_area_struct *vma, |
1041 | unsigned long pfn, size_t size) | |
1042 | { | |
1043 | int ret = -ENXIO; | |
1044 | unsigned long nr_vma_pages = vma_pages(vma); | |
1045 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1046 | unsigned long off = vma->vm_pgoff; | |
1047 | ||
1048 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { | |
1049 | ret = remap_pfn_range(vma, vma->vm_start, | |
1050 | pfn + off, | |
1051 | vma->vm_end - vma->vm_start, | |
1052 | vma->vm_page_prot); | |
1053 | } | |
1054 | ||
1055 | return ret; | |
1056 | } | |
1057 | ||
1058 | static int iommu_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
1059 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1060 | unsigned long attrs) | |
1061 | { | |
1062 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1063 | unsigned long off = vma->vm_pgoff; | |
4c360ace | 1064 | struct page **pages; |
06d60728 CH |
1065 | int ret; |
1066 | ||
1067 | vma->vm_page_prot = arch_dma_mmap_pgprot(dev, vma->vm_page_prot, attrs); | |
1068 | ||
1069 | if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) | |
1070 | return ret; | |
1071 | ||
1072 | if (off >= nr_pages || vma_pages(vma) > nr_pages - off) | |
1073 | return -ENXIO; | |
1074 | ||
1075 | if (!is_vmalloc_addr(cpu_addr)) { | |
1076 | unsigned long pfn = page_to_pfn(virt_to_page(cpu_addr)); | |
1077 | return __iommu_dma_mmap_pfn(vma, pfn, size); | |
1078 | } | |
1079 | ||
1080 | if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) { | |
1081 | /* | |
1082 | * DMA_ATTR_FORCE_CONTIGUOUS allocations are always remapped, | |
1083 | * hence in the vmalloc space. | |
1084 | */ | |
1085 | unsigned long pfn = vmalloc_to_pfn(cpu_addr); | |
1086 | return __iommu_dma_mmap_pfn(vma, pfn, size); | |
1087 | } | |
1088 | ||
4c360ace RM |
1089 | pages = __iommu_dma_get_pages(cpu_addr); |
1090 | if (!pages) | |
06d60728 | 1091 | return -ENXIO; |
4c360ace | 1092 | return __iommu_dma_mmap(pages, size, vma); |
06d60728 CH |
1093 | } |
1094 | ||
1095 | static int __iommu_dma_get_sgtable_page(struct sg_table *sgt, struct page *page, | |
1096 | size_t size) | |
1097 | { | |
1098 | int ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
1099 | ||
1100 | if (!ret) | |
1101 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
1102 | return ret; | |
1103 | } | |
1104 | ||
1105 | static int iommu_dma_get_sgtable(struct device *dev, struct sg_table *sgt, | |
1106 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1107 | unsigned long attrs) | |
1108 | { | |
1109 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
4c360ace | 1110 | struct page **pages; |
06d60728 CH |
1111 | |
1112 | if (!is_vmalloc_addr(cpu_addr)) { | |
1113 | struct page *page = virt_to_page(cpu_addr); | |
1114 | return __iommu_dma_get_sgtable_page(sgt, page, size); | |
1115 | } | |
1116 | ||
1117 | if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) { | |
1118 | /* | |
1119 | * DMA_ATTR_FORCE_CONTIGUOUS allocations are always remapped, | |
1120 | * hence in the vmalloc space. | |
1121 | */ | |
1122 | struct page *page = vmalloc_to_page(cpu_addr); | |
1123 | return __iommu_dma_get_sgtable_page(sgt, page, size); | |
1124 | } | |
1125 | ||
4c360ace RM |
1126 | pages = __iommu_dma_get_pages(cpu_addr); |
1127 | if (!pages) | |
06d60728 | 1128 | return -ENXIO; |
4c360ace | 1129 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, |
06d60728 CH |
1130 | GFP_KERNEL); |
1131 | } | |
1132 | ||
1133 | static const struct dma_map_ops iommu_dma_ops = { | |
1134 | .alloc = iommu_dma_alloc, | |
1135 | .free = iommu_dma_free, | |
1136 | .mmap = iommu_dma_mmap, | |
1137 | .get_sgtable = iommu_dma_get_sgtable, | |
1138 | .map_page = iommu_dma_map_page, | |
1139 | .unmap_page = iommu_dma_unmap_page, | |
1140 | .map_sg = iommu_dma_map_sg, | |
1141 | .unmap_sg = iommu_dma_unmap_sg, | |
1142 | .sync_single_for_cpu = iommu_dma_sync_single_for_cpu, | |
1143 | .sync_single_for_device = iommu_dma_sync_single_for_device, | |
1144 | .sync_sg_for_cpu = iommu_dma_sync_sg_for_cpu, | |
1145 | .sync_sg_for_device = iommu_dma_sync_sg_for_device, | |
1146 | .map_resource = iommu_dma_map_resource, | |
1147 | .unmap_resource = iommu_dma_unmap_resource, | |
1148 | }; | |
1149 | ||
1150 | /* | |
1151 | * The IOMMU core code allocates the default DMA domain, which the underlying | |
1152 | * IOMMU driver needs to support via the dma-iommu layer. | |
1153 | */ | |
1154 | void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size) | |
1155 | { | |
1156 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); | |
1157 | ||
1158 | if (!domain) | |
1159 | goto out_err; | |
1160 | ||
1161 | /* | |
1162 | * The IOMMU core code allocates the default DMA domain, which the | |
1163 | * underlying IOMMU driver needs to support via the dma-iommu layer. | |
1164 | */ | |
1165 | if (domain->type == IOMMU_DOMAIN_DMA) { | |
1166 | if (iommu_dma_init_domain(domain, dma_base, size, dev)) | |
1167 | goto out_err; | |
1168 | dev->dma_ops = &iommu_dma_ops; | |
1169 | } | |
1170 | ||
1171 | return; | |
1172 | out_err: | |
1173 | pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n", | |
1174 | dev_name(dev)); | |
1175 | } | |
1176 | ||
44bb7e24 RM |
1177 | static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev, |
1178 | phys_addr_t msi_addr, struct iommu_domain *domain) | |
1179 | { | |
1180 | struct iommu_dma_cookie *cookie = domain->iova_cookie; | |
1181 | struct iommu_dma_msi_page *msi_page; | |
842fe519 | 1182 | dma_addr_t iova; |
44bb7e24 | 1183 | int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; |
fdbe574e | 1184 | size_t size = cookie_msi_granule(cookie); |
44bb7e24 | 1185 | |
fdbe574e | 1186 | msi_addr &= ~(phys_addr_t)(size - 1); |
44bb7e24 RM |
1187 | list_for_each_entry(msi_page, &cookie->msi_page_list, list) |
1188 | if (msi_page->phys == msi_addr) | |
1189 | return msi_page; | |
1190 | ||
1191 | msi_page = kzalloc(sizeof(*msi_page), GFP_ATOMIC); | |
1192 | if (!msi_page) | |
1193 | return NULL; | |
1194 | ||
b61d271e | 1195 | iova = __iommu_dma_map(dev, msi_addr, size, prot); |
cad34be7 | 1196 | if (iova == DMA_MAPPING_ERROR) |
a44e6657 | 1197 | goto out_free_page; |
44bb7e24 RM |
1198 | |
1199 | INIT_LIST_HEAD(&msi_page->list); | |
a44e6657 RM |
1200 | msi_page->phys = msi_addr; |
1201 | msi_page->iova = iova; | |
44bb7e24 RM |
1202 | list_add(&msi_page->list, &cookie->msi_page_list); |
1203 | return msi_page; | |
1204 | ||
44bb7e24 RM |
1205 | out_free_page: |
1206 | kfree(msi_page); | |
1207 | return NULL; | |
1208 | } | |
1209 | ||
ece6e6f0 | 1210 | int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) |
44bb7e24 | 1211 | { |
ece6e6f0 | 1212 | struct device *dev = msi_desc_to_dev(desc); |
44bb7e24 RM |
1213 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); |
1214 | struct iommu_dma_cookie *cookie; | |
1215 | struct iommu_dma_msi_page *msi_page; | |
44bb7e24 RM |
1216 | unsigned long flags; |
1217 | ||
ece6e6f0 JG |
1218 | if (!domain || !domain->iova_cookie) { |
1219 | desc->iommu_cookie = NULL; | |
1220 | return 0; | |
1221 | } | |
44bb7e24 RM |
1222 | |
1223 | cookie = domain->iova_cookie; | |
1224 | ||
1225 | /* | |
1226 | * We disable IRQs to rule out a possible inversion against | |
1227 | * irq_desc_lock if, say, someone tries to retarget the affinity | |
1228 | * of an MSI from within an IPI handler. | |
1229 | */ | |
1230 | spin_lock_irqsave(&cookie->msi_lock, flags); | |
1231 | msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain); | |
1232 | spin_unlock_irqrestore(&cookie->msi_lock, flags); | |
1233 | ||
ece6e6f0 JG |
1234 | msi_desc_set_iommu_cookie(desc, msi_page); |
1235 | ||
1236 | if (!msi_page) | |
1237 | return -ENOMEM; | |
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | void iommu_dma_compose_msi_msg(struct msi_desc *desc, | |
1242 | struct msi_msg *msg) | |
1243 | { | |
1244 | struct device *dev = msi_desc_to_dev(desc); | |
1245 | const struct iommu_domain *domain = iommu_get_domain_for_dev(dev); | |
1246 | const struct iommu_dma_msi_page *msi_page; | |
1247 | ||
1248 | msi_page = msi_desc_get_iommu_cookie(desc); | |
1249 | ||
1250 | if (!domain || !domain->iova_cookie || WARN_ON(!msi_page)) | |
1251 | return; | |
1252 | ||
1253 | msg->address_hi = upper_32_bits(msi_page->iova); | |
1254 | msg->address_lo &= cookie_msi_granule(domain->iova_cookie) - 1; | |
1255 | msg->address_lo += lower_32_bits(msi_page->iova); | |
44bb7e24 | 1256 | } |
06d60728 CH |
1257 | |
1258 | static int iommu_dma_init(void) | |
1259 | { | |
1260 | return iova_cache_get(); | |
1261 | } | |
1262 | arch_initcall(iommu_dma_init); |