[linux-2.6-block.git] / drivers / iommu / arm-smmu-regs.h

/*
 * IOMMU API for ARM architected SMMU implementations.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright (C) 2013 ARM Limited
 *
 * Author: Will Deacon <will.deacon@arm.com>
 */

#ifndef _ARM_SMMU_REGS_H
#define _ARM_SMMU_REGS_H

/* Configuration registers */
#define ARM_SMMU_GR0_sCR0		0x0
#define sCR0_CLIENTPD			(1 << 0)
#define sCR0_GFRE			(1 << 1)
#define sCR0_GFIE			(1 << 2)
#define sCR0_EXIDENABLE			(1 << 3)
#define sCR0_GCFGFRE			(1 << 4)
#define sCR0_GCFGFIE			(1 << 5)
#define sCR0_USFCFG			(1 << 10)
#define sCR0_VMIDPNE			(1 << 11)
#define sCR0_PTM			(1 << 12)
#define sCR0_FB				(1 << 13)
#define sCR0_VMID16EN			(1 << 31)
#define sCR0_BSU_SHIFT			14
#define sCR0_BSU_MASK			0x3

/* Auxiliary Configuration register */
#define ARM_SMMU_GR0_sACR		0x10

/* Identification registers */
#define ARM_SMMU_GR0_ID0		0x20
#define ARM_SMMU_GR0_ID1		0x24
#define ARM_SMMU_GR0_ID2		0x28
#define ARM_SMMU_GR0_ID3		0x2c
#define ARM_SMMU_GR0_ID4		0x30
#define ARM_SMMU_GR0_ID5		0x34
#define ARM_SMMU_GR0_ID6		0x38
#define ARM_SMMU_GR0_ID7		0x3c
#define ARM_SMMU_GR0_sGFSR		0x48
#define ARM_SMMU_GR0_sGFSYNR0		0x50
#define ARM_SMMU_GR0_sGFSYNR1		0x54
#define ARM_SMMU_GR0_sGFSYNR2		0x58

#define ID0_S1TS			(1 << 30)
#define ID0_S2TS			(1 << 29)
#define ID0_NTS				(1 << 28)
#define ID0_SMS				(1 << 27)
#define ID0_ATOSNS			(1 << 26)
#define ID0_PTFS_NO_AARCH32		(1 << 25)
#define ID0_PTFS_NO_AARCH32S		(1 << 24)
#define ID0_CTTW			(1 << 14)
#define ID0_NUMIRPT_SHIFT		16
#define ID0_NUMIRPT_MASK		0xff
#define ID0_NUMSIDB_SHIFT		9
#define ID0_NUMSIDB_MASK		0xf
#define ID0_EXIDS			(1 << 8)
#define ID0_NUMSMRG_SHIFT		0
#define ID0_NUMSMRG_MASK		0xff

#define ID1_PAGESIZE			(1 << 31)
#define ID1_NUMPAGENDXB_SHIFT		28
#define ID1_NUMPAGENDXB_MASK		7
#define ID1_NUMS2CB_SHIFT		16
#define ID1_NUMS2CB_MASK		0xff
#define ID1_NUMCB_SHIFT			0
#define ID1_NUMCB_MASK			0xff

#define ID2_OAS_SHIFT			4
#define ID2_OAS_MASK			0xf
#define ID2_IAS_SHIFT			0
#define ID2_IAS_MASK			0xf
#define ID2_UBS_SHIFT			8
#define ID2_UBS_MASK			0xf
#define ID2_PTFS_4K			(1 << 12)
#define ID2_PTFS_16K			(1 << 13)
#define ID2_PTFS_64K			(1 << 14)
#define ID2_VMID16			(1 << 15)

#define ID7_MAJOR_SHIFT			4
#define ID7_MAJOR_MASK			0xf

/* Global TLB invalidation */
#define ARM_SMMU_GR0_TLBIVMID		0x64
#define ARM_SMMU_GR0_TLBIALLNSNH	0x68
#define ARM_SMMU_GR0_TLBIALLH		0x6c
#define ARM_SMMU_GR0_sTLBGSYNC		0x70
#define ARM_SMMU_GR0_sTLBGSTATUS	0x74
#define sTLBGSTATUS_GSACTIVE		(1 << 0)

/* Stream mapping registers */
#define ARM_SMMU_GR0_SMR(n)		(0x800 + ((n) << 2))
#define SMR_VALID			(1 << 31)
#define SMR_MASK_SHIFT			16
#define SMR_ID_SHIFT			0

#define ARM_SMMU_GR0_S2CR(n)		(0xc00 + ((n) << 2))
#define S2CR_CBNDX_SHIFT		0
#define S2CR_CBNDX_MASK			0xff
#define S2CR_EXIDVALID			(1 << 10)
#define S2CR_TYPE_SHIFT			16
#define S2CR_TYPE_MASK			0x3
enum arm_smmu_s2cr_type {
	S2CR_TYPE_TRANS,
	S2CR_TYPE_BYPASS,
	S2CR_TYPE_FAULT,
};

#define S2CR_PRIVCFG_SHIFT		24
#define S2CR_PRIVCFG_MASK		0x3
enum arm_smmu_s2cr_privcfg {
	S2CR_PRIVCFG_DEFAULT,
	S2CR_PRIVCFG_DIPAN,
	S2CR_PRIVCFG_UNPRIV,
	S2CR_PRIVCFG_PRIV,
};

/* Context bank attribute registers */
#define ARM_SMMU_GR1_CBAR(n)		(0x0 + ((n) << 2))
#define CBAR_VMID_SHIFT			0
#define CBAR_VMID_MASK			0xff
#define CBAR_S1_BPSHCFG_SHIFT		8
#define CBAR_S1_BPSHCFG_MASK		3
#define CBAR_S1_BPSHCFG_NSH		3
#define CBAR_S1_MEMATTR_SHIFT		12
#define CBAR_S1_MEMATTR_MASK		0xf
#define CBAR_S1_MEMATTR_WB		0xf
#define CBAR_TYPE_SHIFT			16
#define CBAR_TYPE_MASK			0x3
#define CBAR_TYPE_S2_TRANS		(0 << CBAR_TYPE_SHIFT)
#define CBAR_TYPE_S1_TRANS_S2_BYPASS	(1 << CBAR_TYPE_SHIFT)
#define CBAR_TYPE_S1_TRANS_S2_FAULT	(2 << CBAR_TYPE_SHIFT)
#define CBAR_TYPE_S1_TRANS_S2_TRANS	(3 << CBAR_TYPE_SHIFT)
#define CBAR_IRPTNDX_SHIFT		24
#define CBAR_IRPTNDX_MASK		0xff

#define ARM_SMMU_GR1_CBA2R(n)		(0x800 + ((n) << 2))
#define CBA2R_RW64_32BIT		(0 << 0)
#define CBA2R_RW64_64BIT		(1 << 0)
#define CBA2R_VMID_SHIFT		16
#define CBA2R_VMID_MASK			0xffff

#define ARM_SMMU_CB_SCTLR		0x0
#define ARM_SMMU_CB_ACTLR		0x4
#define ARM_SMMU_CB_RESUME		0x8
#define ARM_SMMU_CB_TTBCR2		0x10
#define ARM_SMMU_CB_TTBR0		0x20
#define ARM_SMMU_CB_TTBR1		0x28
#define ARM_SMMU_CB_TTBCR		0x30
#define ARM_SMMU_CB_CONTEXTIDR		0x34
#define ARM_SMMU_CB_S1_MAIR0		0x38
#define ARM_SMMU_CB_S1_MAIR1		0x3c
#define ARM_SMMU_CB_PAR			0x50
#define ARM_SMMU_CB_FSR			0x58
#define ARM_SMMU_CB_FAR			0x60
#define ARM_SMMU_CB_FSYNR0		0x68
#define ARM_SMMU_CB_S1_TLBIVA		0x600
#define ARM_SMMU_CB_S1_TLBIASID		0x610
#define ARM_SMMU_CB_S1_TLBIVAL		0x620
#define ARM_SMMU_CB_S2_TLBIIPAS2	0x630
#define ARM_SMMU_CB_S2_TLBIIPAS2L	0x638
#define ARM_SMMU_CB_TLBSYNC		0x7f0
#define ARM_SMMU_CB_TLBSTATUS		0x7f4
#define ARM_SMMU_CB_ATS1PR		0x800
#define ARM_SMMU_CB_ATSR		0x8f0

#define SCTLR_S1_ASIDPNE		(1 << 12)
#define SCTLR_CFCFG			(1 << 7)
#define SCTLR_CFIE			(1 << 6)
#define SCTLR_CFRE			(1 << 5)
#define SCTLR_E				(1 << 4)
#define SCTLR_AFE			(1 << 2)
#define SCTLR_TRE			(1 << 1)
#define SCTLR_M				(1 << 0)

#define CB_PAR_F			(1 << 0)

#define ATSR_ACTIVE			(1 << 0)

#define RESUME_RETRY			(0 << 0)
#define RESUME_TERMINATE		(1 << 0)

#define TTBCR2_SEP_SHIFT		15
#define TTBCR2_SEP_UPSTREAM		(0x7 << TTBCR2_SEP_SHIFT)
#define TTBCR2_AS			(1 << 4)

#define TTBRn_ASID_SHIFT		48

#define FSR_MULTI			(1 << 31)
#define FSR_SS				(1 << 30)
#define FSR_UUT				(1 << 8)
#define FSR_ASF				(1 << 7)
#define FSR_TLBLKF			(1 << 6)
#define FSR_TLBMCF			(1 << 5)
#define FSR_EF				(1 << 4)
#define FSR_PF				(1 << 3)
#define FSR_AFF				(1 << 2)
#define FSR_TF				(1 << 1)

#define FSR_IGN				(FSR_AFF | FSR_ASF | \
					 FSR_TLBMCF | FSR_TLBLKF)
#define FSR_FAULT			(FSR_MULTI | FSR_SS | FSR_UUT | \
					 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)

#define FSYNR0_WNR			(1 << 4)

#endif /* _ARM_SMMU_REGS_H */
Commit	Line	Data
2b03774b RC	1	/*
	2	* IOMMU API for ARM architected SMMU implementations.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	16	*
	17	* Copyright (C) 2013 ARM Limited
	18	*
	19	* Author: Will Deacon <will.deacon@arm.com>
	20	*/
	21
	22	#ifndef _ARM_SMMU_REGS_H
	23	#define _ARM_SMMU_REGS_H
	24
	25	/* Configuration registers */
	26	#define ARM_SMMU_GR0_sCR0 0x0
	27	#define sCR0_CLIENTPD (1 << 0)
	28	#define sCR0_GFRE (1 << 1)
	29	#define sCR0_GFIE (1 << 2)
	30	#define sCR0_EXIDENABLE (1 << 3)
	31	#define sCR0_GCFGFRE (1 << 4)
	32	#define sCR0_GCFGFIE (1 << 5)
	33	#define sCR0_USFCFG (1 << 10)
	34	#define sCR0_VMIDPNE (1 << 11)
	35	#define sCR0_PTM (1 << 12)
	36	#define sCR0_FB (1 << 13)
	37	#define sCR0_VMID16EN (1 << 31)
	38	#define sCR0_BSU_SHIFT 14
	39	#define sCR0_BSU_MASK 0x3
	40
	41	/* Auxiliary Configuration register */
	42	#define ARM_SMMU_GR0_sACR 0x10
	43
	44	/* Identification registers */
	45	#define ARM_SMMU_GR0_ID0 0x20
	46	#define ARM_SMMU_GR0_ID1 0x24
	47	#define ARM_SMMU_GR0_ID2 0x28
	48	#define ARM_SMMU_GR0_ID3 0x2c
	49	#define ARM_SMMU_GR0_ID4 0x30
	50	#define ARM_SMMU_GR0_ID5 0x34
	51	#define ARM_SMMU_GR0_ID6 0x38
	52	#define ARM_SMMU_GR0_ID7 0x3c
	53	#define ARM_SMMU_GR0_sGFSR 0x48
	54	#define ARM_SMMU_GR0_sGFSYNR0 0x50
	55	#define ARM_SMMU_GR0_sGFSYNR1 0x54
	56	#define ARM_SMMU_GR0_sGFSYNR2 0x58
	57
	58	#define ID0_S1TS (1 << 30)
	59	#define ID0_S2TS (1 << 29)
	60	#define ID0_NTS (1 << 28)
	61	#define ID0_SMS (1 << 27)
	62	#define ID0_ATOSNS (1 << 26)
	63	#define ID0_PTFS_NO_AARCH32 (1 << 25)
	64	#define ID0_PTFS_NO_AARCH32S (1 << 24)
65	#define ID0_CTTW (1 << 14)
66	#define ID0_NUMIRPT_SHIFT 16
67	#define ID0_NUMIRPT_MASK 0xff
68	#define ID0_NUMSIDB_SHIFT 9
69	#define ID0_NUMSIDB_MASK 0xf
70	#define ID0_EXIDS (1 << 8)
71	#define ID0_NUMSMRG_SHIFT 0
72	#define ID0_NUMSMRG_MASK 0xff
73
74	#define ID1_PAGESIZE (1 << 31)
75	#define ID1_NUMPAGENDXB_SHIFT 28
76	#define ID1_NUMPAGENDXB_MASK 7
77	#define ID1_NUMS2CB_SHIFT 16
78	#define ID1_NUMS2CB_MASK 0xff
79	#define ID1_NUMCB_SHIFT 0
80	#define ID1_NUMCB_MASK 0xff
81
82	#define ID2_OAS_SHIFT 4
83	#define ID2_OAS_MASK 0xf
84	#define ID2_IAS_SHIFT 0
85	#define ID2_IAS_MASK 0xf
86	#define ID2_UBS_SHIFT 8
87	#define ID2_UBS_MASK 0xf
88	#define ID2_PTFS_4K (1 << 12)
89	#define ID2_PTFS_16K (1 << 13)
90	#define ID2_PTFS_64K (1 << 14)
91	#define ID2_VMID16 (1 << 15)
92
93	#define ID7_MAJOR_SHIFT 4
94	#define ID7_MAJOR_MASK 0xf
95
96	/* Global TLB invalidation */
97	#define ARM_SMMU_GR0_TLBIVMID 0x64
98	#define ARM_SMMU_GR0_TLBIALLNSNH 0x68
99	#define ARM_SMMU_GR0_TLBIALLH 0x6c
100	#define ARM_SMMU_GR0_sTLBGSYNC 0x70
101	#define ARM_SMMU_GR0_sTLBGSTATUS 0x74
102	#define sTLBGSTATUS_GSACTIVE (1 << 0)
103
104	/* Stream mapping registers */
105	#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
106	#define SMR_VALID (1 << 31)
107	#define SMR_MASK_SHIFT 16
108	#define SMR_ID_SHIFT 0
109
110	#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
111	#define S2CR_CBNDX_SHIFT 0
112	#define S2CR_CBNDX_MASK 0xff
113	#define S2CR_EXIDVALID (1 << 10)
114	#define S2CR_TYPE_SHIFT 16
115	#define S2CR_TYPE_MASK 0x3
116	enum arm_smmu_s2cr_type {
117	S2CR_TYPE_TRANS,
118	S2CR_TYPE_BYPASS,
119	S2CR_TYPE_FAULT,
120	};
121
122	#define S2CR_PRIVCFG_SHIFT 24
123	#define S2CR_PRIVCFG_MASK 0x3
124	enum arm_smmu_s2cr_privcfg {
125	S2CR_PRIVCFG_DEFAULT,
126	S2CR_PRIVCFG_DIPAN,
127	S2CR_PRIVCFG_UNPRIV,
128	S2CR_PRIVCFG_PRIV,
129	};
130
131	/* Context bank attribute registers */
132	#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
133	#define CBAR_VMID_SHIFT 0
134	#define CBAR_VMID_MASK 0xff
135	#define CBAR_S1_BPSHCFG_SHIFT 8
136	#define CBAR_S1_BPSHCFG_MASK 3
137	#define CBAR_S1_BPSHCFG_NSH 3
138	#define CBAR_S1_MEMATTR_SHIFT 12
139	#define CBAR_S1_MEMATTR_MASK 0xf
140	#define CBAR_S1_MEMATTR_WB 0xf
141	#define CBAR_TYPE_SHIFT 16
142	#define CBAR_TYPE_MASK 0x3
143	#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
144	#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
145	#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
146	#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
147	#define CBAR_IRPTNDX_SHIFT 24
148	#define CBAR_IRPTNDX_MASK 0xff
149
150	#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
151	#define CBA2R_RW64_32BIT (0 << 0)
152	#define CBA2R_RW64_64BIT (1 << 0)
153	#define CBA2R_VMID_SHIFT 16
154	#define CBA2R_VMID_MASK 0xffff
155
156	#define ARM_SMMU_CB_SCTLR 0x0
157	#define ARM_SMMU_CB_ACTLR 0x4
158	#define ARM_SMMU_CB_RESUME 0x8
159	#define ARM_SMMU_CB_TTBCR2 0x10
160	#define ARM_SMMU_CB_TTBR0 0x20
161	#define ARM_SMMU_CB_TTBR1 0x28
162	#define ARM_SMMU_CB_TTBCR 0x30
163	#define ARM_SMMU_CB_CONTEXTIDR 0x34
164	#define ARM_SMMU_CB_S1_MAIR0 0x38
165	#define ARM_SMMU_CB_S1_MAIR1 0x3c
166	#define ARM_SMMU_CB_PAR 0x50
167	#define ARM_SMMU_CB_FSR 0x58
168	#define ARM_SMMU_CB_FAR 0x60
169	#define ARM_SMMU_CB_FSYNR0 0x68
170	#define ARM_SMMU_CB_S1_TLBIVA 0x600
171	#define ARM_SMMU_CB_S1_TLBIASID 0x610
172	#define ARM_SMMU_CB_S1_TLBIVAL 0x620
173	#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
174	#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
175	#define ARM_SMMU_CB_TLBSYNC 0x7f0
176	#define ARM_SMMU_CB_TLBSTATUS 0x7f4
177	#define ARM_SMMU_CB_ATS1PR 0x800
178	#define ARM_SMMU_CB_ATSR 0x8f0
179
180	#define SCTLR_S1_ASIDPNE (1 << 12)
181	#define SCTLR_CFCFG (1 << 7)
182	#define SCTLR_CFIE (1 << 6)
183	#define SCTLR_CFRE (1 << 5)
184	#define SCTLR_E (1 << 4)
185	#define SCTLR_AFE (1 << 2)
186	#define SCTLR_TRE (1 << 1)
187	#define SCTLR_M (1 << 0)
188
189	#define CB_PAR_F (1 << 0)
190
191	#define ATSR_ACTIVE (1 << 0)
192
193	#define RESUME_RETRY (0 << 0)
194	#define RESUME_TERMINATE (1 << 0)
195
196	#define TTBCR2_SEP_SHIFT 15
197	#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
198	#define TTBCR2_AS (1 << 4)
199
200	#define TTBRn_ASID_SHIFT 48
201
202	#define FSR_MULTI (1 << 31)
203	#define FSR_SS (1 << 30)
204	#define FSR_UUT (1 << 8)
205	#define FSR_ASF (1 << 7)
206	#define FSR_TLBLKF (1 << 6)
207	#define FSR_TLBMCF (1 << 5)
208	#define FSR_EF (1 << 4)
209	#define FSR_PF (1 << 3)
210	#define FSR_AFF (1 << 2)
211	#define FSR_TF (1 << 1)
212
213	#define FSR_IGN (FSR_AFF \| FSR_ASF \| \
214	FSR_TLBMCF \| FSR_TLBLKF)
215	#define FSR_FAULT (FSR_MULTI \| FSR_SS \| FSR_UUT \| \
216	FSR_EF \| FSR_PF \| FSR_TF \| FSR_IGN)
217
218	#define FSYNR0_WNR (1 << 4)
219
220	#endif /* _ARM_SMMU_REGS_H */