[linux-block.git] / drivers / iommu / arm / arm-smmu / arm-smmu-qcom.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
 */

#include <linux/acpi.h>
#include <linux/adreno-smmu-priv.h>
#include <linux/delay.h>
#include <linux/of_device.h>
#include <linux/firmware/qcom/qcom_scm.h>

#include "arm-smmu.h"
#include "arm-smmu-qcom.h"

#define QCOM_DUMMY_VAL	-1

static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
{
	return container_of(smmu, struct qcom_smmu, smmu);
}

static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
				int sync, int status)
{
	unsigned int spin_cnt, delay;
	u32 reg;

	arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);
	for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
		for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
			reg = arm_smmu_readl(smmu, page, status);
			if (!(reg & ARM_SMMU_sTLBGSTATUS_GSACTIVE))
				return;
			cpu_relax();
		}
		udelay(delay);
	}

	qcom_smmu_tlb_sync_debug(smmu);
}

static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
		u32 reg)
{
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);

	/*
	 * On the GPU device we want to process subsequent transactions after a
	 * fault to keep the GPU from hanging
	 */
	reg |= ARM_SMMU_SCTLR_HUPCF;

	if (qsmmu->stall_enabled & BIT(idx))
		reg |= ARM_SMMU_SCTLR_CFCFG;

	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
}

static void qcom_adreno_smmu_get_fault_info(const void *cookie,
		struct adreno_smmu_fault_info *info)
{
	struct arm_smmu_domain *smmu_domain = (void *)cookie;
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;

	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
	info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
}

static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
{
	struct arm_smmu_domain *smmu_domain = (void *)cookie;
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);

	if (enabled)
		qsmmu->stall_enabled |= BIT(cfg->cbndx);
	else
		qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
}

static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate)
{
	struct arm_smmu_domain *smmu_domain = (void *)cookie;
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;
	u32 reg = 0;

	if (terminate)
		reg |= ARM_SMMU_RESUME_TERMINATE;

	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
}

#define QCOM_ADRENO_SMMU_GPU_SID 0

static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
{
	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
	int i;

	/*
	 * The GPU will always use SID 0 so that is a handy way to uniquely
	 * identify it and configure it for per-instance pagetables
	 */
	for (i = 0; i < fwspec->num_ids; i++) {
		u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);

		if (sid == QCOM_ADRENO_SMMU_GPU_SID)
			return true;
	}

	return false;
}

static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
		const void *cookie)
{
	struct arm_smmu_domain *smmu_domain = (void *)cookie;
	struct io_pgtable *pgtable =
		io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	return &pgtable->cfg;
}

/*
 * Local implementation to configure TTBR0 with the specified pagetable config.
 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
 * are active
 */

static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
		const struct io_pgtable_cfg *pgtbl_cfg)
{
	struct arm_smmu_domain *smmu_domain = (void *)cookie;
	struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];

	/* The domain must have split pagetables already enabled */
	if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
		return -EINVAL;

	/* If the pagetable config is NULL, disable TTBR0 */
	if (!pgtbl_cfg) {
		/* Do nothing if it is already disabled */
		if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
			return -EINVAL;

		/* Set TCR to the original configuration */
		cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
		cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
	} else {
		u32 tcr = cb->tcr[0];

		/* Don't call this again if TTBR0 is already enabled */
		if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
			return -EINVAL;

		tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
		tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);

		cb->tcr[0] = tcr;
		cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
		cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
	}

	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);

	return 0;
}

static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
					       struct arm_smmu_device *smmu,
					       struct device *dev, int start)
{
	int count;

	/*
	 * Assign context bank 0 to the GPU device so the GPU hardware can
	 * switch pagetables
	 */
	if (qcom_adreno_smmu_is_gpu_device(dev)) {
		start = 0;
		count = 1;
	} else {
		start = 1;
		count = smmu->num_context_banks;
	}

	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
}

static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
{
	const struct device_node *np = smmu->dev->of_node;

	if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))
		return false;

	return true;
}

static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
{
	struct adreno_smmu_priv *priv;

	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;

	/* Only enable split pagetables for the GPU device (SID 0) */
	if (!qcom_adreno_smmu_is_gpu_device(dev))
		return 0;

	/*
	 * All targets that use the qcom,adreno-smmu compatible string *should*
	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes
	 * that is the case when the TTBR1 quirk is enabled
	 */
	if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&
	    (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
	    (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
		pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;

	/*
	 * Initialize private interface with GPU:
	 */

	priv = dev_get_drvdata(dev);
	priv->cookie = smmu_domain;
	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
	priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
	priv->set_stall = qcom_adreno_smmu_set_stall;
	priv->resume_translation = qcom_adreno_smmu_resume_translation;

	return 0;
}

static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
	{ .compatible = "qcom,adreno" },
	{ .compatible = "qcom,mdp4" },
	{ .compatible = "qcom,mdss" },
	{ .compatible = "qcom,sc7180-mdss" },
	{ .compatible = "qcom,sc7180-mss-pil" },
	{ .compatible = "qcom,sc7280-mdss" },
	{ .compatible = "qcom,sc7280-mss-pil" },
	{ .compatible = "qcom,sc8180x-mdss" },
	{ .compatible = "qcom,sc8280xp-mdss" },
	{ .compatible = "qcom,sm8150-mdss" },
	{ .compatible = "qcom,sm8250-mdss" },
	{ .compatible = "qcom,sdm845-mdss" },
	{ .compatible = "qcom,sdm845-mss-pil" },
	{ }
};

static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
{
	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;

	return 0;
}

static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
{
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	unsigned int last_s2cr;
	u32 reg;
	u32 smr;
	int i;

	/*
	 * Some platforms support more than the Arm SMMU architected maximum of
	 * 128 stream matching groups. For unknown reasons, the additional
	 * groups don't exhibit the same behavior as the architected registers,
	 * so limit the groups to 128 until the behavior is fixed for the other
	 * groups.
	 */
	if (smmu->num_mapping_groups > 128) {
		dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
		smmu->num_mapping_groups = 128;
	}

	last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);

	/*
	 * With some firmware versions writes to S2CR of type FAULT are
	 * ignored, and writing BYPASS will end up written as FAULT in the
	 * register. Perform a write to S2CR to detect if this is the case and
	 * if so reserve a context bank to emulate bypass streams.
	 */
	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) |
	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) |
	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
	arm_smmu_gr0_write(smmu, last_s2cr, reg);
	reg = arm_smmu_gr0_read(smmu, last_s2cr);
	if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
		qsmmu->bypass_quirk = true;
		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;

		set_bit(qsmmu->bypass_cbndx, smmu->context_map);

		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);

		reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
	}

	for (i = 0; i < smmu->num_mapping_groups; i++) {
		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));

		if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
			/* Ignore valid bit for SMR mask extraction. */
			smr &= ~ARM_SMMU_SMR_VALID;
			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
			smmu->smrs[i].valid = true;

			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
			smmu->s2crs[i].cbndx = 0xff;
		}
	}

	return 0;
}

static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
{
	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	u32 cbndx = s2cr->cbndx;
	u32 type = s2cr->type;
	u32 reg;

	if (qsmmu->bypass_quirk) {
		if (type == S2CR_TYPE_BYPASS) {
			/*
			 * Firmware with quirky S2CR handling will substitute
			 * BYPASS writes with FAULT, so point the stream to the
			 * reserved context bank and ask for translation on the
			 * stream
			 */
			type = S2CR_TYPE_TRANS;
			cbndx = qsmmu->bypass_cbndx;
		} else if (type == S2CR_TYPE_FAULT) {
			/*
			 * Firmware with quirky S2CR handling will ignore FAULT
			 * writes, so trick it to write FAULT by asking for a
			 * BYPASS.
			 */
			type = S2CR_TYPE_BYPASS;
			cbndx = 0xff;
		}
	}

	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
}

static int qcom_smmu_def_domain_type(struct device *dev)
{
	const struct of_device_id *match =
		of_match_device(qcom_smmu_client_of_match, dev);

	return match ? IOMMU_DOMAIN_IDENTITY : 0;
}

static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
{
	int ret;

	arm_mmu500_reset(smmu);

	/*
	 * To address performance degradation in non-real time clients,
	 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
	 * such as MTP and db845, whose firmwares implement secure monitor
	 * call handlers to turn on/off the wait-for-safe logic.
	 */
	ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
	if (ret)
		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");

	return ret;
}

static const struct arm_smmu_impl qcom_smmu_v2_impl = {
	.init_context = qcom_smmu_init_context,
	.cfg_probe = qcom_smmu_cfg_probe,
	.def_domain_type = qcom_smmu_def_domain_type,
	.write_s2cr = qcom_smmu_write_s2cr,
	.tlb_sync = qcom_smmu_tlb_sync,
};

static const struct arm_smmu_impl qcom_smmu_500_impl = {
	.init_context = qcom_smmu_init_context,
	.cfg_probe = qcom_smmu_cfg_probe,
	.def_domain_type = qcom_smmu_def_domain_type,
	.reset = arm_mmu500_reset,
	.write_s2cr = qcom_smmu_write_s2cr,
	.tlb_sync = qcom_smmu_tlb_sync,
};

static const struct arm_smmu_impl sdm845_smmu_500_impl = {
	.init_context = qcom_smmu_init_context,
	.cfg_probe = qcom_smmu_cfg_probe,
	.def_domain_type = qcom_smmu_def_domain_type,
	.reset = qcom_sdm845_smmu500_reset,
	.write_s2cr = qcom_smmu_write_s2cr,
	.tlb_sync = qcom_smmu_tlb_sync,
};

static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
	.init_context = qcom_adreno_smmu_init_context,
	.def_domain_type = qcom_smmu_def_domain_type,
	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
	.write_sctlr = qcom_adreno_smmu_write_sctlr,
	.tlb_sync = qcom_smmu_tlb_sync,
};

static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
	.init_context = qcom_adreno_smmu_init_context,
	.def_domain_type = qcom_smmu_def_domain_type,
	.reset = arm_mmu500_reset,
	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
	.write_sctlr = qcom_adreno_smmu_write_sctlr,
	.tlb_sync = qcom_smmu_tlb_sync,
};

static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
		const struct qcom_smmu_match_data *data)
{
	const struct device_node *np = smmu->dev->of_node;
	const struct arm_smmu_impl *impl;
	struct qcom_smmu *qsmmu;

	if (!data)
		return ERR_PTR(-EINVAL);

	if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))
		impl = data->adreno_impl;
	else
		impl = data->impl;

	if (!impl)
		return smmu;

	/* Check to make sure qcom_scm has finished probing */
	if (!qcom_scm_is_available())
		return ERR_PTR(-EPROBE_DEFER);

	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
	if (!qsmmu)
		return ERR_PTR(-ENOMEM);

	qsmmu->smmu.impl = impl;
	qsmmu->cfg = data->cfg;

	return &qsmmu->smmu;
}

/* Implementation Defined Register Space 0 register offsets */
static const u32 qcom_smmu_impl0_reg_offset[] = {
	[QCOM_SMMU_TBU_PWR_STATUS]		= 0x2204,
	[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK]	= 0x25dc,
	[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR]	= 0x2670,
};

static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
	.reg_offset = qcom_smmu_impl0_reg_offset,
};

/*
 * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
 * there are not enough context banks.
 */
static const struct qcom_smmu_match_data msm8996_smmu_data = {
	.impl = NULL,
	.adreno_impl = &qcom_adreno_smmu_v2_impl,
};

static const struct qcom_smmu_match_data qcom_smmu_v2_data = {
	.impl = &qcom_smmu_v2_impl,
	.adreno_impl = &qcom_adreno_smmu_v2_impl,
};

static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
	.impl = &sdm845_smmu_500_impl,
	/*
	 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled
	 * by the separate sdm845-smmu-v2 device.
	 */
	/* Also no debug configuration. */
};

static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
	.impl = &qcom_smmu_500_impl,
	.adreno_impl = &qcom_adreno_smmu_500_impl,
	.cfg = &qcom_smmu_impl0_cfg,
};

/*
 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
 * special handling and can not be covered by the qcom,smmu-500 entry.
 */
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
	{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
	{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
	{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data  },
	{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
	{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
	{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
	{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
	{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
	{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
	{ }
};

#ifdef CONFIG_ACPI
static struct acpi_platform_list qcom_acpi_platlist[] = {
	{ "LENOVO", "CB-01   ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
	{ "QCOM  ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
	{ }
};
#endif

struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
{
	const struct device_node *np = smmu->dev->of_node;
	const struct of_device_id *match;

#ifdef CONFIG_ACPI
	if (np == NULL) {
		/* Match platform for ACPI boot */
		if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
			return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
	}
#endif

	match = of_match_node(qcom_smmu_impl_of_match, np);
	if (match)
		return qcom_smmu_create(smmu, match->data);

	return smmu;
}
Commit	Line	Data
759aaa10 VG	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Copyright (c) 2019, The Linux Foundation. All rights reserved.
	4	*/
	5
a51627c5	6	#include <linux/acpi.h>
5c7469c6	7	#include <linux/adreno-smmu-priv.h>
b9b721d1	8	#include <linux/delay.h>
0e764a01	9	#include <linux/of_device.h>
3bf90eca	10	#include <linux/firmware/qcom/qcom_scm.h>
759aaa10 VG	11
759aaa10 VG	12	#include "arm-smmu.h"
b9b721d1	13	#include "arm-smmu-qcom.h"
759aaa10	14
b9b721d1	15	#define QCOM_DUMMY_VAL -1
759aaa10	16
f9081b8f BA	17	static struct qcom_smmu to_qcom_smmu(struct arm_smmu_device smmu)
	18	{
	19	return container_of(smmu, struct qcom_smmu, smmu);
	20	}
	21
b9b721d1 SPR	22	static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
	23	int sync, int status)
	24	{
	25	unsigned int spin_cnt, delay;
	26	u32 reg;
	27
	28	arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);
	29	for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
	30	for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
	31	reg = arm_smmu_readl(smmu, page, status);
	32	if (!(reg & ARM_SMMU_sTLBGSTATUS_GSACTIVE))
	33	return;
	34	cpu_relax();
	35	}
	36	udelay(delay);
	37	}
	38
	39	qcom_smmu_tlb_sync_debug(smmu);
	40	}
	41
bffb2eaf RC	42	static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
	43	u32 reg)
	44	{
ba6014a4 RC	45	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
ba6014a4 RC	46
bffb2eaf RC	47	/*
	48	* On the GPU device we want to process subsequent transactions after a
	49	* fault to keep the GPU from hanging
	50	*/
	51	reg \|= ARM_SMMU_SCTLR_HUPCF;
	52
ba6014a4 RC	53	if (qsmmu->stall_enabled & BIT(idx))
	54	reg \|= ARM_SMMU_SCTLR_CFCFG;
	55
bffb2eaf RC	56	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
	57	}
	58
ab5df7b9 JC	59	static void qcom_adreno_smmu_get_fault_info(const void *cookie,
	60	struct adreno_smmu_fault_info *info)
	61	{
	62	struct arm_smmu_domain smmu_domain = (void )cookie;
	63	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	64	struct arm_smmu_device *smmu = smmu_domain->smmu;
	65
	66	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
	67	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
	68	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
	69	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
	70	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
c31112fb	71	info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
ab5df7b9 JC	72	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
	73	}
	74
ba6014a4 RC	75	static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
	76	{
	77	struct arm_smmu_domain smmu_domain = (void )cookie;
	78	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	79	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
	80
	81	if (enabled)
	82	qsmmu->stall_enabled \|= BIT(cfg->cbndx);
	83	else
	84	qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
	85	}
	86
	87	static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate)
	88	{
	89	struct arm_smmu_domain smmu_domain = (void )cookie;
	90	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	91	struct arm_smmu_device *smmu = smmu_domain->smmu;
	92	u32 reg = 0;
	93
	94	if (terminate)
	95	reg \|= ARM_SMMU_RESUME_TERMINATE;
	96
	97	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
	98	}
	99
5c7469c6 JC	100	#define QCOM_ADRENO_SMMU_GPU_SID 0
	101
	102	static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
	103	{
	104	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
	105	int i;
	106
	107	/*
	108	* The GPU will always use SID 0 so that is a handy way to uniquely
	109	* identify it and configure it for per-instance pagetables
	110	*/
	111	for (i = 0; i < fwspec->num_ids; i++) {
	112	u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
	113
	114	if (sid == QCOM_ADRENO_SMMU_GPU_SID)
	115	return true;
	116	}
	117
	118	return false;
	119	}
	120
	121	static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
	122	const void *cookie)
	123	{
	124	struct arm_smmu_domain smmu_domain = (void )cookie;
	125	struct io_pgtable *pgtable =
	126	io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	127	return &pgtable->cfg;
	128	}
	129
	130	/*
	131	* Local implementation to configure TTBR0 with the specified pagetable config.
	132	* The GPU driver will call this to enable TTBR0 when per-instance pagetables
	133	* are active
	134	*/
	135
	136	static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
	137	const struct io_pgtable_cfg *pgtbl_cfg)
	138	{
	139	struct arm_smmu_domain smmu_domain = (void )cookie;
	140	struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	141	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	142	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
	143
	144	/* The domain must have split pagetables already enabled */
	145	if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
	146	return -EINVAL;
	147
	148	/* If the pagetable config is NULL, disable TTBR0 */
	149	if (!pgtbl_cfg) {
	150	/* Do nothing if it is already disabled */
	151	if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
	152	return -EINVAL;
	153
	154	/* Set TCR to the original configuration */
	155	cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
	156	cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
	157	} else {
	158	u32 tcr = cb->tcr[0];
	159
	160	/* Don't call this again if TTBR0 is already enabled */
	161	if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
	162	return -EINVAL;
	163
164	tcr \|= arm_smmu_lpae_tcr(pgtbl_cfg);
165	tcr &= ~(ARM_SMMU_TCR_EPD0 \| ARM_SMMU_TCR_EPD1);
166
167	cb->tcr[0] = tcr;
168	cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
169	cb->ttbr[0] \|= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
170	}
171
172	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
173
174	return 0;
175	}
176
177	static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
178	struct arm_smmu_device *smmu,
179	struct device *dev, int start)
180	{
181	int count;
182
183	/*
184	* Assign context bank 0 to the GPU device so the GPU hardware can
185	* switch pagetables
186	*/
187	if (qcom_adreno_smmu_is_gpu_device(dev)) {
188	start = 0;
189	count = 1;
190	} else {
191	start = 1;
192	count = smmu->num_context_banks;
193	}
194
195	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
196	}
197
a242f429 EA	198	static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
	199	{
	200	const struct device_node *np = smmu->dev->of_node;
	201
	202	if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))
	203	return false;
	204
	205	return true;
	206	}
	207
5c7469c6 JC	208	static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
	209	struct io_pgtable_cfg pgtbl_cfg, struct device dev)
	210	{
	211	struct adreno_smmu_priv *priv;
	212
ef75702d SPR	213	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
ef75702d SPR	214
5c7469c6 JC	215	/* Only enable split pagetables for the GPU device (SID 0) */
	216	if (!qcom_adreno_smmu_is_gpu_device(dev))
	217	return 0;
	218
	219	/*
	220	* All targets that use the qcom,adreno-smmu compatible string should
	221	* be AARCH64 stage 1 but double check because the arm-smmu code assumes
	222	* that is the case when the TTBR1 quirk is enabled
	223	*/
a242f429 EA	224	if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&
a242f429 EA	225	(smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
5c7469c6 JC	226	(smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
	227	pgtbl_cfg->quirks \|= IO_PGTABLE_QUIRK_ARM_TTBR1;
	228
	229	/*
	230	* Initialize private interface with GPU:
	231	*/
	232
	233	priv = dev_get_drvdata(dev);
	234	priv->cookie = smmu_domain;
	235	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
	236	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
ab5df7b9	237	priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
ba6014a4 RC	238	priv->set_stall = qcom_adreno_smmu_set_stall;
ba6014a4 RC	239	priv->resume_translation = qcom_adreno_smmu_resume_translation;
5c7469c6 JC	240
	241	return 0;
	242	}
	243
a082121b	244	static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
0e764a01 JC	245	{ .compatible = "qcom,adreno" },
	246	{ .compatible = "qcom,mdp4" },
	247	{ .compatible = "qcom,mdss" },
	248	{ .compatible = "qcom,sc7180-mdss" },
d100ff38	249	{ .compatible = "qcom,sc7180-mss-pil" },
0b779f56	250	{ .compatible = "qcom,sc7280-mdss" },
e37f1fe4	251	{ .compatible = "qcom,sc7280-mss-pil" },
1a7180ff	252	{ .compatible = "qcom,sc8180x-mdss" },
5fba66d4	253	{ .compatible = "qcom,sc8280xp-mdss" },
c2b83395	254	{ .compatible = "qcom,sm8150-mdss" },
3482c0b7	255	{ .compatible = "qcom,sm8250-mdss" },
0e764a01	256	{ .compatible = "qcom,sdm845-mdss" },
d100ff38	257	{ .compatible = "qcom,sdm845-mss-pil" },
0e764a01 JC	258	{ }
	259	};
	260
ef75702d SPR	261	static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
	262	struct io_pgtable_cfg pgtbl_cfg, struct device dev)
	263	{
	264	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
	265
	266	return 0;
	267	}
	268
07a7f2ca BA	269	static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
07a7f2ca BA	270	{
f9081b8f	271	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
12261134	272	unsigned int last_s2cr;
f9081b8f	273	u32 reg;
07a7f2ca BA	274	u32 smr;
	275	int i;
	276
12261134 MS	277	/*
	278	* Some platforms support more than the Arm SMMU architected maximum of
	279	* 128 stream matching groups. For unknown reasons, the additional
	280	* groups don't exhibit the same behavior as the architected registers,
	281	* so limit the groups to 128 until the behavior is fixed for the other
	282	* groups.
	283	*/
	284	if (smmu->num_mapping_groups > 128) {
	285	dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
	286	smmu->num_mapping_groups = 128;
	287	}
	288
	289	last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
	290
f9081b8f BA	291	/*
	292	* With some firmware versions writes to S2CR of type FAULT are
	293	* ignored, and writing BYPASS will end up written as FAULT in the
	294	* register. Perform a write to S2CR to detect if this is the case and
	295	* if so reserve a context bank to emulate bypass streams.
	296	*/
	297	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) \|
	298	FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) \|
	299	FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
	300	arm_smmu_gr0_write(smmu, last_s2cr, reg);
	301	reg = arm_smmu_gr0_read(smmu, last_s2cr);
	302	if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
	303	qsmmu->bypass_quirk = true;
	304	qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
	305
	306	set_bit(qsmmu->bypass_cbndx, smmu->context_map);
	307
aded8c7c BA	308	arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
aded8c7c BA	309
f9081b8f BA	310	reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
	311	arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
	312	}
	313
07a7f2ca BA	314	for (i = 0; i < smmu->num_mapping_groups; i++) {
	315	smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
	316
	317	if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
dead723e IM	318	/* Ignore valid bit for SMR mask extraction. */
dead723e IM	319	smr &= ~ARM_SMMU_SMR_VALID;
07a7f2ca BA	320	smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
	321	smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
	322	smmu->smrs[i].valid = true;
	323
	324	smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
	325	smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
	326	smmu->s2crs[i].cbndx = 0xff;
	327	}
	328	}
	329
	330	return 0;
	331	}
	332
f9081b8f BA	333	static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
	334	{
	335	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
	336	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	337	u32 cbndx = s2cr->cbndx;
	338	u32 type = s2cr->type;
	339	u32 reg;
	340
	341	if (qsmmu->bypass_quirk) {
	342	if (type == S2CR_TYPE_BYPASS) {
	343	/*
	344	* Firmware with quirky S2CR handling will substitute
	345	* BYPASS writes with FAULT, so point the stream to the
	346	* reserved context bank and ask for translation on the
	347	* stream
	348	*/
	349	type = S2CR_TYPE_TRANS;
	350	cbndx = qsmmu->bypass_cbndx;
	351	} else if (type == S2CR_TYPE_FAULT) {
	352	/*
	353	* Firmware with quirky S2CR handling will ignore FAULT
	354	* writes, so trick it to write FAULT by asking for a
	355	* BYPASS.
	356	*/
	357	type = S2CR_TYPE_BYPASS;
	358	cbndx = 0xff;
	359	}
	360	}
	361
	362	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) \|
	363	FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) \|
	364	FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
	365	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
	366	}
	367
0e764a01 JC	368	static int qcom_smmu_def_domain_type(struct device *dev)
	369	{
	370	const struct of_device_id *match =
	371	of_match_device(qcom_smmu_client_of_match, dev);
	372
	373	return match ? IOMMU_DOMAIN_IDENTITY : 0;
	374	}
	375
759aaa10 VG	376	static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
	377	{
	378	int ret;
	379
417b76ad DB	380	arm_mmu500_reset(smmu);
417b76ad DB	381
759aaa10 VG	382	/*
	383	* To address performance degradation in non-real time clients,
	384	* such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
	385	* such as MTP and db845, whose firmwares implement secure monitor
	386	* call handlers to turn on/off the wait-for-safe logic.
	387	*/
	388	ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
	389	if (ret)
	390	dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
	391
	392	return ret;
	393	}
	394
b4c6ee51 DB	395	static const struct arm_smmu_impl qcom_smmu_v2_impl = {
	396	.init_context = qcom_smmu_init_context,
	397	.cfg_probe = qcom_smmu_cfg_probe,
	398	.def_domain_type = qcom_smmu_def_domain_type,
	399	.write_s2cr = qcom_smmu_write_s2cr,
	400	.tlb_sync = qcom_smmu_tlb_sync,
	401	};
	402
	403	static const struct arm_smmu_impl qcom_smmu_500_impl = {
ef75702d	404	.init_context = qcom_smmu_init_context,
07a7f2ca	405	.cfg_probe = qcom_smmu_cfg_probe,
0e764a01	406	.def_domain_type = qcom_smmu_def_domain_type,
417b76ad DB	407	.reset = arm_mmu500_reset,
	408	.write_s2cr = qcom_smmu_write_s2cr,
	409	.tlb_sync = qcom_smmu_tlb_sync,
	410	};
	411
	412	static const struct arm_smmu_impl sdm845_smmu_500_impl = {
	413	.init_context = qcom_smmu_init_context,
	414	.cfg_probe = qcom_smmu_cfg_probe,
	415	.def_domain_type = qcom_smmu_def_domain_type,
	416	.reset = qcom_sdm845_smmu500_reset,
f9081b8f	417	.write_s2cr = qcom_smmu_write_s2cr,
b9b721d1	418	.tlb_sync = qcom_smmu_tlb_sync,
759aaa10 VG	419	};
759aaa10 VG	420
b4c6ee51 DB	421	static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
	422	.init_context = qcom_adreno_smmu_init_context,
	423	.def_domain_type = qcom_smmu_def_domain_type,
	424	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
	425	.write_sctlr = qcom_adreno_smmu_write_sctlr,
	426	.tlb_sync = qcom_smmu_tlb_sync,
	427	};
	428
	429	static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
5c7469c6 JC	430	.init_context = qcom_adreno_smmu_init_context,
5c7469c6 JC	431	.def_domain_type = qcom_smmu_def_domain_type,
417b76ad	432	.reset = arm_mmu500_reset,
5c7469c6	433	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
bffb2eaf	434	.write_sctlr = qcom_adreno_smmu_write_sctlr,
b9b721d1	435	.tlb_sync = qcom_smmu_tlb_sync,
5c7469c6 JC	436	};
	437
	438	static struct arm_smmu_device qcom_smmu_create(struct arm_smmu_device smmu,
4c1d0ad1	439	const struct qcom_smmu_match_data *data)
759aaa10	440	{
30b912a0	441	const struct device_node *np = smmu->dev->of_node;
4c1d0ad1	442	const struct arm_smmu_impl *impl;
759aaa10 VG	443	struct qcom_smmu *qsmmu;
759aaa10 VG	444
4c1d0ad1 DB	445	if (!data)
	446	return ERR_PTR(-EINVAL);
	447
30b912a0 DB	448	if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))
	449	impl = data->adreno_impl;
	450	else
	451	impl = data->impl;
	452
4c1d0ad1 DB	453	if (!impl)
	454	return smmu;
	455
72b55c96 JS	456	/* Check to make sure qcom_scm has finished probing */
	457	if (!qcom_scm_is_available())
	458	return ERR_PTR(-EPROBE_DEFER);
	459
af9da914	460	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
759aaa10 VG	461	if (!qsmmu)
	462	return ERR_PTR(-ENOMEM);
	463
5c7469c6	464	qsmmu->smmu.impl = impl;
4172dda2	465	qsmmu->cfg = data->cfg;
759aaa10 VG	466
	467	return &qsmmu->smmu;
	468	}
5c7469c6	469
4172dda2 DB	470	/* Implementation Defined Register Space 0 register offsets */
	471	static const u32 qcom_smmu_impl0_reg_offset[] = {
	472	[QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
	473	[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
	474	[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
	475	};
	476
	477	static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
	478	.reg_offset = qcom_smmu_impl0_reg_offset,
	479	};
	480
30b912a0 DB	481	/*
	482	* It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
	483	* there are not enough context banks.
	484	*/
	485	static const struct qcom_smmu_match_data msm8996_smmu_data = {
	486	.impl = NULL,
b4c6ee51	487	.adreno_impl = &qcom_adreno_smmu_v2_impl,
4c1d0ad1 DB	488	};
4c1d0ad1 DB	489
b4c6ee51 DB	490	static const struct qcom_smmu_match_data qcom_smmu_v2_data = {
	491	.impl = &qcom_smmu_v2_impl,
	492	.adreno_impl = &qcom_adreno_smmu_v2_impl,
4c1d0ad1 DB	493	};
4c1d0ad1 DB	494
417b76ad DB	495	static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
	496	.impl = &sdm845_smmu_500_impl,
	497	/*
	498	* No need for adreno impl here. On sdm845 the Adreno SMMU is handled
	499	* by the separate sdm845-smmu-v2 device.
	500	*/
4172dda2 DB	501	/* Also no debug configuration. */
	502	};
	503
	504	static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
b4c6ee51 DB	505	.impl = &qcom_smmu_500_impl,
b4c6ee51 DB	506	.adreno_impl = &qcom_adreno_smmu_500_impl,
4172dda2	507	.cfg = &qcom_smmu_impl0_cfg,
417b76ad DB	508	};
417b76ad DB	509
80b71080 DB	510	/*
	511	* Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
	512	* special handling and can not be covered by the qcom,smmu-500 entry.
	513	*/
00597f9f	514	static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
30b912a0	515	{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
b4c6ee51	516	{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
4172dda2 DB	517	{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
	518	{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
	519	{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
	520	{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
	521	{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
	522	{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
b4c6ee51 DB	523	{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
b4c6ee51 DB	524	{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
417b76ad	525	{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
4172dda2 DB	526	{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
4172dda2 DB	527	{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
3811a728	528	{ .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
4172dda2 DB	529	{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
	530	{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
	531	{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
	532	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
	533	{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
	534	{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
80b71080	535	{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
00597f9f SPR	536	{ }
	537	};
	538
22c2d718	539	#ifdef CONFIG_ACPI
a51627c5 SG	540	static struct acpi_platform_list qcom_acpi_platlist[] = {
	541	{ "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
	542	{ "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
	543	{ }
	544	};
22c2d718	545	#endif
a51627c5	546
5c7469c6 JC	547	struct arm_smmu_device qcom_smmu_impl_init(struct arm_smmu_device smmu)
5c7469c6 JC	548	{
00597f9f	549	const struct device_node *np = smmu->dev->of_node;
4c1d0ad1	550	const struct of_device_id *match;
5c7469c6	551
22c2d718	552	#ifdef CONFIG_ACPI
a51627c5 SG	553	if (np == NULL) {
	554	/* Match platform for ACPI boot */
	555	if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
4172dda2	556	return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
a51627c5	557	}
22c2d718	558	#endif
00597f9f	559
4c1d0ad1 DB	560	match = of_match_node(qcom_smmu_impl_of_match, np);
	561	if (match)
	562	return qcom_smmu_create(smmu, match->data);
ab9a77a1	563
00597f9f	564	return smmu;
5c7469c6	565	}