[linux-block.git] / drivers / iommu / arm / arm-smmu / arm-smmu-qcom.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
 */

#include <linux/adreno-smmu-priv.h>
#include <linux/of_device.h>
#include <linux/qcom_scm.h>

#include "arm-smmu.h"

struct qcom_smmu {
	struct arm_smmu_device smmu;
	bool bypass_quirk;
	u8 bypass_cbndx;
};

static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
{
	return container_of(smmu, struct qcom_smmu, smmu);
}

static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
		u32 reg)
{
	/*
	 * On the GPU device we want to process subsequent transactions after a
	 * fault to keep the GPU from hanging
	 */
	reg |= ARM_SMMU_SCTLR_HUPCF;

	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
}

#define QCOM_ADRENO_SMMU_GPU_SID 0

static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
{
	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
	int i;

	/*
	 * The GPU will always use SID 0 so that is a handy way to uniquely
	 * identify it and configure it for per-instance pagetables
	 */
	for (i = 0; i < fwspec->num_ids; i++) {
		u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);

		if (sid == QCOM_ADRENO_SMMU_GPU_SID)
			return true;
	}

	return false;
}

static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
		const void *cookie)
{
	struct arm_smmu_domain *smmu_domain = (void *)cookie;
	struct io_pgtable *pgtable =
		io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	return &pgtable->cfg;
}

/*
 * Local implementation to configure TTBR0 with the specified pagetable config.
 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
 * are active
 */

static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
		const struct io_pgtable_cfg *pgtbl_cfg)
{
	struct arm_smmu_domain *smmu_domain = (void *)cookie;
	struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];

	/* The domain must have split pagetables already enabled */
	if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
		return -EINVAL;

	/* If the pagetable config is NULL, disable TTBR0 */
	if (!pgtbl_cfg) {
		/* Do nothing if it is already disabled */
		if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
			return -EINVAL;

		/* Set TCR to the original configuration */
		cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
		cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
	} else {
		u32 tcr = cb->tcr[0];

		/* Don't call this again if TTBR0 is already enabled */
		if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
			return -EINVAL;

		tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
		tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);

		cb->tcr[0] = tcr;
		cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
		cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
	}

	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);

	return 0;
}

static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
					       struct arm_smmu_device *smmu,
					       struct device *dev, int start)
{
	int count;

	/*
	 * Assign context bank 0 to the GPU device so the GPU hardware can
	 * switch pagetables
	 */
	if (qcom_adreno_smmu_is_gpu_device(dev)) {
		start = 0;
		count = 1;
	} else {
		start = 1;
		count = smmu->num_context_banks;
	}

	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
}

static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
{
	struct adreno_smmu_priv *priv;

	/* Only enable split pagetables for the GPU device (SID 0) */
	if (!qcom_adreno_smmu_is_gpu_device(dev))
		return 0;

	/*
	 * All targets that use the qcom,adreno-smmu compatible string *should*
	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes
	 * that is the case when the TTBR1 quirk is enabled
	 */
	if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
	    (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
		pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;

	/*
	 * Initialize private interface with GPU:
	 */

	priv = dev_get_drvdata(dev);
	priv->cookie = smmu_domain;
	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;

	return 0;
}

static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
	{ .compatible = "qcom,adreno" },
	{ .compatible = "qcom,mdp4" },
	{ .compatible = "qcom,mdss" },
	{ .compatible = "qcom,sc7180-mdss" },
	{ .compatible = "qcom,sc7180-mss-pil" },
	{ .compatible = "qcom,sdm845-mdss" },
	{ .compatible = "qcom,sdm845-mss-pil" },
	{ }
};

static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
{
	unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	u32 reg;
	u32 smr;
	int i;

	/*
	 * With some firmware versions writes to S2CR of type FAULT are
	 * ignored, and writing BYPASS will end up written as FAULT in the
	 * register. Perform a write to S2CR to detect if this is the case and
	 * if so reserve a context bank to emulate bypass streams.
	 */
	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) |
	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) |
	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
	arm_smmu_gr0_write(smmu, last_s2cr, reg);
	reg = arm_smmu_gr0_read(smmu, last_s2cr);
	if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
		qsmmu->bypass_quirk = true;
		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;

		set_bit(qsmmu->bypass_cbndx, smmu->context_map);

		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);

		reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
	}

	for (i = 0; i < smmu->num_mapping_groups; i++) {
		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));

		if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
			smmu->smrs[i].valid = true;

			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
			smmu->s2crs[i].cbndx = 0xff;
		}
	}

	return 0;
}

static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
{
	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	u32 cbndx = s2cr->cbndx;
	u32 type = s2cr->type;
	u32 reg;

	if (qsmmu->bypass_quirk) {
		if (type == S2CR_TYPE_BYPASS) {
			/*
			 * Firmware with quirky S2CR handling will substitute
			 * BYPASS writes with FAULT, so point the stream to the
			 * reserved context bank and ask for translation on the
			 * stream
			 */
			type = S2CR_TYPE_TRANS;
			cbndx = qsmmu->bypass_cbndx;
		} else if (type == S2CR_TYPE_FAULT) {
			/*
			 * Firmware with quirky S2CR handling will ignore FAULT
			 * writes, so trick it to write FAULT by asking for a
			 * BYPASS.
			 */
			type = S2CR_TYPE_BYPASS;
			cbndx = 0xff;
		}
	}

	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
}

static int qcom_smmu_def_domain_type(struct device *dev)
{
	const struct of_device_id *match =
		of_match_device(qcom_smmu_client_of_match, dev);

	return match ? IOMMU_DOMAIN_IDENTITY : 0;
}

static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
{
	int ret;

	/*
	 * To address performance degradation in non-real time clients,
	 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
	 * such as MTP and db845, whose firmwares implement secure monitor
	 * call handlers to turn on/off the wait-for-safe logic.
	 */
	ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
	if (ret)
		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");

	return ret;
}

static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
{
	const struct device_node *np = smmu->dev->of_node;

	arm_mmu500_reset(smmu);

	if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
		return qcom_sdm845_smmu500_reset(smmu);

	return 0;
}

static const struct arm_smmu_impl qcom_smmu_impl = {
	.cfg_probe = qcom_smmu_cfg_probe,
	.def_domain_type = qcom_smmu_def_domain_type,
	.reset = qcom_smmu500_reset,
	.write_s2cr = qcom_smmu_write_s2cr,
};

static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
	.init_context = qcom_adreno_smmu_init_context,
	.def_domain_type = qcom_smmu_def_domain_type,
	.reset = qcom_smmu500_reset,
	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
	.write_sctlr = qcom_adreno_smmu_write_sctlr,
};

static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
		const struct arm_smmu_impl *impl)
{
	struct qcom_smmu *qsmmu;

	/* Check to make sure qcom_scm has finished probing */
	if (!qcom_scm_is_available())
		return ERR_PTR(-EPROBE_DEFER);

	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
	if (!qsmmu)
		return ERR_PTR(-ENOMEM);

	qsmmu->smmu.impl = impl;

	return &qsmmu->smmu;
}

static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
	{ .compatible = "qcom,msm8998-smmu-v2" },
	{ .compatible = "qcom,sc7180-smmu-500" },
	{ .compatible = "qcom,sdm630-smmu-v2" },
	{ .compatible = "qcom,sdm845-smmu-500" },
	{ .compatible = "qcom,sm8150-smmu-500" },
	{ .compatible = "qcom,sm8250-smmu-500" },
	{ }
};

struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
{
	const struct device_node *np = smmu->dev->of_node;

	if (of_match_node(qcom_smmu_impl_of_match, np))
		return qcom_smmu_create(smmu, &qcom_smmu_impl);

	if (of_device_is_compatible(np, "qcom,adreno-smmu"))
		return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);

	return smmu;
}
Commit	Line	Data
759aaa10 VG	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Copyright (c) 2019, The Linux Foundation. All rights reserved.
	4	*/
	5
5c7469c6	6	#include <linux/adreno-smmu-priv.h>
0e764a01	7	#include <linux/of_device.h>
759aaa10 VG	8	#include <linux/qcom_scm.h>
	9
	10	#include "arm-smmu.h"
	11
	12	struct qcom_smmu {
	13	struct arm_smmu_device smmu;
f9081b8f BA	14	bool bypass_quirk;
f9081b8f BA	15	u8 bypass_cbndx;
759aaa10 VG	16	};
759aaa10 VG	17
f9081b8f BA	18	static struct qcom_smmu to_qcom_smmu(struct arm_smmu_device smmu)
	19	{
	20	return container_of(smmu, struct qcom_smmu, smmu);
	21	}
	22
bffb2eaf RC	23	static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
	24	u32 reg)
	25	{
	26	/*
	27	* On the GPU device we want to process subsequent transactions after a
	28	* fault to keep the GPU from hanging
	29	*/
	30	reg \|= ARM_SMMU_SCTLR_HUPCF;
	31
	32	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
	33	}
	34
5c7469c6 JC	35	#define QCOM_ADRENO_SMMU_GPU_SID 0
	36
	37	static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
	38	{
	39	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
	40	int i;
	41
	42	/*
	43	* The GPU will always use SID 0 so that is a handy way to uniquely
	44	* identify it and configure it for per-instance pagetables
	45	*/
	46	for (i = 0; i < fwspec->num_ids; i++) {
	47	u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
	48
	49	if (sid == QCOM_ADRENO_SMMU_GPU_SID)
	50	return true;
	51	}
	52
	53	return false;
	54	}
	55
	56	static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
	57	const void *cookie)
	58	{
	59	struct arm_smmu_domain smmu_domain = (void )cookie;
	60	struct io_pgtable *pgtable =
	61	io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	62	return &pgtable->cfg;
	63	}
	64
	65	/*
	66	* Local implementation to configure TTBR0 with the specified pagetable config.
	67	* The GPU driver will call this to enable TTBR0 when per-instance pagetables
	68	* are active
	69	*/
	70
	71	static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
	72	const struct io_pgtable_cfg *pgtbl_cfg)
	73	{
	74	struct arm_smmu_domain smmu_domain = (void )cookie;
	75	struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	76	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	77	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
	78
	79	/* The domain must have split pagetables already enabled */
	80	if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
	81	return -EINVAL;
	82
	83	/* If the pagetable config is NULL, disable TTBR0 */
	84	if (!pgtbl_cfg) {
	85	/* Do nothing if it is already disabled */
	86	if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
	87	return -EINVAL;
	88
	89	/* Set TCR to the original configuration */
	90	cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
	91	cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
	92	} else {
	93	u32 tcr = cb->tcr[0];
	94
	95	/* Don't call this again if TTBR0 is already enabled */
	96	if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
	97	return -EINVAL;
	98
99	tcr \|= arm_smmu_lpae_tcr(pgtbl_cfg);
100	tcr &= ~(ARM_SMMU_TCR_EPD0 \| ARM_SMMU_TCR_EPD1);
101
102	cb->tcr[0] = tcr;
103	cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
104	cb->ttbr[0] \|= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
105	}
106
107	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
108
109	return 0;
110	}
111
112	static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
113	struct arm_smmu_device *smmu,
114	struct device *dev, int start)
115	{
116	int count;
117
118	/*
119	* Assign context bank 0 to the GPU device so the GPU hardware can
120	* switch pagetables
121	*/
122	if (qcom_adreno_smmu_is_gpu_device(dev)) {
123	start = 0;
124	count = 1;
125	} else {
126	start = 1;
127	count = smmu->num_context_banks;
128	}
129
130	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
131	}
132
133	static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
134	struct io_pgtable_cfg pgtbl_cfg, struct device dev)
135	{
136	struct adreno_smmu_priv *priv;
137
138	/* Only enable split pagetables for the GPU device (SID 0) */
139	if (!qcom_adreno_smmu_is_gpu_device(dev))
140	return 0;
141
142	/*
143	* All targets that use the qcom,adreno-smmu compatible string should
144	* be AARCH64 stage 1 but double check because the arm-smmu code assumes
145	* that is the case when the TTBR1 quirk is enabled
146	*/
147	if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
148	(smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
149	pgtbl_cfg->quirks \|= IO_PGTABLE_QUIRK_ARM_TTBR1;
150
151	/*
152	* Initialize private interface with GPU:
153	*/
154
155	priv = dev_get_drvdata(dev);
156	priv->cookie = smmu_domain;
157	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
158	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
159
160	return 0;
161	}
162
a082121b	163	static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
0e764a01 JC	164	{ .compatible = "qcom,adreno" },
	165	{ .compatible = "qcom,mdp4" },
	166	{ .compatible = "qcom,mdss" },
	167	{ .compatible = "qcom,sc7180-mdss" },
d100ff38	168	{ .compatible = "qcom,sc7180-mss-pil" },
0e764a01	169	{ .compatible = "qcom,sdm845-mdss" },
d100ff38	170	{ .compatible = "qcom,sdm845-mss-pil" },
0e764a01 JC	171	{ }
	172	};
	173
07a7f2ca BA	174	static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
07a7f2ca BA	175	{
f9081b8f BA	176	unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
	177	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	178	u32 reg;
07a7f2ca BA	179	u32 smr;
	180	int i;
	181
f9081b8f BA	182	/*
	183	* With some firmware versions writes to S2CR of type FAULT are
	184	* ignored, and writing BYPASS will end up written as FAULT in the
	185	* register. Perform a write to S2CR to detect if this is the case and
	186	* if so reserve a context bank to emulate bypass streams.
	187	*/
	188	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) \|
	189	FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) \|
	190	FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
	191	arm_smmu_gr0_write(smmu, last_s2cr, reg);
	192	reg = arm_smmu_gr0_read(smmu, last_s2cr);
	193	if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
	194	qsmmu->bypass_quirk = true;
	195	qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
	196
	197	set_bit(qsmmu->bypass_cbndx, smmu->context_map);
	198
aded8c7c BA	199	arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
aded8c7c BA	200
f9081b8f BA	201	reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
	202	arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
	203	}
	204
07a7f2ca BA	205	for (i = 0; i < smmu->num_mapping_groups; i++) {
	206	smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
	207
	208	if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
	209	smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
	210	smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
	211	smmu->smrs[i].valid = true;
	212
	213	smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
	214	smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
	215	smmu->s2crs[i].cbndx = 0xff;
	216	}
	217	}
	218
	219	return 0;
	220	}
	221
f9081b8f BA	222	static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
	223	{
	224	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
	225	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	226	u32 cbndx = s2cr->cbndx;
	227	u32 type = s2cr->type;
	228	u32 reg;
	229
	230	if (qsmmu->bypass_quirk) {
	231	if (type == S2CR_TYPE_BYPASS) {
	232	/*
	233	* Firmware with quirky S2CR handling will substitute
	234	* BYPASS writes with FAULT, so point the stream to the
	235	* reserved context bank and ask for translation on the
	236	* stream
	237	*/
	238	type = S2CR_TYPE_TRANS;
	239	cbndx = qsmmu->bypass_cbndx;
	240	} else if (type == S2CR_TYPE_FAULT) {
	241	/*
	242	* Firmware with quirky S2CR handling will ignore FAULT
	243	* writes, so trick it to write FAULT by asking for a
	244	* BYPASS.
	245	*/
	246	type = S2CR_TYPE_BYPASS;
	247	cbndx = 0xff;
	248	}
	249	}
	250
	251	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) \|
	252	FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) \|
	253	FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
	254	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
	255	}
	256
0e764a01 JC	257	static int qcom_smmu_def_domain_type(struct device *dev)
	258	{
	259	const struct of_device_id *match =
	260	of_match_device(qcom_smmu_client_of_match, dev);
	261
	262	return match ? IOMMU_DOMAIN_IDENTITY : 0;
	263	}
	264
759aaa10 VG	265	static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
	266	{
	267	int ret;
	268
759aaa10 VG	269	/*
	270	* To address performance degradation in non-real time clients,
	271	* such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
	272	* such as MTP and db845, whose firmwares implement secure monitor
	273	* call handlers to turn on/off the wait-for-safe logic.
	274	*/
	275	ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
	276	if (ret)
	277	dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
	278
	279	return ret;
	280	}
	281
64510ede SPR	282	static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
	283	{
	284	const struct device_node *np = smmu->dev->of_node;
	285
	286	arm_mmu500_reset(smmu);
	287
	288	if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
	289	return qcom_sdm845_smmu500_reset(smmu);
	290
	291	return 0;
	292	}
	293
759aaa10	294	static const struct arm_smmu_impl qcom_smmu_impl = {
07a7f2ca	295	.cfg_probe = qcom_smmu_cfg_probe,
0e764a01	296	.def_domain_type = qcom_smmu_def_domain_type,
64510ede	297	.reset = qcom_smmu500_reset,
f9081b8f	298	.write_s2cr = qcom_smmu_write_s2cr,
759aaa10 VG	299	};
759aaa10 VG	300
5c7469c6 JC	301	static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
	302	.init_context = qcom_adreno_smmu_init_context,
	303	.def_domain_type = qcom_smmu_def_domain_type,
	304	.reset = qcom_smmu500_reset,
	305	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
bffb2eaf	306	.write_sctlr = qcom_adreno_smmu_write_sctlr,
5c7469c6 JC	307	};
	308
	309	static struct arm_smmu_device qcom_smmu_create(struct arm_smmu_device smmu,
	310	const struct arm_smmu_impl *impl)
759aaa10 VG	311	{
	312	struct qcom_smmu *qsmmu;
	313
72b55c96 JS	314	/* Check to make sure qcom_scm has finished probing */
	315	if (!qcom_scm_is_available())
	316	return ERR_PTR(-EPROBE_DEFER);
	317
af9da914	318	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
759aaa10 VG	319	if (!qsmmu)
	320	return ERR_PTR(-ENOMEM);
	321
5c7469c6	322	qsmmu->smmu.impl = impl;
759aaa10 VG	323
	324	return &qsmmu->smmu;
	325	}
5c7469c6	326
00597f9f	327	static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
b812834b	328	{ .compatible = "qcom,msm8998-smmu-v2" },
00597f9f	329	{ .compatible = "qcom,sc7180-smmu-500" },
b812834b	330	{ .compatible = "qcom,sdm630-smmu-v2" },
00597f9f SPR	331	{ .compatible = "qcom,sdm845-smmu-500" },
	332	{ .compatible = "qcom,sm8150-smmu-500" },
	333	{ .compatible = "qcom,sm8250-smmu-500" },
	334	{ }
	335	};
	336
5c7469c6 JC	337	struct arm_smmu_device qcom_smmu_impl_init(struct arm_smmu_device smmu)
5c7469c6 JC	338	{
00597f9f	339	const struct device_node *np = smmu->dev->of_node;
5c7469c6	340
00597f9f SPR	341	if (of_match_node(qcom_smmu_impl_of_match, np))
	342	return qcom_smmu_create(smmu, &qcom_smmu_impl);
	343
	344	if (of_device_is_compatible(np, "qcom,adreno-smmu"))
	345	return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
	346
	347	return smmu;
5c7469c6	348	}