[linux-block.git] / drivers / iommu / arm / arm-smmu / arm-smmu-qcom.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
 */

#include <linux/adreno-smmu-priv.h>
#include <linux/of_device.h>
#include <linux/qcom_scm.h>

#include "arm-smmu.h"

struct qcom_smmu {
	struct arm_smmu_device smmu;
	bool bypass_quirk;
	u8 bypass_cbndx;
};

static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
{
	return container_of(smmu, struct qcom_smmu, smmu);
}

#define QCOM_ADRENO_SMMU_GPU_SID 0

static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
{
	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
	int i;

	/*
	 * The GPU will always use SID 0 so that is a handy way to uniquely
	 * identify it and configure it for per-instance pagetables
	 */
	for (i = 0; i < fwspec->num_ids; i++) {
		u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);

		if (sid == QCOM_ADRENO_SMMU_GPU_SID)
			return true;
	}

	return false;
}

static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
		const void *cookie)
{
	struct arm_smmu_domain *smmu_domain = (void *)cookie;
	struct io_pgtable *pgtable =
		io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	return &pgtable->cfg;
}

/*
 * Local implementation to configure TTBR0 with the specified pagetable config.
 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
 * are active
 */

static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
		const struct io_pgtable_cfg *pgtbl_cfg)
{
	struct arm_smmu_domain *smmu_domain = (void *)cookie;
	struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];

	/* The domain must have split pagetables already enabled */
	if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
		return -EINVAL;

	/* If the pagetable config is NULL, disable TTBR0 */
	if (!pgtbl_cfg) {
		/* Do nothing if it is already disabled */
		if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
			return -EINVAL;

		/* Set TCR to the original configuration */
		cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
		cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
	} else {
		u32 tcr = cb->tcr[0];

		/* Don't call this again if TTBR0 is already enabled */
		if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
			return -EINVAL;

		tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
		tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);

		cb->tcr[0] = tcr;
		cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
		cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
	}

	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);

	return 0;
}

static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
					       struct arm_smmu_device *smmu,
					       struct device *dev, int start)
{
	int count;

	/*
	 * Assign context bank 0 to the GPU device so the GPU hardware can
	 * switch pagetables
	 */
	if (qcom_adreno_smmu_is_gpu_device(dev)) {
		start = 0;
		count = 1;
	} else {
		start = 1;
		count = smmu->num_context_banks;
	}

	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
}

static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
{
	struct adreno_smmu_priv *priv;

	/* Only enable split pagetables for the GPU device (SID 0) */
	if (!qcom_adreno_smmu_is_gpu_device(dev))
		return 0;

	/*
	 * All targets that use the qcom,adreno-smmu compatible string *should*
	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes
	 * that is the case when the TTBR1 quirk is enabled
	 */
	if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
	    (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
		pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;

	/*
	 * Initialize private interface with GPU:
	 */

	priv = dev_get_drvdata(dev);
	priv->cookie = smmu_domain;
	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;

	return 0;
}

static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
	{ .compatible = "qcom,adreno" },
	{ .compatible = "qcom,mdp4" },
	{ .compatible = "qcom,mdss" },
	{ .compatible = "qcom,sc7180-mdss" },
	{ .compatible = "qcom,sc7180-mss-pil" },
	{ .compatible = "qcom,sdm845-mdss" },
	{ .compatible = "qcom,sdm845-mss-pil" },
	{ }
};

static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
{
	unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	u32 reg;
	u32 smr;
	int i;

	/*
	 * With some firmware versions writes to S2CR of type FAULT are
	 * ignored, and writing BYPASS will end up written as FAULT in the
	 * register. Perform a write to S2CR to detect if this is the case and
	 * if so reserve a context bank to emulate bypass streams.
	 */
	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) |
	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) |
	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
	arm_smmu_gr0_write(smmu, last_s2cr, reg);
	reg = arm_smmu_gr0_read(smmu, last_s2cr);
	if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
		qsmmu->bypass_quirk = true;
		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;

		set_bit(qsmmu->bypass_cbndx, smmu->context_map);

		reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
	}

	for (i = 0; i < smmu->num_mapping_groups; i++) {
		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));

		if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
			smmu->smrs[i].valid = true;

			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
			smmu->s2crs[i].cbndx = 0xff;
		}
	}

	return 0;
}

static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
{
	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	u32 cbndx = s2cr->cbndx;
	u32 type = s2cr->type;
	u32 reg;

	if (qsmmu->bypass_quirk) {
		if (type == S2CR_TYPE_BYPASS) {
			/*
			 * Firmware with quirky S2CR handling will substitute
			 * BYPASS writes with FAULT, so point the stream to the
			 * reserved context bank and ask for translation on the
			 * stream
			 */
			type = S2CR_TYPE_TRANS;
			cbndx = qsmmu->bypass_cbndx;
		} else if (type == S2CR_TYPE_FAULT) {
			/*
			 * Firmware with quirky S2CR handling will ignore FAULT
			 * writes, so trick it to write FAULT by asking for a
			 * BYPASS.
			 */
			type = S2CR_TYPE_BYPASS;
			cbndx = 0xff;
		}
	}

	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
}

static int qcom_smmu_def_domain_type(struct device *dev)
{
	const struct of_device_id *match =
		of_match_device(qcom_smmu_client_of_match, dev);

	return match ? IOMMU_DOMAIN_IDENTITY : 0;
}

static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
{
	int ret;

	/*
	 * To address performance degradation in non-real time clients,
	 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
	 * such as MTP and db845, whose firmwares implement secure monitor
	 * call handlers to turn on/off the wait-for-safe logic.
	 */
	ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
	if (ret)
		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");

	return ret;
}

static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
{
	const struct device_node *np = smmu->dev->of_node;

	arm_mmu500_reset(smmu);

	if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
		return qcom_sdm845_smmu500_reset(smmu);

	return 0;
}

static const struct arm_smmu_impl qcom_smmu_impl = {
	.cfg_probe = qcom_smmu_cfg_probe,
	.def_domain_type = qcom_smmu_def_domain_type,
	.reset = qcom_smmu500_reset,
	.write_s2cr = qcom_smmu_write_s2cr,
};

static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
	.init_context = qcom_adreno_smmu_init_context,
	.def_domain_type = qcom_smmu_def_domain_type,
	.reset = qcom_smmu500_reset,
	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
};

static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
		const struct arm_smmu_impl *impl)
{
	struct qcom_smmu *qsmmu;

	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
	if (!qsmmu)
		return ERR_PTR(-ENOMEM);

	qsmmu->smmu.impl = impl;

	return &qsmmu->smmu;
}

struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
{
	return qcom_smmu_create(smmu, &qcom_smmu_impl);
}

struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu)
{
	return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
}
Commit	Line	Data
759aaa10 VG	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Copyright (c) 2019, The Linux Foundation. All rights reserved.
	4	*/
	5
5c7469c6	6	#include <linux/adreno-smmu-priv.h>
0e764a01	7	#include <linux/of_device.h>
759aaa10 VG	8	#include <linux/qcom_scm.h>
	9
	10	#include "arm-smmu.h"
	11
	12	struct qcom_smmu {
	13	struct arm_smmu_device smmu;
f9081b8f BA	14	bool bypass_quirk;
f9081b8f BA	15	u8 bypass_cbndx;
759aaa10 VG	16	};
759aaa10 VG	17
f9081b8f BA	18	static struct qcom_smmu to_qcom_smmu(struct arm_smmu_device smmu)
	19	{
	20	return container_of(smmu, struct qcom_smmu, smmu);
	21	}
	22
5c7469c6 JC	23	#define QCOM_ADRENO_SMMU_GPU_SID 0
	24
	25	static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
	26	{
	27	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
	28	int i;
	29
	30	/*
	31	* The GPU will always use SID 0 so that is a handy way to uniquely
	32	* identify it and configure it for per-instance pagetables
	33	*/
	34	for (i = 0; i < fwspec->num_ids; i++) {
	35	u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
	36
	37	if (sid == QCOM_ADRENO_SMMU_GPU_SID)
	38	return true;
	39	}
	40
	41	return false;
	42	}
	43
	44	static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
	45	const void *cookie)
	46	{
	47	struct arm_smmu_domain smmu_domain = (void )cookie;
	48	struct io_pgtable *pgtable =
	49	io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	50	return &pgtable->cfg;
	51	}
	52
	53	/*
	54	* Local implementation to configure TTBR0 with the specified pagetable config.
	55	* The GPU driver will call this to enable TTBR0 when per-instance pagetables
	56	* are active
	57	*/
	58
	59	static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
	60	const struct io_pgtable_cfg *pgtbl_cfg)
	61	{
	62	struct arm_smmu_domain smmu_domain = (void )cookie;
	63	struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
	64	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	65	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
	66
	67	/* The domain must have split pagetables already enabled */
	68	if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
	69	return -EINVAL;
	70
	71	/* If the pagetable config is NULL, disable TTBR0 */
	72	if (!pgtbl_cfg) {
	73	/* Do nothing if it is already disabled */
	74	if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
	75	return -EINVAL;
	76
	77	/* Set TCR to the original configuration */
	78	cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
	79	cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
	80	} else {
	81	u32 tcr = cb->tcr[0];
	82
	83	/* Don't call this again if TTBR0 is already enabled */
	84	if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
	85	return -EINVAL;
	86
87	tcr \|= arm_smmu_lpae_tcr(pgtbl_cfg);
88	tcr &= ~(ARM_SMMU_TCR_EPD0 \| ARM_SMMU_TCR_EPD1);
89
90	cb->tcr[0] = tcr;
91	cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
92	cb->ttbr[0] \|= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
93	}
94
95	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
96
97	return 0;
98	}
99
100	static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
101	struct arm_smmu_device *smmu,
102	struct device *dev, int start)
103	{
104	int count;
105
106	/*
107	* Assign context bank 0 to the GPU device so the GPU hardware can
108	* switch pagetables
109	*/
110	if (qcom_adreno_smmu_is_gpu_device(dev)) {
111	start = 0;
112	count = 1;
113	} else {
114	start = 1;
115	count = smmu->num_context_banks;
116	}
117
118	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
119	}
120
121	static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
122	struct io_pgtable_cfg pgtbl_cfg, struct device dev)
123	{
124	struct adreno_smmu_priv *priv;
125
126	/* Only enable split pagetables for the GPU device (SID 0) */
127	if (!qcom_adreno_smmu_is_gpu_device(dev))
128	return 0;
129
130	/*
131	* All targets that use the qcom,adreno-smmu compatible string should
132	* be AARCH64 stage 1 but double check because the arm-smmu code assumes
133	* that is the case when the TTBR1 quirk is enabled
134	*/
135	if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
136	(smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
137	pgtbl_cfg->quirks \|= IO_PGTABLE_QUIRK_ARM_TTBR1;
138
139	/*
140	* Initialize private interface with GPU:
141	*/
142
143	priv = dev_get_drvdata(dev);
144	priv->cookie = smmu_domain;
145	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
146	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
147
148	return 0;
149	}
150
a082121b	151	static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
0e764a01 JC	152	{ .compatible = "qcom,adreno" },
	153	{ .compatible = "qcom,mdp4" },
	154	{ .compatible = "qcom,mdss" },
	155	{ .compatible = "qcom,sc7180-mdss" },
d100ff38	156	{ .compatible = "qcom,sc7180-mss-pil" },
0e764a01	157	{ .compatible = "qcom,sdm845-mdss" },
d100ff38	158	{ .compatible = "qcom,sdm845-mss-pil" },
0e764a01 JC	159	{ }
	160	};
	161
07a7f2ca BA	162	static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
07a7f2ca BA	163	{
f9081b8f BA	164	unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
	165	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	166	u32 reg;
07a7f2ca BA	167	u32 smr;
	168	int i;
	169
f9081b8f BA	170	/*
	171	* With some firmware versions writes to S2CR of type FAULT are
	172	* ignored, and writing BYPASS will end up written as FAULT in the
	173	* register. Perform a write to S2CR to detect if this is the case and
	174	* if so reserve a context bank to emulate bypass streams.
	175	*/
	176	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) \|
	177	FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) \|
	178	FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
	179	arm_smmu_gr0_write(smmu, last_s2cr, reg);
	180	reg = arm_smmu_gr0_read(smmu, last_s2cr);
	181	if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
	182	qsmmu->bypass_quirk = true;
	183	qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
	184
	185	set_bit(qsmmu->bypass_cbndx, smmu->context_map);
	186
	187	reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
	188	arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
	189	}
	190
07a7f2ca BA	191	for (i = 0; i < smmu->num_mapping_groups; i++) {
	192	smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
	193
	194	if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
	195	smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
	196	smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
	197	smmu->smrs[i].valid = true;
	198
	199	smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
	200	smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
	201	smmu->s2crs[i].cbndx = 0xff;
	202	}
	203	}
	204
	205	return 0;
	206	}
	207
f9081b8f BA	208	static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
	209	{
	210	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
	211	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	212	u32 cbndx = s2cr->cbndx;
	213	u32 type = s2cr->type;
	214	u32 reg;
	215
	216	if (qsmmu->bypass_quirk) {
	217	if (type == S2CR_TYPE_BYPASS) {
	218	/*
	219	* Firmware with quirky S2CR handling will substitute
	220	* BYPASS writes with FAULT, so point the stream to the
	221	* reserved context bank and ask for translation on the
	222	* stream
	223	*/
	224	type = S2CR_TYPE_TRANS;
	225	cbndx = qsmmu->bypass_cbndx;
	226	} else if (type == S2CR_TYPE_FAULT) {
	227	/*
	228	* Firmware with quirky S2CR handling will ignore FAULT
	229	* writes, so trick it to write FAULT by asking for a
	230	* BYPASS.
	231	*/
	232	type = S2CR_TYPE_BYPASS;
	233	cbndx = 0xff;
	234	}
	235	}
	236
	237	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) \|
	238	FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) \|
	239	FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
	240	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
	241	}
	242
0e764a01 JC	243	static int qcom_smmu_def_domain_type(struct device *dev)
	244	{
	245	const struct of_device_id *match =
	246	of_match_device(qcom_smmu_client_of_match, dev);
	247
	248	return match ? IOMMU_DOMAIN_IDENTITY : 0;
	249	}
	250
759aaa10 VG	251	static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
	252	{
	253	int ret;
	254
759aaa10 VG	255	/*
	256	* To address performance degradation in non-real time clients,
	257	* such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
	258	* such as MTP and db845, whose firmwares implement secure monitor
	259	* call handlers to turn on/off the wait-for-safe logic.
	260	*/
	261	ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
	262	if (ret)
	263	dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
	264
	265	return ret;
	266	}
	267
64510ede SPR	268	static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
	269	{
	270	const struct device_node *np = smmu->dev->of_node;
	271
	272	arm_mmu500_reset(smmu);
	273
	274	if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
	275	return qcom_sdm845_smmu500_reset(smmu);
	276
	277	return 0;
	278	}
	279
759aaa10	280	static const struct arm_smmu_impl qcom_smmu_impl = {
07a7f2ca	281	.cfg_probe = qcom_smmu_cfg_probe,
0e764a01	282	.def_domain_type = qcom_smmu_def_domain_type,
64510ede	283	.reset = qcom_smmu500_reset,
f9081b8f	284	.write_s2cr = qcom_smmu_write_s2cr,
759aaa10 VG	285	};
759aaa10 VG	286
5c7469c6 JC	287	static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
	288	.init_context = qcom_adreno_smmu_init_context,
	289	.def_domain_type = qcom_smmu_def_domain_type,
	290	.reset = qcom_smmu500_reset,
	291	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
	292	};
	293
	294	static struct arm_smmu_device qcom_smmu_create(struct arm_smmu_device smmu,
	295	const struct arm_smmu_impl *impl)
759aaa10 VG	296	{
	297	struct qcom_smmu *qsmmu;
	298
af9da914	299	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
759aaa10 VG	300	if (!qsmmu)
	301	return ERR_PTR(-ENOMEM);
	302
5c7469c6	303	qsmmu->smmu.impl = impl;
759aaa10 VG	304
	305	return &qsmmu->smmu;
	306	}
5c7469c6 JC	307
	308	struct arm_smmu_device qcom_smmu_impl_init(struct arm_smmu_device smmu)
	309	{
	310	return qcom_smmu_create(smmu, &qcom_smmu_impl);
	311	}
	312
	313	struct arm_smmu_device qcom_adreno_smmu_impl_init(struct arm_smmu_device smmu)
	314	{
	315	return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
	316	}