Commit | Line | Data |
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45051539 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
8d283c35 | 2 | /* |
5d0d7156 | 3 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 4 | * Author: Joerg Roedel <jroedel@suse.de> |
8d283c35 | 5 | * Leo Duran <leo.duran@amd.com> |
8d283c35 JR |
6 | */ |
7 | ||
1965aae3 PA |
8 | #ifndef _ASM_X86_AMD_IOMMU_TYPES_H |
9 | #define _ASM_X86_AMD_IOMMU_TYPES_H | |
8d283c35 JR |
10 | |
11 | #include <linux/types.h> | |
5d214fe6 | 12 | #include <linux/mutex.h> |
a38180bd | 13 | #include <linux/msi.h> |
8d283c35 JR |
14 | #include <linux/list.h> |
15 | #include <linux/spinlock.h> | |
c5081cd7 | 16 | #include <linux/pci.h> |
4b180d97 | 17 | #include <linux/irqreturn.h> |
8d283c35 | 18 | |
bb52777e JR |
19 | /* |
20 | * Maximum number of IOMMUs supported | |
21 | */ | |
22 | #define MAX_IOMMUS 32 | |
23 | ||
8d283c35 JR |
24 | /* |
25 | * some size calculation constants | |
26 | */ | |
83f5aac1 | 27 | #define DEV_TABLE_ENTRY_SIZE 32 |
8d283c35 JR |
28 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
29 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) | |
30 | ||
8d283c35 JR |
31 | /* Capability offsets used by the driver */ |
32 | #define MMIO_CAP_HDR_OFFSET 0x00 | |
33 | #define MMIO_RANGE_OFFSET 0x0c | |
a80dc3e0 | 34 | #define MMIO_MISC_OFFSET 0x10 |
8d283c35 JR |
35 | |
36 | /* Masks, shifts and macros to parse the device range capability */ | |
37 | #define MMIO_RANGE_LD_MASK 0xff000000 | |
38 | #define MMIO_RANGE_FD_MASK 0x00ff0000 | |
39 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 | |
40 | #define MMIO_RANGE_LD_SHIFT 24 | |
41 | #define MMIO_RANGE_FD_SHIFT 16 | |
42 | #define MMIO_RANGE_BUS_SHIFT 8 | |
43 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) | |
44 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) | |
45 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) | |
a80dc3e0 | 46 | #define MMIO_MSI_NUM(x) ((x) & 0x1f) |
8d283c35 JR |
47 | |
48 | /* Flag masks for the AMD IOMMU exclusion range */ | |
49 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL | |
50 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL | |
51 | ||
52 | /* Used offsets into the MMIO space */ | |
53 | #define MMIO_DEV_TABLE_OFFSET 0x0000 | |
54 | #define MMIO_CMD_BUF_OFFSET 0x0008 | |
55 | #define MMIO_EVT_BUF_OFFSET 0x0010 | |
56 | #define MMIO_CONTROL_OFFSET 0x0018 | |
57 | #define MMIO_EXCL_BASE_OFFSET 0x0020 | |
58 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 | |
d99ddec3 | 59 | #define MMIO_EXT_FEATURES 0x0030 |
1a29ac01 | 60 | #define MMIO_PPR_LOG_OFFSET 0x0038 |
8bda0cfb SS |
61 | #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 |
62 | #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8 | |
66929812 SS |
63 | #define MMIO_MSI_ADDR_LO_OFFSET 0x015C |
64 | #define MMIO_MSI_ADDR_HI_OFFSET 0x0160 | |
65 | #define MMIO_MSI_DATA_OFFSET 0x0164 | |
66 | #define MMIO_INTCAPXT_EVT_OFFSET 0x0170 | |
67 | #define MMIO_INTCAPXT_PPR_OFFSET 0x0178 | |
68 | #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180 | |
8d283c35 JR |
69 | #define MMIO_CMD_HEAD_OFFSET 0x2000 |
70 | #define MMIO_CMD_TAIL_OFFSET 0x2008 | |
71 | #define MMIO_EVT_HEAD_OFFSET 0x2010 | |
72 | #define MMIO_EVT_TAIL_OFFSET 0x2018 | |
73 | #define MMIO_STATUS_OFFSET 0x2020 | |
1a29ac01 JR |
74 | #define MMIO_PPR_HEAD_OFFSET 0x2030 |
75 | #define MMIO_PPR_TAIL_OFFSET 0x2038 | |
8bda0cfb SS |
76 | #define MMIO_GA_HEAD_OFFSET 0x2040 |
77 | #define MMIO_GA_TAIL_OFFSET 0x2048 | |
30861ddc SK |
78 | #define MMIO_CNTR_CONF_OFFSET 0x4000 |
79 | #define MMIO_CNTR_REG_OFFSET 0x40000 | |
80 | #define MMIO_REG_END_OFFSET 0x80000 | |
81 | ||
8d283c35 | 82 | |
d99ddec3 JR |
83 | |
84 | /* Extended Feature Bits */ | |
85 | #define FEATURE_PREFETCH (1ULL<<0) | |
86 | #define FEATURE_PPR (1ULL<<1) | |
87 | #define FEATURE_X2APIC (1ULL<<2) | |
88 | #define FEATURE_NX (1ULL<<3) | |
89 | #define FEATURE_GT (1ULL<<4) | |
90 | #define FEATURE_IA (1ULL<<6) | |
91 | #define FEATURE_GA (1ULL<<7) | |
92 | #define FEATURE_HE (1ULL<<8) | |
93 | #define FEATURE_PC (1ULL<<9) | |
3928aa3f | 94 | #define FEATURE_GAM_VAPIC (1ULL<<21) |
ff18c4e5 | 95 | #define FEATURE_EPHSUP (1ULL<<50) |
d99ddec3 | 96 | |
62f71abb JR |
97 | #define FEATURE_PASID_SHIFT 32 |
98 | #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) | |
99 | ||
52815b75 JR |
100 | #define FEATURE_GLXVAL_SHIFT 14 |
101 | #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) | |
102 | ||
a919a018 SS |
103 | /* Note: |
104 | * The current driver only support 16-bit PASID. | |
105 | * Currently, hardware only implement upto 16-bit PASID | |
106 | * even though the spec says it could have upto 20 bits. | |
107 | */ | |
108 | #define PASID_MASK 0x0000ffff | |
52815b75 | 109 | |
519c31ba | 110 | /* MMIO status bits */ |
925fe08b | 111 | #define MMIO_STATUS_EVT_INT_MASK (1 << 1) |
72e1dcc4 JR |
112 | #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) |
113 | #define MMIO_STATUS_PPR_INT_MASK (1 << 6) | |
8bda0cfb SS |
114 | #define MMIO_STATUS_GALOG_RUN_MASK (1 << 8) |
115 | #define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9) | |
116 | #define MMIO_STATUS_GALOG_INT_MASK (1 << 10) | |
519c31ba | 117 | |
90008ee4 JR |
118 | /* event logging constants */ |
119 | #define EVENT_ENTRY_SIZE 0x10 | |
120 | #define EVENT_TYPE_SHIFT 28 | |
121 | #define EVENT_TYPE_MASK 0xf | |
122 | #define EVENT_TYPE_ILL_DEV 0x1 | |
123 | #define EVENT_TYPE_IO_FAULT 0x2 | |
124 | #define EVENT_TYPE_DEV_TAB_ERR 0x3 | |
125 | #define EVENT_TYPE_PAGE_TAB_ERR 0x4 | |
126 | #define EVENT_TYPE_ILL_CMD 0x5 | |
127 | #define EVENT_TYPE_CMD_HARD_ERR 0x6 | |
128 | #define EVENT_TYPE_IOTLB_INV_TO 0x7 | |
129 | #define EVENT_TYPE_INV_DEV_REQ 0x8 | |
e7f63ffc | 130 | #define EVENT_TYPE_INV_PPR_REQ 0x9 |
90008ee4 JR |
131 | #define EVENT_DEVID_MASK 0xffff |
132 | #define EVENT_DEVID_SHIFT 0 | |
ec21f17a SS |
133 | #define EVENT_DOMID_MASK_LO 0xffff |
134 | #define EVENT_DOMID_MASK_HI 0xf0000 | |
90008ee4 JR |
135 | #define EVENT_FLAGS_MASK 0xfff |
136 | #define EVENT_FLAGS_SHIFT 0x10 | |
137 | ||
8d283c35 JR |
138 | /* feature control bits */ |
139 | #define CONTROL_IOMMU_EN 0x00ULL | |
140 | #define CONTROL_HT_TUN_EN 0x01ULL | |
141 | #define CONTROL_EVT_LOG_EN 0x02ULL | |
142 | #define CONTROL_EVT_INT_EN 0x03ULL | |
143 | #define CONTROL_COMWAIT_EN 0x04ULL | |
1456e9d2 | 144 | #define CONTROL_INV_TIMEOUT 0x05ULL |
8d283c35 JR |
145 | #define CONTROL_PASSPW_EN 0x08ULL |
146 | #define CONTROL_RESPASSPW_EN 0x09ULL | |
147 | #define CONTROL_COHERENT_EN 0x0aULL | |
148 | #define CONTROL_ISOC_EN 0x0bULL | |
149 | #define CONTROL_CMDBUF_EN 0x0cULL | |
bde9e6b9 AH |
150 | #define CONTROL_PPRLOG_EN 0x0dULL |
151 | #define CONTROL_PPRINT_EN 0x0eULL | |
1a29ac01 | 152 | #define CONTROL_PPR_EN 0x0fULL |
cbc33a90 | 153 | #define CONTROL_GT_EN 0x10ULL |
3928aa3f SS |
154 | #define CONTROL_GA_EN 0x11ULL |
155 | #define CONTROL_GAM_EN 0x19ULL | |
8bda0cfb SS |
156 | #define CONTROL_GALOG_EN 0x1CULL |
157 | #define CONTROL_GAINT_EN 0x1DULL | |
90fcffd9 | 158 | #define CONTROL_XT_EN 0x32ULL |
66929812 | 159 | #define CONTROL_INTCAPXT_EN 0x33ULL |
8d283c35 | 160 | |
1456e9d2 JR |
161 | #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) |
162 | #define CTRL_INV_TO_NONE 0 | |
163 | #define CTRL_INV_TO_1MS 1 | |
164 | #define CTRL_INV_TO_10MS 2 | |
165 | #define CTRL_INV_TO_100MS 3 | |
166 | #define CTRL_INV_TO_1S 4 | |
167 | #define CTRL_INV_TO_10S 5 | |
168 | #define CTRL_INV_TO_100S 6 | |
169 | ||
8d283c35 JR |
170 | /* command specific defines */ |
171 | #define CMD_COMPL_WAIT 0x01 | |
172 | #define CMD_INV_DEV_ENTRY 0x02 | |
cb41ed85 JR |
173 | #define CMD_INV_IOMMU_PAGES 0x03 |
174 | #define CMD_INV_IOTLB_PAGES 0x04 | |
7ef2798d | 175 | #define CMD_INV_IRT 0x05 |
c99afa25 | 176 | #define CMD_COMPLETE_PPR 0x07 |
58fc7f14 | 177 | #define CMD_INV_ALL 0x08 |
8d283c35 JR |
178 | |
179 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 | |
519c31ba | 180 | #define CMD_COMPL_WAIT_INT_MASK 0x02 |
8d283c35 JR |
181 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
182 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 | |
22e266c7 | 183 | #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 |
8d283c35 | 184 | |
c99afa25 JR |
185 | #define PPR_STATUS_MASK 0xf |
186 | #define PPR_STATUS_SHIFT 12 | |
187 | ||
999ba417 JR |
188 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
189 | ||
8d283c35 JR |
190 | /* macros and definitions for device table entries */ |
191 | #define DEV_ENTRY_VALID 0x00 | |
192 | #define DEV_ENTRY_TRANSLATION 0x01 | |
ff18c4e5 | 193 | #define DEV_ENTRY_PPR 0x34 |
8d283c35 JR |
194 | #define DEV_ENTRY_IR 0x3d |
195 | #define DEV_ENTRY_IW 0x3e | |
9f5f5fb3 | 196 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
8d283c35 JR |
197 | #define DEV_ENTRY_EX 0x67 |
198 | #define DEV_ENTRY_SYSMGT1 0x68 | |
199 | #define DEV_ENTRY_SYSMGT2 0x69 | |
0ea2c422 | 200 | #define DEV_ENTRY_IRQ_TBL_EN 0x80 |
8d283c35 JR |
201 | #define DEV_ENTRY_INIT_PASS 0xb8 |
202 | #define DEV_ENTRY_EINT_PASS 0xb9 | |
203 | #define DEV_ENTRY_NMI_PASS 0xba | |
204 | #define DEV_ENTRY_LINT0_PASS 0xbe | |
205 | #define DEV_ENTRY_LINT1_PASS 0xbf | |
38ddf41b JR |
206 | #define DEV_ENTRY_MODE_MASK 0x07 |
207 | #define DEV_ENTRY_MODE_SHIFT 0x09 | |
8d283c35 | 208 | |
7ef2798d JR |
209 | #define MAX_DEV_TABLE_ENTRIES 0xffff |
210 | ||
8d283c35 JR |
211 | /* constants to configure the command buffer */ |
212 | #define CMD_BUFFER_SIZE 8192 | |
549c90dc | 213 | #define CMD_BUFFER_UNINITIALIZED 1 |
8d283c35 JR |
214 | #define CMD_BUFFER_ENTRIES 512 |
215 | #define MMIO_CMD_SIZE_SHIFT 56 | |
216 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) | |
217 | ||
335503e5 JR |
218 | /* constants for event buffer handling */ |
219 | #define EVT_BUFFER_SIZE 8192 /* 512 entries */ | |
220 | #define EVT_LEN_MASK (0x9ULL << 56) | |
221 | ||
1a29ac01 JR |
222 | /* Constants for PPR Log handling */ |
223 | #define PPR_LOG_ENTRIES 512 | |
224 | #define PPR_LOG_SIZE_SHIFT 56 | |
225 | #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) | |
226 | #define PPR_ENTRY_SIZE 16 | |
227 | #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) | |
228 | ||
72e1dcc4 JR |
229 | #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) |
230 | #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) | |
231 | #define PPR_DEVID(x) ((x) & 0xffffULL) | |
232 | #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) | |
233 | #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) | |
234 | #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) | |
235 | #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) | |
236 | ||
237 | #define PPR_REQ_FAULT 0x01 | |
238 | ||
8bda0cfb SS |
239 | /* Constants for GA Log handling */ |
240 | #define GA_LOG_ENTRIES 512 | |
241 | #define GA_LOG_SIZE_SHIFT 56 | |
242 | #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT) | |
243 | #define GA_ENTRY_SIZE 8 | |
244 | #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES) | |
245 | ||
246 | #define GA_TAG(x) (u32)(x & 0xffffffffULL) | |
247 | #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL) | |
248 | #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL) | |
249 | ||
250 | #define GA_GUEST_NR 0x1 | |
251 | ||
53019a9e BH |
252 | /* Bit value definition for dte irq remapping fields*/ |
253 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
254 | #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60) | |
255 | #define DTE_IRQ_TABLE_LEN_MASK (0xfULL << 1) | |
256 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
257 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
258 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
259 | ||
0feae533 | 260 | #define PAGE_MODE_NONE 0x00 |
8d283c35 JR |
261 | #define PAGE_MODE_1_LEVEL 0x01 |
262 | #define PAGE_MODE_2_LEVEL 0x02 | |
263 | #define PAGE_MODE_3_LEVEL 0x03 | |
9355a081 JR |
264 | #define PAGE_MODE_4_LEVEL 0x04 |
265 | #define PAGE_MODE_5_LEVEL 0x05 | |
266 | #define PAGE_MODE_6_LEVEL 0x06 | |
69be8852 | 267 | #define PAGE_MODE_7_LEVEL 0x07 |
8d283c35 | 268 | |
9355a081 JR |
269 | #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) |
270 | #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ | |
271 | ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ | |
272 | (0xffffffffffffffffULL)) | |
273 | #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) | |
50020fb6 JR |
274 | #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) |
275 | #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ | |
07a80a6b | 276 | IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW) |
a6b256b4 | 277 | #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) |
50020fb6 | 278 | |
abdc5eb3 JR |
279 | #define PM_MAP_4k 0 |
280 | #define PM_ADDR_MASK 0x000ffffffffff000ULL | |
281 | #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ | |
282 | (~((1ULL << (12 + ((lvl) * 9))) - 1))) | |
283 | #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) | |
8d283c35 | 284 | |
cbb9d729 JR |
285 | /* |
286 | * Returns the page table level to use for a given page size | |
287 | * Pagesize is expected to be a power-of-two | |
288 | */ | |
289 | #define PAGE_SIZE_LEVEL(pagesize) \ | |
290 | ((__ffs(pagesize) - 12) / 9) | |
291 | /* | |
292 | * Returns the number of ptes to use for a given page size | |
293 | * Pagesize is expected to be a power-of-two | |
294 | */ | |
295 | #define PAGE_SIZE_PTE_COUNT(pagesize) \ | |
296 | (1ULL << ((__ffs(pagesize) - 12) % 9)) | |
297 | ||
298 | /* | |
299 | * Aligns a given io-virtual address to a given page size | |
300 | * Pagesize is expected to be a power-of-two | |
301 | */ | |
302 | #define PAGE_SIZE_ALIGN(address, pagesize) \ | |
303 | ((address) & ~((pagesize) - 1)) | |
304 | /* | |
df805abb | 305 | * Creates an IOMMU PTE for an address and a given pagesize |
cbb9d729 JR |
306 | * The PTE has no permission bits set |
307 | * Pagesize is expected to be a power-of-two larger than 4096 | |
308 | */ | |
309 | #define PAGE_SIZE_PTE(address, pagesize) \ | |
310 | (((address) | ((pagesize) - 1)) & \ | |
311 | (~(pagesize >> 1)) & PM_ADDR_MASK) | |
312 | ||
24cd7723 JR |
313 | /* |
314 | * Takes a PTE value with mode=0x07 and returns the page size it maps | |
315 | */ | |
316 | #define PTE_PAGE_SIZE(pte) \ | |
317 | (1ULL << (1 + ffz(((pte) | 0xfffULL)))) | |
318 | ||
3039ca1b JR |
319 | /* |
320 | * Takes a page-table level and returns the default page-size for this level | |
321 | */ | |
322 | #define PTE_LEVEL_PAGE_SIZE(level) \ | |
323 | (1ULL << (12 + (9 * (level)))) | |
324 | ||
07a80a6b BH |
325 | /* |
326 | * Bit value definition for I/O PTE fields | |
327 | */ | |
328 | #define IOMMU_PTE_PR (1ULL << 0) | |
8d283c35 JR |
329 | #define IOMMU_PTE_U (1ULL << 59) |
330 | #define IOMMU_PTE_FC (1ULL << 60) | |
331 | #define IOMMU_PTE_IR (1ULL << 61) | |
332 | #define IOMMU_PTE_IW (1ULL << 62) | |
333 | ||
07a80a6b BH |
334 | /* |
335 | * Bit value definition for DTE fields | |
336 | */ | |
337 | #define DTE_FLAG_V (1ULL << 0) | |
338 | #define DTE_FLAG_TV (1ULL << 1) | |
339 | #define DTE_FLAG_IR (1ULL << 61) | |
340 | #define DTE_FLAG_IW (1ULL << 62) | |
341 | ||
ca9cab3a JR |
342 | #define DTE_FLAG_IOTLB (1ULL << 32) |
343 | #define DTE_FLAG_GV (1ULL << 55) | |
cbf3ccd0 | 344 | #define DTE_FLAG_MASK (0x3ffULL << 32) |
52815b75 JR |
345 | #define DTE_GLX_SHIFT (56) |
346 | #define DTE_GLX_MASK (3) | |
45a01c42 | 347 | #define DEV_DOMID_MASK 0xffffULL |
52815b75 JR |
348 | |
349 | #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) | |
350 | #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) | |
c20f3653 | 351 | #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL) |
52815b75 JR |
352 | |
353 | #define DTE_GCR3_INDEX_A 0 | |
354 | #define DTE_GCR3_INDEX_B 1 | |
355 | #define DTE_GCR3_INDEX_C 1 | |
356 | ||
357 | #define DTE_GCR3_SHIFT_A 58 | |
358 | #define DTE_GCR3_SHIFT_B 16 | |
359 | #define DTE_GCR3_SHIFT_C 43 | |
360 | ||
b16137b1 | 361 | #define GCR3_VALID 0x01ULL |
fd7b5535 | 362 | |
8d283c35 | 363 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
07a80a6b | 364 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR) |
2543a786 | 365 | #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK)) |
8d283c35 JR |
366 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) |
367 | ||
368 | #define IOMMU_PROT_MASK 0x03 | |
369 | #define IOMMU_PROT_IR 0x01 | |
370 | #define IOMMU_PROT_IW 0x02 | |
371 | ||
8aafaaf2 JR |
372 | #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2) |
373 | ||
8d283c35 JR |
374 | /* IOMMU capabilities */ |
375 | #define IOMMU_CAP_IOTLB 24 | |
376 | #define IOMMU_CAP_NPCACHE 26 | |
d99ddec3 | 377 | #define IOMMU_CAP_EFR 27 |
8d283c35 | 378 | |
3928aa3f SS |
379 | /* IOMMU Feature Reporting Field (for IVHD type 10h */ |
380 | #define IOMMU_FEAT_GASUP_SHIFT 6 | |
381 | ||
382 | /* IOMMU Extended Feature Register (EFR) */ | |
90fcffd9 | 383 | #define IOMMU_EFR_XTSUP_SHIFT 2 |
3928aa3f | 384 | #define IOMMU_EFR_GASUP_SHIFT 7 |
81307143 | 385 | #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46 |
3928aa3f | 386 | |
8d283c35 JR |
387 | #define MAX_DOMAIN_ID 65536 |
388 | ||
9fdb19d6 JR |
389 | /* Protection domain flags */ |
390 | #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ | |
e2dc14a2 JR |
391 | #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops |
392 | domain for an IOMMU */ | |
0feae533 JR |
393 | #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page |
394 | translation */ | |
52815b75 | 395 | #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */ |
0feae533 | 396 | |
fefda117 JR |
397 | extern bool amd_iommu_dump; |
398 | #define DUMP_printk(format, arg...) \ | |
399 | do { \ | |
400 | if (amd_iommu_dump) \ | |
4c6f40d4 | 401 | printk(KERN_INFO "AMD-Vi: " format, ## arg); \ |
fefda117 | 402 | } while(0); |
9fdb19d6 | 403 | |
318afd41 JR |
404 | /* global flag if IOMMUs cache non-present entries */ |
405 | extern bool amd_iommu_np_cache; | |
60f723b4 JR |
406 | /* Only true if all IOMMUs support device IOTLBs */ |
407 | extern bool amd_iommu_iotlb_sup; | |
318afd41 | 408 | |
05152a04 JR |
409 | #define MAX_IRQS_PER_TABLE 256 |
410 | #define IRQ_TABLE_ALIGNMENT 128 | |
411 | ||
0ea2c422 | 412 | struct irq_remap_table { |
27790398 | 413 | raw_spinlock_t lock; |
0ea2c422 JR |
414 | unsigned min_index; |
415 | u32 *table; | |
416 | }; | |
417 | ||
418 | extern struct irq_remap_table **irq_lookup_table; | |
419 | ||
05152a04 JR |
420 | /* Interrupt remapping feature used? */ |
421 | extern bool amd_iommu_irq_remap; | |
422 | ||
423 | /* kmem_cache to get tables with 128 byte alignement */ | |
424 | extern struct kmem_cache *amd_iommu_irq_cache; | |
425 | ||
3bd22172 JR |
426 | /* |
427 | * Make iterating over all IOMMUs easier | |
428 | */ | |
429 | #define for_each_iommu(iommu) \ | |
430 | list_for_each_entry((iommu), &amd_iommu_list, list) | |
431 | #define for_each_iommu_safe(iommu, next) \ | |
432 | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) | |
433 | ||
384de729 JR |
434 | #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
435 | #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) | |
436 | #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) | |
437 | #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ | |
438 | #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) | |
439 | #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) | |
9fdb19d6 | 440 | |
72e1dcc4 JR |
441 | /* |
442 | * This struct is used to pass information about | |
443 | * incoming PPR faults around. | |
444 | */ | |
445 | struct amd_iommu_fault { | |
446 | u64 address; /* IO virtual address of the fault*/ | |
447 | u32 pasid; /* Address space identifier */ | |
448 | u16 device_id; /* Originating PCI device id */ | |
449 | u16 tag; /* PPR tag */ | |
450 | u16 flags; /* Fault flags */ | |
451 | ||
452 | }; | |
453 | ||
72e1dcc4 | 454 | |
f3572db8 | 455 | struct iommu_domain; |
7c71d306 | 456 | struct irq_domain; |
880ac60e | 457 | struct amd_irte_ops; |
f3572db8 | 458 | |
4c232a70 BH |
459 | #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0) |
460 | ||
5694703f JR |
461 | /* |
462 | * This structure contains generic data for IOMMU protection domains | |
463 | * independent of their use. | |
464 | */ | |
8d283c35 | 465 | struct protection_domain { |
7c392cbe | 466 | struct list_head dev_list; /* List of all devices in this domain */ |
3f4b87b9 JR |
467 | struct iommu_domain domain; /* generic domain handle used by |
468 | iommu core code */ | |
9fdb19d6 JR |
469 | spinlock_t lock; /* mostly used to lock the page table*/ |
470 | u16 id; /* the domain id written to the device table */ | |
471 | int mode; /* paging mode (0-6 levels) */ | |
472 | u64 *pt_root; /* page table root pointer */ | |
52815b75 JR |
473 | int glx; /* Number of levels for GCR3 table */ |
474 | u64 *gcr3_tbl; /* Guest CR3 table */ | |
9fdb19d6 | 475 | unsigned long flags; /* flags to find out type of domain */ |
863c74eb | 476 | unsigned dev_cnt; /* devices assigned to this domain */ |
c4596114 | 477 | unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ |
8d283c35 JR |
478 | }; |
479 | ||
5694703f JR |
480 | /* |
481 | * Structure where we save information about one hardware AMD IOMMU in the | |
482 | * system. | |
483 | */ | |
8d283c35 JR |
484 | struct amd_iommu { |
485 | struct list_head list; | |
5694703f | 486 | |
bb52777e JR |
487 | /* Index within the IOMMU array */ |
488 | int index; | |
489 | ||
5694703f | 490 | /* locks the accesses to the hardware */ |
27790398 | 491 | raw_spinlock_t lock; |
8d283c35 | 492 | |
3eaf28a1 JR |
493 | /* Pointer to PCI device of this IOMMU */ |
494 | struct pci_dev *dev; | |
495 | ||
c1bf94ec JR |
496 | /* Cache pdev to root device for resume quirks */ |
497 | struct pci_dev *root_pdev; | |
498 | ||
5694703f | 499 | /* physical address of MMIO space */ |
8d283c35 | 500 | u64 mmio_phys; |
30861ddc SK |
501 | |
502 | /* physical end address of MMIO space */ | |
503 | u64 mmio_phys_end; | |
504 | ||
5694703f | 505 | /* virtual address of MMIO space */ |
98f1ad25 | 506 | u8 __iomem *mmio_base; |
5694703f JR |
507 | |
508 | /* capabilities of that IOMMU read from ACPI */ | |
8d283c35 | 509 | u32 cap; |
5694703f | 510 | |
e9bf5197 JR |
511 | /* flags read from acpi table */ |
512 | u8 acpi_flags; | |
513 | ||
d99ddec3 JR |
514 | /* Extended features */ |
515 | u64 features; | |
516 | ||
400a28a0 JR |
517 | /* IOMMUv2 */ |
518 | bool is_iommu_v2; | |
519 | ||
23c742db JR |
520 | /* PCI device id of the IOMMU device */ |
521 | u16 devid; | |
522 | ||
eac9fbc6 RK |
523 | /* |
524 | * Capability pointer. There could be more than one IOMMU per PCI | |
525 | * device function if there are more than one AMD IOMMU capability | |
526 | * pointers. | |
527 | */ | |
528 | u16 cap_ptr; | |
529 | ||
ee893c24 JR |
530 | /* pci domain of this IOMMU */ |
531 | u16 pci_seg; | |
532 | ||
5694703f | 533 | /* start of exclusion range of that IOMMU */ |
8d283c35 | 534 | u64 exclusion_start; |
5694703f | 535 | /* length of exclusion range of that IOMMU */ |
8d283c35 JR |
536 | u64 exclusion_length; |
537 | ||
5694703f | 538 | /* command buffer virtual address */ |
8d283c35 | 539 | u8 *cmd_buf; |
d334a563 TL |
540 | u32 cmd_buf_head; |
541 | u32 cmd_buf_tail; | |
8d283c35 | 542 | |
eac9fbc6 RK |
543 | /* event buffer virtual address */ |
544 | u8 *evt_buf; | |
335503e5 | 545 | |
1a29ac01 JR |
546 | /* Base of the PPR log, if present */ |
547 | u8 *ppr_log; | |
548 | ||
8bda0cfb SS |
549 | /* Base of the GA log, if present */ |
550 | u8 *ga_log; | |
551 | ||
552 | /* Tail of the GA log, if present */ | |
553 | u8 *ga_log_tail; | |
554 | ||
a80dc3e0 JR |
555 | /* true if interrupts for this IOMMU are already enabled */ |
556 | bool int_enabled; | |
557 | ||
eac9fbc6 | 558 | /* if one, we need to send a completion wait command */ |
0cfd7aa9 | 559 | bool need_sync; |
eac9fbc6 | 560 | |
b0119e87 JR |
561 | /* Handle for IOMMU core code */ |
562 | struct iommu_device iommu; | |
563 | ||
4c894f47 | 564 | /* |
5bcd757f MG |
565 | * We can't rely on the BIOS to restore all values on reinit, so we |
566 | * need to stash them | |
4c894f47 | 567 | */ |
5bcd757f MG |
568 | |
569 | /* The iommu BAR */ | |
570 | u32 stored_addr_lo; | |
571 | u32 stored_addr_hi; | |
572 | ||
573 | /* | |
574 | * Each iommu has 6 l1s, each of which is documented as having 0x12 | |
575 | * registers | |
576 | */ | |
577 | u32 stored_l1[6][0x12]; | |
578 | ||
579 | /* The l2 indirect registers */ | |
580 | u32 stored_l2[0x83]; | |
30861ddc SK |
581 | |
582 | /* The maximum PC banks and counters/bank (PCSup=1) */ | |
583 | u8 max_banks; | |
584 | u8 max_counters; | |
7c71d306 JL |
585 | #ifdef CONFIG_IRQ_REMAP |
586 | struct irq_domain *ir_domain; | |
587 | struct irq_domain *msi_domain; | |
880ac60e SS |
588 | |
589 | struct amd_irte_ops *irte_ops; | |
7c71d306 | 590 | #endif |
4bf5beef | 591 | |
4c232a70 | 592 | u32 flags; |
4bf5beef | 593 | volatile u64 __aligned(8) cmd_sem; |
7d0f5fd3 GH |
594 | |
595 | #ifdef CONFIG_AMD_IOMMU_DEBUGFS | |
596 | /* DebugFS Info */ | |
597 | struct dentry *debugfs; | |
598 | #endif | |
66929812 SS |
599 | /* IRQ notifier for IntCapXT interrupt */ |
600 | struct irq_affinity_notify intcapxt_notify; | |
8d283c35 JR |
601 | }; |
602 | ||
b7a42b9d JR |
603 | static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev) |
604 | { | |
2926a2aa JR |
605 | struct iommu_device *iommu = dev_to_iommu_device(dev); |
606 | ||
607 | return container_of(iommu, struct amd_iommu, iommu); | |
b7a42b9d JR |
608 | } |
609 | ||
2a0cb4e2 WZ |
610 | #define ACPIHID_UID_LEN 256 |
611 | #define ACPIHID_HID_LEN 9 | |
612 | ||
613 | struct acpihid_map_entry { | |
614 | struct list_head list; | |
615 | u8 uid[ACPIHID_UID_LEN]; | |
616 | u8 hid[ACPIHID_HID_LEN]; | |
617 | u16 devid; | |
618 | u16 root_devid; | |
619 | bool cmd_line; | |
620 | struct iommu_group *group; | |
621 | }; | |
622 | ||
6efed63b JR |
623 | struct devid_map { |
624 | struct list_head list; | |
625 | u8 id; | |
626 | u16 devid; | |
31cff67f | 627 | bool cmd_line; |
6efed63b JR |
628 | }; |
629 | ||
daae2d25 BH |
630 | /* |
631 | * This struct contains device specific data for the IOMMU | |
632 | */ | |
633 | struct iommu_dev_data { | |
ab7b2577 JR |
634 | /*Protect against attach/detach races */ |
635 | spinlock_t lock; | |
636 | ||
daae2d25 | 637 | struct list_head list; /* For domain->dev_list */ |
779da732 | 638 | struct llist_node dev_data_list; /* For global dev_data_list */ |
daae2d25 | 639 | struct protection_domain *domain; /* Domain the device is bound to */ |
3332364e | 640 | struct pci_dev *pdev; |
daae2d25 | 641 | u16 devid; /* PCI Device ID */ |
daae2d25 BH |
642 | bool iommu_v2; /* Device can make use of IOMMUv2 */ |
643 | bool passthrough; /* Device is identity mapped */ | |
644 | struct { | |
645 | bool enabled; | |
646 | int qdep; | |
647 | } ats; /* ATS state */ | |
648 | bool pri_tlp; /* PASID TLB required for | |
649 | PPR completions */ | |
650 | u32 errata; /* Bitmap for errata to apply */ | |
651 | bool use_vapic; /* Enable device to use vapic mode */ | |
652 | bool defer_attach; | |
653 | ||
654 | struct ratelimit_state rs; /* Ratelimit IOPF messages */ | |
655 | }; | |
656 | ||
6efed63b JR |
657 | /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ |
658 | extern struct list_head ioapic_map; | |
659 | extern struct list_head hpet_map; | |
2a0cb4e2 | 660 | extern struct list_head acpihid_map; |
6efed63b | 661 | |
5694703f JR |
662 | /* |
663 | * List with all IOMMUs in the system. This list is not locked because it is | |
664 | * only written and read at driver initialization or suspend time | |
665 | */ | |
8d283c35 JR |
666 | extern struct list_head amd_iommu_list; |
667 | ||
bb52777e JR |
668 | /* |
669 | * Array with pointers to each IOMMU struct | |
670 | * The indices are referenced in the protection domains | |
671 | */ | |
672 | extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
673 | ||
5694703f JR |
674 | /* |
675 | * Structure defining one entry in the device table | |
676 | */ | |
8d283c35 | 677 | struct dev_table_entry { |
ee6c2868 | 678 | u64 data[4]; |
8d283c35 JR |
679 | }; |
680 | ||
5694703f JR |
681 | /* |
682 | * One entry for unity mappings parsed out of the ACPI table. | |
683 | */ | |
8d283c35 JR |
684 | struct unity_map_entry { |
685 | struct list_head list; | |
5694703f JR |
686 | |
687 | /* starting device id this entry is used for (including) */ | |
8d283c35 | 688 | u16 devid_start; |
5694703f | 689 | /* end device id this entry is used for (including) */ |
8d283c35 | 690 | u16 devid_end; |
5694703f JR |
691 | |
692 | /* start address to unity map (including) */ | |
8d283c35 | 693 | u64 address_start; |
5694703f | 694 | /* end address to unity map (including) */ |
8d283c35 | 695 | u64 address_end; |
5694703f JR |
696 | |
697 | /* required protection */ | |
8d283c35 JR |
698 | int prot; |
699 | }; | |
700 | ||
5694703f JR |
701 | /* |
702 | * List of all unity mappings. It is not locked because as runtime it is only | |
703 | * read. It is created at ACPI table parsing time. | |
704 | */ | |
8d283c35 JR |
705 | extern struct list_head amd_iommu_unity_map; |
706 | ||
5694703f JR |
707 | /* |
708 | * Data structures for device handling | |
709 | */ | |
710 | ||
711 | /* | |
712 | * Device table used by hardware. Read and write accesses by software are | |
713 | * locked with the amd_iommu_pd_table lock. | |
714 | */ | |
8d283c35 | 715 | extern struct dev_table_entry *amd_iommu_dev_table; |
5694703f JR |
716 | |
717 | /* | |
718 | * Alias table to find requestor ids to device ids. Not locked because only | |
719 | * read on runtime. | |
720 | */ | |
8d283c35 | 721 | extern u16 *amd_iommu_alias_table; |
5694703f JR |
722 | |
723 | /* | |
724 | * Reverse lookup table to find the IOMMU which translates a specific device. | |
725 | */ | |
8d283c35 JR |
726 | extern struct amd_iommu **amd_iommu_rlookup_table; |
727 | ||
5694703f | 728 | /* size of the dma_ops aperture as power of 2 */ |
8d283c35 JR |
729 | extern unsigned amd_iommu_aperture_order; |
730 | ||
5694703f | 731 | /* largest PCI device id we expect translation requests for */ |
8d283c35 JR |
732 | extern u16 amd_iommu_last_bdf; |
733 | ||
5694703f | 734 | /* allocation bitmap for domain ids */ |
8d283c35 JR |
735 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
736 | ||
afa9fdc2 FT |
737 | /* |
738 | * If true, the addresses will be flushed on unmap time, not when | |
739 | * they are reused | |
740 | */ | |
621a5f7a | 741 | extern bool amd_iommu_unmap_flush; |
afa9fdc2 | 742 | |
a919a018 SS |
743 | /* Smallest max PASID supported by any IOMMU in the system */ |
744 | extern u32 amd_iommu_max_pasid; | |
62f71abb | 745 | |
400a28a0 JR |
746 | extern bool amd_iommu_v2_present; |
747 | ||
5abcdba4 JR |
748 | extern bool amd_iommu_force_isolation; |
749 | ||
52815b75 JR |
750 | /* Max levels of glxval supported */ |
751 | extern int amd_iommu_max_glx_val; | |
752 | ||
98f1ad25 JR |
753 | /* |
754 | * This function flushes all internal caches of | |
755 | * the IOMMU used by this driver. | |
756 | */ | |
757 | extern void iommu_flush_all_caches(struct amd_iommu *iommu); | |
758 | ||
6efed63b JR |
759 | static inline int get_ioapic_devid(int id) |
760 | { | |
761 | struct devid_map *entry; | |
762 | ||
763 | list_for_each_entry(entry, &ioapic_map, list) { | |
764 | if (entry->id == id) | |
765 | return entry->devid; | |
766 | } | |
767 | ||
768 | return -EINVAL; | |
769 | } | |
770 | ||
771 | static inline int get_hpet_devid(int id) | |
772 | { | |
773 | struct devid_map *entry; | |
774 | ||
775 | list_for_each_entry(entry, &hpet_map, list) { | |
776 | if (entry->id == id) | |
777 | return entry->devid; | |
778 | } | |
779 | ||
780 | return -EINVAL; | |
781 | } | |
782 | ||
3928aa3f SS |
783 | enum amd_iommu_intr_mode_type { |
784 | AMD_IOMMU_GUEST_IR_LEGACY, | |
785 | ||
786 | /* This mode is not visible to users. It is used when | |
787 | * we cannot fully enable vAPIC and fallback to only support | |
788 | * legacy interrupt remapping via 128-bit IRTE. | |
789 | */ | |
790 | AMD_IOMMU_GUEST_IR_LEGACY_GA, | |
791 | AMD_IOMMU_GUEST_IR_VAPIC, | |
792 | }; | |
793 | ||
794 | #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \ | |
795 | x == AMD_IOMMU_GUEST_IR_LEGACY_GA) | |
796 | ||
797 | #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC) | |
a38180bd SS |
798 | |
799 | union irte { | |
800 | u32 val; | |
801 | struct { | |
802 | u32 valid : 1, | |
803 | no_fault : 1, | |
804 | int_type : 3, | |
805 | rq_eoi : 1, | |
806 | dm : 1, | |
807 | rsvd_1 : 1, | |
808 | destination : 8, | |
809 | vector : 8, | |
810 | rsvd_2 : 8; | |
811 | } fields; | |
812 | }; | |
813 | ||
90fcffd9 SS |
814 | #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff) |
815 | #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff) | |
816 | ||
a38180bd SS |
817 | union irte_ga_lo { |
818 | u64 val; | |
819 | ||
820 | /* For int remapping */ | |
821 | struct { | |
822 | u64 valid : 1, | |
823 | no_fault : 1, | |
824 | /* ------ */ | |
825 | int_type : 3, | |
826 | rq_eoi : 1, | |
827 | dm : 1, | |
828 | /* ------ */ | |
829 | guest_mode : 1, | |
90fcffd9 SS |
830 | destination : 24, |
831 | ga_tag : 32; | |
a38180bd SS |
832 | } fields_remap; |
833 | ||
834 | /* For guest vAPIC */ | |
835 | struct { | |
836 | u64 valid : 1, | |
837 | no_fault : 1, | |
838 | /* ------ */ | |
839 | ga_log_intr : 1, | |
840 | rsvd1 : 3, | |
841 | is_run : 1, | |
842 | /* ------ */ | |
843 | guest_mode : 1, | |
90fcffd9 | 844 | destination : 24, |
a38180bd SS |
845 | ga_tag : 32; |
846 | } fields_vapic; | |
847 | }; | |
848 | ||
849 | union irte_ga_hi { | |
850 | u64 val; | |
851 | struct { | |
852 | u64 vector : 8, | |
853 | rsvd_1 : 4, | |
854 | ga_root_ptr : 40, | |
90fcffd9 SS |
855 | rsvd_2 : 4, |
856 | destination : 8; | |
a38180bd SS |
857 | } fields; |
858 | }; | |
859 | ||
860 | struct irte_ga { | |
861 | union irte_ga_lo lo; | |
862 | union irte_ga_hi hi; | |
863 | }; | |
864 | ||
865 | struct irq_2_irte { | |
866 | u16 devid; /* Device ID for IRTE table */ | |
867 | u16 index; /* Index into IRTE table*/ | |
868 | }; | |
869 | ||
870 | struct amd_ir_data { | |
b9fc6b56 | 871 | u32 cached_ga_tag; |
a38180bd | 872 | struct irq_2_irte irq_2_irte; |
a38180bd | 873 | struct msi_msg msi_entry; |
880ac60e | 874 | void *entry; /* Pointer to union irte or struct irte_ga */ |
8dbea3fd | 875 | void *ref; /* Pointer to the actual irte */ |
b9c6ff94 SS |
876 | |
877 | /** | |
878 | * Store information for activate/de-activate | |
879 | * Guest virtual APIC mode during runtime. | |
880 | */ | |
881 | struct irq_cfg *cfg; | |
882 | int ga_vector; | |
883 | int ga_root_ptr; | |
884 | int ga_tag; | |
880ac60e SS |
885 | }; |
886 | ||
887 | struct amd_irte_ops { | |
d98de49a | 888 | void (*prepare)(void *, u32, u32, u8, u32, int); |
880ac60e SS |
889 | void (*activate)(void *, u16, u16); |
890 | void (*deactivate)(void *, u16, u16); | |
891 | void (*set_affinity)(void *, u16, u16, u8, u32); | |
892 | void *(*get)(struct irq_remap_table *, int); | |
893 | void (*set_allocated)(struct irq_remap_table *, int); | |
894 | bool (*is_allocated)(struct irq_remap_table *, int); | |
895 | void (*clear_allocated)(struct irq_remap_table *, int); | |
a38180bd SS |
896 | }; |
897 | ||
880ac60e SS |
898 | #ifdef CONFIG_IRQ_REMAP |
899 | extern struct amd_irte_ops irte_32_ops; | |
900 | extern struct amd_irte_ops irte_128_ops; | |
901 | #endif | |
902 | ||
1965aae3 | 903 | #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ |