Commit | Line | Data |
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8d283c35 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
8d283c35 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
1965aae3 PA |
20 | #ifndef _ASM_X86_AMD_IOMMU_TYPES_H |
21 | #define _ASM_X86_AMD_IOMMU_TYPES_H | |
8d283c35 JR |
22 | |
23 | #include <linux/types.h> | |
5d214fe6 | 24 | #include <linux/mutex.h> |
a38180bd | 25 | #include <linux/msi.h> |
8d283c35 JR |
26 | #include <linux/list.h> |
27 | #include <linux/spinlock.h> | |
c5081cd7 | 28 | #include <linux/pci.h> |
4b180d97 | 29 | #include <linux/irqreturn.h> |
8d283c35 | 30 | |
bb52777e JR |
31 | /* |
32 | * Maximum number of IOMMUs supported | |
33 | */ | |
34 | #define MAX_IOMMUS 32 | |
35 | ||
8d283c35 JR |
36 | /* |
37 | * some size calculation constants | |
38 | */ | |
83f5aac1 | 39 | #define DEV_TABLE_ENTRY_SIZE 32 |
8d283c35 JR |
40 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
41 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) | |
42 | ||
8d283c35 JR |
43 | /* Capability offsets used by the driver */ |
44 | #define MMIO_CAP_HDR_OFFSET 0x00 | |
45 | #define MMIO_RANGE_OFFSET 0x0c | |
a80dc3e0 | 46 | #define MMIO_MISC_OFFSET 0x10 |
8d283c35 JR |
47 | |
48 | /* Masks, shifts and macros to parse the device range capability */ | |
49 | #define MMIO_RANGE_LD_MASK 0xff000000 | |
50 | #define MMIO_RANGE_FD_MASK 0x00ff0000 | |
51 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 | |
52 | #define MMIO_RANGE_LD_SHIFT 24 | |
53 | #define MMIO_RANGE_FD_SHIFT 16 | |
54 | #define MMIO_RANGE_BUS_SHIFT 8 | |
55 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) | |
56 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) | |
57 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) | |
a80dc3e0 | 58 | #define MMIO_MSI_NUM(x) ((x) & 0x1f) |
8d283c35 JR |
59 | |
60 | /* Flag masks for the AMD IOMMU exclusion range */ | |
61 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL | |
62 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL | |
63 | ||
64 | /* Used offsets into the MMIO space */ | |
65 | #define MMIO_DEV_TABLE_OFFSET 0x0000 | |
66 | #define MMIO_CMD_BUF_OFFSET 0x0008 | |
67 | #define MMIO_EVT_BUF_OFFSET 0x0010 | |
68 | #define MMIO_CONTROL_OFFSET 0x0018 | |
69 | #define MMIO_EXCL_BASE_OFFSET 0x0020 | |
70 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 | |
d99ddec3 | 71 | #define MMIO_EXT_FEATURES 0x0030 |
1a29ac01 | 72 | #define MMIO_PPR_LOG_OFFSET 0x0038 |
8bda0cfb SS |
73 | #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 |
74 | #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8 | |
8d283c35 JR |
75 | #define MMIO_CMD_HEAD_OFFSET 0x2000 |
76 | #define MMIO_CMD_TAIL_OFFSET 0x2008 | |
77 | #define MMIO_EVT_HEAD_OFFSET 0x2010 | |
78 | #define MMIO_EVT_TAIL_OFFSET 0x2018 | |
79 | #define MMIO_STATUS_OFFSET 0x2020 | |
1a29ac01 JR |
80 | #define MMIO_PPR_HEAD_OFFSET 0x2030 |
81 | #define MMIO_PPR_TAIL_OFFSET 0x2038 | |
8bda0cfb SS |
82 | #define MMIO_GA_HEAD_OFFSET 0x2040 |
83 | #define MMIO_GA_TAIL_OFFSET 0x2048 | |
30861ddc SK |
84 | #define MMIO_CNTR_CONF_OFFSET 0x4000 |
85 | #define MMIO_CNTR_REG_OFFSET 0x40000 | |
86 | #define MMIO_REG_END_OFFSET 0x80000 | |
87 | ||
8d283c35 | 88 | |
d99ddec3 JR |
89 | |
90 | /* Extended Feature Bits */ | |
91 | #define FEATURE_PREFETCH (1ULL<<0) | |
92 | #define FEATURE_PPR (1ULL<<1) | |
93 | #define FEATURE_X2APIC (1ULL<<2) | |
94 | #define FEATURE_NX (1ULL<<3) | |
95 | #define FEATURE_GT (1ULL<<4) | |
96 | #define FEATURE_IA (1ULL<<6) | |
97 | #define FEATURE_GA (1ULL<<7) | |
98 | #define FEATURE_HE (1ULL<<8) | |
99 | #define FEATURE_PC (1ULL<<9) | |
3928aa3f | 100 | #define FEATURE_GAM_VAPIC (1ULL<<21) |
ff18c4e5 | 101 | #define FEATURE_EPHSUP (1ULL<<50) |
d99ddec3 | 102 | |
62f71abb JR |
103 | #define FEATURE_PASID_SHIFT 32 |
104 | #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) | |
105 | ||
52815b75 JR |
106 | #define FEATURE_GLXVAL_SHIFT 14 |
107 | #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) | |
108 | ||
a919a018 SS |
109 | /* Note: |
110 | * The current driver only support 16-bit PASID. | |
111 | * Currently, hardware only implement upto 16-bit PASID | |
112 | * even though the spec says it could have upto 20 bits. | |
113 | */ | |
114 | #define PASID_MASK 0x0000ffff | |
52815b75 | 115 | |
519c31ba | 116 | /* MMIO status bits */ |
925fe08b | 117 | #define MMIO_STATUS_EVT_INT_MASK (1 << 1) |
72e1dcc4 JR |
118 | #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) |
119 | #define MMIO_STATUS_PPR_INT_MASK (1 << 6) | |
8bda0cfb SS |
120 | #define MMIO_STATUS_GALOG_RUN_MASK (1 << 8) |
121 | #define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9) | |
122 | #define MMIO_STATUS_GALOG_INT_MASK (1 << 10) | |
519c31ba | 123 | |
90008ee4 JR |
124 | /* event logging constants */ |
125 | #define EVENT_ENTRY_SIZE 0x10 | |
126 | #define EVENT_TYPE_SHIFT 28 | |
127 | #define EVENT_TYPE_MASK 0xf | |
128 | #define EVENT_TYPE_ILL_DEV 0x1 | |
129 | #define EVENT_TYPE_IO_FAULT 0x2 | |
130 | #define EVENT_TYPE_DEV_TAB_ERR 0x3 | |
131 | #define EVENT_TYPE_PAGE_TAB_ERR 0x4 | |
132 | #define EVENT_TYPE_ILL_CMD 0x5 | |
133 | #define EVENT_TYPE_CMD_HARD_ERR 0x6 | |
134 | #define EVENT_TYPE_IOTLB_INV_TO 0x7 | |
135 | #define EVENT_TYPE_INV_DEV_REQ 0x8 | |
e7f63ffc | 136 | #define EVENT_TYPE_INV_PPR_REQ 0x9 |
90008ee4 JR |
137 | #define EVENT_DEVID_MASK 0xffff |
138 | #define EVENT_DEVID_SHIFT 0 | |
139 | #define EVENT_DOMID_MASK 0xffff | |
140 | #define EVENT_DOMID_SHIFT 0 | |
141 | #define EVENT_FLAGS_MASK 0xfff | |
142 | #define EVENT_FLAGS_SHIFT 0x10 | |
143 | ||
8d283c35 JR |
144 | /* feature control bits */ |
145 | #define CONTROL_IOMMU_EN 0x00ULL | |
146 | #define CONTROL_HT_TUN_EN 0x01ULL | |
147 | #define CONTROL_EVT_LOG_EN 0x02ULL | |
148 | #define CONTROL_EVT_INT_EN 0x03ULL | |
149 | #define CONTROL_COMWAIT_EN 0x04ULL | |
1456e9d2 | 150 | #define CONTROL_INV_TIMEOUT 0x05ULL |
8d283c35 JR |
151 | #define CONTROL_PASSPW_EN 0x08ULL |
152 | #define CONTROL_RESPASSPW_EN 0x09ULL | |
153 | #define CONTROL_COHERENT_EN 0x0aULL | |
154 | #define CONTROL_ISOC_EN 0x0bULL | |
155 | #define CONTROL_CMDBUF_EN 0x0cULL | |
156 | #define CONTROL_PPFLOG_EN 0x0dULL | |
157 | #define CONTROL_PPFINT_EN 0x0eULL | |
1a29ac01 | 158 | #define CONTROL_PPR_EN 0x0fULL |
cbc33a90 | 159 | #define CONTROL_GT_EN 0x10ULL |
3928aa3f SS |
160 | #define CONTROL_GA_EN 0x11ULL |
161 | #define CONTROL_GAM_EN 0x19ULL | |
8bda0cfb SS |
162 | #define CONTROL_GALOG_EN 0x1CULL |
163 | #define CONTROL_GAINT_EN 0x1DULL | |
8d283c35 | 164 | |
1456e9d2 JR |
165 | #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) |
166 | #define CTRL_INV_TO_NONE 0 | |
167 | #define CTRL_INV_TO_1MS 1 | |
168 | #define CTRL_INV_TO_10MS 2 | |
169 | #define CTRL_INV_TO_100MS 3 | |
170 | #define CTRL_INV_TO_1S 4 | |
171 | #define CTRL_INV_TO_10S 5 | |
172 | #define CTRL_INV_TO_100S 6 | |
173 | ||
8d283c35 JR |
174 | /* command specific defines */ |
175 | #define CMD_COMPL_WAIT 0x01 | |
176 | #define CMD_INV_DEV_ENTRY 0x02 | |
cb41ed85 JR |
177 | #define CMD_INV_IOMMU_PAGES 0x03 |
178 | #define CMD_INV_IOTLB_PAGES 0x04 | |
7ef2798d | 179 | #define CMD_INV_IRT 0x05 |
c99afa25 | 180 | #define CMD_COMPLETE_PPR 0x07 |
58fc7f14 | 181 | #define CMD_INV_ALL 0x08 |
8d283c35 JR |
182 | |
183 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 | |
519c31ba | 184 | #define CMD_COMPL_WAIT_INT_MASK 0x02 |
8d283c35 JR |
185 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
186 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 | |
22e266c7 | 187 | #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 |
8d283c35 | 188 | |
c99afa25 JR |
189 | #define PPR_STATUS_MASK 0xf |
190 | #define PPR_STATUS_SHIFT 12 | |
191 | ||
999ba417 JR |
192 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
193 | ||
8d283c35 JR |
194 | /* macros and definitions for device table entries */ |
195 | #define DEV_ENTRY_VALID 0x00 | |
196 | #define DEV_ENTRY_TRANSLATION 0x01 | |
ff18c4e5 | 197 | #define DEV_ENTRY_PPR 0x34 |
8d283c35 JR |
198 | #define DEV_ENTRY_IR 0x3d |
199 | #define DEV_ENTRY_IW 0x3e | |
9f5f5fb3 | 200 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
8d283c35 JR |
201 | #define DEV_ENTRY_EX 0x67 |
202 | #define DEV_ENTRY_SYSMGT1 0x68 | |
203 | #define DEV_ENTRY_SYSMGT2 0x69 | |
0ea2c422 | 204 | #define DEV_ENTRY_IRQ_TBL_EN 0x80 |
8d283c35 JR |
205 | #define DEV_ENTRY_INIT_PASS 0xb8 |
206 | #define DEV_ENTRY_EINT_PASS 0xb9 | |
207 | #define DEV_ENTRY_NMI_PASS 0xba | |
208 | #define DEV_ENTRY_LINT0_PASS 0xbe | |
209 | #define DEV_ENTRY_LINT1_PASS 0xbf | |
38ddf41b JR |
210 | #define DEV_ENTRY_MODE_MASK 0x07 |
211 | #define DEV_ENTRY_MODE_SHIFT 0x09 | |
8d283c35 | 212 | |
7ef2798d JR |
213 | #define MAX_DEV_TABLE_ENTRIES 0xffff |
214 | ||
8d283c35 JR |
215 | /* constants to configure the command buffer */ |
216 | #define CMD_BUFFER_SIZE 8192 | |
549c90dc | 217 | #define CMD_BUFFER_UNINITIALIZED 1 |
8d283c35 JR |
218 | #define CMD_BUFFER_ENTRIES 512 |
219 | #define MMIO_CMD_SIZE_SHIFT 56 | |
220 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) | |
221 | ||
335503e5 JR |
222 | /* constants for event buffer handling */ |
223 | #define EVT_BUFFER_SIZE 8192 /* 512 entries */ | |
224 | #define EVT_LEN_MASK (0x9ULL << 56) | |
225 | ||
1a29ac01 JR |
226 | /* Constants for PPR Log handling */ |
227 | #define PPR_LOG_ENTRIES 512 | |
228 | #define PPR_LOG_SIZE_SHIFT 56 | |
229 | #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) | |
230 | #define PPR_ENTRY_SIZE 16 | |
231 | #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) | |
232 | ||
72e1dcc4 JR |
233 | #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) |
234 | #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) | |
235 | #define PPR_DEVID(x) ((x) & 0xffffULL) | |
236 | #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) | |
237 | #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) | |
238 | #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) | |
239 | #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) | |
240 | ||
241 | #define PPR_REQ_FAULT 0x01 | |
242 | ||
8bda0cfb SS |
243 | /* Constants for GA Log handling */ |
244 | #define GA_LOG_ENTRIES 512 | |
245 | #define GA_LOG_SIZE_SHIFT 56 | |
246 | #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT) | |
247 | #define GA_ENTRY_SIZE 8 | |
248 | #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES) | |
249 | ||
250 | #define GA_TAG(x) (u32)(x & 0xffffffffULL) | |
251 | #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL) | |
252 | #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL) | |
253 | ||
254 | #define GA_GUEST_NR 0x1 | |
255 | ||
53019a9e BH |
256 | /* Bit value definition for dte irq remapping fields*/ |
257 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
258 | #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60) | |
259 | #define DTE_IRQ_TABLE_LEN_MASK (0xfULL << 1) | |
260 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
261 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
262 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
263 | ||
0feae533 | 264 | #define PAGE_MODE_NONE 0x00 |
8d283c35 JR |
265 | #define PAGE_MODE_1_LEVEL 0x01 |
266 | #define PAGE_MODE_2_LEVEL 0x02 | |
267 | #define PAGE_MODE_3_LEVEL 0x03 | |
9355a081 JR |
268 | #define PAGE_MODE_4_LEVEL 0x04 |
269 | #define PAGE_MODE_5_LEVEL 0x05 | |
270 | #define PAGE_MODE_6_LEVEL 0x06 | |
8d283c35 | 271 | |
9355a081 JR |
272 | #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) |
273 | #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ | |
274 | ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ | |
275 | (0xffffffffffffffffULL)) | |
276 | #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) | |
50020fb6 JR |
277 | #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) |
278 | #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ | |
07a80a6b | 279 | IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW) |
a6b256b4 | 280 | #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) |
50020fb6 | 281 | |
abdc5eb3 JR |
282 | #define PM_MAP_4k 0 |
283 | #define PM_ADDR_MASK 0x000ffffffffff000ULL | |
284 | #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ | |
285 | (~((1ULL << (12 + ((lvl) * 9))) - 1))) | |
286 | #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) | |
8d283c35 | 287 | |
cbb9d729 JR |
288 | /* |
289 | * Returns the page table level to use for a given page size | |
290 | * Pagesize is expected to be a power-of-two | |
291 | */ | |
292 | #define PAGE_SIZE_LEVEL(pagesize) \ | |
293 | ((__ffs(pagesize) - 12) / 9) | |
294 | /* | |
295 | * Returns the number of ptes to use for a given page size | |
296 | * Pagesize is expected to be a power-of-two | |
297 | */ | |
298 | #define PAGE_SIZE_PTE_COUNT(pagesize) \ | |
299 | (1ULL << ((__ffs(pagesize) - 12) % 9)) | |
300 | ||
301 | /* | |
302 | * Aligns a given io-virtual address to a given page size | |
303 | * Pagesize is expected to be a power-of-two | |
304 | */ | |
305 | #define PAGE_SIZE_ALIGN(address, pagesize) \ | |
306 | ((address) & ~((pagesize) - 1)) | |
307 | /* | |
df805abb | 308 | * Creates an IOMMU PTE for an address and a given pagesize |
cbb9d729 JR |
309 | * The PTE has no permission bits set |
310 | * Pagesize is expected to be a power-of-two larger than 4096 | |
311 | */ | |
312 | #define PAGE_SIZE_PTE(address, pagesize) \ | |
313 | (((address) | ((pagesize) - 1)) & \ | |
314 | (~(pagesize >> 1)) & PM_ADDR_MASK) | |
315 | ||
24cd7723 JR |
316 | /* |
317 | * Takes a PTE value with mode=0x07 and returns the page size it maps | |
318 | */ | |
319 | #define PTE_PAGE_SIZE(pte) \ | |
320 | (1ULL << (1 + ffz(((pte) | 0xfffULL)))) | |
321 | ||
3039ca1b JR |
322 | /* |
323 | * Takes a page-table level and returns the default page-size for this level | |
324 | */ | |
325 | #define PTE_LEVEL_PAGE_SIZE(level) \ | |
326 | (1ULL << (12 + (9 * (level)))) | |
327 | ||
07a80a6b BH |
328 | /* |
329 | * Bit value definition for I/O PTE fields | |
330 | */ | |
331 | #define IOMMU_PTE_PR (1ULL << 0) | |
8d283c35 JR |
332 | #define IOMMU_PTE_U (1ULL << 59) |
333 | #define IOMMU_PTE_FC (1ULL << 60) | |
334 | #define IOMMU_PTE_IR (1ULL << 61) | |
335 | #define IOMMU_PTE_IW (1ULL << 62) | |
336 | ||
07a80a6b BH |
337 | /* |
338 | * Bit value definition for DTE fields | |
339 | */ | |
340 | #define DTE_FLAG_V (1ULL << 0) | |
341 | #define DTE_FLAG_TV (1ULL << 1) | |
342 | #define DTE_FLAG_IR (1ULL << 61) | |
343 | #define DTE_FLAG_IW (1ULL << 62) | |
344 | ||
ca9cab3a JR |
345 | #define DTE_FLAG_IOTLB (1ULL << 32) |
346 | #define DTE_FLAG_GV (1ULL << 55) | |
cbf3ccd0 | 347 | #define DTE_FLAG_MASK (0x3ffULL << 32) |
52815b75 JR |
348 | #define DTE_GLX_SHIFT (56) |
349 | #define DTE_GLX_MASK (3) | |
45a01c42 | 350 | #define DEV_DOMID_MASK 0xffffULL |
52815b75 JR |
351 | |
352 | #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) | |
353 | #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) | |
354 | #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL) | |
355 | ||
356 | #define DTE_GCR3_INDEX_A 0 | |
357 | #define DTE_GCR3_INDEX_B 1 | |
358 | #define DTE_GCR3_INDEX_C 1 | |
359 | ||
360 | #define DTE_GCR3_SHIFT_A 58 | |
361 | #define DTE_GCR3_SHIFT_B 16 | |
362 | #define DTE_GCR3_SHIFT_C 43 | |
363 | ||
b16137b1 | 364 | #define GCR3_VALID 0x01ULL |
fd7b5535 | 365 | |
8d283c35 | 366 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
07a80a6b | 367 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR) |
2543a786 | 368 | #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK)) |
8d283c35 JR |
369 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) |
370 | ||
371 | #define IOMMU_PROT_MASK 0x03 | |
372 | #define IOMMU_PROT_IR 0x01 | |
373 | #define IOMMU_PROT_IW 0x02 | |
374 | ||
375 | /* IOMMU capabilities */ | |
376 | #define IOMMU_CAP_IOTLB 24 | |
377 | #define IOMMU_CAP_NPCACHE 26 | |
d99ddec3 | 378 | #define IOMMU_CAP_EFR 27 |
8d283c35 | 379 | |
3928aa3f SS |
380 | /* IOMMU Feature Reporting Field (for IVHD type 10h */ |
381 | #define IOMMU_FEAT_GASUP_SHIFT 6 | |
382 | ||
383 | /* IOMMU Extended Feature Register (EFR) */ | |
384 | #define IOMMU_EFR_GASUP_SHIFT 7 | |
385 | ||
8d283c35 JR |
386 | #define MAX_DOMAIN_ID 65536 |
387 | ||
9fdb19d6 JR |
388 | /* Protection domain flags */ |
389 | #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ | |
e2dc14a2 JR |
390 | #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops |
391 | domain for an IOMMU */ | |
0feae533 JR |
392 | #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page |
393 | translation */ | |
52815b75 | 394 | #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */ |
0feae533 | 395 | |
fefda117 JR |
396 | extern bool amd_iommu_dump; |
397 | #define DUMP_printk(format, arg...) \ | |
398 | do { \ | |
399 | if (amd_iommu_dump) \ | |
4c6f40d4 | 400 | printk(KERN_INFO "AMD-Vi: " format, ## arg); \ |
fefda117 | 401 | } while(0); |
9fdb19d6 | 402 | |
318afd41 JR |
403 | /* global flag if IOMMUs cache non-present entries */ |
404 | extern bool amd_iommu_np_cache; | |
60f723b4 JR |
405 | /* Only true if all IOMMUs support device IOTLBs */ |
406 | extern bool amd_iommu_iotlb_sup; | |
318afd41 | 407 | |
05152a04 JR |
408 | #define MAX_IRQS_PER_TABLE 256 |
409 | #define IRQ_TABLE_ALIGNMENT 128 | |
410 | ||
0ea2c422 | 411 | struct irq_remap_table { |
27790398 | 412 | raw_spinlock_t lock; |
0ea2c422 JR |
413 | unsigned min_index; |
414 | u32 *table; | |
415 | }; | |
416 | ||
417 | extern struct irq_remap_table **irq_lookup_table; | |
418 | ||
05152a04 JR |
419 | /* Interrupt remapping feature used? */ |
420 | extern bool amd_iommu_irq_remap; | |
421 | ||
422 | /* kmem_cache to get tables with 128 byte alignement */ | |
423 | extern struct kmem_cache *amd_iommu_irq_cache; | |
424 | ||
3bd22172 JR |
425 | /* |
426 | * Make iterating over all IOMMUs easier | |
427 | */ | |
428 | #define for_each_iommu(iommu) \ | |
429 | list_for_each_entry((iommu), &amd_iommu_list, list) | |
430 | #define for_each_iommu_safe(iommu, next) \ | |
431 | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) | |
432 | ||
384de729 JR |
433 | #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
434 | #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) | |
435 | #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) | |
436 | #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ | |
437 | #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) | |
438 | #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) | |
9fdb19d6 | 439 | |
72e1dcc4 JR |
440 | |
441 | /* | |
442 | * This struct is used to pass information about | |
443 | * incoming PPR faults around. | |
444 | */ | |
445 | struct amd_iommu_fault { | |
446 | u64 address; /* IO virtual address of the fault*/ | |
447 | u32 pasid; /* Address space identifier */ | |
448 | u16 device_id; /* Originating PCI device id */ | |
449 | u16 tag; /* PPR tag */ | |
450 | u16 flags; /* Fault flags */ | |
451 | ||
452 | }; | |
453 | ||
72e1dcc4 | 454 | |
f3572db8 | 455 | struct iommu_domain; |
7c71d306 | 456 | struct irq_domain; |
880ac60e | 457 | struct amd_irte_ops; |
f3572db8 | 458 | |
4c232a70 BH |
459 | #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0) |
460 | ||
5694703f JR |
461 | /* |
462 | * This structure contains generic data for IOMMU protection domains | |
463 | * independent of their use. | |
464 | */ | |
8d283c35 | 465 | struct protection_domain { |
aeb26f55 | 466 | struct list_head list; /* for list of all protection domains */ |
7c392cbe | 467 | struct list_head dev_list; /* List of all devices in this domain */ |
3f4b87b9 JR |
468 | struct iommu_domain domain; /* generic domain handle used by |
469 | iommu core code */ | |
9fdb19d6 | 470 | spinlock_t lock; /* mostly used to lock the page table*/ |
5d214fe6 | 471 | struct mutex api_lock; /* protect page tables in the iommu-api path */ |
9fdb19d6 JR |
472 | u16 id; /* the domain id written to the device table */ |
473 | int mode; /* paging mode (0-6 levels) */ | |
474 | u64 *pt_root; /* page table root pointer */ | |
52815b75 JR |
475 | int glx; /* Number of levels for GCR3 table */ |
476 | u64 *gcr3_tbl; /* Guest CR3 table */ | |
9fdb19d6 | 477 | unsigned long flags; /* flags to find out type of domain */ |
04bfdd84 | 478 | bool updated; /* complete domain flush required */ |
863c74eb | 479 | unsigned dev_cnt; /* devices assigned to this domain */ |
c4596114 | 480 | unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ |
8d283c35 JR |
481 | }; |
482 | ||
5694703f JR |
483 | /* |
484 | * Structure where we save information about one hardware AMD IOMMU in the | |
485 | * system. | |
486 | */ | |
8d283c35 JR |
487 | struct amd_iommu { |
488 | struct list_head list; | |
5694703f | 489 | |
bb52777e JR |
490 | /* Index within the IOMMU array */ |
491 | int index; | |
492 | ||
5694703f | 493 | /* locks the accesses to the hardware */ |
27790398 | 494 | raw_spinlock_t lock; |
8d283c35 | 495 | |
3eaf28a1 JR |
496 | /* Pointer to PCI device of this IOMMU */ |
497 | struct pci_dev *dev; | |
498 | ||
c1bf94ec JR |
499 | /* Cache pdev to root device for resume quirks */ |
500 | struct pci_dev *root_pdev; | |
501 | ||
5694703f | 502 | /* physical address of MMIO space */ |
8d283c35 | 503 | u64 mmio_phys; |
30861ddc SK |
504 | |
505 | /* physical end address of MMIO space */ | |
506 | u64 mmio_phys_end; | |
507 | ||
5694703f | 508 | /* virtual address of MMIO space */ |
98f1ad25 | 509 | u8 __iomem *mmio_base; |
5694703f JR |
510 | |
511 | /* capabilities of that IOMMU read from ACPI */ | |
8d283c35 | 512 | u32 cap; |
5694703f | 513 | |
e9bf5197 JR |
514 | /* flags read from acpi table */ |
515 | u8 acpi_flags; | |
516 | ||
d99ddec3 JR |
517 | /* Extended features */ |
518 | u64 features; | |
519 | ||
400a28a0 JR |
520 | /* IOMMUv2 */ |
521 | bool is_iommu_v2; | |
522 | ||
23c742db JR |
523 | /* PCI device id of the IOMMU device */ |
524 | u16 devid; | |
525 | ||
eac9fbc6 RK |
526 | /* |
527 | * Capability pointer. There could be more than one IOMMU per PCI | |
528 | * device function if there are more than one AMD IOMMU capability | |
529 | * pointers. | |
530 | */ | |
531 | u16 cap_ptr; | |
532 | ||
ee893c24 JR |
533 | /* pci domain of this IOMMU */ |
534 | u16 pci_seg; | |
535 | ||
5694703f | 536 | /* start of exclusion range of that IOMMU */ |
8d283c35 | 537 | u64 exclusion_start; |
5694703f | 538 | /* length of exclusion range of that IOMMU */ |
8d283c35 JR |
539 | u64 exclusion_length; |
540 | ||
5694703f | 541 | /* command buffer virtual address */ |
8d283c35 | 542 | u8 *cmd_buf; |
d334a563 TL |
543 | u32 cmd_buf_head; |
544 | u32 cmd_buf_tail; | |
8d283c35 | 545 | |
eac9fbc6 RK |
546 | /* event buffer virtual address */ |
547 | u8 *evt_buf; | |
335503e5 | 548 | |
1a29ac01 JR |
549 | /* Base of the PPR log, if present */ |
550 | u8 *ppr_log; | |
551 | ||
8bda0cfb SS |
552 | /* Base of the GA log, if present */ |
553 | u8 *ga_log; | |
554 | ||
555 | /* Tail of the GA log, if present */ | |
556 | u8 *ga_log_tail; | |
557 | ||
a80dc3e0 JR |
558 | /* true if interrupts for this IOMMU are already enabled */ |
559 | bool int_enabled; | |
560 | ||
eac9fbc6 | 561 | /* if one, we need to send a completion wait command */ |
0cfd7aa9 | 562 | bool need_sync; |
eac9fbc6 | 563 | |
b0119e87 JR |
564 | /* Handle for IOMMU core code */ |
565 | struct iommu_device iommu; | |
566 | ||
4c894f47 | 567 | /* |
5bcd757f MG |
568 | * We can't rely on the BIOS to restore all values on reinit, so we |
569 | * need to stash them | |
4c894f47 | 570 | */ |
5bcd757f MG |
571 | |
572 | /* The iommu BAR */ | |
573 | u32 stored_addr_lo; | |
574 | u32 stored_addr_hi; | |
575 | ||
576 | /* | |
577 | * Each iommu has 6 l1s, each of which is documented as having 0x12 | |
578 | * registers | |
579 | */ | |
580 | u32 stored_l1[6][0x12]; | |
581 | ||
582 | /* The l2 indirect registers */ | |
583 | u32 stored_l2[0x83]; | |
30861ddc SK |
584 | |
585 | /* The maximum PC banks and counters/bank (PCSup=1) */ | |
586 | u8 max_banks; | |
587 | u8 max_counters; | |
7c71d306 JL |
588 | #ifdef CONFIG_IRQ_REMAP |
589 | struct irq_domain *ir_domain; | |
590 | struct irq_domain *msi_domain; | |
880ac60e SS |
591 | |
592 | struct amd_irte_ops *irte_ops; | |
7c71d306 | 593 | #endif |
4bf5beef | 594 | |
4c232a70 | 595 | u32 flags; |
4bf5beef | 596 | volatile u64 __aligned(8) cmd_sem; |
8d283c35 JR |
597 | }; |
598 | ||
b7a42b9d JR |
599 | static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev) |
600 | { | |
2926a2aa JR |
601 | struct iommu_device *iommu = dev_to_iommu_device(dev); |
602 | ||
603 | return container_of(iommu, struct amd_iommu, iommu); | |
b7a42b9d JR |
604 | } |
605 | ||
2a0cb4e2 WZ |
606 | #define ACPIHID_UID_LEN 256 |
607 | #define ACPIHID_HID_LEN 9 | |
608 | ||
609 | struct acpihid_map_entry { | |
610 | struct list_head list; | |
611 | u8 uid[ACPIHID_UID_LEN]; | |
612 | u8 hid[ACPIHID_HID_LEN]; | |
613 | u16 devid; | |
614 | u16 root_devid; | |
615 | bool cmd_line; | |
616 | struct iommu_group *group; | |
617 | }; | |
618 | ||
6efed63b JR |
619 | struct devid_map { |
620 | struct list_head list; | |
621 | u8 id; | |
622 | u16 devid; | |
31cff67f | 623 | bool cmd_line; |
6efed63b JR |
624 | }; |
625 | ||
daae2d25 BH |
626 | /* |
627 | * This struct contains device specific data for the IOMMU | |
628 | */ | |
629 | struct iommu_dev_data { | |
630 | struct list_head list; /* For domain->dev_list */ | |
779da732 | 631 | struct llist_node dev_data_list; /* For global dev_data_list */ |
daae2d25 BH |
632 | struct protection_domain *domain; /* Domain the device is bound to */ |
633 | u16 devid; /* PCI Device ID */ | |
634 | u16 alias; /* Alias Device ID */ | |
635 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
636 | bool passthrough; /* Device is identity mapped */ | |
637 | struct { | |
638 | bool enabled; | |
639 | int qdep; | |
640 | } ats; /* ATS state */ | |
641 | bool pri_tlp; /* PASID TLB required for | |
642 | PPR completions */ | |
643 | u32 errata; /* Bitmap for errata to apply */ | |
644 | bool use_vapic; /* Enable device to use vapic mode */ | |
645 | bool defer_attach; | |
646 | ||
647 | struct ratelimit_state rs; /* Ratelimit IOPF messages */ | |
648 | }; | |
649 | ||
6efed63b JR |
650 | /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ |
651 | extern struct list_head ioapic_map; | |
652 | extern struct list_head hpet_map; | |
2a0cb4e2 | 653 | extern struct list_head acpihid_map; |
6efed63b | 654 | |
5694703f JR |
655 | /* |
656 | * List with all IOMMUs in the system. This list is not locked because it is | |
657 | * only written and read at driver initialization or suspend time | |
658 | */ | |
8d283c35 JR |
659 | extern struct list_head amd_iommu_list; |
660 | ||
bb52777e JR |
661 | /* |
662 | * Array with pointers to each IOMMU struct | |
663 | * The indices are referenced in the protection domains | |
664 | */ | |
665 | extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
666 | ||
aeb26f55 JR |
667 | /* |
668 | * Declarations for the global list of all protection domains | |
669 | */ | |
670 | extern spinlock_t amd_iommu_pd_lock; | |
671 | extern struct list_head amd_iommu_pd_list; | |
672 | ||
5694703f JR |
673 | /* |
674 | * Structure defining one entry in the device table | |
675 | */ | |
8d283c35 | 676 | struct dev_table_entry { |
ee6c2868 | 677 | u64 data[4]; |
8d283c35 JR |
678 | }; |
679 | ||
5694703f JR |
680 | /* |
681 | * One entry for unity mappings parsed out of the ACPI table. | |
682 | */ | |
8d283c35 JR |
683 | struct unity_map_entry { |
684 | struct list_head list; | |
5694703f JR |
685 | |
686 | /* starting device id this entry is used for (including) */ | |
8d283c35 | 687 | u16 devid_start; |
5694703f | 688 | /* end device id this entry is used for (including) */ |
8d283c35 | 689 | u16 devid_end; |
5694703f JR |
690 | |
691 | /* start address to unity map (including) */ | |
8d283c35 | 692 | u64 address_start; |
5694703f | 693 | /* end address to unity map (including) */ |
8d283c35 | 694 | u64 address_end; |
5694703f JR |
695 | |
696 | /* required protection */ | |
8d283c35 JR |
697 | int prot; |
698 | }; | |
699 | ||
5694703f JR |
700 | /* |
701 | * List of all unity mappings. It is not locked because as runtime it is only | |
702 | * read. It is created at ACPI table parsing time. | |
703 | */ | |
8d283c35 JR |
704 | extern struct list_head amd_iommu_unity_map; |
705 | ||
5694703f JR |
706 | /* |
707 | * Data structures for device handling | |
708 | */ | |
709 | ||
710 | /* | |
711 | * Device table used by hardware. Read and write accesses by software are | |
712 | * locked with the amd_iommu_pd_table lock. | |
713 | */ | |
8d283c35 | 714 | extern struct dev_table_entry *amd_iommu_dev_table; |
5694703f JR |
715 | |
716 | /* | |
717 | * Alias table to find requestor ids to device ids. Not locked because only | |
718 | * read on runtime. | |
719 | */ | |
8d283c35 | 720 | extern u16 *amd_iommu_alias_table; |
5694703f JR |
721 | |
722 | /* | |
723 | * Reverse lookup table to find the IOMMU which translates a specific device. | |
724 | */ | |
8d283c35 JR |
725 | extern struct amd_iommu **amd_iommu_rlookup_table; |
726 | ||
5694703f | 727 | /* size of the dma_ops aperture as power of 2 */ |
8d283c35 JR |
728 | extern unsigned amd_iommu_aperture_order; |
729 | ||
5694703f | 730 | /* largest PCI device id we expect translation requests for */ |
8d283c35 JR |
731 | extern u16 amd_iommu_last_bdf; |
732 | ||
5694703f | 733 | /* allocation bitmap for domain ids */ |
8d283c35 JR |
734 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
735 | ||
afa9fdc2 FT |
736 | /* |
737 | * If true, the addresses will be flushed on unmap time, not when | |
738 | * they are reused | |
739 | */ | |
621a5f7a | 740 | extern bool amd_iommu_unmap_flush; |
afa9fdc2 | 741 | |
a919a018 SS |
742 | /* Smallest max PASID supported by any IOMMU in the system */ |
743 | extern u32 amd_iommu_max_pasid; | |
62f71abb | 744 | |
400a28a0 JR |
745 | extern bool amd_iommu_v2_present; |
746 | ||
5abcdba4 JR |
747 | extern bool amd_iommu_force_isolation; |
748 | ||
52815b75 JR |
749 | /* Max levels of glxval supported */ |
750 | extern int amd_iommu_max_glx_val; | |
751 | ||
98f1ad25 JR |
752 | /* |
753 | * This function flushes all internal caches of | |
754 | * the IOMMU used by this driver. | |
755 | */ | |
756 | extern void iommu_flush_all_caches(struct amd_iommu *iommu); | |
757 | ||
6efed63b JR |
758 | static inline int get_ioapic_devid(int id) |
759 | { | |
760 | struct devid_map *entry; | |
761 | ||
762 | list_for_each_entry(entry, &ioapic_map, list) { | |
763 | if (entry->id == id) | |
764 | return entry->devid; | |
765 | } | |
766 | ||
767 | return -EINVAL; | |
768 | } | |
769 | ||
770 | static inline int get_hpet_devid(int id) | |
771 | { | |
772 | struct devid_map *entry; | |
773 | ||
774 | list_for_each_entry(entry, &hpet_map, list) { | |
775 | if (entry->id == id) | |
776 | return entry->devid; | |
777 | } | |
778 | ||
779 | return -EINVAL; | |
780 | } | |
781 | ||
3928aa3f SS |
782 | enum amd_iommu_intr_mode_type { |
783 | AMD_IOMMU_GUEST_IR_LEGACY, | |
784 | ||
785 | /* This mode is not visible to users. It is used when | |
786 | * we cannot fully enable vAPIC and fallback to only support | |
787 | * legacy interrupt remapping via 128-bit IRTE. | |
788 | */ | |
789 | AMD_IOMMU_GUEST_IR_LEGACY_GA, | |
790 | AMD_IOMMU_GUEST_IR_VAPIC, | |
791 | }; | |
792 | ||
793 | #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \ | |
794 | x == AMD_IOMMU_GUEST_IR_LEGACY_GA) | |
795 | ||
796 | #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC) | |
a38180bd SS |
797 | |
798 | union irte { | |
799 | u32 val; | |
800 | struct { | |
801 | u32 valid : 1, | |
802 | no_fault : 1, | |
803 | int_type : 3, | |
804 | rq_eoi : 1, | |
805 | dm : 1, | |
806 | rsvd_1 : 1, | |
807 | destination : 8, | |
808 | vector : 8, | |
809 | rsvd_2 : 8; | |
810 | } fields; | |
811 | }; | |
812 | ||
813 | union irte_ga_lo { | |
814 | u64 val; | |
815 | ||
816 | /* For int remapping */ | |
817 | struct { | |
818 | u64 valid : 1, | |
819 | no_fault : 1, | |
820 | /* ------ */ | |
821 | int_type : 3, | |
822 | rq_eoi : 1, | |
823 | dm : 1, | |
824 | /* ------ */ | |
825 | guest_mode : 1, | |
826 | destination : 8, | |
827 | rsvd : 48; | |
828 | } fields_remap; | |
829 | ||
830 | /* For guest vAPIC */ | |
831 | struct { | |
832 | u64 valid : 1, | |
833 | no_fault : 1, | |
834 | /* ------ */ | |
835 | ga_log_intr : 1, | |
836 | rsvd1 : 3, | |
837 | is_run : 1, | |
838 | /* ------ */ | |
839 | guest_mode : 1, | |
840 | destination : 8, | |
841 | rsvd2 : 16, | |
842 | ga_tag : 32; | |
843 | } fields_vapic; | |
844 | }; | |
845 | ||
846 | union irte_ga_hi { | |
847 | u64 val; | |
848 | struct { | |
849 | u64 vector : 8, | |
850 | rsvd_1 : 4, | |
851 | ga_root_ptr : 40, | |
852 | rsvd_2 : 12; | |
853 | } fields; | |
854 | }; | |
855 | ||
856 | struct irte_ga { | |
857 | union irte_ga_lo lo; | |
858 | union irte_ga_hi hi; | |
859 | }; | |
860 | ||
861 | struct irq_2_irte { | |
862 | u16 devid; /* Device ID for IRTE table */ | |
863 | u16 index; /* Index into IRTE table*/ | |
864 | }; | |
865 | ||
866 | struct amd_ir_data { | |
b9fc6b56 | 867 | u32 cached_ga_tag; |
a38180bd | 868 | struct irq_2_irte irq_2_irte; |
a38180bd | 869 | struct msi_msg msi_entry; |
880ac60e | 870 | void *entry; /* Pointer to union irte or struct irte_ga */ |
8dbea3fd | 871 | void *ref; /* Pointer to the actual irte */ |
880ac60e SS |
872 | }; |
873 | ||
874 | struct amd_irte_ops { | |
d98de49a | 875 | void (*prepare)(void *, u32, u32, u8, u32, int); |
880ac60e SS |
876 | void (*activate)(void *, u16, u16); |
877 | void (*deactivate)(void *, u16, u16); | |
878 | void (*set_affinity)(void *, u16, u16, u8, u32); | |
879 | void *(*get)(struct irq_remap_table *, int); | |
880 | void (*set_allocated)(struct irq_remap_table *, int); | |
881 | bool (*is_allocated)(struct irq_remap_table *, int); | |
882 | void (*clear_allocated)(struct irq_remap_table *, int); | |
a38180bd SS |
883 | }; |
884 | ||
880ac60e SS |
885 | #ifdef CONFIG_IRQ_REMAP |
886 | extern struct amd_irte_ops irte_32_ops; | |
887 | extern struct amd_irte_ops irte_128_ops; | |
888 | #endif | |
889 | ||
1965aae3 | 890 | #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ |