Commit | Line | Data |
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f6e2e6b6 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
f6e2e6b6 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
f6e2e6b6 | 22 | #include <linux/list.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
f3c6ea1b | 24 | #include <linux/syscore_ops.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
403f81d8 | 27 | #include <linux/amd-iommu.h> |
400a28a0 | 28 | #include <linux/export.h> |
066f2e98 | 29 | #include <linux/iommu.h> |
f6e2e6b6 | 30 | #include <asm/pci-direct.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
ea1b0d39 | 33 | #include <asm/x86_init.h> |
22e6daf4 | 34 | #include <asm/iommu_table.h> |
eb1eb7ae | 35 | #include <asm/io_apic.h> |
6b474b82 | 36 | #include <asm/irq_remapping.h> |
403f81d8 JR |
37 | |
38 | #include "amd_iommu_proto.h" | |
39 | #include "amd_iommu_types.h" | |
05152a04 | 40 | #include "irq_remapping.h" |
403f81d8 | 41 | |
f6e2e6b6 JR |
42 | /* |
43 | * definitions for the ACPI scanning code | |
44 | */ | |
f6e2e6b6 | 45 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
46 | |
47 | #define ACPI_IVHD_TYPE 0x10 | |
48 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
49 | #define ACPI_IVMD_TYPE 0x21 | |
50 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
51 | ||
52 | #define IVHD_DEV_ALL 0x01 | |
53 | #define IVHD_DEV_SELECT 0x02 | |
54 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
55 | #define IVHD_DEV_RANGE_END 0x04 | |
56 | #define IVHD_DEV_ALIAS 0x42 | |
57 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
58 | #define IVHD_DEV_EXT_SELECT 0x46 | |
59 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
6efed63b JR |
60 | #define IVHD_DEV_SPECIAL 0x48 |
61 | ||
62 | #define IVHD_SPECIAL_IOAPIC 1 | |
63 | #define IVHD_SPECIAL_HPET 2 | |
f6e2e6b6 | 64 | |
6da7342f JR |
65 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
66 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
67 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
68 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
69 | |
70 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
71 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
72 | ||
73 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
74 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
75 | #define ACPI_DEVFLAG_NMI 0x04 | |
76 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
77 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
78 | #define ACPI_DEVFLAG_LINT0 0x40 | |
79 | #define ACPI_DEVFLAG_LINT1 0x80 | |
80 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
81 | ||
b65233a9 JR |
82 | /* |
83 | * ACPI table definitions | |
84 | * | |
85 | * These data structures are laid over the table to parse the important values | |
86 | * out of it. | |
87 | */ | |
88 | ||
89 | /* | |
90 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
91 | * or more ivhd_entrys. | |
92 | */ | |
f6e2e6b6 JR |
93 | struct ivhd_header { |
94 | u8 type; | |
95 | u8 flags; | |
96 | u16 length; | |
97 | u16 devid; | |
98 | u16 cap_ptr; | |
99 | u64 mmio_phys; | |
100 | u16 pci_seg; | |
101 | u16 info; | |
7d7d38af SS |
102 | u32 efr_attr; |
103 | ||
104 | /* Following only valid on IVHD type 11h and 40h */ | |
105 | u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ | |
106 | u64 res; | |
f6e2e6b6 JR |
107 | } __attribute__((packed)); |
108 | ||
b65233a9 JR |
109 | /* |
110 | * A device entry describing which devices a specific IOMMU translates and | |
111 | * which requestor ids they use. | |
112 | */ | |
f6e2e6b6 JR |
113 | struct ivhd_entry { |
114 | u8 type; | |
115 | u16 devid; | |
116 | u8 flags; | |
117 | u32 ext; | |
118 | } __attribute__((packed)); | |
119 | ||
b65233a9 JR |
120 | /* |
121 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
122 | * ranges for devices and regions that should be unity mapped. | |
123 | */ | |
f6e2e6b6 JR |
124 | struct ivmd_header { |
125 | u8 type; | |
126 | u8 flags; | |
127 | u16 length; | |
128 | u16 devid; | |
129 | u16 aux; | |
130 | u64 resv; | |
131 | u64 range_start; | |
132 | u64 range_length; | |
133 | } __attribute__((packed)); | |
134 | ||
fefda117 | 135 | bool amd_iommu_dump; |
05152a04 | 136 | bool amd_iommu_irq_remap __read_mostly; |
fefda117 | 137 | |
02f3b3f5 | 138 | static bool amd_iommu_detected; |
a5235725 | 139 | static bool __initdata amd_iommu_disabled; |
c1cbebee | 140 | |
b65233a9 JR |
141 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
142 | to handle */ | |
2e22847f | 143 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 144 | we find in ACPI */ |
621a5f7a | 145 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 146 | |
2e22847f | 147 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 148 | system */ |
928abd25 | 149 | |
bb52777e JR |
150 | /* Array to assign indices to IOMMUs*/ |
151 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
152 | int amd_iommus_present; | |
153 | ||
318afd41 JR |
154 | /* IOMMUs have a non-present cache? */ |
155 | bool amd_iommu_np_cache __read_mostly; | |
60f723b4 | 156 | bool amd_iommu_iotlb_sup __read_mostly = true; |
318afd41 | 157 | |
a919a018 | 158 | u32 amd_iommu_max_pasid __read_mostly = ~0; |
62f71abb | 159 | |
400a28a0 | 160 | bool amd_iommu_v2_present __read_mostly; |
4160cd9e | 161 | static bool amd_iommu_pc_present __read_mostly; |
400a28a0 | 162 | |
5abcdba4 JR |
163 | bool amd_iommu_force_isolation __read_mostly; |
164 | ||
aeb26f55 JR |
165 | /* |
166 | * List of protection domains - used during resume | |
167 | */ | |
168 | LIST_HEAD(amd_iommu_pd_list); | |
169 | spinlock_t amd_iommu_pd_lock; | |
170 | ||
b65233a9 JR |
171 | /* |
172 | * Pointer to the device table which is shared by all AMD IOMMUs | |
173 | * it is indexed by the PCI device id or the HT unit id and contains | |
174 | * information about the domain the device belongs to as well as the | |
175 | * page table root pointer. | |
176 | */ | |
928abd25 | 177 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
178 | |
179 | /* | |
180 | * The alias table is a driver specific data structure which contains the | |
181 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
182 | * More than one device can share the same requestor id. | |
183 | */ | |
928abd25 | 184 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
185 | |
186 | /* | |
187 | * The rlookup table is used to find the IOMMU which is responsible | |
188 | * for a specific device. It is also indexed by the PCI device id. | |
189 | */ | |
928abd25 | 190 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 | 191 | |
b65233a9 | 192 | /* |
0ea2c422 JR |
193 | * This table is used to find the irq remapping table for a given device id |
194 | * quickly. | |
195 | */ | |
196 | struct irq_remap_table **irq_lookup_table; | |
197 | ||
b65233a9 | 198 | /* |
df805abb | 199 | * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap |
b65233a9 JR |
200 | * to know which ones are already in use. |
201 | */ | |
928abd25 JR |
202 | unsigned long *amd_iommu_pd_alloc_bitmap; |
203 | ||
b65233a9 JR |
204 | static u32 dev_table_size; /* size of the device table */ |
205 | static u32 alias_table_size; /* size of the alias table */ | |
206 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 207 | |
2c0ae172 JR |
208 | enum iommu_init_state { |
209 | IOMMU_START_STATE, | |
210 | IOMMU_IVRS_DETECTED, | |
211 | IOMMU_ACPI_FINISHED, | |
212 | IOMMU_ENABLED, | |
213 | IOMMU_PCI_INIT, | |
214 | IOMMU_INTERRUPTS_EN, | |
215 | IOMMU_DMA_OPS, | |
216 | IOMMU_INITIALIZED, | |
217 | IOMMU_NOT_FOUND, | |
218 | IOMMU_INIT_ERROR, | |
219 | }; | |
220 | ||
235dacbc JR |
221 | /* Early ioapic and hpet maps from kernel command line */ |
222 | #define EARLY_MAP_SIZE 4 | |
223 | static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; | |
224 | static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; | |
225 | static int __initdata early_ioapic_map_size; | |
226 | static int __initdata early_hpet_map_size; | |
dfbb6d47 | 227 | static bool __initdata cmdline_maps; |
235dacbc | 228 | |
2c0ae172 JR |
229 | static enum iommu_init_state init_state = IOMMU_START_STATE; |
230 | ||
ae295142 | 231 | static int amd_iommu_enable_interrupts(void); |
2c0ae172 | 232 | static int __init iommu_go_to_state(enum iommu_init_state state); |
aafd8ba0 | 233 | static void init_device_table_dma(void); |
3d9761e7 | 234 | |
38e45d02 SS |
235 | static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu, |
236 | u8 bank, u8 cntr, u8 fxn, | |
237 | u64 *value, bool is_write); | |
238 | ||
208ec8c9 JR |
239 | static inline void update_last_devid(u16 devid) |
240 | { | |
241 | if (devid > amd_iommu_last_bdf) | |
242 | amd_iommu_last_bdf = devid; | |
243 | } | |
244 | ||
c571484e JR |
245 | static inline unsigned long tbl_size(int entry_size) |
246 | { | |
247 | unsigned shift = PAGE_SHIFT + | |
421f909c | 248 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
249 | |
250 | return 1UL << shift; | |
251 | } | |
252 | ||
5bcd757f MG |
253 | /* Access to l1 and l2 indexed register spaces */ |
254 | ||
255 | static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) | |
256 | { | |
257 | u32 val; | |
258 | ||
259 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
260 | pci_read_config_dword(iommu->dev, 0xfc, &val); | |
261 | return val; | |
262 | } | |
263 | ||
264 | static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) | |
265 | { | |
266 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); | |
267 | pci_write_config_dword(iommu->dev, 0xfc, val); | |
268 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
269 | } | |
270 | ||
271 | static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) | |
272 | { | |
273 | u32 val; | |
274 | ||
275 | pci_write_config_dword(iommu->dev, 0xf0, address); | |
276 | pci_read_config_dword(iommu->dev, 0xf4, &val); | |
277 | return val; | |
278 | } | |
279 | ||
280 | static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) | |
281 | { | |
282 | pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); | |
283 | pci_write_config_dword(iommu->dev, 0xf4, val); | |
284 | } | |
285 | ||
b65233a9 JR |
286 | /**************************************************************************** |
287 | * | |
288 | * AMD IOMMU MMIO register space handling functions | |
289 | * | |
290 | * These functions are used to program the IOMMU device registers in | |
291 | * MMIO space required for that driver. | |
292 | * | |
293 | ****************************************************************************/ | |
3e8064ba | 294 | |
b65233a9 JR |
295 | /* |
296 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
297 | * exclusion range are passed through untranslated | |
298 | */ | |
05f92db9 | 299 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
300 | { |
301 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
302 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
303 | u64 entry; | |
304 | ||
305 | if (!iommu->exclusion_start) | |
306 | return; | |
307 | ||
308 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
309 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
310 | &entry, sizeof(entry)); | |
311 | ||
312 | entry = limit; | |
313 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
314 | &entry, sizeof(entry)); | |
315 | } | |
316 | ||
b65233a9 | 317 | /* Programs the physical address of the device table into the IOMMU hardware */ |
6b7f000e | 318 | static void iommu_set_device_table(struct amd_iommu *iommu) |
b2026aa2 | 319 | { |
f609891f | 320 | u64 entry; |
b2026aa2 JR |
321 | |
322 | BUG_ON(iommu->mmio_base == NULL); | |
323 | ||
324 | entry = virt_to_phys(amd_iommu_dev_table); | |
325 | entry |= (dev_table_size >> 12) - 1; | |
326 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
327 | &entry, sizeof(entry)); | |
328 | } | |
329 | ||
b65233a9 | 330 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 331 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
332 | { |
333 | u32 ctrl; | |
334 | ||
335 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
336 | ctrl |= (1 << bit); | |
337 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
338 | } | |
339 | ||
ca020711 | 340 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
341 | { |
342 | u32 ctrl; | |
343 | ||
199d0d50 | 344 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
345 | ctrl &= ~(1 << bit); |
346 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
347 | } | |
348 | ||
1456e9d2 JR |
349 | static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) |
350 | { | |
351 | u32 ctrl; | |
352 | ||
353 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
354 | ctrl &= ~CTRL_INV_TO_MASK; | |
355 | ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; | |
356 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
357 | } | |
358 | ||
b65233a9 | 359 | /* Function to enable the hardware */ |
05f92db9 | 360 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 361 | { |
b2026aa2 | 362 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); |
b2026aa2 JR |
363 | } |
364 | ||
92ac4320 | 365 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 366 | { |
a8c485bb CW |
367 | /* Disable command buffer */ |
368 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
369 | ||
370 | /* Disable event logging and event interrupts */ | |
371 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
372 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
373 | ||
374 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 375 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
376 | } |
377 | ||
b65233a9 JR |
378 | /* |
379 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
380 | * the system has one. | |
381 | */ | |
30861ddc | 382 | static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) |
6c56747b | 383 | { |
30861ddc SK |
384 | if (!request_mem_region(address, end, "amd_iommu")) { |
385 | pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n", | |
386 | address, end); | |
e82752d8 | 387 | pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n"); |
6c56747b | 388 | return NULL; |
e82752d8 | 389 | } |
6c56747b | 390 | |
30861ddc | 391 | return (u8 __iomem *)ioremap_nocache(address, end); |
6c56747b JR |
392 | } |
393 | ||
394 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
395 | { | |
396 | if (iommu->mmio_base) | |
397 | iounmap(iommu->mmio_base); | |
30861ddc | 398 | release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); |
6c56747b JR |
399 | } |
400 | ||
ac7ccf67 SS |
401 | static inline u32 get_ivhd_header_size(struct ivhd_header *h) |
402 | { | |
403 | u32 size = 0; | |
404 | ||
405 | switch (h->type) { | |
406 | case 0x10: | |
407 | size = 24; | |
408 | break; | |
409 | case 0x11: | |
410 | case 0x40: | |
411 | size = 40; | |
412 | break; | |
413 | } | |
414 | return size; | |
415 | } | |
416 | ||
b65233a9 JR |
417 | /**************************************************************************** |
418 | * | |
419 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
420 | * parsing. In this pass we try to find out the highest device id this | |
421 | * code has to handle. Upon this information the size of the shared data | |
422 | * structures is determined later. | |
423 | * | |
424 | ****************************************************************************/ | |
425 | ||
b514e555 JR |
426 | /* |
427 | * This function calculates the length of a given IVHD entry | |
428 | */ | |
429 | static inline int ivhd_entry_length(u8 *ivhd) | |
430 | { | |
431 | return 0x04 << (*ivhd >> 6); | |
432 | } | |
433 | ||
b65233a9 JR |
434 | /* |
435 | * After reading the highest device id from the IOMMU PCI capability header | |
436 | * this function looks if there is a higher device id defined in the ACPI table | |
437 | */ | |
3e8064ba JR |
438 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
439 | { | |
440 | u8 *p = (void *)h, *end = (void *)h; | |
441 | struct ivhd_entry *dev; | |
442 | ||
ac7ccf67 SS |
443 | u32 ivhd_size = get_ivhd_header_size(h); |
444 | ||
445 | if (!ivhd_size) { | |
446 | pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type); | |
447 | return -EINVAL; | |
448 | } | |
449 | ||
450 | p += ivhd_size; | |
3e8064ba JR |
451 | end += h->length; |
452 | ||
3e8064ba JR |
453 | while (p < end) { |
454 | dev = (struct ivhd_entry *)p; | |
455 | switch (dev->type) { | |
d1259416 JR |
456 | case IVHD_DEV_ALL: |
457 | /* Use maximum BDF value for DEV_ALL */ | |
458 | update_last_devid(0xffff); | |
459 | break; | |
3e8064ba JR |
460 | case IVHD_DEV_SELECT: |
461 | case IVHD_DEV_RANGE_END: | |
462 | case IVHD_DEV_ALIAS: | |
463 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 464 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 465 | update_last_devid(dev->devid); |
3e8064ba JR |
466 | break; |
467 | default: | |
468 | break; | |
469 | } | |
b514e555 | 470 | p += ivhd_entry_length(p); |
3e8064ba JR |
471 | } |
472 | ||
473 | WARN_ON(p != end); | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
b65233a9 JR |
478 | /* |
479 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
480 | * id which we need to handle. This is the first of three functions which parse | |
481 | * the ACPI table. So we check the checksum here. | |
482 | */ | |
3e8064ba JR |
483 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
484 | { | |
485 | int i; | |
486 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
487 | struct ivhd_header *h; | |
488 | ||
489 | /* | |
490 | * Validate checksum here so we don't need to do it when | |
491 | * we actually parse the table | |
492 | */ | |
493 | for (i = 0; i < table->length; ++i) | |
494 | checksum += p[i]; | |
02f3b3f5 | 495 | if (checksum != 0) |
3e8064ba | 496 | /* ACPI table corrupt */ |
02f3b3f5 | 497 | return -ENODEV; |
3e8064ba JR |
498 | |
499 | p += IVRS_HEADER_LENGTH; | |
500 | ||
501 | end += table->length; | |
502 | while (p < end) { | |
503 | h = (struct ivhd_header *)p; | |
504 | switch (h->type) { | |
505 | case ACPI_IVHD_TYPE: | |
506 | find_last_devid_from_ivhd(h); | |
507 | break; | |
508 | default: | |
509 | break; | |
510 | } | |
511 | p += h->length; | |
512 | } | |
513 | WARN_ON(p != end); | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
b65233a9 JR |
518 | /**************************************************************************** |
519 | * | |
df805abb | 520 | * The following functions belong to the code path which parses the ACPI table |
b65233a9 JR |
521 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific |
522 | * data structures, initialize the device/alias/rlookup table and also | |
523 | * basically initialize the hardware. | |
524 | * | |
525 | ****************************************************************************/ | |
526 | ||
527 | /* | |
528 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
529 | * write commands to that buffer later and the IOMMU will execute them | |
530 | * asynchronously | |
531 | */ | |
f2c2db53 | 532 | static int __init alloc_command_buffer(struct amd_iommu *iommu) |
b36ca91e | 533 | { |
f2c2db53 JR |
534 | iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
535 | get_order(CMD_BUFFER_SIZE)); | |
b36ca91e | 536 | |
f2c2db53 | 537 | return iommu->cmd_buf ? 0 : -ENOMEM; |
58492e12 JR |
538 | } |
539 | ||
93f1cc67 JR |
540 | /* |
541 | * This function resets the command buffer if the IOMMU stopped fetching | |
542 | * commands from it. | |
543 | */ | |
544 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
545 | { | |
546 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
547 | ||
548 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
549 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
550 | ||
551 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
552 | } | |
553 | ||
58492e12 JR |
554 | /* |
555 | * This function writes the command buffer address to the hardware and | |
556 | * enables it. | |
557 | */ | |
558 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
559 | { | |
560 | u64 entry; | |
561 | ||
562 | BUG_ON(iommu->cmd_buf == NULL); | |
563 | ||
564 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 565 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 566 | |
b36ca91e | 567 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 568 | &entry, sizeof(entry)); |
b36ca91e | 569 | |
93f1cc67 | 570 | amd_iommu_reset_cmd_buffer(iommu); |
b36ca91e JR |
571 | } |
572 | ||
573 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
574 | { | |
deba4bce | 575 | free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
576 | } |
577 | ||
335503e5 | 578 | /* allocates the memory where the IOMMU will log its events to */ |
f2c2db53 | 579 | static int __init alloc_event_buffer(struct amd_iommu *iommu) |
335503e5 | 580 | { |
f2c2db53 JR |
581 | iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
582 | get_order(EVT_BUFFER_SIZE)); | |
335503e5 | 583 | |
f2c2db53 | 584 | return iommu->evt_buf ? 0 : -ENOMEM; |
58492e12 JR |
585 | } |
586 | ||
587 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
588 | { | |
589 | u64 entry; | |
590 | ||
591 | BUG_ON(iommu->evt_buf == NULL); | |
592 | ||
335503e5 | 593 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 594 | |
335503e5 JR |
595 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
596 | &entry, sizeof(entry)); | |
597 | ||
09067207 JR |
598 | /* set head and tail to zero manually */ |
599 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
600 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
601 | ||
58492e12 | 602 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
603 | } |
604 | ||
605 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
606 | { | |
607 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
608 | } | |
609 | ||
1a29ac01 | 610 | /* allocates the memory where the IOMMU will log its events to */ |
f2c2db53 | 611 | static int __init alloc_ppr_log(struct amd_iommu *iommu) |
1a29ac01 | 612 | { |
f2c2db53 JR |
613 | iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
614 | get_order(PPR_LOG_SIZE)); | |
1a29ac01 | 615 | |
f2c2db53 | 616 | return iommu->ppr_log ? 0 : -ENOMEM; |
1a29ac01 JR |
617 | } |
618 | ||
619 | static void iommu_enable_ppr_log(struct amd_iommu *iommu) | |
620 | { | |
621 | u64 entry; | |
622 | ||
623 | if (iommu->ppr_log == NULL) | |
624 | return; | |
625 | ||
626 | entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; | |
627 | ||
628 | memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, | |
629 | &entry, sizeof(entry)); | |
630 | ||
631 | /* set head and tail to zero manually */ | |
632 | writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
633 | writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
634 | ||
635 | iommu_feature_enable(iommu, CONTROL_PPFLOG_EN); | |
636 | iommu_feature_enable(iommu, CONTROL_PPR_EN); | |
637 | } | |
638 | ||
639 | static void __init free_ppr_log(struct amd_iommu *iommu) | |
640 | { | |
641 | if (iommu->ppr_log == NULL) | |
642 | return; | |
643 | ||
644 | free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); | |
645 | } | |
646 | ||
cbc33a90 JR |
647 | static void iommu_enable_gt(struct amd_iommu *iommu) |
648 | { | |
649 | if (!iommu_feature(iommu, FEATURE_GT)) | |
650 | return; | |
651 | ||
652 | iommu_feature_enable(iommu, CONTROL_GT_EN); | |
653 | } | |
654 | ||
b65233a9 | 655 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
656 | static void set_dev_entry_bit(u16 devid, u8 bit) |
657 | { | |
ee6c2868 JR |
658 | int i = (bit >> 6) & 0x03; |
659 | int _bit = bit & 0x3f; | |
3566b778 | 660 | |
ee6c2868 | 661 | amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); |
3566b778 JR |
662 | } |
663 | ||
c5cca146 JR |
664 | static int get_dev_entry_bit(u16 devid, u8 bit) |
665 | { | |
ee6c2868 JR |
666 | int i = (bit >> 6) & 0x03; |
667 | int _bit = bit & 0x3f; | |
c5cca146 | 668 | |
ee6c2868 | 669 | return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; |
c5cca146 JR |
670 | } |
671 | ||
672 | ||
673 | void amd_iommu_apply_erratum_63(u16 devid) | |
674 | { | |
675 | int sysmgt; | |
676 | ||
677 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
678 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
679 | ||
680 | if (sysmgt == 0x01) | |
681 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
682 | } | |
683 | ||
5ff4789d JR |
684 | /* Writes the specific IOMMU for a device into the rlookup table */ |
685 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
686 | { | |
687 | amd_iommu_rlookup_table[devid] = iommu; | |
688 | } | |
689 | ||
b65233a9 JR |
690 | /* |
691 | * This function takes the device specific flags read from the ACPI | |
692 | * table and sets up the device table entry with that information | |
693 | */ | |
5ff4789d JR |
694 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
695 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
696 | { |
697 | if (flags & ACPI_DEVFLAG_INITPASS) | |
698 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
699 | if (flags & ACPI_DEVFLAG_EXTINT) | |
700 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
701 | if (flags & ACPI_DEVFLAG_NMI) | |
702 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
703 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
704 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
705 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
706 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
707 | if (flags & ACPI_DEVFLAG_LINT0) | |
708 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
709 | if (flags & ACPI_DEVFLAG_LINT1) | |
710 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 711 | |
c5cca146 JR |
712 | amd_iommu_apply_erratum_63(devid); |
713 | ||
5ff4789d | 714 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
715 | } |
716 | ||
c50e3247 | 717 | static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line) |
6efed63b JR |
718 | { |
719 | struct devid_map *entry; | |
720 | struct list_head *list; | |
721 | ||
31cff67f JR |
722 | if (type == IVHD_SPECIAL_IOAPIC) |
723 | list = &ioapic_map; | |
724 | else if (type == IVHD_SPECIAL_HPET) | |
725 | list = &hpet_map; | |
726 | else | |
6efed63b JR |
727 | return -EINVAL; |
728 | ||
31cff67f JR |
729 | list_for_each_entry(entry, list, list) { |
730 | if (!(entry->id == id && entry->cmd_line)) | |
731 | continue; | |
732 | ||
733 | pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n", | |
734 | type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); | |
735 | ||
c50e3247 JR |
736 | *devid = entry->devid; |
737 | ||
31cff67f JR |
738 | return 0; |
739 | } | |
740 | ||
6efed63b JR |
741 | entry = kzalloc(sizeof(*entry), GFP_KERNEL); |
742 | if (!entry) | |
743 | return -ENOMEM; | |
744 | ||
31cff67f | 745 | entry->id = id; |
c50e3247 | 746 | entry->devid = *devid; |
31cff67f | 747 | entry->cmd_line = cmd_line; |
6efed63b JR |
748 | |
749 | list_add_tail(&entry->list, list); | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
235dacbc JR |
754 | static int __init add_early_maps(void) |
755 | { | |
756 | int i, ret; | |
757 | ||
758 | for (i = 0; i < early_ioapic_map_size; ++i) { | |
759 | ret = add_special_device(IVHD_SPECIAL_IOAPIC, | |
760 | early_ioapic_map[i].id, | |
c50e3247 | 761 | &early_ioapic_map[i].devid, |
235dacbc JR |
762 | early_ioapic_map[i].cmd_line); |
763 | if (ret) | |
764 | return ret; | |
765 | } | |
766 | ||
767 | for (i = 0; i < early_hpet_map_size; ++i) { | |
768 | ret = add_special_device(IVHD_SPECIAL_HPET, | |
769 | early_hpet_map[i].id, | |
c50e3247 | 770 | &early_hpet_map[i].devid, |
235dacbc JR |
771 | early_hpet_map[i].cmd_line); |
772 | if (ret) | |
773 | return ret; | |
774 | } | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
b65233a9 | 779 | /* |
df805abb | 780 | * Reads the device exclusion range from ACPI and initializes the IOMMU with |
b65233a9 JR |
781 | * it |
782 | */ | |
3566b778 JR |
783 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
784 | { | |
785 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
786 | ||
787 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
788 | return; | |
789 | ||
790 | if (iommu) { | |
b65233a9 JR |
791 | /* |
792 | * We only can configure exclusion ranges per IOMMU, not | |
793 | * per device. But we can enable the exclusion range per | |
794 | * device. This is done here | |
795 | */ | |
2c16c9fd | 796 | set_dev_entry_bit(devid, DEV_ENTRY_EX); |
3566b778 JR |
797 | iommu->exclusion_start = m->range_start; |
798 | iommu->exclusion_length = m->range_length; | |
799 | } | |
800 | } | |
801 | ||
b65233a9 JR |
802 | /* |
803 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
804 | * initializes the hardware and our data structures with it. | |
805 | */ | |
6efed63b | 806 | static int __init init_iommu_from_acpi(struct amd_iommu *iommu, |
5d0c8e49 JR |
807 | struct ivhd_header *h) |
808 | { | |
809 | u8 *p = (u8 *)h; | |
810 | u8 *end = p, flags = 0; | |
0de66d5b JR |
811 | u16 devid = 0, devid_start = 0, devid_to = 0; |
812 | u32 dev_i, ext_flags = 0; | |
58a3bee5 | 813 | bool alias = false; |
5d0c8e49 | 814 | struct ivhd_entry *e; |
ac7ccf67 | 815 | u32 ivhd_size; |
235dacbc JR |
816 | int ret; |
817 | ||
818 | ||
819 | ret = add_early_maps(); | |
820 | if (ret) | |
821 | return ret; | |
5d0c8e49 JR |
822 | |
823 | /* | |
e9bf5197 | 824 | * First save the recommended feature enable bits from ACPI |
5d0c8e49 | 825 | */ |
e9bf5197 | 826 | iommu->acpi_flags = h->flags; |
5d0c8e49 JR |
827 | |
828 | /* | |
829 | * Done. Now parse the device entries | |
830 | */ | |
ac7ccf67 SS |
831 | ivhd_size = get_ivhd_header_size(h); |
832 | if (!ivhd_size) { | |
833 | pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type); | |
834 | return -EINVAL; | |
835 | } | |
836 | ||
837 | p += ivhd_size; | |
838 | ||
5d0c8e49 JR |
839 | end += h->length; |
840 | ||
42a698f4 | 841 | |
5d0c8e49 JR |
842 | while (p < end) { |
843 | e = (struct ivhd_entry *)p; | |
844 | switch (e->type) { | |
845 | case IVHD_DEV_ALL: | |
42a698f4 | 846 | |
226e889b | 847 | DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags); |
42a698f4 | 848 | |
226e889b JR |
849 | for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i) |
850 | set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); | |
5d0c8e49 JR |
851 | break; |
852 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
853 | |
854 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
855 | "flags: %02x\n", | |
c5081cd7 | 856 | PCI_BUS_NUM(e->devid), |
42a698f4 JR |
857 | PCI_SLOT(e->devid), |
858 | PCI_FUNC(e->devid), | |
859 | e->flags); | |
860 | ||
5d0c8e49 | 861 | devid = e->devid; |
5ff4789d | 862 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
863 | break; |
864 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
865 | |
866 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
867 | "devid: %02x:%02x.%x flags: %02x\n", | |
c5081cd7 | 868 | PCI_BUS_NUM(e->devid), |
42a698f4 JR |
869 | PCI_SLOT(e->devid), |
870 | PCI_FUNC(e->devid), | |
871 | e->flags); | |
872 | ||
5d0c8e49 JR |
873 | devid_start = e->devid; |
874 | flags = e->flags; | |
875 | ext_flags = 0; | |
58a3bee5 | 876 | alias = false; |
5d0c8e49 JR |
877 | break; |
878 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
879 | |
880 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
881 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
c5081cd7 | 882 | PCI_BUS_NUM(e->devid), |
42a698f4 JR |
883 | PCI_SLOT(e->devid), |
884 | PCI_FUNC(e->devid), | |
885 | e->flags, | |
c5081cd7 | 886 | PCI_BUS_NUM(e->ext >> 8), |
42a698f4 JR |
887 | PCI_SLOT(e->ext >> 8), |
888 | PCI_FUNC(e->ext >> 8)); | |
889 | ||
5d0c8e49 JR |
890 | devid = e->devid; |
891 | devid_to = e->ext >> 8; | |
7a6a3a08 | 892 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 893 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
894 | amd_iommu_alias_table[devid] = devid_to; |
895 | break; | |
896 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
897 | |
898 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
899 | "devid: %02x:%02x.%x flags: %02x " | |
900 | "devid_to: %02x:%02x.%x\n", | |
c5081cd7 | 901 | PCI_BUS_NUM(e->devid), |
42a698f4 JR |
902 | PCI_SLOT(e->devid), |
903 | PCI_FUNC(e->devid), | |
904 | e->flags, | |
c5081cd7 | 905 | PCI_BUS_NUM(e->ext >> 8), |
42a698f4 JR |
906 | PCI_SLOT(e->ext >> 8), |
907 | PCI_FUNC(e->ext >> 8)); | |
908 | ||
5d0c8e49 JR |
909 | devid_start = e->devid; |
910 | flags = e->flags; | |
911 | devid_to = e->ext >> 8; | |
912 | ext_flags = 0; | |
58a3bee5 | 913 | alias = true; |
5d0c8e49 JR |
914 | break; |
915 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
916 | |
917 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
918 | "flags: %02x ext: %08x\n", | |
c5081cd7 | 919 | PCI_BUS_NUM(e->devid), |
42a698f4 JR |
920 | PCI_SLOT(e->devid), |
921 | PCI_FUNC(e->devid), | |
922 | e->flags, e->ext); | |
923 | ||
5d0c8e49 | 924 | devid = e->devid; |
5ff4789d JR |
925 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
926 | e->ext); | |
5d0c8e49 JR |
927 | break; |
928 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
929 | |
930 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
931 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
c5081cd7 | 932 | PCI_BUS_NUM(e->devid), |
42a698f4 JR |
933 | PCI_SLOT(e->devid), |
934 | PCI_FUNC(e->devid), | |
935 | e->flags, e->ext); | |
936 | ||
5d0c8e49 JR |
937 | devid_start = e->devid; |
938 | flags = e->flags; | |
939 | ext_flags = e->ext; | |
58a3bee5 | 940 | alias = false; |
5d0c8e49 JR |
941 | break; |
942 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
943 | |
944 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
c5081cd7 | 945 | PCI_BUS_NUM(e->devid), |
42a698f4 JR |
946 | PCI_SLOT(e->devid), |
947 | PCI_FUNC(e->devid)); | |
948 | ||
5d0c8e49 JR |
949 | devid = e->devid; |
950 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 951 | if (alias) { |
5d0c8e49 | 952 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
953 | set_dev_entry_from_acpi(iommu, |
954 | devid_to, flags, ext_flags); | |
955 | } | |
956 | set_dev_entry_from_acpi(iommu, dev_i, | |
957 | flags, ext_flags); | |
5d0c8e49 JR |
958 | } |
959 | break; | |
6efed63b JR |
960 | case IVHD_DEV_SPECIAL: { |
961 | u8 handle, type; | |
962 | const char *var; | |
963 | u16 devid; | |
964 | int ret; | |
965 | ||
966 | handle = e->ext & 0xff; | |
967 | devid = (e->ext >> 8) & 0xffff; | |
968 | type = (e->ext >> 24) & 0xff; | |
969 | ||
970 | if (type == IVHD_SPECIAL_IOAPIC) | |
971 | var = "IOAPIC"; | |
972 | else if (type == IVHD_SPECIAL_HPET) | |
973 | var = "HPET"; | |
974 | else | |
975 | var = "UNKNOWN"; | |
976 | ||
977 | DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", | |
978 | var, (int)handle, | |
c5081cd7 | 979 | PCI_BUS_NUM(devid), |
6efed63b JR |
980 | PCI_SLOT(devid), |
981 | PCI_FUNC(devid)); | |
982 | ||
c50e3247 | 983 | ret = add_special_device(type, handle, &devid, false); |
6efed63b JR |
984 | if (ret) |
985 | return ret; | |
c50e3247 JR |
986 | |
987 | /* | |
988 | * add_special_device might update the devid in case a | |
989 | * command-line override is present. So call | |
990 | * set_dev_entry_from_acpi after add_special_device. | |
991 | */ | |
992 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); | |
993 | ||
6efed63b JR |
994 | break; |
995 | } | |
5d0c8e49 JR |
996 | default: |
997 | break; | |
998 | } | |
999 | ||
b514e555 | 1000 | p += ivhd_entry_length(p); |
5d0c8e49 | 1001 | } |
6efed63b JR |
1002 | |
1003 | return 0; | |
5d0c8e49 JR |
1004 | } |
1005 | ||
e47d402d JR |
1006 | static void __init free_iommu_one(struct amd_iommu *iommu) |
1007 | { | |
1008 | free_command_buffer(iommu); | |
335503e5 | 1009 | free_event_buffer(iommu); |
1a29ac01 | 1010 | free_ppr_log(iommu); |
e47d402d JR |
1011 | iommu_unmap_mmio_space(iommu); |
1012 | } | |
1013 | ||
1014 | static void __init free_iommu_all(void) | |
1015 | { | |
1016 | struct amd_iommu *iommu, *next; | |
1017 | ||
3bd22172 | 1018 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
1019 | list_del(&iommu->list); |
1020 | free_iommu_one(iommu); | |
1021 | kfree(iommu); | |
1022 | } | |
1023 | } | |
1024 | ||
318fe782 SS |
1025 | /* |
1026 | * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) | |
1027 | * Workaround: | |
1028 | * BIOS should disable L2B micellaneous clock gating by setting | |
1029 | * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b | |
1030 | */ | |
e2f1a3bd | 1031 | static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) |
318fe782 SS |
1032 | { |
1033 | u32 value; | |
1034 | ||
1035 | if ((boot_cpu_data.x86 != 0x15) || | |
1036 | (boot_cpu_data.x86_model < 0x10) || | |
1037 | (boot_cpu_data.x86_model > 0x1f)) | |
1038 | return; | |
1039 | ||
1040 | pci_write_config_dword(iommu->dev, 0xf0, 0x90); | |
1041 | pci_read_config_dword(iommu->dev, 0xf4, &value); | |
1042 | ||
1043 | if (value & BIT(2)) | |
1044 | return; | |
1045 | ||
1046 | /* Select NB indirect register 0x90 and enable writing */ | |
1047 | pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); | |
1048 | ||
1049 | pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); | |
1050 | pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n", | |
1051 | dev_name(&iommu->dev->dev)); | |
1052 | ||
1053 | /* Clear the enable writing bit */ | |
1054 | pci_write_config_dword(iommu->dev, 0xf0, 0x90); | |
1055 | } | |
1056 | ||
358875fd JC |
1057 | /* |
1058 | * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) | |
1059 | * Workaround: | |
1060 | * BIOS should enable ATS write permission check by setting | |
1061 | * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b | |
1062 | */ | |
1063 | static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) | |
1064 | { | |
1065 | u32 value; | |
1066 | ||
1067 | if ((boot_cpu_data.x86 != 0x15) || | |
1068 | (boot_cpu_data.x86_model < 0x30) || | |
1069 | (boot_cpu_data.x86_model > 0x3f)) | |
1070 | return; | |
1071 | ||
1072 | /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ | |
1073 | value = iommu_read_l2(iommu, 0x47); | |
1074 | ||
1075 | if (value & BIT(0)) | |
1076 | return; | |
1077 | ||
1078 | /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ | |
1079 | iommu_write_l2(iommu, 0x47, value | BIT(0)); | |
1080 | ||
1081 | pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n", | |
1082 | dev_name(&iommu->dev->dev)); | |
1083 | } | |
1084 | ||
b65233a9 JR |
1085 | /* |
1086 | * This function clues the initialization function for one IOMMU | |
1087 | * together and also allocates the command buffer and programs the | |
1088 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
1089 | */ | |
e47d402d JR |
1090 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
1091 | { | |
6efed63b JR |
1092 | int ret; |
1093 | ||
e47d402d | 1094 | spin_lock_init(&iommu->lock); |
bb52777e JR |
1095 | |
1096 | /* Add IOMMU to internal data structures */ | |
e47d402d | 1097 | list_add_tail(&iommu->list, &amd_iommu_list); |
bb52777e JR |
1098 | iommu->index = amd_iommus_present++; |
1099 | ||
1100 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | |
1101 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | |
1102 | return -ENOSYS; | |
1103 | } | |
1104 | ||
1105 | /* Index is fine - add IOMMU to the array */ | |
1106 | amd_iommus[iommu->index] = iommu; | |
e47d402d JR |
1107 | |
1108 | /* | |
1109 | * Copy data from ACPI table entry to the iommu struct | |
1110 | */ | |
23c742db | 1111 | iommu->devid = h->devid; |
e47d402d | 1112 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 1113 | iommu->pci_seg = h->pci_seg; |
e47d402d | 1114 | iommu->mmio_phys = h->mmio_phys; |
30861ddc | 1115 | |
7d7d38af SS |
1116 | switch (h->type) { |
1117 | case 0x10: | |
1118 | /* Check if IVHD EFR contains proper max banks/counters */ | |
1119 | if ((h->efr_attr != 0) && | |
1120 | ((h->efr_attr & (0xF << 13)) != 0) && | |
1121 | ((h->efr_attr & (0x3F << 17)) != 0)) | |
1122 | iommu->mmio_phys_end = MMIO_REG_END_OFFSET; | |
1123 | else | |
1124 | iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; | |
1125 | break; | |
1126 | case 0x11: | |
1127 | case 0x40: | |
1128 | if (h->efr_reg & (1 << 9)) | |
1129 | iommu->mmio_phys_end = MMIO_REG_END_OFFSET; | |
1130 | else | |
1131 | iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; | |
1132 | break; | |
1133 | default: | |
1134 | return -EINVAL; | |
30861ddc SK |
1135 | } |
1136 | ||
1137 | iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, | |
1138 | iommu->mmio_phys_end); | |
e47d402d JR |
1139 | if (!iommu->mmio_base) |
1140 | return -ENOMEM; | |
1141 | ||
f2c2db53 | 1142 | if (alloc_command_buffer(iommu)) |
e47d402d JR |
1143 | return -ENOMEM; |
1144 | ||
f2c2db53 | 1145 | if (alloc_event_buffer(iommu)) |
335503e5 JR |
1146 | return -ENOMEM; |
1147 | ||
a80dc3e0 JR |
1148 | iommu->int_enabled = false; |
1149 | ||
6efed63b JR |
1150 | ret = init_iommu_from_acpi(iommu, h); |
1151 | if (ret) | |
1152 | return ret; | |
f6fec00a | 1153 | |
7c71d306 JL |
1154 | ret = amd_iommu_create_irq_domain(iommu); |
1155 | if (ret) | |
1156 | return ret; | |
1157 | ||
f6fec00a JR |
1158 | /* |
1159 | * Make sure IOMMU is not considered to translate itself. The IVRS | |
1160 | * table tells us so, but this is a lie! | |
1161 | */ | |
1162 | amd_iommu_rlookup_table[iommu->devid] = NULL; | |
1163 | ||
23c742db | 1164 | return 0; |
e47d402d JR |
1165 | } |
1166 | ||
b65233a9 JR |
1167 | /* |
1168 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
1169 | * IOMMU structure and initializes it with init_iommu_one() | |
1170 | */ | |
e47d402d JR |
1171 | static int __init init_iommu_all(struct acpi_table_header *table) |
1172 | { | |
1173 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1174 | struct ivhd_header *h; | |
1175 | struct amd_iommu *iommu; | |
1176 | int ret; | |
1177 | ||
e47d402d JR |
1178 | end += table->length; |
1179 | p += IVRS_HEADER_LENGTH; | |
1180 | ||
1181 | while (p < end) { | |
1182 | h = (struct ivhd_header *)p; | |
1183 | switch (*p) { | |
1184 | case ACPI_IVHD_TYPE: | |
9c72041f | 1185 | |
ae908c22 | 1186 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f | 1187 | "seg: %d flags: %01x info %04x\n", |
c5081cd7 | 1188 | PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid), |
9c72041f JR |
1189 | PCI_FUNC(h->devid), h->cap_ptr, |
1190 | h->pci_seg, h->flags, h->info); | |
1191 | DUMP_printk(" mmio-addr: %016llx\n", | |
1192 | h->mmio_phys); | |
1193 | ||
e47d402d | 1194 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
02f3b3f5 JR |
1195 | if (iommu == NULL) |
1196 | return -ENOMEM; | |
3551a708 | 1197 | |
e47d402d | 1198 | ret = init_iommu_one(iommu, h); |
02f3b3f5 JR |
1199 | if (ret) |
1200 | return ret; | |
e47d402d JR |
1201 | break; |
1202 | default: | |
1203 | break; | |
1204 | } | |
1205 | p += h->length; | |
1206 | ||
1207 | } | |
1208 | WARN_ON(p != end); | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
30861ddc SK |
1213 | |
1214 | static void init_iommu_perf_ctr(struct amd_iommu *iommu) | |
1215 | { | |
1216 | u64 val = 0xabcd, val2 = 0; | |
1217 | ||
1218 | if (!iommu_feature(iommu, FEATURE_PC)) | |
1219 | return; | |
1220 | ||
1221 | amd_iommu_pc_present = true; | |
1222 | ||
1223 | /* Check if the performance counters can be written to */ | |
38e45d02 SS |
1224 | if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) || |
1225 | (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) || | |
30861ddc SK |
1226 | (val != val2)) { |
1227 | pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n"); | |
1228 | amd_iommu_pc_present = false; | |
1229 | return; | |
1230 | } | |
1231 | ||
1232 | pr_info("AMD-Vi: IOMMU performance counters supported\n"); | |
1233 | ||
1234 | val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); | |
1235 | iommu->max_banks = (u8) ((val >> 12) & 0x3f); | |
1236 | iommu->max_counters = (u8) ((val >> 7) & 0xf); | |
1237 | } | |
1238 | ||
066f2e98 AW |
1239 | static ssize_t amd_iommu_show_cap(struct device *dev, |
1240 | struct device_attribute *attr, | |
1241 | char *buf) | |
1242 | { | |
1243 | struct amd_iommu *iommu = dev_get_drvdata(dev); | |
1244 | return sprintf(buf, "%x\n", iommu->cap); | |
1245 | } | |
1246 | static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); | |
1247 | ||
1248 | static ssize_t amd_iommu_show_features(struct device *dev, | |
1249 | struct device_attribute *attr, | |
1250 | char *buf) | |
1251 | { | |
1252 | struct amd_iommu *iommu = dev_get_drvdata(dev); | |
1253 | return sprintf(buf, "%llx\n", iommu->features); | |
1254 | } | |
1255 | static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); | |
1256 | ||
1257 | static struct attribute *amd_iommu_attrs[] = { | |
1258 | &dev_attr_cap.attr, | |
1259 | &dev_attr_features.attr, | |
1260 | NULL, | |
1261 | }; | |
1262 | ||
1263 | static struct attribute_group amd_iommu_group = { | |
1264 | .name = "amd-iommu", | |
1265 | .attrs = amd_iommu_attrs, | |
1266 | }; | |
1267 | ||
1268 | static const struct attribute_group *amd_iommu_groups[] = { | |
1269 | &amd_iommu_group, | |
1270 | NULL, | |
1271 | }; | |
30861ddc | 1272 | |
23c742db JR |
1273 | static int iommu_init_pci(struct amd_iommu *iommu) |
1274 | { | |
1275 | int cap_ptr = iommu->cap_ptr; | |
1276 | u32 range, misc, low, high; | |
1277 | ||
c5081cd7 | 1278 | iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid), |
23c742db JR |
1279 | iommu->devid & 0xff); |
1280 | if (!iommu->dev) | |
1281 | return -ENODEV; | |
1282 | ||
cbbc00be JL |
1283 | /* Prevent binding other PCI device drivers to IOMMU devices */ |
1284 | iommu->dev->match_driver = false; | |
1285 | ||
23c742db JR |
1286 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
1287 | &iommu->cap); | |
1288 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
1289 | &range); | |
1290 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, | |
1291 | &misc); | |
1292 | ||
23c742db JR |
1293 | if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) |
1294 | amd_iommu_iotlb_sup = false; | |
1295 | ||
1296 | /* read extended feature bits */ | |
1297 | low = readl(iommu->mmio_base + MMIO_EXT_FEATURES); | |
1298 | high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4); | |
1299 | ||
1300 | iommu->features = ((u64)high << 32) | low; | |
1301 | ||
1302 | if (iommu_feature(iommu, FEATURE_GT)) { | |
1303 | int glxval; | |
a919a018 SS |
1304 | u32 max_pasid; |
1305 | u64 pasmax; | |
23c742db | 1306 | |
a919a018 SS |
1307 | pasmax = iommu->features & FEATURE_PASID_MASK; |
1308 | pasmax >>= FEATURE_PASID_SHIFT; | |
1309 | max_pasid = (1 << (pasmax + 1)) - 1; | |
23c742db | 1310 | |
a919a018 SS |
1311 | amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid); |
1312 | ||
1313 | BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); | |
23c742db JR |
1314 | |
1315 | glxval = iommu->features & FEATURE_GLXVAL_MASK; | |
1316 | glxval >>= FEATURE_GLXVAL_SHIFT; | |
1317 | ||
1318 | if (amd_iommu_max_glx_val == -1) | |
1319 | amd_iommu_max_glx_val = glxval; | |
1320 | else | |
1321 | amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); | |
1322 | } | |
1323 | ||
1324 | if (iommu_feature(iommu, FEATURE_GT) && | |
1325 | iommu_feature(iommu, FEATURE_PPR)) { | |
1326 | iommu->is_iommu_v2 = true; | |
1327 | amd_iommu_v2_present = true; | |
1328 | } | |
1329 | ||
f2c2db53 JR |
1330 | if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) |
1331 | return -ENOMEM; | |
23c742db JR |
1332 | |
1333 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) | |
1334 | amd_iommu_np_cache = true; | |
1335 | ||
30861ddc SK |
1336 | init_iommu_perf_ctr(iommu); |
1337 | ||
23c742db JR |
1338 | if (is_rd890_iommu(iommu->dev)) { |
1339 | int i, j; | |
1340 | ||
1341 | iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number, | |
1342 | PCI_DEVFN(0, 0)); | |
1343 | ||
1344 | /* | |
1345 | * Some rd890 systems may not be fully reconfigured by the | |
1346 | * BIOS, so it's necessary for us to store this information so | |
1347 | * it can be reprogrammed on resume | |
1348 | */ | |
1349 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1350 | &iommu->stored_addr_lo); | |
1351 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
1352 | &iommu->stored_addr_hi); | |
1353 | ||
1354 | /* Low bit locks writes to configuration space */ | |
1355 | iommu->stored_addr_lo &= ~1; | |
1356 | ||
1357 | for (i = 0; i < 6; i++) | |
1358 | for (j = 0; j < 0x12; j++) | |
1359 | iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); | |
1360 | ||
1361 | for (i = 0; i < 0x83; i++) | |
1362 | iommu->stored_l2[i] = iommu_read_l2(iommu, i); | |
1363 | } | |
1364 | ||
318fe782 | 1365 | amd_iommu_erratum_746_workaround(iommu); |
358875fd | 1366 | amd_iommu_ats_write_check_workaround(iommu); |
318fe782 | 1367 | |
066f2e98 AW |
1368 | iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu, |
1369 | amd_iommu_groups, "ivhd%d", | |
1370 | iommu->index); | |
1371 | ||
23c742db JR |
1372 | return pci_enable_device(iommu->dev); |
1373 | } | |
1374 | ||
4d121c32 JR |
1375 | static void print_iommu_info(void) |
1376 | { | |
1377 | static const char * const feat_str[] = { | |
1378 | "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", | |
1379 | "IA", "GA", "HE", "PC" | |
1380 | }; | |
1381 | struct amd_iommu *iommu; | |
1382 | ||
1383 | for_each_iommu(iommu) { | |
1384 | int i; | |
1385 | ||
1386 | pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n", | |
1387 | dev_name(&iommu->dev->dev), iommu->cap_ptr); | |
1388 | ||
1389 | if (iommu->cap & (1 << IOMMU_CAP_EFR)) { | |
1390 | pr_info("AMD-Vi: Extended features: "); | |
2bd5ed00 | 1391 | for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { |
4d121c32 JR |
1392 | if (iommu_feature(iommu, (1ULL << i))) |
1393 | pr_cont(" %s", feat_str[i]); | |
1394 | } | |
30861ddc | 1395 | pr_cont("\n"); |
500c25ed | 1396 | } |
4d121c32 | 1397 | } |
ebe60bbf JR |
1398 | if (irq_remapping_enabled) |
1399 | pr_info("AMD-Vi: Interrupt remapping enabled\n"); | |
4d121c32 JR |
1400 | } |
1401 | ||
2c0ae172 | 1402 | static int __init amd_iommu_init_pci(void) |
23c742db JR |
1403 | { |
1404 | struct amd_iommu *iommu; | |
1405 | int ret = 0; | |
1406 | ||
1407 | for_each_iommu(iommu) { | |
1408 | ret = iommu_init_pci(iommu); | |
1409 | if (ret) | |
1410 | break; | |
1411 | } | |
1412 | ||
aafd8ba0 JR |
1413 | init_device_table_dma(); |
1414 | ||
1415 | for_each_iommu(iommu) | |
1416 | iommu_flush_all_caches(iommu); | |
1417 | ||
3a18404c | 1418 | ret = amd_iommu_init_api(); |
23c742db | 1419 | |
3a18404c JR |
1420 | if (!ret) |
1421 | print_iommu_info(); | |
4d121c32 | 1422 | |
23c742db JR |
1423 | return ret; |
1424 | } | |
1425 | ||
a80dc3e0 JR |
1426 | /**************************************************************************** |
1427 | * | |
1428 | * The following functions initialize the MSI interrupts for all IOMMUs | |
df805abb | 1429 | * in the system. It's a bit challenging because there could be multiple |
a80dc3e0 JR |
1430 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per |
1431 | * pci_dev. | |
1432 | * | |
1433 | ****************************************************************************/ | |
1434 | ||
9f800de3 | 1435 | static int iommu_setup_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
1436 | { |
1437 | int r; | |
a80dc3e0 | 1438 | |
9ddd592a JR |
1439 | r = pci_enable_msi(iommu->dev); |
1440 | if (r) | |
1441 | return r; | |
a80dc3e0 | 1442 | |
72fe00f0 JR |
1443 | r = request_threaded_irq(iommu->dev->irq, |
1444 | amd_iommu_int_handler, | |
1445 | amd_iommu_int_thread, | |
1446 | 0, "AMD-Vi", | |
3f398bc7 | 1447 | iommu); |
a80dc3e0 JR |
1448 | |
1449 | if (r) { | |
1450 | pci_disable_msi(iommu->dev); | |
9ddd592a | 1451 | return r; |
a80dc3e0 JR |
1452 | } |
1453 | ||
fab6afa3 | 1454 | iommu->int_enabled = true; |
1a29ac01 | 1455 | |
a80dc3e0 JR |
1456 | return 0; |
1457 | } | |
1458 | ||
05f92db9 | 1459 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 | 1460 | { |
9ddd592a JR |
1461 | int ret; |
1462 | ||
a80dc3e0 | 1463 | if (iommu->int_enabled) |
9ddd592a | 1464 | goto enable_faults; |
a80dc3e0 | 1465 | |
82fcfc67 | 1466 | if (iommu->dev->msi_cap) |
9ddd592a JR |
1467 | ret = iommu_setup_msi(iommu); |
1468 | else | |
1469 | ret = -ENODEV; | |
1470 | ||
1471 | if (ret) | |
1472 | return ret; | |
a80dc3e0 | 1473 | |
9ddd592a JR |
1474 | enable_faults: |
1475 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); | |
a80dc3e0 | 1476 | |
9ddd592a JR |
1477 | if (iommu->ppr_log != NULL) |
1478 | iommu_feature_enable(iommu, CONTROL_PPFINT_EN); | |
1479 | ||
1480 | return 0; | |
a80dc3e0 JR |
1481 | } |
1482 | ||
b65233a9 JR |
1483 | /**************************************************************************** |
1484 | * | |
1485 | * The next functions belong to the third pass of parsing the ACPI | |
1486 | * table. In this last pass the memory mapping requirements are | |
df805abb | 1487 | * gathered (like exclusion and unity mapping ranges). |
b65233a9 JR |
1488 | * |
1489 | ****************************************************************************/ | |
1490 | ||
be2a022c JR |
1491 | static void __init free_unity_maps(void) |
1492 | { | |
1493 | struct unity_map_entry *entry, *next; | |
1494 | ||
1495 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
1496 | list_del(&entry->list); | |
1497 | kfree(entry); | |
1498 | } | |
1499 | } | |
1500 | ||
b65233a9 | 1501 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
1502 | static int __init init_exclusion_range(struct ivmd_header *m) |
1503 | { | |
1504 | int i; | |
1505 | ||
1506 | switch (m->type) { | |
1507 | case ACPI_IVMD_TYPE: | |
1508 | set_device_exclusion_range(m->devid, m); | |
1509 | break; | |
1510 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 1511 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
1512 | set_device_exclusion_range(i, m); |
1513 | break; | |
1514 | case ACPI_IVMD_TYPE_RANGE: | |
1515 | for (i = m->devid; i <= m->aux; ++i) | |
1516 | set_device_exclusion_range(i, m); | |
1517 | break; | |
1518 | default: | |
1519 | break; | |
1520 | } | |
1521 | ||
1522 | return 0; | |
1523 | } | |
1524 | ||
b65233a9 | 1525 | /* called for unity map ACPI definition */ |
be2a022c JR |
1526 | static int __init init_unity_map_range(struct ivmd_header *m) |
1527 | { | |
98f1ad25 | 1528 | struct unity_map_entry *e = NULL; |
02acc43a | 1529 | char *s; |
be2a022c JR |
1530 | |
1531 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1532 | if (e == NULL) | |
1533 | return -ENOMEM; | |
1534 | ||
1535 | switch (m->type) { | |
1536 | default: | |
0bc252f4 JR |
1537 | kfree(e); |
1538 | return 0; | |
be2a022c | 1539 | case ACPI_IVMD_TYPE: |
02acc43a | 1540 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1541 | e->devid_start = e->devid_end = m->devid; |
1542 | break; | |
1543 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1544 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1545 | e->devid_start = 0; |
1546 | e->devid_end = amd_iommu_last_bdf; | |
1547 | break; | |
1548 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1549 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1550 | e->devid_start = m->devid; |
1551 | e->devid_end = m->aux; | |
1552 | break; | |
1553 | } | |
1554 | e->address_start = PAGE_ALIGN(m->range_start); | |
1555 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1556 | e->prot = m->flags >> 1; | |
1557 | ||
02acc43a JR |
1558 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1559 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
c5081cd7 SK |
1560 | PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), |
1561 | PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end), | |
02acc43a JR |
1562 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), |
1563 | e->address_start, e->address_end, m->flags); | |
1564 | ||
be2a022c JR |
1565 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1566 | ||
1567 | return 0; | |
1568 | } | |
1569 | ||
b65233a9 | 1570 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1571 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1572 | { | |
1573 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1574 | struct ivmd_header *m; | |
1575 | ||
be2a022c JR |
1576 | end += table->length; |
1577 | p += IVRS_HEADER_LENGTH; | |
1578 | ||
1579 | while (p < end) { | |
1580 | m = (struct ivmd_header *)p; | |
1581 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1582 | init_exclusion_range(m); | |
1583 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1584 | init_unity_map_range(m); | |
1585 | ||
1586 | p += m->length; | |
1587 | } | |
1588 | ||
1589 | return 0; | |
1590 | } | |
1591 | ||
9f5f5fb3 JR |
1592 | /* |
1593 | * Init the device table to not allow DMA access for devices and | |
1594 | * suppress all page faults | |
1595 | */ | |
33f28c59 | 1596 | static void init_device_table_dma(void) |
9f5f5fb3 | 1597 | { |
0de66d5b | 1598 | u32 devid; |
9f5f5fb3 JR |
1599 | |
1600 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1601 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1602 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1603 | } |
1604 | } | |
1605 | ||
d04e0ba3 JR |
1606 | static void __init uninit_device_table_dma(void) |
1607 | { | |
1608 | u32 devid; | |
1609 | ||
1610 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1611 | amd_iommu_dev_table[devid].data[0] = 0ULL; | |
1612 | amd_iommu_dev_table[devid].data[1] = 0ULL; | |
1613 | } | |
1614 | } | |
1615 | ||
33f28c59 JR |
1616 | static void init_device_table(void) |
1617 | { | |
1618 | u32 devid; | |
1619 | ||
1620 | if (!amd_iommu_irq_remap) | |
1621 | return; | |
1622 | ||
1623 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1624 | set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN); | |
1625 | } | |
1626 | ||
e9bf5197 JR |
1627 | static void iommu_init_flags(struct amd_iommu *iommu) |
1628 | { | |
1629 | iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? | |
1630 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
1631 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
1632 | ||
1633 | iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? | |
1634 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
1635 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
1636 | ||
1637 | iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? | |
1638 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
1639 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
1640 | ||
1641 | iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? | |
1642 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
1643 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
1644 | ||
1645 | /* | |
1646 | * make IOMMU memory accesses cache coherent | |
1647 | */ | |
1648 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
1456e9d2 JR |
1649 | |
1650 | /* Set IOTLB invalidation timeout to 1s */ | |
1651 | iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); | |
e9bf5197 JR |
1652 | } |
1653 | ||
5bcd757f | 1654 | static void iommu_apply_resume_quirks(struct amd_iommu *iommu) |
4c894f47 | 1655 | { |
5bcd757f MG |
1656 | int i, j; |
1657 | u32 ioc_feature_control; | |
c1bf94ec | 1658 | struct pci_dev *pdev = iommu->root_pdev; |
5bcd757f MG |
1659 | |
1660 | /* RD890 BIOSes may not have completely reconfigured the iommu */ | |
c1bf94ec | 1661 | if (!is_rd890_iommu(iommu->dev) || !pdev) |
5bcd757f MG |
1662 | return; |
1663 | ||
1664 | /* | |
1665 | * First, we need to ensure that the iommu is enabled. This is | |
1666 | * controlled by a register in the northbridge | |
1667 | */ | |
5bcd757f MG |
1668 | |
1669 | /* Select Northbridge indirect register 0x75 and enable writing */ | |
1670 | pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); | |
1671 | pci_read_config_dword(pdev, 0x64, &ioc_feature_control); | |
1672 | ||
1673 | /* Enable the iommu */ | |
1674 | if (!(ioc_feature_control & 0x1)) | |
1675 | pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); | |
1676 | ||
5bcd757f MG |
1677 | /* Restore the iommu BAR */ |
1678 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1679 | iommu->stored_addr_lo); | |
1680 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
1681 | iommu->stored_addr_hi); | |
1682 | ||
1683 | /* Restore the l1 indirect regs for each of the 6 l1s */ | |
1684 | for (i = 0; i < 6; i++) | |
1685 | for (j = 0; j < 0x12; j++) | |
1686 | iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); | |
1687 | ||
1688 | /* Restore the l2 indirect regs */ | |
1689 | for (i = 0; i < 0x83; i++) | |
1690 | iommu_write_l2(iommu, i, iommu->stored_l2[i]); | |
1691 | ||
1692 | /* Lock PCI setup registers */ | |
1693 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1694 | iommu->stored_addr_lo | 1); | |
4c894f47 JR |
1695 | } |
1696 | ||
b65233a9 JR |
1697 | /* |
1698 | * This function finally enables all IOMMUs found in the system after | |
1699 | * they have been initialized | |
1700 | */ | |
11ee5ac4 | 1701 | static void early_enable_iommus(void) |
8736197b JR |
1702 | { |
1703 | struct amd_iommu *iommu; | |
1704 | ||
3bd22172 | 1705 | for_each_iommu(iommu) { |
a8c485bb | 1706 | iommu_disable(iommu); |
e9bf5197 | 1707 | iommu_init_flags(iommu); |
58492e12 JR |
1708 | iommu_set_device_table(iommu); |
1709 | iommu_enable_command_buffer(iommu); | |
1710 | iommu_enable_event_buffer(iommu); | |
8736197b JR |
1711 | iommu_set_exclusion_range(iommu); |
1712 | iommu_enable(iommu); | |
7d0c5cc5 | 1713 | iommu_flush_all_caches(iommu); |
8736197b JR |
1714 | } |
1715 | } | |
1716 | ||
11ee5ac4 JR |
1717 | static void enable_iommus_v2(void) |
1718 | { | |
1719 | struct amd_iommu *iommu; | |
1720 | ||
1721 | for_each_iommu(iommu) { | |
1722 | iommu_enable_ppr_log(iommu); | |
1723 | iommu_enable_gt(iommu); | |
1724 | } | |
1725 | } | |
1726 | ||
1727 | static void enable_iommus(void) | |
1728 | { | |
1729 | early_enable_iommus(); | |
1730 | ||
1731 | enable_iommus_v2(); | |
1732 | } | |
1733 | ||
92ac4320 JR |
1734 | static void disable_iommus(void) |
1735 | { | |
1736 | struct amd_iommu *iommu; | |
1737 | ||
1738 | for_each_iommu(iommu) | |
1739 | iommu_disable(iommu); | |
1740 | } | |
1741 | ||
7441e9cb JR |
1742 | /* |
1743 | * Suspend/Resume support | |
1744 | * disable suspend until real resume implemented | |
1745 | */ | |
1746 | ||
f3c6ea1b | 1747 | static void amd_iommu_resume(void) |
7441e9cb | 1748 | { |
5bcd757f MG |
1749 | struct amd_iommu *iommu; |
1750 | ||
1751 | for_each_iommu(iommu) | |
1752 | iommu_apply_resume_quirks(iommu); | |
1753 | ||
736501ee JR |
1754 | /* re-load the hardware */ |
1755 | enable_iommus(); | |
3d9761e7 JR |
1756 | |
1757 | amd_iommu_enable_interrupts(); | |
7441e9cb JR |
1758 | } |
1759 | ||
f3c6ea1b | 1760 | static int amd_iommu_suspend(void) |
7441e9cb | 1761 | { |
736501ee JR |
1762 | /* disable IOMMUs to go out of the way for BIOS */ |
1763 | disable_iommus(); | |
1764 | ||
1765 | return 0; | |
7441e9cb JR |
1766 | } |
1767 | ||
f3c6ea1b | 1768 | static struct syscore_ops amd_iommu_syscore_ops = { |
7441e9cb JR |
1769 | .suspend = amd_iommu_suspend, |
1770 | .resume = amd_iommu_resume, | |
1771 | }; | |
1772 | ||
8704a1ba JR |
1773 | static void __init free_on_init_error(void) |
1774 | { | |
0ea2c422 JR |
1775 | free_pages((unsigned long)irq_lookup_table, |
1776 | get_order(rlookup_table_size)); | |
8704a1ba | 1777 | |
a591989a JL |
1778 | kmem_cache_destroy(amd_iommu_irq_cache); |
1779 | amd_iommu_irq_cache = NULL; | |
8704a1ba JR |
1780 | |
1781 | free_pages((unsigned long)amd_iommu_rlookup_table, | |
1782 | get_order(rlookup_table_size)); | |
1783 | ||
1784 | free_pages((unsigned long)amd_iommu_alias_table, | |
1785 | get_order(alias_table_size)); | |
1786 | ||
1787 | free_pages((unsigned long)amd_iommu_dev_table, | |
1788 | get_order(dev_table_size)); | |
1789 | ||
1790 | free_iommu_all(); | |
1791 | ||
8704a1ba JR |
1792 | #ifdef CONFIG_GART_IOMMU |
1793 | /* | |
1794 | * We failed to initialize the AMD IOMMU - try fallback to GART | |
1795 | * if possible. | |
1796 | */ | |
1797 | gart_iommu_init(); | |
1798 | ||
1799 | #endif | |
1800 | } | |
1801 | ||
c2ff5cf5 JR |
1802 | /* SB IOAPIC is always on this device in AMD systems */ |
1803 | #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) | |
1804 | ||
eb1eb7ae JR |
1805 | static bool __init check_ioapic_information(void) |
1806 | { | |
dfbb6d47 | 1807 | const char *fw_bug = FW_BUG; |
c2ff5cf5 | 1808 | bool ret, has_sb_ioapic; |
eb1eb7ae JR |
1809 | int idx; |
1810 | ||
c2ff5cf5 JR |
1811 | has_sb_ioapic = false; |
1812 | ret = false; | |
eb1eb7ae | 1813 | |
dfbb6d47 JR |
1814 | /* |
1815 | * If we have map overrides on the kernel command line the | |
1816 | * messages in this function might not describe firmware bugs | |
1817 | * anymore - so be careful | |
1818 | */ | |
1819 | if (cmdline_maps) | |
1820 | fw_bug = ""; | |
1821 | ||
c2ff5cf5 JR |
1822 | for (idx = 0; idx < nr_ioapics; idx++) { |
1823 | int devid, id = mpc_ioapic_id(idx); | |
1824 | ||
1825 | devid = get_ioapic_devid(id); | |
1826 | if (devid < 0) { | |
dfbb6d47 JR |
1827 | pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n", |
1828 | fw_bug, id); | |
c2ff5cf5 JR |
1829 | ret = false; |
1830 | } else if (devid == IOAPIC_SB_DEVID) { | |
1831 | has_sb_ioapic = true; | |
1832 | ret = true; | |
eb1eb7ae JR |
1833 | } |
1834 | } | |
1835 | ||
c2ff5cf5 JR |
1836 | if (!has_sb_ioapic) { |
1837 | /* | |
1838 | * We expect the SB IOAPIC to be listed in the IVRS | |
1839 | * table. The system timer is connected to the SB IOAPIC | |
1840 | * and if we don't have it in the list the system will | |
1841 | * panic at boot time. This situation usually happens | |
1842 | * when the BIOS is buggy and provides us the wrong | |
1843 | * device id for the IOAPIC in the system. | |
1844 | */ | |
dfbb6d47 | 1845 | pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug); |
c2ff5cf5 JR |
1846 | } |
1847 | ||
1848 | if (!ret) | |
dfbb6d47 | 1849 | pr_err("AMD-Vi: Disabling interrupt remapping\n"); |
c2ff5cf5 JR |
1850 | |
1851 | return ret; | |
eb1eb7ae JR |
1852 | } |
1853 | ||
d04e0ba3 JR |
1854 | static void __init free_dma_resources(void) |
1855 | { | |
d04e0ba3 JR |
1856 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1857 | get_order(MAX_DOMAIN_ID/8)); | |
1858 | ||
1859 | free_unity_maps(); | |
1860 | } | |
1861 | ||
b65233a9 | 1862 | /* |
8704a1ba JR |
1863 | * This is the hardware init function for AMD IOMMU in the system. |
1864 | * This function is called either from amd_iommu_init or from the interrupt | |
1865 | * remapping setup code. | |
b65233a9 JR |
1866 | * |
1867 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1868 | * three times: | |
1869 | * | |
1870 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1871 | * Upon this information the size of the data structures is | |
1872 | * determined that needs to be allocated. | |
1873 | * | |
1874 | * 2 pass) Initialize the data structures just allocated with the | |
1875 | * information in the ACPI table about available AMD IOMMUs | |
1876 | * in the system. It also maps the PCI devices in the | |
1877 | * system to specific IOMMUs | |
1878 | * | |
1879 | * 3 pass) After the basic data structures are allocated and | |
1880 | * initialized we update them with information about memory | |
1881 | * remapping requirements parsed out of the ACPI table in | |
1882 | * this last pass. | |
1883 | * | |
8704a1ba JR |
1884 | * After everything is set up the IOMMUs are enabled and the necessary |
1885 | * hotplug and suspend notifiers are registered. | |
b65233a9 | 1886 | */ |
643511b3 | 1887 | static int __init early_amd_iommu_init(void) |
fe74c9cf | 1888 | { |
02f3b3f5 JR |
1889 | struct acpi_table_header *ivrs_base; |
1890 | acpi_size ivrs_size; | |
1891 | acpi_status status; | |
fe74c9cf JR |
1892 | int i, ret = 0; |
1893 | ||
643511b3 | 1894 | if (!amd_iommu_detected) |
8704a1ba JR |
1895 | return -ENODEV; |
1896 | ||
02f3b3f5 JR |
1897 | status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size); |
1898 | if (status == AE_NOT_FOUND) | |
1899 | return -ENODEV; | |
1900 | else if (ACPI_FAILURE(status)) { | |
1901 | const char *err = acpi_format_exception(status); | |
1902 | pr_err("AMD-Vi: IVRS table error: %s\n", err); | |
1903 | return -EINVAL; | |
1904 | } | |
1905 | ||
fe74c9cf JR |
1906 | /* |
1907 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1908 | * we need to handle. Upon this information the shared data | |
1909 | * structures for the IOMMUs in the system will be allocated | |
1910 | */ | |
2c0ae172 JR |
1911 | ret = find_last_devid_acpi(ivrs_base); |
1912 | if (ret) | |
3551a708 JR |
1913 | goto out; |
1914 | ||
c571484e JR |
1915 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1916 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1917 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf | 1918 | |
fe74c9cf | 1919 | /* Device table - directly used by all IOMMUs */ |
8704a1ba | 1920 | ret = -ENOMEM; |
5dc8bff0 | 1921 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1922 | get_order(dev_table_size)); |
1923 | if (amd_iommu_dev_table == NULL) | |
1924 | goto out; | |
1925 | ||
1926 | /* | |
1927 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1928 | * IOMMU see for that device | |
1929 | */ | |
1930 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1931 | get_order(alias_table_size)); | |
1932 | if (amd_iommu_alias_table == NULL) | |
2c0ae172 | 1933 | goto out; |
fe74c9cf JR |
1934 | |
1935 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1936 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1937 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1938 | get_order(rlookup_table_size)); |
1939 | if (amd_iommu_rlookup_table == NULL) | |
2c0ae172 | 1940 | goto out; |
fe74c9cf | 1941 | |
5dc8bff0 JR |
1942 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1943 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1944 | get_order(MAX_DOMAIN_ID/8)); |
1945 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
2c0ae172 | 1946 | goto out; |
fe74c9cf JR |
1947 | |
1948 | /* | |
5dc8bff0 | 1949 | * let all alias entries point to itself |
fe74c9cf | 1950 | */ |
3a61ec38 | 1951 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1952 | amd_iommu_alias_table[i] = i; |
1953 | ||
fe74c9cf JR |
1954 | /* |
1955 | * never allocate domain 0 because its used as the non-allocated and | |
1956 | * error value placeholder | |
1957 | */ | |
1958 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1959 | ||
aeb26f55 JR |
1960 | spin_lock_init(&amd_iommu_pd_lock); |
1961 | ||
fe74c9cf JR |
1962 | /* |
1963 | * now the data structures are allocated and basically initialized | |
1964 | * start the real acpi table scan | |
1965 | */ | |
02f3b3f5 JR |
1966 | ret = init_iommu_all(ivrs_base); |
1967 | if (ret) | |
2c0ae172 | 1968 | goto out; |
fe74c9cf | 1969 | |
eb1eb7ae JR |
1970 | if (amd_iommu_irq_remap) |
1971 | amd_iommu_irq_remap = check_ioapic_information(); | |
1972 | ||
05152a04 JR |
1973 | if (amd_iommu_irq_remap) { |
1974 | /* | |
1975 | * Interrupt remapping enabled, create kmem_cache for the | |
1976 | * remapping tables. | |
1977 | */ | |
83ed9c13 | 1978 | ret = -ENOMEM; |
05152a04 JR |
1979 | amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", |
1980 | MAX_IRQS_PER_TABLE * sizeof(u32), | |
1981 | IRQ_TABLE_ALIGNMENT, | |
1982 | 0, NULL); | |
1983 | if (!amd_iommu_irq_cache) | |
1984 | goto out; | |
0ea2c422 JR |
1985 | |
1986 | irq_lookup_table = (void *)__get_free_pages( | |
1987 | GFP_KERNEL | __GFP_ZERO, | |
1988 | get_order(rlookup_table_size)); | |
1989 | if (!irq_lookup_table) | |
1990 | goto out; | |
05152a04 JR |
1991 | } |
1992 | ||
02f3b3f5 JR |
1993 | ret = init_memory_definitions(ivrs_base); |
1994 | if (ret) | |
2c0ae172 | 1995 | goto out; |
3551a708 | 1996 | |
eb1eb7ae JR |
1997 | /* init the device table */ |
1998 | init_device_table(); | |
1999 | ||
8704a1ba | 2000 | out: |
02f3b3f5 JR |
2001 | /* Don't leak any ACPI memory */ |
2002 | early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size); | |
2003 | ivrs_base = NULL; | |
2004 | ||
643511b3 JR |
2005 | return ret; |
2006 | } | |
2007 | ||
ae295142 | 2008 | static int amd_iommu_enable_interrupts(void) |
3d9761e7 JR |
2009 | { |
2010 | struct amd_iommu *iommu; | |
2011 | int ret = 0; | |
2012 | ||
2013 | for_each_iommu(iommu) { | |
2014 | ret = iommu_init_msi(iommu); | |
2015 | if (ret) | |
2016 | goto out; | |
2017 | } | |
2018 | ||
2019 | out: | |
2020 | return ret; | |
2021 | } | |
2022 | ||
02f3b3f5 JR |
2023 | static bool detect_ivrs(void) |
2024 | { | |
2025 | struct acpi_table_header *ivrs_base; | |
2026 | acpi_size ivrs_size; | |
2027 | acpi_status status; | |
2028 | ||
2029 | status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size); | |
2030 | if (status == AE_NOT_FOUND) | |
2031 | return false; | |
2032 | else if (ACPI_FAILURE(status)) { | |
2033 | const char *err = acpi_format_exception(status); | |
2034 | pr_err("AMD-Vi: IVRS table error: %s\n", err); | |
2035 | return false; | |
2036 | } | |
2037 | ||
2038 | early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size); | |
2039 | ||
1adb7d31 JR |
2040 | /* Make sure ACS will be enabled during PCI probe */ |
2041 | pci_request_acs(); | |
2042 | ||
02f3b3f5 JR |
2043 | return true; |
2044 | } | |
2045 | ||
2c0ae172 | 2046 | /**************************************************************************** |
8704a1ba | 2047 | * |
2c0ae172 JR |
2048 | * AMD IOMMU Initialization State Machine |
2049 | * | |
2050 | ****************************************************************************/ | |
2051 | ||
2052 | static int __init state_next(void) | |
8704a1ba JR |
2053 | { |
2054 | int ret = 0; | |
2055 | ||
2c0ae172 JR |
2056 | switch (init_state) { |
2057 | case IOMMU_START_STATE: | |
2058 | if (!detect_ivrs()) { | |
2059 | init_state = IOMMU_NOT_FOUND; | |
2060 | ret = -ENODEV; | |
2061 | } else { | |
2062 | init_state = IOMMU_IVRS_DETECTED; | |
2063 | } | |
2064 | break; | |
2065 | case IOMMU_IVRS_DETECTED: | |
2066 | ret = early_amd_iommu_init(); | |
2067 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; | |
2068 | break; | |
2069 | case IOMMU_ACPI_FINISHED: | |
2070 | early_enable_iommus(); | |
2071 | register_syscore_ops(&amd_iommu_syscore_ops); | |
2072 | x86_platform.iommu_shutdown = disable_iommus; | |
2073 | init_state = IOMMU_ENABLED; | |
2074 | break; | |
2075 | case IOMMU_ENABLED: | |
2076 | ret = amd_iommu_init_pci(); | |
2077 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; | |
2078 | enable_iommus_v2(); | |
2079 | break; | |
2080 | case IOMMU_PCI_INIT: | |
2081 | ret = amd_iommu_enable_interrupts(); | |
2082 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; | |
2083 | break; | |
2084 | case IOMMU_INTERRUPTS_EN: | |
1e6a7b04 | 2085 | ret = amd_iommu_init_dma_ops(); |
2c0ae172 JR |
2086 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS; |
2087 | break; | |
2088 | case IOMMU_DMA_OPS: | |
2089 | init_state = IOMMU_INITIALIZED; | |
2090 | break; | |
2091 | case IOMMU_INITIALIZED: | |
2092 | /* Nothing to do */ | |
2093 | break; | |
2094 | case IOMMU_NOT_FOUND: | |
2095 | case IOMMU_INIT_ERROR: | |
2096 | /* Error states => do nothing */ | |
2097 | ret = -EINVAL; | |
2098 | break; | |
2099 | default: | |
2100 | /* Unknown state */ | |
2101 | BUG(); | |
2102 | } | |
3d9761e7 | 2103 | |
2c0ae172 JR |
2104 | return ret; |
2105 | } | |
7441e9cb | 2106 | |
2c0ae172 JR |
2107 | static int __init iommu_go_to_state(enum iommu_init_state state) |
2108 | { | |
2109 | int ret = 0; | |
f5325094 | 2110 | |
2c0ae172 JR |
2111 | while (init_state != state) { |
2112 | ret = state_next(); | |
2113 | if (init_state == IOMMU_NOT_FOUND || | |
2114 | init_state == IOMMU_INIT_ERROR) | |
2115 | break; | |
2116 | } | |
f2f12b6f | 2117 | |
fe74c9cf | 2118 | return ret; |
2c0ae172 | 2119 | } |
fe74c9cf | 2120 | |
6b474b82 JR |
2121 | #ifdef CONFIG_IRQ_REMAP |
2122 | int __init amd_iommu_prepare(void) | |
2123 | { | |
3f4cb7c0 TG |
2124 | int ret; |
2125 | ||
7fa1c842 | 2126 | amd_iommu_irq_remap = true; |
84d07793 | 2127 | |
3f4cb7c0 TG |
2128 | ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); |
2129 | if (ret) | |
2130 | return ret; | |
2131 | return amd_iommu_irq_remap ? 0 : -ENODEV; | |
6b474b82 | 2132 | } |
d7f07769 | 2133 | |
6b474b82 JR |
2134 | int __init amd_iommu_enable(void) |
2135 | { | |
2136 | int ret; | |
2137 | ||
2138 | ret = iommu_go_to_state(IOMMU_ENABLED); | |
2139 | if (ret) | |
2140 | return ret; | |
d7f07769 | 2141 | |
6b474b82 | 2142 | irq_remapping_enabled = 1; |
d7f07769 | 2143 | |
6b474b82 JR |
2144 | return 0; |
2145 | } | |
2146 | ||
2147 | void amd_iommu_disable(void) | |
2148 | { | |
2149 | amd_iommu_suspend(); | |
2150 | } | |
2151 | ||
2152 | int amd_iommu_reenable(int mode) | |
2153 | { | |
2154 | amd_iommu_resume(); | |
2155 | ||
2156 | return 0; | |
2157 | } | |
d7f07769 | 2158 | |
6b474b82 JR |
2159 | int __init amd_iommu_enable_faulting(void) |
2160 | { | |
2161 | /* We enable MSI later when PCI is initialized */ | |
2162 | return 0; | |
2163 | } | |
2164 | #endif | |
d7f07769 | 2165 | |
2c0ae172 JR |
2166 | /* |
2167 | * This is the core init function for AMD IOMMU hardware in the system. | |
2168 | * This function is called from the generic x86 DMA layer initialization | |
2169 | * code. | |
2170 | */ | |
2171 | static int __init amd_iommu_init(void) | |
2172 | { | |
2173 | int ret; | |
2174 | ||
2175 | ret = iommu_go_to_state(IOMMU_INITIALIZED); | |
2176 | if (ret) { | |
d04e0ba3 JR |
2177 | free_dma_resources(); |
2178 | if (!irq_remapping_enabled) { | |
2179 | disable_iommus(); | |
2180 | free_on_init_error(); | |
2181 | } else { | |
2182 | struct amd_iommu *iommu; | |
2183 | ||
2184 | uninit_device_table_dma(); | |
2185 | for_each_iommu(iommu) | |
2186 | iommu_flush_all_caches(iommu); | |
2187 | } | |
2c0ae172 JR |
2188 | } |
2189 | ||
2190 | return ret; | |
fe74c9cf JR |
2191 | } |
2192 | ||
b65233a9 JR |
2193 | /**************************************************************************** |
2194 | * | |
2195 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
2196 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
2197 | * IOMMUs | |
2198 | * | |
2199 | ****************************************************************************/ | |
480125ba | 2200 | int __init amd_iommu_detect(void) |
ae7877de | 2201 | { |
2c0ae172 | 2202 | int ret; |
02f3b3f5 | 2203 | |
75f1cdf1 | 2204 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) |
480125ba | 2205 | return -ENODEV; |
ae7877de | 2206 | |
a5235725 | 2207 | if (amd_iommu_disabled) |
480125ba | 2208 | return -ENODEV; |
a5235725 | 2209 | |
2c0ae172 JR |
2210 | ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); |
2211 | if (ret) | |
2212 | return ret; | |
11bd04f6 | 2213 | |
02f3b3f5 JR |
2214 | amd_iommu_detected = true; |
2215 | iommu_detected = 1; | |
2216 | x86_init.iommu.iommu_init = amd_iommu_init; | |
2217 | ||
4781bc42 | 2218 | return 1; |
ae7877de JR |
2219 | } |
2220 | ||
b65233a9 JR |
2221 | /**************************************************************************** |
2222 | * | |
2223 | * Parsing functions for the AMD IOMMU specific kernel command line | |
2224 | * options. | |
2225 | * | |
2226 | ****************************************************************************/ | |
2227 | ||
fefda117 JR |
2228 | static int __init parse_amd_iommu_dump(char *str) |
2229 | { | |
2230 | amd_iommu_dump = true; | |
2231 | ||
2232 | return 1; | |
2233 | } | |
2234 | ||
918ad6c5 JR |
2235 | static int __init parse_amd_iommu_options(char *str) |
2236 | { | |
2237 | for (; *str; ++str) { | |
695b5676 | 2238 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 2239 | amd_iommu_unmap_flush = true; |
a5235725 JR |
2240 | if (strncmp(str, "off", 3) == 0) |
2241 | amd_iommu_disabled = true; | |
5abcdba4 JR |
2242 | if (strncmp(str, "force_isolation", 15) == 0) |
2243 | amd_iommu_force_isolation = true; | |
918ad6c5 JR |
2244 | } |
2245 | ||
2246 | return 1; | |
2247 | } | |
2248 | ||
440e8998 JR |
2249 | static int __init parse_ivrs_ioapic(char *str) |
2250 | { | |
2251 | unsigned int bus, dev, fn; | |
2252 | int ret, id, i; | |
2253 | u16 devid; | |
2254 | ||
2255 | ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); | |
2256 | ||
2257 | if (ret != 4) { | |
2258 | pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str); | |
2259 | return 1; | |
2260 | } | |
2261 | ||
2262 | if (early_ioapic_map_size == EARLY_MAP_SIZE) { | |
2263 | pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", | |
2264 | str); | |
2265 | return 1; | |
2266 | } | |
2267 | ||
2268 | devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); | |
2269 | ||
dfbb6d47 | 2270 | cmdline_maps = true; |
440e8998 JR |
2271 | i = early_ioapic_map_size++; |
2272 | early_ioapic_map[i].id = id; | |
2273 | early_ioapic_map[i].devid = devid; | |
2274 | early_ioapic_map[i].cmd_line = true; | |
2275 | ||
2276 | return 1; | |
2277 | } | |
2278 | ||
2279 | static int __init parse_ivrs_hpet(char *str) | |
2280 | { | |
2281 | unsigned int bus, dev, fn; | |
2282 | int ret, id, i; | |
2283 | u16 devid; | |
2284 | ||
2285 | ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); | |
2286 | ||
2287 | if (ret != 4) { | |
2288 | pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str); | |
2289 | return 1; | |
2290 | } | |
2291 | ||
2292 | if (early_hpet_map_size == EARLY_MAP_SIZE) { | |
2293 | pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n", | |
2294 | str); | |
2295 | return 1; | |
2296 | } | |
2297 | ||
2298 | devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); | |
2299 | ||
dfbb6d47 | 2300 | cmdline_maps = true; |
440e8998 JR |
2301 | i = early_hpet_map_size++; |
2302 | early_hpet_map[i].id = id; | |
2303 | early_hpet_map[i].devid = devid; | |
2304 | early_hpet_map[i].cmd_line = true; | |
2305 | ||
2306 | return 1; | |
2307 | } | |
2308 | ||
2309 | __setup("amd_iommu_dump", parse_amd_iommu_dump); | |
2310 | __setup("amd_iommu=", parse_amd_iommu_options); | |
2311 | __setup("ivrs_ioapic", parse_ivrs_ioapic); | |
2312 | __setup("ivrs_hpet", parse_ivrs_hpet); | |
22e6daf4 KRW |
2313 | |
2314 | IOMMU_INIT_FINISH(amd_iommu_detect, | |
2315 | gart_iommu_hole_init, | |
98f1ad25 JR |
2316 | NULL, |
2317 | NULL); | |
400a28a0 JR |
2318 | |
2319 | bool amd_iommu_v2_supported(void) | |
2320 | { | |
2321 | return amd_iommu_v2_present; | |
2322 | } | |
2323 | EXPORT_SYMBOL(amd_iommu_v2_supported); | |
30861ddc SK |
2324 | |
2325 | /**************************************************************************** | |
2326 | * | |
2327 | * IOMMU EFR Performance Counter support functionality. This code allows | |
2328 | * access to the IOMMU PC functionality. | |
2329 | * | |
2330 | ****************************************************************************/ | |
2331 | ||
2332 | u8 amd_iommu_pc_get_max_banks(u16 devid) | |
2333 | { | |
2334 | struct amd_iommu *iommu; | |
2335 | u8 ret = 0; | |
2336 | ||
2337 | /* locate the iommu governing the devid */ | |
2338 | iommu = amd_iommu_rlookup_table[devid]; | |
2339 | if (iommu) | |
2340 | ret = iommu->max_banks; | |
2341 | ||
2342 | return ret; | |
2343 | } | |
2344 | EXPORT_SYMBOL(amd_iommu_pc_get_max_banks); | |
2345 | ||
2346 | bool amd_iommu_pc_supported(void) | |
2347 | { | |
2348 | return amd_iommu_pc_present; | |
2349 | } | |
2350 | EXPORT_SYMBOL(amd_iommu_pc_supported); | |
2351 | ||
2352 | u8 amd_iommu_pc_get_max_counters(u16 devid) | |
2353 | { | |
2354 | struct amd_iommu *iommu; | |
2355 | u8 ret = 0; | |
2356 | ||
2357 | /* locate the iommu governing the devid */ | |
2358 | iommu = amd_iommu_rlookup_table[devid]; | |
2359 | if (iommu) | |
2360 | ret = iommu->max_counters; | |
2361 | ||
2362 | return ret; | |
2363 | } | |
2364 | EXPORT_SYMBOL(amd_iommu_pc_get_max_counters); | |
2365 | ||
38e45d02 SS |
2366 | static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu, |
2367 | u8 bank, u8 cntr, u8 fxn, | |
30861ddc SK |
2368 | u64 *value, bool is_write) |
2369 | { | |
30861ddc SK |
2370 | u32 offset; |
2371 | u32 max_offset_lim; | |
2372 | ||
30861ddc | 2373 | /* Check for valid iommu and pc register indexing */ |
38e45d02 | 2374 | if (WARN_ON((fxn > 0x28) || (fxn & 7))) |
30861ddc SK |
2375 | return -ENODEV; |
2376 | ||
2377 | offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn); | |
2378 | ||
2379 | /* Limit the offset to the hw defined mmio region aperture */ | |
2380 | max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) | | |
2381 | (iommu->max_counters << 8) | 0x28); | |
2382 | if ((offset < MMIO_CNTR_REG_OFFSET) || | |
2383 | (offset > max_offset_lim)) | |
2384 | return -EINVAL; | |
2385 | ||
2386 | if (is_write) { | |
2387 | writel((u32)*value, iommu->mmio_base + offset); | |
2388 | writel((*value >> 32), iommu->mmio_base + offset + 4); | |
2389 | } else { | |
2390 | *value = readl(iommu->mmio_base + offset + 4); | |
2391 | *value <<= 32; | |
2392 | *value = readl(iommu->mmio_base + offset); | |
2393 | } | |
2394 | ||
2395 | return 0; | |
2396 | } | |
2397 | EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val); | |
38e45d02 SS |
2398 | |
2399 | int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn, | |
2400 | u64 *value, bool is_write) | |
2401 | { | |
2402 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
2403 | ||
2404 | /* Make sure the IOMMU PC resource is available */ | |
2405 | if (!amd_iommu_pc_present || iommu == NULL) | |
2406 | return -ENODEV; | |
2407 | ||
2408 | return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn, | |
2409 | value, is_write); | |
2410 | } |