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Linux 4.5-rc5
[linux-2.6-block.git] / drivers / iommu / amd_iommu_init.c
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f6e2e6b6 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
63ce3ae8 3 * Author: Joerg Roedel <jroedel@suse.de>
f6e2e6b6
JR		 4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
f6e2e6b6 22#include <linux/list.h>
5a0e3ad6 23#include <linux/slab.h>
f3c6ea1b 24#include <linux/syscore_ops.h>
a80dc3e0
JR		 25#include <linux/interrupt.h>
26#include <linux/msi.h>
403f81d8 27#include <linux/amd-iommu.h>
400a28a0 28#include <linux/export.h>
066f2e98 29#include <linux/iommu.h>
f6e2e6b6 30#include <asm/pci-direct.h>
46a7fa27 31#include <asm/iommu.h>
1d9b16d1 32#include <asm/gart.h>
ea1b0d39 33#include <asm/x86_init.h>
22e6daf4 34#include <asm/iommu_table.h>
eb1eb7ae 35#include <asm/io_apic.h>
6b474b82 36#include <asm/irq_remapping.h>
403f81d8
JR		 37
38#include "amd_iommu_proto.h"
39#include "amd_iommu_types.h"
05152a04 40#include "irq_remapping.h"
403f81d8 41
f6e2e6b6
JR		 42/*
43 * definitions for the ACPI scanning code
44 */
f6e2e6b6 45#define IVRS_HEADER_LENGTH 48
f6e2e6b6
JR		 46
47#define ACPI_IVHD_TYPE 0x10
48#define ACPI_IVMD_TYPE_ALL 0x20
49#define ACPI_IVMD_TYPE 0x21
50#define ACPI_IVMD_TYPE_RANGE 0x22
51
52#define IVHD_DEV_ALL 0x01
53#define IVHD_DEV_SELECT 0x02
54#define IVHD_DEV_SELECT_RANGE_START 0x03
55#define IVHD_DEV_RANGE_END 0x04
56#define IVHD_DEV_ALIAS 0x42
57#define IVHD_DEV_ALIAS_RANGE 0x43
58#define IVHD_DEV_EXT_SELECT 0x46
59#define IVHD_DEV_EXT_SELECT_RANGE 0x47
6efed63b
JR		 60#define IVHD_DEV_SPECIAL 0x48
61
62#define IVHD_SPECIAL_IOAPIC 1
63#define IVHD_SPECIAL_HPET 2
f6e2e6b6 64
6da7342f
JR		 65#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
66#define IVHD_FLAG_PASSPW_EN_MASK 0x02
67#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
68#define IVHD_FLAG_ISOC_EN_MASK 0x08
f6e2e6b6
JR		 69
70#define IVMD_FLAG_EXCL_RANGE 0x08
71#define IVMD_FLAG_UNITY_MAP 0x01
72
73#define ACPI_DEVFLAG_INITPASS 0x01
74#define ACPI_DEVFLAG_EXTINT 0x02
75#define ACPI_DEVFLAG_NMI 0x04
76#define ACPI_DEVFLAG_SYSMGT1 0x10
77#define ACPI_DEVFLAG_SYSMGT2 0x20
78#define ACPI_DEVFLAG_LINT0 0x40
79#define ACPI_DEVFLAG_LINT1 0x80
80#define ACPI_DEVFLAG_ATSDIS 0x10000000
81
b65233a9
JR		 82/*
83 * ACPI table definitions
84 *
85 * These data structures are laid over the table to parse the important values
86 * out of it.
87 */
88
89/*
90 * structure describing one IOMMU in the ACPI table. Typically followed by one
91 * or more ivhd_entrys.
92 */
f6e2e6b6
JR		 93struct ivhd_header {
94 u8 type;
95 u8 flags;
96 u16 length;
97 u16 devid;
98 u16 cap_ptr;
99 u64 mmio_phys;
100 u16 pci_seg;
101 u16 info;
30861ddc 102 u32 efr;
f6e2e6b6
JR		 103} __attribute__((packed));
104
b65233a9
JR		 105/*
106 * A device entry describing which devices a specific IOMMU translates and
107 * which requestor ids they use.
108 */
f6e2e6b6
JR		 109struct ivhd_entry {
110 u8 type;
111 u16 devid;
112 u8 flags;
113 u32 ext;
114} __attribute__((packed));
115
b65233a9
JR		 116/*
117 * An AMD IOMMU memory definition structure. It defines things like exclusion
118 * ranges for devices and regions that should be unity mapped.
119 */
f6e2e6b6
JR		 120struct ivmd_header {
121 u8 type;
122 u8 flags;
123 u16 length;
124 u16 devid;
125 u16 aux;
126 u64 resv;
127 u64 range_start;
128 u64 range_length;
129} __attribute__((packed));
130
fefda117 131bool amd_iommu_dump;
05152a04 132bool amd_iommu_irq_remap __read_mostly;
fefda117 133
02f3b3f5 134static bool amd_iommu_detected;
a5235725 135static bool __initdata amd_iommu_disabled;
c1cbebee 136
b65233a9
JR		 137u16 amd_iommu_last_bdf; /* largest PCI device id we have
138 to handle */
2e22847f 139LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
b65233a9 140 we find in ACPI */
621a5f7a 141bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
928abd25 142
2e22847f 143LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
b65233a9 144 system */
928abd25 145
bb52777e
JR		 146/* Array to assign indices to IOMMUs*/
147struct amd_iommu *amd_iommus[MAX_IOMMUS];
148int amd_iommus_present;
149
318afd41
JR		 150/* IOMMUs have a non-present cache? */
151bool amd_iommu_np_cache __read_mostly;
60f723b4 152bool amd_iommu_iotlb_sup __read_mostly = true;
318afd41 153
a919a018 154u32 amd_iommu_max_pasid __read_mostly = ~0;
62f71abb 155
400a28a0 156bool amd_iommu_v2_present __read_mostly;
4160cd9e 157static bool amd_iommu_pc_present __read_mostly;
400a28a0 158
5abcdba4
JR		 159bool amd_iommu_force_isolation __read_mostly;
160
aeb26f55
JR		 161/*
162 * List of protection domains - used during resume
163 */
164LIST_HEAD(amd_iommu_pd_list);
165spinlock_t amd_iommu_pd_lock;
166
b65233a9
JR		 167/*
168 * Pointer to the device table which is shared by all AMD IOMMUs
169 * it is indexed by the PCI device id or the HT unit id and contains
170 * information about the domain the device belongs to as well as the
171 * page table root pointer.
172 */
928abd25 173struct dev_table_entry *amd_iommu_dev_table;
b65233a9
JR		 174
175/*
176 * The alias table is a driver specific data structure which contains the
177 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
178 * More than one device can share the same requestor id.
179 */
928abd25 180u16 *amd_iommu_alias_table;
b65233a9
JR		 181
182/*
183 * The rlookup table is used to find the IOMMU which is responsible
184 * for a specific device. It is also indexed by the PCI device id.
185 */
928abd25 186struct amd_iommu **amd_iommu_rlookup_table;
b65233a9 187
b65233a9 188/*
0ea2c422
JR		 189 * This table is used to find the irq remapping table for a given device id
190 * quickly.
191 */
192struct irq_remap_table **irq_lookup_table;
193
b65233a9 194/*
df805abb 195 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
b65233a9
JR		 196 * to know which ones are already in use.
197 */
928abd25
JR		 198unsigned long *amd_iommu_pd_alloc_bitmap;
199
b65233a9
JR		 200static u32 dev_table_size; /* size of the device table */
201static u32 alias_table_size; /* size of the alias table */
202static u32 rlookup_table_size; /* size if the rlookup table */
3e8064ba 203
2c0ae172
JR		 204enum iommu_init_state {
205 IOMMU_START_STATE,
206 IOMMU_IVRS_DETECTED,
207 IOMMU_ACPI_FINISHED,
208 IOMMU_ENABLED,
209 IOMMU_PCI_INIT,
210 IOMMU_INTERRUPTS_EN,
211 IOMMU_DMA_OPS,
212 IOMMU_INITIALIZED,
213 IOMMU_NOT_FOUND,
214 IOMMU_INIT_ERROR,
215};
216
235dacbc
JR		 217/* Early ioapic and hpet maps from kernel command line */
218#define EARLY_MAP_SIZE 4
219static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
220static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
221static int __initdata early_ioapic_map_size;
222static int __initdata early_hpet_map_size;
dfbb6d47 223static bool __initdata cmdline_maps;
235dacbc 224
2c0ae172
JR		 225static enum iommu_init_state init_state = IOMMU_START_STATE;
226
ae295142 227static int amd_iommu_enable_interrupts(void);
2c0ae172 228static int __init iommu_go_to_state(enum iommu_init_state state);
aafd8ba0 229static void init_device_table_dma(void);
3d9761e7 230
208ec8c9
JR		 231static inline void update_last_devid(u16 devid)
232{
233 if (devid > amd_iommu_last_bdf)
234 amd_iommu_last_bdf = devid;
235}
236
c571484e
JR		 237static inline unsigned long tbl_size(int entry_size)
238{
239 unsigned shift = PAGE_SHIFT +
421f909c 240 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
c571484e
JR		 241
242 return 1UL << shift;
243}
244
5bcd757f
MG		 245/* Access to l1 and l2 indexed register spaces */
246
247static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
248{
249 u32 val;
250
251 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
252 pci_read_config_dword(iommu->dev, 0xfc, &val);
253 return val;
254}
255
256static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
257{
258 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
259 pci_write_config_dword(iommu->dev, 0xfc, val);
260 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
261}
262
263static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
264{
265 u32 val;
266
267 pci_write_config_dword(iommu->dev, 0xf0, address);
268 pci_read_config_dword(iommu->dev, 0xf4, &val);
269 return val;
270}
271
272static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
273{
274 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
275 pci_write_config_dword(iommu->dev, 0xf4, val);
276}
277
b65233a9
JR		 278/****************************************************************************
279 *
280 * AMD IOMMU MMIO register space handling functions
281 *
282 * These functions are used to program the IOMMU device registers in
283 * MMIO space required for that driver.
284 *
285 ****************************************************************************/
3e8064ba 286
b65233a9
JR		 287/*
288 * This function set the exclusion range in the IOMMU. DMA accesses to the
289 * exclusion range are passed through untranslated
290 */
05f92db9 291static void iommu_set_exclusion_range(struct amd_iommu *iommu)
b2026aa2
JR		 292{
293 u64 start = iommu->exclusion_start & PAGE_MASK;
294 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
295 u64 entry;
296
297 if (!iommu->exclusion_start)
298 return;
299
300 entry = start | MMIO_EXCL_ENABLE_MASK;
301 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
302 &entry, sizeof(entry));
303
304 entry = limit;
305 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
306 &entry, sizeof(entry));
307}
308
b65233a9 309/* Programs the physical address of the device table into the IOMMU hardware */
6b7f000e 310static void iommu_set_device_table(struct amd_iommu *iommu)
b2026aa2 311{
f609891f 312 u64 entry;
b2026aa2
JR		 313
314 BUG_ON(iommu->mmio_base == NULL);
315
316 entry = virt_to_phys(amd_iommu_dev_table);
317 entry |= (dev_table_size >> 12) - 1;
318 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
319 &entry, sizeof(entry));
320}
321
b65233a9 322/* Generic functions to enable/disable certain features of the IOMMU. */
05f92db9 323static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 324{
325 u32 ctrl;
326
327 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
328 ctrl |= (1 << bit);
329 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
330}
331
ca020711 332static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 333{
334 u32 ctrl;
335
199d0d50 336 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
b2026aa2
JR		 337 ctrl &= ~(1 << bit);
338 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
339}
340
1456e9d2
JR		 341static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
342{
343 u32 ctrl;
344
345 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
346 ctrl &= ~CTRL_INV_TO_MASK;
347 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
348 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
349}
350
b65233a9 351/* Function to enable the hardware */
05f92db9 352static void iommu_enable(struct amd_iommu *iommu)
b2026aa2 353{
b2026aa2 354 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
b2026aa2
JR		 355}
356
92ac4320 357static void iommu_disable(struct amd_iommu *iommu)
126c52be 358{
a8c485bb
CW		 359 /* Disable command buffer */
360 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
361
362 /* Disable event logging and event interrupts */
363 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
364 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
365
366 /* Disable IOMMU hardware itself */
92ac4320 367 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
126c52be
JR		 368}
369
b65233a9
JR		 370/*
371 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
372 * the system has one.
373 */
30861ddc 374static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
6c56747b 375{
30861ddc
SK		 376 if (!request_mem_region(address, end, "amd_iommu")) {
377 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
378 address, end);
e82752d8 379 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
6c56747b 380 return NULL;
e82752d8 381 }
6c56747b 382
30861ddc 383 return (u8 __iomem *)ioremap_nocache(address, end);
6c56747b
JR		 384}
385
386static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
387{
388 if (iommu->mmio_base)
389 iounmap(iommu->mmio_base);
30861ddc 390 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
6c56747b
JR		 391}
392
b65233a9
JR		 393/****************************************************************************
394 *
395 * The functions below belong to the first pass of AMD IOMMU ACPI table
396 * parsing. In this pass we try to find out the highest device id this
397 * code has to handle. Upon this information the size of the shared data
398 * structures is determined later.
399 *
400 ****************************************************************************/
401
b514e555
JR		 402/*
403 * This function calculates the length of a given IVHD entry
404 */
405static inline int ivhd_entry_length(u8 *ivhd)
406{
407 return 0x04 << (*ivhd >> 6);
408}
409
b65233a9
JR		 410/*
411 * After reading the highest device id from the IOMMU PCI capability header
412 * this function looks if there is a higher device id defined in the ACPI table
413 */
3e8064ba
JR		 414static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
415{
416 u8 *p = (void *)h, *end = (void *)h;
417 struct ivhd_entry *dev;
418
419 p += sizeof(*h);
420 end += h->length;
421
3e8064ba
JR		 422 while (p < end) {
423 dev = (struct ivhd_entry *)p;
424 switch (dev->type) {
d1259416
JR		 425 case IVHD_DEV_ALL:
426 /* Use maximum BDF value for DEV_ALL */
427 update_last_devid(0xffff);
428 break;
3e8064ba
JR		 429 case IVHD_DEV_SELECT:
430 case IVHD_DEV_RANGE_END:
431 case IVHD_DEV_ALIAS:
432 case IVHD_DEV_EXT_SELECT:
b65233a9 433 /* all the above subfield types refer to device ids */
208ec8c9 434 update_last_devid(dev->devid);
3e8064ba
JR		 435 break;
436 default:
437 break;
438 }
b514e555 439 p += ivhd_entry_length(p);
3e8064ba
JR		 440 }
441
442 WARN_ON(p != end);
443
444 return 0;
445}
446
b65233a9
JR		 447/*
448 * Iterate over all IVHD entries in the ACPI table and find the highest device
449 * id which we need to handle. This is the first of three functions which parse
450 * the ACPI table. So we check the checksum here.
451 */
3e8064ba
JR		 452static int __init find_last_devid_acpi(struct acpi_table_header *table)
453{
454 int i;
455 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
456 struct ivhd_header *h;
457
458 /*
459 * Validate checksum here so we don't need to do it when
460 * we actually parse the table
461 */
462 for (i = 0; i < table->length; ++i)
463 checksum += p[i];
02f3b3f5 464 if (checksum != 0)
3e8064ba 465 /* ACPI table corrupt */
02f3b3f5 466 return -ENODEV;
3e8064ba
JR		 467
468 p += IVRS_HEADER_LENGTH;
469
470 end += table->length;
471 while (p < end) {
472 h = (struct ivhd_header *)p;
473 switch (h->type) {
474 case ACPI_IVHD_TYPE:
475 find_last_devid_from_ivhd(h);
476 break;
477 default:
478 break;
479 }
480 p += h->length;
481 }
482 WARN_ON(p != end);
483
484 return 0;
485}
486
b65233a9
JR		 487/****************************************************************************
488 *
df805abb 489 * The following functions belong to the code path which parses the ACPI table
b65233a9
JR		 490 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
491 * data structures, initialize the device/alias/rlookup table and also
492 * basically initialize the hardware.
493 *
494 ****************************************************************************/
495
496/*
497 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
498 * write commands to that buffer later and the IOMMU will execute them
499 * asynchronously
500 */
f2c2db53 501static int __init alloc_command_buffer(struct amd_iommu *iommu)
b36ca91e 502{
f2c2db53
JR		 503 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
504 get_order(CMD_BUFFER_SIZE));
b36ca91e 505
f2c2db53 506 return iommu->cmd_buf ? 0 : -ENOMEM;
58492e12
JR		 507}
508
93f1cc67
JR		 509/*
510 * This function resets the command buffer if the IOMMU stopped fetching
511 * commands from it.
512 */
513void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
514{
515 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
516
517 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
518 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
519
520 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
521}
522
58492e12
JR		 523/*
524 * This function writes the command buffer address to the hardware and
525 * enables it.
526 */
527static void iommu_enable_command_buffer(struct amd_iommu *iommu)
528{
529 u64 entry;
530
531 BUG_ON(iommu->cmd_buf == NULL);
532
533 entry = (u64)virt_to_phys(iommu->cmd_buf);
b36ca91e 534 entry |= MMIO_CMD_SIZE_512;
58492e12 535
b36ca91e 536 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
58492e12 537 &entry, sizeof(entry));
b36ca91e 538
93f1cc67 539 amd_iommu_reset_cmd_buffer(iommu);
b36ca91e
JR		 540}
541
542static void __init free_command_buffer(struct amd_iommu *iommu)
543{
deba4bce 544 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
b36ca91e
JR		 545}
546
335503e5 547/* allocates the memory where the IOMMU will log its events to */
f2c2db53 548static int __init alloc_event_buffer(struct amd_iommu *iommu)
335503e5 549{
f2c2db53
JR		 550 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
551 get_order(EVT_BUFFER_SIZE));
335503e5 552
f2c2db53 553 return iommu->evt_buf ? 0 : -ENOMEM;
58492e12
JR		 554}
555
556static void iommu_enable_event_buffer(struct amd_iommu *iommu)
557{
558 u64 entry;
559
560 BUG_ON(iommu->evt_buf == NULL);
561
335503e5 562 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
58492e12 563
335503e5
JR		 564 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
565 &entry, sizeof(entry));
566
09067207
JR		 567 /* set head and tail to zero manually */
568 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
569 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
570
58492e12 571 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
335503e5
JR		 572}
573
574static void __init free_event_buffer(struct amd_iommu *iommu)
575{
576 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
577}
578
1a29ac01 579/* allocates the memory where the IOMMU will log its events to */
f2c2db53 580static int __init alloc_ppr_log(struct amd_iommu *iommu)
1a29ac01 581{
f2c2db53
JR		 582 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
583 get_order(PPR_LOG_SIZE));
1a29ac01 584
f2c2db53 585 return iommu->ppr_log ? 0 : -ENOMEM;
1a29ac01
JR		 586}
587
588static void iommu_enable_ppr_log(struct amd_iommu *iommu)
589{
590 u64 entry;
591
592 if (iommu->ppr_log == NULL)
593 return;
594
595 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
596
597 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
598 &entry, sizeof(entry));
599
600 /* set head and tail to zero manually */
601 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
602 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
603
604 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
605 iommu_feature_enable(iommu, CONTROL_PPR_EN);
606}
607
608static void __init free_ppr_log(struct amd_iommu *iommu)
609{
610 if (iommu->ppr_log == NULL)
611 return;
612
613 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
614}
615
cbc33a90
JR		 616static void iommu_enable_gt(struct amd_iommu *iommu)
617{
618 if (!iommu_feature(iommu, FEATURE_GT))
619 return;
620
621 iommu_feature_enable(iommu, CONTROL_GT_EN);
622}
623
b65233a9 624/* sets a specific bit in the device table entry. */
3566b778
JR		 625static void set_dev_entry_bit(u16 devid, u8 bit)
626{
ee6c2868
JR		 627 int i = (bit >> 6) & 0x03;
628 int _bit = bit & 0x3f;
3566b778 629
ee6c2868 630 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
3566b778
JR		 631}
632
c5cca146
JR		 633static int get_dev_entry_bit(u16 devid, u8 bit)
634{
ee6c2868
JR		 635 int i = (bit >> 6) & 0x03;
636 int _bit = bit & 0x3f;
c5cca146 637
ee6c2868 638 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
c5cca146
JR		 639}
640
641
642void amd_iommu_apply_erratum_63(u16 devid)
643{
644 int sysmgt;
645
646 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
647 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
648
649 if (sysmgt == 0x01)
650 set_dev_entry_bit(devid, DEV_ENTRY_IW);
651}
652
5ff4789d
JR		 653/* Writes the specific IOMMU for a device into the rlookup table */
654static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
655{
656 amd_iommu_rlookup_table[devid] = iommu;
657}
658
b65233a9
JR		 659/*
660 * This function takes the device specific flags read from the ACPI
661 * table and sets up the device table entry with that information
662 */
5ff4789d
JR		 663static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
664 u16 devid, u32 flags, u32 ext_flags)
3566b778
JR		 665{
666 if (flags & ACPI_DEVFLAG_INITPASS)
667 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
668 if (flags & ACPI_DEVFLAG_EXTINT)
669 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
670 if (flags & ACPI_DEVFLAG_NMI)
671 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
672 if (flags & ACPI_DEVFLAG_SYSMGT1)
673 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
674 if (flags & ACPI_DEVFLAG_SYSMGT2)
675 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
676 if (flags & ACPI_DEVFLAG_LINT0)
677 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
678 if (flags & ACPI_DEVFLAG_LINT1)
679 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
3566b778 680
c5cca146
JR		 681 amd_iommu_apply_erratum_63(devid);
682
5ff4789d 683 set_iommu_for_device(iommu, devid);
3566b778
JR		 684}
685
c50e3247 686static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
6efed63b
JR		 687{
688 struct devid_map *entry;
689 struct list_head *list;
690
31cff67f
JR		 691 if (type == IVHD_SPECIAL_IOAPIC)
692 list = &ioapic_map;
693 else if (type == IVHD_SPECIAL_HPET)
694 list = &hpet_map;
695 else
6efed63b
JR		 696 return -EINVAL;
697
31cff67f
JR		 698 list_for_each_entry(entry, list, list) {
699 if (!(entry->id == id && entry->cmd_line))
700 continue;
701
702 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
703 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
704
c50e3247
JR		 705 *devid = entry->devid;
706
31cff67f
JR		 707 return 0;
708 }
709
6efed63b
JR		 710 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
711 if (!entry)
712 return -ENOMEM;
713
31cff67f 714 entry->id = id;
c50e3247 715 entry->devid = *devid;
31cff67f 716 entry->cmd_line = cmd_line;
6efed63b
JR		 717
718 list_add_tail(&entry->list, list);
719
720 return 0;
721}
722
235dacbc
JR		 723static int __init add_early_maps(void)
724{
725 int i, ret;
726
727 for (i = 0; i < early_ioapic_map_size; ++i) {
728 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
729 early_ioapic_map[i].id,
c50e3247 730 &early_ioapic_map[i].devid,
235dacbc
JR		 731 early_ioapic_map[i].cmd_line);
732 if (ret)
733 return ret;
734 }
735
736 for (i = 0; i < early_hpet_map_size; ++i) {
737 ret = add_special_device(IVHD_SPECIAL_HPET,
738 early_hpet_map[i].id,
c50e3247 739 &early_hpet_map[i].devid,
235dacbc
JR		 740 early_hpet_map[i].cmd_line);
741 if (ret)
742 return ret;
743 }
744
745 return 0;
746}
747
b65233a9 748/*
df805abb 749 * Reads the device exclusion range from ACPI and initializes the IOMMU with
b65233a9
JR		 750 * it
751 */
3566b778
JR		 752static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
753{
754 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
755
756 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
757 return;
758
759 if (iommu) {
b65233a9
JR		 760 /*
761 * We only can configure exclusion ranges per IOMMU, not
762 * per device. But we can enable the exclusion range per
763 * device. This is done here
764 */
2c16c9fd 765 set_dev_entry_bit(devid, DEV_ENTRY_EX);
3566b778
JR		 766 iommu->exclusion_start = m->range_start;
767 iommu->exclusion_length = m->range_length;
768 }
769}
770
b65233a9
JR		 771/*
772 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
773 * initializes the hardware and our data structures with it.
774 */
6efed63b 775static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
5d0c8e49
JR		 776 struct ivhd_header *h)
777{
778 u8 *p = (u8 *)h;
779 u8 *end = p, flags = 0;
0de66d5b
JR		 780 u16 devid = 0, devid_start = 0, devid_to = 0;
781 u32 dev_i, ext_flags = 0;
58a3bee5 782 bool alias = false;
5d0c8e49 783 struct ivhd_entry *e;
235dacbc
JR		 784 int ret;
785
786
787 ret = add_early_maps();
788 if (ret)
789 return ret;
5d0c8e49
JR		 790
791 /*
e9bf5197 792 * First save the recommended feature enable bits from ACPI
5d0c8e49 793 */
e9bf5197 794 iommu->acpi_flags = h->flags;
5d0c8e49
JR		 795
796 /*
797 * Done. Now parse the device entries
798 */
799 p += sizeof(struct ivhd_header);
800 end += h->length;
801
42a698f4 802
5d0c8e49
JR		 803 while (p < end) {
804 e = (struct ivhd_entry *)p;
805 switch (e->type) {
806 case IVHD_DEV_ALL:
42a698f4 807
226e889b 808 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
42a698f4 809
226e889b
JR		 810 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
811 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
5d0c8e49
JR		 812 break;
813 case IVHD_DEV_SELECT:
42a698f4
JR		 814
815 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
816 "flags: %02x\n",
c5081cd7 817 PCI_BUS_NUM(e->devid),
42a698f4
JR		 818 PCI_SLOT(e->devid),
819 PCI_FUNC(e->devid),
820 e->flags);
821
5d0c8e49 822 devid = e->devid;
5ff4789d 823 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
5d0c8e49
JR		 824 break;
825 case IVHD_DEV_SELECT_RANGE_START:
42a698f4
JR		 826
827 DUMP_printk(" DEV_SELECT_RANGE_START\t "
828 "devid: %02x:%02x.%x flags: %02x\n",
c5081cd7 829 PCI_BUS_NUM(e->devid),
42a698f4
JR		 830 PCI_SLOT(e->devid),
831 PCI_FUNC(e->devid),
832 e->flags);
833
5d0c8e49
JR		 834 devid_start = e->devid;
835 flags = e->flags;
836 ext_flags = 0;
58a3bee5 837 alias = false;
5d0c8e49
JR		 838 break;
839 case IVHD_DEV_ALIAS:
42a698f4
JR		 840
841 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
842 "flags: %02x devid_to: %02x:%02x.%x\n",
c5081cd7 843 PCI_BUS_NUM(e->devid),
42a698f4
JR		 844 PCI_SLOT(e->devid),
845 PCI_FUNC(e->devid),
846 e->flags,
c5081cd7 847 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 848 PCI_SLOT(e->ext >> 8),
849 PCI_FUNC(e->ext >> 8));
850
5d0c8e49
JR		 851 devid = e->devid;
852 devid_to = e->ext >> 8;
7a6a3a08 853 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
7455aab1 854 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
5d0c8e49
JR		 855 amd_iommu_alias_table[devid] = devid_to;
856 break;
857 case IVHD_DEV_ALIAS_RANGE:
42a698f4
JR		 858
859 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
860 "devid: %02x:%02x.%x flags: %02x "
861 "devid_to: %02x:%02x.%x\n",
c5081cd7 862 PCI_BUS_NUM(e->devid),
42a698f4
JR		 863 PCI_SLOT(e->devid),
864 PCI_FUNC(e->devid),
865 e->flags,
c5081cd7 866 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 867 PCI_SLOT(e->ext >> 8),
868 PCI_FUNC(e->ext >> 8));
869
5d0c8e49
JR		 870 devid_start = e->devid;
871 flags = e->flags;
872 devid_to = e->ext >> 8;
873 ext_flags = 0;
58a3bee5 874 alias = true;
5d0c8e49
JR		 875 break;
876 case IVHD_DEV_EXT_SELECT:
42a698f4
JR		 877
878 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
879 "flags: %02x ext: %08x\n",
c5081cd7 880 PCI_BUS_NUM(e->devid),
42a698f4
JR		 881 PCI_SLOT(e->devid),
882 PCI_FUNC(e->devid),
883 e->flags, e->ext);
884
5d0c8e49 885 devid = e->devid;
5ff4789d
JR		 886 set_dev_entry_from_acpi(iommu, devid, e->flags,
887 e->ext);
5d0c8e49
JR		 888 break;
889 case IVHD_DEV_EXT_SELECT_RANGE:
42a698f4
JR		 890
891 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
892 "%02x:%02x.%x flags: %02x ext: %08x\n",
c5081cd7 893 PCI_BUS_NUM(e->devid),
42a698f4
JR		 894 PCI_SLOT(e->devid),
895 PCI_FUNC(e->devid),
896 e->flags, e->ext);
897
5d0c8e49
JR		 898 devid_start = e->devid;
899 flags = e->flags;
900 ext_flags = e->ext;
58a3bee5 901 alias = false;
5d0c8e49
JR		 902 break;
903 case IVHD_DEV_RANGE_END:
42a698f4
JR		 904
905 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
c5081cd7 906 PCI_BUS_NUM(e->devid),
42a698f4
JR		 907 PCI_SLOT(e->devid),
908 PCI_FUNC(e->devid));
909
5d0c8e49
JR		 910 devid = e->devid;
911 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
7a6a3a08 912 if (alias) {
5d0c8e49 913 amd_iommu_alias_table[dev_i] = devid_to;
7a6a3a08
JR		 914 set_dev_entry_from_acpi(iommu,
915 devid_to, flags, ext_flags);
916 }
917 set_dev_entry_from_acpi(iommu, dev_i,
918 flags, ext_flags);
5d0c8e49
JR		 919 }
920 break;
6efed63b
JR		 921 case IVHD_DEV_SPECIAL: {
922 u8 handle, type;
923 const char *var;
924 u16 devid;
925 int ret;
926
927 handle = e->ext & 0xff;
928 devid = (e->ext >> 8) & 0xffff;
929 type = (e->ext >> 24) & 0xff;
930
931 if (type == IVHD_SPECIAL_IOAPIC)
932 var = "IOAPIC";
933 else if (type == IVHD_SPECIAL_HPET)
934 var = "HPET";
935 else
936 var = "UNKNOWN";
937
938 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
939 var, (int)handle,
c5081cd7 940 PCI_BUS_NUM(devid),
6efed63b
JR		 941 PCI_SLOT(devid),
942 PCI_FUNC(devid));
943
c50e3247 944 ret = add_special_device(type, handle, &devid, false);
6efed63b
JR		 945 if (ret)
946 return ret;
c50e3247
JR		 947
948 /*
949 * add_special_device might update the devid in case a
950 * command-line override is present. So call
951 * set_dev_entry_from_acpi after add_special_device.
952 */
953 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
954
6efed63b
JR		 955 break;
956 }
5d0c8e49
JR		 957 default:
958 break;
959 }
960
b514e555 961 p += ivhd_entry_length(p);
5d0c8e49 962 }
6efed63b
JR		 963
964 return 0;
5d0c8e49
JR		 965}
966
e47d402d
JR		 967static void __init free_iommu_one(struct amd_iommu *iommu)
968{
969 free_command_buffer(iommu);
335503e5 970 free_event_buffer(iommu);
1a29ac01 971 free_ppr_log(iommu);
e47d402d
JR		 972 iommu_unmap_mmio_space(iommu);
973}
974
975static void __init free_iommu_all(void)
976{
977 struct amd_iommu *iommu, *next;
978
3bd22172 979 for_each_iommu_safe(iommu, next) {
e47d402d
JR		 980 list_del(&iommu->list);
981 free_iommu_one(iommu);
982 kfree(iommu);
983 }
984}
985
318fe782
SS		 986/*
987 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
988 * Workaround:
989 * BIOS should disable L2B micellaneous clock gating by setting
990 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
991 */
e2f1a3bd 992static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
318fe782
SS		 993{
994 u32 value;
995
996 if ((boot_cpu_data.x86 != 0x15) ||
997 (boot_cpu_data.x86_model < 0x10) ||
998 (boot_cpu_data.x86_model > 0x1f))
999 return;
1000
1001 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1002 pci_read_config_dword(iommu->dev, 0xf4, &value);
1003
1004 if (value & BIT(2))
1005 return;
1006
1007 /* Select NB indirect register 0x90 and enable writing */
1008 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1009
1010 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1011 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1012 dev_name(&iommu->dev->dev));
1013
1014 /* Clear the enable writing bit */
1015 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1016}
1017
b65233a9
JR		 1018/*
1019 * This function clues the initialization function for one IOMMU
1020 * together and also allocates the command buffer and programs the
1021 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1022 */
e47d402d
JR		 1023static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1024{
6efed63b
JR		 1025 int ret;
1026
e47d402d 1027 spin_lock_init(&iommu->lock);
bb52777e
JR		 1028
1029 /* Add IOMMU to internal data structures */
e47d402d 1030 list_add_tail(&iommu->list, &amd_iommu_list);
bb52777e
JR		 1031 iommu->index = amd_iommus_present++;
1032
1033 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1034 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1035 return -ENOSYS;
1036 }
1037
1038 /* Index is fine - add IOMMU to the array */
1039 amd_iommus[iommu->index] = iommu;
e47d402d
JR		 1040
1041 /*
1042 * Copy data from ACPI table entry to the iommu struct
1043 */
23c742db 1044 iommu->devid = h->devid;
e47d402d 1045 iommu->cap_ptr = h->cap_ptr;
ee893c24 1046 iommu->pci_seg = h->pci_seg;
e47d402d 1047 iommu->mmio_phys = h->mmio_phys;
30861ddc
SK		 1048
1049 /* Check if IVHD EFR contains proper max banks/counters */
1050 if ((h->efr != 0) &&
1051 ((h->efr & (0xF << 13)) != 0) &&
1052 ((h->efr & (0x3F << 17)) != 0)) {
1053 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1054 } else {
1055 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1056 }
1057
1058 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1059 iommu->mmio_phys_end);
e47d402d
JR		 1060 if (!iommu->mmio_base)
1061 return -ENOMEM;
1062
f2c2db53 1063 if (alloc_command_buffer(iommu))
e47d402d
JR		 1064 return -ENOMEM;
1065
f2c2db53 1066 if (alloc_event_buffer(iommu))
335503e5
JR		 1067 return -ENOMEM;
1068
a80dc3e0
JR		 1069 iommu->int_enabled = false;
1070
6efed63b
JR		 1071 ret = init_iommu_from_acpi(iommu, h);
1072 if (ret)
1073 return ret;
f6fec00a 1074
7c71d306
JL		 1075 ret = amd_iommu_create_irq_domain(iommu);
1076 if (ret)
1077 return ret;
1078
f6fec00a
JR		 1079 /*
1080 * Make sure IOMMU is not considered to translate itself. The IVRS
1081 * table tells us so, but this is a lie!
1082 */
1083 amd_iommu_rlookup_table[iommu->devid] = NULL;
1084
23c742db 1085 return 0;
e47d402d
JR		 1086}
1087
b65233a9
JR		 1088/*
1089 * Iterates over all IOMMU entries in the ACPI table, allocates the
1090 * IOMMU structure and initializes it with init_iommu_one()
1091 */
e47d402d
JR		 1092static int __init init_iommu_all(struct acpi_table_header *table)
1093{
1094 u8 *p = (u8 *)table, *end = (u8 *)table;
1095 struct ivhd_header *h;
1096 struct amd_iommu *iommu;
1097 int ret;
1098
e47d402d
JR		 1099 end += table->length;
1100 p += IVRS_HEADER_LENGTH;
1101
1102 while (p < end) {
1103 h = (struct ivhd_header *)p;
1104 switch (*p) {
1105 case ACPI_IVHD_TYPE:
9c72041f 1106
ae908c22 1107 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
9c72041f 1108 "seg: %d flags: %01x info %04x\n",
c5081cd7 1109 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
9c72041f
JR		 1110 PCI_FUNC(h->devid), h->cap_ptr,
1111 h->pci_seg, h->flags, h->info);
1112 DUMP_printk(" mmio-addr: %016llx\n",
1113 h->mmio_phys);
1114
e47d402d 1115 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
02f3b3f5
JR		 1116 if (iommu == NULL)
1117 return -ENOMEM;
3551a708 1118
e47d402d 1119 ret = init_iommu_one(iommu, h);
02f3b3f5
JR		 1120 if (ret)
1121 return ret;
e47d402d
JR		 1122 break;
1123 default:
1124 break;
1125 }
1126 p += h->length;
1127
1128 }
1129 WARN_ON(p != end);
1130
1131 return 0;
1132}
1133
30861ddc
SK		 1134
1135static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1136{
1137 u64 val = 0xabcd, val2 = 0;
1138
1139 if (!iommu_feature(iommu, FEATURE_PC))
1140 return;
1141
1142 amd_iommu_pc_present = true;
1143
1144 /* Check if the performance counters can be written to */
1145 if ((0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val, true)) ||
1146 (0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val2, false)) ||
1147 (val != val2)) {
1148 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1149 amd_iommu_pc_present = false;
1150 return;
1151 }
1152
1153 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1154
1155 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1156 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1157 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1158}
1159
066f2e98
AW		 1160static ssize_t amd_iommu_show_cap(struct device *dev,
1161 struct device_attribute *attr,
1162 char *buf)
1163{
1164 struct amd_iommu *iommu = dev_get_drvdata(dev);
1165 return sprintf(buf, "%x\n", iommu->cap);
1166}
1167static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1168
1169static ssize_t amd_iommu_show_features(struct device *dev,
1170 struct device_attribute *attr,
1171 char *buf)
1172{
1173 struct amd_iommu *iommu = dev_get_drvdata(dev);
1174 return sprintf(buf, "%llx\n", iommu->features);
1175}
1176static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1177
1178static struct attribute *amd_iommu_attrs[] = {
1179 &dev_attr_cap.attr,
1180 &dev_attr_features.attr,
1181 NULL,
1182};
1183
1184static struct attribute_group amd_iommu_group = {
1185 .name = "amd-iommu",
1186 .attrs = amd_iommu_attrs,
1187};
1188
1189static const struct attribute_group *amd_iommu_groups[] = {
1190 &amd_iommu_group,
1191 NULL,
1192};
30861ddc 1193
23c742db
JR		 1194static int iommu_init_pci(struct amd_iommu *iommu)
1195{
1196 int cap_ptr = iommu->cap_ptr;
1197 u32 range, misc, low, high;
1198
c5081cd7 1199 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
23c742db
JR		 1200 iommu->devid & 0xff);
1201 if (!iommu->dev)
1202 return -ENODEV;
1203
cbbc00be
JL		 1204 /* Prevent binding other PCI device drivers to IOMMU devices */
1205 iommu->dev->match_driver = false;
1206
23c742db
JR		 1207 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1208 &iommu->cap);
1209 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1210 &range);
1211 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1212 &misc);
1213
23c742db
JR		 1214 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1215 amd_iommu_iotlb_sup = false;
1216
1217 /* read extended feature bits */
1218 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1219 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1220
1221 iommu->features = ((u64)high << 32) | low;
1222
1223 if (iommu_feature(iommu, FEATURE_GT)) {
1224 int glxval;
a919a018
SS		 1225 u32 max_pasid;
1226 u64 pasmax;
23c742db 1227
a919a018
SS		 1228 pasmax = iommu->features & FEATURE_PASID_MASK;
1229 pasmax >>= FEATURE_PASID_SHIFT;
1230 max_pasid = (1 << (pasmax + 1)) - 1;
23c742db 1231
a919a018
SS		 1232 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1233
1234 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
23c742db
JR		 1235
1236 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1237 glxval >>= FEATURE_GLXVAL_SHIFT;
1238
1239 if (amd_iommu_max_glx_val == -1)
1240 amd_iommu_max_glx_val = glxval;
1241 else
1242 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1243 }
1244
1245 if (iommu_feature(iommu, FEATURE_GT) &&
1246 iommu_feature(iommu, FEATURE_PPR)) {
1247 iommu->is_iommu_v2 = true;
1248 amd_iommu_v2_present = true;
1249 }
1250
f2c2db53
JR		 1251 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1252 return -ENOMEM;
23c742db
JR		 1253
1254 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1255 amd_iommu_np_cache = true;
1256
30861ddc
SK		 1257 init_iommu_perf_ctr(iommu);
1258
23c742db
JR		 1259 if (is_rd890_iommu(iommu->dev)) {
1260 int i, j;
1261
1262 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1263 PCI_DEVFN(0, 0));
1264
1265 /*
1266 * Some rd890 systems may not be fully reconfigured by the
1267 * BIOS, so it's necessary for us to store this information so
1268 * it can be reprogrammed on resume
1269 */
1270 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1271 &iommu->stored_addr_lo);
1272 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1273 &iommu->stored_addr_hi);
1274
1275 /* Low bit locks writes to configuration space */
1276 iommu->stored_addr_lo &= ~1;
1277
1278 for (i = 0; i < 6; i++)
1279 for (j = 0; j < 0x12; j++)
1280 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1281
1282 for (i = 0; i < 0x83; i++)
1283 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1284 }
1285
318fe782
SS		 1286 amd_iommu_erratum_746_workaround(iommu);
1287
066f2e98
AW		 1288 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
1289 amd_iommu_groups, "ivhd%d",
1290 iommu->index);
1291
23c742db
JR		 1292 return pci_enable_device(iommu->dev);
1293}
1294
4d121c32
JR		 1295static void print_iommu_info(void)
1296{
1297 static const char * const feat_str[] = {
1298 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1299 "IA", "GA", "HE", "PC"
1300 };
1301 struct amd_iommu *iommu;
1302
1303 for_each_iommu(iommu) {
1304 int i;
1305
1306 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1307 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1308
1309 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1310 pr_info("AMD-Vi: Extended features: ");
2bd5ed00 1311 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
4d121c32
JR		 1312 if (iommu_feature(iommu, (1ULL << i)))
1313 pr_cont(" %s", feat_str[i]);
1314 }
30861ddc 1315 pr_cont("\n");
500c25ed 1316 }
4d121c32 1317 }
ebe60bbf
JR		 1318 if (irq_remapping_enabled)
1319 pr_info("AMD-Vi: Interrupt remapping enabled\n");
4d121c32
JR		 1320}
1321
2c0ae172 1322static int __init amd_iommu_init_pci(void)
23c742db
JR		 1323{
1324 struct amd_iommu *iommu;
1325 int ret = 0;
1326
1327 for_each_iommu(iommu) {
1328 ret = iommu_init_pci(iommu);
1329 if (ret)
1330 break;
1331 }
1332
aafd8ba0
JR		 1333 init_device_table_dma();
1334
1335 for_each_iommu(iommu)
1336 iommu_flush_all_caches(iommu);
1337
3a18404c 1338 ret = amd_iommu_init_api();
23c742db 1339
3a18404c
JR		 1340 if (!ret)
1341 print_iommu_info();
4d121c32 1342
23c742db
JR		 1343 return ret;
1344}
1345
a80dc3e0
JR		 1346/****************************************************************************
1347 *
1348 * The following functions initialize the MSI interrupts for all IOMMUs
df805abb 1349 * in the system. It's a bit challenging because there could be multiple
a80dc3e0
JR		 1350 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1351 * pci_dev.
1352 *
1353 ****************************************************************************/
1354
9f800de3 1355static int iommu_setup_msi(struct amd_iommu *iommu)
a80dc3e0
JR		 1356{
1357 int r;
a80dc3e0 1358
9ddd592a
JR		 1359 r = pci_enable_msi(iommu->dev);
1360 if (r)
1361 return r;
a80dc3e0 1362
72fe00f0
JR		 1363 r = request_threaded_irq(iommu->dev->irq,
1364 amd_iommu_int_handler,
1365 amd_iommu_int_thread,
1366 0, "AMD-Vi",
3f398bc7 1367 iommu);
a80dc3e0
JR		 1368
1369 if (r) {
1370 pci_disable_msi(iommu->dev);
9ddd592a 1371 return r;
a80dc3e0
JR		 1372 }
1373
fab6afa3 1374 iommu->int_enabled = true;
1a29ac01 1375
a80dc3e0
JR		 1376 return 0;
1377}
1378
05f92db9 1379static int iommu_init_msi(struct amd_iommu *iommu)
a80dc3e0 1380{
9ddd592a
JR		 1381 int ret;
1382
a80dc3e0 1383 if (iommu->int_enabled)
9ddd592a 1384 goto enable_faults;
a80dc3e0 1385
82fcfc67 1386 if (iommu->dev->msi_cap)
9ddd592a
JR		 1387 ret = iommu_setup_msi(iommu);
1388 else
1389 ret = -ENODEV;
1390
1391 if (ret)
1392 return ret;
a80dc3e0 1393
9ddd592a
JR		 1394enable_faults:
1395 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
a80dc3e0 1396
9ddd592a
JR		 1397 if (iommu->ppr_log != NULL)
1398 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1399
1400 return 0;
a80dc3e0
JR		 1401}
1402
b65233a9
JR		 1403/****************************************************************************
1404 *
1405 * The next functions belong to the third pass of parsing the ACPI
1406 * table. In this last pass the memory mapping requirements are
df805abb 1407 * gathered (like exclusion and unity mapping ranges).
b65233a9
JR		 1408 *
1409 ****************************************************************************/
1410
be2a022c
JR		 1411static void __init free_unity_maps(void)
1412{
1413 struct unity_map_entry *entry, *next;
1414
1415 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1416 list_del(&entry->list);
1417 kfree(entry);
1418 }
1419}
1420
b65233a9 1421/* called when we find an exclusion range definition in ACPI */
be2a022c
JR		 1422static int __init init_exclusion_range(struct ivmd_header *m)
1423{
1424 int i;
1425
1426 switch (m->type) {
1427 case ACPI_IVMD_TYPE:
1428 set_device_exclusion_range(m->devid, m);
1429 break;
1430 case ACPI_IVMD_TYPE_ALL:
3a61ec38 1431 for (i = 0; i <= amd_iommu_last_bdf; ++i)
be2a022c
JR		 1432 set_device_exclusion_range(i, m);
1433 break;
1434 case ACPI_IVMD_TYPE_RANGE:
1435 for (i = m->devid; i <= m->aux; ++i)
1436 set_device_exclusion_range(i, m);
1437 break;
1438 default:
1439 break;
1440 }
1441
1442 return 0;
1443}
1444
b65233a9 1445/* called for unity map ACPI definition */
be2a022c
JR		 1446static int __init init_unity_map_range(struct ivmd_header *m)
1447{
98f1ad25 1448 struct unity_map_entry *e = NULL;
02acc43a 1449 char *s;
be2a022c
JR		 1450
1451 e = kzalloc(sizeof(*e), GFP_KERNEL);
1452 if (e == NULL)
1453 return -ENOMEM;
1454
1455 switch (m->type) {
1456 default:
0bc252f4
JR		 1457 kfree(e);
1458 return 0;
be2a022c 1459 case ACPI_IVMD_TYPE:
02acc43a 1460 s = "IVMD_TYPEi\t\t\t";
be2a022c
JR		 1461 e->devid_start = e->devid_end = m->devid;
1462 break;
1463 case ACPI_IVMD_TYPE_ALL:
02acc43a 1464 s = "IVMD_TYPE_ALL\t\t";
be2a022c
JR		 1465 e->devid_start = 0;
1466 e->devid_end = amd_iommu_last_bdf;
1467 break;
1468 case ACPI_IVMD_TYPE_RANGE:
02acc43a 1469 s = "IVMD_TYPE_RANGE\t\t";
be2a022c
JR		 1470 e->devid_start = m->devid;
1471 e->devid_end = m->aux;
1472 break;
1473 }
1474 e->address_start = PAGE_ALIGN(m->range_start);
1475 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1476 e->prot = m->flags >> 1;
1477
02acc43a
JR		 1478 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1479 " range_start: %016llx range_end: %016llx flags: %x\n", s,
c5081cd7
SK		 1480 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1481 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
02acc43a
JR		 1482 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1483 e->address_start, e->address_end, m->flags);
1484
be2a022c
JR		 1485 list_add_tail(&e->list, &amd_iommu_unity_map);
1486
1487 return 0;
1488}
1489
b65233a9 1490/* iterates over all memory definitions we find in the ACPI table */
be2a022c
JR		 1491static int __init init_memory_definitions(struct acpi_table_header *table)
1492{
1493 u8 *p = (u8 *)table, *end = (u8 *)table;
1494 struct ivmd_header *m;
1495
be2a022c
JR		 1496 end += table->length;
1497 p += IVRS_HEADER_LENGTH;
1498
1499 while (p < end) {
1500 m = (struct ivmd_header *)p;
1501 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1502 init_exclusion_range(m);
1503 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1504 init_unity_map_range(m);
1505
1506 p += m->length;
1507 }
1508
1509 return 0;
1510}
1511
9f5f5fb3
JR		 1512/*
1513 * Init the device table to not allow DMA access for devices and
1514 * suppress all page faults
1515 */
33f28c59 1516static void init_device_table_dma(void)
9f5f5fb3 1517{
0de66d5b 1518 u32 devid;
9f5f5fb3
JR		 1519
1520 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1521 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1522 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
9f5f5fb3
JR		 1523 }
1524}
1525
d04e0ba3
JR		 1526static void __init uninit_device_table_dma(void)
1527{
1528 u32 devid;
1529
1530 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1531 amd_iommu_dev_table[devid].data[0] = 0ULL;
1532 amd_iommu_dev_table[devid].data[1] = 0ULL;
1533 }
1534}
1535
33f28c59
JR		 1536static void init_device_table(void)
1537{
1538 u32 devid;
1539
1540 if (!amd_iommu_irq_remap)
1541 return;
1542
1543 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1544 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1545}
1546
e9bf5197
JR		 1547static void iommu_init_flags(struct amd_iommu *iommu)
1548{
1549 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1550 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1551 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1552
1553 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1554 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1555 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1556
1557 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1558 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1559 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1560
1561 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1562 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1563 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1564
1565 /*
1566 * make IOMMU memory accesses cache coherent
1567 */
1568 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1456e9d2
JR		 1569
1570 /* Set IOTLB invalidation timeout to 1s */
1571 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
e9bf5197
JR		 1572}
1573
5bcd757f 1574static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
4c894f47 1575{
5bcd757f
MG		 1576 int i, j;
1577 u32 ioc_feature_control;
c1bf94ec 1578 struct pci_dev *pdev = iommu->root_pdev;
5bcd757f
MG		 1579
1580 /* RD890 BIOSes may not have completely reconfigured the iommu */
c1bf94ec 1581 if (!is_rd890_iommu(iommu->dev) || !pdev)
5bcd757f
MG		 1582 return;
1583
1584 /*
1585 * First, we need to ensure that the iommu is enabled. This is
1586 * controlled by a register in the northbridge
1587 */
5bcd757f
MG		 1588
1589 /* Select Northbridge indirect register 0x75 and enable writing */
1590 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1591 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1592
1593 /* Enable the iommu */
1594 if (!(ioc_feature_control & 0x1))
1595 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1596
5bcd757f
MG		 1597 /* Restore the iommu BAR */
1598 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1599 iommu->stored_addr_lo);
1600 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1601 iommu->stored_addr_hi);
1602
1603 /* Restore the l1 indirect regs for each of the 6 l1s */
1604 for (i = 0; i < 6; i++)
1605 for (j = 0; j < 0x12; j++)
1606 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1607
1608 /* Restore the l2 indirect regs */
1609 for (i = 0; i < 0x83; i++)
1610 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1611
1612 /* Lock PCI setup registers */
1613 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1614 iommu->stored_addr_lo | 1);
4c894f47
JR		 1615}
1616
b65233a9
JR		 1617/*
1618 * This function finally enables all IOMMUs found in the system after
1619 * they have been initialized
1620 */
11ee5ac4 1621static void early_enable_iommus(void)
8736197b
JR		 1622{
1623 struct amd_iommu *iommu;
1624
3bd22172 1625 for_each_iommu(iommu) {
a8c485bb 1626 iommu_disable(iommu);
e9bf5197 1627 iommu_init_flags(iommu);
58492e12
JR		 1628 iommu_set_device_table(iommu);
1629 iommu_enable_command_buffer(iommu);
1630 iommu_enable_event_buffer(iommu);
8736197b
JR		 1631 iommu_set_exclusion_range(iommu);
1632 iommu_enable(iommu);
7d0c5cc5 1633 iommu_flush_all_caches(iommu);
8736197b
JR		 1634 }
1635}
1636
11ee5ac4
JR		 1637static void enable_iommus_v2(void)
1638{
1639 struct amd_iommu *iommu;
1640
1641 for_each_iommu(iommu) {
1642 iommu_enable_ppr_log(iommu);
1643 iommu_enable_gt(iommu);
1644 }
1645}
1646
1647static void enable_iommus(void)
1648{
1649 early_enable_iommus();
1650
1651 enable_iommus_v2();
1652}
1653
92ac4320
JR		 1654static void disable_iommus(void)
1655{
1656 struct amd_iommu *iommu;
1657
1658 for_each_iommu(iommu)
1659 iommu_disable(iommu);
1660}
1661
7441e9cb
JR		 1662/*
1663 * Suspend/Resume support
1664 * disable suspend until real resume implemented
1665 */
1666
f3c6ea1b 1667static void amd_iommu_resume(void)
7441e9cb 1668{
5bcd757f
MG		 1669 struct amd_iommu *iommu;
1670
1671 for_each_iommu(iommu)
1672 iommu_apply_resume_quirks(iommu);
1673
736501ee
JR		 1674 /* re-load the hardware */
1675 enable_iommus();
3d9761e7
JR		 1676
1677 amd_iommu_enable_interrupts();
7441e9cb
JR		 1678}
1679
f3c6ea1b 1680static int amd_iommu_suspend(void)
7441e9cb 1681{
736501ee
JR		 1682 /* disable IOMMUs to go out of the way for BIOS */
1683 disable_iommus();
1684
1685 return 0;
7441e9cb
JR		 1686}
1687
f3c6ea1b 1688static struct syscore_ops amd_iommu_syscore_ops = {
7441e9cb
JR		 1689 .suspend = amd_iommu_suspend,
1690 .resume = amd_iommu_resume,
1691};
1692
8704a1ba
JR		 1693static void __init free_on_init_error(void)
1694{
0ea2c422
JR		 1695 free_pages((unsigned long)irq_lookup_table,
1696 get_order(rlookup_table_size));
8704a1ba 1697
a591989a
JL		 1698 kmem_cache_destroy(amd_iommu_irq_cache);
1699 amd_iommu_irq_cache = NULL;
8704a1ba
JR		 1700
1701 free_pages((unsigned long)amd_iommu_rlookup_table,
1702 get_order(rlookup_table_size));
1703
1704 free_pages((unsigned long)amd_iommu_alias_table,
1705 get_order(alias_table_size));
1706
1707 free_pages((unsigned long)amd_iommu_dev_table,
1708 get_order(dev_table_size));
1709
1710 free_iommu_all();
1711
8704a1ba
JR		 1712#ifdef CONFIG_GART_IOMMU
1713 /*
1714 * We failed to initialize the AMD IOMMU - try fallback to GART
1715 * if possible.
1716 */
1717 gart_iommu_init();
1718
1719#endif
1720}
1721
c2ff5cf5
JR		 1722/* SB IOAPIC is always on this device in AMD systems */
1723#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1724
eb1eb7ae
JR		 1725static bool __init check_ioapic_information(void)
1726{
dfbb6d47 1727 const char *fw_bug = FW_BUG;
c2ff5cf5 1728 bool ret, has_sb_ioapic;
eb1eb7ae
JR		 1729 int idx;
1730
c2ff5cf5
JR		 1731 has_sb_ioapic = false;
1732 ret = false;
eb1eb7ae 1733
dfbb6d47
JR		 1734 /*
1735 * If we have map overrides on the kernel command line the
1736 * messages in this function might not describe firmware bugs
1737 * anymore - so be careful
1738 */
1739 if (cmdline_maps)
1740 fw_bug = "";
1741
c2ff5cf5
JR		 1742 for (idx = 0; idx < nr_ioapics; idx++) {
1743 int devid, id = mpc_ioapic_id(idx);
1744
1745 devid = get_ioapic_devid(id);
1746 if (devid < 0) {
dfbb6d47
JR		 1747 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
1748 fw_bug, id);
c2ff5cf5
JR		 1749 ret = false;
1750 } else if (devid == IOAPIC_SB_DEVID) {
1751 has_sb_ioapic = true;
1752 ret = true;
eb1eb7ae
JR		 1753 }
1754 }
1755
c2ff5cf5
JR		 1756 if (!has_sb_ioapic) {
1757 /*
1758 * We expect the SB IOAPIC to be listed in the IVRS
1759 * table. The system timer is connected to the SB IOAPIC
1760 * and if we don't have it in the list the system will
1761 * panic at boot time. This situation usually happens
1762 * when the BIOS is buggy and provides us the wrong
1763 * device id for the IOAPIC in the system.
1764 */
dfbb6d47 1765 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
c2ff5cf5
JR		 1766 }
1767
1768 if (!ret)
dfbb6d47 1769 pr_err("AMD-Vi: Disabling interrupt remapping\n");
c2ff5cf5
JR		 1770
1771 return ret;
eb1eb7ae
JR		 1772}
1773
d04e0ba3
JR		 1774static void __init free_dma_resources(void)
1775{
d04e0ba3
JR		 1776 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1777 get_order(MAX_DOMAIN_ID/8));
1778
1779 free_unity_maps();
1780}
1781
b65233a9 1782/*
8704a1ba
JR		 1783 * This is the hardware init function for AMD IOMMU in the system.
1784 * This function is called either from amd_iommu_init or from the interrupt
1785 * remapping setup code.
b65233a9
JR		 1786 *
1787 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1788 * three times:
1789 *
1790 * 1 pass) Find the highest PCI device id the driver has to handle.
1791 * Upon this information the size of the data structures is
1792 * determined that needs to be allocated.
1793 *
1794 * 2 pass) Initialize the data structures just allocated with the
1795 * information in the ACPI table about available AMD IOMMUs
1796 * in the system. It also maps the PCI devices in the
1797 * system to specific IOMMUs
1798 *
1799 * 3 pass) After the basic data structures are allocated and
1800 * initialized we update them with information about memory
1801 * remapping requirements parsed out of the ACPI table in
1802 * this last pass.
1803 *
8704a1ba
JR		 1804 * After everything is set up the IOMMUs are enabled and the necessary
1805 * hotplug and suspend notifiers are registered.
b65233a9 1806 */
643511b3 1807static int __init early_amd_iommu_init(void)
fe74c9cf 1808{
02f3b3f5
JR		 1809 struct acpi_table_header *ivrs_base;
1810 acpi_size ivrs_size;
1811 acpi_status status;
fe74c9cf
JR		 1812 int i, ret = 0;
1813
643511b3 1814 if (!amd_iommu_detected)
8704a1ba
JR		 1815 return -ENODEV;
1816
02f3b3f5
JR		 1817 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1818 if (status == AE_NOT_FOUND)
1819 return -ENODEV;
1820 else if (ACPI_FAILURE(status)) {
1821 const char *err = acpi_format_exception(status);
1822 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1823 return -EINVAL;
1824 }
1825
fe74c9cf
JR		 1826 /*
1827 * First parse ACPI tables to find the largest Bus/Dev/Func
1828 * we need to handle. Upon this information the shared data
1829 * structures for the IOMMUs in the system will be allocated
1830 */
2c0ae172
JR		 1831 ret = find_last_devid_acpi(ivrs_base);
1832 if (ret)
3551a708
JR		 1833 goto out;
1834
c571484e
JR		 1835 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1836 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1837 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
fe74c9cf 1838
fe74c9cf 1839 /* Device table - directly used by all IOMMUs */
8704a1ba 1840 ret = -ENOMEM;
5dc8bff0 1841 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 1842 get_order(dev_table_size));
1843 if (amd_iommu_dev_table == NULL)
1844 goto out;
1845
1846 /*
1847 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1848 * IOMMU see for that device
1849 */
1850 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1851 get_order(alias_table_size));
1852 if (amd_iommu_alias_table == NULL)
2c0ae172 1853 goto out;
fe74c9cf
JR		 1854
1855 /* IOMMU rlookup table - find the IOMMU for a specific device */
83fd5cc6
JR		 1856 amd_iommu_rlookup_table = (void *)__get_free_pages(
1857 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 1858 get_order(rlookup_table_size));
1859 if (amd_iommu_rlookup_table == NULL)
2c0ae172 1860 goto out;
fe74c9cf 1861
5dc8bff0
JR		 1862 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1863 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 1864 get_order(MAX_DOMAIN_ID/8));
1865 if (amd_iommu_pd_alloc_bitmap == NULL)
2c0ae172 1866 goto out;
fe74c9cf
JR		 1867
1868 /*
5dc8bff0 1869 * let all alias entries point to itself
fe74c9cf 1870 */
3a61ec38 1871 for (i = 0; i <= amd_iommu_last_bdf; ++i)
fe74c9cf
JR		 1872 amd_iommu_alias_table[i] = i;
1873
fe74c9cf
JR		 1874 /*
1875 * never allocate domain 0 because its used as the non-allocated and
1876 * error value placeholder
1877 */
1878 amd_iommu_pd_alloc_bitmap[0] = 1;
1879
aeb26f55
JR		 1880 spin_lock_init(&amd_iommu_pd_lock);
1881
fe74c9cf
JR		 1882 /*
1883 * now the data structures are allocated and basically initialized
1884 * start the real acpi table scan
1885 */
02f3b3f5
JR		 1886 ret = init_iommu_all(ivrs_base);
1887 if (ret)
2c0ae172 1888 goto out;
fe74c9cf 1889
eb1eb7ae
JR		 1890 if (amd_iommu_irq_remap)
1891 amd_iommu_irq_remap = check_ioapic_information();
1892
05152a04
JR		 1893 if (amd_iommu_irq_remap) {
1894 /*
1895 * Interrupt remapping enabled, create kmem_cache for the
1896 * remapping tables.
1897 */
83ed9c13 1898 ret = -ENOMEM;
05152a04
JR		 1899 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1900 MAX_IRQS_PER_TABLE * sizeof(u32),
1901 IRQ_TABLE_ALIGNMENT,
1902 0, NULL);
1903 if (!amd_iommu_irq_cache)
1904 goto out;
0ea2c422
JR		 1905
1906 irq_lookup_table = (void *)__get_free_pages(
1907 GFP_KERNEL | __GFP_ZERO,
1908 get_order(rlookup_table_size));
1909 if (!irq_lookup_table)
1910 goto out;
05152a04
JR		 1911 }
1912
02f3b3f5
JR		 1913 ret = init_memory_definitions(ivrs_base);
1914 if (ret)
2c0ae172 1915 goto out;
3551a708 1916
eb1eb7ae
JR		 1917 /* init the device table */
1918 init_device_table();
1919
8704a1ba 1920out:
02f3b3f5
JR		 1921 /* Don't leak any ACPI memory */
1922 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1923 ivrs_base = NULL;
1924
643511b3
JR		 1925 return ret;
1926}
1927
ae295142 1928static int amd_iommu_enable_interrupts(void)
3d9761e7
JR		 1929{
1930 struct amd_iommu *iommu;
1931 int ret = 0;
1932
1933 for_each_iommu(iommu) {
1934 ret = iommu_init_msi(iommu);
1935 if (ret)
1936 goto out;
1937 }
1938
1939out:
1940 return ret;
1941}
1942
02f3b3f5
JR		 1943static bool detect_ivrs(void)
1944{
1945 struct acpi_table_header *ivrs_base;
1946 acpi_size ivrs_size;
1947 acpi_status status;
1948
1949 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1950 if (status == AE_NOT_FOUND)
1951 return false;
1952 else if (ACPI_FAILURE(status)) {
1953 const char *err = acpi_format_exception(status);
1954 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1955 return false;
1956 }
1957
1958 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1959
1adb7d31
JR		 1960 /* Make sure ACS will be enabled during PCI probe */
1961 pci_request_acs();
1962
02f3b3f5
JR		 1963 return true;
1964}
1965
2c0ae172 1966/****************************************************************************
8704a1ba 1967 *
2c0ae172
JR		 1968 * AMD IOMMU Initialization State Machine
1969 *
1970 ****************************************************************************/
1971
1972static int __init state_next(void)
8704a1ba
JR		 1973{
1974 int ret = 0;
1975
2c0ae172
JR		 1976 switch (init_state) {
1977 case IOMMU_START_STATE:
1978 if (!detect_ivrs()) {
1979 init_state = IOMMU_NOT_FOUND;
1980 ret = -ENODEV;
1981 } else {
1982 init_state = IOMMU_IVRS_DETECTED;
1983 }
1984 break;
1985 case IOMMU_IVRS_DETECTED:
1986 ret = early_amd_iommu_init();
1987 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
1988 break;
1989 case IOMMU_ACPI_FINISHED:
1990 early_enable_iommus();
1991 register_syscore_ops(&amd_iommu_syscore_ops);
1992 x86_platform.iommu_shutdown = disable_iommus;
1993 init_state = IOMMU_ENABLED;
1994 break;
1995 case IOMMU_ENABLED:
1996 ret = amd_iommu_init_pci();
1997 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
1998 enable_iommus_v2();
1999 break;
2000 case IOMMU_PCI_INIT:
2001 ret = amd_iommu_enable_interrupts();
2002 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2003 break;
2004 case IOMMU_INTERRUPTS_EN:
1e6a7b04 2005 ret = amd_iommu_init_dma_ops();
2c0ae172
JR		 2006 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2007 break;
2008 case IOMMU_DMA_OPS:
2009 init_state = IOMMU_INITIALIZED;
2010 break;
2011 case IOMMU_INITIALIZED:
2012 /* Nothing to do */
2013 break;
2014 case IOMMU_NOT_FOUND:
2015 case IOMMU_INIT_ERROR:
2016 /* Error states => do nothing */
2017 ret = -EINVAL;
2018 break;
2019 default:
2020 /* Unknown state */
2021 BUG();
2022 }
3d9761e7 2023
2c0ae172
JR		 2024 return ret;
2025}
7441e9cb 2026
2c0ae172
JR		 2027static int __init iommu_go_to_state(enum iommu_init_state state)
2028{
2029 int ret = 0;
f5325094 2030
2c0ae172
JR		 2031 while (init_state != state) {
2032 ret = state_next();
2033 if (init_state == IOMMU_NOT_FOUND ||
2034 init_state == IOMMU_INIT_ERROR)
2035 break;
2036 }
f2f12b6f 2037
fe74c9cf 2038 return ret;
2c0ae172 2039}
fe74c9cf 2040
6b474b82
JR		 2041#ifdef CONFIG_IRQ_REMAP
2042int __init amd_iommu_prepare(void)
2043{
3f4cb7c0
TG		 2044 int ret;
2045
7fa1c842 2046 amd_iommu_irq_remap = true;
84d07793 2047
3f4cb7c0
TG		 2048 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2049 if (ret)
2050 return ret;
2051 return amd_iommu_irq_remap ? 0 : -ENODEV;
6b474b82 2052}
d7f07769 2053
6b474b82
JR		 2054int __init amd_iommu_enable(void)
2055{
2056 int ret;
2057
2058 ret = iommu_go_to_state(IOMMU_ENABLED);
2059 if (ret)
2060 return ret;
d7f07769 2061
6b474b82 2062 irq_remapping_enabled = 1;
d7f07769 2063
6b474b82
JR		 2064 return 0;
2065}
2066
2067void amd_iommu_disable(void)
2068{
2069 amd_iommu_suspend();
2070}
2071
2072int amd_iommu_reenable(int mode)
2073{
2074 amd_iommu_resume();
2075
2076 return 0;
2077}
d7f07769 2078
6b474b82
JR		 2079int __init amd_iommu_enable_faulting(void)
2080{
2081 /* We enable MSI later when PCI is initialized */
2082 return 0;
2083}
2084#endif
d7f07769 2085
2c0ae172
JR		 2086/*
2087 * This is the core init function for AMD IOMMU hardware in the system.
2088 * This function is called from the generic x86 DMA layer initialization
2089 * code.
2090 */
2091static int __init amd_iommu_init(void)
2092{
2093 int ret;
2094
2095 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2096 if (ret) {
d04e0ba3
JR		 2097 free_dma_resources();
2098 if (!irq_remapping_enabled) {
2099 disable_iommus();
2100 free_on_init_error();
2101 } else {
2102 struct amd_iommu *iommu;
2103
2104 uninit_device_table_dma();
2105 for_each_iommu(iommu)
2106 iommu_flush_all_caches(iommu);
2107 }
2c0ae172
JR		 2108 }
2109
2110 return ret;
fe74c9cf
JR		 2111}
2112
b65233a9
JR		 2113/****************************************************************************
2114 *
2115 * Early detect code. This code runs at IOMMU detection time in the DMA
2116 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2117 * IOMMUs
2118 *
2119 ****************************************************************************/
480125ba 2120int __init amd_iommu_detect(void)
ae7877de 2121{
2c0ae172 2122 int ret;
02f3b3f5 2123
75f1cdf1 2124 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
480125ba 2125 return -ENODEV;
ae7877de 2126
a5235725 2127 if (amd_iommu_disabled)
480125ba 2128 return -ENODEV;
a5235725 2129
2c0ae172
JR		 2130 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2131 if (ret)
2132 return ret;
11bd04f6 2133
02f3b3f5
JR		 2134 amd_iommu_detected = true;
2135 iommu_detected = 1;
2136 x86_init.iommu.iommu_init = amd_iommu_init;
2137
4781bc42 2138 return 1;
ae7877de
JR		 2139}
2140
b65233a9
JR		 2141/****************************************************************************
2142 *
2143 * Parsing functions for the AMD IOMMU specific kernel command line
2144 * options.
2145 *
2146 ****************************************************************************/
2147
fefda117
JR		 2148static int __init parse_amd_iommu_dump(char *str)
2149{
2150 amd_iommu_dump = true;
2151
2152 return 1;
2153}
2154
918ad6c5
JR		 2155static int __init parse_amd_iommu_options(char *str)
2156{
2157 for (; *str; ++str) {
695b5676 2158 if (strncmp(str, "fullflush", 9) == 0)
afa9fdc2 2159 amd_iommu_unmap_flush = true;
a5235725
JR		 2160 if (strncmp(str, "off", 3) == 0)
2161 amd_iommu_disabled = true;
5abcdba4
JR		 2162 if (strncmp(str, "force_isolation", 15) == 0)
2163 amd_iommu_force_isolation = true;
918ad6c5
JR		 2164 }
2165
2166 return 1;
2167}
2168
440e8998
JR		 2169static int __init parse_ivrs_ioapic(char *str)
2170{
2171 unsigned int bus, dev, fn;
2172 int ret, id, i;
2173 u16 devid;
2174
2175 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2176
2177 if (ret != 4) {
2178 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2179 return 1;
2180 }
2181
2182 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2183 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2184 str);
2185 return 1;
2186 }
2187
2188 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2189
dfbb6d47 2190 cmdline_maps = true;
440e8998
JR		 2191 i = early_ioapic_map_size++;
2192 early_ioapic_map[i].id = id;
2193 early_ioapic_map[i].devid = devid;
2194 early_ioapic_map[i].cmd_line = true;
2195
2196 return 1;
2197}
2198
2199static int __init parse_ivrs_hpet(char *str)
2200{
2201 unsigned int bus, dev, fn;
2202 int ret, id, i;
2203 u16 devid;
2204
2205 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2206
2207 if (ret != 4) {
2208 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2209 return 1;
2210 }
2211
2212 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2213 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2214 str);
2215 return 1;
2216 }
2217
2218 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2219
dfbb6d47 2220 cmdline_maps = true;
440e8998
JR		 2221 i = early_hpet_map_size++;
2222 early_hpet_map[i].id = id;
2223 early_hpet_map[i].devid = devid;
2224 early_hpet_map[i].cmd_line = true;
2225
2226 return 1;
2227}
2228
2229__setup("amd_iommu_dump", parse_amd_iommu_dump);
2230__setup("amd_iommu=", parse_amd_iommu_options);
2231__setup("ivrs_ioapic", parse_ivrs_ioapic);
2232__setup("ivrs_hpet", parse_ivrs_hpet);
22e6daf4
KRW		 2233
2234IOMMU_INIT_FINISH(amd_iommu_detect,
2235 gart_iommu_hole_init,
98f1ad25
JR		 2236 NULL,
2237 NULL);
400a28a0
JR		 2238
2239bool amd_iommu_v2_supported(void)
2240{
2241 return amd_iommu_v2_present;
2242}
2243EXPORT_SYMBOL(amd_iommu_v2_supported);
30861ddc
SK		 2244
2245/****************************************************************************
2246 *
2247 * IOMMU EFR Performance Counter support functionality. This code allows
2248 * access to the IOMMU PC functionality.
2249 *
2250 ****************************************************************************/
2251
2252u8 amd_iommu_pc_get_max_banks(u16 devid)
2253{
2254 struct amd_iommu *iommu;
2255 u8 ret = 0;
2256
2257 /* locate the iommu governing the devid */
2258 iommu = amd_iommu_rlookup_table[devid];
2259 if (iommu)
2260 ret = iommu->max_banks;
2261
2262 return ret;
2263}
2264EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2265
2266bool amd_iommu_pc_supported(void)
2267{
2268 return amd_iommu_pc_present;
2269}
2270EXPORT_SYMBOL(amd_iommu_pc_supported);
2271
2272u8 amd_iommu_pc_get_max_counters(u16 devid)
2273{
2274 struct amd_iommu *iommu;
2275 u8 ret = 0;
2276
2277 /* locate the iommu governing the devid */
2278 iommu = amd_iommu_rlookup_table[devid];
2279 if (iommu)
2280 ret = iommu->max_counters;
2281
2282 return ret;
2283}
2284EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2285
2286int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2287 u64 *value, bool is_write)
2288{
2289 struct amd_iommu *iommu;
2290 u32 offset;
2291 u32 max_offset_lim;
2292
2293 /* Make sure the IOMMU PC resource is available */
2294 if (!amd_iommu_pc_present)
2295 return -ENODEV;
2296
2297 /* Locate the iommu associated with the device ID */
2298 iommu = amd_iommu_rlookup_table[devid];
2299
2300 /* Check for valid iommu and pc register indexing */
2301 if (WARN_ON((iommu == NULL) || (fxn > 0x28) || (fxn & 7)))
2302 return -ENODEV;
2303
2304 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2305
2306 /* Limit the offset to the hw defined mmio region aperture */
2307 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2308 (iommu->max_counters << 8) | 0x28);
2309 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2310 (offset > max_offset_lim))
2311 return -EINVAL;
2312
2313 if (is_write) {
2314 writel((u32)*value, iommu->mmio_base + offset);
2315 writel((*value >> 32), iommu->mmio_base + offset + 4);
2316 } else {
2317 *value = readl(iommu->mmio_base + offset + 4);
2318 *value <<= 32;
2319 *value = readl(iommu->mmio_base + offset);
2320 }
2321
2322 return 0;
2323}
2324EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
Linux 6.x block layer and io_uring tree(s)