Commit | Line | Data |
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f6e2e6b6 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
f6e2e6b6 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
f6e2e6b6 | 22 | #include <linux/list.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
f3c6ea1b | 24 | #include <linux/syscore_ops.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
403f81d8 | 27 | #include <linux/amd-iommu.h> |
400a28a0 | 28 | #include <linux/export.h> |
02f3b3f5 | 29 | #include <acpi/acpi.h> |
f6e2e6b6 | 30 | #include <asm/pci-direct.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
ea1b0d39 | 33 | #include <asm/x86_init.h> |
22e6daf4 | 34 | #include <asm/iommu_table.h> |
eb1eb7ae | 35 | #include <asm/io_apic.h> |
6b474b82 | 36 | #include <asm/irq_remapping.h> |
403f81d8 JR |
37 | |
38 | #include "amd_iommu_proto.h" | |
39 | #include "amd_iommu_types.h" | |
05152a04 | 40 | #include "irq_remapping.h" |
403f81d8 | 41 | |
f6e2e6b6 JR |
42 | /* |
43 | * definitions for the ACPI scanning code | |
44 | */ | |
f6e2e6b6 | 45 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
46 | |
47 | #define ACPI_IVHD_TYPE 0x10 | |
48 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
49 | #define ACPI_IVMD_TYPE 0x21 | |
50 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
51 | ||
52 | #define IVHD_DEV_ALL 0x01 | |
53 | #define IVHD_DEV_SELECT 0x02 | |
54 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
55 | #define IVHD_DEV_RANGE_END 0x04 | |
56 | #define IVHD_DEV_ALIAS 0x42 | |
57 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
58 | #define IVHD_DEV_EXT_SELECT 0x46 | |
59 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
6efed63b JR |
60 | #define IVHD_DEV_SPECIAL 0x48 |
61 | ||
62 | #define IVHD_SPECIAL_IOAPIC 1 | |
63 | #define IVHD_SPECIAL_HPET 2 | |
f6e2e6b6 | 64 | |
6da7342f JR |
65 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
66 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
67 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
68 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
69 | |
70 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
71 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
72 | ||
73 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
74 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
75 | #define ACPI_DEVFLAG_NMI 0x04 | |
76 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
77 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
78 | #define ACPI_DEVFLAG_LINT0 0x40 | |
79 | #define ACPI_DEVFLAG_LINT1 0x80 | |
80 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
81 | ||
b65233a9 JR |
82 | /* |
83 | * ACPI table definitions | |
84 | * | |
85 | * These data structures are laid over the table to parse the important values | |
86 | * out of it. | |
87 | */ | |
88 | ||
89 | /* | |
90 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
91 | * or more ivhd_entrys. | |
92 | */ | |
f6e2e6b6 JR |
93 | struct ivhd_header { |
94 | u8 type; | |
95 | u8 flags; | |
96 | u16 length; | |
97 | u16 devid; | |
98 | u16 cap_ptr; | |
99 | u64 mmio_phys; | |
100 | u16 pci_seg; | |
101 | u16 info; | |
102 | u32 reserved; | |
103 | } __attribute__((packed)); | |
104 | ||
b65233a9 JR |
105 | /* |
106 | * A device entry describing which devices a specific IOMMU translates and | |
107 | * which requestor ids they use. | |
108 | */ | |
f6e2e6b6 JR |
109 | struct ivhd_entry { |
110 | u8 type; | |
111 | u16 devid; | |
112 | u8 flags; | |
113 | u32 ext; | |
114 | } __attribute__((packed)); | |
115 | ||
b65233a9 JR |
116 | /* |
117 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
118 | * ranges for devices and regions that should be unity mapped. | |
119 | */ | |
f6e2e6b6 JR |
120 | struct ivmd_header { |
121 | u8 type; | |
122 | u8 flags; | |
123 | u16 length; | |
124 | u16 devid; | |
125 | u16 aux; | |
126 | u64 resv; | |
127 | u64 range_start; | |
128 | u64 range_length; | |
129 | } __attribute__((packed)); | |
130 | ||
fefda117 | 131 | bool amd_iommu_dump; |
05152a04 | 132 | bool amd_iommu_irq_remap __read_mostly; |
fefda117 | 133 | |
02f3b3f5 | 134 | static bool amd_iommu_detected; |
a5235725 | 135 | static bool __initdata amd_iommu_disabled; |
c1cbebee | 136 | |
b65233a9 JR |
137 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
138 | to handle */ | |
2e22847f | 139 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 140 | we find in ACPI */ |
3775d481 | 141 | u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 142 | |
2e22847f | 143 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 144 | system */ |
928abd25 | 145 | |
bb52777e JR |
146 | /* Array to assign indices to IOMMUs*/ |
147 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
148 | int amd_iommus_present; | |
149 | ||
318afd41 JR |
150 | /* IOMMUs have a non-present cache? */ |
151 | bool amd_iommu_np_cache __read_mostly; | |
60f723b4 | 152 | bool amd_iommu_iotlb_sup __read_mostly = true; |
318afd41 | 153 | |
62f71abb JR |
154 | u32 amd_iommu_max_pasids __read_mostly = ~0; |
155 | ||
400a28a0 JR |
156 | bool amd_iommu_v2_present __read_mostly; |
157 | ||
5abcdba4 JR |
158 | bool amd_iommu_force_isolation __read_mostly; |
159 | ||
aeb26f55 JR |
160 | /* |
161 | * List of protection domains - used during resume | |
162 | */ | |
163 | LIST_HEAD(amd_iommu_pd_list); | |
164 | spinlock_t amd_iommu_pd_lock; | |
165 | ||
b65233a9 JR |
166 | /* |
167 | * Pointer to the device table which is shared by all AMD IOMMUs | |
168 | * it is indexed by the PCI device id or the HT unit id and contains | |
169 | * information about the domain the device belongs to as well as the | |
170 | * page table root pointer. | |
171 | */ | |
928abd25 | 172 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
173 | |
174 | /* | |
175 | * The alias table is a driver specific data structure which contains the | |
176 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
177 | * More than one device can share the same requestor id. | |
178 | */ | |
928abd25 | 179 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
180 | |
181 | /* | |
182 | * The rlookup table is used to find the IOMMU which is responsible | |
183 | * for a specific device. It is also indexed by the PCI device id. | |
184 | */ | |
928abd25 | 185 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 | 186 | |
b65233a9 | 187 | /* |
0ea2c422 JR |
188 | * This table is used to find the irq remapping table for a given device id |
189 | * quickly. | |
190 | */ | |
191 | struct irq_remap_table **irq_lookup_table; | |
192 | ||
b65233a9 | 193 | /* |
df805abb | 194 | * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap |
b65233a9 JR |
195 | * to know which ones are already in use. |
196 | */ | |
928abd25 JR |
197 | unsigned long *amd_iommu_pd_alloc_bitmap; |
198 | ||
b65233a9 JR |
199 | static u32 dev_table_size; /* size of the device table */ |
200 | static u32 alias_table_size; /* size of the alias table */ | |
201 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 202 | |
2c0ae172 JR |
203 | enum iommu_init_state { |
204 | IOMMU_START_STATE, | |
205 | IOMMU_IVRS_DETECTED, | |
206 | IOMMU_ACPI_FINISHED, | |
207 | IOMMU_ENABLED, | |
208 | IOMMU_PCI_INIT, | |
209 | IOMMU_INTERRUPTS_EN, | |
210 | IOMMU_DMA_OPS, | |
211 | IOMMU_INITIALIZED, | |
212 | IOMMU_NOT_FOUND, | |
213 | IOMMU_INIT_ERROR, | |
214 | }; | |
215 | ||
235dacbc JR |
216 | /* Early ioapic and hpet maps from kernel command line */ |
217 | #define EARLY_MAP_SIZE 4 | |
218 | static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; | |
219 | static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; | |
220 | static int __initdata early_ioapic_map_size; | |
221 | static int __initdata early_hpet_map_size; | |
222 | ||
2c0ae172 JR |
223 | static enum iommu_init_state init_state = IOMMU_START_STATE; |
224 | ||
ae295142 | 225 | static int amd_iommu_enable_interrupts(void); |
2c0ae172 | 226 | static int __init iommu_go_to_state(enum iommu_init_state state); |
3d9761e7 | 227 | |
208ec8c9 JR |
228 | static inline void update_last_devid(u16 devid) |
229 | { | |
230 | if (devid > amd_iommu_last_bdf) | |
231 | amd_iommu_last_bdf = devid; | |
232 | } | |
233 | ||
c571484e JR |
234 | static inline unsigned long tbl_size(int entry_size) |
235 | { | |
236 | unsigned shift = PAGE_SHIFT + | |
421f909c | 237 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
238 | |
239 | return 1UL << shift; | |
240 | } | |
241 | ||
5bcd757f MG |
242 | /* Access to l1 and l2 indexed register spaces */ |
243 | ||
244 | static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) | |
245 | { | |
246 | u32 val; | |
247 | ||
248 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
249 | pci_read_config_dword(iommu->dev, 0xfc, &val); | |
250 | return val; | |
251 | } | |
252 | ||
253 | static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) | |
254 | { | |
255 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); | |
256 | pci_write_config_dword(iommu->dev, 0xfc, val); | |
257 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
258 | } | |
259 | ||
260 | static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) | |
261 | { | |
262 | u32 val; | |
263 | ||
264 | pci_write_config_dword(iommu->dev, 0xf0, address); | |
265 | pci_read_config_dword(iommu->dev, 0xf4, &val); | |
266 | return val; | |
267 | } | |
268 | ||
269 | static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) | |
270 | { | |
271 | pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); | |
272 | pci_write_config_dword(iommu->dev, 0xf4, val); | |
273 | } | |
274 | ||
b65233a9 JR |
275 | /**************************************************************************** |
276 | * | |
277 | * AMD IOMMU MMIO register space handling functions | |
278 | * | |
279 | * These functions are used to program the IOMMU device registers in | |
280 | * MMIO space required for that driver. | |
281 | * | |
282 | ****************************************************************************/ | |
3e8064ba | 283 | |
b65233a9 JR |
284 | /* |
285 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
286 | * exclusion range are passed through untranslated | |
287 | */ | |
05f92db9 | 288 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
289 | { |
290 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
291 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
292 | u64 entry; | |
293 | ||
294 | if (!iommu->exclusion_start) | |
295 | return; | |
296 | ||
297 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
298 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
299 | &entry, sizeof(entry)); | |
300 | ||
301 | entry = limit; | |
302 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
303 | &entry, sizeof(entry)); | |
304 | } | |
305 | ||
b65233a9 | 306 | /* Programs the physical address of the device table into the IOMMU hardware */ |
6b7f000e | 307 | static void iommu_set_device_table(struct amd_iommu *iommu) |
b2026aa2 | 308 | { |
f609891f | 309 | u64 entry; |
b2026aa2 JR |
310 | |
311 | BUG_ON(iommu->mmio_base == NULL); | |
312 | ||
313 | entry = virt_to_phys(amd_iommu_dev_table); | |
314 | entry |= (dev_table_size >> 12) - 1; | |
315 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
316 | &entry, sizeof(entry)); | |
317 | } | |
318 | ||
b65233a9 | 319 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 320 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
321 | { |
322 | u32 ctrl; | |
323 | ||
324 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
325 | ctrl |= (1 << bit); | |
326 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
327 | } | |
328 | ||
ca020711 | 329 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
330 | { |
331 | u32 ctrl; | |
332 | ||
199d0d50 | 333 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
334 | ctrl &= ~(1 << bit); |
335 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
336 | } | |
337 | ||
1456e9d2 JR |
338 | static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) |
339 | { | |
340 | u32 ctrl; | |
341 | ||
342 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
343 | ctrl &= ~CTRL_INV_TO_MASK; | |
344 | ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; | |
345 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
346 | } | |
347 | ||
b65233a9 | 348 | /* Function to enable the hardware */ |
05f92db9 | 349 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 350 | { |
b2026aa2 | 351 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); |
b2026aa2 JR |
352 | } |
353 | ||
92ac4320 | 354 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 355 | { |
a8c485bb CW |
356 | /* Disable command buffer */ |
357 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
358 | ||
359 | /* Disable event logging and event interrupts */ | |
360 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
361 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
362 | ||
363 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 364 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
365 | } |
366 | ||
b65233a9 JR |
367 | /* |
368 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
369 | * the system has one. | |
370 | */ | |
98f1ad25 | 371 | static u8 __iomem * __init iommu_map_mmio_space(u64 address) |
6c56747b | 372 | { |
e82752d8 JR |
373 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) { |
374 | pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n", | |
375 | address); | |
376 | pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n"); | |
6c56747b | 377 | return NULL; |
e82752d8 | 378 | } |
6c56747b | 379 | |
98f1ad25 | 380 | return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH); |
6c56747b JR |
381 | } |
382 | ||
383 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
384 | { | |
385 | if (iommu->mmio_base) | |
386 | iounmap(iommu->mmio_base); | |
387 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
388 | } | |
389 | ||
b65233a9 JR |
390 | /**************************************************************************** |
391 | * | |
392 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
393 | * parsing. In this pass we try to find out the highest device id this | |
394 | * code has to handle. Upon this information the size of the shared data | |
395 | * structures is determined later. | |
396 | * | |
397 | ****************************************************************************/ | |
398 | ||
b514e555 JR |
399 | /* |
400 | * This function calculates the length of a given IVHD entry | |
401 | */ | |
402 | static inline int ivhd_entry_length(u8 *ivhd) | |
403 | { | |
404 | return 0x04 << (*ivhd >> 6); | |
405 | } | |
406 | ||
b65233a9 JR |
407 | /* |
408 | * This function reads the last device id the IOMMU has to handle from the PCI | |
409 | * capability header for this IOMMU | |
410 | */ | |
3e8064ba JR |
411 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
412 | { | |
413 | u32 cap; | |
414 | ||
415 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 416 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
417 | |
418 | return 0; | |
419 | } | |
420 | ||
b65233a9 JR |
421 | /* |
422 | * After reading the highest device id from the IOMMU PCI capability header | |
423 | * this function looks if there is a higher device id defined in the ACPI table | |
424 | */ | |
3e8064ba JR |
425 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
426 | { | |
427 | u8 *p = (void *)h, *end = (void *)h; | |
428 | struct ivhd_entry *dev; | |
429 | ||
430 | p += sizeof(*h); | |
431 | end += h->length; | |
432 | ||
433 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
434 | PCI_SLOT(h->devid), | |
435 | PCI_FUNC(h->devid), | |
436 | h->cap_ptr); | |
437 | ||
438 | while (p < end) { | |
439 | dev = (struct ivhd_entry *)p; | |
440 | switch (dev->type) { | |
441 | case IVHD_DEV_SELECT: | |
442 | case IVHD_DEV_RANGE_END: | |
443 | case IVHD_DEV_ALIAS: | |
444 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 445 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 446 | update_last_devid(dev->devid); |
3e8064ba JR |
447 | break; |
448 | default: | |
449 | break; | |
450 | } | |
b514e555 | 451 | p += ivhd_entry_length(p); |
3e8064ba JR |
452 | } |
453 | ||
454 | WARN_ON(p != end); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
b65233a9 JR |
459 | /* |
460 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
461 | * id which we need to handle. This is the first of three functions which parse | |
462 | * the ACPI table. So we check the checksum here. | |
463 | */ | |
3e8064ba JR |
464 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
465 | { | |
466 | int i; | |
467 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
468 | struct ivhd_header *h; | |
469 | ||
470 | /* | |
471 | * Validate checksum here so we don't need to do it when | |
472 | * we actually parse the table | |
473 | */ | |
474 | for (i = 0; i < table->length; ++i) | |
475 | checksum += p[i]; | |
02f3b3f5 | 476 | if (checksum != 0) |
3e8064ba | 477 | /* ACPI table corrupt */ |
02f3b3f5 | 478 | return -ENODEV; |
3e8064ba JR |
479 | |
480 | p += IVRS_HEADER_LENGTH; | |
481 | ||
482 | end += table->length; | |
483 | while (p < end) { | |
484 | h = (struct ivhd_header *)p; | |
485 | switch (h->type) { | |
486 | case ACPI_IVHD_TYPE: | |
487 | find_last_devid_from_ivhd(h); | |
488 | break; | |
489 | default: | |
490 | break; | |
491 | } | |
492 | p += h->length; | |
493 | } | |
494 | WARN_ON(p != end); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
b65233a9 JR |
499 | /**************************************************************************** |
500 | * | |
df805abb | 501 | * The following functions belong to the code path which parses the ACPI table |
b65233a9 JR |
502 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific |
503 | * data structures, initialize the device/alias/rlookup table and also | |
504 | * basically initialize the hardware. | |
505 | * | |
506 | ****************************************************************************/ | |
507 | ||
508 | /* | |
509 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
510 | * write commands to that buffer later and the IOMMU will execute them | |
511 | * asynchronously | |
512 | */ | |
b36ca91e JR |
513 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
514 | { | |
d0312b21 | 515 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 516 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
517 | |
518 | if (cmd_buf == NULL) | |
519 | return NULL; | |
520 | ||
549c90dc | 521 | iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED; |
b36ca91e | 522 | |
58492e12 JR |
523 | return cmd_buf; |
524 | } | |
525 | ||
93f1cc67 JR |
526 | /* |
527 | * This function resets the command buffer if the IOMMU stopped fetching | |
528 | * commands from it. | |
529 | */ | |
530 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
531 | { | |
532 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
533 | ||
534 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
535 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
536 | ||
537 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
538 | } | |
539 | ||
58492e12 JR |
540 | /* |
541 | * This function writes the command buffer address to the hardware and | |
542 | * enables it. | |
543 | */ | |
544 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
545 | { | |
546 | u64 entry; | |
547 | ||
548 | BUG_ON(iommu->cmd_buf == NULL); | |
549 | ||
550 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 551 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 552 | |
b36ca91e | 553 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 554 | &entry, sizeof(entry)); |
b36ca91e | 555 | |
93f1cc67 | 556 | amd_iommu_reset_cmd_buffer(iommu); |
549c90dc | 557 | iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED); |
b36ca91e JR |
558 | } |
559 | ||
560 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
561 | { | |
23c1713f | 562 | free_pages((unsigned long)iommu->cmd_buf, |
549c90dc | 563 | get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED))); |
b36ca91e JR |
564 | } |
565 | ||
335503e5 JR |
566 | /* allocates the memory where the IOMMU will log its events to */ |
567 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
568 | { | |
335503e5 JR |
569 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
570 | get_order(EVT_BUFFER_SIZE)); | |
571 | ||
572 | if (iommu->evt_buf == NULL) | |
573 | return NULL; | |
574 | ||
1bc6f838 JR |
575 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
576 | ||
58492e12 JR |
577 | return iommu->evt_buf; |
578 | } | |
579 | ||
580 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
581 | { | |
582 | u64 entry; | |
583 | ||
584 | BUG_ON(iommu->evt_buf == NULL); | |
585 | ||
335503e5 | 586 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 587 | |
335503e5 JR |
588 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
589 | &entry, sizeof(entry)); | |
590 | ||
09067207 JR |
591 | /* set head and tail to zero manually */ |
592 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
593 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
594 | ||
58492e12 | 595 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
596 | } |
597 | ||
598 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
599 | { | |
600 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
601 | } | |
602 | ||
1a29ac01 JR |
603 | /* allocates the memory where the IOMMU will log its events to */ |
604 | static u8 * __init alloc_ppr_log(struct amd_iommu *iommu) | |
605 | { | |
606 | iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
607 | get_order(PPR_LOG_SIZE)); | |
608 | ||
609 | if (iommu->ppr_log == NULL) | |
610 | return NULL; | |
611 | ||
612 | return iommu->ppr_log; | |
613 | } | |
614 | ||
615 | static void iommu_enable_ppr_log(struct amd_iommu *iommu) | |
616 | { | |
617 | u64 entry; | |
618 | ||
619 | if (iommu->ppr_log == NULL) | |
620 | return; | |
621 | ||
622 | entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; | |
623 | ||
624 | memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, | |
625 | &entry, sizeof(entry)); | |
626 | ||
627 | /* set head and tail to zero manually */ | |
628 | writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
629 | writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
630 | ||
631 | iommu_feature_enable(iommu, CONTROL_PPFLOG_EN); | |
632 | iommu_feature_enable(iommu, CONTROL_PPR_EN); | |
633 | } | |
634 | ||
635 | static void __init free_ppr_log(struct amd_iommu *iommu) | |
636 | { | |
637 | if (iommu->ppr_log == NULL) | |
638 | return; | |
639 | ||
640 | free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); | |
641 | } | |
642 | ||
cbc33a90 JR |
643 | static void iommu_enable_gt(struct amd_iommu *iommu) |
644 | { | |
645 | if (!iommu_feature(iommu, FEATURE_GT)) | |
646 | return; | |
647 | ||
648 | iommu_feature_enable(iommu, CONTROL_GT_EN); | |
649 | } | |
650 | ||
b65233a9 | 651 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
652 | static void set_dev_entry_bit(u16 devid, u8 bit) |
653 | { | |
ee6c2868 JR |
654 | int i = (bit >> 6) & 0x03; |
655 | int _bit = bit & 0x3f; | |
3566b778 | 656 | |
ee6c2868 | 657 | amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); |
3566b778 JR |
658 | } |
659 | ||
c5cca146 JR |
660 | static int get_dev_entry_bit(u16 devid, u8 bit) |
661 | { | |
ee6c2868 JR |
662 | int i = (bit >> 6) & 0x03; |
663 | int _bit = bit & 0x3f; | |
c5cca146 | 664 | |
ee6c2868 | 665 | return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; |
c5cca146 JR |
666 | } |
667 | ||
668 | ||
669 | void amd_iommu_apply_erratum_63(u16 devid) | |
670 | { | |
671 | int sysmgt; | |
672 | ||
673 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
674 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
675 | ||
676 | if (sysmgt == 0x01) | |
677 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
678 | } | |
679 | ||
5ff4789d JR |
680 | /* Writes the specific IOMMU for a device into the rlookup table */ |
681 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
682 | { | |
683 | amd_iommu_rlookup_table[devid] = iommu; | |
684 | } | |
685 | ||
b65233a9 JR |
686 | /* |
687 | * This function takes the device specific flags read from the ACPI | |
688 | * table and sets up the device table entry with that information | |
689 | */ | |
5ff4789d JR |
690 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
691 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
692 | { |
693 | if (flags & ACPI_DEVFLAG_INITPASS) | |
694 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
695 | if (flags & ACPI_DEVFLAG_EXTINT) | |
696 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
697 | if (flags & ACPI_DEVFLAG_NMI) | |
698 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
699 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
700 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
701 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
702 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
703 | if (flags & ACPI_DEVFLAG_LINT0) | |
704 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
705 | if (flags & ACPI_DEVFLAG_LINT1) | |
706 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 707 | |
c5cca146 JR |
708 | amd_iommu_apply_erratum_63(devid); |
709 | ||
5ff4789d | 710 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
711 | } |
712 | ||
31cff67f | 713 | static int __init add_special_device(u8 type, u8 id, u16 devid, bool cmd_line) |
6efed63b JR |
714 | { |
715 | struct devid_map *entry; | |
716 | struct list_head *list; | |
717 | ||
31cff67f JR |
718 | if (type == IVHD_SPECIAL_IOAPIC) |
719 | list = &ioapic_map; | |
720 | else if (type == IVHD_SPECIAL_HPET) | |
721 | list = &hpet_map; | |
722 | else | |
6efed63b JR |
723 | return -EINVAL; |
724 | ||
31cff67f JR |
725 | list_for_each_entry(entry, list, list) { |
726 | if (!(entry->id == id && entry->cmd_line)) | |
727 | continue; | |
728 | ||
729 | pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n", | |
730 | type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
6efed63b JR |
735 | entry = kzalloc(sizeof(*entry), GFP_KERNEL); |
736 | if (!entry) | |
737 | return -ENOMEM; | |
738 | ||
31cff67f JR |
739 | entry->id = id; |
740 | entry->devid = devid; | |
741 | entry->cmd_line = cmd_line; | |
6efed63b JR |
742 | |
743 | list_add_tail(&entry->list, list); | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
235dacbc JR |
748 | static int __init add_early_maps(void) |
749 | { | |
750 | int i, ret; | |
751 | ||
752 | for (i = 0; i < early_ioapic_map_size; ++i) { | |
753 | ret = add_special_device(IVHD_SPECIAL_IOAPIC, | |
754 | early_ioapic_map[i].id, | |
755 | early_ioapic_map[i].devid, | |
756 | early_ioapic_map[i].cmd_line); | |
757 | if (ret) | |
758 | return ret; | |
759 | } | |
760 | ||
761 | for (i = 0; i < early_hpet_map_size; ++i) { | |
762 | ret = add_special_device(IVHD_SPECIAL_HPET, | |
763 | early_hpet_map[i].id, | |
764 | early_hpet_map[i].devid, | |
765 | early_hpet_map[i].cmd_line); | |
766 | if (ret) | |
767 | return ret; | |
768 | } | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
b65233a9 | 773 | /* |
df805abb | 774 | * Reads the device exclusion range from ACPI and initializes the IOMMU with |
b65233a9 JR |
775 | * it |
776 | */ | |
3566b778 JR |
777 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
778 | { | |
779 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
780 | ||
781 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
782 | return; | |
783 | ||
784 | if (iommu) { | |
b65233a9 JR |
785 | /* |
786 | * We only can configure exclusion ranges per IOMMU, not | |
787 | * per device. But we can enable the exclusion range per | |
788 | * device. This is done here | |
789 | */ | |
3566b778 JR |
790 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
791 | iommu->exclusion_start = m->range_start; | |
792 | iommu->exclusion_length = m->range_length; | |
793 | } | |
794 | } | |
795 | ||
b65233a9 JR |
796 | /* |
797 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
798 | * initializes the hardware and our data structures with it. | |
799 | */ | |
6efed63b | 800 | static int __init init_iommu_from_acpi(struct amd_iommu *iommu, |
5d0c8e49 JR |
801 | struct ivhd_header *h) |
802 | { | |
803 | u8 *p = (u8 *)h; | |
804 | u8 *end = p, flags = 0; | |
0de66d5b JR |
805 | u16 devid = 0, devid_start = 0, devid_to = 0; |
806 | u32 dev_i, ext_flags = 0; | |
58a3bee5 | 807 | bool alias = false; |
5d0c8e49 | 808 | struct ivhd_entry *e; |
235dacbc JR |
809 | int ret; |
810 | ||
811 | ||
812 | ret = add_early_maps(); | |
813 | if (ret) | |
814 | return ret; | |
5d0c8e49 JR |
815 | |
816 | /* | |
e9bf5197 | 817 | * First save the recommended feature enable bits from ACPI |
5d0c8e49 | 818 | */ |
e9bf5197 | 819 | iommu->acpi_flags = h->flags; |
5d0c8e49 JR |
820 | |
821 | /* | |
822 | * Done. Now parse the device entries | |
823 | */ | |
824 | p += sizeof(struct ivhd_header); | |
825 | end += h->length; | |
826 | ||
42a698f4 | 827 | |
5d0c8e49 JR |
828 | while (p < end) { |
829 | e = (struct ivhd_entry *)p; | |
830 | switch (e->type) { | |
831 | case IVHD_DEV_ALL: | |
42a698f4 JR |
832 | |
833 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
834 | " last device %02x:%02x.%x flags: %02x\n", | |
835 | PCI_BUS(iommu->first_device), | |
836 | PCI_SLOT(iommu->first_device), | |
837 | PCI_FUNC(iommu->first_device), | |
838 | PCI_BUS(iommu->last_device), | |
839 | PCI_SLOT(iommu->last_device), | |
840 | PCI_FUNC(iommu->last_device), | |
841 | e->flags); | |
842 | ||
5d0c8e49 JR |
843 | for (dev_i = iommu->first_device; |
844 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
845 | set_dev_entry_from_acpi(iommu, dev_i, |
846 | e->flags, 0); | |
5d0c8e49 JR |
847 | break; |
848 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
849 | |
850 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
851 | "flags: %02x\n", | |
852 | PCI_BUS(e->devid), | |
853 | PCI_SLOT(e->devid), | |
854 | PCI_FUNC(e->devid), | |
855 | e->flags); | |
856 | ||
5d0c8e49 | 857 | devid = e->devid; |
5ff4789d | 858 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
859 | break; |
860 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
861 | |
862 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
863 | "devid: %02x:%02x.%x flags: %02x\n", | |
864 | PCI_BUS(e->devid), | |
865 | PCI_SLOT(e->devid), | |
866 | PCI_FUNC(e->devid), | |
867 | e->flags); | |
868 | ||
5d0c8e49 JR |
869 | devid_start = e->devid; |
870 | flags = e->flags; | |
871 | ext_flags = 0; | |
58a3bee5 | 872 | alias = false; |
5d0c8e49 JR |
873 | break; |
874 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
875 | |
876 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
877 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
878 | PCI_BUS(e->devid), | |
879 | PCI_SLOT(e->devid), | |
880 | PCI_FUNC(e->devid), | |
881 | e->flags, | |
882 | PCI_BUS(e->ext >> 8), | |
883 | PCI_SLOT(e->ext >> 8), | |
884 | PCI_FUNC(e->ext >> 8)); | |
885 | ||
5d0c8e49 JR |
886 | devid = e->devid; |
887 | devid_to = e->ext >> 8; | |
7a6a3a08 | 888 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 889 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
890 | amd_iommu_alias_table[devid] = devid_to; |
891 | break; | |
892 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
893 | |
894 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
895 | "devid: %02x:%02x.%x flags: %02x " | |
896 | "devid_to: %02x:%02x.%x\n", | |
897 | PCI_BUS(e->devid), | |
898 | PCI_SLOT(e->devid), | |
899 | PCI_FUNC(e->devid), | |
900 | e->flags, | |
901 | PCI_BUS(e->ext >> 8), | |
902 | PCI_SLOT(e->ext >> 8), | |
903 | PCI_FUNC(e->ext >> 8)); | |
904 | ||
5d0c8e49 JR |
905 | devid_start = e->devid; |
906 | flags = e->flags; | |
907 | devid_to = e->ext >> 8; | |
908 | ext_flags = 0; | |
58a3bee5 | 909 | alias = true; |
5d0c8e49 JR |
910 | break; |
911 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
912 | |
913 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
914 | "flags: %02x ext: %08x\n", | |
915 | PCI_BUS(e->devid), | |
916 | PCI_SLOT(e->devid), | |
917 | PCI_FUNC(e->devid), | |
918 | e->flags, e->ext); | |
919 | ||
5d0c8e49 | 920 | devid = e->devid; |
5ff4789d JR |
921 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
922 | e->ext); | |
5d0c8e49 JR |
923 | break; |
924 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
925 | |
926 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
927 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
928 | PCI_BUS(e->devid), | |
929 | PCI_SLOT(e->devid), | |
930 | PCI_FUNC(e->devid), | |
931 | e->flags, e->ext); | |
932 | ||
5d0c8e49 JR |
933 | devid_start = e->devid; |
934 | flags = e->flags; | |
935 | ext_flags = e->ext; | |
58a3bee5 | 936 | alias = false; |
5d0c8e49 JR |
937 | break; |
938 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
939 | |
940 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
941 | PCI_BUS(e->devid), | |
942 | PCI_SLOT(e->devid), | |
943 | PCI_FUNC(e->devid)); | |
944 | ||
5d0c8e49 JR |
945 | devid = e->devid; |
946 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 947 | if (alias) { |
5d0c8e49 | 948 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
949 | set_dev_entry_from_acpi(iommu, |
950 | devid_to, flags, ext_flags); | |
951 | } | |
952 | set_dev_entry_from_acpi(iommu, dev_i, | |
953 | flags, ext_flags); | |
5d0c8e49 JR |
954 | } |
955 | break; | |
6efed63b JR |
956 | case IVHD_DEV_SPECIAL: { |
957 | u8 handle, type; | |
958 | const char *var; | |
959 | u16 devid; | |
960 | int ret; | |
961 | ||
962 | handle = e->ext & 0xff; | |
963 | devid = (e->ext >> 8) & 0xffff; | |
964 | type = (e->ext >> 24) & 0xff; | |
965 | ||
966 | if (type == IVHD_SPECIAL_IOAPIC) | |
967 | var = "IOAPIC"; | |
968 | else if (type == IVHD_SPECIAL_HPET) | |
969 | var = "HPET"; | |
970 | else | |
971 | var = "UNKNOWN"; | |
972 | ||
973 | DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", | |
974 | var, (int)handle, | |
975 | PCI_BUS(devid), | |
976 | PCI_SLOT(devid), | |
977 | PCI_FUNC(devid)); | |
978 | ||
979 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); | |
31cff67f | 980 | ret = add_special_device(type, handle, devid, false); |
6efed63b JR |
981 | if (ret) |
982 | return ret; | |
983 | break; | |
984 | } | |
5d0c8e49 JR |
985 | default: |
986 | break; | |
987 | } | |
988 | ||
b514e555 | 989 | p += ivhd_entry_length(p); |
5d0c8e49 | 990 | } |
6efed63b JR |
991 | |
992 | return 0; | |
5d0c8e49 JR |
993 | } |
994 | ||
b65233a9 | 995 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
996 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
997 | { | |
0de66d5b | 998 | u32 i; |
5d0c8e49 JR |
999 | |
1000 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
1001 | set_iommu_for_device(iommu, i); | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
e47d402d JR |
1006 | static void __init free_iommu_one(struct amd_iommu *iommu) |
1007 | { | |
1008 | free_command_buffer(iommu); | |
335503e5 | 1009 | free_event_buffer(iommu); |
1a29ac01 | 1010 | free_ppr_log(iommu); |
e47d402d JR |
1011 | iommu_unmap_mmio_space(iommu); |
1012 | } | |
1013 | ||
1014 | static void __init free_iommu_all(void) | |
1015 | { | |
1016 | struct amd_iommu *iommu, *next; | |
1017 | ||
3bd22172 | 1018 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
1019 | list_del(&iommu->list); |
1020 | free_iommu_one(iommu); | |
1021 | kfree(iommu); | |
1022 | } | |
1023 | } | |
1024 | ||
318fe782 SS |
1025 | /* |
1026 | * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) | |
1027 | * Workaround: | |
1028 | * BIOS should disable L2B micellaneous clock gating by setting | |
1029 | * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b | |
1030 | */ | |
e2f1a3bd | 1031 | static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) |
318fe782 SS |
1032 | { |
1033 | u32 value; | |
1034 | ||
1035 | if ((boot_cpu_data.x86 != 0x15) || | |
1036 | (boot_cpu_data.x86_model < 0x10) || | |
1037 | (boot_cpu_data.x86_model > 0x1f)) | |
1038 | return; | |
1039 | ||
1040 | pci_write_config_dword(iommu->dev, 0xf0, 0x90); | |
1041 | pci_read_config_dword(iommu->dev, 0xf4, &value); | |
1042 | ||
1043 | if (value & BIT(2)) | |
1044 | return; | |
1045 | ||
1046 | /* Select NB indirect register 0x90 and enable writing */ | |
1047 | pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); | |
1048 | ||
1049 | pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); | |
1050 | pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n", | |
1051 | dev_name(&iommu->dev->dev)); | |
1052 | ||
1053 | /* Clear the enable writing bit */ | |
1054 | pci_write_config_dword(iommu->dev, 0xf0, 0x90); | |
1055 | } | |
1056 | ||
b65233a9 JR |
1057 | /* |
1058 | * This function clues the initialization function for one IOMMU | |
1059 | * together and also allocates the command buffer and programs the | |
1060 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
1061 | */ | |
e47d402d JR |
1062 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
1063 | { | |
6efed63b JR |
1064 | int ret; |
1065 | ||
e47d402d | 1066 | spin_lock_init(&iommu->lock); |
bb52777e JR |
1067 | |
1068 | /* Add IOMMU to internal data structures */ | |
e47d402d | 1069 | list_add_tail(&iommu->list, &amd_iommu_list); |
bb52777e JR |
1070 | iommu->index = amd_iommus_present++; |
1071 | ||
1072 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | |
1073 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | |
1074 | return -ENOSYS; | |
1075 | } | |
1076 | ||
1077 | /* Index is fine - add IOMMU to the array */ | |
1078 | amd_iommus[iommu->index] = iommu; | |
e47d402d JR |
1079 | |
1080 | /* | |
1081 | * Copy data from ACPI table entry to the iommu struct | |
1082 | */ | |
23c742db | 1083 | iommu->devid = h->devid; |
e47d402d | 1084 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 1085 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
1086 | iommu->mmio_phys = h->mmio_phys; |
1087 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
1088 | if (!iommu->mmio_base) | |
1089 | return -ENOMEM; | |
1090 | ||
e47d402d JR |
1091 | iommu->cmd_buf = alloc_command_buffer(iommu); |
1092 | if (!iommu->cmd_buf) | |
1093 | return -ENOMEM; | |
1094 | ||
335503e5 JR |
1095 | iommu->evt_buf = alloc_event_buffer(iommu); |
1096 | if (!iommu->evt_buf) | |
1097 | return -ENOMEM; | |
1098 | ||
a80dc3e0 JR |
1099 | iommu->int_enabled = false; |
1100 | ||
6efed63b JR |
1101 | ret = init_iommu_from_acpi(iommu, h); |
1102 | if (ret) | |
1103 | return ret; | |
f6fec00a JR |
1104 | |
1105 | /* | |
1106 | * Make sure IOMMU is not considered to translate itself. The IVRS | |
1107 | * table tells us so, but this is a lie! | |
1108 | */ | |
1109 | amd_iommu_rlookup_table[iommu->devid] = NULL; | |
1110 | ||
e47d402d JR |
1111 | init_iommu_devices(iommu); |
1112 | ||
23c742db | 1113 | return 0; |
e47d402d JR |
1114 | } |
1115 | ||
b65233a9 JR |
1116 | /* |
1117 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
1118 | * IOMMU structure and initializes it with init_iommu_one() | |
1119 | */ | |
e47d402d JR |
1120 | static int __init init_iommu_all(struct acpi_table_header *table) |
1121 | { | |
1122 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1123 | struct ivhd_header *h; | |
1124 | struct amd_iommu *iommu; | |
1125 | int ret; | |
1126 | ||
e47d402d JR |
1127 | end += table->length; |
1128 | p += IVRS_HEADER_LENGTH; | |
1129 | ||
1130 | while (p < end) { | |
1131 | h = (struct ivhd_header *)p; | |
1132 | switch (*p) { | |
1133 | case ACPI_IVHD_TYPE: | |
9c72041f | 1134 | |
ae908c22 | 1135 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
1136 | "seg: %d flags: %01x info %04x\n", |
1137 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
1138 | PCI_FUNC(h->devid), h->cap_ptr, | |
1139 | h->pci_seg, h->flags, h->info); | |
1140 | DUMP_printk(" mmio-addr: %016llx\n", | |
1141 | h->mmio_phys); | |
1142 | ||
e47d402d | 1143 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
02f3b3f5 JR |
1144 | if (iommu == NULL) |
1145 | return -ENOMEM; | |
3551a708 | 1146 | |
e47d402d | 1147 | ret = init_iommu_one(iommu, h); |
02f3b3f5 JR |
1148 | if (ret) |
1149 | return ret; | |
e47d402d JR |
1150 | break; |
1151 | default: | |
1152 | break; | |
1153 | } | |
1154 | p += h->length; | |
1155 | ||
1156 | } | |
1157 | WARN_ON(p != end); | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
23c742db JR |
1162 | static int iommu_init_pci(struct amd_iommu *iommu) |
1163 | { | |
1164 | int cap_ptr = iommu->cap_ptr; | |
1165 | u32 range, misc, low, high; | |
1166 | ||
1167 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(iommu->devid), | |
1168 | iommu->devid & 0xff); | |
1169 | if (!iommu->dev) | |
1170 | return -ENODEV; | |
1171 | ||
1172 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, | |
1173 | &iommu->cap); | |
1174 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
1175 | &range); | |
1176 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, | |
1177 | &misc); | |
1178 | ||
1179 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), | |
1180 | MMIO_GET_FD(range)); | |
1181 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
1182 | MMIO_GET_LD(range)); | |
1183 | ||
1184 | if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) | |
1185 | amd_iommu_iotlb_sup = false; | |
1186 | ||
1187 | /* read extended feature bits */ | |
1188 | low = readl(iommu->mmio_base + MMIO_EXT_FEATURES); | |
1189 | high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4); | |
1190 | ||
1191 | iommu->features = ((u64)high << 32) | low; | |
1192 | ||
1193 | if (iommu_feature(iommu, FEATURE_GT)) { | |
1194 | int glxval; | |
1195 | u32 pasids; | |
1196 | u64 shift; | |
1197 | ||
1198 | shift = iommu->features & FEATURE_PASID_MASK; | |
1199 | shift >>= FEATURE_PASID_SHIFT; | |
1200 | pasids = (1 << shift); | |
1201 | ||
1202 | amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids); | |
1203 | ||
1204 | glxval = iommu->features & FEATURE_GLXVAL_MASK; | |
1205 | glxval >>= FEATURE_GLXVAL_SHIFT; | |
1206 | ||
1207 | if (amd_iommu_max_glx_val == -1) | |
1208 | amd_iommu_max_glx_val = glxval; | |
1209 | else | |
1210 | amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); | |
1211 | } | |
1212 | ||
1213 | if (iommu_feature(iommu, FEATURE_GT) && | |
1214 | iommu_feature(iommu, FEATURE_PPR)) { | |
1215 | iommu->is_iommu_v2 = true; | |
1216 | amd_iommu_v2_present = true; | |
1217 | } | |
1218 | ||
1219 | if (iommu_feature(iommu, FEATURE_PPR)) { | |
1220 | iommu->ppr_log = alloc_ppr_log(iommu); | |
1221 | if (!iommu->ppr_log) | |
1222 | return -ENOMEM; | |
1223 | } | |
1224 | ||
1225 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) | |
1226 | amd_iommu_np_cache = true; | |
1227 | ||
1228 | if (is_rd890_iommu(iommu->dev)) { | |
1229 | int i, j; | |
1230 | ||
1231 | iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number, | |
1232 | PCI_DEVFN(0, 0)); | |
1233 | ||
1234 | /* | |
1235 | * Some rd890 systems may not be fully reconfigured by the | |
1236 | * BIOS, so it's necessary for us to store this information so | |
1237 | * it can be reprogrammed on resume | |
1238 | */ | |
1239 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1240 | &iommu->stored_addr_lo); | |
1241 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
1242 | &iommu->stored_addr_hi); | |
1243 | ||
1244 | /* Low bit locks writes to configuration space */ | |
1245 | iommu->stored_addr_lo &= ~1; | |
1246 | ||
1247 | for (i = 0; i < 6; i++) | |
1248 | for (j = 0; j < 0x12; j++) | |
1249 | iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); | |
1250 | ||
1251 | for (i = 0; i < 0x83; i++) | |
1252 | iommu->stored_l2[i] = iommu_read_l2(iommu, i); | |
1253 | } | |
1254 | ||
318fe782 SS |
1255 | amd_iommu_erratum_746_workaround(iommu); |
1256 | ||
23c742db JR |
1257 | return pci_enable_device(iommu->dev); |
1258 | } | |
1259 | ||
4d121c32 JR |
1260 | static void print_iommu_info(void) |
1261 | { | |
1262 | static const char * const feat_str[] = { | |
1263 | "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", | |
1264 | "IA", "GA", "HE", "PC" | |
1265 | }; | |
1266 | struct amd_iommu *iommu; | |
1267 | ||
1268 | for_each_iommu(iommu) { | |
1269 | int i; | |
1270 | ||
1271 | pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n", | |
1272 | dev_name(&iommu->dev->dev), iommu->cap_ptr); | |
1273 | ||
1274 | if (iommu->cap & (1 << IOMMU_CAP_EFR)) { | |
1275 | pr_info("AMD-Vi: Extended features: "); | |
2bd5ed00 | 1276 | for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { |
4d121c32 JR |
1277 | if (iommu_feature(iommu, (1ULL << i))) |
1278 | pr_cont(" %s", feat_str[i]); | |
1279 | } | |
4d121c32 | 1280 | pr_cont("\n"); |
500c25ed | 1281 | } |
4d121c32 | 1282 | } |
ebe60bbf JR |
1283 | if (irq_remapping_enabled) |
1284 | pr_info("AMD-Vi: Interrupt remapping enabled\n"); | |
4d121c32 JR |
1285 | } |
1286 | ||
2c0ae172 | 1287 | static int __init amd_iommu_init_pci(void) |
23c742db JR |
1288 | { |
1289 | struct amd_iommu *iommu; | |
1290 | int ret = 0; | |
1291 | ||
1292 | for_each_iommu(iommu) { | |
1293 | ret = iommu_init_pci(iommu); | |
1294 | if (ret) | |
1295 | break; | |
1296 | } | |
1297 | ||
23c742db JR |
1298 | ret = amd_iommu_init_devices(); |
1299 | ||
4d121c32 JR |
1300 | print_iommu_info(); |
1301 | ||
23c742db JR |
1302 | return ret; |
1303 | } | |
1304 | ||
a80dc3e0 JR |
1305 | /**************************************************************************** |
1306 | * | |
1307 | * The following functions initialize the MSI interrupts for all IOMMUs | |
df805abb | 1308 | * in the system. It's a bit challenging because there could be multiple |
a80dc3e0 JR |
1309 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per |
1310 | * pci_dev. | |
1311 | * | |
1312 | ****************************************************************************/ | |
1313 | ||
9f800de3 | 1314 | static int iommu_setup_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
1315 | { |
1316 | int r; | |
a80dc3e0 | 1317 | |
9ddd592a JR |
1318 | r = pci_enable_msi(iommu->dev); |
1319 | if (r) | |
1320 | return r; | |
a80dc3e0 | 1321 | |
72fe00f0 JR |
1322 | r = request_threaded_irq(iommu->dev->irq, |
1323 | amd_iommu_int_handler, | |
1324 | amd_iommu_int_thread, | |
1325 | 0, "AMD-Vi", | |
1326 | iommu->dev); | |
a80dc3e0 JR |
1327 | |
1328 | if (r) { | |
1329 | pci_disable_msi(iommu->dev); | |
9ddd592a | 1330 | return r; |
a80dc3e0 JR |
1331 | } |
1332 | ||
fab6afa3 | 1333 | iommu->int_enabled = true; |
1a29ac01 | 1334 | |
a80dc3e0 JR |
1335 | return 0; |
1336 | } | |
1337 | ||
05f92db9 | 1338 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 | 1339 | { |
9ddd592a JR |
1340 | int ret; |
1341 | ||
a80dc3e0 | 1342 | if (iommu->int_enabled) |
9ddd592a | 1343 | goto enable_faults; |
a80dc3e0 | 1344 | |
d91cecdd | 1345 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
9ddd592a JR |
1346 | ret = iommu_setup_msi(iommu); |
1347 | else | |
1348 | ret = -ENODEV; | |
1349 | ||
1350 | if (ret) | |
1351 | return ret; | |
a80dc3e0 | 1352 | |
9ddd592a JR |
1353 | enable_faults: |
1354 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); | |
a80dc3e0 | 1355 | |
9ddd592a JR |
1356 | if (iommu->ppr_log != NULL) |
1357 | iommu_feature_enable(iommu, CONTROL_PPFINT_EN); | |
1358 | ||
1359 | return 0; | |
a80dc3e0 JR |
1360 | } |
1361 | ||
b65233a9 JR |
1362 | /**************************************************************************** |
1363 | * | |
1364 | * The next functions belong to the third pass of parsing the ACPI | |
1365 | * table. In this last pass the memory mapping requirements are | |
df805abb | 1366 | * gathered (like exclusion and unity mapping ranges). |
b65233a9 JR |
1367 | * |
1368 | ****************************************************************************/ | |
1369 | ||
be2a022c JR |
1370 | static void __init free_unity_maps(void) |
1371 | { | |
1372 | struct unity_map_entry *entry, *next; | |
1373 | ||
1374 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
1375 | list_del(&entry->list); | |
1376 | kfree(entry); | |
1377 | } | |
1378 | } | |
1379 | ||
b65233a9 | 1380 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
1381 | static int __init init_exclusion_range(struct ivmd_header *m) |
1382 | { | |
1383 | int i; | |
1384 | ||
1385 | switch (m->type) { | |
1386 | case ACPI_IVMD_TYPE: | |
1387 | set_device_exclusion_range(m->devid, m); | |
1388 | break; | |
1389 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 1390 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
1391 | set_device_exclusion_range(i, m); |
1392 | break; | |
1393 | case ACPI_IVMD_TYPE_RANGE: | |
1394 | for (i = m->devid; i <= m->aux; ++i) | |
1395 | set_device_exclusion_range(i, m); | |
1396 | break; | |
1397 | default: | |
1398 | break; | |
1399 | } | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | ||
b65233a9 | 1404 | /* called for unity map ACPI definition */ |
be2a022c JR |
1405 | static int __init init_unity_map_range(struct ivmd_header *m) |
1406 | { | |
98f1ad25 | 1407 | struct unity_map_entry *e = NULL; |
02acc43a | 1408 | char *s; |
be2a022c JR |
1409 | |
1410 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1411 | if (e == NULL) | |
1412 | return -ENOMEM; | |
1413 | ||
1414 | switch (m->type) { | |
1415 | default: | |
0bc252f4 JR |
1416 | kfree(e); |
1417 | return 0; | |
be2a022c | 1418 | case ACPI_IVMD_TYPE: |
02acc43a | 1419 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1420 | e->devid_start = e->devid_end = m->devid; |
1421 | break; | |
1422 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1423 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1424 | e->devid_start = 0; |
1425 | e->devid_end = amd_iommu_last_bdf; | |
1426 | break; | |
1427 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1428 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1429 | e->devid_start = m->devid; |
1430 | e->devid_end = m->aux; | |
1431 | break; | |
1432 | } | |
1433 | e->address_start = PAGE_ALIGN(m->range_start); | |
1434 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1435 | e->prot = m->flags >> 1; | |
1436 | ||
02acc43a JR |
1437 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1438 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1439 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1440 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1441 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1442 | e->address_start, e->address_end, m->flags); | |
1443 | ||
be2a022c JR |
1444 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1445 | ||
1446 | return 0; | |
1447 | } | |
1448 | ||
b65233a9 | 1449 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1450 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1451 | { | |
1452 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1453 | struct ivmd_header *m; | |
1454 | ||
be2a022c JR |
1455 | end += table->length; |
1456 | p += IVRS_HEADER_LENGTH; | |
1457 | ||
1458 | while (p < end) { | |
1459 | m = (struct ivmd_header *)p; | |
1460 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1461 | init_exclusion_range(m); | |
1462 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1463 | init_unity_map_range(m); | |
1464 | ||
1465 | p += m->length; | |
1466 | } | |
1467 | ||
1468 | return 0; | |
1469 | } | |
1470 | ||
9f5f5fb3 JR |
1471 | /* |
1472 | * Init the device table to not allow DMA access for devices and | |
1473 | * suppress all page faults | |
1474 | */ | |
33f28c59 | 1475 | static void init_device_table_dma(void) |
9f5f5fb3 | 1476 | { |
0de66d5b | 1477 | u32 devid; |
9f5f5fb3 JR |
1478 | |
1479 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1480 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1481 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1482 | } |
1483 | } | |
1484 | ||
d04e0ba3 JR |
1485 | static void __init uninit_device_table_dma(void) |
1486 | { | |
1487 | u32 devid; | |
1488 | ||
1489 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1490 | amd_iommu_dev_table[devid].data[0] = 0ULL; | |
1491 | amd_iommu_dev_table[devid].data[1] = 0ULL; | |
1492 | } | |
1493 | } | |
1494 | ||
33f28c59 JR |
1495 | static void init_device_table(void) |
1496 | { | |
1497 | u32 devid; | |
1498 | ||
1499 | if (!amd_iommu_irq_remap) | |
1500 | return; | |
1501 | ||
1502 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1503 | set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN); | |
1504 | } | |
1505 | ||
e9bf5197 JR |
1506 | static void iommu_init_flags(struct amd_iommu *iommu) |
1507 | { | |
1508 | iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? | |
1509 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
1510 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
1511 | ||
1512 | iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? | |
1513 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
1514 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
1515 | ||
1516 | iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? | |
1517 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
1518 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
1519 | ||
1520 | iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? | |
1521 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
1522 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
1523 | ||
1524 | /* | |
1525 | * make IOMMU memory accesses cache coherent | |
1526 | */ | |
1527 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
1456e9d2 JR |
1528 | |
1529 | /* Set IOTLB invalidation timeout to 1s */ | |
1530 | iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); | |
e9bf5197 JR |
1531 | } |
1532 | ||
5bcd757f | 1533 | static void iommu_apply_resume_quirks(struct amd_iommu *iommu) |
4c894f47 | 1534 | { |
5bcd757f MG |
1535 | int i, j; |
1536 | u32 ioc_feature_control; | |
c1bf94ec | 1537 | struct pci_dev *pdev = iommu->root_pdev; |
5bcd757f MG |
1538 | |
1539 | /* RD890 BIOSes may not have completely reconfigured the iommu */ | |
c1bf94ec | 1540 | if (!is_rd890_iommu(iommu->dev) || !pdev) |
5bcd757f MG |
1541 | return; |
1542 | ||
1543 | /* | |
1544 | * First, we need to ensure that the iommu is enabled. This is | |
1545 | * controlled by a register in the northbridge | |
1546 | */ | |
5bcd757f MG |
1547 | |
1548 | /* Select Northbridge indirect register 0x75 and enable writing */ | |
1549 | pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); | |
1550 | pci_read_config_dword(pdev, 0x64, &ioc_feature_control); | |
1551 | ||
1552 | /* Enable the iommu */ | |
1553 | if (!(ioc_feature_control & 0x1)) | |
1554 | pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); | |
1555 | ||
5bcd757f MG |
1556 | /* Restore the iommu BAR */ |
1557 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1558 | iommu->stored_addr_lo); | |
1559 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
1560 | iommu->stored_addr_hi); | |
1561 | ||
1562 | /* Restore the l1 indirect regs for each of the 6 l1s */ | |
1563 | for (i = 0; i < 6; i++) | |
1564 | for (j = 0; j < 0x12; j++) | |
1565 | iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); | |
1566 | ||
1567 | /* Restore the l2 indirect regs */ | |
1568 | for (i = 0; i < 0x83; i++) | |
1569 | iommu_write_l2(iommu, i, iommu->stored_l2[i]); | |
1570 | ||
1571 | /* Lock PCI setup registers */ | |
1572 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1573 | iommu->stored_addr_lo | 1); | |
4c894f47 JR |
1574 | } |
1575 | ||
b65233a9 JR |
1576 | /* |
1577 | * This function finally enables all IOMMUs found in the system after | |
1578 | * they have been initialized | |
1579 | */ | |
11ee5ac4 | 1580 | static void early_enable_iommus(void) |
8736197b JR |
1581 | { |
1582 | struct amd_iommu *iommu; | |
1583 | ||
3bd22172 | 1584 | for_each_iommu(iommu) { |
a8c485bb | 1585 | iommu_disable(iommu); |
e9bf5197 | 1586 | iommu_init_flags(iommu); |
58492e12 JR |
1587 | iommu_set_device_table(iommu); |
1588 | iommu_enable_command_buffer(iommu); | |
1589 | iommu_enable_event_buffer(iommu); | |
8736197b JR |
1590 | iommu_set_exclusion_range(iommu); |
1591 | iommu_enable(iommu); | |
7d0c5cc5 | 1592 | iommu_flush_all_caches(iommu); |
8736197b JR |
1593 | } |
1594 | } | |
1595 | ||
11ee5ac4 JR |
1596 | static void enable_iommus_v2(void) |
1597 | { | |
1598 | struct amd_iommu *iommu; | |
1599 | ||
1600 | for_each_iommu(iommu) { | |
1601 | iommu_enable_ppr_log(iommu); | |
1602 | iommu_enable_gt(iommu); | |
1603 | } | |
1604 | } | |
1605 | ||
1606 | static void enable_iommus(void) | |
1607 | { | |
1608 | early_enable_iommus(); | |
1609 | ||
1610 | enable_iommus_v2(); | |
1611 | } | |
1612 | ||
92ac4320 JR |
1613 | static void disable_iommus(void) |
1614 | { | |
1615 | struct amd_iommu *iommu; | |
1616 | ||
1617 | for_each_iommu(iommu) | |
1618 | iommu_disable(iommu); | |
1619 | } | |
1620 | ||
7441e9cb JR |
1621 | /* |
1622 | * Suspend/Resume support | |
1623 | * disable suspend until real resume implemented | |
1624 | */ | |
1625 | ||
f3c6ea1b | 1626 | static void amd_iommu_resume(void) |
7441e9cb | 1627 | { |
5bcd757f MG |
1628 | struct amd_iommu *iommu; |
1629 | ||
1630 | for_each_iommu(iommu) | |
1631 | iommu_apply_resume_quirks(iommu); | |
1632 | ||
736501ee JR |
1633 | /* re-load the hardware */ |
1634 | enable_iommus(); | |
3d9761e7 JR |
1635 | |
1636 | amd_iommu_enable_interrupts(); | |
7441e9cb JR |
1637 | } |
1638 | ||
f3c6ea1b | 1639 | static int amd_iommu_suspend(void) |
7441e9cb | 1640 | { |
736501ee JR |
1641 | /* disable IOMMUs to go out of the way for BIOS */ |
1642 | disable_iommus(); | |
1643 | ||
1644 | return 0; | |
7441e9cb JR |
1645 | } |
1646 | ||
f3c6ea1b | 1647 | static struct syscore_ops amd_iommu_syscore_ops = { |
7441e9cb JR |
1648 | .suspend = amd_iommu_suspend, |
1649 | .resume = amd_iommu_resume, | |
1650 | }; | |
1651 | ||
8704a1ba JR |
1652 | static void __init free_on_init_error(void) |
1653 | { | |
0ea2c422 JR |
1654 | free_pages((unsigned long)irq_lookup_table, |
1655 | get_order(rlookup_table_size)); | |
8704a1ba | 1656 | |
05152a04 JR |
1657 | if (amd_iommu_irq_cache) { |
1658 | kmem_cache_destroy(amd_iommu_irq_cache); | |
1659 | amd_iommu_irq_cache = NULL; | |
0ea2c422 | 1660 | |
05152a04 | 1661 | } |
8704a1ba JR |
1662 | |
1663 | free_pages((unsigned long)amd_iommu_rlookup_table, | |
1664 | get_order(rlookup_table_size)); | |
1665 | ||
1666 | free_pages((unsigned long)amd_iommu_alias_table, | |
1667 | get_order(alias_table_size)); | |
1668 | ||
1669 | free_pages((unsigned long)amd_iommu_dev_table, | |
1670 | get_order(dev_table_size)); | |
1671 | ||
1672 | free_iommu_all(); | |
1673 | ||
8704a1ba JR |
1674 | #ifdef CONFIG_GART_IOMMU |
1675 | /* | |
1676 | * We failed to initialize the AMD IOMMU - try fallback to GART | |
1677 | * if possible. | |
1678 | */ | |
1679 | gart_iommu_init(); | |
1680 | ||
1681 | #endif | |
1682 | } | |
1683 | ||
c2ff5cf5 JR |
1684 | /* SB IOAPIC is always on this device in AMD systems */ |
1685 | #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) | |
1686 | ||
eb1eb7ae JR |
1687 | static bool __init check_ioapic_information(void) |
1688 | { | |
c2ff5cf5 | 1689 | bool ret, has_sb_ioapic; |
eb1eb7ae JR |
1690 | int idx; |
1691 | ||
c2ff5cf5 JR |
1692 | has_sb_ioapic = false; |
1693 | ret = false; | |
eb1eb7ae | 1694 | |
c2ff5cf5 JR |
1695 | for (idx = 0; idx < nr_ioapics; idx++) { |
1696 | int devid, id = mpc_ioapic_id(idx); | |
1697 | ||
1698 | devid = get_ioapic_devid(id); | |
1699 | if (devid < 0) { | |
1700 | pr_err(FW_BUG "AMD-Vi: IOAPIC[%d] not in IVRS table\n", id); | |
1701 | ret = false; | |
1702 | } else if (devid == IOAPIC_SB_DEVID) { | |
1703 | has_sb_ioapic = true; | |
1704 | ret = true; | |
eb1eb7ae JR |
1705 | } |
1706 | } | |
1707 | ||
c2ff5cf5 JR |
1708 | if (!has_sb_ioapic) { |
1709 | /* | |
1710 | * We expect the SB IOAPIC to be listed in the IVRS | |
1711 | * table. The system timer is connected to the SB IOAPIC | |
1712 | * and if we don't have it in the list the system will | |
1713 | * panic at boot time. This situation usually happens | |
1714 | * when the BIOS is buggy and provides us the wrong | |
1715 | * device id for the IOAPIC in the system. | |
1716 | */ | |
1717 | pr_err(FW_BUG "AMD-Vi: No southbridge IOAPIC found in IVRS table\n"); | |
1718 | } | |
1719 | ||
1720 | if (!ret) | |
1721 | pr_err("AMD-Vi: Disabling interrupt remapping due to BIOS Bug(s)\n"); | |
1722 | ||
1723 | return ret; | |
eb1eb7ae JR |
1724 | } |
1725 | ||
d04e0ba3 JR |
1726 | static void __init free_dma_resources(void) |
1727 | { | |
1728 | amd_iommu_uninit_devices(); | |
1729 | ||
1730 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, | |
1731 | get_order(MAX_DOMAIN_ID/8)); | |
1732 | ||
1733 | free_unity_maps(); | |
1734 | } | |
1735 | ||
b65233a9 | 1736 | /* |
8704a1ba JR |
1737 | * This is the hardware init function for AMD IOMMU in the system. |
1738 | * This function is called either from amd_iommu_init or from the interrupt | |
1739 | * remapping setup code. | |
b65233a9 JR |
1740 | * |
1741 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1742 | * three times: | |
1743 | * | |
1744 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1745 | * Upon this information the size of the data structures is | |
1746 | * determined that needs to be allocated. | |
1747 | * | |
1748 | * 2 pass) Initialize the data structures just allocated with the | |
1749 | * information in the ACPI table about available AMD IOMMUs | |
1750 | * in the system. It also maps the PCI devices in the | |
1751 | * system to specific IOMMUs | |
1752 | * | |
1753 | * 3 pass) After the basic data structures are allocated and | |
1754 | * initialized we update them with information about memory | |
1755 | * remapping requirements parsed out of the ACPI table in | |
1756 | * this last pass. | |
1757 | * | |
8704a1ba JR |
1758 | * After everything is set up the IOMMUs are enabled and the necessary |
1759 | * hotplug and suspend notifiers are registered. | |
b65233a9 | 1760 | */ |
643511b3 | 1761 | static int __init early_amd_iommu_init(void) |
fe74c9cf | 1762 | { |
02f3b3f5 JR |
1763 | struct acpi_table_header *ivrs_base; |
1764 | acpi_size ivrs_size; | |
1765 | acpi_status status; | |
fe74c9cf JR |
1766 | int i, ret = 0; |
1767 | ||
643511b3 | 1768 | if (!amd_iommu_detected) |
8704a1ba JR |
1769 | return -ENODEV; |
1770 | ||
02f3b3f5 JR |
1771 | status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size); |
1772 | if (status == AE_NOT_FOUND) | |
1773 | return -ENODEV; | |
1774 | else if (ACPI_FAILURE(status)) { | |
1775 | const char *err = acpi_format_exception(status); | |
1776 | pr_err("AMD-Vi: IVRS table error: %s\n", err); | |
1777 | return -EINVAL; | |
1778 | } | |
1779 | ||
fe74c9cf JR |
1780 | /* |
1781 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1782 | * we need to handle. Upon this information the shared data | |
1783 | * structures for the IOMMUs in the system will be allocated | |
1784 | */ | |
2c0ae172 JR |
1785 | ret = find_last_devid_acpi(ivrs_base); |
1786 | if (ret) | |
3551a708 JR |
1787 | goto out; |
1788 | ||
c571484e JR |
1789 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1790 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1791 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf | 1792 | |
fe74c9cf | 1793 | /* Device table - directly used by all IOMMUs */ |
8704a1ba | 1794 | ret = -ENOMEM; |
5dc8bff0 | 1795 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1796 | get_order(dev_table_size)); |
1797 | if (amd_iommu_dev_table == NULL) | |
1798 | goto out; | |
1799 | ||
1800 | /* | |
1801 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1802 | * IOMMU see for that device | |
1803 | */ | |
1804 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1805 | get_order(alias_table_size)); | |
1806 | if (amd_iommu_alias_table == NULL) | |
2c0ae172 | 1807 | goto out; |
fe74c9cf JR |
1808 | |
1809 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1810 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1811 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1812 | get_order(rlookup_table_size)); |
1813 | if (amd_iommu_rlookup_table == NULL) | |
2c0ae172 | 1814 | goto out; |
fe74c9cf | 1815 | |
5dc8bff0 JR |
1816 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1817 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1818 | get_order(MAX_DOMAIN_ID/8)); |
1819 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
2c0ae172 | 1820 | goto out; |
fe74c9cf JR |
1821 | |
1822 | /* | |
5dc8bff0 | 1823 | * let all alias entries point to itself |
fe74c9cf | 1824 | */ |
3a61ec38 | 1825 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1826 | amd_iommu_alias_table[i] = i; |
1827 | ||
fe74c9cf JR |
1828 | /* |
1829 | * never allocate domain 0 because its used as the non-allocated and | |
1830 | * error value placeholder | |
1831 | */ | |
1832 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1833 | ||
aeb26f55 JR |
1834 | spin_lock_init(&amd_iommu_pd_lock); |
1835 | ||
fe74c9cf JR |
1836 | /* |
1837 | * now the data structures are allocated and basically initialized | |
1838 | * start the real acpi table scan | |
1839 | */ | |
02f3b3f5 JR |
1840 | ret = init_iommu_all(ivrs_base); |
1841 | if (ret) | |
2c0ae172 | 1842 | goto out; |
fe74c9cf | 1843 | |
eb1eb7ae JR |
1844 | if (amd_iommu_irq_remap) |
1845 | amd_iommu_irq_remap = check_ioapic_information(); | |
1846 | ||
05152a04 JR |
1847 | if (amd_iommu_irq_remap) { |
1848 | /* | |
1849 | * Interrupt remapping enabled, create kmem_cache for the | |
1850 | * remapping tables. | |
1851 | */ | |
1852 | amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", | |
1853 | MAX_IRQS_PER_TABLE * sizeof(u32), | |
1854 | IRQ_TABLE_ALIGNMENT, | |
1855 | 0, NULL); | |
1856 | if (!amd_iommu_irq_cache) | |
1857 | goto out; | |
0ea2c422 JR |
1858 | |
1859 | irq_lookup_table = (void *)__get_free_pages( | |
1860 | GFP_KERNEL | __GFP_ZERO, | |
1861 | get_order(rlookup_table_size)); | |
1862 | if (!irq_lookup_table) | |
1863 | goto out; | |
05152a04 JR |
1864 | } |
1865 | ||
02f3b3f5 JR |
1866 | ret = init_memory_definitions(ivrs_base); |
1867 | if (ret) | |
2c0ae172 | 1868 | goto out; |
3551a708 | 1869 | |
eb1eb7ae JR |
1870 | /* init the device table */ |
1871 | init_device_table(); | |
1872 | ||
8704a1ba | 1873 | out: |
02f3b3f5 JR |
1874 | /* Don't leak any ACPI memory */ |
1875 | early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size); | |
1876 | ivrs_base = NULL; | |
1877 | ||
643511b3 JR |
1878 | return ret; |
1879 | } | |
1880 | ||
ae295142 | 1881 | static int amd_iommu_enable_interrupts(void) |
3d9761e7 JR |
1882 | { |
1883 | struct amd_iommu *iommu; | |
1884 | int ret = 0; | |
1885 | ||
1886 | for_each_iommu(iommu) { | |
1887 | ret = iommu_init_msi(iommu); | |
1888 | if (ret) | |
1889 | goto out; | |
1890 | } | |
1891 | ||
1892 | out: | |
1893 | return ret; | |
1894 | } | |
1895 | ||
02f3b3f5 JR |
1896 | static bool detect_ivrs(void) |
1897 | { | |
1898 | struct acpi_table_header *ivrs_base; | |
1899 | acpi_size ivrs_size; | |
1900 | acpi_status status; | |
1901 | ||
1902 | status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size); | |
1903 | if (status == AE_NOT_FOUND) | |
1904 | return false; | |
1905 | else if (ACPI_FAILURE(status)) { | |
1906 | const char *err = acpi_format_exception(status); | |
1907 | pr_err("AMD-Vi: IVRS table error: %s\n", err); | |
1908 | return false; | |
1909 | } | |
1910 | ||
1911 | early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size); | |
1912 | ||
1adb7d31 JR |
1913 | /* Make sure ACS will be enabled during PCI probe */ |
1914 | pci_request_acs(); | |
1915 | ||
05152a04 JR |
1916 | if (!disable_irq_remap) |
1917 | amd_iommu_irq_remap = true; | |
1918 | ||
02f3b3f5 JR |
1919 | return true; |
1920 | } | |
1921 | ||
b9b1ce70 JR |
1922 | static int amd_iommu_init_dma(void) |
1923 | { | |
33f28c59 | 1924 | struct amd_iommu *iommu; |
b9b1ce70 JR |
1925 | int ret; |
1926 | ||
1927 | if (iommu_pass_through) | |
1928 | ret = amd_iommu_init_passthrough(); | |
1929 | else | |
1930 | ret = amd_iommu_init_dma_ops(); | |
1931 | ||
1932 | if (ret) | |
1933 | return ret; | |
1934 | ||
f528d980 JR |
1935 | init_device_table_dma(); |
1936 | ||
1937 | for_each_iommu(iommu) | |
1938 | iommu_flush_all_caches(iommu); | |
1939 | ||
b9b1ce70 JR |
1940 | amd_iommu_init_api(); |
1941 | ||
1942 | amd_iommu_init_notifier(); | |
1943 | ||
1944 | return 0; | |
1945 | } | |
1946 | ||
2c0ae172 | 1947 | /**************************************************************************** |
8704a1ba | 1948 | * |
2c0ae172 JR |
1949 | * AMD IOMMU Initialization State Machine |
1950 | * | |
1951 | ****************************************************************************/ | |
1952 | ||
1953 | static int __init state_next(void) | |
8704a1ba JR |
1954 | { |
1955 | int ret = 0; | |
1956 | ||
2c0ae172 JR |
1957 | switch (init_state) { |
1958 | case IOMMU_START_STATE: | |
1959 | if (!detect_ivrs()) { | |
1960 | init_state = IOMMU_NOT_FOUND; | |
1961 | ret = -ENODEV; | |
1962 | } else { | |
1963 | init_state = IOMMU_IVRS_DETECTED; | |
1964 | } | |
1965 | break; | |
1966 | case IOMMU_IVRS_DETECTED: | |
1967 | ret = early_amd_iommu_init(); | |
1968 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; | |
1969 | break; | |
1970 | case IOMMU_ACPI_FINISHED: | |
1971 | early_enable_iommus(); | |
1972 | register_syscore_ops(&amd_iommu_syscore_ops); | |
1973 | x86_platform.iommu_shutdown = disable_iommus; | |
1974 | init_state = IOMMU_ENABLED; | |
1975 | break; | |
1976 | case IOMMU_ENABLED: | |
1977 | ret = amd_iommu_init_pci(); | |
1978 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; | |
1979 | enable_iommus_v2(); | |
1980 | break; | |
1981 | case IOMMU_PCI_INIT: | |
1982 | ret = amd_iommu_enable_interrupts(); | |
1983 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; | |
1984 | break; | |
1985 | case IOMMU_INTERRUPTS_EN: | |
1986 | ret = amd_iommu_init_dma(); | |
1987 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS; | |
1988 | break; | |
1989 | case IOMMU_DMA_OPS: | |
1990 | init_state = IOMMU_INITIALIZED; | |
1991 | break; | |
1992 | case IOMMU_INITIALIZED: | |
1993 | /* Nothing to do */ | |
1994 | break; | |
1995 | case IOMMU_NOT_FOUND: | |
1996 | case IOMMU_INIT_ERROR: | |
1997 | /* Error states => do nothing */ | |
1998 | ret = -EINVAL; | |
1999 | break; | |
2000 | default: | |
2001 | /* Unknown state */ | |
2002 | BUG(); | |
2003 | } | |
3d9761e7 | 2004 | |
2c0ae172 JR |
2005 | return ret; |
2006 | } | |
7441e9cb | 2007 | |
2c0ae172 JR |
2008 | static int __init iommu_go_to_state(enum iommu_init_state state) |
2009 | { | |
2010 | int ret = 0; | |
f5325094 | 2011 | |
2c0ae172 JR |
2012 | while (init_state != state) { |
2013 | ret = state_next(); | |
2014 | if (init_state == IOMMU_NOT_FOUND || | |
2015 | init_state == IOMMU_INIT_ERROR) | |
2016 | break; | |
2017 | } | |
f2f12b6f | 2018 | |
fe74c9cf | 2019 | return ret; |
2c0ae172 | 2020 | } |
fe74c9cf | 2021 | |
6b474b82 JR |
2022 | #ifdef CONFIG_IRQ_REMAP |
2023 | int __init amd_iommu_prepare(void) | |
2024 | { | |
2025 | return iommu_go_to_state(IOMMU_ACPI_FINISHED); | |
2026 | } | |
d7f07769 | 2027 | |
6b474b82 JR |
2028 | int __init amd_iommu_supported(void) |
2029 | { | |
2030 | return amd_iommu_irq_remap ? 1 : 0; | |
2031 | } | |
2032 | ||
2033 | int __init amd_iommu_enable(void) | |
2034 | { | |
2035 | int ret; | |
2036 | ||
2037 | ret = iommu_go_to_state(IOMMU_ENABLED); | |
2038 | if (ret) | |
2039 | return ret; | |
d7f07769 | 2040 | |
6b474b82 | 2041 | irq_remapping_enabled = 1; |
d7f07769 | 2042 | |
6b474b82 JR |
2043 | return 0; |
2044 | } | |
2045 | ||
2046 | void amd_iommu_disable(void) | |
2047 | { | |
2048 | amd_iommu_suspend(); | |
2049 | } | |
2050 | ||
2051 | int amd_iommu_reenable(int mode) | |
2052 | { | |
2053 | amd_iommu_resume(); | |
2054 | ||
2055 | return 0; | |
2056 | } | |
d7f07769 | 2057 | |
6b474b82 JR |
2058 | int __init amd_iommu_enable_faulting(void) |
2059 | { | |
2060 | /* We enable MSI later when PCI is initialized */ | |
2061 | return 0; | |
2062 | } | |
2063 | #endif | |
d7f07769 | 2064 | |
2c0ae172 JR |
2065 | /* |
2066 | * This is the core init function for AMD IOMMU hardware in the system. | |
2067 | * This function is called from the generic x86 DMA layer initialization | |
2068 | * code. | |
2069 | */ | |
2070 | static int __init amd_iommu_init(void) | |
2071 | { | |
2072 | int ret; | |
2073 | ||
2074 | ret = iommu_go_to_state(IOMMU_INITIALIZED); | |
2075 | if (ret) { | |
d04e0ba3 JR |
2076 | free_dma_resources(); |
2077 | if (!irq_remapping_enabled) { | |
2078 | disable_iommus(); | |
2079 | free_on_init_error(); | |
2080 | } else { | |
2081 | struct amd_iommu *iommu; | |
2082 | ||
2083 | uninit_device_table_dma(); | |
2084 | for_each_iommu(iommu) | |
2085 | iommu_flush_all_caches(iommu); | |
2086 | } | |
2c0ae172 JR |
2087 | } |
2088 | ||
2089 | return ret; | |
fe74c9cf JR |
2090 | } |
2091 | ||
b65233a9 JR |
2092 | /**************************************************************************** |
2093 | * | |
2094 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
2095 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
2096 | * IOMMUs | |
2097 | * | |
2098 | ****************************************************************************/ | |
480125ba | 2099 | int __init amd_iommu_detect(void) |
ae7877de | 2100 | { |
2c0ae172 | 2101 | int ret; |
02f3b3f5 | 2102 | |
75f1cdf1 | 2103 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) |
480125ba | 2104 | return -ENODEV; |
ae7877de | 2105 | |
a5235725 | 2106 | if (amd_iommu_disabled) |
480125ba | 2107 | return -ENODEV; |
a5235725 | 2108 | |
2c0ae172 JR |
2109 | ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); |
2110 | if (ret) | |
2111 | return ret; | |
11bd04f6 | 2112 | |
02f3b3f5 JR |
2113 | amd_iommu_detected = true; |
2114 | iommu_detected = 1; | |
2115 | x86_init.iommu.iommu_init = amd_iommu_init; | |
2116 | ||
02f3b3f5 | 2117 | return 0; |
ae7877de JR |
2118 | } |
2119 | ||
b65233a9 JR |
2120 | /**************************************************************************** |
2121 | * | |
2122 | * Parsing functions for the AMD IOMMU specific kernel command line | |
2123 | * options. | |
2124 | * | |
2125 | ****************************************************************************/ | |
2126 | ||
fefda117 JR |
2127 | static int __init parse_amd_iommu_dump(char *str) |
2128 | { | |
2129 | amd_iommu_dump = true; | |
2130 | ||
2131 | return 1; | |
2132 | } | |
2133 | ||
918ad6c5 JR |
2134 | static int __init parse_amd_iommu_options(char *str) |
2135 | { | |
2136 | for (; *str; ++str) { | |
695b5676 | 2137 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 2138 | amd_iommu_unmap_flush = true; |
a5235725 JR |
2139 | if (strncmp(str, "off", 3) == 0) |
2140 | amd_iommu_disabled = true; | |
5abcdba4 JR |
2141 | if (strncmp(str, "force_isolation", 15) == 0) |
2142 | amd_iommu_force_isolation = true; | |
918ad6c5 JR |
2143 | } |
2144 | ||
2145 | return 1; | |
2146 | } | |
2147 | ||
fefda117 | 2148 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 2149 | __setup("amd_iommu=", parse_amd_iommu_options); |
22e6daf4 KRW |
2150 | |
2151 | IOMMU_INIT_FINISH(amd_iommu_detect, | |
2152 | gart_iommu_hole_init, | |
98f1ad25 JR |
2153 | NULL, |
2154 | NULL); | |
400a28a0 JR |
2155 | |
2156 | bool amd_iommu_v2_supported(void) | |
2157 | { | |
2158 | return amd_iommu_v2_present; | |
2159 | } | |
2160 | EXPORT_SYMBOL(amd_iommu_v2_supported); |