projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
fsl/fman: fix error handling
[linux-2.6-block.git] / drivers / iommu / amd_iommu_init.c
CommitLineData
f6e2e6b6 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
63ce3ae8 3 * Author: Joerg Roedel <jroedel@suse.de>
f6e2e6b6
JR		 4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
f6e2e6b6 22#include <linux/list.h>
5a0e3ad6 23#include <linux/slab.h>
f3c6ea1b 24#include <linux/syscore_ops.h>
a80dc3e0
JR		 25#include <linux/interrupt.h>
26#include <linux/msi.h>
403f81d8 27#include <linux/amd-iommu.h>
400a28a0 28#include <linux/export.h>
066f2e98 29#include <linux/iommu.h>
f6e2e6b6 30#include <asm/pci-direct.h>
46a7fa27 31#include <asm/iommu.h>
1d9b16d1 32#include <asm/gart.h>
ea1b0d39 33#include <asm/x86_init.h>
22e6daf4 34#include <asm/iommu_table.h>
eb1eb7ae 35#include <asm/io_apic.h>
6b474b82 36#include <asm/irq_remapping.h>
403f81d8
JR		 37
38#include "amd_iommu_proto.h"
39#include "amd_iommu_types.h"
05152a04 40#include "irq_remapping.h"
403f81d8 41
f6e2e6b6
JR		 42/*
43 * definitions for the ACPI scanning code
44 */
f6e2e6b6 45#define IVRS_HEADER_LENGTH 48
f6e2e6b6 46
8c7142f5 47#define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
f6e2e6b6
JR		 48#define ACPI_IVMD_TYPE_ALL 0x20
49#define ACPI_IVMD_TYPE 0x21
50#define ACPI_IVMD_TYPE_RANGE 0x22
51
52#define IVHD_DEV_ALL 0x01
53#define IVHD_DEV_SELECT 0x02
54#define IVHD_DEV_SELECT_RANGE_START 0x03
55#define IVHD_DEV_RANGE_END 0x04
56#define IVHD_DEV_ALIAS 0x42
57#define IVHD_DEV_ALIAS_RANGE 0x43
58#define IVHD_DEV_EXT_SELECT 0x46
59#define IVHD_DEV_EXT_SELECT_RANGE 0x47
6efed63b 60#define IVHD_DEV_SPECIAL 0x48
8c7142f5 61#define IVHD_DEV_ACPI_HID 0xf0
6efed63b 62
2a0cb4e2
WZ		 63#define UID_NOT_PRESENT 0
64#define UID_IS_INTEGER 1
65#define UID_IS_CHARACTER 2
66
6efed63b
JR		 67#define IVHD_SPECIAL_IOAPIC 1
68#define IVHD_SPECIAL_HPET 2
f6e2e6b6 69
6da7342f
JR		 70#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
71#define IVHD_FLAG_PASSPW_EN_MASK 0x02
72#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
73#define IVHD_FLAG_ISOC_EN_MASK 0x08
f6e2e6b6
JR		 74
75#define IVMD_FLAG_EXCL_RANGE 0x08
76#define IVMD_FLAG_UNITY_MAP 0x01
77
78#define ACPI_DEVFLAG_INITPASS 0x01
79#define ACPI_DEVFLAG_EXTINT 0x02
80#define ACPI_DEVFLAG_NMI 0x04
81#define ACPI_DEVFLAG_SYSMGT1 0x10
82#define ACPI_DEVFLAG_SYSMGT2 0x20
83#define ACPI_DEVFLAG_LINT0 0x40
84#define ACPI_DEVFLAG_LINT1 0x80
85#define ACPI_DEVFLAG_ATSDIS 0x10000000
86
b65233a9
JR		 87/*
88 * ACPI table definitions
89 *
90 * These data structures are laid over the table to parse the important values
91 * out of it.
92 */
93
94/*
95 * structure describing one IOMMU in the ACPI table. Typically followed by one
96 * or more ivhd_entrys.
97 */
f6e2e6b6
JR		 98struct ivhd_header {
99 u8 type;
100 u8 flags;
101 u16 length;
102 u16 devid;
103 u16 cap_ptr;
104 u64 mmio_phys;
105 u16 pci_seg;
106 u16 info;
7d7d38af
SS		 107 u32 efr_attr;
108
109 /* Following only valid on IVHD type 11h and 40h */
110 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
111 u64 res;
f6e2e6b6
JR		 112} __attribute__((packed));
113
b65233a9
JR		 114/*
115 * A device entry describing which devices a specific IOMMU translates and
116 * which requestor ids they use.
117 */
f6e2e6b6
JR		 118struct ivhd_entry {
119 u8 type;
120 u16 devid;
121 u8 flags;
122 u32 ext;
2a0cb4e2
WZ		 123 u32 hidh;
124 u64 cid;
125 u8 uidf;
126 u8 uidl;
127 u8 uid;
f6e2e6b6
JR		 128} __attribute__((packed));
129
b65233a9
JR		 130/*
131 * An AMD IOMMU memory definition structure. It defines things like exclusion
132 * ranges for devices and regions that should be unity mapped.
133 */
f6e2e6b6
JR		 134struct ivmd_header {
135 u8 type;
136 u8 flags;
137 u16 length;
138 u16 devid;
139 u16 aux;
140 u64 resv;
141 u64 range_start;
142 u64 range_length;
143} __attribute__((packed));
144
fefda117 145bool amd_iommu_dump;
05152a04 146bool amd_iommu_irq_remap __read_mostly;
fefda117 147
02f3b3f5 148static bool amd_iommu_detected;
a5235725 149static bool __initdata amd_iommu_disabled;
8c7142f5 150static int amd_iommu_target_ivhd_type;
c1cbebee 151
b65233a9
JR		 152u16 amd_iommu_last_bdf; /* largest PCI device id we have
153 to handle */
2e22847f 154LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
b65233a9 155 we find in ACPI */
621a5f7a 156bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
928abd25 157
2e22847f 158LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
b65233a9 159 system */
928abd25 160
bb52777e
JR		 161/* Array to assign indices to IOMMUs*/
162struct amd_iommu *amd_iommus[MAX_IOMMUS];
163int amd_iommus_present;
164
318afd41
JR		 165/* IOMMUs have a non-present cache? */
166bool amd_iommu_np_cache __read_mostly;
60f723b4 167bool amd_iommu_iotlb_sup __read_mostly = true;
318afd41 168
a919a018 169u32 amd_iommu_max_pasid __read_mostly = ~0;
62f71abb 170
400a28a0 171bool amd_iommu_v2_present __read_mostly;
4160cd9e 172static bool amd_iommu_pc_present __read_mostly;
400a28a0 173
5abcdba4
JR		 174bool amd_iommu_force_isolation __read_mostly;
175
aeb26f55
JR		 176/*
177 * List of protection domains - used during resume
178 */
179LIST_HEAD(amd_iommu_pd_list);
180spinlock_t amd_iommu_pd_lock;
181
b65233a9
JR		 182/*
183 * Pointer to the device table which is shared by all AMD IOMMUs
184 * it is indexed by the PCI device id or the HT unit id and contains
185 * information about the domain the device belongs to as well as the
186 * page table root pointer.
187 */
928abd25 188struct dev_table_entry *amd_iommu_dev_table;
b65233a9
JR		 189
190/*
191 * The alias table is a driver specific data structure which contains the
192 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
193 * More than one device can share the same requestor id.
194 */
928abd25 195u16 *amd_iommu_alias_table;
b65233a9
JR		 196
197/*
198 * The rlookup table is used to find the IOMMU which is responsible
199 * for a specific device. It is also indexed by the PCI device id.
200 */
928abd25 201struct amd_iommu **amd_iommu_rlookup_table;
b65233a9 202
b65233a9 203/*
0ea2c422
JR		 204 * This table is used to find the irq remapping table for a given device id
205 * quickly.
206 */
207struct irq_remap_table **irq_lookup_table;
208
b65233a9 209/*
df805abb 210 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
b65233a9
JR		 211 * to know which ones are already in use.
212 */
928abd25
JR		 213unsigned long *amd_iommu_pd_alloc_bitmap;
214
b65233a9
JR		 215static u32 dev_table_size; /* size of the device table */
216static u32 alias_table_size; /* size of the alias table */
217static u32 rlookup_table_size; /* size if the rlookup table */
3e8064ba 218
2c0ae172
JR		 219enum iommu_init_state {
220 IOMMU_START_STATE,
221 IOMMU_IVRS_DETECTED,
222 IOMMU_ACPI_FINISHED,
223 IOMMU_ENABLED,
224 IOMMU_PCI_INIT,
225 IOMMU_INTERRUPTS_EN,
226 IOMMU_DMA_OPS,
227 IOMMU_INITIALIZED,
228 IOMMU_NOT_FOUND,
229 IOMMU_INIT_ERROR,
230};
231
235dacbc
JR		 232/* Early ioapic and hpet maps from kernel command line */
233#define EARLY_MAP_SIZE 4
234static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
235static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
2a0cb4e2
WZ		 236static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
237
235dacbc
JR		 238static int __initdata early_ioapic_map_size;
239static int __initdata early_hpet_map_size;
2a0cb4e2
WZ		 240static int __initdata early_acpihid_map_size;
241
dfbb6d47 242static bool __initdata cmdline_maps;
235dacbc 243
2c0ae172
JR		 244static enum iommu_init_state init_state = IOMMU_START_STATE;
245
ae295142 246static int amd_iommu_enable_interrupts(void);
2c0ae172 247static int __init iommu_go_to_state(enum iommu_init_state state);
aafd8ba0 248static void init_device_table_dma(void);
3d9761e7 249
38e45d02
SS		 250static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
251 u8 bank, u8 cntr, u8 fxn,
252 u64 *value, bool is_write);
253
208ec8c9
JR		 254static inline void update_last_devid(u16 devid)
255{
256 if (devid > amd_iommu_last_bdf)
257 amd_iommu_last_bdf = devid;
258}
259
c571484e
JR		 260static inline unsigned long tbl_size(int entry_size)
261{
262 unsigned shift = PAGE_SHIFT +
421f909c 263 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
c571484e
JR		 264
265 return 1UL << shift;
266}
267
5bcd757f
MG		 268/* Access to l1 and l2 indexed register spaces */
269
270static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
271{
272 u32 val;
273
274 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
275 pci_read_config_dword(iommu->dev, 0xfc, &val);
276 return val;
277}
278
279static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
280{
281 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
282 pci_write_config_dword(iommu->dev, 0xfc, val);
283 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
284}
285
286static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
287{
288 u32 val;
289
290 pci_write_config_dword(iommu->dev, 0xf0, address);
291 pci_read_config_dword(iommu->dev, 0xf4, &val);
292 return val;
293}
294
295static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
296{
297 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
298 pci_write_config_dword(iommu->dev, 0xf4, val);
299}
300
b65233a9
JR		 301/****************************************************************************
302 *
303 * AMD IOMMU MMIO register space handling functions
304 *
305 * These functions are used to program the IOMMU device registers in
306 * MMIO space required for that driver.
307 *
308 ****************************************************************************/
3e8064ba 309
b65233a9
JR		 310/*
311 * This function set the exclusion range in the IOMMU. DMA accesses to the
312 * exclusion range are passed through untranslated
313 */
05f92db9 314static void iommu_set_exclusion_range(struct amd_iommu *iommu)
b2026aa2
JR		 315{
316 u64 start = iommu->exclusion_start & PAGE_MASK;
317 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
318 u64 entry;
319
320 if (!iommu->exclusion_start)
321 return;
322
323 entry = start | MMIO_EXCL_ENABLE_MASK;
324 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
325 &entry, sizeof(entry));
326
327 entry = limit;
328 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
329 &entry, sizeof(entry));
330}
331
b65233a9 332/* Programs the physical address of the device table into the IOMMU hardware */
6b7f000e 333static void iommu_set_device_table(struct amd_iommu *iommu)
b2026aa2 334{
f609891f 335 u64 entry;
b2026aa2
JR		 336
337 BUG_ON(iommu->mmio_base == NULL);
338
339 entry = virt_to_phys(amd_iommu_dev_table);
340 entry |= (dev_table_size >> 12) - 1;
341 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
342 &entry, sizeof(entry));
343}
344
b65233a9 345/* Generic functions to enable/disable certain features of the IOMMU. */
05f92db9 346static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 347{
348 u32 ctrl;
349
350 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
351 ctrl |= (1 << bit);
352 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
353}
354
ca020711 355static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 356{
357 u32 ctrl;
358
199d0d50 359 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
b2026aa2
JR		 360 ctrl &= ~(1 << bit);
361 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
362}
363
1456e9d2
JR		 364static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
365{
366 u32 ctrl;
367
368 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
369 ctrl &= ~CTRL_INV_TO_MASK;
370 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
371 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
372}
373
b65233a9 374/* Function to enable the hardware */
05f92db9 375static void iommu_enable(struct amd_iommu *iommu)
b2026aa2 376{
b2026aa2 377 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
b2026aa2
JR		 378}
379
92ac4320 380static void iommu_disable(struct amd_iommu *iommu)
126c52be 381{
a8c485bb
CW		 382 /* Disable command buffer */
383 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
384
385 /* Disable event logging and event interrupts */
386 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
387 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
388
389 /* Disable IOMMU hardware itself */
92ac4320 390 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
126c52be
JR		 391}
392
b65233a9
JR		 393/*
394 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
395 * the system has one.
396 */
30861ddc 397static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
6c56747b 398{
30861ddc
SK		 399 if (!request_mem_region(address, end, "amd_iommu")) {
400 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
401 address, end);
e82752d8 402 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
6c56747b 403 return NULL;
e82752d8 404 }
6c56747b 405
30861ddc 406 return (u8 __iomem *)ioremap_nocache(address, end);
6c56747b
JR		 407}
408
409static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
410{
411 if (iommu->mmio_base)
412 iounmap(iommu->mmio_base);
30861ddc 413 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
6c56747b
JR		 414}
415
ac7ccf67
SS		 416static inline u32 get_ivhd_header_size(struct ivhd_header *h)
417{
418 u32 size = 0;
419
420 switch (h->type) {
421 case 0x10:
422 size = 24;
423 break;
424 case 0x11:
425 case 0x40:
426 size = 40;
427 break;
428 }
429 return size;
430}
431
b65233a9
JR		 432/****************************************************************************
433 *
434 * The functions below belong to the first pass of AMD IOMMU ACPI table
435 * parsing. In this pass we try to find out the highest device id this
436 * code has to handle. Upon this information the size of the shared data
437 * structures is determined later.
438 *
439 ****************************************************************************/
440
b514e555
JR		 441/*
442 * This function calculates the length of a given IVHD entry
443 */
444static inline int ivhd_entry_length(u8 *ivhd)
445{
8c7142f5
SS		 446 u32 type = ((struct ivhd_entry *)ivhd)->type;
447
448 if (type < 0x80) {
449 return 0x04 << (*ivhd >> 6);
450 } else if (type == IVHD_DEV_ACPI_HID) {
451 /* For ACPI_HID, offset 21 is uid len */
452 return *((u8 *)ivhd + 21) + 22;
453 }
454 return 0;
b514e555
JR		 455}
456
b65233a9
JR		 457/*
458 * After reading the highest device id from the IOMMU PCI capability header
459 * this function looks if there is a higher device id defined in the ACPI table
460 */
3e8064ba
JR		 461static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
462{
463 u8 *p = (void *)h, *end = (void *)h;
464 struct ivhd_entry *dev;
465
ac7ccf67
SS		 466 u32 ivhd_size = get_ivhd_header_size(h);
467
468 if (!ivhd_size) {
469 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
470 return -EINVAL;
471 }
472
473 p += ivhd_size;
3e8064ba
JR		 474 end += h->length;
475
3e8064ba
JR		 476 while (p < end) {
477 dev = (struct ivhd_entry *)p;
478 switch (dev->type) {
d1259416
JR		 479 case IVHD_DEV_ALL:
480 /* Use maximum BDF value for DEV_ALL */
481 update_last_devid(0xffff);
482 break;
3e8064ba
JR		 483 case IVHD_DEV_SELECT:
484 case IVHD_DEV_RANGE_END:
485 case IVHD_DEV_ALIAS:
486 case IVHD_DEV_EXT_SELECT:
b65233a9 487 /* all the above subfield types refer to device ids */
208ec8c9 488 update_last_devid(dev->devid);
3e8064ba
JR		 489 break;
490 default:
491 break;
492 }
b514e555 493 p += ivhd_entry_length(p);
3e8064ba
JR		 494 }
495
496 WARN_ON(p != end);
497
498 return 0;
499}
500
8c7142f5
SS		 501static int __init check_ivrs_checksum(struct acpi_table_header *table)
502{
503 int i;
504 u8 checksum = 0, *p = (u8 *)table;
505
506 for (i = 0; i < table->length; ++i)
507 checksum += p[i];
508 if (checksum != 0) {
509 /* ACPI table corrupt */
510 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
511 return -ENODEV;
512 }
513
514 return 0;
515}
516
b65233a9
JR		 517/*
518 * Iterate over all IVHD entries in the ACPI table and find the highest device
519 * id which we need to handle. This is the first of three functions which parse
520 * the ACPI table. So we check the checksum here.
521 */
3e8064ba
JR		 522static int __init find_last_devid_acpi(struct acpi_table_header *table)
523{
8c7142f5 524 u8 *p = (u8 *)table, *end = (u8 *)table;
3e8064ba
JR		 525 struct ivhd_header *h;
526
3e8064ba
JR		 527 p += IVRS_HEADER_LENGTH;
528
529 end += table->length;
530 while (p < end) {
531 h = (struct ivhd_header *)p;
8c7142f5
SS		 532 if (h->type == amd_iommu_target_ivhd_type) {
533 int ret = find_last_devid_from_ivhd(h);
534
535 if (ret)
536 return ret;
3e8064ba
JR		 537 }
538 p += h->length;
539 }
540 WARN_ON(p != end);
541
542 return 0;
543}
544
b65233a9
JR		 545/****************************************************************************
546 *
df805abb 547 * The following functions belong to the code path which parses the ACPI table
b65233a9
JR		 548 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
549 * data structures, initialize the device/alias/rlookup table and also
550 * basically initialize the hardware.
551 *
552 ****************************************************************************/
553
554/*
555 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
556 * write commands to that buffer later and the IOMMU will execute them
557 * asynchronously
558 */
f2c2db53 559static int __init alloc_command_buffer(struct amd_iommu *iommu)
b36ca91e 560{
f2c2db53
JR		 561 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
562 get_order(CMD_BUFFER_SIZE));
b36ca91e 563
f2c2db53 564 return iommu->cmd_buf ? 0 : -ENOMEM;
58492e12
JR		 565}
566
93f1cc67
JR		 567/*
568 * This function resets the command buffer if the IOMMU stopped fetching
569 * commands from it.
570 */
571void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
572{
573 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
574
575 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
576 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
577
578 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
579}
580
58492e12
JR		 581/*
582 * This function writes the command buffer address to the hardware and
583 * enables it.
584 */
585static void iommu_enable_command_buffer(struct amd_iommu *iommu)
586{
587 u64 entry;
588
589 BUG_ON(iommu->cmd_buf == NULL);
590
591 entry = (u64)virt_to_phys(iommu->cmd_buf);
b36ca91e 592 entry |= MMIO_CMD_SIZE_512;
58492e12 593
b36ca91e 594 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
58492e12 595 &entry, sizeof(entry));
b36ca91e 596
93f1cc67 597 amd_iommu_reset_cmd_buffer(iommu);
b36ca91e
JR		 598}
599
600static void __init free_command_buffer(struct amd_iommu *iommu)
601{
deba4bce 602 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
b36ca91e
JR		 603}
604
335503e5 605/* allocates the memory where the IOMMU will log its events to */
f2c2db53 606static int __init alloc_event_buffer(struct amd_iommu *iommu)
335503e5 607{
f2c2db53
JR		 608 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
609 get_order(EVT_BUFFER_SIZE));
335503e5 610
f2c2db53 611 return iommu->evt_buf ? 0 : -ENOMEM;
58492e12
JR		 612}
613
614static void iommu_enable_event_buffer(struct amd_iommu *iommu)
615{
616 u64 entry;
617
618 BUG_ON(iommu->evt_buf == NULL);
619
335503e5 620 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
58492e12 621
335503e5
JR		 622 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
623 &entry, sizeof(entry));
624
09067207
JR		 625 /* set head and tail to zero manually */
626 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
627 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
628
58492e12 629 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
335503e5
JR		 630}
631
632static void __init free_event_buffer(struct amd_iommu *iommu)
633{
634 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
635}
636
1a29ac01 637/* allocates the memory where the IOMMU will log its events to */
f2c2db53 638static int __init alloc_ppr_log(struct amd_iommu *iommu)
1a29ac01 639{
f2c2db53
JR		 640 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
641 get_order(PPR_LOG_SIZE));
1a29ac01 642
f2c2db53 643 return iommu->ppr_log ? 0 : -ENOMEM;
1a29ac01
JR		 644}
645
646static void iommu_enable_ppr_log(struct amd_iommu *iommu)
647{
648 u64 entry;
649
650 if (iommu->ppr_log == NULL)
651 return;
652
653 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
654
655 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
656 &entry, sizeof(entry));
657
658 /* set head and tail to zero manually */
659 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
660 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
661
662 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
663 iommu_feature_enable(iommu, CONTROL_PPR_EN);
664}
665
666static void __init free_ppr_log(struct amd_iommu *iommu)
667{
668 if (iommu->ppr_log == NULL)
669 return;
670
671 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
672}
673
cbc33a90
JR		 674static void iommu_enable_gt(struct amd_iommu *iommu)
675{
676 if (!iommu_feature(iommu, FEATURE_GT))
677 return;
678
679 iommu_feature_enable(iommu, CONTROL_GT_EN);
680}
681
b65233a9 682/* sets a specific bit in the device table entry. */
3566b778
JR		 683static void set_dev_entry_bit(u16 devid, u8 bit)
684{
ee6c2868
JR		 685 int i = (bit >> 6) & 0x03;
686 int _bit = bit & 0x3f;
3566b778 687
ee6c2868 688 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
3566b778
JR		 689}
690
c5cca146
JR		 691static int get_dev_entry_bit(u16 devid, u8 bit)
692{
ee6c2868
JR		 693 int i = (bit >> 6) & 0x03;
694 int _bit = bit & 0x3f;
c5cca146 695
ee6c2868 696 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
c5cca146
JR		 697}
698
699
700void amd_iommu_apply_erratum_63(u16 devid)
701{
702 int sysmgt;
703
704 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
705 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
706
707 if (sysmgt == 0x01)
708 set_dev_entry_bit(devid, DEV_ENTRY_IW);
709}
710
5ff4789d
JR		 711/* Writes the specific IOMMU for a device into the rlookup table */
712static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
713{
714 amd_iommu_rlookup_table[devid] = iommu;
715}
716
b65233a9
JR		 717/*
718 * This function takes the device specific flags read from the ACPI
719 * table and sets up the device table entry with that information
720 */
5ff4789d
JR		 721static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
722 u16 devid, u32 flags, u32 ext_flags)
3566b778
JR		 723{
724 if (flags & ACPI_DEVFLAG_INITPASS)
725 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
726 if (flags & ACPI_DEVFLAG_EXTINT)
727 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
728 if (flags & ACPI_DEVFLAG_NMI)
729 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
730 if (flags & ACPI_DEVFLAG_SYSMGT1)
731 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
732 if (flags & ACPI_DEVFLAG_SYSMGT2)
733 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
734 if (flags & ACPI_DEVFLAG_LINT0)
735 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
736 if (flags & ACPI_DEVFLAG_LINT1)
737 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
3566b778 738
c5cca146
JR		 739 amd_iommu_apply_erratum_63(devid);
740
5ff4789d 741 set_iommu_for_device(iommu, devid);
3566b778
JR		 742}
743
c50e3247 744static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
6efed63b
JR		 745{
746 struct devid_map *entry;
747 struct list_head *list;
748
31cff67f
JR		 749 if (type == IVHD_SPECIAL_IOAPIC)
750 list = &ioapic_map;
751 else if (type == IVHD_SPECIAL_HPET)
752 list = &hpet_map;
753 else
6efed63b
JR		 754 return -EINVAL;
755
31cff67f
JR		 756 list_for_each_entry(entry, list, list) {
757 if (!(entry->id == id && entry->cmd_line))
758 continue;
759
760 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
761 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
762
c50e3247
JR		 763 *devid = entry->devid;
764
31cff67f
JR		 765 return 0;
766 }
767
6efed63b
JR		 768 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
769 if (!entry)
770 return -ENOMEM;
771
31cff67f 772 entry->id = id;
c50e3247 773 entry->devid = *devid;
31cff67f 774 entry->cmd_line = cmd_line;
6efed63b
JR		 775
776 list_add_tail(&entry->list, list);
777
778 return 0;
779}
780
2a0cb4e2
WZ		 781static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
782 bool cmd_line)
783{
784 struct acpihid_map_entry *entry;
785 struct list_head *list = &acpihid_map;
786
787 list_for_each_entry(entry, list, list) {
788 if (strcmp(entry->hid, hid) ||
789 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
790 !entry->cmd_line)
791 continue;
792
793 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
794 hid, uid);
795 *devid = entry->devid;
796 return 0;
797 }
798
799 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
800 if (!entry)
801 return -ENOMEM;
802
803 memcpy(entry->uid, uid, strlen(uid));
804 memcpy(entry->hid, hid, strlen(hid));
805 entry->devid = *devid;
806 entry->cmd_line = cmd_line;
807 entry->root_devid = (entry->devid & (~0x7));
808
809 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
810 entry->cmd_line ? "cmd" : "ivrs",
811 entry->hid, entry->uid, entry->root_devid);
812
813 list_add_tail(&entry->list, list);
814 return 0;
815}
816
235dacbc
JR		 817static int __init add_early_maps(void)
818{
819 int i, ret;
820
821 for (i = 0; i < early_ioapic_map_size; ++i) {
822 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
823 early_ioapic_map[i].id,
c50e3247 824 &early_ioapic_map[i].devid,
235dacbc
JR		 825 early_ioapic_map[i].cmd_line);
826 if (ret)
827 return ret;
828 }
829
830 for (i = 0; i < early_hpet_map_size; ++i) {
831 ret = add_special_device(IVHD_SPECIAL_HPET,
832 early_hpet_map[i].id,
c50e3247 833 &early_hpet_map[i].devid,
235dacbc
JR		 834 early_hpet_map[i].cmd_line);
835 if (ret)
836 return ret;
837 }
838
2a0cb4e2
WZ		 839 for (i = 0; i < early_acpihid_map_size; ++i) {
840 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
841 early_acpihid_map[i].uid,
842 &early_acpihid_map[i].devid,
843 early_acpihid_map[i].cmd_line);
844 if (ret)
845 return ret;
846 }
847
235dacbc
JR		 848 return 0;
849}
850
b65233a9 851/*
df805abb 852 * Reads the device exclusion range from ACPI and initializes the IOMMU with
b65233a9
JR		 853 * it
854 */
3566b778
JR		 855static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
856{
857 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
858
859 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
860 return;
861
862 if (iommu) {
b65233a9
JR		 863 /*
864 * We only can configure exclusion ranges per IOMMU, not
865 * per device. But we can enable the exclusion range per
866 * device. This is done here
867 */
2c16c9fd 868 set_dev_entry_bit(devid, DEV_ENTRY_EX);
3566b778
JR		 869 iommu->exclusion_start = m->range_start;
870 iommu->exclusion_length = m->range_length;
871 }
872}
873
b65233a9
JR		 874/*
875 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
876 * initializes the hardware and our data structures with it.
877 */
6efed63b 878static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
5d0c8e49
JR		 879 struct ivhd_header *h)
880{
881 u8 *p = (u8 *)h;
882 u8 *end = p, flags = 0;
0de66d5b
JR		 883 u16 devid = 0, devid_start = 0, devid_to = 0;
884 u32 dev_i, ext_flags = 0;
58a3bee5 885 bool alias = false;
5d0c8e49 886 struct ivhd_entry *e;
ac7ccf67 887 u32 ivhd_size;
235dacbc
JR		 888 int ret;
889
890
891 ret = add_early_maps();
892 if (ret)
893 return ret;
5d0c8e49
JR		 894
895 /*
e9bf5197 896 * First save the recommended feature enable bits from ACPI
5d0c8e49 897 */
e9bf5197 898 iommu->acpi_flags = h->flags;
5d0c8e49
JR		 899
900 /*
901 * Done. Now parse the device entries
902 */
ac7ccf67
SS		 903 ivhd_size = get_ivhd_header_size(h);
904 if (!ivhd_size) {
905 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
906 return -EINVAL;
907 }
908
909 p += ivhd_size;
910
5d0c8e49
JR		 911 end += h->length;
912
42a698f4 913
5d0c8e49
JR		 914 while (p < end) {
915 e = (struct ivhd_entry *)p;
916 switch (e->type) {
917 case IVHD_DEV_ALL:
42a698f4 918
226e889b 919 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
42a698f4 920
226e889b
JR		 921 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
922 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
5d0c8e49
JR		 923 break;
924 case IVHD_DEV_SELECT:
42a698f4
JR		 925
926 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
927 "flags: %02x\n",
c5081cd7 928 PCI_BUS_NUM(e->devid),
42a698f4
JR		 929 PCI_SLOT(e->devid),
930 PCI_FUNC(e->devid),
931 e->flags);
932
5d0c8e49 933 devid = e->devid;
5ff4789d 934 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
5d0c8e49
JR		 935 break;
936 case IVHD_DEV_SELECT_RANGE_START:
42a698f4
JR		 937
938 DUMP_printk(" DEV_SELECT_RANGE_START\t "
939 "devid: %02x:%02x.%x flags: %02x\n",
c5081cd7 940 PCI_BUS_NUM(e->devid),
42a698f4
JR		 941 PCI_SLOT(e->devid),
942 PCI_FUNC(e->devid),
943 e->flags);
944
5d0c8e49
JR		 945 devid_start = e->devid;
946 flags = e->flags;
947 ext_flags = 0;
58a3bee5 948 alias = false;
5d0c8e49
JR		 949 break;
950 case IVHD_DEV_ALIAS:
42a698f4
JR		 951
952 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
953 "flags: %02x devid_to: %02x:%02x.%x\n",
c5081cd7 954 PCI_BUS_NUM(e->devid),
42a698f4
JR		 955 PCI_SLOT(e->devid),
956 PCI_FUNC(e->devid),
957 e->flags,
c5081cd7 958 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 959 PCI_SLOT(e->ext >> 8),
960 PCI_FUNC(e->ext >> 8));
961
5d0c8e49
JR		 962 devid = e->devid;
963 devid_to = e->ext >> 8;
7a6a3a08 964 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
7455aab1 965 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
5d0c8e49
JR		 966 amd_iommu_alias_table[devid] = devid_to;
967 break;
968 case IVHD_DEV_ALIAS_RANGE:
42a698f4
JR		 969
970 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
971 "devid: %02x:%02x.%x flags: %02x "
972 "devid_to: %02x:%02x.%x\n",
c5081cd7 973 PCI_BUS_NUM(e->devid),
42a698f4
JR		 974 PCI_SLOT(e->devid),
975 PCI_FUNC(e->devid),
976 e->flags,
c5081cd7 977 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 978 PCI_SLOT(e->ext >> 8),
979 PCI_FUNC(e->ext >> 8));
980
5d0c8e49
JR		 981 devid_start = e->devid;
982 flags = e->flags;
983 devid_to = e->ext >> 8;
984 ext_flags = 0;
58a3bee5 985 alias = true;
5d0c8e49
JR		 986 break;
987 case IVHD_DEV_EXT_SELECT:
42a698f4
JR		 988
989 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
990 "flags: %02x ext: %08x\n",
c5081cd7 991 PCI_BUS_NUM(e->devid),
42a698f4
JR		 992 PCI_SLOT(e->devid),
993 PCI_FUNC(e->devid),
994 e->flags, e->ext);
995
5d0c8e49 996 devid = e->devid;
5ff4789d
JR		 997 set_dev_entry_from_acpi(iommu, devid, e->flags,
998 e->ext);
5d0c8e49
JR		 999 break;
1000 case IVHD_DEV_EXT_SELECT_RANGE:
42a698f4
JR		 1001
1002 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1003 "%02x:%02x.%x flags: %02x ext: %08x\n",
c5081cd7 1004 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1005 PCI_SLOT(e->devid),
1006 PCI_FUNC(e->devid),
1007 e->flags, e->ext);
1008
5d0c8e49
JR		 1009 devid_start = e->devid;
1010 flags = e->flags;
1011 ext_flags = e->ext;
58a3bee5 1012 alias = false;
5d0c8e49
JR		 1013 break;
1014 case IVHD_DEV_RANGE_END:
42a698f4
JR		 1015
1016 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
c5081cd7 1017 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1018 PCI_SLOT(e->devid),
1019 PCI_FUNC(e->devid));
1020
5d0c8e49
JR		 1021 devid = e->devid;
1022 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
7a6a3a08 1023 if (alias) {
5d0c8e49 1024 amd_iommu_alias_table[dev_i] = devid_to;
7a6a3a08
JR		 1025 set_dev_entry_from_acpi(iommu,
1026 devid_to, flags, ext_flags);
1027 }
1028 set_dev_entry_from_acpi(iommu, dev_i,
1029 flags, ext_flags);
5d0c8e49
JR		 1030 }
1031 break;
6efed63b
JR		 1032 case IVHD_DEV_SPECIAL: {
1033 u8 handle, type;
1034 const char *var;
1035 u16 devid;
1036 int ret;
1037
1038 handle = e->ext & 0xff;
1039 devid = (e->ext >> 8) & 0xffff;
1040 type = (e->ext >> 24) & 0xff;
1041
1042 if (type == IVHD_SPECIAL_IOAPIC)
1043 var = "IOAPIC";
1044 else if (type == IVHD_SPECIAL_HPET)
1045 var = "HPET";
1046 else
1047 var = "UNKNOWN";
1048
1049 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1050 var, (int)handle,
c5081cd7 1051 PCI_BUS_NUM(devid),
6efed63b
JR		 1052 PCI_SLOT(devid),
1053 PCI_FUNC(devid));
1054
c50e3247 1055 ret = add_special_device(type, handle, &devid, false);
6efed63b
JR		 1056 if (ret)
1057 return ret;
c50e3247
JR		 1058
1059 /*
1060 * add_special_device might update the devid in case a
1061 * command-line override is present. So call
1062 * set_dev_entry_from_acpi after add_special_device.
1063 */
1064 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1065
6efed63b
JR		 1066 break;
1067 }
2a0cb4e2
WZ		 1068 case IVHD_DEV_ACPI_HID: {
1069 u16 devid;
1070 u8 hid[ACPIHID_HID_LEN] = {0};
1071 u8 uid[ACPIHID_UID_LEN] = {0};
1072 int ret;
1073
1074 if (h->type != 0x40) {
1075 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1076 e->type);
1077 break;
1078 }
1079
1080 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1081 hid[ACPIHID_HID_LEN - 1] = '\0';
1082
1083 if (!(*hid)) {
1084 pr_err(FW_BUG "Invalid HID.\n");
1085 break;
1086 }
1087
1088 switch (e->uidf) {
1089 case UID_NOT_PRESENT:
1090
1091 if (e->uidl != 0)
1092 pr_warn(FW_BUG "Invalid UID length.\n");
1093
1094 break;
1095 case UID_IS_INTEGER:
1096
1097 sprintf(uid, "%d", e->uid);
1098
1099 break;
1100 case UID_IS_CHARACTER:
1101
1102 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1103 uid[ACPIHID_UID_LEN - 1] = '\0';
1104
1105 break;
1106 default:
1107 break;
1108 }
1109
1110 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1111 hid, uid,
1112 PCI_BUS_NUM(devid),
1113 PCI_SLOT(devid),
1114 PCI_FUNC(devid));
1115
1116 devid = e->devid;
1117 flags = e->flags;
1118
1119 ret = add_acpi_hid_device(hid, uid, &devid, false);
1120 if (ret)
1121 return ret;
1122
1123 /*
1124 * add_special_device might update the devid in case a
1125 * command-line override is present. So call
1126 * set_dev_entry_from_acpi after add_special_device.
1127 */
1128 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1129
1130 break;
1131 }
5d0c8e49
JR		 1132 default:
1133 break;
1134 }
1135
b514e555 1136 p += ivhd_entry_length(p);
5d0c8e49 1137 }
6efed63b
JR		 1138
1139 return 0;
5d0c8e49
JR		 1140}
1141
e47d402d
JR		 1142static void __init free_iommu_one(struct amd_iommu *iommu)
1143{
1144 free_command_buffer(iommu);
335503e5 1145 free_event_buffer(iommu);
1a29ac01 1146 free_ppr_log(iommu);
e47d402d
JR		 1147 iommu_unmap_mmio_space(iommu);
1148}
1149
1150static void __init free_iommu_all(void)
1151{
1152 struct amd_iommu *iommu, *next;
1153
3bd22172 1154 for_each_iommu_safe(iommu, next) {
e47d402d
JR		 1155 list_del(&iommu->list);
1156 free_iommu_one(iommu);
1157 kfree(iommu);
1158 }
1159}
1160
318fe782
SS		 1161/*
1162 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1163 * Workaround:
1164 * BIOS should disable L2B micellaneous clock gating by setting
1165 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1166 */
e2f1a3bd 1167static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
318fe782
SS		 1168{
1169 u32 value;
1170
1171 if ((boot_cpu_data.x86 != 0x15) ||
1172 (boot_cpu_data.x86_model < 0x10) ||
1173 (boot_cpu_data.x86_model > 0x1f))
1174 return;
1175
1176 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1177 pci_read_config_dword(iommu->dev, 0xf4, &value);
1178
1179 if (value & BIT(2))
1180 return;
1181
1182 /* Select NB indirect register 0x90 and enable writing */
1183 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1184
1185 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1186 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1187 dev_name(&iommu->dev->dev));
1188
1189 /* Clear the enable writing bit */
1190 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1191}
1192
358875fd
JC		 1193/*
1194 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1195 * Workaround:
1196 * BIOS should enable ATS write permission check by setting
1197 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1198 */
1199static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1200{
1201 u32 value;
1202
1203 if ((boot_cpu_data.x86 != 0x15) ||
1204 (boot_cpu_data.x86_model < 0x30) ||
1205 (boot_cpu_data.x86_model > 0x3f))
1206 return;
1207
1208 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1209 value = iommu_read_l2(iommu, 0x47);
1210
1211 if (value & BIT(0))
1212 return;
1213
1214 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1215 iommu_write_l2(iommu, 0x47, value | BIT(0));
1216
1217 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1218 dev_name(&iommu->dev->dev));
1219}
1220
b65233a9
JR		 1221/*
1222 * This function clues the initialization function for one IOMMU
1223 * together and also allocates the command buffer and programs the
1224 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1225 */
e47d402d
JR		 1226static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1227{
6efed63b
JR		 1228 int ret;
1229
e47d402d 1230 spin_lock_init(&iommu->lock);
bb52777e
JR		 1231
1232 /* Add IOMMU to internal data structures */
e47d402d 1233 list_add_tail(&iommu->list, &amd_iommu_list);
bb52777e
JR		 1234 iommu->index = amd_iommus_present++;
1235
1236 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1237 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1238 return -ENOSYS;
1239 }
1240
1241 /* Index is fine - add IOMMU to the array */
1242 amd_iommus[iommu->index] = iommu;
e47d402d
JR		 1243
1244 /*
1245 * Copy data from ACPI table entry to the iommu struct
1246 */
23c742db 1247 iommu->devid = h->devid;
e47d402d 1248 iommu->cap_ptr = h->cap_ptr;
ee893c24 1249 iommu->pci_seg = h->pci_seg;
e47d402d 1250 iommu->mmio_phys = h->mmio_phys;
30861ddc 1251
7d7d38af
SS		 1252 switch (h->type) {
1253 case 0x10:
1254 /* Check if IVHD EFR contains proper max banks/counters */
1255 if ((h->efr_attr != 0) &&
1256 ((h->efr_attr & (0xF << 13)) != 0) &&
1257 ((h->efr_attr & (0x3F << 17)) != 0))
1258 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1259 else
1260 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1261 break;
1262 case 0x11:
1263 case 0x40:
1264 if (h->efr_reg & (1 << 9))
1265 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1266 else
1267 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1268 break;
1269 default:
1270 return -EINVAL;
30861ddc
SK		 1271 }
1272
1273 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1274 iommu->mmio_phys_end);
e47d402d
JR		 1275 if (!iommu->mmio_base)
1276 return -ENOMEM;
1277
f2c2db53 1278 if (alloc_command_buffer(iommu))
e47d402d
JR		 1279 return -ENOMEM;
1280
f2c2db53 1281 if (alloc_event_buffer(iommu))
335503e5
JR		 1282 return -ENOMEM;
1283
a80dc3e0
JR		 1284 iommu->int_enabled = false;
1285
6efed63b
JR		 1286 ret = init_iommu_from_acpi(iommu, h);
1287 if (ret)
1288 return ret;
f6fec00a 1289
7c71d306
JL		 1290 ret = amd_iommu_create_irq_domain(iommu);
1291 if (ret)
1292 return ret;
1293
f6fec00a
JR		 1294 /*
1295 * Make sure IOMMU is not considered to translate itself. The IVRS
1296 * table tells us so, but this is a lie!
1297 */
1298 amd_iommu_rlookup_table[iommu->devid] = NULL;
1299
23c742db 1300 return 0;
e47d402d
JR		 1301}
1302
8c7142f5
SS		 1303/**
1304 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1305 * @ivrs Pointer to the IVRS header
1306 *
1307 * This function search through all IVDB of the maximum supported IVHD
1308 */
1309static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1310{
1311 u8 *base = (u8 *)ivrs;
1312 struct ivhd_header *ivhd = (struct ivhd_header *)
1313 (base + IVRS_HEADER_LENGTH);
1314 u8 last_type = ivhd->type;
1315 u16 devid = ivhd->devid;
1316
1317 while (((u8 *)ivhd - base < ivrs->length) &&
1318 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1319 u8 *p = (u8 *) ivhd;
1320
1321 if (ivhd->devid == devid)
1322 last_type = ivhd->type;
1323 ivhd = (struct ivhd_header *)(p + ivhd->length);
1324 }
1325
1326 return last_type;
1327}
1328
b65233a9
JR		 1329/*
1330 * Iterates over all IOMMU entries in the ACPI table, allocates the
1331 * IOMMU structure and initializes it with init_iommu_one()
1332 */
e47d402d
JR		 1333static int __init init_iommu_all(struct acpi_table_header *table)
1334{
1335 u8 *p = (u8 *)table, *end = (u8 *)table;
1336 struct ivhd_header *h;
1337 struct amd_iommu *iommu;
1338 int ret;
1339
e47d402d
JR		 1340 end += table->length;
1341 p += IVRS_HEADER_LENGTH;
1342
1343 while (p < end) {
1344 h = (struct ivhd_header *)p;
8c7142f5 1345 if (*p == amd_iommu_target_ivhd_type) {
9c72041f 1346
ae908c22 1347 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
9c72041f 1348 "seg: %d flags: %01x info %04x\n",
c5081cd7 1349 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
9c72041f
JR		 1350 PCI_FUNC(h->devid), h->cap_ptr,
1351 h->pci_seg, h->flags, h->info);
1352 DUMP_printk(" mmio-addr: %016llx\n",
1353 h->mmio_phys);
1354
e47d402d 1355 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
02f3b3f5
JR		 1356 if (iommu == NULL)
1357 return -ENOMEM;
3551a708 1358
e47d402d 1359 ret = init_iommu_one(iommu, h);
02f3b3f5
JR		 1360 if (ret)
1361 return ret;
e47d402d
JR		 1362 }
1363 p += h->length;
1364
1365 }
1366 WARN_ON(p != end);
1367
1368 return 0;
1369}
1370
30861ddc
SK		 1371
1372static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1373{
1374 u64 val = 0xabcd, val2 = 0;
1375
1376 if (!iommu_feature(iommu, FEATURE_PC))
1377 return;
1378
1379 amd_iommu_pc_present = true;
1380
1381 /* Check if the performance counters can be written to */
38e45d02
SS		 1382 if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
1383 (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
30861ddc
SK		 1384 (val != val2)) {
1385 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1386 amd_iommu_pc_present = false;
1387 return;
1388 }
1389
1390 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1391
1392 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1393 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1394 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1395}
1396
066f2e98
AW		 1397static ssize_t amd_iommu_show_cap(struct device *dev,
1398 struct device_attribute *attr,
1399 char *buf)
1400{
1401 struct amd_iommu *iommu = dev_get_drvdata(dev);
1402 return sprintf(buf, "%x\n", iommu->cap);
1403}
1404static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1405
1406static ssize_t amd_iommu_show_features(struct device *dev,
1407 struct device_attribute *attr,
1408 char *buf)
1409{
1410 struct amd_iommu *iommu = dev_get_drvdata(dev);
1411 return sprintf(buf, "%llx\n", iommu->features);
1412}
1413static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1414
1415static struct attribute *amd_iommu_attrs[] = {
1416 &dev_attr_cap.attr,
1417 &dev_attr_features.attr,
1418 NULL,
1419};
1420
1421static struct attribute_group amd_iommu_group = {
1422 .name = "amd-iommu",
1423 .attrs = amd_iommu_attrs,
1424};
1425
1426static const struct attribute_group *amd_iommu_groups[] = {
1427 &amd_iommu_group,
1428 NULL,
1429};
30861ddc 1430
23c742db
JR		 1431static int iommu_init_pci(struct amd_iommu *iommu)
1432{
1433 int cap_ptr = iommu->cap_ptr;
1434 u32 range, misc, low, high;
1435
c5081cd7 1436 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
23c742db
JR		 1437 iommu->devid & 0xff);
1438 if (!iommu->dev)
1439 return -ENODEV;
1440
cbbc00be
JL		 1441 /* Prevent binding other PCI device drivers to IOMMU devices */
1442 iommu->dev->match_driver = false;
1443
23c742db
JR		 1444 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1445 &iommu->cap);
1446 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1447 &range);
1448 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1449 &misc);
1450
23c742db
JR		 1451 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1452 amd_iommu_iotlb_sup = false;
1453
1454 /* read extended feature bits */
1455 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1456 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1457
1458 iommu->features = ((u64)high << 32) | low;
1459
1460 if (iommu_feature(iommu, FEATURE_GT)) {
1461 int glxval;
a919a018
SS		 1462 u32 max_pasid;
1463 u64 pasmax;
23c742db 1464
a919a018
SS		 1465 pasmax = iommu->features & FEATURE_PASID_MASK;
1466 pasmax >>= FEATURE_PASID_SHIFT;
1467 max_pasid = (1 << (pasmax + 1)) - 1;
23c742db 1468
a919a018
SS		 1469 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1470
1471 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
23c742db
JR		 1472
1473 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1474 glxval >>= FEATURE_GLXVAL_SHIFT;
1475
1476 if (amd_iommu_max_glx_val == -1)
1477 amd_iommu_max_glx_val = glxval;
1478 else
1479 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1480 }
1481
1482 if (iommu_feature(iommu, FEATURE_GT) &&
1483 iommu_feature(iommu, FEATURE_PPR)) {
1484 iommu->is_iommu_v2 = true;
1485 amd_iommu_v2_present = true;
1486 }
1487
f2c2db53
JR		 1488 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1489 return -ENOMEM;
23c742db
JR		 1490
1491 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1492 amd_iommu_np_cache = true;
1493
30861ddc
SK		 1494 init_iommu_perf_ctr(iommu);
1495
23c742db
JR		 1496 if (is_rd890_iommu(iommu->dev)) {
1497 int i, j;
1498
1499 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1500 PCI_DEVFN(0, 0));
1501
1502 /*
1503 * Some rd890 systems may not be fully reconfigured by the
1504 * BIOS, so it's necessary for us to store this information so
1505 * it can be reprogrammed on resume
1506 */
1507 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1508 &iommu->stored_addr_lo);
1509 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1510 &iommu->stored_addr_hi);
1511
1512 /* Low bit locks writes to configuration space */
1513 iommu->stored_addr_lo &= ~1;
1514
1515 for (i = 0; i < 6; i++)
1516 for (j = 0; j < 0x12; j++)
1517 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1518
1519 for (i = 0; i < 0x83; i++)
1520 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1521 }
1522
318fe782 1523 amd_iommu_erratum_746_workaround(iommu);
358875fd 1524 amd_iommu_ats_write_check_workaround(iommu);
318fe782 1525
066f2e98
AW		 1526 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
1527 amd_iommu_groups, "ivhd%d",
1528 iommu->index);
1529
23c742db
JR		 1530 return pci_enable_device(iommu->dev);
1531}
1532
4d121c32
JR		 1533static void print_iommu_info(void)
1534{
1535 static const char * const feat_str[] = {
1536 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1537 "IA", "GA", "HE", "PC"
1538 };
1539 struct amd_iommu *iommu;
1540
1541 for_each_iommu(iommu) {
1542 int i;
1543
1544 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1545 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1546
1547 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1548 pr_info("AMD-Vi: Extended features: ");
2bd5ed00 1549 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
4d121c32
JR		 1550 if (iommu_feature(iommu, (1ULL << i)))
1551 pr_cont(" %s", feat_str[i]);
1552 }
30861ddc 1553 pr_cont("\n");
500c25ed 1554 }
4d121c32 1555 }
ebe60bbf
JR		 1556 if (irq_remapping_enabled)
1557 pr_info("AMD-Vi: Interrupt remapping enabled\n");
4d121c32
JR		 1558}
1559
2c0ae172 1560static int __init amd_iommu_init_pci(void)
23c742db
JR		 1561{
1562 struct amd_iommu *iommu;
1563 int ret = 0;
1564
1565 for_each_iommu(iommu) {
1566 ret = iommu_init_pci(iommu);
1567 if (ret)
1568 break;
1569 }
1570
aafd8ba0
JR		 1571 init_device_table_dma();
1572
1573 for_each_iommu(iommu)
1574 iommu_flush_all_caches(iommu);
1575
3a18404c 1576 ret = amd_iommu_init_api();
23c742db 1577
3a18404c
JR		 1578 if (!ret)
1579 print_iommu_info();
4d121c32 1580
23c742db
JR		 1581 return ret;
1582}
1583
a80dc3e0
JR		 1584/****************************************************************************
1585 *
1586 * The following functions initialize the MSI interrupts for all IOMMUs
df805abb 1587 * in the system. It's a bit challenging because there could be multiple
a80dc3e0
JR		 1588 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1589 * pci_dev.
1590 *
1591 ****************************************************************************/
1592
9f800de3 1593static int iommu_setup_msi(struct amd_iommu *iommu)
a80dc3e0
JR		 1594{
1595 int r;
a80dc3e0 1596
9ddd592a
JR		 1597 r = pci_enable_msi(iommu->dev);
1598 if (r)
1599 return r;
a80dc3e0 1600
72fe00f0
JR		 1601 r = request_threaded_irq(iommu->dev->irq,
1602 amd_iommu_int_handler,
1603 amd_iommu_int_thread,
1604 0, "AMD-Vi",
3f398bc7 1605 iommu);
a80dc3e0
JR		 1606
1607 if (r) {
1608 pci_disable_msi(iommu->dev);
9ddd592a 1609 return r;
a80dc3e0
JR		 1610 }
1611
fab6afa3 1612 iommu->int_enabled = true;
1a29ac01 1613
a80dc3e0
JR		 1614 return 0;
1615}
1616
05f92db9 1617static int iommu_init_msi(struct amd_iommu *iommu)
a80dc3e0 1618{
9ddd592a
JR		 1619 int ret;
1620
a80dc3e0 1621 if (iommu->int_enabled)
9ddd592a 1622 goto enable_faults;
a80dc3e0 1623
82fcfc67 1624 if (iommu->dev->msi_cap)
9ddd592a
JR		 1625 ret = iommu_setup_msi(iommu);
1626 else
1627 ret = -ENODEV;
1628
1629 if (ret)
1630 return ret;
a80dc3e0 1631
9ddd592a
JR		 1632enable_faults:
1633 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
a80dc3e0 1634
9ddd592a
JR		 1635 if (iommu->ppr_log != NULL)
1636 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1637
1638 return 0;
a80dc3e0
JR		 1639}
1640
b65233a9
JR		 1641/****************************************************************************
1642 *
1643 * The next functions belong to the third pass of parsing the ACPI
1644 * table. In this last pass the memory mapping requirements are
df805abb 1645 * gathered (like exclusion and unity mapping ranges).
b65233a9
JR		 1646 *
1647 ****************************************************************************/
1648
be2a022c
JR		 1649static void __init free_unity_maps(void)
1650{
1651 struct unity_map_entry *entry, *next;
1652
1653 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1654 list_del(&entry->list);
1655 kfree(entry);
1656 }
1657}
1658
b65233a9 1659/* called when we find an exclusion range definition in ACPI */
be2a022c
JR		 1660static int __init init_exclusion_range(struct ivmd_header *m)
1661{
1662 int i;
1663
1664 switch (m->type) {
1665 case ACPI_IVMD_TYPE:
1666 set_device_exclusion_range(m->devid, m);
1667 break;
1668 case ACPI_IVMD_TYPE_ALL:
3a61ec38 1669 for (i = 0; i <= amd_iommu_last_bdf; ++i)
be2a022c
JR		 1670 set_device_exclusion_range(i, m);
1671 break;
1672 case ACPI_IVMD_TYPE_RANGE:
1673 for (i = m->devid; i <= m->aux; ++i)
1674 set_device_exclusion_range(i, m);
1675 break;
1676 default:
1677 break;
1678 }
1679
1680 return 0;
1681}
1682
b65233a9 1683/* called for unity map ACPI definition */
be2a022c
JR		 1684static int __init init_unity_map_range(struct ivmd_header *m)
1685{
98f1ad25 1686 struct unity_map_entry *e = NULL;
02acc43a 1687 char *s;
be2a022c
JR		 1688
1689 e = kzalloc(sizeof(*e), GFP_KERNEL);
1690 if (e == NULL)
1691 return -ENOMEM;
1692
1693 switch (m->type) {
1694 default:
0bc252f4
JR		 1695 kfree(e);
1696 return 0;
be2a022c 1697 case ACPI_IVMD_TYPE:
02acc43a 1698 s = "IVMD_TYPEi\t\t\t";
be2a022c
JR		 1699 e->devid_start = e->devid_end = m->devid;
1700 break;
1701 case ACPI_IVMD_TYPE_ALL:
02acc43a 1702 s = "IVMD_TYPE_ALL\t\t";
be2a022c
JR		 1703 e->devid_start = 0;
1704 e->devid_end = amd_iommu_last_bdf;
1705 break;
1706 case ACPI_IVMD_TYPE_RANGE:
02acc43a 1707 s = "IVMD_TYPE_RANGE\t\t";
be2a022c
JR		 1708 e->devid_start = m->devid;
1709 e->devid_end = m->aux;
1710 break;
1711 }
1712 e->address_start = PAGE_ALIGN(m->range_start);
1713 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1714 e->prot = m->flags >> 1;
1715
02acc43a
JR		 1716 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1717 " range_start: %016llx range_end: %016llx flags: %x\n", s,
c5081cd7
SK		 1718 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1719 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
02acc43a
JR		 1720 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1721 e->address_start, e->address_end, m->flags);
1722
be2a022c
JR		 1723 list_add_tail(&e->list, &amd_iommu_unity_map);
1724
1725 return 0;
1726}
1727
b65233a9 1728/* iterates over all memory definitions we find in the ACPI table */
be2a022c
JR		 1729static int __init init_memory_definitions(struct acpi_table_header *table)
1730{
1731 u8 *p = (u8 *)table, *end = (u8 *)table;
1732 struct ivmd_header *m;
1733
be2a022c
JR		 1734 end += table->length;
1735 p += IVRS_HEADER_LENGTH;
1736
1737 while (p < end) {
1738 m = (struct ivmd_header *)p;
1739 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1740 init_exclusion_range(m);
1741 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1742 init_unity_map_range(m);
1743
1744 p += m->length;
1745 }
1746
1747 return 0;
1748}
1749
9f5f5fb3
JR		 1750/*
1751 * Init the device table to not allow DMA access for devices and
1752 * suppress all page faults
1753 */
33f28c59 1754static void init_device_table_dma(void)
9f5f5fb3 1755{
0de66d5b 1756 u32 devid;
9f5f5fb3
JR		 1757
1758 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1759 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1760 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
9f5f5fb3
JR		 1761 }
1762}
1763
d04e0ba3
JR		 1764static void __init uninit_device_table_dma(void)
1765{
1766 u32 devid;
1767
1768 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1769 amd_iommu_dev_table[devid].data[0] = 0ULL;
1770 amd_iommu_dev_table[devid].data[1] = 0ULL;
1771 }
1772}
1773
33f28c59
JR		 1774static void init_device_table(void)
1775{
1776 u32 devid;
1777
1778 if (!amd_iommu_irq_remap)
1779 return;
1780
1781 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1782 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1783}
1784
e9bf5197
JR		 1785static void iommu_init_flags(struct amd_iommu *iommu)
1786{
1787 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1788 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1789 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1790
1791 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1792 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1793 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1794
1795 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1796 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1797 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1798
1799 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1800 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1801 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1802
1803 /*
1804 * make IOMMU memory accesses cache coherent
1805 */
1806 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1456e9d2
JR		 1807
1808 /* Set IOTLB invalidation timeout to 1s */
1809 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
e9bf5197
JR		 1810}
1811
5bcd757f 1812static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
4c894f47 1813{
5bcd757f
MG		 1814 int i, j;
1815 u32 ioc_feature_control;
c1bf94ec 1816 struct pci_dev *pdev = iommu->root_pdev;
5bcd757f
MG		 1817
1818 /* RD890 BIOSes may not have completely reconfigured the iommu */
c1bf94ec 1819 if (!is_rd890_iommu(iommu->dev) || !pdev)
5bcd757f
MG		 1820 return;
1821
1822 /*
1823 * First, we need to ensure that the iommu is enabled. This is
1824 * controlled by a register in the northbridge
1825 */
5bcd757f
MG		 1826
1827 /* Select Northbridge indirect register 0x75 and enable writing */
1828 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1829 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1830
1831 /* Enable the iommu */
1832 if (!(ioc_feature_control & 0x1))
1833 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1834
5bcd757f
MG		 1835 /* Restore the iommu BAR */
1836 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1837 iommu->stored_addr_lo);
1838 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1839 iommu->stored_addr_hi);
1840
1841 /* Restore the l1 indirect regs for each of the 6 l1s */
1842 for (i = 0; i < 6; i++)
1843 for (j = 0; j < 0x12; j++)
1844 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1845
1846 /* Restore the l2 indirect regs */
1847 for (i = 0; i < 0x83; i++)
1848 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1849
1850 /* Lock PCI setup registers */
1851 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1852 iommu->stored_addr_lo | 1);
4c894f47
JR		 1853}
1854
b65233a9
JR		 1855/*
1856 * This function finally enables all IOMMUs found in the system after
1857 * they have been initialized
1858 */
11ee5ac4 1859static void early_enable_iommus(void)
8736197b
JR		 1860{
1861 struct amd_iommu *iommu;
1862
3bd22172 1863 for_each_iommu(iommu) {
a8c485bb 1864 iommu_disable(iommu);
e9bf5197 1865 iommu_init_flags(iommu);
58492e12
JR		 1866 iommu_set_device_table(iommu);
1867 iommu_enable_command_buffer(iommu);
1868 iommu_enable_event_buffer(iommu);
8736197b
JR		 1869 iommu_set_exclusion_range(iommu);
1870 iommu_enable(iommu);
7d0c5cc5 1871 iommu_flush_all_caches(iommu);
8736197b
JR		 1872 }
1873}
1874
11ee5ac4
JR		 1875static void enable_iommus_v2(void)
1876{
1877 struct amd_iommu *iommu;
1878
1879 for_each_iommu(iommu) {
1880 iommu_enable_ppr_log(iommu);
1881 iommu_enable_gt(iommu);
1882 }
1883}
1884
1885static void enable_iommus(void)
1886{
1887 early_enable_iommus();
1888
1889 enable_iommus_v2();
1890}
1891
92ac4320
JR		 1892static void disable_iommus(void)
1893{
1894 struct amd_iommu *iommu;
1895
1896 for_each_iommu(iommu)
1897 iommu_disable(iommu);
1898}
1899
7441e9cb
JR		 1900/*
1901 * Suspend/Resume support
1902 * disable suspend until real resume implemented
1903 */
1904
f3c6ea1b 1905static void amd_iommu_resume(void)
7441e9cb 1906{
5bcd757f
MG		 1907 struct amd_iommu *iommu;
1908
1909 for_each_iommu(iommu)
1910 iommu_apply_resume_quirks(iommu);
1911
736501ee
JR		 1912 /* re-load the hardware */
1913 enable_iommus();
3d9761e7
JR		 1914
1915 amd_iommu_enable_interrupts();
7441e9cb
JR		 1916}
1917
f3c6ea1b 1918static int amd_iommu_suspend(void)
7441e9cb 1919{
736501ee
JR		 1920 /* disable IOMMUs to go out of the way for BIOS */
1921 disable_iommus();
1922
1923 return 0;
7441e9cb
JR		 1924}
1925
f3c6ea1b 1926static struct syscore_ops amd_iommu_syscore_ops = {
7441e9cb
JR		 1927 .suspend = amd_iommu_suspend,
1928 .resume = amd_iommu_resume,
1929};
1930
8704a1ba
JR		 1931static void __init free_on_init_error(void)
1932{
0ea2c422
JR		 1933 free_pages((unsigned long)irq_lookup_table,
1934 get_order(rlookup_table_size));
8704a1ba 1935
a591989a
JL		 1936 kmem_cache_destroy(amd_iommu_irq_cache);
1937 amd_iommu_irq_cache = NULL;
8704a1ba
JR		 1938
1939 free_pages((unsigned long)amd_iommu_rlookup_table,
1940 get_order(rlookup_table_size));
1941
1942 free_pages((unsigned long)amd_iommu_alias_table,
1943 get_order(alias_table_size));
1944
1945 free_pages((unsigned long)amd_iommu_dev_table,
1946 get_order(dev_table_size));
1947
1948 free_iommu_all();
1949
8704a1ba
JR		 1950#ifdef CONFIG_GART_IOMMU
1951 /*
1952 * We failed to initialize the AMD IOMMU - try fallback to GART
1953 * if possible.
1954 */
1955 gart_iommu_init();
1956
1957#endif
1958}
1959
c2ff5cf5
JR		 1960/* SB IOAPIC is always on this device in AMD systems */
1961#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1962
eb1eb7ae
JR		 1963static bool __init check_ioapic_information(void)
1964{
dfbb6d47 1965 const char *fw_bug = FW_BUG;
c2ff5cf5 1966 bool ret, has_sb_ioapic;
eb1eb7ae
JR		 1967 int idx;
1968
c2ff5cf5
JR		 1969 has_sb_ioapic = false;
1970 ret = false;
eb1eb7ae 1971
dfbb6d47
JR		 1972 /*
1973 * If we have map overrides on the kernel command line the
1974 * messages in this function might not describe firmware bugs
1975 * anymore - so be careful
1976 */
1977 if (cmdline_maps)
1978 fw_bug = "";
1979
c2ff5cf5
JR		 1980 for (idx = 0; idx < nr_ioapics; idx++) {
1981 int devid, id = mpc_ioapic_id(idx);
1982
1983 devid = get_ioapic_devid(id);
1984 if (devid < 0) {
dfbb6d47
JR		 1985 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
1986 fw_bug, id);
c2ff5cf5
JR		 1987 ret = false;
1988 } else if (devid == IOAPIC_SB_DEVID) {
1989 has_sb_ioapic = true;
1990 ret = true;
eb1eb7ae
JR		 1991 }
1992 }
1993
c2ff5cf5
JR		 1994 if (!has_sb_ioapic) {
1995 /*
1996 * We expect the SB IOAPIC to be listed in the IVRS
1997 * table. The system timer is connected to the SB IOAPIC
1998 * and if we don't have it in the list the system will
1999 * panic at boot time. This situation usually happens
2000 * when the BIOS is buggy and provides us the wrong
2001 * device id for the IOAPIC in the system.
2002 */
dfbb6d47 2003 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
c2ff5cf5
JR		 2004 }
2005
2006 if (!ret)
dfbb6d47 2007 pr_err("AMD-Vi: Disabling interrupt remapping\n");
c2ff5cf5
JR		 2008
2009 return ret;
eb1eb7ae
JR		 2010}
2011
d04e0ba3
JR		 2012static void __init free_dma_resources(void)
2013{
d04e0ba3
JR		 2014 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2015 get_order(MAX_DOMAIN_ID/8));
2016
2017 free_unity_maps();
2018}
2019
b65233a9 2020/*
8704a1ba
JR		 2021 * This is the hardware init function for AMD IOMMU in the system.
2022 * This function is called either from amd_iommu_init or from the interrupt
2023 * remapping setup code.
b65233a9
JR		 2024 *
2025 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
8c7142f5 2026 * four times:
b65233a9 2027 *
8c7142f5
SS		 2028 * 1 pass) Discover the most comprehensive IVHD type to use.
2029 *
2030 * 2 pass) Find the highest PCI device id the driver has to handle.
b65233a9
JR		 2031 * Upon this information the size of the data structures is
2032 * determined that needs to be allocated.
2033 *
8c7142f5 2034 * 3 pass) Initialize the data structures just allocated with the
b65233a9
JR		 2035 * information in the ACPI table about available AMD IOMMUs
2036 * in the system. It also maps the PCI devices in the
2037 * system to specific IOMMUs
2038 *
8c7142f5 2039 * 4 pass) After the basic data structures are allocated and
b65233a9
JR		 2040 * initialized we update them with information about memory
2041 * remapping requirements parsed out of the ACPI table in
2042 * this last pass.
2043 *
8704a1ba
JR		 2044 * After everything is set up the IOMMUs are enabled and the necessary
2045 * hotplug and suspend notifiers are registered.
b65233a9 2046 */
643511b3 2047static int __init early_amd_iommu_init(void)
fe74c9cf 2048{
02f3b3f5
JR		 2049 struct acpi_table_header *ivrs_base;
2050 acpi_size ivrs_size;
2051 acpi_status status;
fe74c9cf
JR		 2052 int i, ret = 0;
2053
643511b3 2054 if (!amd_iommu_detected)
8704a1ba
JR		 2055 return -ENODEV;
2056
02f3b3f5
JR		 2057 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2058 if (status == AE_NOT_FOUND)
2059 return -ENODEV;
2060 else if (ACPI_FAILURE(status)) {
2061 const char *err = acpi_format_exception(status);
2062 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2063 return -EINVAL;
2064 }
2065
8c7142f5
SS		 2066 /*
2067 * Validate checksum here so we don't need to do it when
2068 * we actually parse the table
2069 */
2070 ret = check_ivrs_checksum(ivrs_base);
2071 if (ret)
2072 return ret;
2073
2074 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2075 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2076
fe74c9cf
JR		 2077 /*
2078 * First parse ACPI tables to find the largest Bus/Dev/Func
2079 * we need to handle. Upon this information the shared data
2080 * structures for the IOMMUs in the system will be allocated
2081 */
2c0ae172
JR		 2082 ret = find_last_devid_acpi(ivrs_base);
2083 if (ret)
3551a708
JR		 2084 goto out;
2085
c571484e
JR		 2086 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2087 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2088 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
fe74c9cf 2089
fe74c9cf 2090 /* Device table - directly used by all IOMMUs */
8704a1ba 2091 ret = -ENOMEM;
5dc8bff0 2092 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2093 get_order(dev_table_size));
2094 if (amd_iommu_dev_table == NULL)
2095 goto out;
2096
2097 /*
2098 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2099 * IOMMU see for that device
2100 */
2101 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2102 get_order(alias_table_size));
2103 if (amd_iommu_alias_table == NULL)
2c0ae172 2104 goto out;
fe74c9cf
JR		 2105
2106 /* IOMMU rlookup table - find the IOMMU for a specific device */
83fd5cc6
JR		 2107 amd_iommu_rlookup_table = (void *)__get_free_pages(
2108 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2109 get_order(rlookup_table_size));
2110 if (amd_iommu_rlookup_table == NULL)
2c0ae172 2111 goto out;
fe74c9cf 2112
5dc8bff0
JR		 2113 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2114 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2115 get_order(MAX_DOMAIN_ID/8));
2116 if (amd_iommu_pd_alloc_bitmap == NULL)
2c0ae172 2117 goto out;
fe74c9cf
JR		 2118
2119 /*
5dc8bff0 2120 * let all alias entries point to itself
fe74c9cf 2121 */
3a61ec38 2122 for (i = 0; i <= amd_iommu_last_bdf; ++i)
fe74c9cf
JR		 2123 amd_iommu_alias_table[i] = i;
2124
fe74c9cf
JR		 2125 /*
2126 * never allocate domain 0 because its used as the non-allocated and
2127 * error value placeholder
2128 */
2129 amd_iommu_pd_alloc_bitmap[0] = 1;
2130
aeb26f55
JR		 2131 spin_lock_init(&amd_iommu_pd_lock);
2132
fe74c9cf
JR		 2133 /*
2134 * now the data structures are allocated and basically initialized
2135 * start the real acpi table scan
2136 */
02f3b3f5
JR		 2137 ret = init_iommu_all(ivrs_base);
2138 if (ret)
2c0ae172 2139 goto out;
fe74c9cf 2140
eb1eb7ae
JR		 2141 if (amd_iommu_irq_remap)
2142 amd_iommu_irq_remap = check_ioapic_information();
2143
05152a04
JR		 2144 if (amd_iommu_irq_remap) {
2145 /*
2146 * Interrupt remapping enabled, create kmem_cache for the
2147 * remapping tables.
2148 */
83ed9c13 2149 ret = -ENOMEM;
05152a04
JR		 2150 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2151 MAX_IRQS_PER_TABLE * sizeof(u32),
2152 IRQ_TABLE_ALIGNMENT,
2153 0, NULL);
2154 if (!amd_iommu_irq_cache)
2155 goto out;
0ea2c422
JR		 2156
2157 irq_lookup_table = (void *)__get_free_pages(
2158 GFP_KERNEL | __GFP_ZERO,
2159 get_order(rlookup_table_size));
2160 if (!irq_lookup_table)
2161 goto out;
05152a04
JR		 2162 }
2163
02f3b3f5
JR		 2164 ret = init_memory_definitions(ivrs_base);
2165 if (ret)
2c0ae172 2166 goto out;
3551a708 2167
eb1eb7ae
JR		 2168 /* init the device table */
2169 init_device_table();
2170
8704a1ba 2171out:
02f3b3f5
JR		 2172 /* Don't leak any ACPI memory */
2173 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2174 ivrs_base = NULL;
2175
643511b3
JR		 2176 return ret;
2177}
2178
ae295142 2179static int amd_iommu_enable_interrupts(void)
3d9761e7
JR		 2180{
2181 struct amd_iommu *iommu;
2182 int ret = 0;
2183
2184 for_each_iommu(iommu) {
2185 ret = iommu_init_msi(iommu);
2186 if (ret)
2187 goto out;
2188 }
2189
2190out:
2191 return ret;
2192}
2193
02f3b3f5
JR		 2194static bool detect_ivrs(void)
2195{
2196 struct acpi_table_header *ivrs_base;
2197 acpi_size ivrs_size;
2198 acpi_status status;
2199
2200 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2201 if (status == AE_NOT_FOUND)
2202 return false;
2203 else if (ACPI_FAILURE(status)) {
2204 const char *err = acpi_format_exception(status);
2205 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2206 return false;
2207 }
2208
2209 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2210
1adb7d31
JR		 2211 /* Make sure ACS will be enabled during PCI probe */
2212 pci_request_acs();
2213
02f3b3f5
JR		 2214 return true;
2215}
2216
2c0ae172 2217/****************************************************************************
8704a1ba 2218 *
2c0ae172
JR		 2219 * AMD IOMMU Initialization State Machine
2220 *
2221 ****************************************************************************/
2222
2223static int __init state_next(void)
8704a1ba
JR		 2224{
2225 int ret = 0;
2226
2c0ae172
JR		 2227 switch (init_state) {
2228 case IOMMU_START_STATE:
2229 if (!detect_ivrs()) {
2230 init_state = IOMMU_NOT_FOUND;
2231 ret = -ENODEV;
2232 } else {
2233 init_state = IOMMU_IVRS_DETECTED;
2234 }
2235 break;
2236 case IOMMU_IVRS_DETECTED:
2237 ret = early_amd_iommu_init();
2238 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2239 break;
2240 case IOMMU_ACPI_FINISHED:
2241 early_enable_iommus();
2242 register_syscore_ops(&amd_iommu_syscore_ops);
2243 x86_platform.iommu_shutdown = disable_iommus;
2244 init_state = IOMMU_ENABLED;
2245 break;
2246 case IOMMU_ENABLED:
2247 ret = amd_iommu_init_pci();
2248 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2249 enable_iommus_v2();
2250 break;
2251 case IOMMU_PCI_INIT:
2252 ret = amd_iommu_enable_interrupts();
2253 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2254 break;
2255 case IOMMU_INTERRUPTS_EN:
1e6a7b04 2256 ret = amd_iommu_init_dma_ops();
2c0ae172
JR		 2257 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2258 break;
2259 case IOMMU_DMA_OPS:
2260 init_state = IOMMU_INITIALIZED;
2261 break;
2262 case IOMMU_INITIALIZED:
2263 /* Nothing to do */
2264 break;
2265 case IOMMU_NOT_FOUND:
2266 case IOMMU_INIT_ERROR:
2267 /* Error states => do nothing */
2268 ret = -EINVAL;
2269 break;
2270 default:
2271 /* Unknown state */
2272 BUG();
2273 }
3d9761e7 2274
2c0ae172
JR		 2275 return ret;
2276}
7441e9cb 2277
2c0ae172
JR		 2278static int __init iommu_go_to_state(enum iommu_init_state state)
2279{
2280 int ret = 0;
f5325094 2281
2c0ae172
JR		 2282 while (init_state != state) {
2283 ret = state_next();
2284 if (init_state == IOMMU_NOT_FOUND ||
2285 init_state == IOMMU_INIT_ERROR)
2286 break;
2287 }
f2f12b6f 2288
fe74c9cf 2289 return ret;
2c0ae172 2290}
fe74c9cf 2291
6b474b82
JR		 2292#ifdef CONFIG_IRQ_REMAP
2293int __init amd_iommu_prepare(void)
2294{
3f4cb7c0
TG		 2295 int ret;
2296
7fa1c842 2297 amd_iommu_irq_remap = true;
84d07793 2298
3f4cb7c0
TG		 2299 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2300 if (ret)
2301 return ret;
2302 return amd_iommu_irq_remap ? 0 : -ENODEV;
6b474b82 2303}
d7f07769 2304
6b474b82
JR		 2305int __init amd_iommu_enable(void)
2306{
2307 int ret;
2308
2309 ret = iommu_go_to_state(IOMMU_ENABLED);
2310 if (ret)
2311 return ret;
d7f07769 2312
6b474b82 2313 irq_remapping_enabled = 1;
d7f07769 2314
6b474b82
JR		 2315 return 0;
2316}
2317
2318void amd_iommu_disable(void)
2319{
2320 amd_iommu_suspend();
2321}
2322
2323int amd_iommu_reenable(int mode)
2324{
2325 amd_iommu_resume();
2326
2327 return 0;
2328}
d7f07769 2329
6b474b82
JR		 2330int __init amd_iommu_enable_faulting(void)
2331{
2332 /* We enable MSI later when PCI is initialized */
2333 return 0;
2334}
2335#endif
d7f07769 2336
2c0ae172
JR		 2337/*
2338 * This is the core init function for AMD IOMMU hardware in the system.
2339 * This function is called from the generic x86 DMA layer initialization
2340 * code.
2341 */
2342static int __init amd_iommu_init(void)
2343{
2344 int ret;
2345
2346 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2347 if (ret) {
d04e0ba3
JR		 2348 free_dma_resources();
2349 if (!irq_remapping_enabled) {
2350 disable_iommus();
2351 free_on_init_error();
2352 } else {
2353 struct amd_iommu *iommu;
2354
2355 uninit_device_table_dma();
2356 for_each_iommu(iommu)
2357 iommu_flush_all_caches(iommu);
2358 }
2c0ae172
JR		 2359 }
2360
2361 return ret;
fe74c9cf
JR		 2362}
2363
b65233a9
JR		 2364/****************************************************************************
2365 *
2366 * Early detect code. This code runs at IOMMU detection time in the DMA
2367 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2368 * IOMMUs
2369 *
2370 ****************************************************************************/
480125ba 2371int __init amd_iommu_detect(void)
ae7877de 2372{
2c0ae172 2373 int ret;
02f3b3f5 2374
75f1cdf1 2375 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
480125ba 2376 return -ENODEV;
ae7877de 2377
a5235725 2378 if (amd_iommu_disabled)
480125ba 2379 return -ENODEV;
a5235725 2380
2c0ae172
JR		 2381 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2382 if (ret)
2383 return ret;
11bd04f6 2384
02f3b3f5
JR		 2385 amd_iommu_detected = true;
2386 iommu_detected = 1;
2387 x86_init.iommu.iommu_init = amd_iommu_init;
2388
4781bc42 2389 return 1;
ae7877de
JR		 2390}
2391
b65233a9
JR		 2392/****************************************************************************
2393 *
2394 * Parsing functions for the AMD IOMMU specific kernel command line
2395 * options.
2396 *
2397 ****************************************************************************/
2398
fefda117
JR		 2399static int __init parse_amd_iommu_dump(char *str)
2400{
2401 amd_iommu_dump = true;
2402
2403 return 1;
2404}
2405
918ad6c5
JR		 2406static int __init parse_amd_iommu_options(char *str)
2407{
2408 for (; *str; ++str) {
695b5676 2409 if (strncmp(str, "fullflush", 9) == 0)
afa9fdc2 2410 amd_iommu_unmap_flush = true;
a5235725
JR		 2411 if (strncmp(str, "off", 3) == 0)
2412 amd_iommu_disabled = true;
5abcdba4
JR		 2413 if (strncmp(str, "force_isolation", 15) == 0)
2414 amd_iommu_force_isolation = true;
918ad6c5
JR		 2415 }
2416
2417 return 1;
2418}
2419
440e8998
JR		 2420static int __init parse_ivrs_ioapic(char *str)
2421{
2422 unsigned int bus, dev, fn;
2423 int ret, id, i;
2424 u16 devid;
2425
2426 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2427
2428 if (ret != 4) {
2429 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2430 return 1;
2431 }
2432
2433 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2434 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2435 str);
2436 return 1;
2437 }
2438
2439 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2440
dfbb6d47 2441 cmdline_maps = true;
440e8998
JR		 2442 i = early_ioapic_map_size++;
2443 early_ioapic_map[i].id = id;
2444 early_ioapic_map[i].devid = devid;
2445 early_ioapic_map[i].cmd_line = true;
2446
2447 return 1;
2448}
2449
2450static int __init parse_ivrs_hpet(char *str)
2451{
2452 unsigned int bus, dev, fn;
2453 int ret, id, i;
2454 u16 devid;
2455
2456 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2457
2458 if (ret != 4) {
2459 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2460 return 1;
2461 }
2462
2463 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2464 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2465 str);
2466 return 1;
2467 }
2468
2469 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2470
dfbb6d47 2471 cmdline_maps = true;
440e8998
JR		 2472 i = early_hpet_map_size++;
2473 early_hpet_map[i].id = id;
2474 early_hpet_map[i].devid = devid;
2475 early_hpet_map[i].cmd_line = true;
2476
2477 return 1;
2478}
2479
ca3bf5d4
SS		 2480static int __init parse_ivrs_acpihid(char *str)
2481{
2482 u32 bus, dev, fn;
2483 char *hid, *uid, *p;
2484 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2485 int ret, i;
2486
2487 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2488 if (ret != 4) {
2489 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2490 return 1;
2491 }
2492
2493 p = acpiid;
2494 hid = strsep(&p, ":");
2495 uid = p;
2496
2497 if (!hid || !(*hid) || !uid) {
2498 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2499 return 1;
2500 }
2501
2502 i = early_acpihid_map_size++;
2503 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2504 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2505 early_acpihid_map[i].devid =
2506 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2507 early_acpihid_map[i].cmd_line = true;
2508
2509 return 1;
2510}
2511
440e8998
JR		 2512__setup("amd_iommu_dump", parse_amd_iommu_dump);
2513__setup("amd_iommu=", parse_amd_iommu_options);
2514__setup("ivrs_ioapic", parse_ivrs_ioapic);
2515__setup("ivrs_hpet", parse_ivrs_hpet);
ca3bf5d4 2516__setup("ivrs_acpihid", parse_ivrs_acpihid);
22e6daf4
KRW		 2517
2518IOMMU_INIT_FINISH(amd_iommu_detect,
2519 gart_iommu_hole_init,
98f1ad25
JR		 2520 NULL,
2521 NULL);
400a28a0
JR		 2522
2523bool amd_iommu_v2_supported(void)
2524{
2525 return amd_iommu_v2_present;
2526}
2527EXPORT_SYMBOL(amd_iommu_v2_supported);
30861ddc
SK		 2528
2529/****************************************************************************
2530 *
2531 * IOMMU EFR Performance Counter support functionality. This code allows
2532 * access to the IOMMU PC functionality.
2533 *
2534 ****************************************************************************/
2535
2536u8 amd_iommu_pc_get_max_banks(u16 devid)
2537{
2538 struct amd_iommu *iommu;
2539 u8 ret = 0;
2540
2541 /* locate the iommu governing the devid */
2542 iommu = amd_iommu_rlookup_table[devid];
2543 if (iommu)
2544 ret = iommu->max_banks;
2545
2546 return ret;
2547}
2548EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2549
2550bool amd_iommu_pc_supported(void)
2551{
2552 return amd_iommu_pc_present;
2553}
2554EXPORT_SYMBOL(amd_iommu_pc_supported);
2555
2556u8 amd_iommu_pc_get_max_counters(u16 devid)
2557{
2558 struct amd_iommu *iommu;
2559 u8 ret = 0;
2560
2561 /* locate the iommu governing the devid */
2562 iommu = amd_iommu_rlookup_table[devid];
2563 if (iommu)
2564 ret = iommu->max_counters;
2565
2566 return ret;
2567}
2568EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2569
38e45d02
SS		 2570static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
2571 u8 bank, u8 cntr, u8 fxn,
30861ddc
SK		 2572 u64 *value, bool is_write)
2573{
30861ddc
SK		 2574 u32 offset;
2575 u32 max_offset_lim;
2576
30861ddc 2577 /* Check for valid iommu and pc register indexing */
38e45d02 2578 if (WARN_ON((fxn > 0x28) || (fxn & 7)))
30861ddc
SK		 2579 return -ENODEV;
2580
2581 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2582
2583 /* Limit the offset to the hw defined mmio region aperture */
2584 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2585 (iommu->max_counters << 8) | 0x28);
2586 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2587 (offset > max_offset_lim))
2588 return -EINVAL;
2589
2590 if (is_write) {
2591 writel((u32)*value, iommu->mmio_base + offset);
2592 writel((*value >> 32), iommu->mmio_base + offset + 4);
2593 } else {
2594 *value = readl(iommu->mmio_base + offset + 4);
2595 *value <<= 32;
2596 *value = readl(iommu->mmio_base + offset);
2597 }
2598
2599 return 0;
2600}
2601EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
38e45d02
SS		 2602
2603int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2604 u64 *value, bool is_write)
2605{
2606 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2607
2608 /* Make sure the IOMMU PC resource is available */
2609 if (!amd_iommu_pc_present || iommu == NULL)
2610 return -ENODEV;
2611
2612 return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,
2613 value, is_write);
2614}
Linux 6.x block layer and io_uring tree(s)