Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
3b839a57 | 36 | #include <linux/dma-contiguous.h> |
7c71d306 | 37 | #include <linux/irqdomain.h> |
5f6bed50 | 38 | #include <linux/percpu.h> |
2b324506 JR |
39 | #include <asm/irq_remapping.h> |
40 | #include <asm/io_apic.h> | |
41 | #include <asm/apic.h> | |
42 | #include <asm/hw_irq.h> | |
17f5b569 | 43 | #include <asm/msidef.h> |
b6c02715 | 44 | #include <asm/proto.h> |
46a7fa27 | 45 | #include <asm/iommu.h> |
1d9b16d1 | 46 | #include <asm/gart.h> |
27c2127a | 47 | #include <asm/dma.h> |
403f81d8 JR |
48 | |
49 | #include "amd_iommu_proto.h" | |
50 | #include "amd_iommu_types.h" | |
6b474b82 | 51 | #include "irq_remapping.h" |
b6c02715 JR |
52 | |
53 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
54 | ||
815b33fd | 55 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 56 | |
aa3de9c0 OBC |
57 | /* |
58 | * This bitmap is used to advertise the page sizes our hardware support | |
59 | * to the IOMMU core, which will then use this information to split | |
60 | * physically contiguous memory regions it is mapping into page sizes | |
61 | * that we support. | |
62 | * | |
954e3dd8 | 63 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 64 | */ |
954e3dd8 | 65 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 66 | |
b6c02715 JR |
67 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
68 | ||
8fa5f802 JR |
69 | /* List of all available dev_data structures */ |
70 | static LIST_HEAD(dev_data_list); | |
71 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
72 | ||
6efed63b JR |
73 | LIST_HEAD(ioapic_map); |
74 | LIST_HEAD(hpet_map); | |
75 | ||
0feae533 JR |
76 | /* |
77 | * Domain for untranslated devices - only allocated | |
78 | * if iommu=pt passed on kernel cmd line. | |
79 | */ | |
b22f6434 | 80 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 81 | |
72e1dcc4 | 82 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 83 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 84 | |
ac1534a5 JR |
85 | static struct dma_map_ops amd_iommu_dma_ops; |
86 | ||
50917e26 JR |
87 | /* |
88 | * This struct contains device specific data for the IOMMU | |
89 | */ | |
90 | struct iommu_dev_data { | |
91 | struct list_head list; /* For domain->dev_list */ | |
92 | struct list_head dev_data_list; /* For global dev_data_list */ | |
50917e26 | 93 | struct protection_domain *domain; /* Domain the device is bound to */ |
50917e26 | 94 | u16 devid; /* PCI Device ID */ |
e3156048 | 95 | u16 alias; /* Alias Device ID */ |
50917e26 | 96 | bool iommu_v2; /* Device can make use of IOMMUv2 */ |
1e6a7b04 | 97 | bool passthrough; /* Device is identity mapped */ |
50917e26 JR |
98 | struct { |
99 | bool enabled; | |
100 | int qdep; | |
101 | } ats; /* ATS state */ | |
102 | bool pri_tlp; /* PASID TLB required for | |
103 | PPR completions */ | |
104 | u32 errata; /* Bitmap for errata to apply */ | |
105 | }; | |
106 | ||
431b2a20 JR |
107 | /* |
108 | * general struct to manage commands send to an IOMMU | |
109 | */ | |
d6449536 | 110 | struct iommu_cmd { |
b6c02715 JR |
111 | u32 data[4]; |
112 | }; | |
113 | ||
05152a04 JR |
114 | struct kmem_cache *amd_iommu_irq_cache; |
115 | ||
04bfdd84 | 116 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 117 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 118 | static void detach_device(struct device *dev); |
c1eee67b | 119 | |
007b74ba JR |
120 | /* |
121 | * For dynamic growth the aperture size is split into ranges of 128MB of | |
122 | * DMA address space each. This struct represents one such range. | |
123 | */ | |
124 | struct aperture_range { | |
125 | ||
08c5fb93 JR |
126 | spinlock_t bitmap_lock; |
127 | ||
007b74ba JR |
128 | /* address allocation bitmap */ |
129 | unsigned long *bitmap; | |
ae62d49c | 130 | unsigned long offset; |
60e6a7cb | 131 | unsigned long next_bit; |
007b74ba JR |
132 | |
133 | /* | |
134 | * Array of PTE pages for the aperture. In this array we save all the | |
135 | * leaf pages of the domain page table used for the aperture. This way | |
136 | * we don't need to walk the page table to find a specific PTE. We can | |
137 | * just calculate its address in constant time. | |
138 | */ | |
139 | u64 *pte_pages[64]; | |
007b74ba JR |
140 | }; |
141 | ||
142 | /* | |
143 | * Data container for a dma_ops specific protection domain | |
144 | */ | |
145 | struct dma_ops_domain { | |
146 | /* generic protection domain information */ | |
147 | struct protection_domain domain; | |
148 | ||
149 | /* size of the aperture for the mappings */ | |
150 | unsigned long aperture_size; | |
151 | ||
ebaecb42 | 152 | /* aperture index we start searching for free addresses */ |
5f6bed50 | 153 | u32 __percpu *next_index; |
007b74ba JR |
154 | |
155 | /* address space relevant data */ | |
156 | struct aperture_range *aperture[APERTURE_MAX_RANGES]; | |
007b74ba JR |
157 | }; |
158 | ||
15898bbc JR |
159 | /**************************************************************************** |
160 | * | |
161 | * Helper functions | |
162 | * | |
163 | ****************************************************************************/ | |
164 | ||
3f4b87b9 JR |
165 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
166 | { | |
167 | return container_of(dom, struct protection_domain, domain); | |
168 | } | |
169 | ||
e3156048 JR |
170 | static inline u16 get_device_id(struct device *dev) |
171 | { | |
172 | struct pci_dev *pdev = to_pci_dev(dev); | |
173 | ||
174 | return PCI_DEVID(pdev->bus->number, pdev->devfn); | |
175 | } | |
176 | ||
f62dda66 | 177 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
178 | { |
179 | struct iommu_dev_data *dev_data; | |
180 | unsigned long flags; | |
181 | ||
182 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
183 | if (!dev_data) | |
184 | return NULL; | |
185 | ||
f62dda66 | 186 | dev_data->devid = devid; |
8fa5f802 JR |
187 | |
188 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
189 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
190 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
191 | ||
192 | return dev_data; | |
193 | } | |
194 | ||
3b03bb74 JR |
195 | static struct iommu_dev_data *search_dev_data(u16 devid) |
196 | { | |
197 | struct iommu_dev_data *dev_data; | |
198 | unsigned long flags; | |
199 | ||
200 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
201 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
202 | if (dev_data->devid == devid) | |
203 | goto out_unlock; | |
204 | } | |
205 | ||
206 | dev_data = NULL; | |
207 | ||
208 | out_unlock: | |
209 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
210 | ||
211 | return dev_data; | |
212 | } | |
213 | ||
e3156048 JR |
214 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
215 | { | |
216 | *(u16 *)data = alias; | |
217 | return 0; | |
218 | } | |
219 | ||
220 | static u16 get_alias(struct device *dev) | |
221 | { | |
222 | struct pci_dev *pdev = to_pci_dev(dev); | |
223 | u16 devid, ivrs_alias, pci_alias; | |
224 | ||
225 | devid = get_device_id(dev); | |
226 | ivrs_alias = amd_iommu_alias_table[devid]; | |
227 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
228 | ||
229 | if (ivrs_alias == pci_alias) | |
230 | return ivrs_alias; | |
231 | ||
232 | /* | |
233 | * DMA alias showdown | |
234 | * | |
235 | * The IVRS is fairly reliable in telling us about aliases, but it | |
236 | * can't know about every screwy device. If we don't have an IVRS | |
237 | * reported alias, use the PCI reported alias. In that case we may | |
238 | * still need to initialize the rlookup and dev_table entries if the | |
239 | * alias is to a non-existent device. | |
240 | */ | |
241 | if (ivrs_alias == devid) { | |
242 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
243 | amd_iommu_rlookup_table[pci_alias] = | |
244 | amd_iommu_rlookup_table[devid]; | |
245 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
246 | amd_iommu_dev_table[devid].data, | |
247 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
248 | } | |
249 | ||
250 | return pci_alias; | |
251 | } | |
252 | ||
253 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
254 | "for device %s[%04x:%04x], kernel reported alias " | |
255 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
256 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
257 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
258 | PCI_FUNC(pci_alias)); | |
259 | ||
260 | /* | |
261 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
262 | * bus, then the IVRS table may know about a quirk that we don't. | |
263 | */ | |
264 | if (pci_alias == devid && | |
265 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
266 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
267 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
268 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
269 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
270 | dev_name(dev)); | |
271 | } | |
272 | ||
273 | return ivrs_alias; | |
274 | } | |
275 | ||
3b03bb74 JR |
276 | static struct iommu_dev_data *find_dev_data(u16 devid) |
277 | { | |
278 | struct iommu_dev_data *dev_data; | |
279 | ||
280 | dev_data = search_dev_data(devid); | |
281 | ||
282 | if (dev_data == NULL) | |
283 | dev_data = alloc_dev_data(devid); | |
284 | ||
285 | return dev_data; | |
286 | } | |
287 | ||
657cbb6b JR |
288 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
289 | { | |
290 | return dev->archdata.iommu; | |
291 | } | |
292 | ||
5abcdba4 JR |
293 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
294 | { | |
295 | static const int caps[] = { | |
296 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
297 | PCI_EXT_CAP_ID_PRI, |
298 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
299 | }; |
300 | int i, pos; | |
301 | ||
302 | for (i = 0; i < 3; ++i) { | |
303 | pos = pci_find_ext_capability(pdev, caps[i]); | |
304 | if (pos == 0) | |
305 | return false; | |
306 | } | |
307 | ||
308 | return true; | |
309 | } | |
310 | ||
6a113ddc JR |
311 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
312 | { | |
313 | struct iommu_dev_data *dev_data; | |
314 | ||
315 | dev_data = get_dev_data(&pdev->dev); | |
316 | ||
317 | return dev_data->errata & (1 << erratum) ? true : false; | |
318 | } | |
319 | ||
71c70984 | 320 | /* |
0bb6e243 JR |
321 | * This function actually applies the mapping to the page table of the |
322 | * dma_ops domain. | |
71c70984 | 323 | */ |
0bb6e243 JR |
324 | static void alloc_unity_mapping(struct dma_ops_domain *dma_dom, |
325 | struct unity_map_entry *e) | |
71c70984 | 326 | { |
0bb6e243 | 327 | u64 addr; |
71c70984 | 328 | |
0bb6e243 JR |
329 | for (addr = e->address_start; addr < e->address_end; |
330 | addr += PAGE_SIZE) { | |
331 | if (addr < dma_dom->aperture_size) | |
332 | __set_bit(addr >> PAGE_SHIFT, | |
333 | dma_dom->aperture[0]->bitmap); | |
71c70984 | 334 | } |
0bb6e243 | 335 | } |
71c70984 | 336 | |
0bb6e243 JR |
337 | /* |
338 | * Inits the unity mappings required for a specific device | |
339 | */ | |
340 | static void init_unity_mappings_for_device(struct device *dev, | |
341 | struct dma_ops_domain *dma_dom) | |
342 | { | |
343 | struct unity_map_entry *e; | |
344 | u16 devid; | |
71c70984 | 345 | |
0bb6e243 | 346 | devid = get_device_id(dev); |
71c70984 | 347 | |
0bb6e243 JR |
348 | list_for_each_entry(e, &amd_iommu_unity_map, list) { |
349 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
350 | continue; | |
351 | alloc_unity_mapping(dma_dom, e); | |
352 | } | |
71c70984 JR |
353 | } |
354 | ||
98fc5a69 JR |
355 | /* |
356 | * This function checks if the driver got a valid device from the caller to | |
357 | * avoid dereferencing invalid pointers. | |
358 | */ | |
359 | static bool check_device(struct device *dev) | |
360 | { | |
361 | u16 devid; | |
362 | ||
363 | if (!dev || !dev->dma_mask) | |
364 | return false; | |
365 | ||
b82a2272 YW |
366 | /* No PCI device */ |
367 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
368 | return false; |
369 | ||
370 | devid = get_device_id(dev); | |
371 | ||
372 | /* Out of our scope? */ | |
373 | if (devid > amd_iommu_last_bdf) | |
374 | return false; | |
375 | ||
376 | if (amd_iommu_rlookup_table[devid] == NULL) | |
377 | return false; | |
378 | ||
379 | return true; | |
380 | } | |
381 | ||
25b11ce2 | 382 | static void init_iommu_group(struct device *dev) |
2851db21 | 383 | { |
0bb6e243 JR |
384 | struct dma_ops_domain *dma_domain; |
385 | struct iommu_domain *domain; | |
2851db21 | 386 | struct iommu_group *group; |
2851db21 | 387 | |
65d5352f | 388 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
389 | if (IS_ERR(group)) |
390 | return; | |
391 | ||
392 | domain = iommu_group_default_domain(group); | |
393 | if (!domain) | |
394 | goto out; | |
395 | ||
396 | dma_domain = to_pdomain(domain)->priv; | |
397 | ||
398 | init_unity_mappings_for_device(dev, dma_domain); | |
399 | out: | |
400 | iommu_group_put(group); | |
eb9c9527 AW |
401 | } |
402 | ||
403 | static int iommu_init_device(struct device *dev) | |
404 | { | |
405 | struct pci_dev *pdev = to_pci_dev(dev); | |
406 | struct iommu_dev_data *dev_data; | |
eb9c9527 AW |
407 | |
408 | if (dev->archdata.iommu) | |
409 | return 0; | |
410 | ||
411 | dev_data = find_dev_data(get_device_id(dev)); | |
412 | if (!dev_data) | |
413 | return -ENOMEM; | |
414 | ||
e3156048 JR |
415 | dev_data->alias = get_alias(dev); |
416 | ||
5abcdba4 JR |
417 | if (pci_iommuv2_capable(pdev)) { |
418 | struct amd_iommu *iommu; | |
419 | ||
420 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
421 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
422 | } | |
423 | ||
657cbb6b JR |
424 | dev->archdata.iommu = dev_data; |
425 | ||
066f2e98 AW |
426 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
427 | dev); | |
428 | ||
657cbb6b JR |
429 | return 0; |
430 | } | |
431 | ||
26018874 JR |
432 | static void iommu_ignore_device(struct device *dev) |
433 | { | |
434 | u16 devid, alias; | |
435 | ||
436 | devid = get_device_id(dev); | |
e3156048 | 437 | alias = get_alias(dev); |
26018874 JR |
438 | |
439 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
440 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
441 | ||
442 | amd_iommu_rlookup_table[devid] = NULL; | |
443 | amd_iommu_rlookup_table[alias] = NULL; | |
444 | } | |
445 | ||
657cbb6b JR |
446 | static void iommu_uninit_device(struct device *dev) |
447 | { | |
c1931090 AW |
448 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
449 | ||
450 | if (!dev_data) | |
451 | return; | |
452 | ||
b6809ee5 JR |
453 | if (dev_data->domain) |
454 | detach_device(dev); | |
455 | ||
066f2e98 AW |
456 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
457 | dev); | |
458 | ||
9dcd6130 AW |
459 | iommu_group_remove_device(dev); |
460 | ||
aafd8ba0 JR |
461 | /* Remove dma-ops */ |
462 | dev->archdata.dma_ops = NULL; | |
463 | ||
8fa5f802 | 464 | /* |
c1931090 AW |
465 | * We keep dev_data around for unplugged devices and reuse it when the |
466 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 467 | */ |
657cbb6b | 468 | } |
b7cc9554 | 469 | |
7f26508b JR |
470 | #ifdef CONFIG_AMD_IOMMU_STATS |
471 | ||
472 | /* | |
473 | * Initialization code for statistics collection | |
474 | */ | |
475 | ||
da49f6df | 476 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 477 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 478 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 479 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 480 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 481 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 482 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 483 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 484 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 485 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 486 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 487 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
488 | DECLARE_STATS_COUNTER(complete_ppr); |
489 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
490 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
491 | DECLARE_STATS_COUNTER(pri_requests); | |
492 | ||
7f26508b | 493 | static struct dentry *stats_dir; |
7f26508b JR |
494 | static struct dentry *de_fflush; |
495 | ||
496 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
497 | { | |
498 | if (stats_dir == NULL) | |
499 | return; | |
500 | ||
501 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
502 | &cnt->value); | |
503 | } | |
504 | ||
505 | static void amd_iommu_stats_init(void) | |
506 | { | |
507 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
508 | if (stats_dir == NULL) | |
509 | return; | |
510 | ||
7f26508b | 511 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 512 | &amd_iommu_unmap_flush); |
da49f6df JR |
513 | |
514 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 515 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 516 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 517 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 518 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 519 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 520 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 521 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 522 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 523 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 524 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 525 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
526 | amd_iommu_stats_add(&complete_ppr); |
527 | amd_iommu_stats_add(&invalidate_iotlb); | |
528 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
529 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
530 | } |
531 | ||
532 | #endif | |
533 | ||
a80dc3e0 JR |
534 | /**************************************************************************** |
535 | * | |
536 | * Interrupt handling functions | |
537 | * | |
538 | ****************************************************************************/ | |
539 | ||
e3e59876 JR |
540 | static void dump_dte_entry(u16 devid) |
541 | { | |
542 | int i; | |
543 | ||
ee6c2868 JR |
544 | for (i = 0; i < 4; ++i) |
545 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
546 | amd_iommu_dev_table[devid].data[i]); |
547 | } | |
548 | ||
945b4ac4 JR |
549 | static void dump_command(unsigned long phys_addr) |
550 | { | |
551 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
552 | int i; | |
553 | ||
554 | for (i = 0; i < 4; ++i) | |
555 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
556 | } | |
557 | ||
a345b23b | 558 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 559 | { |
3d06fca8 JR |
560 | int type, devid, domid, flags; |
561 | volatile u32 *event = __evt; | |
562 | int count = 0; | |
563 | u64 address; | |
564 | ||
565 | retry: | |
566 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
567 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
568 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
569 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
570 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
571 | ||
572 | if (type == 0) { | |
573 | /* Did we hit the erratum? */ | |
574 | if (++count == LOOP_TIMEOUT) { | |
575 | pr_err("AMD-Vi: No event written to event log\n"); | |
576 | return; | |
577 | } | |
578 | udelay(1); | |
579 | goto retry; | |
580 | } | |
90008ee4 | 581 | |
4c6f40d4 | 582 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
583 | |
584 | switch (type) { | |
585 | case EVENT_TYPE_ILL_DEV: | |
586 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
587 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 588 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 589 | address, flags); |
e3e59876 | 590 | dump_dte_entry(devid); |
90008ee4 JR |
591 | break; |
592 | case EVENT_TYPE_IO_FAULT: | |
593 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
594 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 595 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
596 | domid, address, flags); |
597 | break; | |
598 | case EVENT_TYPE_DEV_TAB_ERR: | |
599 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
600 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 601 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
602 | address, flags); |
603 | break; | |
604 | case EVENT_TYPE_PAGE_TAB_ERR: | |
605 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
606 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 607 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
608 | domid, address, flags); |
609 | break; | |
610 | case EVENT_TYPE_ILL_CMD: | |
611 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 612 | dump_command(address); |
90008ee4 JR |
613 | break; |
614 | case EVENT_TYPE_CMD_HARD_ERR: | |
615 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
616 | "flags=0x%04x]\n", address, flags); | |
617 | break; | |
618 | case EVENT_TYPE_IOTLB_INV_TO: | |
619 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
620 | "address=0x%016llx]\n", | |
c5081cd7 | 621 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
622 | address); |
623 | break; | |
624 | case EVENT_TYPE_INV_DEV_REQ: | |
625 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
626 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 627 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
628 | address, flags); |
629 | break; | |
630 | default: | |
631 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
632 | } | |
3d06fca8 JR |
633 | |
634 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
635 | } |
636 | ||
637 | static void iommu_poll_events(struct amd_iommu *iommu) | |
638 | { | |
639 | u32 head, tail; | |
90008ee4 JR |
640 | |
641 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
642 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
643 | ||
644 | while (head != tail) { | |
a345b23b | 645 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 646 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
647 | } |
648 | ||
649 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
650 | } |
651 | ||
eee53537 | 652 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
653 | { |
654 | struct amd_iommu_fault fault; | |
72e1dcc4 | 655 | |
399be2f5 JR |
656 | INC_STATS_COUNTER(pri_requests); |
657 | ||
72e1dcc4 JR |
658 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
659 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
660 | return; | |
661 | } | |
662 | ||
663 | fault.address = raw[1]; | |
664 | fault.pasid = PPR_PASID(raw[0]); | |
665 | fault.device_id = PPR_DEVID(raw[0]); | |
666 | fault.tag = PPR_TAG(raw[0]); | |
667 | fault.flags = PPR_FLAGS(raw[0]); | |
668 | ||
72e1dcc4 JR |
669 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
670 | } | |
671 | ||
672 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
673 | { | |
72e1dcc4 JR |
674 | u32 head, tail; |
675 | ||
676 | if (iommu->ppr_log == NULL) | |
677 | return; | |
678 | ||
72e1dcc4 JR |
679 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
680 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
681 | ||
682 | while (head != tail) { | |
eee53537 JR |
683 | volatile u64 *raw; |
684 | u64 entry[2]; | |
685 | int i; | |
686 | ||
687 | raw = (u64 *)(iommu->ppr_log + head); | |
688 | ||
689 | /* | |
690 | * Hardware bug: Interrupt may arrive before the entry is | |
691 | * written to memory. If this happens we need to wait for the | |
692 | * entry to arrive. | |
693 | */ | |
694 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
695 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
696 | break; | |
697 | udelay(1); | |
698 | } | |
72e1dcc4 | 699 | |
eee53537 JR |
700 | /* Avoid memcpy function-call overhead */ |
701 | entry[0] = raw[0]; | |
702 | entry[1] = raw[1]; | |
72e1dcc4 | 703 | |
eee53537 JR |
704 | /* |
705 | * To detect the hardware bug we need to clear the entry | |
706 | * back to zero. | |
707 | */ | |
708 | raw[0] = raw[1] = 0UL; | |
709 | ||
710 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
711 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
712 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 713 | |
eee53537 JR |
714 | /* Handle PPR entry */ |
715 | iommu_handle_ppr_entry(iommu, entry); | |
716 | ||
eee53537 JR |
717 | /* Refresh ring-buffer information */ |
718 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
719 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
720 | } | |
72e1dcc4 JR |
721 | } |
722 | ||
72fe00f0 | 723 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 724 | { |
3f398bc7 SS |
725 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
726 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 727 | |
3f398bc7 SS |
728 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
729 | /* Enable EVT and PPR interrupts again */ | |
730 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
731 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 732 | |
3f398bc7 SS |
733 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
734 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
735 | iommu_poll_events(iommu); | |
736 | } | |
90008ee4 | 737 | |
3f398bc7 SS |
738 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
739 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
740 | iommu_poll_ppr_log(iommu); | |
741 | } | |
90008ee4 | 742 | |
3f398bc7 SS |
743 | /* |
744 | * Hardware bug: ERBT1312 | |
745 | * When re-enabling interrupt (by writing 1 | |
746 | * to clear the bit), the hardware might also try to set | |
747 | * the interrupt bit in the event status register. | |
748 | * In this scenario, the bit will be set, and disable | |
749 | * subsequent interrupts. | |
750 | * | |
751 | * Workaround: The IOMMU driver should read back the | |
752 | * status register and check if the interrupt bits are cleared. | |
753 | * If not, driver will need to go through the interrupt handler | |
754 | * again and re-clear the bits | |
755 | */ | |
756 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
757 | } | |
90008ee4 | 758 | return IRQ_HANDLED; |
a80dc3e0 JR |
759 | } |
760 | ||
72fe00f0 JR |
761 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
762 | { | |
763 | return IRQ_WAKE_THREAD; | |
764 | } | |
765 | ||
431b2a20 JR |
766 | /**************************************************************************** |
767 | * | |
768 | * IOMMU command queuing functions | |
769 | * | |
770 | ****************************************************************************/ | |
771 | ||
ac0ea6e9 JR |
772 | static int wait_on_sem(volatile u64 *sem) |
773 | { | |
774 | int i = 0; | |
775 | ||
776 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
777 | udelay(1); | |
778 | i += 1; | |
779 | } | |
780 | ||
781 | if (i == LOOP_TIMEOUT) { | |
782 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
783 | return -EIO; | |
784 | } | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
790 | struct iommu_cmd *cmd, | |
791 | u32 tail) | |
a19ae1ec | 792 | { |
a19ae1ec JR |
793 | u8 *target; |
794 | ||
8a7c5ef3 | 795 | target = iommu->cmd_buf + tail; |
deba4bce | 796 | tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 JR |
797 | |
798 | /* Copy command to buffer */ | |
799 | memcpy(target, cmd, sizeof(*cmd)); | |
800 | ||
801 | /* Tell the IOMMU about it */ | |
a19ae1ec | 802 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 803 | } |
a19ae1ec | 804 | |
815b33fd | 805 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 806 | { |
815b33fd JR |
807 | WARN_ON(address & 0x7ULL); |
808 | ||
ded46737 | 809 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
810 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
811 | cmd->data[1] = upper_32_bits(__pa(address)); | |
812 | cmd->data[2] = 1; | |
ded46737 JR |
813 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
814 | } | |
815 | ||
94fe79e2 JR |
816 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
817 | { | |
818 | memset(cmd, 0, sizeof(*cmd)); | |
819 | cmd->data[0] = devid; | |
820 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
821 | } | |
822 | ||
11b6402c JR |
823 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
824 | size_t size, u16 domid, int pde) | |
825 | { | |
826 | u64 pages; | |
ae0cbbb1 | 827 | bool s; |
11b6402c JR |
828 | |
829 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 830 | s = false; |
11b6402c JR |
831 | |
832 | if (pages > 1) { | |
833 | /* | |
834 | * If we have to flush more than one page, flush all | |
835 | * TLB entries for this domain | |
836 | */ | |
837 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 838 | s = true; |
11b6402c JR |
839 | } |
840 | ||
841 | address &= PAGE_MASK; | |
842 | ||
843 | memset(cmd, 0, sizeof(*cmd)); | |
844 | cmd->data[1] |= domid; | |
845 | cmd->data[2] = lower_32_bits(address); | |
846 | cmd->data[3] = upper_32_bits(address); | |
847 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
848 | if (s) /* size bit - we flush more than one 4kb page */ | |
849 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 850 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
851 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
852 | } | |
853 | ||
cb41ed85 JR |
854 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
855 | u64 address, size_t size) | |
856 | { | |
857 | u64 pages; | |
ae0cbbb1 | 858 | bool s; |
cb41ed85 JR |
859 | |
860 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 861 | s = false; |
cb41ed85 JR |
862 | |
863 | if (pages > 1) { | |
864 | /* | |
865 | * If we have to flush more than one page, flush all | |
866 | * TLB entries for this domain | |
867 | */ | |
868 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 869 | s = true; |
cb41ed85 JR |
870 | } |
871 | ||
872 | address &= PAGE_MASK; | |
873 | ||
874 | memset(cmd, 0, sizeof(*cmd)); | |
875 | cmd->data[0] = devid; | |
876 | cmd->data[0] |= (qdep & 0xff) << 24; | |
877 | cmd->data[1] = devid; | |
878 | cmd->data[2] = lower_32_bits(address); | |
879 | cmd->data[3] = upper_32_bits(address); | |
880 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
881 | if (s) | |
882 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
883 | } | |
884 | ||
22e266c7 JR |
885 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
886 | u64 address, bool size) | |
887 | { | |
888 | memset(cmd, 0, sizeof(*cmd)); | |
889 | ||
890 | address &= ~(0xfffULL); | |
891 | ||
a919a018 | 892 | cmd->data[0] = pasid; |
22e266c7 JR |
893 | cmd->data[1] = domid; |
894 | cmd->data[2] = lower_32_bits(address); | |
895 | cmd->data[3] = upper_32_bits(address); | |
896 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
897 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
898 | if (size) | |
899 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
900 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
901 | } | |
902 | ||
903 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
904 | int qdep, u64 address, bool size) | |
905 | { | |
906 | memset(cmd, 0, sizeof(*cmd)); | |
907 | ||
908 | address &= ~(0xfffULL); | |
909 | ||
910 | cmd->data[0] = devid; | |
e8d2d82d | 911 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
912 | cmd->data[0] |= (qdep & 0xff) << 24; |
913 | cmd->data[1] = devid; | |
e8d2d82d | 914 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
915 | cmd->data[2] = lower_32_bits(address); |
916 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
917 | cmd->data[3] = upper_32_bits(address); | |
918 | if (size) | |
919 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
920 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
921 | } | |
922 | ||
c99afa25 JR |
923 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
924 | int status, int tag, bool gn) | |
925 | { | |
926 | memset(cmd, 0, sizeof(*cmd)); | |
927 | ||
928 | cmd->data[0] = devid; | |
929 | if (gn) { | |
a919a018 | 930 | cmd->data[1] = pasid; |
c99afa25 JR |
931 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
932 | } | |
933 | cmd->data[3] = tag & 0x1ff; | |
934 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
935 | ||
936 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
937 | } | |
938 | ||
58fc7f14 JR |
939 | static void build_inv_all(struct iommu_cmd *cmd) |
940 | { | |
941 | memset(cmd, 0, sizeof(*cmd)); | |
942 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
943 | } |
944 | ||
7ef2798d JR |
945 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
946 | { | |
947 | memset(cmd, 0, sizeof(*cmd)); | |
948 | cmd->data[0] = devid; | |
949 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
950 | } | |
951 | ||
431b2a20 | 952 | /* |
431b2a20 | 953 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 954 | * hardware about the new command. |
431b2a20 | 955 | */ |
f1ca1512 JR |
956 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
957 | struct iommu_cmd *cmd, | |
958 | bool sync) | |
a19ae1ec | 959 | { |
ac0ea6e9 | 960 | u32 left, tail, head, next_tail; |
a19ae1ec | 961 | unsigned long flags; |
a19ae1ec | 962 | |
ac0ea6e9 | 963 | again: |
a19ae1ec | 964 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 965 | |
ac0ea6e9 JR |
966 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
967 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
deba4bce JR |
968 | next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
969 | left = (head - next_tail) % CMD_BUFFER_SIZE; | |
a19ae1ec | 970 | |
ac0ea6e9 JR |
971 | if (left <= 2) { |
972 | struct iommu_cmd sync_cmd; | |
973 | volatile u64 sem = 0; | |
974 | int ret; | |
8d201968 | 975 | |
ac0ea6e9 JR |
976 | build_completion_wait(&sync_cmd, (u64)&sem); |
977 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 978 | |
ac0ea6e9 JR |
979 | spin_unlock_irqrestore(&iommu->lock, flags); |
980 | ||
981 | if ((ret = wait_on_sem(&sem)) != 0) | |
982 | return ret; | |
983 | ||
984 | goto again; | |
8d201968 JR |
985 | } |
986 | ||
ac0ea6e9 JR |
987 | copy_cmd_to_buffer(iommu, cmd, tail); |
988 | ||
989 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 990 | iommu->need_sync = sync; |
ac0ea6e9 | 991 | |
a19ae1ec | 992 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 993 | |
815b33fd | 994 | return 0; |
8d201968 JR |
995 | } |
996 | ||
f1ca1512 JR |
997 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
998 | { | |
999 | return iommu_queue_command_sync(iommu, cmd, true); | |
1000 | } | |
1001 | ||
8d201968 JR |
1002 | /* |
1003 | * This function queues a completion wait command into the command | |
1004 | * buffer of an IOMMU | |
1005 | */ | |
a19ae1ec | 1006 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1007 | { |
1008 | struct iommu_cmd cmd; | |
815b33fd | 1009 | volatile u64 sem = 0; |
ac0ea6e9 | 1010 | int ret; |
8d201968 | 1011 | |
09ee17eb | 1012 | if (!iommu->need_sync) |
815b33fd | 1013 | return 0; |
09ee17eb | 1014 | |
815b33fd | 1015 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1016 | |
f1ca1512 | 1017 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1018 | if (ret) |
815b33fd | 1019 | return ret; |
8d201968 | 1020 | |
ac0ea6e9 | 1021 | return wait_on_sem(&sem); |
8d201968 JR |
1022 | } |
1023 | ||
d8c13085 | 1024 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1025 | { |
d8c13085 | 1026 | struct iommu_cmd cmd; |
a19ae1ec | 1027 | |
d8c13085 | 1028 | build_inv_dte(&cmd, devid); |
7e4f88da | 1029 | |
d8c13085 JR |
1030 | return iommu_queue_command(iommu, &cmd); |
1031 | } | |
09ee17eb | 1032 | |
7d0c5cc5 JR |
1033 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1034 | { | |
1035 | u32 devid; | |
09ee17eb | 1036 | |
7d0c5cc5 JR |
1037 | for (devid = 0; devid <= 0xffff; ++devid) |
1038 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1039 | |
7d0c5cc5 JR |
1040 | iommu_completion_wait(iommu); |
1041 | } | |
84df8175 | 1042 | |
7d0c5cc5 JR |
1043 | /* |
1044 | * This function uses heavy locking and may disable irqs for some time. But | |
1045 | * this is no issue because it is only called during resume. | |
1046 | */ | |
1047 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1048 | { | |
1049 | u32 dom_id; | |
a19ae1ec | 1050 | |
7d0c5cc5 JR |
1051 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1052 | struct iommu_cmd cmd; | |
1053 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1054 | dom_id, 1); | |
1055 | iommu_queue_command(iommu, &cmd); | |
1056 | } | |
8eed9833 | 1057 | |
7d0c5cc5 | 1058 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1059 | } |
1060 | ||
58fc7f14 | 1061 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1062 | { |
58fc7f14 | 1063 | struct iommu_cmd cmd; |
0518a3a4 | 1064 | |
58fc7f14 | 1065 | build_inv_all(&cmd); |
0518a3a4 | 1066 | |
58fc7f14 JR |
1067 | iommu_queue_command(iommu, &cmd); |
1068 | iommu_completion_wait(iommu); | |
1069 | } | |
1070 | ||
7ef2798d JR |
1071 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1072 | { | |
1073 | struct iommu_cmd cmd; | |
1074 | ||
1075 | build_inv_irt(&cmd, devid); | |
1076 | ||
1077 | iommu_queue_command(iommu, &cmd); | |
1078 | } | |
1079 | ||
1080 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1081 | { | |
1082 | u32 devid; | |
1083 | ||
1084 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1085 | iommu_flush_irt(iommu, devid); | |
1086 | ||
1087 | iommu_completion_wait(iommu); | |
1088 | } | |
1089 | ||
7d0c5cc5 JR |
1090 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1091 | { | |
58fc7f14 JR |
1092 | if (iommu_feature(iommu, FEATURE_IA)) { |
1093 | iommu_flush_all(iommu); | |
1094 | } else { | |
1095 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1096 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1097 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1098 | } |
1099 | } | |
1100 | ||
431b2a20 | 1101 | /* |
cb41ed85 | 1102 | * Command send function for flushing on-device TLB |
431b2a20 | 1103 | */ |
6c542047 JR |
1104 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1105 | u64 address, size_t size) | |
3fa43655 JR |
1106 | { |
1107 | struct amd_iommu *iommu; | |
b00d3bcf | 1108 | struct iommu_cmd cmd; |
cb41ed85 | 1109 | int qdep; |
3fa43655 | 1110 | |
ea61cddb JR |
1111 | qdep = dev_data->ats.qdep; |
1112 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1113 | |
ea61cddb | 1114 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1115 | |
1116 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1117 | } |
1118 | ||
431b2a20 | 1119 | /* |
431b2a20 | 1120 | * Command send function for invalidating a device table entry |
431b2a20 | 1121 | */ |
6c542047 | 1122 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1123 | { |
3fa43655 | 1124 | struct amd_iommu *iommu; |
e25bfb56 | 1125 | u16 alias; |
ee2fa743 | 1126 | int ret; |
a19ae1ec | 1127 | |
6c542047 | 1128 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1129 | alias = dev_data->alias; |
a19ae1ec | 1130 | |
f62dda66 | 1131 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1132 | if (!ret && alias != dev_data->devid) |
1133 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1134 | if (ret) |
1135 | return ret; | |
1136 | ||
ea61cddb | 1137 | if (dev_data->ats.enabled) |
6c542047 | 1138 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1139 | |
ee2fa743 | 1140 | return ret; |
a19ae1ec JR |
1141 | } |
1142 | ||
431b2a20 JR |
1143 | /* |
1144 | * TLB invalidation function which is called from the mapping functions. | |
1145 | * It invalidates a single PTE if the range to flush is within a single | |
1146 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1147 | */ | |
17b124bf JR |
1148 | static void __domain_flush_pages(struct protection_domain *domain, |
1149 | u64 address, size_t size, int pde) | |
a19ae1ec | 1150 | { |
cb41ed85 | 1151 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1152 | struct iommu_cmd cmd; |
1153 | int ret = 0, i; | |
a19ae1ec | 1154 | |
11b6402c | 1155 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1156 | |
6de8ad9b JR |
1157 | for (i = 0; i < amd_iommus_present; ++i) { |
1158 | if (!domain->dev_iommu[i]) | |
1159 | continue; | |
1160 | ||
1161 | /* | |
1162 | * Devices of this domain are behind this IOMMU | |
1163 | * We need a TLB flush | |
1164 | */ | |
11b6402c | 1165 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1166 | } |
1167 | ||
cb41ed85 | 1168 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1169 | |
ea61cddb | 1170 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1171 | continue; |
1172 | ||
6c542047 | 1173 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1174 | } |
1175 | ||
11b6402c | 1176 | WARN_ON(ret); |
6de8ad9b JR |
1177 | } |
1178 | ||
17b124bf JR |
1179 | static void domain_flush_pages(struct protection_domain *domain, |
1180 | u64 address, size_t size) | |
6de8ad9b | 1181 | { |
17b124bf | 1182 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1183 | } |
b6c02715 | 1184 | |
1c655773 | 1185 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1186 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1187 | { |
17b124bf | 1188 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1189 | } |
1190 | ||
42a49f96 | 1191 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1192 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1193 | { |
17b124bf | 1194 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1195 | } |
1196 | ||
17b124bf | 1197 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1198 | { |
17b124bf | 1199 | int i; |
18811f55 | 1200 | |
17b124bf JR |
1201 | for (i = 0; i < amd_iommus_present; ++i) { |
1202 | if (!domain->dev_iommu[i]) | |
1203 | continue; | |
bfd1be18 | 1204 | |
17b124bf JR |
1205 | /* |
1206 | * Devices of this domain are behind this IOMMU | |
1207 | * We need to wait for completion of all commands. | |
1208 | */ | |
1209 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1210 | } |
e394d72a JR |
1211 | } |
1212 | ||
b00d3bcf | 1213 | |
09b42804 | 1214 | /* |
b00d3bcf | 1215 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1216 | */ |
17b124bf | 1217 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1218 | { |
b00d3bcf | 1219 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1220 | |
b00d3bcf | 1221 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1222 | device_flush_dte(dev_data); |
a345b23b JR |
1223 | } |
1224 | ||
431b2a20 JR |
1225 | /**************************************************************************** |
1226 | * | |
1227 | * The functions below are used the create the page table mappings for | |
1228 | * unity mapped regions. | |
1229 | * | |
1230 | ****************************************************************************/ | |
1231 | ||
308973d3 JR |
1232 | /* |
1233 | * This function is used to add another level to an IO page table. Adding | |
1234 | * another level increases the size of the address space by 9 bits to a size up | |
1235 | * to 64 bits. | |
1236 | */ | |
1237 | static bool increase_address_space(struct protection_domain *domain, | |
1238 | gfp_t gfp) | |
1239 | { | |
1240 | u64 *pte; | |
1241 | ||
1242 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1243 | /* address space already 64 bit large */ | |
1244 | return false; | |
1245 | ||
1246 | pte = (void *)get_zeroed_page(gfp); | |
1247 | if (!pte) | |
1248 | return false; | |
1249 | ||
1250 | *pte = PM_LEVEL_PDE(domain->mode, | |
1251 | virt_to_phys(domain->pt_root)); | |
1252 | domain->pt_root = pte; | |
1253 | domain->mode += 1; | |
1254 | domain->updated = true; | |
1255 | ||
1256 | return true; | |
1257 | } | |
1258 | ||
1259 | static u64 *alloc_pte(struct protection_domain *domain, | |
1260 | unsigned long address, | |
cbb9d729 | 1261 | unsigned long page_size, |
308973d3 JR |
1262 | u64 **pte_page, |
1263 | gfp_t gfp) | |
1264 | { | |
cbb9d729 | 1265 | int level, end_lvl; |
308973d3 | 1266 | u64 *pte, *page; |
cbb9d729 JR |
1267 | |
1268 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1269 | |
1270 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1271 | increase_address_space(domain, gfp); | |
1272 | ||
cbb9d729 JR |
1273 | level = domain->mode - 1; |
1274 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1275 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1276 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1277 | |
1278 | while (level > end_lvl) { | |
7bfa5bd2 JR |
1279 | u64 __pte, __npte; |
1280 | ||
1281 | __pte = *pte; | |
1282 | ||
1283 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
308973d3 JR |
1284 | page = (u64 *)get_zeroed_page(gfp); |
1285 | if (!page) | |
1286 | return NULL; | |
7bfa5bd2 JR |
1287 | |
1288 | __npte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1289 | ||
1290 | if (cmpxchg64(pte, __pte, __npte)) { | |
1291 | free_page((unsigned long)page); | |
1292 | continue; | |
1293 | } | |
308973d3 JR |
1294 | } |
1295 | ||
cbb9d729 JR |
1296 | /* No level skipping support yet */ |
1297 | if (PM_PTE_LEVEL(*pte) != level) | |
1298 | return NULL; | |
1299 | ||
308973d3 JR |
1300 | level -= 1; |
1301 | ||
1302 | pte = IOMMU_PTE_PAGE(*pte); | |
1303 | ||
1304 | if (pte_page && level == end_lvl) | |
1305 | *pte_page = pte; | |
1306 | ||
1307 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1308 | } | |
1309 | ||
1310 | return pte; | |
1311 | } | |
1312 | ||
1313 | /* | |
1314 | * This function checks if there is a PTE for a given dma address. If | |
1315 | * there is one, it returns the pointer to it. | |
1316 | */ | |
3039ca1b JR |
1317 | static u64 *fetch_pte(struct protection_domain *domain, |
1318 | unsigned long address, | |
1319 | unsigned long *page_size) | |
308973d3 JR |
1320 | { |
1321 | int level; | |
1322 | u64 *pte; | |
1323 | ||
24cd7723 JR |
1324 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1325 | return NULL; | |
1326 | ||
3039ca1b JR |
1327 | level = domain->mode - 1; |
1328 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1329 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1330 | |
24cd7723 JR |
1331 | while (level > 0) { |
1332 | ||
1333 | /* Not Present */ | |
308973d3 JR |
1334 | if (!IOMMU_PTE_PRESENT(*pte)) |
1335 | return NULL; | |
1336 | ||
24cd7723 | 1337 | /* Large PTE */ |
3039ca1b JR |
1338 | if (PM_PTE_LEVEL(*pte) == 7 || |
1339 | PM_PTE_LEVEL(*pte) == 0) | |
1340 | break; | |
24cd7723 JR |
1341 | |
1342 | /* No level skipping support yet */ | |
1343 | if (PM_PTE_LEVEL(*pte) != level) | |
1344 | return NULL; | |
1345 | ||
308973d3 JR |
1346 | level -= 1; |
1347 | ||
24cd7723 | 1348 | /* Walk to the next level */ |
3039ca1b JR |
1349 | pte = IOMMU_PTE_PAGE(*pte); |
1350 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1351 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1352 | } | |
1353 | ||
1354 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1355 | unsigned long pte_mask; | |
1356 | ||
1357 | /* | |
1358 | * If we have a series of large PTEs, make | |
1359 | * sure to return a pointer to the first one. | |
1360 | */ | |
1361 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1362 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1363 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1364 | } |
1365 | ||
1366 | return pte; | |
1367 | } | |
1368 | ||
431b2a20 JR |
1369 | /* |
1370 | * Generic mapping functions. It maps a physical address into a DMA | |
1371 | * address space. It allocates the page table pages if necessary. | |
1372 | * In the future it can be extended to a generic mapping function | |
1373 | * supporting all features of AMD IOMMU page tables like level skipping | |
1374 | * and full 64 bit address spaces. | |
1375 | */ | |
38e817fe JR |
1376 | static int iommu_map_page(struct protection_domain *dom, |
1377 | unsigned long bus_addr, | |
1378 | unsigned long phys_addr, | |
abdc5eb3 | 1379 | int prot, |
cbb9d729 | 1380 | unsigned long page_size) |
bd0e5211 | 1381 | { |
8bda3092 | 1382 | u64 __pte, *pte; |
cbb9d729 | 1383 | int i, count; |
abdc5eb3 | 1384 | |
d4b03664 JR |
1385 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1386 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1387 | ||
bad1cac2 | 1388 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1389 | return -EINVAL; |
1390 | ||
d4b03664 JR |
1391 | count = PAGE_SIZE_PTE_COUNT(page_size); |
1392 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
cbb9d729 | 1393 | |
63eaa75e ML |
1394 | if (!pte) |
1395 | return -ENOMEM; | |
1396 | ||
cbb9d729 JR |
1397 | for (i = 0; i < count; ++i) |
1398 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1399 | return -EBUSY; | |
bd0e5211 | 1400 | |
d4b03664 | 1401 | if (count > 1) { |
cbb9d729 JR |
1402 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1403 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1404 | } else | |
1405 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1406 | |
bd0e5211 JR |
1407 | if (prot & IOMMU_PROT_IR) |
1408 | __pte |= IOMMU_PTE_IR; | |
1409 | if (prot & IOMMU_PROT_IW) | |
1410 | __pte |= IOMMU_PTE_IW; | |
1411 | ||
cbb9d729 JR |
1412 | for (i = 0; i < count; ++i) |
1413 | pte[i] = __pte; | |
bd0e5211 | 1414 | |
04bfdd84 JR |
1415 | update_domain(dom); |
1416 | ||
bd0e5211 JR |
1417 | return 0; |
1418 | } | |
1419 | ||
24cd7723 JR |
1420 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1421 | unsigned long bus_addr, | |
1422 | unsigned long page_size) | |
eb74ff6c | 1423 | { |
71b390e9 JR |
1424 | unsigned long long unmapped; |
1425 | unsigned long unmap_size; | |
24cd7723 JR |
1426 | u64 *pte; |
1427 | ||
1428 | BUG_ON(!is_power_of_2(page_size)); | |
1429 | ||
1430 | unmapped = 0; | |
eb74ff6c | 1431 | |
24cd7723 JR |
1432 | while (unmapped < page_size) { |
1433 | ||
71b390e9 JR |
1434 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1435 | ||
1436 | if (pte) { | |
1437 | int i, count; | |
1438 | ||
1439 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1440 | for (i = 0; i < count; i++) |
1441 | pte[i] = 0ULL; | |
1442 | } | |
1443 | ||
1444 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1445 | unmapped += unmap_size; | |
1446 | } | |
1447 | ||
60d0ca3c | 1448 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1449 | |
24cd7723 | 1450 | return unmapped; |
eb74ff6c | 1451 | } |
eb74ff6c | 1452 | |
431b2a20 JR |
1453 | /**************************************************************************** |
1454 | * | |
1455 | * The next functions belong to the address allocator for the dma_ops | |
1456 | * interface functions. They work like the allocators in the other IOMMU | |
1457 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1458 | * the aperture. Maybe it could be enhanced in the future to a more | |
1459 | * efficient allocator. | |
1460 | * | |
1461 | ****************************************************************************/ | |
d3086444 | 1462 | |
431b2a20 | 1463 | /* |
384de729 | 1464 | * The address allocator core functions. |
431b2a20 JR |
1465 | * |
1466 | * called with domain->lock held | |
1467 | */ | |
384de729 | 1468 | |
171e7b37 JR |
1469 | /* |
1470 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1471 | * ranges. | |
1472 | */ | |
1473 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1474 | unsigned long start_page, | |
1475 | unsigned int pages) | |
1476 | { | |
1477 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1478 | ||
1479 | if (start_page + pages > last_page) | |
1480 | pages = last_page - start_page; | |
1481 | ||
1482 | for (i = start_page; i < start_page + pages; ++i) { | |
1483 | int index = i / APERTURE_RANGE_PAGES; | |
1484 | int page = i % APERTURE_RANGE_PAGES; | |
1485 | __set_bit(page, dom->aperture[index]->bitmap); | |
1486 | } | |
1487 | } | |
1488 | ||
9cabe89b JR |
1489 | /* |
1490 | * This function is used to add a new aperture range to an existing | |
1491 | * aperture in case of dma_ops domain allocation or address allocation | |
1492 | * failure. | |
1493 | */ | |
576175c2 | 1494 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1495 | bool populate, gfp_t gfp) |
1496 | { | |
1497 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
5d7c94c3 | 1498 | unsigned long i, old_size, pte_pgsize; |
a73c1566 JR |
1499 | struct aperture_range *range; |
1500 | struct amd_iommu *iommu; | |
1501 | unsigned long flags; | |
9cabe89b | 1502 | |
f5e9705c JR |
1503 | #ifdef CONFIG_IOMMU_STRESS |
1504 | populate = false; | |
1505 | #endif | |
1506 | ||
9cabe89b JR |
1507 | if (index >= APERTURE_MAX_RANGES) |
1508 | return -ENOMEM; | |
1509 | ||
a73c1566 JR |
1510 | range = kzalloc(sizeof(struct aperture_range), gfp); |
1511 | if (!range) | |
9cabe89b JR |
1512 | return -ENOMEM; |
1513 | ||
a73c1566 JR |
1514 | range->bitmap = (void *)get_zeroed_page(gfp); |
1515 | if (!range->bitmap) | |
9cabe89b JR |
1516 | goto out_free; |
1517 | ||
a73c1566 | 1518 | range->offset = dma_dom->aperture_size; |
9cabe89b | 1519 | |
a73c1566 | 1520 | spin_lock_init(&range->bitmap_lock); |
08c5fb93 | 1521 | |
9cabe89b JR |
1522 | if (populate) { |
1523 | unsigned long address = dma_dom->aperture_size; | |
1524 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1525 | u64 *pte, *pte_page; | |
1526 | ||
1527 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1528 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1529 | &pte_page, gfp); |
1530 | if (!pte) | |
1531 | goto out_free; | |
1532 | ||
a73c1566 | 1533 | range->pte_pages[i] = pte_page; |
9cabe89b JR |
1534 | |
1535 | address += APERTURE_RANGE_SIZE / 64; | |
1536 | } | |
1537 | } | |
1538 | ||
92d420ec JR |
1539 | spin_lock_irqsave(&dma_dom->domain.lock, flags); |
1540 | ||
a73c1566 | 1541 | /* First take the bitmap_lock and then publish the range */ |
92d420ec | 1542 | spin_lock(&range->bitmap_lock); |
a73c1566 JR |
1543 | |
1544 | old_size = dma_dom->aperture_size; | |
1545 | dma_dom->aperture[index] = range; | |
1546 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
9cabe89b | 1547 | |
17f5b569 JR |
1548 | /* Reserve address range used for MSI messages */ |
1549 | if (old_size < MSI_ADDR_BASE_LO && | |
1550 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1551 | unsigned long spage; | |
1552 | int pages; | |
1553 | ||
1554 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1555 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1556 | ||
1557 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1558 | } | |
1559 | ||
b595076a | 1560 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1561 | for_each_iommu(iommu) { |
1562 | if (iommu->exclusion_start && | |
1563 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1564 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1565 | unsigned long startpage; | |
1566 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1567 | iommu->exclusion_length, | |
1568 | PAGE_SIZE); | |
1569 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1570 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1571 | } | |
00cd122a JR |
1572 | } |
1573 | ||
1574 | /* | |
1575 | * Check for areas already mapped as present in the new aperture | |
1576 | * range and mark those pages as reserved in the allocator. Such | |
1577 | * mappings may already exist as a result of requested unity | |
1578 | * mappings for devices. | |
1579 | */ | |
1580 | for (i = dma_dom->aperture[index]->offset; | |
1581 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1582 | i += pte_pgsize) { |
3039ca1b | 1583 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1584 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1585 | continue; | |
1586 | ||
5d7c94c3 JR |
1587 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1588 | pte_pgsize >> 12); | |
00cd122a JR |
1589 | } |
1590 | ||
04bfdd84 JR |
1591 | update_domain(&dma_dom->domain); |
1592 | ||
92d420ec JR |
1593 | spin_unlock(&range->bitmap_lock); |
1594 | ||
1595 | spin_unlock_irqrestore(&dma_dom->domain.lock, flags); | |
a73c1566 | 1596 | |
9cabe89b JR |
1597 | return 0; |
1598 | ||
1599 | out_free: | |
04bfdd84 JR |
1600 | update_domain(&dma_dom->domain); |
1601 | ||
a73c1566 | 1602 | free_page((unsigned long)range->bitmap); |
9cabe89b | 1603 | |
a73c1566 | 1604 | kfree(range); |
9cabe89b JR |
1605 | |
1606 | return -ENOMEM; | |
1607 | } | |
1608 | ||
ccb50e03 JR |
1609 | static dma_addr_t dma_ops_aperture_alloc(struct dma_ops_domain *dom, |
1610 | struct aperture_range *range, | |
a0f51447 | 1611 | unsigned long pages, |
a0f51447 JR |
1612 | unsigned long dma_mask, |
1613 | unsigned long boundary_size, | |
7b5e25b8 JR |
1614 | unsigned long align_mask, |
1615 | bool trylock) | |
a0f51447 JR |
1616 | { |
1617 | unsigned long offset, limit, flags; | |
1618 | dma_addr_t address; | |
ccb50e03 | 1619 | bool flush = false; |
a0f51447 JR |
1620 | |
1621 | offset = range->offset >> PAGE_SHIFT; | |
1622 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1623 | dma_mask >> PAGE_SHIFT); | |
1624 | ||
7b5e25b8 JR |
1625 | if (trylock) { |
1626 | if (!spin_trylock_irqsave(&range->bitmap_lock, flags)) | |
1627 | return -1; | |
1628 | } else { | |
1629 | spin_lock_irqsave(&range->bitmap_lock, flags); | |
1630 | } | |
1631 | ||
60e6a7cb JR |
1632 | address = iommu_area_alloc(range->bitmap, limit, range->next_bit, |
1633 | pages, offset, boundary_size, align_mask); | |
ccb50e03 | 1634 | if (address == -1) { |
60e6a7cb JR |
1635 | /* Nothing found, retry one time */ |
1636 | address = iommu_area_alloc(range->bitmap, limit, | |
1637 | 0, pages, offset, boundary_size, | |
1638 | align_mask); | |
ccb50e03 JR |
1639 | flush = true; |
1640 | } | |
60e6a7cb JR |
1641 | |
1642 | if (address != -1) | |
1643 | range->next_bit = address + pages; | |
1644 | ||
a0f51447 JR |
1645 | spin_unlock_irqrestore(&range->bitmap_lock, flags); |
1646 | ||
ccb50e03 JR |
1647 | if (flush) { |
1648 | domain_flush_tlb(&dom->domain); | |
1649 | domain_flush_complete(&dom->domain); | |
1650 | } | |
1651 | ||
a0f51447 JR |
1652 | return address; |
1653 | } | |
1654 | ||
384de729 JR |
1655 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1656 | struct dma_ops_domain *dom, | |
1657 | unsigned int pages, | |
1658 | unsigned long align_mask, | |
05ab49e0 | 1659 | u64 dma_mask) |
384de729 | 1660 | { |
ab7032bb | 1661 | unsigned long boundary_size, mask; |
384de729 | 1662 | unsigned long address = -1; |
7b5e25b8 | 1663 | bool first = true; |
5f6bed50 JR |
1664 | u32 start, i; |
1665 | ||
1666 | preempt_disable(); | |
384de729 | 1667 | |
e6aabee0 JR |
1668 | mask = dma_get_seg_boundary(dev); |
1669 | ||
7b5e25b8 | 1670 | again: |
5f6bed50 JR |
1671 | start = this_cpu_read(*dom->next_index); |
1672 | ||
1673 | /* Sanity check - is it really necessary? */ | |
1674 | if (unlikely(start > APERTURE_MAX_RANGES)) { | |
1675 | start = 0; | |
1676 | this_cpu_write(*dom->next_index, 0); | |
1677 | } | |
1678 | ||
e6aabee0 JR |
1679 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : |
1680 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
384de729 | 1681 | |
2a87442c JR |
1682 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1683 | struct aperture_range *range; | |
5f6bed50 JR |
1684 | int index; |
1685 | ||
1686 | index = (start + i) % APERTURE_MAX_RANGES; | |
ccb50e03 | 1687 | |
5f6bed50 | 1688 | range = dom->aperture[index]; |
2a87442c JR |
1689 | |
1690 | if (!range || range->offset >= dma_mask) | |
1691 | continue; | |
384de729 | 1692 | |
2a87442c | 1693 | address = dma_ops_aperture_alloc(dom, range, pages, |
60e6a7cb | 1694 | dma_mask, boundary_size, |
7b5e25b8 | 1695 | align_mask, first); |
384de729 | 1696 | if (address != -1) { |
2a87442c | 1697 | address = range->offset + (address << PAGE_SHIFT); |
5f6bed50 | 1698 | this_cpu_write(*dom->next_index, index); |
384de729 JR |
1699 | break; |
1700 | } | |
384de729 JR |
1701 | } |
1702 | ||
7b5e25b8 JR |
1703 | if (address == -1 && first) { |
1704 | first = false; | |
1705 | goto again; | |
1706 | } | |
1707 | ||
5f6bed50 JR |
1708 | preempt_enable(); |
1709 | ||
384de729 JR |
1710 | return address; |
1711 | } | |
1712 | ||
d3086444 JR |
1713 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1714 | struct dma_ops_domain *dom, | |
6d4f343f | 1715 | unsigned int pages, |
832a90c3 JR |
1716 | unsigned long align_mask, |
1717 | u64 dma_mask) | |
d3086444 | 1718 | { |
266a3bd2 | 1719 | unsigned long address = -1; |
d3086444 | 1720 | |
266a3bd2 JR |
1721 | while (address == -1) { |
1722 | address = dma_ops_area_alloc(dev, dom, pages, | |
1723 | align_mask, dma_mask); | |
1724 | ||
7bfa5bd2 | 1725 | if (address == -1 && alloc_new_range(dom, false, GFP_ATOMIC)) |
266a3bd2 JR |
1726 | break; |
1727 | } | |
d3086444 | 1728 | |
384de729 | 1729 | if (unlikely(address == -1)) |
8fd524b3 | 1730 | address = DMA_ERROR_CODE; |
d3086444 JR |
1731 | |
1732 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1733 | ||
1734 | return address; | |
1735 | } | |
1736 | ||
431b2a20 JR |
1737 | /* |
1738 | * The address free function. | |
1739 | * | |
1740 | * called with domain->lock held | |
1741 | */ | |
d3086444 JR |
1742 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1743 | unsigned long address, | |
1744 | unsigned int pages) | |
1745 | { | |
384de729 JR |
1746 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1747 | struct aperture_range *range = dom->aperture[i]; | |
08c5fb93 | 1748 | unsigned long flags; |
80be308d | 1749 | |
384de729 JR |
1750 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1751 | ||
47bccd6b JR |
1752 | #ifdef CONFIG_IOMMU_STRESS |
1753 | if (i < 4) | |
1754 | return; | |
1755 | #endif | |
80be308d | 1756 | |
4eeca8c5 | 1757 | if (amd_iommu_unmap_flush) { |
d41ab098 JR |
1758 | domain_flush_tlb(&dom->domain); |
1759 | domain_flush_complete(&dom->domain); | |
1760 | } | |
384de729 JR |
1761 | |
1762 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1763 | |
08c5fb93 | 1764 | spin_lock_irqsave(&range->bitmap_lock, flags); |
4eeca8c5 JR |
1765 | if (address + pages > range->next_bit) |
1766 | range->next_bit = address + pages; | |
a66022c4 | 1767 | bitmap_clear(range->bitmap, address, pages); |
08c5fb93 | 1768 | spin_unlock_irqrestore(&range->bitmap_lock, flags); |
384de729 | 1769 | |
d3086444 JR |
1770 | } |
1771 | ||
431b2a20 JR |
1772 | /**************************************************************************** |
1773 | * | |
1774 | * The next functions belong to the domain allocation. A domain is | |
1775 | * allocated for every IOMMU as the default domain. If device isolation | |
1776 | * is enabled, every device get its own domain. The most important thing | |
1777 | * about domains is the page table mapping the DMA address space they | |
1778 | * contain. | |
1779 | * | |
1780 | ****************************************************************************/ | |
1781 | ||
aeb26f55 JR |
1782 | /* |
1783 | * This function adds a protection domain to the global protection domain list | |
1784 | */ | |
1785 | static void add_domain_to_list(struct protection_domain *domain) | |
1786 | { | |
1787 | unsigned long flags; | |
1788 | ||
1789 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1790 | list_add(&domain->list, &amd_iommu_pd_list); | |
1791 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1792 | } | |
1793 | ||
1794 | /* | |
1795 | * This function removes a protection domain to the global | |
1796 | * protection domain list | |
1797 | */ | |
1798 | static void del_domain_from_list(struct protection_domain *domain) | |
1799 | { | |
1800 | unsigned long flags; | |
1801 | ||
1802 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1803 | list_del(&domain->list); | |
1804 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1805 | } | |
1806 | ||
ec487d1a JR |
1807 | static u16 domain_id_alloc(void) |
1808 | { | |
1809 | unsigned long flags; | |
1810 | int id; | |
1811 | ||
1812 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1813 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1814 | BUG_ON(id == 0); | |
1815 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1816 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1817 | else | |
1818 | id = 0; | |
1819 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1820 | ||
1821 | return id; | |
1822 | } | |
1823 | ||
a2acfb75 JR |
1824 | static void domain_id_free(int id) |
1825 | { | |
1826 | unsigned long flags; | |
1827 | ||
1828 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1829 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1830 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1831 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1832 | } | |
a2acfb75 | 1833 | |
5c34c403 JR |
1834 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1835 | static void free_pt_##LVL (unsigned long __pt) \ | |
1836 | { \ | |
1837 | unsigned long p; \ | |
1838 | u64 *pt; \ | |
1839 | int i; \ | |
1840 | \ | |
1841 | pt = (u64 *)__pt; \ | |
1842 | \ | |
1843 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1844 | /* PTE present? */ \ |
5c34c403 JR |
1845 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1846 | continue; \ | |
1847 | \ | |
0b3fff54 JR |
1848 | /* Large PTE? */ \ |
1849 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1850 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1851 | continue; \ | |
1852 | \ | |
5c34c403 JR |
1853 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1854 | FN(p); \ | |
1855 | } \ | |
1856 | free_page((unsigned long)pt); \ | |
1857 | } | |
1858 | ||
1859 | DEFINE_FREE_PT_FN(l2, free_page) | |
1860 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1861 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1862 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1863 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1864 | ||
86db2e5d | 1865 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1866 | { |
5c34c403 | 1867 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1868 | |
5c34c403 JR |
1869 | switch (domain->mode) { |
1870 | case PAGE_MODE_NONE: | |
1871 | break; | |
1872 | case PAGE_MODE_1_LEVEL: | |
1873 | free_page(root); | |
1874 | break; | |
1875 | case PAGE_MODE_2_LEVEL: | |
1876 | free_pt_l2(root); | |
1877 | break; | |
1878 | case PAGE_MODE_3_LEVEL: | |
1879 | free_pt_l3(root); | |
1880 | break; | |
1881 | case PAGE_MODE_4_LEVEL: | |
1882 | free_pt_l4(root); | |
1883 | break; | |
1884 | case PAGE_MODE_5_LEVEL: | |
1885 | free_pt_l5(root); | |
1886 | break; | |
1887 | case PAGE_MODE_6_LEVEL: | |
1888 | free_pt_l6(root); | |
1889 | break; | |
1890 | default: | |
1891 | BUG(); | |
ec487d1a | 1892 | } |
ec487d1a JR |
1893 | } |
1894 | ||
b16137b1 JR |
1895 | static void free_gcr3_tbl_level1(u64 *tbl) |
1896 | { | |
1897 | u64 *ptr; | |
1898 | int i; | |
1899 | ||
1900 | for (i = 0; i < 512; ++i) { | |
1901 | if (!(tbl[i] & GCR3_VALID)) | |
1902 | continue; | |
1903 | ||
1904 | ptr = __va(tbl[i] & PAGE_MASK); | |
1905 | ||
1906 | free_page((unsigned long)ptr); | |
1907 | } | |
1908 | } | |
1909 | ||
1910 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1911 | { | |
1912 | u64 *ptr; | |
1913 | int i; | |
1914 | ||
1915 | for (i = 0; i < 512; ++i) { | |
1916 | if (!(tbl[i] & GCR3_VALID)) | |
1917 | continue; | |
1918 | ||
1919 | ptr = __va(tbl[i] & PAGE_MASK); | |
1920 | ||
1921 | free_gcr3_tbl_level1(ptr); | |
1922 | } | |
1923 | } | |
1924 | ||
52815b75 JR |
1925 | static void free_gcr3_table(struct protection_domain *domain) |
1926 | { | |
b16137b1 JR |
1927 | if (domain->glx == 2) |
1928 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1929 | else if (domain->glx == 1) | |
1930 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1931 | else |
1932 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1933 | |
52815b75 JR |
1934 | free_page((unsigned long)domain->gcr3_tbl); |
1935 | } | |
1936 | ||
431b2a20 JR |
1937 | /* |
1938 | * Free a domain, only used if something went wrong in the | |
1939 | * allocation path and we need to free an already allocated page table | |
1940 | */ | |
ec487d1a JR |
1941 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1942 | { | |
384de729 JR |
1943 | int i; |
1944 | ||
ec487d1a JR |
1945 | if (!dom) |
1946 | return; | |
1947 | ||
5f6bed50 JR |
1948 | free_percpu(dom->next_index); |
1949 | ||
aeb26f55 JR |
1950 | del_domain_from_list(&dom->domain); |
1951 | ||
86db2e5d | 1952 | free_pagetable(&dom->domain); |
ec487d1a | 1953 | |
384de729 JR |
1954 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1955 | if (!dom->aperture[i]) | |
1956 | continue; | |
1957 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1958 | kfree(dom->aperture[i]); | |
1959 | } | |
ec487d1a JR |
1960 | |
1961 | kfree(dom); | |
1962 | } | |
1963 | ||
a639a8ee JR |
1964 | static int dma_ops_domain_alloc_apertures(struct dma_ops_domain *dma_dom, |
1965 | int max_apertures) | |
1966 | { | |
1967 | int ret, i, apertures; | |
1968 | ||
1969 | apertures = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
1970 | ret = 0; | |
1971 | ||
1972 | for (i = apertures; i < max_apertures; ++i) { | |
1973 | ret = alloc_new_range(dma_dom, false, GFP_KERNEL); | |
1974 | if (ret) | |
1975 | break; | |
1976 | } | |
1977 | ||
1978 | return ret; | |
1979 | } | |
1980 | ||
431b2a20 JR |
1981 | /* |
1982 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1983 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1984 | * structures required for the dma_ops interface |
1985 | */ | |
87a64d52 | 1986 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1987 | { |
1988 | struct dma_ops_domain *dma_dom; | |
5f6bed50 | 1989 | int cpu; |
ec487d1a JR |
1990 | |
1991 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1992 | if (!dma_dom) | |
1993 | return NULL; | |
1994 | ||
7a5a566e | 1995 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1996 | goto free_dma_dom; |
7a5a566e | 1997 | |
5f6bed50 JR |
1998 | dma_dom->next_index = alloc_percpu(u32); |
1999 | if (!dma_dom->next_index) | |
2000 | goto free_dma_dom; | |
2001 | ||
8f7a017c | 2002 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 2003 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 2004 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
2005 | dma_dom->domain.priv = dma_dom; |
2006 | if (!dma_dom->domain.pt_root) | |
2007 | goto free_dma_dom; | |
ec487d1a | 2008 | |
aeb26f55 JR |
2009 | add_domain_to_list(&dma_dom->domain); |
2010 | ||
576175c2 | 2011 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 2012 | goto free_dma_dom; |
ec487d1a | 2013 | |
431b2a20 | 2014 | /* |
ec487d1a JR |
2015 | * mark the first page as allocated so we never return 0 as |
2016 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 2017 | */ |
384de729 | 2018 | dma_dom->aperture[0]->bitmap[0] = 1; |
ec487d1a | 2019 | |
5f6bed50 JR |
2020 | for_each_possible_cpu(cpu) |
2021 | *per_cpu_ptr(dma_dom->next_index, cpu) = 0; | |
ec487d1a JR |
2022 | |
2023 | return dma_dom; | |
2024 | ||
2025 | free_dma_dom: | |
2026 | dma_ops_domain_free(dma_dom); | |
2027 | ||
2028 | return NULL; | |
2029 | } | |
2030 | ||
5b28df6f JR |
2031 | /* |
2032 | * little helper function to check whether a given protection domain is a | |
2033 | * dma_ops domain | |
2034 | */ | |
2035 | static bool dma_ops_domain(struct protection_domain *domain) | |
2036 | { | |
2037 | return domain->flags & PD_DMA_OPS_MASK; | |
2038 | } | |
2039 | ||
fd7b5535 | 2040 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2041 | { |
132bd68f | 2042 | u64 pte_root = 0; |
ee6c2868 | 2043 | u64 flags = 0; |
863c74eb | 2044 | |
132bd68f JR |
2045 | if (domain->mode != PAGE_MODE_NONE) |
2046 | pte_root = virt_to_phys(domain->pt_root); | |
2047 | ||
38ddf41b JR |
2048 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2049 | << DEV_ENTRY_MODE_SHIFT; | |
2050 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2051 | |
ee6c2868 JR |
2052 | flags = amd_iommu_dev_table[devid].data[1]; |
2053 | ||
fd7b5535 JR |
2054 | if (ats) |
2055 | flags |= DTE_FLAG_IOTLB; | |
2056 | ||
52815b75 JR |
2057 | if (domain->flags & PD_IOMMUV2_MASK) { |
2058 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2059 | u64 glx = domain->glx; | |
2060 | u64 tmp; | |
2061 | ||
2062 | pte_root |= DTE_FLAG_GV; | |
2063 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2064 | ||
2065 | /* First mask out possible old values for GCR3 table */ | |
2066 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2067 | flags &= ~tmp; | |
2068 | ||
2069 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2070 | flags &= ~tmp; | |
2071 | ||
2072 | /* Encode GCR3 table into DTE */ | |
2073 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2074 | pte_root |= tmp; | |
2075 | ||
2076 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2077 | flags |= tmp; | |
2078 | ||
2079 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2080 | flags |= tmp; | |
2081 | } | |
2082 | ||
ee6c2868 JR |
2083 | flags &= ~(0xffffUL); |
2084 | flags |= domain->id; | |
2085 | ||
2086 | amd_iommu_dev_table[devid].data[1] = flags; | |
2087 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2088 | } |
2089 | ||
2090 | static void clear_dte_entry(u16 devid) | |
2091 | { | |
15898bbc | 2092 | /* remove entry from the device table seen by the hardware */ |
cbf3ccd0 JR |
2093 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; |
2094 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; | |
15898bbc JR |
2095 | |
2096 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2097 | } |
2098 | ||
ec9e79ef JR |
2099 | static void do_attach(struct iommu_dev_data *dev_data, |
2100 | struct protection_domain *domain) | |
7f760ddd | 2101 | { |
7f760ddd | 2102 | struct amd_iommu *iommu; |
e25bfb56 | 2103 | u16 alias; |
ec9e79ef | 2104 | bool ats; |
fd7b5535 | 2105 | |
ec9e79ef | 2106 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 2107 | alias = dev_data->alias; |
ec9e79ef | 2108 | ats = dev_data->ats.enabled; |
7f760ddd JR |
2109 | |
2110 | /* Update data structures */ | |
2111 | dev_data->domain = domain; | |
2112 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
2113 | |
2114 | /* Do reference counting */ | |
2115 | domain->dev_iommu[iommu->index] += 1; | |
2116 | domain->dev_cnt += 1; | |
2117 | ||
e25bfb56 JR |
2118 | /* Update device table */ |
2119 | set_dte_entry(dev_data->devid, domain, ats); | |
2120 | if (alias != dev_data->devid) | |
9b1a12d2 | 2121 | set_dte_entry(alias, domain, ats); |
e25bfb56 | 2122 | |
6c542047 | 2123 | device_flush_dte(dev_data); |
7f760ddd JR |
2124 | } |
2125 | ||
ec9e79ef | 2126 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2127 | { |
7f760ddd | 2128 | struct amd_iommu *iommu; |
e25bfb56 | 2129 | u16 alias; |
7f760ddd | 2130 | |
5adad991 JR |
2131 | /* |
2132 | * First check if the device is still attached. It might already | |
2133 | * be detached from its domain because the generic | |
2134 | * iommu_detach_group code detached it and we try again here in | |
2135 | * our alias handling. | |
2136 | */ | |
2137 | if (!dev_data->domain) | |
2138 | return; | |
2139 | ||
ec9e79ef | 2140 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 2141 | alias = dev_data->alias; |
15898bbc JR |
2142 | |
2143 | /* decrease reference counters */ | |
7f760ddd JR |
2144 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2145 | dev_data->domain->dev_cnt -= 1; | |
2146 | ||
2147 | /* Update data structures */ | |
2148 | dev_data->domain = NULL; | |
2149 | list_del(&dev_data->list); | |
f62dda66 | 2150 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
2151 | if (alias != dev_data->devid) |
2152 | clear_dte_entry(alias); | |
15898bbc | 2153 | |
7f760ddd | 2154 | /* Flush the DTE entry */ |
6c542047 | 2155 | device_flush_dte(dev_data); |
2b681faf JR |
2156 | } |
2157 | ||
2158 | /* | |
2159 | * If a device is not yet associated with a domain, this function does | |
2160 | * assigns it visible for the hardware | |
2161 | */ | |
ec9e79ef | 2162 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2163 | struct protection_domain *domain) |
2b681faf | 2164 | { |
84fe6c19 | 2165 | int ret; |
657cbb6b | 2166 | |
272e4f99 JR |
2167 | /* |
2168 | * Must be called with IRQs disabled. Warn here to detect early | |
2169 | * when its not. | |
2170 | */ | |
2171 | WARN_ON(!irqs_disabled()); | |
2172 | ||
2b681faf JR |
2173 | /* lock domain */ |
2174 | spin_lock(&domain->lock); | |
2175 | ||
397111ab | 2176 | ret = -EBUSY; |
150952f9 | 2177 | if (dev_data->domain != NULL) |
397111ab | 2178 | goto out_unlock; |
15898bbc | 2179 | |
397111ab | 2180 | /* Attach alias group root */ |
150952f9 | 2181 | do_attach(dev_data, domain); |
24100055 | 2182 | |
84fe6c19 JL |
2183 | ret = 0; |
2184 | ||
2185 | out_unlock: | |
2186 | ||
eba6ac60 JR |
2187 | /* ready */ |
2188 | spin_unlock(&domain->lock); | |
15898bbc | 2189 | |
84fe6c19 | 2190 | return ret; |
0feae533 | 2191 | } |
b20ac0d4 | 2192 | |
52815b75 JR |
2193 | |
2194 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2195 | { | |
2196 | pci_disable_ats(pdev); | |
2197 | pci_disable_pri(pdev); | |
2198 | pci_disable_pasid(pdev); | |
2199 | } | |
2200 | ||
6a113ddc JR |
2201 | /* FIXME: Change generic reset-function to do the same */ |
2202 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2203 | { | |
2204 | u16 control; | |
2205 | int pos; | |
2206 | ||
46277b75 | 2207 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2208 | if (!pos) |
2209 | return -EINVAL; | |
2210 | ||
46277b75 JR |
2211 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2212 | control |= PCI_PRI_CTRL_RESET; | |
2213 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2214 | |
2215 | return 0; | |
2216 | } | |
2217 | ||
52815b75 JR |
2218 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2219 | { | |
6a113ddc JR |
2220 | bool reset_enable; |
2221 | int reqs, ret; | |
2222 | ||
2223 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2224 | reqs = 32; | |
2225 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2226 | reqs = 1; | |
2227 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2228 | |
2229 | /* Only allow access to user-accessible pages */ | |
2230 | ret = pci_enable_pasid(pdev, 0); | |
2231 | if (ret) | |
2232 | goto out_err; | |
2233 | ||
2234 | /* First reset the PRI state of the device */ | |
2235 | ret = pci_reset_pri(pdev); | |
2236 | if (ret) | |
2237 | goto out_err; | |
2238 | ||
6a113ddc JR |
2239 | /* Enable PRI */ |
2240 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2241 | if (ret) |
2242 | goto out_err; | |
2243 | ||
6a113ddc JR |
2244 | if (reset_enable) { |
2245 | ret = pri_reset_while_enabled(pdev); | |
2246 | if (ret) | |
2247 | goto out_err; | |
2248 | } | |
2249 | ||
52815b75 JR |
2250 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2251 | if (ret) | |
2252 | goto out_err; | |
2253 | ||
2254 | return 0; | |
2255 | ||
2256 | out_err: | |
2257 | pci_disable_pri(pdev); | |
2258 | pci_disable_pasid(pdev); | |
2259 | ||
2260 | return ret; | |
2261 | } | |
2262 | ||
c99afa25 | 2263 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2264 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2265 | |
98f1ad25 | 2266 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2267 | { |
a3b93121 | 2268 | u16 status; |
c99afa25 JR |
2269 | int pos; |
2270 | ||
46277b75 | 2271 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2272 | if (!pos) |
2273 | return false; | |
2274 | ||
a3b93121 | 2275 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2276 | |
a3b93121 | 2277 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2278 | } |
2279 | ||
407d733e | 2280 | /* |
df805abb | 2281 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2282 | * assigns it visible for the hardware |
2283 | */ | |
15898bbc JR |
2284 | static int attach_device(struct device *dev, |
2285 | struct protection_domain *domain) | |
0feae533 | 2286 | { |
fd7b5535 | 2287 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2288 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2289 | unsigned long flags; |
15898bbc | 2290 | int ret; |
eba6ac60 | 2291 | |
ea61cddb JR |
2292 | dev_data = get_dev_data(dev); |
2293 | ||
52815b75 | 2294 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2295 | if (!dev_data->passthrough) |
52815b75 JR |
2296 | return -EINVAL; |
2297 | ||
02ca2021 JR |
2298 | if (dev_data->iommu_v2) { |
2299 | if (pdev_iommuv2_enable(pdev) != 0) | |
2300 | return -EINVAL; | |
52815b75 | 2301 | |
02ca2021 JR |
2302 | dev_data->ats.enabled = true; |
2303 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2304 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2305 | } | |
52815b75 JR |
2306 | } else if (amd_iommu_iotlb_sup && |
2307 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2308 | dev_data->ats.enabled = true; |
2309 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2310 | } | |
fd7b5535 | 2311 | |
eba6ac60 | 2312 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2313 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2314 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2315 | ||
0feae533 JR |
2316 | /* |
2317 | * We might boot into a crash-kernel here. The crashed kernel | |
2318 | * left the caches in the IOMMU dirty. So we have to flush | |
2319 | * here to evict all dirty stuff. | |
2320 | */ | |
17b124bf | 2321 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2322 | |
2323 | return ret; | |
b20ac0d4 JR |
2324 | } |
2325 | ||
355bf553 JR |
2326 | /* |
2327 | * Removes a device from a protection domain (unlocked) | |
2328 | */ | |
ec9e79ef | 2329 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2330 | { |
2ca76279 | 2331 | struct protection_domain *domain; |
c4596114 | 2332 | |
272e4f99 JR |
2333 | /* |
2334 | * Must be called with IRQs disabled. Warn here to detect early | |
2335 | * when its not. | |
2336 | */ | |
2337 | WARN_ON(!irqs_disabled()); | |
2ca76279 | 2338 | |
f34c73f5 JR |
2339 | if (WARN_ON(!dev_data->domain)) |
2340 | return; | |
24100055 | 2341 | |
2ca76279 | 2342 | domain = dev_data->domain; |
71f77580 | 2343 | |
f1dd0a8b | 2344 | spin_lock(&domain->lock); |
24100055 | 2345 | |
150952f9 | 2346 | do_detach(dev_data); |
7f760ddd | 2347 | |
f1dd0a8b | 2348 | spin_unlock(&domain->lock); |
355bf553 JR |
2349 | } |
2350 | ||
2351 | /* | |
2352 | * Removes a device from a protection domain (with devtable_lock held) | |
2353 | */ | |
15898bbc | 2354 | static void detach_device(struct device *dev) |
355bf553 | 2355 | { |
52815b75 | 2356 | struct protection_domain *domain; |
ea61cddb | 2357 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2358 | unsigned long flags; |
2359 | ||
ec9e79ef | 2360 | dev_data = get_dev_data(dev); |
52815b75 | 2361 | domain = dev_data->domain; |
ec9e79ef | 2362 | |
355bf553 JR |
2363 | /* lock device table */ |
2364 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2365 | __detach_device(dev_data); |
355bf553 | 2366 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2367 | |
02ca2021 | 2368 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2369 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2370 | else if (dev_data->ats.enabled) | |
ea61cddb | 2371 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2372 | |
2373 | dev_data->ats.enabled = false; | |
355bf553 | 2374 | } |
e275a2a0 | 2375 | |
aafd8ba0 | 2376 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2377 | { |
5abcdba4 | 2378 | struct iommu_dev_data *dev_data; |
07ee8694 | 2379 | struct iommu_domain *domain; |
e275a2a0 | 2380 | struct amd_iommu *iommu; |
5abcdba4 | 2381 | u16 devid; |
aafd8ba0 | 2382 | int ret; |
e275a2a0 | 2383 | |
aafd8ba0 | 2384 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2385 | return 0; |
e275a2a0 | 2386 | |
aafd8ba0 JR |
2387 | devid = get_device_id(dev); |
2388 | iommu = amd_iommu_rlookup_table[devid]; | |
657cbb6b | 2389 | |
aafd8ba0 | 2390 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2391 | if (ret) { |
2392 | if (ret != -ENOTSUPP) | |
2393 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2394 | dev_name(dev)); | |
657cbb6b | 2395 | |
aafd8ba0 | 2396 | iommu_ignore_device(dev); |
343e9cac | 2397 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2398 | goto out; |
2399 | } | |
2400 | init_iommu_group(dev); | |
2c9195e9 | 2401 | |
07ee8694 | 2402 | dev_data = get_dev_data(dev); |
2c9195e9 | 2403 | |
4d58b8a6 | 2404 | BUG_ON(!dev_data); |
657cbb6b | 2405 | |
1e6a7b04 | 2406 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2407 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2408 | |
07ee8694 JR |
2409 | /* Domains are initialized for this device - have a look what we ended up with */ |
2410 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2411 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2412 | dev_data->passthrough = true; |
32302324 | 2413 | else |
2c9195e9 | 2414 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2415 | |
aafd8ba0 | 2416 | out: |
e275a2a0 JR |
2417 | iommu_completion_wait(iommu); |
2418 | ||
e275a2a0 JR |
2419 | return 0; |
2420 | } | |
2421 | ||
aafd8ba0 | 2422 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2423 | { |
aafd8ba0 JR |
2424 | struct amd_iommu *iommu; |
2425 | u16 devid; | |
2426 | ||
2427 | if (!check_device(dev)) | |
2428 | return; | |
2429 | ||
2430 | devid = get_device_id(dev); | |
2431 | iommu = amd_iommu_rlookup_table[devid]; | |
2432 | ||
2433 | iommu_uninit_device(dev); | |
2434 | iommu_completion_wait(iommu); | |
8638c491 JR |
2435 | } |
2436 | ||
431b2a20 JR |
2437 | /***************************************************************************** |
2438 | * | |
2439 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2440 | * | |
2441 | *****************************************************************************/ | |
2442 | ||
2443 | /* | |
2444 | * In the dma_ops path we only have the struct device. This function | |
2445 | * finds the corresponding IOMMU, the protection domain and the | |
2446 | * requestor id for a given device. | |
2447 | * If the device is not yet associated with a domain this is also done | |
2448 | * in this function. | |
2449 | */ | |
94f6d190 | 2450 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2451 | { |
94f6d190 | 2452 | struct protection_domain *domain; |
063071df | 2453 | struct iommu_domain *io_domain; |
b20ac0d4 | 2454 | |
f99c0f1c | 2455 | if (!check_device(dev)) |
94f6d190 | 2456 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2457 | |
063071df | 2458 | io_domain = iommu_get_domain_for_dev(dev); |
0bb6e243 JR |
2459 | if (!io_domain) |
2460 | return NULL; | |
b20ac0d4 | 2461 | |
0bb6e243 JR |
2462 | domain = to_pdomain(io_domain); |
2463 | if (!dma_ops_domain(domain)) | |
94f6d190 | 2464 | return ERR_PTR(-EBUSY); |
f91ba190 | 2465 | |
0bb6e243 | 2466 | return domain; |
b20ac0d4 JR |
2467 | } |
2468 | ||
04bfdd84 JR |
2469 | static void update_device_table(struct protection_domain *domain) |
2470 | { | |
492667da | 2471 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2472 | |
ea61cddb JR |
2473 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2474 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2475 | } |
2476 | ||
2477 | static void update_domain(struct protection_domain *domain) | |
2478 | { | |
2479 | if (!domain->updated) | |
2480 | return; | |
2481 | ||
2482 | update_device_table(domain); | |
17b124bf JR |
2483 | |
2484 | domain_flush_devices(domain); | |
2485 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2486 | |
2487 | domain->updated = false; | |
2488 | } | |
2489 | ||
8bda3092 JR |
2490 | /* |
2491 | * This function fetches the PTE for a given address in the aperture | |
2492 | */ | |
2493 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2494 | unsigned long address) | |
2495 | { | |
384de729 | 2496 | struct aperture_range *aperture; |
8bda3092 JR |
2497 | u64 *pte, *pte_page; |
2498 | ||
384de729 JR |
2499 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2500 | if (!aperture) | |
2501 | return NULL; | |
2502 | ||
2503 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2504 | if (!pte) { |
cbb9d729 | 2505 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2506 | GFP_ATOMIC); |
384de729 JR |
2507 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2508 | } else | |
8c8c143c | 2509 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2510 | |
04bfdd84 | 2511 | update_domain(&dom->domain); |
8bda3092 JR |
2512 | |
2513 | return pte; | |
2514 | } | |
2515 | ||
431b2a20 JR |
2516 | /* |
2517 | * This is the generic map function. It maps one 4kb page at paddr to | |
2518 | * the given address in the DMA address space for the domain. | |
2519 | */ | |
680525e0 | 2520 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2521 | unsigned long address, |
2522 | phys_addr_t paddr, | |
2523 | int direction) | |
2524 | { | |
2525 | u64 *pte, __pte; | |
2526 | ||
2527 | WARN_ON(address > dom->aperture_size); | |
2528 | ||
2529 | paddr &= PAGE_MASK; | |
2530 | ||
8bda3092 | 2531 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2532 | if (!pte) |
8fd524b3 | 2533 | return DMA_ERROR_CODE; |
cb76c322 JR |
2534 | |
2535 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2536 | ||
2537 | if (direction == DMA_TO_DEVICE) | |
2538 | __pte |= IOMMU_PTE_IR; | |
2539 | else if (direction == DMA_FROM_DEVICE) | |
2540 | __pte |= IOMMU_PTE_IW; | |
2541 | else if (direction == DMA_BIDIRECTIONAL) | |
2542 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2543 | ||
a7fb668f | 2544 | WARN_ON_ONCE(*pte); |
cb76c322 JR |
2545 | |
2546 | *pte = __pte; | |
2547 | ||
2548 | return (dma_addr_t)address; | |
2549 | } | |
2550 | ||
431b2a20 JR |
2551 | /* |
2552 | * The generic unmapping function for on page in the DMA address space. | |
2553 | */ | |
680525e0 | 2554 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2555 | unsigned long address) |
2556 | { | |
384de729 | 2557 | struct aperture_range *aperture; |
cb76c322 JR |
2558 | u64 *pte; |
2559 | ||
2560 | if (address >= dom->aperture_size) | |
2561 | return; | |
2562 | ||
384de729 JR |
2563 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2564 | if (!aperture) | |
2565 | return; | |
2566 | ||
2567 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2568 | if (!pte) | |
2569 | return; | |
cb76c322 | 2570 | |
8c8c143c | 2571 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 | 2572 | |
a7fb668f | 2573 | WARN_ON_ONCE(!*pte); |
cb76c322 JR |
2574 | |
2575 | *pte = 0ULL; | |
2576 | } | |
2577 | ||
431b2a20 JR |
2578 | /* |
2579 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2580 | * contiguous memory region into DMA address space. It is used by all |
2581 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2582 | * Must be called with the domain lock held. |
2583 | */ | |
cb76c322 | 2584 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2585 | struct dma_ops_domain *dma_dom, |
2586 | phys_addr_t paddr, | |
2587 | size_t size, | |
6d4f343f | 2588 | int dir, |
832a90c3 JR |
2589 | bool align, |
2590 | u64 dma_mask) | |
cb76c322 JR |
2591 | { |
2592 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2593 | dma_addr_t address, start, ret; |
cb76c322 | 2594 | unsigned int pages; |
6d4f343f | 2595 | unsigned long align_mask = 0; |
cb76c322 JR |
2596 | int i; |
2597 | ||
e3c449f5 | 2598 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2599 | paddr &= PAGE_MASK; |
2600 | ||
8ecaf8f1 JR |
2601 | INC_STATS_COUNTER(total_map_requests); |
2602 | ||
c1858976 JR |
2603 | if (pages > 1) |
2604 | INC_STATS_COUNTER(cross_page); | |
2605 | ||
6d4f343f JR |
2606 | if (align) |
2607 | align_mask = (1UL << get_order(size)) - 1; | |
2608 | ||
832a90c3 JR |
2609 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2610 | dma_mask); | |
ebaecb42 | 2611 | |
266a3bd2 JR |
2612 | if (address == DMA_ERROR_CODE) |
2613 | goto out; | |
cb76c322 JR |
2614 | |
2615 | start = address; | |
2616 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2617 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2618 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2619 | goto out_unmap; |
2620 | ||
cb76c322 JR |
2621 | paddr += PAGE_SIZE; |
2622 | start += PAGE_SIZE; | |
2623 | } | |
2624 | address += offset; | |
2625 | ||
5774f7c5 JR |
2626 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2627 | ||
ab7032bb | 2628 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2629 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2630 | domain_flush_complete(&dma_dom->domain); |
2631 | } | |
270cab24 | 2632 | |
cb76c322 JR |
2633 | out: |
2634 | return address; | |
53812c11 JR |
2635 | |
2636 | out_unmap: | |
2637 | ||
2638 | for (--i; i >= 0; --i) { | |
2639 | start -= PAGE_SIZE; | |
680525e0 | 2640 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2641 | } |
2642 | ||
2643 | dma_ops_free_addresses(dma_dom, address, pages); | |
2644 | ||
8fd524b3 | 2645 | return DMA_ERROR_CODE; |
cb76c322 JR |
2646 | } |
2647 | ||
431b2a20 JR |
2648 | /* |
2649 | * Does the reverse of the __map_single function. Must be called with | |
2650 | * the domain lock held too | |
2651 | */ | |
cd8c82e8 | 2652 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2653 | dma_addr_t dma_addr, |
2654 | size_t size, | |
2655 | int dir) | |
2656 | { | |
04e0463e | 2657 | dma_addr_t flush_addr; |
cb76c322 JR |
2658 | dma_addr_t i, start; |
2659 | unsigned int pages; | |
2660 | ||
8fd524b3 | 2661 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2662 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2663 | return; |
2664 | ||
04e0463e | 2665 | flush_addr = dma_addr; |
e3c449f5 | 2666 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2667 | dma_addr &= PAGE_MASK; |
2668 | start = dma_addr; | |
2669 | ||
2670 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2671 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2672 | start += PAGE_SIZE; |
2673 | } | |
2674 | ||
84b3a0bc JR |
2675 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2676 | ||
2677 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
cb76c322 JR |
2678 | } |
2679 | ||
431b2a20 JR |
2680 | /* |
2681 | * The exported map_single function for dma_ops. | |
2682 | */ | |
51491367 FT |
2683 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2684 | unsigned long offset, size_t size, | |
2685 | enum dma_data_direction dir, | |
2686 | struct dma_attrs *attrs) | |
4da70b9e | 2687 | { |
92d420ec | 2688 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2689 | struct protection_domain *domain; |
832a90c3 | 2690 | u64 dma_mask; |
4da70b9e | 2691 | |
0f2a86f2 JR |
2692 | INC_STATS_COUNTER(cnt_map_single); |
2693 | ||
94f6d190 JR |
2694 | domain = get_domain(dev); |
2695 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2696 | return (dma_addr_t)paddr; |
94f6d190 JR |
2697 | else if (IS_ERR(domain)) |
2698 | return DMA_ERROR_CODE; | |
4da70b9e | 2699 | |
f99c0f1c JR |
2700 | dma_mask = *dev->dma_mask; |
2701 | ||
92d420ec | 2702 | return __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2703 | dma_mask); |
4da70b9e JR |
2704 | } |
2705 | ||
431b2a20 JR |
2706 | /* |
2707 | * The exported unmap_single function for dma_ops. | |
2708 | */ | |
51491367 FT |
2709 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2710 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e | 2711 | { |
4da70b9e | 2712 | struct protection_domain *domain; |
4da70b9e | 2713 | |
146a6917 JR |
2714 | INC_STATS_COUNTER(cnt_unmap_single); |
2715 | ||
94f6d190 JR |
2716 | domain = get_domain(dev); |
2717 | if (IS_ERR(domain)) | |
5b28df6f JR |
2718 | return; |
2719 | ||
cd8c82e8 | 2720 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e JR |
2721 | } |
2722 | ||
431b2a20 JR |
2723 | /* |
2724 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2725 | * lists). | |
2726 | */ | |
65b050ad | 2727 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2728 | int nelems, enum dma_data_direction dir, |
2729 | struct dma_attrs *attrs) | |
65b050ad | 2730 | { |
65b050ad | 2731 | struct protection_domain *domain; |
65b050ad JR |
2732 | int i; |
2733 | struct scatterlist *s; | |
2734 | phys_addr_t paddr; | |
2735 | int mapped_elems = 0; | |
832a90c3 | 2736 | u64 dma_mask; |
65b050ad | 2737 | |
d03f067a JR |
2738 | INC_STATS_COUNTER(cnt_map_sg); |
2739 | ||
94f6d190 | 2740 | domain = get_domain(dev); |
a0e191b2 | 2741 | if (IS_ERR(domain)) |
94f6d190 | 2742 | return 0; |
dbcc112e | 2743 | |
832a90c3 | 2744 | dma_mask = *dev->dma_mask; |
65b050ad | 2745 | |
65b050ad JR |
2746 | for_each_sg(sglist, s, nelems, i) { |
2747 | paddr = sg_phys(s); | |
2748 | ||
cd8c82e8 | 2749 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2750 | paddr, s->length, dir, false, |
2751 | dma_mask); | |
65b050ad JR |
2752 | |
2753 | if (s->dma_address) { | |
2754 | s->dma_length = s->length; | |
2755 | mapped_elems++; | |
2756 | } else | |
2757 | goto unmap; | |
65b050ad JR |
2758 | } |
2759 | ||
65b050ad | 2760 | return mapped_elems; |
92d420ec | 2761 | |
65b050ad JR |
2762 | unmap: |
2763 | for_each_sg(sglist, s, mapped_elems, i) { | |
2764 | if (s->dma_address) | |
cd8c82e8 | 2765 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2766 | s->dma_length, dir); |
2767 | s->dma_address = s->dma_length = 0; | |
2768 | } | |
2769 | ||
92d420ec | 2770 | return 0; |
65b050ad JR |
2771 | } |
2772 | ||
431b2a20 JR |
2773 | /* |
2774 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2775 | * lists). | |
2776 | */ | |
65b050ad | 2777 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2778 | int nelems, enum dma_data_direction dir, |
2779 | struct dma_attrs *attrs) | |
65b050ad | 2780 | { |
65b050ad JR |
2781 | struct protection_domain *domain; |
2782 | struct scatterlist *s; | |
65b050ad JR |
2783 | int i; |
2784 | ||
55877a6b JR |
2785 | INC_STATS_COUNTER(cnt_unmap_sg); |
2786 | ||
94f6d190 JR |
2787 | domain = get_domain(dev); |
2788 | if (IS_ERR(domain)) | |
5b28df6f JR |
2789 | return; |
2790 | ||
65b050ad | 2791 | for_each_sg(sglist, s, nelems, i) { |
cd8c82e8 | 2792 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2793 | s->dma_length, dir); |
65b050ad JR |
2794 | s->dma_address = s->dma_length = 0; |
2795 | } | |
65b050ad JR |
2796 | } |
2797 | ||
431b2a20 JR |
2798 | /* |
2799 | * The exported alloc_coherent function for dma_ops. | |
2800 | */ | |
5d8b53cf | 2801 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2802 | dma_addr_t *dma_addr, gfp_t flag, |
2803 | struct dma_attrs *attrs) | |
5d8b53cf | 2804 | { |
832a90c3 | 2805 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 | 2806 | struct protection_domain *domain; |
3b839a57 | 2807 | struct page *page; |
5d8b53cf | 2808 | |
c8f0fb36 JR |
2809 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2810 | ||
94f6d190 JR |
2811 | domain = get_domain(dev); |
2812 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2813 | page = alloc_pages(flag, get_order(size)); |
2814 | *dma_addr = page_to_phys(page); | |
2815 | return page_address(page); | |
94f6d190 JR |
2816 | } else if (IS_ERR(domain)) |
2817 | return NULL; | |
5d8b53cf | 2818 | |
3b839a57 | 2819 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2820 | dma_mask = dev->coherent_dma_mask; |
2821 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2822 | flag |= __GFP_ZERO; |
5d8b53cf | 2823 | |
3b839a57 JR |
2824 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2825 | if (!page) { | |
d0164adc | 2826 | if (!gfpflags_allow_blocking(flag)) |
3b839a57 | 2827 | return NULL; |
5d8b53cf | 2828 | |
3b839a57 JR |
2829 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2830 | get_order(size)); | |
2831 | if (!page) | |
2832 | return NULL; | |
2833 | } | |
5d8b53cf | 2834 | |
832a90c3 JR |
2835 | if (!dma_mask) |
2836 | dma_mask = *dev->dma_mask; | |
2837 | ||
3b839a57 | 2838 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2839 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2840 | |
92d420ec | 2841 | if (*dma_addr == DMA_ERROR_CODE) |
5b28df6f | 2842 | goto out_free; |
5d8b53cf | 2843 | |
3b839a57 | 2844 | return page_address(page); |
5b28df6f JR |
2845 | |
2846 | out_free: | |
2847 | ||
3b839a57 JR |
2848 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2849 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2850 | |
2851 | return NULL; | |
5d8b53cf JR |
2852 | } |
2853 | ||
431b2a20 JR |
2854 | /* |
2855 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2856 | */ |
5d8b53cf | 2857 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2858 | void *virt_addr, dma_addr_t dma_addr, |
2859 | struct dma_attrs *attrs) | |
5d8b53cf | 2860 | { |
5d8b53cf | 2861 | struct protection_domain *domain; |
3b839a57 | 2862 | struct page *page; |
5d8b53cf | 2863 | |
5d31ee7e JR |
2864 | INC_STATS_COUNTER(cnt_free_coherent); |
2865 | ||
3b839a57 JR |
2866 | page = virt_to_page(virt_addr); |
2867 | size = PAGE_ALIGN(size); | |
2868 | ||
94f6d190 JR |
2869 | domain = get_domain(dev); |
2870 | if (IS_ERR(domain)) | |
5b28df6f JR |
2871 | goto free_mem; |
2872 | ||
cd8c82e8 | 2873 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2874 | |
5d8b53cf | 2875 | free_mem: |
3b839a57 JR |
2876 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2877 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2878 | } |
2879 | ||
b39ba6ad JR |
2880 | /* |
2881 | * This function is called by the DMA layer to find out if we can handle a | |
2882 | * particular device. It is part of the dma_ops. | |
2883 | */ | |
2884 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2885 | { | |
420aef8a | 2886 | return check_device(dev); |
b39ba6ad JR |
2887 | } |
2888 | ||
a639a8ee JR |
2889 | static int set_dma_mask(struct device *dev, u64 mask) |
2890 | { | |
2891 | struct protection_domain *domain; | |
2892 | int max_apertures = 1; | |
2893 | ||
2894 | domain = get_domain(dev); | |
2895 | if (IS_ERR(domain)) | |
2896 | return PTR_ERR(domain); | |
2897 | ||
2898 | if (mask == DMA_BIT_MASK(64)) | |
2899 | max_apertures = 8; | |
2900 | else if (mask > DMA_BIT_MASK(32)) | |
2901 | max_apertures = 4; | |
2902 | ||
2903 | /* | |
2904 | * To prevent lock contention it doesn't make sense to allocate more | |
2905 | * apertures than online cpus | |
2906 | */ | |
2907 | if (max_apertures > num_online_cpus()) | |
2908 | max_apertures = num_online_cpus(); | |
2909 | ||
2910 | if (dma_ops_domain_alloc_apertures(domain->priv, max_apertures)) | |
2911 | dev_err(dev, "Can't allocate %d iommu apertures\n", | |
2912 | max_apertures); | |
2913 | ||
2914 | return 0; | |
2915 | } | |
2916 | ||
160c1d8e | 2917 | static struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2918 | .alloc = alloc_coherent, |
2919 | .free = free_coherent, | |
2920 | .map_page = map_page, | |
2921 | .unmap_page = unmap_page, | |
2922 | .map_sg = map_sg, | |
2923 | .unmap_sg = unmap_sg, | |
2924 | .dma_supported = amd_iommu_dma_supported, | |
2925 | .set_dma_mask = set_dma_mask, | |
6631ee9d JR |
2926 | }; |
2927 | ||
3a18404c | 2928 | int __init amd_iommu_init_api(void) |
27c2127a | 2929 | { |
3a18404c | 2930 | return bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2931 | } |
2932 | ||
6631ee9d JR |
2933 | int __init amd_iommu_init_dma_ops(void) |
2934 | { | |
32302324 | 2935 | swiotlb = iommu_pass_through ? 1 : 0; |
6631ee9d | 2936 | iommu_detected = 1; |
6631ee9d | 2937 | |
52717828 JR |
2938 | /* |
2939 | * In case we don't initialize SWIOTLB (actually the common case | |
2940 | * when AMD IOMMU is enabled), make sure there are global | |
2941 | * dma_ops set as a fall-back for devices not handled by this | |
2942 | * driver (for example non-PCI devices). | |
2943 | */ | |
2944 | if (!swiotlb) | |
2945 | dma_ops = &nommu_dma_ops; | |
2946 | ||
7f26508b JR |
2947 | amd_iommu_stats_init(); |
2948 | ||
62410eeb JR |
2949 | if (amd_iommu_unmap_flush) |
2950 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2951 | else | |
2952 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2953 | ||
6631ee9d | 2954 | return 0; |
6631ee9d | 2955 | } |
6d98cd80 JR |
2956 | |
2957 | /***************************************************************************** | |
2958 | * | |
2959 | * The following functions belong to the exported interface of AMD IOMMU | |
2960 | * | |
2961 | * This interface allows access to lower level functions of the IOMMU | |
2962 | * like protection domain handling and assignement of devices to domains | |
2963 | * which is not possible with the dma_ops interface. | |
2964 | * | |
2965 | *****************************************************************************/ | |
2966 | ||
6d98cd80 JR |
2967 | static void cleanup_domain(struct protection_domain *domain) |
2968 | { | |
9b29d3c6 | 2969 | struct iommu_dev_data *entry; |
6d98cd80 | 2970 | unsigned long flags; |
6d98cd80 JR |
2971 | |
2972 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2973 | ||
9b29d3c6 JR |
2974 | while (!list_empty(&domain->dev_list)) { |
2975 | entry = list_first_entry(&domain->dev_list, | |
2976 | struct iommu_dev_data, list); | |
2977 | __detach_device(entry); | |
492667da | 2978 | } |
6d98cd80 JR |
2979 | |
2980 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2981 | } | |
2982 | ||
2650815f JR |
2983 | static void protection_domain_free(struct protection_domain *domain) |
2984 | { | |
2985 | if (!domain) | |
2986 | return; | |
2987 | ||
aeb26f55 JR |
2988 | del_domain_from_list(domain); |
2989 | ||
2650815f JR |
2990 | if (domain->id) |
2991 | domain_id_free(domain->id); | |
2992 | ||
2993 | kfree(domain); | |
2994 | } | |
2995 | ||
7a5a566e JR |
2996 | static int protection_domain_init(struct protection_domain *domain) |
2997 | { | |
2998 | spin_lock_init(&domain->lock); | |
2999 | mutex_init(&domain->api_lock); | |
3000 | domain->id = domain_id_alloc(); | |
3001 | if (!domain->id) | |
3002 | return -ENOMEM; | |
3003 | INIT_LIST_HEAD(&domain->dev_list); | |
3004 | ||
3005 | return 0; | |
3006 | } | |
3007 | ||
2650815f | 3008 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
3009 | { |
3010 | struct protection_domain *domain; | |
3011 | ||
3012 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3013 | if (!domain) | |
2650815f | 3014 | return NULL; |
c156e347 | 3015 | |
7a5a566e | 3016 | if (protection_domain_init(domain)) |
2650815f JR |
3017 | goto out_err; |
3018 | ||
aeb26f55 JR |
3019 | add_domain_to_list(domain); |
3020 | ||
2650815f JR |
3021 | return domain; |
3022 | ||
3023 | out_err: | |
3024 | kfree(domain); | |
3025 | ||
3026 | return NULL; | |
3027 | } | |
3028 | ||
3f4b87b9 | 3029 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 3030 | { |
3f4b87b9 | 3031 | struct protection_domain *pdomain; |
0bb6e243 | 3032 | struct dma_ops_domain *dma_domain; |
2650815f | 3033 | |
0bb6e243 JR |
3034 | switch (type) { |
3035 | case IOMMU_DOMAIN_UNMANAGED: | |
3036 | pdomain = protection_domain_alloc(); | |
3037 | if (!pdomain) | |
3038 | return NULL; | |
c156e347 | 3039 | |
0bb6e243 JR |
3040 | pdomain->mode = PAGE_MODE_3_LEVEL; |
3041 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
3042 | if (!pdomain->pt_root) { | |
3043 | protection_domain_free(pdomain); | |
3044 | return NULL; | |
3045 | } | |
c156e347 | 3046 | |
0bb6e243 JR |
3047 | pdomain->domain.geometry.aperture_start = 0; |
3048 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
3049 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 3050 | |
0bb6e243 JR |
3051 | break; |
3052 | case IOMMU_DOMAIN_DMA: | |
3053 | dma_domain = dma_ops_domain_alloc(); | |
3054 | if (!dma_domain) { | |
3055 | pr_err("AMD-Vi: Failed to allocate\n"); | |
3056 | return NULL; | |
3057 | } | |
3058 | pdomain = &dma_domain->domain; | |
3059 | break; | |
07f643a3 JR |
3060 | case IOMMU_DOMAIN_IDENTITY: |
3061 | pdomain = protection_domain_alloc(); | |
3062 | if (!pdomain) | |
3063 | return NULL; | |
c156e347 | 3064 | |
07f643a3 JR |
3065 | pdomain->mode = PAGE_MODE_NONE; |
3066 | break; | |
0bb6e243 JR |
3067 | default: |
3068 | return NULL; | |
3069 | } | |
c156e347 | 3070 | |
3f4b87b9 | 3071 | return &pdomain->domain; |
c156e347 JR |
3072 | } |
3073 | ||
3f4b87b9 | 3074 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 3075 | { |
3f4b87b9 | 3076 | struct protection_domain *domain; |
98383fc3 | 3077 | |
3f4b87b9 | 3078 | if (!dom) |
98383fc3 JR |
3079 | return; |
3080 | ||
3f4b87b9 JR |
3081 | domain = to_pdomain(dom); |
3082 | ||
98383fc3 JR |
3083 | if (domain->dev_cnt > 0) |
3084 | cleanup_domain(domain); | |
3085 | ||
3086 | BUG_ON(domain->dev_cnt != 0); | |
3087 | ||
132bd68f JR |
3088 | if (domain->mode != PAGE_MODE_NONE) |
3089 | free_pagetable(domain); | |
98383fc3 | 3090 | |
52815b75 JR |
3091 | if (domain->flags & PD_IOMMUV2_MASK) |
3092 | free_gcr3_table(domain); | |
3093 | ||
8b408fe4 | 3094 | protection_domain_free(domain); |
98383fc3 JR |
3095 | } |
3096 | ||
684f2888 JR |
3097 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3098 | struct device *dev) | |
3099 | { | |
657cbb6b | 3100 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3101 | struct amd_iommu *iommu; |
684f2888 JR |
3102 | u16 devid; |
3103 | ||
98fc5a69 | 3104 | if (!check_device(dev)) |
684f2888 JR |
3105 | return; |
3106 | ||
98fc5a69 | 3107 | devid = get_device_id(dev); |
684f2888 | 3108 | |
657cbb6b | 3109 | if (dev_data->domain != NULL) |
15898bbc | 3110 | detach_device(dev); |
684f2888 JR |
3111 | |
3112 | iommu = amd_iommu_rlookup_table[devid]; | |
3113 | if (!iommu) | |
3114 | return; | |
3115 | ||
684f2888 JR |
3116 | iommu_completion_wait(iommu); |
3117 | } | |
3118 | ||
01106066 JR |
3119 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3120 | struct device *dev) | |
3121 | { | |
3f4b87b9 | 3122 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3123 | struct iommu_dev_data *dev_data; |
01106066 | 3124 | struct amd_iommu *iommu; |
15898bbc | 3125 | int ret; |
01106066 | 3126 | |
98fc5a69 | 3127 | if (!check_device(dev)) |
01106066 JR |
3128 | return -EINVAL; |
3129 | ||
657cbb6b JR |
3130 | dev_data = dev->archdata.iommu; |
3131 | ||
f62dda66 | 3132 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3133 | if (!iommu) |
3134 | return -EINVAL; | |
3135 | ||
657cbb6b | 3136 | if (dev_data->domain) |
15898bbc | 3137 | detach_device(dev); |
01106066 | 3138 | |
15898bbc | 3139 | ret = attach_device(dev, domain); |
01106066 JR |
3140 | |
3141 | iommu_completion_wait(iommu); | |
3142 | ||
15898bbc | 3143 | return ret; |
01106066 JR |
3144 | } |
3145 | ||
468e2366 | 3146 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3147 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3148 | { |
3f4b87b9 | 3149 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3150 | int prot = 0; |
3151 | int ret; | |
3152 | ||
132bd68f JR |
3153 | if (domain->mode == PAGE_MODE_NONE) |
3154 | return -EINVAL; | |
3155 | ||
c6229ca6 JR |
3156 | if (iommu_prot & IOMMU_READ) |
3157 | prot |= IOMMU_PROT_IR; | |
3158 | if (iommu_prot & IOMMU_WRITE) | |
3159 | prot |= IOMMU_PROT_IW; | |
3160 | ||
5d214fe6 | 3161 | mutex_lock(&domain->api_lock); |
795e74f7 | 3162 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3163 | mutex_unlock(&domain->api_lock); |
3164 | ||
795e74f7 | 3165 | return ret; |
c6229ca6 JR |
3166 | } |
3167 | ||
5009065d OBC |
3168 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3169 | size_t page_size) | |
eb74ff6c | 3170 | { |
3f4b87b9 | 3171 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3172 | size_t unmap_size; |
eb74ff6c | 3173 | |
132bd68f JR |
3174 | if (domain->mode == PAGE_MODE_NONE) |
3175 | return -EINVAL; | |
3176 | ||
5d214fe6 | 3177 | mutex_lock(&domain->api_lock); |
468e2366 | 3178 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3179 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3180 | |
17b124bf | 3181 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3182 | |
5009065d | 3183 | return unmap_size; |
eb74ff6c JR |
3184 | } |
3185 | ||
645c4c8d | 3186 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3187 | dma_addr_t iova) |
645c4c8d | 3188 | { |
3f4b87b9 | 3189 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3190 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3191 | u64 *pte, __pte; |
645c4c8d | 3192 | |
132bd68f JR |
3193 | if (domain->mode == PAGE_MODE_NONE) |
3194 | return iova; | |
3195 | ||
3039ca1b | 3196 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3197 | |
a6d41a40 | 3198 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3199 | return 0; |
3200 | ||
b24b1b63 JR |
3201 | offset_mask = pte_pgsize - 1; |
3202 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3203 | |
b24b1b63 | 3204 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3205 | } |
3206 | ||
ab636481 | 3207 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3208 | { |
80a506b8 JR |
3209 | switch (cap) { |
3210 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3211 | return true; |
bdddadcb | 3212 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3213 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3214 | case IOMMU_CAP_NOEXEC: |
3215 | return false; | |
80a506b8 JR |
3216 | } |
3217 | ||
ab636481 | 3218 | return false; |
dbb9fd86 SY |
3219 | } |
3220 | ||
35cf248f JR |
3221 | static void amd_iommu_get_dm_regions(struct device *dev, |
3222 | struct list_head *head) | |
3223 | { | |
3224 | struct unity_map_entry *entry; | |
3225 | u16 devid; | |
3226 | ||
3227 | devid = get_device_id(dev); | |
3228 | ||
3229 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3230 | struct iommu_dm_region *region; | |
3231 | ||
3232 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3233 | continue; | |
3234 | ||
3235 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3236 | if (!region) { | |
3237 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3238 | dev_name(dev)); | |
3239 | return; | |
3240 | } | |
3241 | ||
3242 | region->start = entry->address_start; | |
3243 | region->length = entry->address_end - entry->address_start; | |
3244 | if (entry->prot & IOMMU_PROT_IR) | |
3245 | region->prot |= IOMMU_READ; | |
3246 | if (entry->prot & IOMMU_PROT_IW) | |
3247 | region->prot |= IOMMU_WRITE; | |
3248 | ||
3249 | list_add_tail(®ion->list, head); | |
3250 | } | |
3251 | } | |
3252 | ||
3253 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3254 | struct list_head *head) | |
3255 | { | |
3256 | struct iommu_dm_region *entry, *next; | |
3257 | ||
3258 | list_for_each_entry_safe(entry, next, head, list) | |
3259 | kfree(entry); | |
3260 | } | |
3261 | ||
b22f6434 | 3262 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3263 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3264 | .domain_alloc = amd_iommu_domain_alloc, |
3265 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3266 | .attach_dev = amd_iommu_attach_device, |
3267 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3268 | .map = amd_iommu_map, |
3269 | .unmap = amd_iommu_unmap, | |
315786eb | 3270 | .map_sg = default_iommu_map_sg, |
26961efe | 3271 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3272 | .add_device = amd_iommu_add_device, |
3273 | .remove_device = amd_iommu_remove_device, | |
a960fadb | 3274 | .device_group = pci_device_group, |
35cf248f JR |
3275 | .get_dm_regions = amd_iommu_get_dm_regions, |
3276 | .put_dm_regions = amd_iommu_put_dm_regions, | |
aa3de9c0 | 3277 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3278 | }; |
3279 | ||
0feae533 JR |
3280 | /***************************************************************************** |
3281 | * | |
3282 | * The next functions do a basic initialization of IOMMU for pass through | |
3283 | * mode | |
3284 | * | |
3285 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3286 | * DMA-API translation. | |
3287 | * | |
3288 | *****************************************************************************/ | |
3289 | ||
72e1dcc4 JR |
3290 | /* IOMMUv2 specific functions */ |
3291 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3292 | { | |
3293 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3294 | } | |
3295 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3296 | ||
3297 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3298 | { | |
3299 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3300 | } | |
3301 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3302 | |
3303 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3304 | { | |
3f4b87b9 | 3305 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3306 | unsigned long flags; |
3307 | ||
3308 | spin_lock_irqsave(&domain->lock, flags); | |
3309 | ||
3310 | /* Update data structure */ | |
3311 | domain->mode = PAGE_MODE_NONE; | |
3312 | domain->updated = true; | |
3313 | ||
3314 | /* Make changes visible to IOMMUs */ | |
3315 | update_domain(domain); | |
3316 | ||
3317 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3318 | free_pagetable(domain); | |
3319 | ||
3320 | spin_unlock_irqrestore(&domain->lock, flags); | |
3321 | } | |
3322 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3323 | |
3324 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3325 | { | |
3f4b87b9 | 3326 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3327 | unsigned long flags; |
3328 | int levels, ret; | |
3329 | ||
3330 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3331 | return -EINVAL; | |
3332 | ||
3333 | /* Number of GCR3 table levels required */ | |
3334 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3335 | levels += 1; | |
3336 | ||
3337 | if (levels > amd_iommu_max_glx_val) | |
3338 | return -EINVAL; | |
3339 | ||
3340 | spin_lock_irqsave(&domain->lock, flags); | |
3341 | ||
3342 | /* | |
3343 | * Save us all sanity checks whether devices already in the | |
3344 | * domain support IOMMUv2. Just force that the domain has no | |
3345 | * devices attached when it is switched into IOMMUv2 mode. | |
3346 | */ | |
3347 | ret = -EBUSY; | |
3348 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3349 | goto out; | |
3350 | ||
3351 | ret = -ENOMEM; | |
3352 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3353 | if (domain->gcr3_tbl == NULL) | |
3354 | goto out; | |
3355 | ||
3356 | domain->glx = levels; | |
3357 | domain->flags |= PD_IOMMUV2_MASK; | |
3358 | domain->updated = true; | |
3359 | ||
3360 | update_domain(domain); | |
3361 | ||
3362 | ret = 0; | |
3363 | ||
3364 | out: | |
3365 | spin_unlock_irqrestore(&domain->lock, flags); | |
3366 | ||
3367 | return ret; | |
3368 | } | |
3369 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3370 | |
3371 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3372 | u64 address, bool size) | |
3373 | { | |
3374 | struct iommu_dev_data *dev_data; | |
3375 | struct iommu_cmd cmd; | |
3376 | int i, ret; | |
3377 | ||
3378 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3379 | return -EINVAL; | |
3380 | ||
3381 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3382 | ||
3383 | /* | |
3384 | * IOMMU TLB needs to be flushed before Device TLB to | |
3385 | * prevent device TLB refill from IOMMU TLB | |
3386 | */ | |
3387 | for (i = 0; i < amd_iommus_present; ++i) { | |
3388 | if (domain->dev_iommu[i] == 0) | |
3389 | continue; | |
3390 | ||
3391 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3392 | if (ret != 0) | |
3393 | goto out; | |
3394 | } | |
3395 | ||
3396 | /* Wait until IOMMU TLB flushes are complete */ | |
3397 | domain_flush_complete(domain); | |
3398 | ||
3399 | /* Now flush device TLBs */ | |
3400 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3401 | struct amd_iommu *iommu; | |
3402 | int qdep; | |
3403 | ||
1c1cc454 JR |
3404 | /* |
3405 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3406 | * domain. | |
3407 | */ | |
3408 | if (!dev_data->ats.enabled) | |
3409 | continue; | |
22e266c7 JR |
3410 | |
3411 | qdep = dev_data->ats.qdep; | |
3412 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3413 | ||
3414 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3415 | qdep, address, size); | |
3416 | ||
3417 | ret = iommu_queue_command(iommu, &cmd); | |
3418 | if (ret != 0) | |
3419 | goto out; | |
3420 | } | |
3421 | ||
3422 | /* Wait until all device TLBs are flushed */ | |
3423 | domain_flush_complete(domain); | |
3424 | ||
3425 | ret = 0; | |
3426 | ||
3427 | out: | |
3428 | ||
3429 | return ret; | |
3430 | } | |
3431 | ||
3432 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3433 | u64 address) | |
3434 | { | |
399be2f5 JR |
3435 | INC_STATS_COUNTER(invalidate_iotlb); |
3436 | ||
22e266c7 JR |
3437 | return __flush_pasid(domain, pasid, address, false); |
3438 | } | |
3439 | ||
3440 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3441 | u64 address) | |
3442 | { | |
3f4b87b9 | 3443 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3444 | unsigned long flags; |
3445 | int ret; | |
3446 | ||
3447 | spin_lock_irqsave(&domain->lock, flags); | |
3448 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3449 | spin_unlock_irqrestore(&domain->lock, flags); | |
3450 | ||
3451 | return ret; | |
3452 | } | |
3453 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3454 | ||
3455 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3456 | { | |
399be2f5 JR |
3457 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3458 | ||
22e266c7 JR |
3459 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3460 | true); | |
3461 | } | |
3462 | ||
3463 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3464 | { | |
3f4b87b9 | 3465 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3466 | unsigned long flags; |
3467 | int ret; | |
3468 | ||
3469 | spin_lock_irqsave(&domain->lock, flags); | |
3470 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3471 | spin_unlock_irqrestore(&domain->lock, flags); | |
3472 | ||
3473 | return ret; | |
3474 | } | |
3475 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3476 | ||
b16137b1 JR |
3477 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3478 | { | |
3479 | int index; | |
3480 | u64 *pte; | |
3481 | ||
3482 | while (true) { | |
3483 | ||
3484 | index = (pasid >> (9 * level)) & 0x1ff; | |
3485 | pte = &root[index]; | |
3486 | ||
3487 | if (level == 0) | |
3488 | break; | |
3489 | ||
3490 | if (!(*pte & GCR3_VALID)) { | |
3491 | if (!alloc) | |
3492 | return NULL; | |
3493 | ||
3494 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3495 | if (root == NULL) | |
3496 | return NULL; | |
3497 | ||
3498 | *pte = __pa(root) | GCR3_VALID; | |
3499 | } | |
3500 | ||
3501 | root = __va(*pte & PAGE_MASK); | |
3502 | ||
3503 | level -= 1; | |
3504 | } | |
3505 | ||
3506 | return pte; | |
3507 | } | |
3508 | ||
3509 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3510 | unsigned long cr3) | |
3511 | { | |
3512 | u64 *pte; | |
3513 | ||
3514 | if (domain->mode != PAGE_MODE_NONE) | |
3515 | return -EINVAL; | |
3516 | ||
3517 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3518 | if (pte == NULL) | |
3519 | return -ENOMEM; | |
3520 | ||
3521 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3522 | ||
3523 | return __amd_iommu_flush_tlb(domain, pasid); | |
3524 | } | |
3525 | ||
3526 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3527 | { | |
3528 | u64 *pte; | |
3529 | ||
3530 | if (domain->mode != PAGE_MODE_NONE) | |
3531 | return -EINVAL; | |
3532 | ||
3533 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3534 | if (pte == NULL) | |
3535 | return 0; | |
3536 | ||
3537 | *pte = 0; | |
3538 | ||
3539 | return __amd_iommu_flush_tlb(domain, pasid); | |
3540 | } | |
3541 | ||
3542 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3543 | unsigned long cr3) | |
3544 | { | |
3f4b87b9 | 3545 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3546 | unsigned long flags; |
3547 | int ret; | |
3548 | ||
3549 | spin_lock_irqsave(&domain->lock, flags); | |
3550 | ret = __set_gcr3(domain, pasid, cr3); | |
3551 | spin_unlock_irqrestore(&domain->lock, flags); | |
3552 | ||
3553 | return ret; | |
3554 | } | |
3555 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3556 | ||
3557 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3558 | { | |
3f4b87b9 | 3559 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3560 | unsigned long flags; |
3561 | int ret; | |
3562 | ||
3563 | spin_lock_irqsave(&domain->lock, flags); | |
3564 | ret = __clear_gcr3(domain, pasid); | |
3565 | spin_unlock_irqrestore(&domain->lock, flags); | |
3566 | ||
3567 | return ret; | |
3568 | } | |
3569 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3570 | |
3571 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3572 | int status, int tag) | |
3573 | { | |
3574 | struct iommu_dev_data *dev_data; | |
3575 | struct amd_iommu *iommu; | |
3576 | struct iommu_cmd cmd; | |
3577 | ||
399be2f5 JR |
3578 | INC_STATS_COUNTER(complete_ppr); |
3579 | ||
c99afa25 JR |
3580 | dev_data = get_dev_data(&pdev->dev); |
3581 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3582 | ||
3583 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3584 | tag, dev_data->pri_tlp); | |
3585 | ||
3586 | return iommu_queue_command(iommu, &cmd); | |
3587 | } | |
3588 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3589 | |
3590 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3591 | { | |
3f4b87b9 | 3592 | struct protection_domain *pdomain; |
f3572db8 | 3593 | |
3f4b87b9 JR |
3594 | pdomain = get_domain(&pdev->dev); |
3595 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3596 | return NULL; |
3597 | ||
3598 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3599 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3600 | return NULL; |
3601 | ||
3f4b87b9 | 3602 | return &pdomain->domain; |
f3572db8 JR |
3603 | } |
3604 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3605 | |
3606 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3607 | { | |
3608 | struct iommu_dev_data *dev_data; | |
3609 | ||
3610 | if (!amd_iommu_v2_supported()) | |
3611 | return; | |
3612 | ||
3613 | dev_data = get_dev_data(&pdev->dev); | |
3614 | dev_data->errata |= (1 << erratum); | |
3615 | } | |
3616 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3617 | |
3618 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3619 | struct amd_iommu_device_info *info) | |
3620 | { | |
3621 | int max_pasids; | |
3622 | int pos; | |
3623 | ||
3624 | if (pdev == NULL || info == NULL) | |
3625 | return -EINVAL; | |
3626 | ||
3627 | if (!amd_iommu_v2_supported()) | |
3628 | return -EINVAL; | |
3629 | ||
3630 | memset(info, 0, sizeof(*info)); | |
3631 | ||
3632 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3633 | if (pos) | |
3634 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3635 | ||
3636 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3637 | if (pos) | |
3638 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3639 | ||
3640 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3641 | if (pos) { | |
3642 | int features; | |
3643 | ||
3644 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3645 | max_pasids = min(max_pasids, (1 << 20)); | |
3646 | ||
3647 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3648 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3649 | ||
3650 | features = pci_pasid_features(pdev); | |
3651 | if (features & PCI_PASID_CAP_EXEC) | |
3652 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3653 | if (features & PCI_PASID_CAP_PRIV) | |
3654 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3655 | } | |
3656 | ||
3657 | return 0; | |
3658 | } | |
3659 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3660 | |
3661 | #ifdef CONFIG_IRQ_REMAP | |
3662 | ||
3663 | /***************************************************************************** | |
3664 | * | |
3665 | * Interrupt Remapping Implementation | |
3666 | * | |
3667 | *****************************************************************************/ | |
3668 | ||
3669 | union irte { | |
3670 | u32 val; | |
3671 | struct { | |
3672 | u32 valid : 1, | |
3673 | no_fault : 1, | |
3674 | int_type : 3, | |
3675 | rq_eoi : 1, | |
3676 | dm : 1, | |
3677 | rsvd_1 : 1, | |
3678 | destination : 8, | |
3679 | vector : 8, | |
3680 | rsvd_2 : 8; | |
3681 | } fields; | |
3682 | }; | |
3683 | ||
9c724966 JL |
3684 | struct irq_2_irte { |
3685 | u16 devid; /* Device ID for IRTE table */ | |
3686 | u16 index; /* Index into IRTE table*/ | |
3687 | }; | |
3688 | ||
7c71d306 JL |
3689 | struct amd_ir_data { |
3690 | struct irq_2_irte irq_2_irte; | |
3691 | union irte irte_entry; | |
3692 | union { | |
3693 | struct msi_msg msi_entry; | |
3694 | }; | |
3695 | }; | |
3696 | ||
3697 | static struct irq_chip amd_ir_chip; | |
3698 | ||
2b324506 JR |
3699 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3700 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3701 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3702 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3703 | ||
3704 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3705 | { | |
3706 | u64 dte; | |
3707 | ||
3708 | dte = amd_iommu_dev_table[devid].data[2]; | |
3709 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3710 | dte |= virt_to_phys(table->table); | |
3711 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3712 | dte |= DTE_IRQ_TABLE_LEN; | |
3713 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3714 | ||
3715 | amd_iommu_dev_table[devid].data[2] = dte; | |
3716 | } | |
3717 | ||
3718 | #define IRTE_ALLOCATED (~1U) | |
3719 | ||
3720 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3721 | { | |
3722 | struct irq_remap_table *table = NULL; | |
3723 | struct amd_iommu *iommu; | |
3724 | unsigned long flags; | |
3725 | u16 alias; | |
3726 | ||
3727 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3728 | ||
3729 | iommu = amd_iommu_rlookup_table[devid]; | |
3730 | if (!iommu) | |
3731 | goto out_unlock; | |
3732 | ||
3733 | table = irq_lookup_table[devid]; | |
3734 | if (table) | |
3735 | goto out; | |
3736 | ||
3737 | alias = amd_iommu_alias_table[devid]; | |
3738 | table = irq_lookup_table[alias]; | |
3739 | if (table) { | |
3740 | irq_lookup_table[devid] = table; | |
3741 | set_dte_irq_entry(devid, table); | |
3742 | iommu_flush_dte(iommu, devid); | |
3743 | goto out; | |
3744 | } | |
3745 | ||
3746 | /* Nothing there yet, allocate new irq remapping table */ | |
3747 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3748 | if (!table) | |
3749 | goto out; | |
3750 | ||
197887f0 JR |
3751 | /* Initialize table spin-lock */ |
3752 | spin_lock_init(&table->lock); | |
3753 | ||
2b324506 JR |
3754 | if (ioapic) |
3755 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3756 | table->min_index = 32; | |
3757 | ||
3758 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3759 | if (!table->table) { | |
3760 | kfree(table); | |
821f0f68 | 3761 | table = NULL; |
2b324506 JR |
3762 | goto out; |
3763 | } | |
3764 | ||
3765 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3766 | ||
3767 | if (ioapic) { | |
3768 | int i; | |
3769 | ||
3770 | for (i = 0; i < 32; ++i) | |
3771 | table->table[i] = IRTE_ALLOCATED; | |
3772 | } | |
3773 | ||
3774 | irq_lookup_table[devid] = table; | |
3775 | set_dte_irq_entry(devid, table); | |
3776 | iommu_flush_dte(iommu, devid); | |
3777 | if (devid != alias) { | |
3778 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3779 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3780 | iommu_flush_dte(iommu, alias); |
3781 | } | |
3782 | ||
3783 | out: | |
3784 | iommu_completion_wait(iommu); | |
3785 | ||
3786 | out_unlock: | |
3787 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3788 | ||
3789 | return table; | |
3790 | } | |
3791 | ||
3c3d4f90 | 3792 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3793 | { |
3794 | struct irq_remap_table *table; | |
3795 | unsigned long flags; | |
3796 | int index, c; | |
3797 | ||
3798 | table = get_irq_table(devid, false); | |
3799 | if (!table) | |
3800 | return -ENODEV; | |
3801 | ||
3802 | spin_lock_irqsave(&table->lock, flags); | |
3803 | ||
3804 | /* Scan table for free entries */ | |
3805 | for (c = 0, index = table->min_index; | |
3806 | index < MAX_IRQS_PER_TABLE; | |
3807 | ++index) { | |
3808 | if (table->table[index] == 0) | |
3809 | c += 1; | |
3810 | else | |
3811 | c = 0; | |
3812 | ||
3813 | if (c == count) { | |
2b324506 JR |
3814 | for (; c != 0; --c) |
3815 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3816 | ||
3817 | index -= count - 1; | |
2b324506 JR |
3818 | goto out; |
3819 | } | |
3820 | } | |
3821 | ||
3822 | index = -ENOSPC; | |
3823 | ||
3824 | out: | |
3825 | spin_unlock_irqrestore(&table->lock, flags); | |
3826 | ||
3827 | return index; | |
3828 | } | |
3829 | ||
2b324506 JR |
3830 | static int modify_irte(u16 devid, int index, union irte irte) |
3831 | { | |
3832 | struct irq_remap_table *table; | |
3833 | struct amd_iommu *iommu; | |
3834 | unsigned long flags; | |
3835 | ||
3836 | iommu = amd_iommu_rlookup_table[devid]; | |
3837 | if (iommu == NULL) | |
3838 | return -EINVAL; | |
3839 | ||
3840 | table = get_irq_table(devid, false); | |
3841 | if (!table) | |
3842 | return -ENOMEM; | |
3843 | ||
3844 | spin_lock_irqsave(&table->lock, flags); | |
3845 | table->table[index] = irte.val; | |
3846 | spin_unlock_irqrestore(&table->lock, flags); | |
3847 | ||
3848 | iommu_flush_irt(iommu, devid); | |
3849 | iommu_completion_wait(iommu); | |
3850 | ||
3851 | return 0; | |
3852 | } | |
3853 | ||
3854 | static void free_irte(u16 devid, int index) | |
3855 | { | |
3856 | struct irq_remap_table *table; | |
3857 | struct amd_iommu *iommu; | |
3858 | unsigned long flags; | |
3859 | ||
3860 | iommu = amd_iommu_rlookup_table[devid]; | |
3861 | if (iommu == NULL) | |
3862 | return; | |
3863 | ||
3864 | table = get_irq_table(devid, false); | |
3865 | if (!table) | |
3866 | return; | |
3867 | ||
3868 | spin_lock_irqsave(&table->lock, flags); | |
3869 | table->table[index] = 0; | |
3870 | spin_unlock_irqrestore(&table->lock, flags); | |
3871 | ||
3872 | iommu_flush_irt(iommu, devid); | |
3873 | iommu_completion_wait(iommu); | |
3874 | } | |
3875 | ||
7c71d306 | 3876 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3877 | { |
7c71d306 | 3878 | int devid = -1; |
5527de74 | 3879 | |
7c71d306 JL |
3880 | switch (info->type) { |
3881 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3882 | devid = get_ioapic_devid(info->ioapic_id); | |
3883 | break; | |
3884 | case X86_IRQ_ALLOC_TYPE_HPET: | |
3885 | devid = get_hpet_devid(info->hpet_id); | |
3886 | break; | |
3887 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3888 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3889 | devid = get_device_id(&info->msi_dev->dev); | |
3890 | break; | |
3891 | default: | |
3892 | BUG_ON(1); | |
3893 | break; | |
3894 | } | |
5527de74 | 3895 | |
7c71d306 JL |
3896 | return devid; |
3897 | } | |
5527de74 | 3898 | |
7c71d306 JL |
3899 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
3900 | { | |
3901 | struct amd_iommu *iommu; | |
3902 | int devid; | |
5527de74 | 3903 | |
7c71d306 JL |
3904 | if (!info) |
3905 | return NULL; | |
5527de74 | 3906 | |
7c71d306 JL |
3907 | devid = get_devid(info); |
3908 | if (devid >= 0) { | |
3909 | iommu = amd_iommu_rlookup_table[devid]; | |
3910 | if (iommu) | |
3911 | return iommu->ir_domain; | |
3912 | } | |
5527de74 | 3913 | |
7c71d306 | 3914 | return NULL; |
5527de74 JR |
3915 | } |
3916 | ||
7c71d306 | 3917 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 3918 | { |
7c71d306 JL |
3919 | struct amd_iommu *iommu; |
3920 | int devid; | |
5527de74 | 3921 | |
7c71d306 JL |
3922 | if (!info) |
3923 | return NULL; | |
5527de74 | 3924 | |
7c71d306 JL |
3925 | switch (info->type) { |
3926 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3927 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3928 | devid = get_device_id(&info->msi_dev->dev); | |
1fb260bc DC |
3929 | iommu = amd_iommu_rlookup_table[devid]; |
3930 | if (iommu) | |
3931 | return iommu->msi_domain; | |
7c71d306 JL |
3932 | break; |
3933 | default: | |
3934 | break; | |
3935 | } | |
5527de74 | 3936 | |
7c71d306 JL |
3937 | return NULL; |
3938 | } | |
5527de74 | 3939 | |
6b474b82 | 3940 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
3941 | .prepare = amd_iommu_prepare, |
3942 | .enable = amd_iommu_enable, | |
3943 | .disable = amd_iommu_disable, | |
3944 | .reenable = amd_iommu_reenable, | |
3945 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
3946 | .get_ir_irq_domain = get_ir_irq_domain, |
3947 | .get_irq_domain = get_irq_domain, | |
3948 | }; | |
5527de74 | 3949 | |
7c71d306 JL |
3950 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
3951 | struct irq_cfg *irq_cfg, | |
3952 | struct irq_alloc_info *info, | |
3953 | int devid, int index, int sub_handle) | |
3954 | { | |
3955 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
3956 | struct msi_msg *msg = &data->msi_entry; | |
3957 | union irte *irte = &data->irte_entry; | |
3958 | struct IO_APIC_route_entry *entry; | |
5527de74 | 3959 | |
7c71d306 JL |
3960 | data->irq_2_irte.devid = devid; |
3961 | data->irq_2_irte.index = index + sub_handle; | |
5527de74 | 3962 | |
7c71d306 JL |
3963 | /* Setup IRTE for IOMMU */ |
3964 | irte->val = 0; | |
3965 | irte->fields.vector = irq_cfg->vector; | |
3966 | irte->fields.int_type = apic->irq_delivery_mode; | |
3967 | irte->fields.destination = irq_cfg->dest_apicid; | |
3968 | irte->fields.dm = apic->irq_dest_mode; | |
3969 | irte->fields.valid = 1; | |
3970 | ||
3971 | switch (info->type) { | |
3972 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3973 | /* Setup IOAPIC entry */ | |
3974 | entry = info->ioapic_entry; | |
3975 | info->ioapic_entry = NULL; | |
3976 | memset(entry, 0, sizeof(*entry)); | |
3977 | entry->vector = index; | |
3978 | entry->mask = 0; | |
3979 | entry->trigger = info->ioapic_trigger; | |
3980 | entry->polarity = info->ioapic_polarity; | |
3981 | /* Mask level triggered irqs. */ | |
3982 | if (info->ioapic_trigger) | |
3983 | entry->mask = 1; | |
3984 | break; | |
5527de74 | 3985 | |
7c71d306 JL |
3986 | case X86_IRQ_ALLOC_TYPE_HPET: |
3987 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3988 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3989 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3990 | msg->address_lo = MSI_ADDR_BASE_LO; | |
3991 | msg->data = irte_info->index; | |
3992 | break; | |
5527de74 | 3993 | |
7c71d306 JL |
3994 | default: |
3995 | BUG_ON(1); | |
3996 | break; | |
3997 | } | |
5527de74 JR |
3998 | } |
3999 | ||
7c71d306 JL |
4000 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4001 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4002 | { |
7c71d306 JL |
4003 | struct irq_alloc_info *info = arg; |
4004 | struct irq_data *irq_data; | |
4005 | struct amd_ir_data *data; | |
5527de74 | 4006 | struct irq_cfg *cfg; |
7c71d306 JL |
4007 | int i, ret, devid; |
4008 | int index = -1; | |
5527de74 | 4009 | |
7c71d306 JL |
4010 | if (!info) |
4011 | return -EINVAL; | |
4012 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4013 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4014 | return -EINVAL; |
4015 | ||
7c71d306 JL |
4016 | /* |
4017 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4018 | * to support multiple MSI interrupts. | |
4019 | */ | |
4020 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4021 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4022 | |
7c71d306 JL |
4023 | devid = get_devid(info); |
4024 | if (devid < 0) | |
4025 | return -EINVAL; | |
5527de74 | 4026 | |
7c71d306 JL |
4027 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4028 | if (ret < 0) | |
4029 | return ret; | |
0b4d48cb | 4030 | |
7c71d306 JL |
4031 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
4032 | if (get_irq_table(devid, true)) | |
4033 | index = info->ioapic_pin; | |
4034 | else | |
4035 | ret = -ENOMEM; | |
4036 | } else { | |
3c3d4f90 | 4037 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
4038 | } |
4039 | if (index < 0) { | |
4040 | pr_warn("Failed to allocate IRTE\n"); | |
7c71d306 JL |
4041 | goto out_free_parent; |
4042 | } | |
0b4d48cb | 4043 | |
7c71d306 JL |
4044 | for (i = 0; i < nr_irqs; i++) { |
4045 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4046 | cfg = irqd_cfg(irq_data); | |
4047 | if (!irq_data || !cfg) { | |
4048 | ret = -EINVAL; | |
4049 | goto out_free_data; | |
4050 | } | |
0b4d48cb | 4051 | |
a130e69f JR |
4052 | ret = -ENOMEM; |
4053 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4054 | if (!data) | |
4055 | goto out_free_data; | |
4056 | ||
7c71d306 JL |
4057 | irq_data->hwirq = (devid << 16) + i; |
4058 | irq_data->chip_data = data; | |
4059 | irq_data->chip = &amd_ir_chip; | |
4060 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4061 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4062 | } | |
a130e69f | 4063 | |
7c71d306 | 4064 | return 0; |
0b4d48cb | 4065 | |
7c71d306 JL |
4066 | out_free_data: |
4067 | for (i--; i >= 0; i--) { | |
4068 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4069 | if (irq_data) | |
4070 | kfree(irq_data->chip_data); | |
4071 | } | |
4072 | for (i = 0; i < nr_irqs; i++) | |
4073 | free_irte(devid, index + i); | |
4074 | out_free_parent: | |
4075 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4076 | return ret; | |
0b4d48cb JR |
4077 | } |
4078 | ||
7c71d306 JL |
4079 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4080 | unsigned int nr_irqs) | |
0b4d48cb | 4081 | { |
7c71d306 JL |
4082 | struct irq_2_irte *irte_info; |
4083 | struct irq_data *irq_data; | |
4084 | struct amd_ir_data *data; | |
4085 | int i; | |
0b4d48cb | 4086 | |
7c71d306 JL |
4087 | for (i = 0; i < nr_irqs; i++) { |
4088 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4089 | if (irq_data && irq_data->chip_data) { | |
4090 | data = irq_data->chip_data; | |
4091 | irte_info = &data->irq_2_irte; | |
4092 | free_irte(irte_info->devid, irte_info->index); | |
4093 | kfree(data); | |
4094 | } | |
4095 | } | |
4096 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4097 | } | |
0b4d48cb | 4098 | |
7c71d306 JL |
4099 | static void irq_remapping_activate(struct irq_domain *domain, |
4100 | struct irq_data *irq_data) | |
4101 | { | |
4102 | struct amd_ir_data *data = irq_data->chip_data; | |
4103 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
0b4d48cb | 4104 | |
7c71d306 | 4105 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); |
0b4d48cb JR |
4106 | } |
4107 | ||
7c71d306 JL |
4108 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4109 | struct irq_data *irq_data) | |
0b4d48cb | 4110 | { |
7c71d306 JL |
4111 | struct amd_ir_data *data = irq_data->chip_data; |
4112 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4113 | union irte entry; | |
0b4d48cb | 4114 | |
7c71d306 JL |
4115 | entry.val = 0; |
4116 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); | |
4117 | } | |
0b4d48cb | 4118 | |
7c71d306 JL |
4119 | static struct irq_domain_ops amd_ir_domain_ops = { |
4120 | .alloc = irq_remapping_alloc, | |
4121 | .free = irq_remapping_free, | |
4122 | .activate = irq_remapping_activate, | |
4123 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4124 | }; |
0b4d48cb | 4125 | |
7c71d306 JL |
4126 | static int amd_ir_set_affinity(struct irq_data *data, |
4127 | const struct cpumask *mask, bool force) | |
4128 | { | |
4129 | struct amd_ir_data *ir_data = data->chip_data; | |
4130 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4131 | struct irq_cfg *cfg = irqd_cfg(data); | |
4132 | struct irq_data *parent = data->parent_data; | |
4133 | int ret; | |
0b4d48cb | 4134 | |
7c71d306 JL |
4135 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4136 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4137 | return ret; | |
0b4d48cb | 4138 | |
7c71d306 JL |
4139 | /* |
4140 | * Atomically updates the IRTE with the new destination, vector | |
4141 | * and flushes the interrupt entry cache. | |
4142 | */ | |
4143 | ir_data->irte_entry.fields.vector = cfg->vector; | |
4144 | ir_data->irte_entry.fields.destination = cfg->dest_apicid; | |
4145 | modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry); | |
0b4d48cb | 4146 | |
7c71d306 JL |
4147 | /* |
4148 | * After this point, all the interrupts will start arriving | |
4149 | * at the new destination. So, time to cleanup the previous | |
4150 | * vector allocation. | |
4151 | */ | |
c6c2002b | 4152 | send_cleanup_vector(cfg); |
7c71d306 JL |
4153 | |
4154 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4155 | } |
4156 | ||
7c71d306 | 4157 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4158 | { |
7c71d306 | 4159 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4160 | |
7c71d306 JL |
4161 | *msg = ir_data->msi_entry; |
4162 | } | |
d976195c | 4163 | |
7c71d306 JL |
4164 | static struct irq_chip amd_ir_chip = { |
4165 | .irq_ack = ir_ack_apic_edge, | |
4166 | .irq_set_affinity = amd_ir_set_affinity, | |
4167 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
4168 | }; | |
d976195c | 4169 | |
7c71d306 JL |
4170 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4171 | { | |
4172 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
4173 | if (!iommu->ir_domain) | |
4174 | return -ENOMEM; | |
d976195c | 4175 | |
7c71d306 JL |
4176 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
4177 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
4178 | |
4179 | return 0; | |
4180 | } | |
2b324506 | 4181 | #endif |