Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
17f5b569 | 34 | #include <asm/msidef.h> |
b6c02715 | 35 | #include <asm/proto.h> |
46a7fa27 | 36 | #include <asm/iommu.h> |
1d9b16d1 | 37 | #include <asm/gart.h> |
27c2127a | 38 | #include <asm/dma.h> |
403f81d8 JR |
39 | |
40 | #include "amd_iommu_proto.h" | |
41 | #include "amd_iommu_types.h" | |
b6c02715 JR |
42 | |
43 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
44 | ||
815b33fd | 45 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 46 | |
b6c02715 JR |
47 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
48 | ||
bd60b735 JR |
49 | /* A list of preallocated protection domains */ |
50 | static LIST_HEAD(iommu_pd_list); | |
51 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
52 | ||
8fa5f802 JR |
53 | /* List of all available dev_data structures */ |
54 | static LIST_HEAD(dev_data_list); | |
55 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
56 | ||
0feae533 JR |
57 | /* |
58 | * Domain for untranslated devices - only allocated | |
59 | * if iommu=pt passed on kernel cmd line. | |
60 | */ | |
61 | static struct protection_domain *pt_domain; | |
62 | ||
26961efe | 63 | static struct iommu_ops amd_iommu_ops; |
26961efe | 64 | |
72e1dcc4 | 65 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 66 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 67 | |
431b2a20 JR |
68 | /* |
69 | * general struct to manage commands send to an IOMMU | |
70 | */ | |
d6449536 | 71 | struct iommu_cmd { |
b6c02715 JR |
72 | u32 data[4]; |
73 | }; | |
74 | ||
04bfdd84 | 75 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 76 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 77 | |
15898bbc JR |
78 | /**************************************************************************** |
79 | * | |
80 | * Helper functions | |
81 | * | |
82 | ****************************************************************************/ | |
83 | ||
f62dda66 | 84 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
85 | { |
86 | struct iommu_dev_data *dev_data; | |
87 | unsigned long flags; | |
88 | ||
89 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
90 | if (!dev_data) | |
91 | return NULL; | |
92 | ||
f62dda66 | 93 | dev_data->devid = devid; |
8fa5f802 JR |
94 | atomic_set(&dev_data->bind, 0); |
95 | ||
96 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
97 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
98 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
99 | ||
100 | return dev_data; | |
101 | } | |
102 | ||
103 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
104 | { | |
105 | unsigned long flags; | |
106 | ||
107 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
108 | list_del(&dev_data->dev_data_list); | |
109 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
110 | ||
111 | kfree(dev_data); | |
112 | } | |
113 | ||
3b03bb74 JR |
114 | static struct iommu_dev_data *search_dev_data(u16 devid) |
115 | { | |
116 | struct iommu_dev_data *dev_data; | |
117 | unsigned long flags; | |
118 | ||
119 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
120 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
121 | if (dev_data->devid == devid) | |
122 | goto out_unlock; | |
123 | } | |
124 | ||
125 | dev_data = NULL; | |
126 | ||
127 | out_unlock: | |
128 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
129 | ||
130 | return dev_data; | |
131 | } | |
132 | ||
133 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
134 | { | |
135 | struct iommu_dev_data *dev_data; | |
136 | ||
137 | dev_data = search_dev_data(devid); | |
138 | ||
139 | if (dev_data == NULL) | |
140 | dev_data = alloc_dev_data(devid); | |
141 | ||
142 | return dev_data; | |
143 | } | |
144 | ||
15898bbc JR |
145 | static inline u16 get_device_id(struct device *dev) |
146 | { | |
147 | struct pci_dev *pdev = to_pci_dev(dev); | |
148 | ||
149 | return calc_devid(pdev->bus->number, pdev->devfn); | |
150 | } | |
151 | ||
657cbb6b JR |
152 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
153 | { | |
154 | return dev->archdata.iommu; | |
155 | } | |
156 | ||
5abcdba4 JR |
157 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
158 | { | |
159 | static const int caps[] = { | |
160 | PCI_EXT_CAP_ID_ATS, | |
161 | PCI_PRI_CAP, | |
162 | PCI_PASID_CAP, | |
163 | }; | |
164 | int i, pos; | |
165 | ||
166 | for (i = 0; i < 3; ++i) { | |
167 | pos = pci_find_ext_capability(pdev, caps[i]); | |
168 | if (pos == 0) | |
169 | return false; | |
170 | } | |
171 | ||
172 | return true; | |
173 | } | |
174 | ||
71c70984 JR |
175 | /* |
176 | * In this function the list of preallocated protection domains is traversed to | |
177 | * find the domain for a specific device | |
178 | */ | |
179 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
180 | { | |
181 | struct dma_ops_domain *entry, *ret = NULL; | |
182 | unsigned long flags; | |
183 | u16 alias = amd_iommu_alias_table[devid]; | |
184 | ||
185 | if (list_empty(&iommu_pd_list)) | |
186 | return NULL; | |
187 | ||
188 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
189 | ||
190 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
191 | if (entry->target_dev == devid || | |
192 | entry->target_dev == alias) { | |
193 | ret = entry; | |
194 | break; | |
195 | } | |
196 | } | |
197 | ||
198 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
199 | ||
200 | return ret; | |
201 | } | |
202 | ||
98fc5a69 JR |
203 | /* |
204 | * This function checks if the driver got a valid device from the caller to | |
205 | * avoid dereferencing invalid pointers. | |
206 | */ | |
207 | static bool check_device(struct device *dev) | |
208 | { | |
209 | u16 devid; | |
210 | ||
211 | if (!dev || !dev->dma_mask) | |
212 | return false; | |
213 | ||
214 | /* No device or no PCI device */ | |
339d3261 | 215 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
216 | return false; |
217 | ||
218 | devid = get_device_id(dev); | |
219 | ||
220 | /* Out of our scope? */ | |
221 | if (devid > amd_iommu_last_bdf) | |
222 | return false; | |
223 | ||
224 | if (amd_iommu_rlookup_table[devid] == NULL) | |
225 | return false; | |
226 | ||
227 | return true; | |
228 | } | |
229 | ||
657cbb6b JR |
230 | static int iommu_init_device(struct device *dev) |
231 | { | |
5abcdba4 | 232 | struct pci_dev *pdev = to_pci_dev(dev); |
657cbb6b | 233 | struct iommu_dev_data *dev_data; |
8fa5f802 | 234 | u16 alias; |
657cbb6b JR |
235 | |
236 | if (dev->archdata.iommu) | |
237 | return 0; | |
238 | ||
3b03bb74 | 239 | dev_data = find_dev_data(get_device_id(dev)); |
657cbb6b JR |
240 | if (!dev_data) |
241 | return -ENOMEM; | |
242 | ||
f62dda66 | 243 | alias = amd_iommu_alias_table[dev_data->devid]; |
2b02b091 | 244 | if (alias != dev_data->devid) { |
71f77580 | 245 | struct iommu_dev_data *alias_data; |
b00d3bcf | 246 | |
71f77580 JR |
247 | alias_data = find_dev_data(alias); |
248 | if (alias_data == NULL) { | |
249 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
250 | dev_name(dev)); | |
2b02b091 JR |
251 | free_dev_data(dev_data); |
252 | return -ENOTSUPP; | |
253 | } | |
71f77580 | 254 | dev_data->alias_data = alias_data; |
26018874 | 255 | } |
657cbb6b | 256 | |
5abcdba4 JR |
257 | if (pci_iommuv2_capable(pdev)) { |
258 | struct amd_iommu *iommu; | |
259 | ||
260 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
261 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
262 | } | |
263 | ||
657cbb6b JR |
264 | dev->archdata.iommu = dev_data; |
265 | ||
657cbb6b JR |
266 | return 0; |
267 | } | |
268 | ||
26018874 JR |
269 | static void iommu_ignore_device(struct device *dev) |
270 | { | |
271 | u16 devid, alias; | |
272 | ||
273 | devid = get_device_id(dev); | |
274 | alias = amd_iommu_alias_table[devid]; | |
275 | ||
276 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
277 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
278 | ||
279 | amd_iommu_rlookup_table[devid] = NULL; | |
280 | amd_iommu_rlookup_table[alias] = NULL; | |
281 | } | |
282 | ||
657cbb6b JR |
283 | static void iommu_uninit_device(struct device *dev) |
284 | { | |
8fa5f802 JR |
285 | /* |
286 | * Nothing to do here - we keep dev_data around for unplugged devices | |
287 | * and reuse it when the device is re-plugged - not doing so would | |
288 | * introduce a ton of races. | |
289 | */ | |
657cbb6b | 290 | } |
b7cc9554 JR |
291 | |
292 | void __init amd_iommu_uninit_devices(void) | |
293 | { | |
8fa5f802 | 294 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
295 | struct pci_dev *pdev = NULL; |
296 | ||
297 | for_each_pci_dev(pdev) { | |
298 | ||
299 | if (!check_device(&pdev->dev)) | |
300 | continue; | |
301 | ||
302 | iommu_uninit_device(&pdev->dev); | |
303 | } | |
8fa5f802 JR |
304 | |
305 | /* Free all of our dev_data structures */ | |
306 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
307 | free_dev_data(dev_data); | |
b7cc9554 JR |
308 | } |
309 | ||
310 | int __init amd_iommu_init_devices(void) | |
311 | { | |
312 | struct pci_dev *pdev = NULL; | |
313 | int ret = 0; | |
314 | ||
315 | for_each_pci_dev(pdev) { | |
316 | ||
317 | if (!check_device(&pdev->dev)) | |
318 | continue; | |
319 | ||
320 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
321 | if (ret == -ENOTSUPP) |
322 | iommu_ignore_device(&pdev->dev); | |
323 | else if (ret) | |
b7cc9554 JR |
324 | goto out_free; |
325 | } | |
326 | ||
327 | return 0; | |
328 | ||
329 | out_free: | |
330 | ||
331 | amd_iommu_uninit_devices(); | |
332 | ||
333 | return ret; | |
334 | } | |
7f26508b JR |
335 | #ifdef CONFIG_AMD_IOMMU_STATS |
336 | ||
337 | /* | |
338 | * Initialization code for statistics collection | |
339 | */ | |
340 | ||
da49f6df | 341 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 342 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 343 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 344 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 345 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 346 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 347 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 348 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 349 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 350 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 351 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 352 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 353 | |
7f26508b | 354 | static struct dentry *stats_dir; |
7f26508b JR |
355 | static struct dentry *de_fflush; |
356 | ||
357 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
358 | { | |
359 | if (stats_dir == NULL) | |
360 | return; | |
361 | ||
362 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
363 | &cnt->value); | |
364 | } | |
365 | ||
366 | static void amd_iommu_stats_init(void) | |
367 | { | |
368 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
369 | if (stats_dir == NULL) | |
370 | return; | |
371 | ||
7f26508b JR |
372 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
373 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
374 | |
375 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 376 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 377 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 378 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 379 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 380 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 381 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 382 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 383 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 384 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 385 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 386 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
387 | } |
388 | ||
389 | #endif | |
390 | ||
a80dc3e0 JR |
391 | /**************************************************************************** |
392 | * | |
393 | * Interrupt handling functions | |
394 | * | |
395 | ****************************************************************************/ | |
396 | ||
e3e59876 JR |
397 | static void dump_dte_entry(u16 devid) |
398 | { | |
399 | int i; | |
400 | ||
ee6c2868 JR |
401 | for (i = 0; i < 4; ++i) |
402 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
403 | amd_iommu_dev_table[devid].data[i]); |
404 | } | |
405 | ||
945b4ac4 JR |
406 | static void dump_command(unsigned long phys_addr) |
407 | { | |
408 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
409 | int i; | |
410 | ||
411 | for (i = 0; i < 4; ++i) | |
412 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
413 | } | |
414 | ||
a345b23b | 415 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
416 | { |
417 | u32 *event = __evt; | |
418 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
419 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
420 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
421 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
422 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
423 | ||
4c6f40d4 | 424 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
425 | |
426 | switch (type) { | |
427 | case EVENT_TYPE_ILL_DEV: | |
428 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
429 | "address=0x%016llx flags=0x%04x]\n", | |
430 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
431 | address, flags); | |
e3e59876 | 432 | dump_dte_entry(devid); |
90008ee4 JR |
433 | break; |
434 | case EVENT_TYPE_IO_FAULT: | |
435 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
436 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
437 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
438 | domid, address, flags); | |
439 | break; | |
440 | case EVENT_TYPE_DEV_TAB_ERR: | |
441 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
442 | "address=0x%016llx flags=0x%04x]\n", | |
443 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
444 | address, flags); | |
445 | break; | |
446 | case EVENT_TYPE_PAGE_TAB_ERR: | |
447 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
448 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
449 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
450 | domid, address, flags); | |
451 | break; | |
452 | case EVENT_TYPE_ILL_CMD: | |
453 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 454 | dump_command(address); |
90008ee4 JR |
455 | break; |
456 | case EVENT_TYPE_CMD_HARD_ERR: | |
457 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
458 | "flags=0x%04x]\n", address, flags); | |
459 | break; | |
460 | case EVENT_TYPE_IOTLB_INV_TO: | |
461 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
462 | "address=0x%016llx]\n", | |
463 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
464 | address); | |
465 | break; | |
466 | case EVENT_TYPE_INV_DEV_REQ: | |
467 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
468 | "address=0x%016llx flags=0x%04x]\n", | |
469 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
470 | address, flags); | |
471 | break; | |
472 | default: | |
473 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
474 | } | |
475 | } | |
476 | ||
477 | static void iommu_poll_events(struct amd_iommu *iommu) | |
478 | { | |
479 | u32 head, tail; | |
480 | unsigned long flags; | |
481 | ||
482 | spin_lock_irqsave(&iommu->lock, flags); | |
483 | ||
484 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
485 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
486 | ||
487 | while (head != tail) { | |
a345b23b | 488 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
489 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
490 | } | |
491 | ||
492 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
493 | ||
494 | spin_unlock_irqrestore(&iommu->lock, flags); | |
495 | } | |
496 | ||
72e1dcc4 JR |
497 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head) |
498 | { | |
499 | struct amd_iommu_fault fault; | |
500 | volatile u64 *raw; | |
501 | int i; | |
502 | ||
503 | raw = (u64 *)(iommu->ppr_log + head); | |
504 | ||
505 | /* | |
506 | * Hardware bug: Interrupt may arrive before the entry is written to | |
507 | * memory. If this happens we need to wait for the entry to arrive. | |
508 | */ | |
509 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
510 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
511 | break; | |
512 | udelay(1); | |
513 | } | |
514 | ||
515 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { | |
516 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
517 | return; | |
518 | } | |
519 | ||
520 | fault.address = raw[1]; | |
521 | fault.pasid = PPR_PASID(raw[0]); | |
522 | fault.device_id = PPR_DEVID(raw[0]); | |
523 | fault.tag = PPR_TAG(raw[0]); | |
524 | fault.flags = PPR_FLAGS(raw[0]); | |
525 | ||
526 | /* | |
527 | * To detect the hardware bug we need to clear the entry | |
528 | * to back to zero. | |
529 | */ | |
530 | raw[0] = raw[1] = 0; | |
531 | ||
532 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); | |
533 | } | |
534 | ||
535 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
536 | { | |
537 | unsigned long flags; | |
538 | u32 head, tail; | |
539 | ||
540 | if (iommu->ppr_log == NULL) | |
541 | return; | |
542 | ||
543 | spin_lock_irqsave(&iommu->lock, flags); | |
544 | ||
545 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
546 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
547 | ||
548 | while (head != tail) { | |
549 | ||
550 | /* Handle PPR entry */ | |
551 | iommu_handle_ppr_entry(iommu, head); | |
552 | ||
553 | /* Update and refresh ring-buffer state*/ | |
554 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; | |
555 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
556 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
557 | } | |
558 | ||
559 | /* enable ppr interrupts again */ | |
560 | writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
561 | ||
562 | spin_unlock_irqrestore(&iommu->lock, flags); | |
563 | } | |
564 | ||
72fe00f0 | 565 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 566 | { |
90008ee4 JR |
567 | struct amd_iommu *iommu; |
568 | ||
72e1dcc4 | 569 | for_each_iommu(iommu) { |
90008ee4 | 570 | iommu_poll_events(iommu); |
72e1dcc4 JR |
571 | iommu_poll_ppr_log(iommu); |
572 | } | |
90008ee4 JR |
573 | |
574 | return IRQ_HANDLED; | |
a80dc3e0 JR |
575 | } |
576 | ||
72fe00f0 JR |
577 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
578 | { | |
579 | return IRQ_WAKE_THREAD; | |
580 | } | |
581 | ||
431b2a20 JR |
582 | /**************************************************************************** |
583 | * | |
584 | * IOMMU command queuing functions | |
585 | * | |
586 | ****************************************************************************/ | |
587 | ||
ac0ea6e9 JR |
588 | static int wait_on_sem(volatile u64 *sem) |
589 | { | |
590 | int i = 0; | |
591 | ||
592 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
593 | udelay(1); | |
594 | i += 1; | |
595 | } | |
596 | ||
597 | if (i == LOOP_TIMEOUT) { | |
598 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
599 | return -EIO; | |
600 | } | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
606 | struct iommu_cmd *cmd, | |
607 | u32 tail) | |
a19ae1ec | 608 | { |
a19ae1ec JR |
609 | u8 *target; |
610 | ||
8a7c5ef3 | 611 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
612 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
613 | ||
614 | /* Copy command to buffer */ | |
615 | memcpy(target, cmd, sizeof(*cmd)); | |
616 | ||
617 | /* Tell the IOMMU about it */ | |
a19ae1ec | 618 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 619 | } |
a19ae1ec | 620 | |
815b33fd | 621 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 622 | { |
815b33fd JR |
623 | WARN_ON(address & 0x7ULL); |
624 | ||
ded46737 | 625 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
626 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
627 | cmd->data[1] = upper_32_bits(__pa(address)); | |
628 | cmd->data[2] = 1; | |
ded46737 JR |
629 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
630 | } | |
631 | ||
94fe79e2 JR |
632 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
633 | { | |
634 | memset(cmd, 0, sizeof(*cmd)); | |
635 | cmd->data[0] = devid; | |
636 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
637 | } | |
638 | ||
11b6402c JR |
639 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
640 | size_t size, u16 domid, int pde) | |
641 | { | |
642 | u64 pages; | |
643 | int s; | |
644 | ||
645 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
646 | s = 0; | |
647 | ||
648 | if (pages > 1) { | |
649 | /* | |
650 | * If we have to flush more than one page, flush all | |
651 | * TLB entries for this domain | |
652 | */ | |
653 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
654 | s = 1; | |
655 | } | |
656 | ||
657 | address &= PAGE_MASK; | |
658 | ||
659 | memset(cmd, 0, sizeof(*cmd)); | |
660 | cmd->data[1] |= domid; | |
661 | cmd->data[2] = lower_32_bits(address); | |
662 | cmd->data[3] = upper_32_bits(address); | |
663 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
664 | if (s) /* size bit - we flush more than one 4kb page */ | |
665 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
666 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
667 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
668 | } | |
669 | ||
cb41ed85 JR |
670 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
671 | u64 address, size_t size) | |
672 | { | |
673 | u64 pages; | |
674 | int s; | |
675 | ||
676 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
677 | s = 0; | |
678 | ||
679 | if (pages > 1) { | |
680 | /* | |
681 | * If we have to flush more than one page, flush all | |
682 | * TLB entries for this domain | |
683 | */ | |
684 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
685 | s = 1; | |
686 | } | |
687 | ||
688 | address &= PAGE_MASK; | |
689 | ||
690 | memset(cmd, 0, sizeof(*cmd)); | |
691 | cmd->data[0] = devid; | |
692 | cmd->data[0] |= (qdep & 0xff) << 24; | |
693 | cmd->data[1] = devid; | |
694 | cmd->data[2] = lower_32_bits(address); | |
695 | cmd->data[3] = upper_32_bits(address); | |
696 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
697 | if (s) | |
698 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
699 | } | |
700 | ||
22e266c7 JR |
701 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
702 | u64 address, bool size) | |
703 | { | |
704 | memset(cmd, 0, sizeof(*cmd)); | |
705 | ||
706 | address &= ~(0xfffULL); | |
707 | ||
708 | cmd->data[0] = pasid & PASID_MASK; | |
709 | cmd->data[1] = domid; | |
710 | cmd->data[2] = lower_32_bits(address); | |
711 | cmd->data[3] = upper_32_bits(address); | |
712 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
713 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
714 | if (size) | |
715 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
716 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
717 | } | |
718 | ||
719 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
720 | int qdep, u64 address, bool size) | |
721 | { | |
722 | memset(cmd, 0, sizeof(*cmd)); | |
723 | ||
724 | address &= ~(0xfffULL); | |
725 | ||
726 | cmd->data[0] = devid; | |
727 | cmd->data[0] |= (pasid & 0xff) << 16; | |
728 | cmd->data[0] |= (qdep & 0xff) << 24; | |
729 | cmd->data[1] = devid; | |
730 | cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16; | |
731 | cmd->data[2] = lower_32_bits(address); | |
732 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
733 | cmd->data[3] = upper_32_bits(address); | |
734 | if (size) | |
735 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
736 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
737 | } | |
738 | ||
58fc7f14 JR |
739 | static void build_inv_all(struct iommu_cmd *cmd) |
740 | { | |
741 | memset(cmd, 0, sizeof(*cmd)); | |
742 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
743 | } |
744 | ||
431b2a20 | 745 | /* |
431b2a20 | 746 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 747 | * hardware about the new command. |
431b2a20 | 748 | */ |
f1ca1512 JR |
749 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
750 | struct iommu_cmd *cmd, | |
751 | bool sync) | |
a19ae1ec | 752 | { |
ac0ea6e9 | 753 | u32 left, tail, head, next_tail; |
a19ae1ec | 754 | unsigned long flags; |
a19ae1ec | 755 | |
549c90dc | 756 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
757 | |
758 | again: | |
a19ae1ec | 759 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 760 | |
ac0ea6e9 JR |
761 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
762 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
763 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
764 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 765 | |
ac0ea6e9 JR |
766 | if (left <= 2) { |
767 | struct iommu_cmd sync_cmd; | |
768 | volatile u64 sem = 0; | |
769 | int ret; | |
8d201968 | 770 | |
ac0ea6e9 JR |
771 | build_completion_wait(&sync_cmd, (u64)&sem); |
772 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 773 | |
ac0ea6e9 JR |
774 | spin_unlock_irqrestore(&iommu->lock, flags); |
775 | ||
776 | if ((ret = wait_on_sem(&sem)) != 0) | |
777 | return ret; | |
778 | ||
779 | goto again; | |
8d201968 JR |
780 | } |
781 | ||
ac0ea6e9 JR |
782 | copy_cmd_to_buffer(iommu, cmd, tail); |
783 | ||
784 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 785 | iommu->need_sync = sync; |
ac0ea6e9 | 786 | |
a19ae1ec | 787 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 788 | |
815b33fd | 789 | return 0; |
8d201968 JR |
790 | } |
791 | ||
f1ca1512 JR |
792 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
793 | { | |
794 | return iommu_queue_command_sync(iommu, cmd, true); | |
795 | } | |
796 | ||
8d201968 JR |
797 | /* |
798 | * This function queues a completion wait command into the command | |
799 | * buffer of an IOMMU | |
800 | */ | |
a19ae1ec | 801 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
802 | { |
803 | struct iommu_cmd cmd; | |
815b33fd | 804 | volatile u64 sem = 0; |
ac0ea6e9 | 805 | int ret; |
8d201968 | 806 | |
09ee17eb | 807 | if (!iommu->need_sync) |
815b33fd | 808 | return 0; |
09ee17eb | 809 | |
815b33fd | 810 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 811 | |
f1ca1512 | 812 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 813 | if (ret) |
815b33fd | 814 | return ret; |
8d201968 | 815 | |
ac0ea6e9 | 816 | return wait_on_sem(&sem); |
8d201968 JR |
817 | } |
818 | ||
d8c13085 | 819 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 820 | { |
d8c13085 | 821 | struct iommu_cmd cmd; |
a19ae1ec | 822 | |
d8c13085 | 823 | build_inv_dte(&cmd, devid); |
7e4f88da | 824 | |
d8c13085 JR |
825 | return iommu_queue_command(iommu, &cmd); |
826 | } | |
09ee17eb | 827 | |
7d0c5cc5 JR |
828 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
829 | { | |
830 | u32 devid; | |
09ee17eb | 831 | |
7d0c5cc5 JR |
832 | for (devid = 0; devid <= 0xffff; ++devid) |
833 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 834 | |
7d0c5cc5 JR |
835 | iommu_completion_wait(iommu); |
836 | } | |
84df8175 | 837 | |
7d0c5cc5 JR |
838 | /* |
839 | * This function uses heavy locking and may disable irqs for some time. But | |
840 | * this is no issue because it is only called during resume. | |
841 | */ | |
842 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
843 | { | |
844 | u32 dom_id; | |
a19ae1ec | 845 | |
7d0c5cc5 JR |
846 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
847 | struct iommu_cmd cmd; | |
848 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
849 | dom_id, 1); | |
850 | iommu_queue_command(iommu, &cmd); | |
851 | } | |
8eed9833 | 852 | |
7d0c5cc5 | 853 | iommu_completion_wait(iommu); |
a19ae1ec JR |
854 | } |
855 | ||
58fc7f14 | 856 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 857 | { |
58fc7f14 | 858 | struct iommu_cmd cmd; |
0518a3a4 | 859 | |
58fc7f14 | 860 | build_inv_all(&cmd); |
0518a3a4 | 861 | |
58fc7f14 JR |
862 | iommu_queue_command(iommu, &cmd); |
863 | iommu_completion_wait(iommu); | |
864 | } | |
865 | ||
7d0c5cc5 JR |
866 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
867 | { | |
58fc7f14 JR |
868 | if (iommu_feature(iommu, FEATURE_IA)) { |
869 | iommu_flush_all(iommu); | |
870 | } else { | |
871 | iommu_flush_dte_all(iommu); | |
872 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
873 | } |
874 | } | |
875 | ||
431b2a20 | 876 | /* |
cb41ed85 | 877 | * Command send function for flushing on-device TLB |
431b2a20 | 878 | */ |
6c542047 JR |
879 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
880 | u64 address, size_t size) | |
3fa43655 JR |
881 | { |
882 | struct amd_iommu *iommu; | |
b00d3bcf | 883 | struct iommu_cmd cmd; |
cb41ed85 | 884 | int qdep; |
3fa43655 | 885 | |
ea61cddb JR |
886 | qdep = dev_data->ats.qdep; |
887 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 888 | |
ea61cddb | 889 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
890 | |
891 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
892 | } |
893 | ||
431b2a20 | 894 | /* |
431b2a20 | 895 | * Command send function for invalidating a device table entry |
431b2a20 | 896 | */ |
6c542047 | 897 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 898 | { |
3fa43655 | 899 | struct amd_iommu *iommu; |
ee2fa743 | 900 | int ret; |
a19ae1ec | 901 | |
6c542047 | 902 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 903 | |
f62dda66 | 904 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
905 | if (ret) |
906 | return ret; | |
907 | ||
ea61cddb | 908 | if (dev_data->ats.enabled) |
6c542047 | 909 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 910 | |
ee2fa743 | 911 | return ret; |
a19ae1ec JR |
912 | } |
913 | ||
431b2a20 JR |
914 | /* |
915 | * TLB invalidation function which is called from the mapping functions. | |
916 | * It invalidates a single PTE if the range to flush is within a single | |
917 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
918 | */ | |
17b124bf JR |
919 | static void __domain_flush_pages(struct protection_domain *domain, |
920 | u64 address, size_t size, int pde) | |
a19ae1ec | 921 | { |
cb41ed85 | 922 | struct iommu_dev_data *dev_data; |
11b6402c JR |
923 | struct iommu_cmd cmd; |
924 | int ret = 0, i; | |
a19ae1ec | 925 | |
11b6402c | 926 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 927 | |
6de8ad9b JR |
928 | for (i = 0; i < amd_iommus_present; ++i) { |
929 | if (!domain->dev_iommu[i]) | |
930 | continue; | |
931 | ||
932 | /* | |
933 | * Devices of this domain are behind this IOMMU | |
934 | * We need a TLB flush | |
935 | */ | |
11b6402c | 936 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
937 | } |
938 | ||
cb41ed85 | 939 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 940 | |
ea61cddb | 941 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
942 | continue; |
943 | ||
6c542047 | 944 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
945 | } |
946 | ||
11b6402c | 947 | WARN_ON(ret); |
6de8ad9b JR |
948 | } |
949 | ||
17b124bf JR |
950 | static void domain_flush_pages(struct protection_domain *domain, |
951 | u64 address, size_t size) | |
6de8ad9b | 952 | { |
17b124bf | 953 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 954 | } |
b6c02715 | 955 | |
1c655773 | 956 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 957 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 958 | { |
17b124bf | 959 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
960 | } |
961 | ||
42a49f96 | 962 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 963 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 964 | { |
17b124bf | 965 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
966 | } |
967 | ||
17b124bf | 968 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 969 | { |
17b124bf | 970 | int i; |
18811f55 | 971 | |
17b124bf JR |
972 | for (i = 0; i < amd_iommus_present; ++i) { |
973 | if (!domain->dev_iommu[i]) | |
974 | continue; | |
bfd1be18 | 975 | |
17b124bf JR |
976 | /* |
977 | * Devices of this domain are behind this IOMMU | |
978 | * We need to wait for completion of all commands. | |
979 | */ | |
980 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 981 | } |
e394d72a JR |
982 | } |
983 | ||
b00d3bcf | 984 | |
09b42804 | 985 | /* |
b00d3bcf | 986 | * This function flushes the DTEs for all devices in domain |
09b42804 | 987 | */ |
17b124bf | 988 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 989 | { |
b00d3bcf | 990 | struct iommu_dev_data *dev_data; |
b26e81b8 | 991 | |
b00d3bcf | 992 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 993 | device_flush_dte(dev_data); |
a345b23b JR |
994 | } |
995 | ||
431b2a20 JR |
996 | /**************************************************************************** |
997 | * | |
998 | * The functions below are used the create the page table mappings for | |
999 | * unity mapped regions. | |
1000 | * | |
1001 | ****************************************************************************/ | |
1002 | ||
308973d3 JR |
1003 | /* |
1004 | * This function is used to add another level to an IO page table. Adding | |
1005 | * another level increases the size of the address space by 9 bits to a size up | |
1006 | * to 64 bits. | |
1007 | */ | |
1008 | static bool increase_address_space(struct protection_domain *domain, | |
1009 | gfp_t gfp) | |
1010 | { | |
1011 | u64 *pte; | |
1012 | ||
1013 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1014 | /* address space already 64 bit large */ | |
1015 | return false; | |
1016 | ||
1017 | pte = (void *)get_zeroed_page(gfp); | |
1018 | if (!pte) | |
1019 | return false; | |
1020 | ||
1021 | *pte = PM_LEVEL_PDE(domain->mode, | |
1022 | virt_to_phys(domain->pt_root)); | |
1023 | domain->pt_root = pte; | |
1024 | domain->mode += 1; | |
1025 | domain->updated = true; | |
1026 | ||
1027 | return true; | |
1028 | } | |
1029 | ||
1030 | static u64 *alloc_pte(struct protection_domain *domain, | |
1031 | unsigned long address, | |
cbb9d729 | 1032 | unsigned long page_size, |
308973d3 JR |
1033 | u64 **pte_page, |
1034 | gfp_t gfp) | |
1035 | { | |
cbb9d729 | 1036 | int level, end_lvl; |
308973d3 | 1037 | u64 *pte, *page; |
cbb9d729 JR |
1038 | |
1039 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1040 | |
1041 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1042 | increase_address_space(domain, gfp); | |
1043 | ||
cbb9d729 JR |
1044 | level = domain->mode - 1; |
1045 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1046 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1047 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1048 | |
1049 | while (level > end_lvl) { | |
1050 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1051 | page = (u64 *)get_zeroed_page(gfp); | |
1052 | if (!page) | |
1053 | return NULL; | |
1054 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1055 | } | |
1056 | ||
cbb9d729 JR |
1057 | /* No level skipping support yet */ |
1058 | if (PM_PTE_LEVEL(*pte) != level) | |
1059 | return NULL; | |
1060 | ||
308973d3 JR |
1061 | level -= 1; |
1062 | ||
1063 | pte = IOMMU_PTE_PAGE(*pte); | |
1064 | ||
1065 | if (pte_page && level == end_lvl) | |
1066 | *pte_page = pte; | |
1067 | ||
1068 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1069 | } | |
1070 | ||
1071 | return pte; | |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * This function checks if there is a PTE for a given dma address. If | |
1076 | * there is one, it returns the pointer to it. | |
1077 | */ | |
24cd7723 | 1078 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1079 | { |
1080 | int level; | |
1081 | u64 *pte; | |
1082 | ||
24cd7723 JR |
1083 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1084 | return NULL; | |
1085 | ||
1086 | level = domain->mode - 1; | |
1087 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1088 | |
24cd7723 JR |
1089 | while (level > 0) { |
1090 | ||
1091 | /* Not Present */ | |
308973d3 JR |
1092 | if (!IOMMU_PTE_PRESENT(*pte)) |
1093 | return NULL; | |
1094 | ||
24cd7723 JR |
1095 | /* Large PTE */ |
1096 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1097 | unsigned long pte_mask, __pte; | |
1098 | ||
1099 | /* | |
1100 | * If we have a series of large PTEs, make | |
1101 | * sure to return a pointer to the first one. | |
1102 | */ | |
1103 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1104 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1105 | __pte = ((unsigned long)pte) & pte_mask; | |
1106 | ||
1107 | return (u64 *)__pte; | |
1108 | } | |
1109 | ||
1110 | /* No level skipping support yet */ | |
1111 | if (PM_PTE_LEVEL(*pte) != level) | |
1112 | return NULL; | |
1113 | ||
308973d3 JR |
1114 | level -= 1; |
1115 | ||
24cd7723 | 1116 | /* Walk to the next level */ |
308973d3 JR |
1117 | pte = IOMMU_PTE_PAGE(*pte); |
1118 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1119 | } |
1120 | ||
1121 | return pte; | |
1122 | } | |
1123 | ||
431b2a20 JR |
1124 | /* |
1125 | * Generic mapping functions. It maps a physical address into a DMA | |
1126 | * address space. It allocates the page table pages if necessary. | |
1127 | * In the future it can be extended to a generic mapping function | |
1128 | * supporting all features of AMD IOMMU page tables like level skipping | |
1129 | * and full 64 bit address spaces. | |
1130 | */ | |
38e817fe JR |
1131 | static int iommu_map_page(struct protection_domain *dom, |
1132 | unsigned long bus_addr, | |
1133 | unsigned long phys_addr, | |
abdc5eb3 | 1134 | int prot, |
cbb9d729 | 1135 | unsigned long page_size) |
bd0e5211 | 1136 | { |
8bda3092 | 1137 | u64 __pte, *pte; |
cbb9d729 | 1138 | int i, count; |
abdc5eb3 | 1139 | |
bad1cac2 | 1140 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1141 | return -EINVAL; |
1142 | ||
cbb9d729 JR |
1143 | bus_addr = PAGE_ALIGN(bus_addr); |
1144 | phys_addr = PAGE_ALIGN(phys_addr); | |
1145 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1146 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1147 | ||
1148 | for (i = 0; i < count; ++i) | |
1149 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1150 | return -EBUSY; | |
bd0e5211 | 1151 | |
cbb9d729 JR |
1152 | if (page_size > PAGE_SIZE) { |
1153 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1154 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1155 | } else | |
1156 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1157 | |
bd0e5211 JR |
1158 | if (prot & IOMMU_PROT_IR) |
1159 | __pte |= IOMMU_PTE_IR; | |
1160 | if (prot & IOMMU_PROT_IW) | |
1161 | __pte |= IOMMU_PTE_IW; | |
1162 | ||
cbb9d729 JR |
1163 | for (i = 0; i < count; ++i) |
1164 | pte[i] = __pte; | |
bd0e5211 | 1165 | |
04bfdd84 JR |
1166 | update_domain(dom); |
1167 | ||
bd0e5211 JR |
1168 | return 0; |
1169 | } | |
1170 | ||
24cd7723 JR |
1171 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1172 | unsigned long bus_addr, | |
1173 | unsigned long page_size) | |
eb74ff6c | 1174 | { |
24cd7723 JR |
1175 | unsigned long long unmap_size, unmapped; |
1176 | u64 *pte; | |
1177 | ||
1178 | BUG_ON(!is_power_of_2(page_size)); | |
1179 | ||
1180 | unmapped = 0; | |
eb74ff6c | 1181 | |
24cd7723 JR |
1182 | while (unmapped < page_size) { |
1183 | ||
1184 | pte = fetch_pte(dom, bus_addr); | |
1185 | ||
1186 | if (!pte) { | |
1187 | /* | |
1188 | * No PTE for this address | |
1189 | * move forward in 4kb steps | |
1190 | */ | |
1191 | unmap_size = PAGE_SIZE; | |
1192 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1193 | /* 4kb PTE found for this address */ | |
1194 | unmap_size = PAGE_SIZE; | |
1195 | *pte = 0ULL; | |
1196 | } else { | |
1197 | int count, i; | |
1198 | ||
1199 | /* Large PTE found which maps this address */ | |
1200 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1201 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1202 | for (i = 0; i < count; i++) | |
1203 | pte[i] = 0ULL; | |
1204 | } | |
1205 | ||
1206 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1207 | unmapped += unmap_size; | |
1208 | } | |
1209 | ||
1210 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1211 | |
24cd7723 | 1212 | return unmapped; |
eb74ff6c | 1213 | } |
eb74ff6c | 1214 | |
431b2a20 JR |
1215 | /* |
1216 | * This function checks if a specific unity mapping entry is needed for | |
1217 | * this specific IOMMU. | |
1218 | */ | |
bd0e5211 JR |
1219 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1220 | struct unity_map_entry *entry) | |
1221 | { | |
1222 | u16 bdf, i; | |
1223 | ||
1224 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1225 | bdf = amd_iommu_alias_table[i]; | |
1226 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1227 | return 1; | |
1228 | } | |
1229 | ||
1230 | return 0; | |
1231 | } | |
1232 | ||
431b2a20 JR |
1233 | /* |
1234 | * This function actually applies the mapping to the page table of the | |
1235 | * dma_ops domain. | |
1236 | */ | |
bd0e5211 JR |
1237 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1238 | struct unity_map_entry *e) | |
1239 | { | |
1240 | u64 addr; | |
1241 | int ret; | |
1242 | ||
1243 | for (addr = e->address_start; addr < e->address_end; | |
1244 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1245 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1246 | PAGE_SIZE); |
bd0e5211 JR |
1247 | if (ret) |
1248 | return ret; | |
1249 | /* | |
1250 | * if unity mapping is in aperture range mark the page | |
1251 | * as allocated in the aperture | |
1252 | */ | |
1253 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1254 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1255 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1256 | } |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
171e7b37 JR |
1261 | /* |
1262 | * Init the unity mappings for a specific IOMMU in the system | |
1263 | * | |
1264 | * Basically iterates over all unity mapping entries and applies them to | |
1265 | * the default domain DMA of that IOMMU if necessary. | |
1266 | */ | |
1267 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1268 | { | |
1269 | struct unity_map_entry *entry; | |
1270 | int ret; | |
1271 | ||
1272 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1273 | if (!iommu_for_unity_map(iommu, entry)) | |
1274 | continue; | |
1275 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1276 | if (ret) | |
1277 | return ret; | |
1278 | } | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
431b2a20 JR |
1283 | /* |
1284 | * Inits the unity mappings required for a specific device | |
1285 | */ | |
bd0e5211 JR |
1286 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1287 | u16 devid) | |
1288 | { | |
1289 | struct unity_map_entry *e; | |
1290 | int ret; | |
1291 | ||
1292 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1293 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1294 | continue; | |
1295 | ret = dma_ops_unity_map(dma_dom, e); | |
1296 | if (ret) | |
1297 | return ret; | |
1298 | } | |
1299 | ||
1300 | return 0; | |
1301 | } | |
1302 | ||
431b2a20 JR |
1303 | /**************************************************************************** |
1304 | * | |
1305 | * The next functions belong to the address allocator for the dma_ops | |
1306 | * interface functions. They work like the allocators in the other IOMMU | |
1307 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1308 | * the aperture. Maybe it could be enhanced in the future to a more | |
1309 | * efficient allocator. | |
1310 | * | |
1311 | ****************************************************************************/ | |
d3086444 | 1312 | |
431b2a20 | 1313 | /* |
384de729 | 1314 | * The address allocator core functions. |
431b2a20 JR |
1315 | * |
1316 | * called with domain->lock held | |
1317 | */ | |
384de729 | 1318 | |
171e7b37 JR |
1319 | /* |
1320 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1321 | * ranges. | |
1322 | */ | |
1323 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1324 | unsigned long start_page, | |
1325 | unsigned int pages) | |
1326 | { | |
1327 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1328 | ||
1329 | if (start_page + pages > last_page) | |
1330 | pages = last_page - start_page; | |
1331 | ||
1332 | for (i = start_page; i < start_page + pages; ++i) { | |
1333 | int index = i / APERTURE_RANGE_PAGES; | |
1334 | int page = i % APERTURE_RANGE_PAGES; | |
1335 | __set_bit(page, dom->aperture[index]->bitmap); | |
1336 | } | |
1337 | } | |
1338 | ||
9cabe89b JR |
1339 | /* |
1340 | * This function is used to add a new aperture range to an existing | |
1341 | * aperture in case of dma_ops domain allocation or address allocation | |
1342 | * failure. | |
1343 | */ | |
576175c2 | 1344 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1345 | bool populate, gfp_t gfp) |
1346 | { | |
1347 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1348 | struct amd_iommu *iommu; |
17f5b569 | 1349 | unsigned long i, old_size; |
9cabe89b | 1350 | |
f5e9705c JR |
1351 | #ifdef CONFIG_IOMMU_STRESS |
1352 | populate = false; | |
1353 | #endif | |
1354 | ||
9cabe89b JR |
1355 | if (index >= APERTURE_MAX_RANGES) |
1356 | return -ENOMEM; | |
1357 | ||
1358 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1359 | if (!dma_dom->aperture[index]) | |
1360 | return -ENOMEM; | |
1361 | ||
1362 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1363 | if (!dma_dom->aperture[index]->bitmap) | |
1364 | goto out_free; | |
1365 | ||
1366 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1367 | ||
1368 | if (populate) { | |
1369 | unsigned long address = dma_dom->aperture_size; | |
1370 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1371 | u64 *pte, *pte_page; | |
1372 | ||
1373 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1374 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1375 | &pte_page, gfp); |
1376 | if (!pte) | |
1377 | goto out_free; | |
1378 | ||
1379 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1380 | ||
1381 | address += APERTURE_RANGE_SIZE / 64; | |
1382 | } | |
1383 | } | |
1384 | ||
17f5b569 | 1385 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1386 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1387 | ||
17f5b569 JR |
1388 | /* Reserve address range used for MSI messages */ |
1389 | if (old_size < MSI_ADDR_BASE_LO && | |
1390 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1391 | unsigned long spage; | |
1392 | int pages; | |
1393 | ||
1394 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1395 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1396 | ||
1397 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1398 | } | |
1399 | ||
b595076a | 1400 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1401 | for_each_iommu(iommu) { |
1402 | if (iommu->exclusion_start && | |
1403 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1404 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1405 | unsigned long startpage; | |
1406 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1407 | iommu->exclusion_length, | |
1408 | PAGE_SIZE); | |
1409 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1410 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1411 | } | |
00cd122a JR |
1412 | } |
1413 | ||
1414 | /* | |
1415 | * Check for areas already mapped as present in the new aperture | |
1416 | * range and mark those pages as reserved in the allocator. Such | |
1417 | * mappings may already exist as a result of requested unity | |
1418 | * mappings for devices. | |
1419 | */ | |
1420 | for (i = dma_dom->aperture[index]->offset; | |
1421 | i < dma_dom->aperture_size; | |
1422 | i += PAGE_SIZE) { | |
24cd7723 | 1423 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1424 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1425 | continue; | |
1426 | ||
fcd0861d | 1427 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1428 | } |
1429 | ||
04bfdd84 JR |
1430 | update_domain(&dma_dom->domain); |
1431 | ||
9cabe89b JR |
1432 | return 0; |
1433 | ||
1434 | out_free: | |
04bfdd84 JR |
1435 | update_domain(&dma_dom->domain); |
1436 | ||
9cabe89b JR |
1437 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1438 | ||
1439 | kfree(dma_dom->aperture[index]); | |
1440 | dma_dom->aperture[index] = NULL; | |
1441 | ||
1442 | return -ENOMEM; | |
1443 | } | |
1444 | ||
384de729 JR |
1445 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1446 | struct dma_ops_domain *dom, | |
1447 | unsigned int pages, | |
1448 | unsigned long align_mask, | |
1449 | u64 dma_mask, | |
1450 | unsigned long start) | |
1451 | { | |
803b8cb4 | 1452 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1453 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1454 | int i = start >> APERTURE_RANGE_SHIFT; | |
1455 | unsigned long boundary_size; | |
1456 | unsigned long address = -1; | |
1457 | unsigned long limit; | |
1458 | ||
803b8cb4 JR |
1459 | next_bit >>= PAGE_SHIFT; |
1460 | ||
384de729 JR |
1461 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1462 | PAGE_SIZE) >> PAGE_SHIFT; | |
1463 | ||
1464 | for (;i < max_index; ++i) { | |
1465 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1466 | ||
1467 | if (dom->aperture[i]->offset >= dma_mask) | |
1468 | break; | |
1469 | ||
1470 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1471 | dma_mask >> PAGE_SHIFT); | |
1472 | ||
1473 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1474 | limit, next_bit, pages, 0, | |
1475 | boundary_size, align_mask); | |
1476 | if (address != -1) { | |
1477 | address = dom->aperture[i]->offset + | |
1478 | (address << PAGE_SHIFT); | |
803b8cb4 | 1479 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1480 | break; |
1481 | } | |
1482 | ||
1483 | next_bit = 0; | |
1484 | } | |
1485 | ||
1486 | return address; | |
1487 | } | |
1488 | ||
d3086444 JR |
1489 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1490 | struct dma_ops_domain *dom, | |
6d4f343f | 1491 | unsigned int pages, |
832a90c3 JR |
1492 | unsigned long align_mask, |
1493 | u64 dma_mask) | |
d3086444 | 1494 | { |
d3086444 | 1495 | unsigned long address; |
d3086444 | 1496 | |
fe16f088 JR |
1497 | #ifdef CONFIG_IOMMU_STRESS |
1498 | dom->next_address = 0; | |
1499 | dom->need_flush = true; | |
1500 | #endif | |
d3086444 | 1501 | |
384de729 | 1502 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1503 | dma_mask, dom->next_address); |
d3086444 | 1504 | |
1c655773 | 1505 | if (address == -1) { |
803b8cb4 | 1506 | dom->next_address = 0; |
384de729 JR |
1507 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1508 | dma_mask, 0); | |
1c655773 JR |
1509 | dom->need_flush = true; |
1510 | } | |
d3086444 | 1511 | |
384de729 | 1512 | if (unlikely(address == -1)) |
8fd524b3 | 1513 | address = DMA_ERROR_CODE; |
d3086444 JR |
1514 | |
1515 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1516 | ||
1517 | return address; | |
1518 | } | |
1519 | ||
431b2a20 JR |
1520 | /* |
1521 | * The address free function. | |
1522 | * | |
1523 | * called with domain->lock held | |
1524 | */ | |
d3086444 JR |
1525 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1526 | unsigned long address, | |
1527 | unsigned int pages) | |
1528 | { | |
384de729 JR |
1529 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1530 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1531 | |
384de729 JR |
1532 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1533 | ||
47bccd6b JR |
1534 | #ifdef CONFIG_IOMMU_STRESS |
1535 | if (i < 4) | |
1536 | return; | |
1537 | #endif | |
80be308d | 1538 | |
803b8cb4 | 1539 | if (address >= dom->next_address) |
80be308d | 1540 | dom->need_flush = true; |
384de729 JR |
1541 | |
1542 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1543 | |
a66022c4 | 1544 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1545 | |
d3086444 JR |
1546 | } |
1547 | ||
431b2a20 JR |
1548 | /**************************************************************************** |
1549 | * | |
1550 | * The next functions belong to the domain allocation. A domain is | |
1551 | * allocated for every IOMMU as the default domain. If device isolation | |
1552 | * is enabled, every device get its own domain. The most important thing | |
1553 | * about domains is the page table mapping the DMA address space they | |
1554 | * contain. | |
1555 | * | |
1556 | ****************************************************************************/ | |
1557 | ||
aeb26f55 JR |
1558 | /* |
1559 | * This function adds a protection domain to the global protection domain list | |
1560 | */ | |
1561 | static void add_domain_to_list(struct protection_domain *domain) | |
1562 | { | |
1563 | unsigned long flags; | |
1564 | ||
1565 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1566 | list_add(&domain->list, &amd_iommu_pd_list); | |
1567 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1568 | } | |
1569 | ||
1570 | /* | |
1571 | * This function removes a protection domain to the global | |
1572 | * protection domain list | |
1573 | */ | |
1574 | static void del_domain_from_list(struct protection_domain *domain) | |
1575 | { | |
1576 | unsigned long flags; | |
1577 | ||
1578 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1579 | list_del(&domain->list); | |
1580 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1581 | } | |
1582 | ||
ec487d1a JR |
1583 | static u16 domain_id_alloc(void) |
1584 | { | |
1585 | unsigned long flags; | |
1586 | int id; | |
1587 | ||
1588 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1589 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1590 | BUG_ON(id == 0); | |
1591 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1592 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1593 | else | |
1594 | id = 0; | |
1595 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1596 | ||
1597 | return id; | |
1598 | } | |
1599 | ||
a2acfb75 JR |
1600 | static void domain_id_free(int id) |
1601 | { | |
1602 | unsigned long flags; | |
1603 | ||
1604 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1605 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1606 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1607 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1608 | } | |
a2acfb75 | 1609 | |
86db2e5d | 1610 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1611 | { |
1612 | int i, j; | |
1613 | u64 *p1, *p2, *p3; | |
1614 | ||
86db2e5d | 1615 | p1 = domain->pt_root; |
ec487d1a JR |
1616 | |
1617 | if (!p1) | |
1618 | return; | |
1619 | ||
1620 | for (i = 0; i < 512; ++i) { | |
1621 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1622 | continue; | |
1623 | ||
1624 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1625 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1626 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1627 | continue; | |
1628 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1629 | free_page((unsigned long)p3); | |
1630 | } | |
1631 | ||
1632 | free_page((unsigned long)p2); | |
1633 | } | |
1634 | ||
1635 | free_page((unsigned long)p1); | |
86db2e5d JR |
1636 | |
1637 | domain->pt_root = NULL; | |
ec487d1a JR |
1638 | } |
1639 | ||
b16137b1 JR |
1640 | static void free_gcr3_tbl_level1(u64 *tbl) |
1641 | { | |
1642 | u64 *ptr; | |
1643 | int i; | |
1644 | ||
1645 | for (i = 0; i < 512; ++i) { | |
1646 | if (!(tbl[i] & GCR3_VALID)) | |
1647 | continue; | |
1648 | ||
1649 | ptr = __va(tbl[i] & PAGE_MASK); | |
1650 | ||
1651 | free_page((unsigned long)ptr); | |
1652 | } | |
1653 | } | |
1654 | ||
1655 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1656 | { | |
1657 | u64 *ptr; | |
1658 | int i; | |
1659 | ||
1660 | for (i = 0; i < 512; ++i) { | |
1661 | if (!(tbl[i] & GCR3_VALID)) | |
1662 | continue; | |
1663 | ||
1664 | ptr = __va(tbl[i] & PAGE_MASK); | |
1665 | ||
1666 | free_gcr3_tbl_level1(ptr); | |
1667 | } | |
1668 | } | |
1669 | ||
52815b75 JR |
1670 | static void free_gcr3_table(struct protection_domain *domain) |
1671 | { | |
b16137b1 JR |
1672 | if (domain->glx == 2) |
1673 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1674 | else if (domain->glx == 1) | |
1675 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1676 | else if (domain->glx != 0) | |
1677 | BUG(); | |
1678 | ||
52815b75 JR |
1679 | free_page((unsigned long)domain->gcr3_tbl); |
1680 | } | |
1681 | ||
431b2a20 JR |
1682 | /* |
1683 | * Free a domain, only used if something went wrong in the | |
1684 | * allocation path and we need to free an already allocated page table | |
1685 | */ | |
ec487d1a JR |
1686 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1687 | { | |
384de729 JR |
1688 | int i; |
1689 | ||
ec487d1a JR |
1690 | if (!dom) |
1691 | return; | |
1692 | ||
aeb26f55 JR |
1693 | del_domain_from_list(&dom->domain); |
1694 | ||
86db2e5d | 1695 | free_pagetable(&dom->domain); |
ec487d1a | 1696 | |
384de729 JR |
1697 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1698 | if (!dom->aperture[i]) | |
1699 | continue; | |
1700 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1701 | kfree(dom->aperture[i]); | |
1702 | } | |
ec487d1a JR |
1703 | |
1704 | kfree(dom); | |
1705 | } | |
1706 | ||
431b2a20 JR |
1707 | /* |
1708 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1709 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1710 | * structures required for the dma_ops interface |
1711 | */ | |
87a64d52 | 1712 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1713 | { |
1714 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1715 | |
1716 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1717 | if (!dma_dom) | |
1718 | return NULL; | |
1719 | ||
1720 | spin_lock_init(&dma_dom->domain.lock); | |
1721 | ||
1722 | dma_dom->domain.id = domain_id_alloc(); | |
1723 | if (dma_dom->domain.id == 0) | |
1724 | goto free_dma_dom; | |
7c392cbe | 1725 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1726 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1727 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1728 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1729 | dma_dom->domain.priv = dma_dom; |
1730 | if (!dma_dom->domain.pt_root) | |
1731 | goto free_dma_dom; | |
ec487d1a | 1732 | |
1c655773 | 1733 | dma_dom->need_flush = false; |
bd60b735 | 1734 | dma_dom->target_dev = 0xffff; |
1c655773 | 1735 | |
aeb26f55 JR |
1736 | add_domain_to_list(&dma_dom->domain); |
1737 | ||
576175c2 | 1738 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1739 | goto free_dma_dom; |
ec487d1a | 1740 | |
431b2a20 | 1741 | /* |
ec487d1a JR |
1742 | * mark the first page as allocated so we never return 0 as |
1743 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1744 | */ |
384de729 | 1745 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1746 | dma_dom->next_address = 0; |
ec487d1a | 1747 | |
ec487d1a JR |
1748 | |
1749 | return dma_dom; | |
1750 | ||
1751 | free_dma_dom: | |
1752 | dma_ops_domain_free(dma_dom); | |
1753 | ||
1754 | return NULL; | |
1755 | } | |
1756 | ||
5b28df6f JR |
1757 | /* |
1758 | * little helper function to check whether a given protection domain is a | |
1759 | * dma_ops domain | |
1760 | */ | |
1761 | static bool dma_ops_domain(struct protection_domain *domain) | |
1762 | { | |
1763 | return domain->flags & PD_DMA_OPS_MASK; | |
1764 | } | |
1765 | ||
fd7b5535 | 1766 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1767 | { |
132bd68f | 1768 | u64 pte_root = 0; |
ee6c2868 | 1769 | u64 flags = 0; |
863c74eb | 1770 | |
132bd68f JR |
1771 | if (domain->mode != PAGE_MODE_NONE) |
1772 | pte_root = virt_to_phys(domain->pt_root); | |
1773 | ||
38ddf41b JR |
1774 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1775 | << DEV_ENTRY_MODE_SHIFT; | |
1776 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1777 | |
ee6c2868 JR |
1778 | flags = amd_iommu_dev_table[devid].data[1]; |
1779 | ||
fd7b5535 JR |
1780 | if (ats) |
1781 | flags |= DTE_FLAG_IOTLB; | |
1782 | ||
52815b75 JR |
1783 | if (domain->flags & PD_IOMMUV2_MASK) { |
1784 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1785 | u64 glx = domain->glx; | |
1786 | u64 tmp; | |
1787 | ||
1788 | pte_root |= DTE_FLAG_GV; | |
1789 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1790 | ||
1791 | /* First mask out possible old values for GCR3 table */ | |
1792 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1793 | flags &= ~tmp; | |
1794 | ||
1795 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1796 | flags &= ~tmp; | |
1797 | ||
1798 | /* Encode GCR3 table into DTE */ | |
1799 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1800 | pte_root |= tmp; | |
1801 | ||
1802 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1803 | flags |= tmp; | |
1804 | ||
1805 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1806 | flags |= tmp; | |
1807 | } | |
1808 | ||
ee6c2868 JR |
1809 | flags &= ~(0xffffUL); |
1810 | flags |= domain->id; | |
1811 | ||
1812 | amd_iommu_dev_table[devid].data[1] = flags; | |
1813 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1814 | } |
1815 | ||
1816 | static void clear_dte_entry(u16 devid) | |
1817 | { | |
15898bbc JR |
1818 | /* remove entry from the device table seen by the hardware */ |
1819 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1820 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
1821 | |
1822 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1823 | } |
1824 | ||
ec9e79ef JR |
1825 | static void do_attach(struct iommu_dev_data *dev_data, |
1826 | struct protection_domain *domain) | |
7f760ddd | 1827 | { |
7f760ddd | 1828 | struct amd_iommu *iommu; |
ec9e79ef | 1829 | bool ats; |
fd7b5535 | 1830 | |
ec9e79ef JR |
1831 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1832 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1833 | |
1834 | /* Update data structures */ | |
1835 | dev_data->domain = domain; | |
1836 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1837 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1838 | |
1839 | /* Do reference counting */ | |
1840 | domain->dev_iommu[iommu->index] += 1; | |
1841 | domain->dev_cnt += 1; | |
1842 | ||
1843 | /* Flush the DTE entry */ | |
6c542047 | 1844 | device_flush_dte(dev_data); |
7f760ddd JR |
1845 | } |
1846 | ||
ec9e79ef | 1847 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1848 | { |
7f760ddd | 1849 | struct amd_iommu *iommu; |
7f760ddd | 1850 | |
ec9e79ef | 1851 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
1852 | |
1853 | /* decrease reference counters */ | |
7f760ddd JR |
1854 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1855 | dev_data->domain->dev_cnt -= 1; | |
1856 | ||
1857 | /* Update data structures */ | |
1858 | dev_data->domain = NULL; | |
1859 | list_del(&dev_data->list); | |
f62dda66 | 1860 | clear_dte_entry(dev_data->devid); |
15898bbc | 1861 | |
7f760ddd | 1862 | /* Flush the DTE entry */ |
6c542047 | 1863 | device_flush_dte(dev_data); |
2b681faf JR |
1864 | } |
1865 | ||
1866 | /* | |
1867 | * If a device is not yet associated with a domain, this function does | |
1868 | * assigns it visible for the hardware | |
1869 | */ | |
ec9e79ef | 1870 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1871 | struct protection_domain *domain) |
2b681faf | 1872 | { |
84fe6c19 | 1873 | int ret; |
657cbb6b | 1874 | |
2b681faf JR |
1875 | /* lock domain */ |
1876 | spin_lock(&domain->lock); | |
1877 | ||
71f77580 JR |
1878 | if (dev_data->alias_data != NULL) { |
1879 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 1880 | |
2b02b091 JR |
1881 | /* Some sanity checks */ |
1882 | ret = -EBUSY; | |
1883 | if (alias_data->domain != NULL && | |
1884 | alias_data->domain != domain) | |
1885 | goto out_unlock; | |
eba6ac60 | 1886 | |
2b02b091 JR |
1887 | if (dev_data->domain != NULL && |
1888 | dev_data->domain != domain) | |
1889 | goto out_unlock; | |
15898bbc | 1890 | |
2b02b091 | 1891 | /* Do real assignment */ |
7f760ddd | 1892 | if (alias_data->domain == NULL) |
ec9e79ef | 1893 | do_attach(alias_data, domain); |
24100055 JR |
1894 | |
1895 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1896 | } |
15898bbc | 1897 | |
7f760ddd | 1898 | if (dev_data->domain == NULL) |
ec9e79ef | 1899 | do_attach(dev_data, domain); |
eba6ac60 | 1900 | |
24100055 JR |
1901 | atomic_inc(&dev_data->bind); |
1902 | ||
84fe6c19 JL |
1903 | ret = 0; |
1904 | ||
1905 | out_unlock: | |
1906 | ||
eba6ac60 JR |
1907 | /* ready */ |
1908 | spin_unlock(&domain->lock); | |
15898bbc | 1909 | |
84fe6c19 | 1910 | return ret; |
0feae533 | 1911 | } |
b20ac0d4 | 1912 | |
52815b75 JR |
1913 | |
1914 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
1915 | { | |
1916 | pci_disable_ats(pdev); | |
1917 | pci_disable_pri(pdev); | |
1918 | pci_disable_pasid(pdev); | |
1919 | } | |
1920 | ||
1921 | static int pdev_iommuv2_enable(struct pci_dev *pdev) | |
1922 | { | |
1923 | int ret; | |
1924 | ||
1925 | /* Only allow access to user-accessible pages */ | |
1926 | ret = pci_enable_pasid(pdev, 0); | |
1927 | if (ret) | |
1928 | goto out_err; | |
1929 | ||
1930 | /* First reset the PRI state of the device */ | |
1931 | ret = pci_reset_pri(pdev); | |
1932 | if (ret) | |
1933 | goto out_err; | |
1934 | ||
1935 | /* FIXME: Hardcode number of outstanding requests for now */ | |
1936 | ret = pci_enable_pri(pdev, 32); | |
1937 | if (ret) | |
1938 | goto out_err; | |
1939 | ||
1940 | ret = pci_enable_ats(pdev, PAGE_SHIFT); | |
1941 | if (ret) | |
1942 | goto out_err; | |
1943 | ||
1944 | return 0; | |
1945 | ||
1946 | out_err: | |
1947 | pci_disable_pri(pdev); | |
1948 | pci_disable_pasid(pdev); | |
1949 | ||
1950 | return ret; | |
1951 | } | |
1952 | ||
407d733e JR |
1953 | /* |
1954 | * If a device is not yet associated with a domain, this function does | |
1955 | * assigns it visible for the hardware | |
1956 | */ | |
15898bbc JR |
1957 | static int attach_device(struct device *dev, |
1958 | struct protection_domain *domain) | |
0feae533 | 1959 | { |
fd7b5535 | 1960 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 1961 | struct iommu_dev_data *dev_data; |
eba6ac60 | 1962 | unsigned long flags; |
15898bbc | 1963 | int ret; |
eba6ac60 | 1964 | |
ea61cddb JR |
1965 | dev_data = get_dev_data(dev); |
1966 | ||
52815b75 JR |
1967 | if (domain->flags & PD_IOMMUV2_MASK) { |
1968 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
1969 | return -EINVAL; | |
1970 | ||
1971 | if (pdev_iommuv2_enable(pdev) != 0) | |
1972 | return -EINVAL; | |
1973 | ||
1974 | dev_data->ats.enabled = true; | |
1975 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
1976 | } else if (amd_iommu_iotlb_sup && | |
1977 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
1978 | dev_data->ats.enabled = true; |
1979 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
1980 | } | |
fd7b5535 | 1981 | |
eba6ac60 | 1982 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 1983 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
1984 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1985 | ||
0feae533 JR |
1986 | /* |
1987 | * We might boot into a crash-kernel here. The crashed kernel | |
1988 | * left the caches in the IOMMU dirty. So we have to flush | |
1989 | * here to evict all dirty stuff. | |
1990 | */ | |
17b124bf | 1991 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1992 | |
1993 | return ret; | |
b20ac0d4 JR |
1994 | } |
1995 | ||
355bf553 JR |
1996 | /* |
1997 | * Removes a device from a protection domain (unlocked) | |
1998 | */ | |
ec9e79ef | 1999 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2000 | { |
2ca76279 | 2001 | struct protection_domain *domain; |
7c392cbe | 2002 | unsigned long flags; |
c4596114 | 2003 | |
7f760ddd | 2004 | BUG_ON(!dev_data->domain); |
355bf553 | 2005 | |
2ca76279 JR |
2006 | domain = dev_data->domain; |
2007 | ||
2008 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2009 | |
71f77580 JR |
2010 | if (dev_data->alias_data != NULL) { |
2011 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2012 | ||
7f760ddd | 2013 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2014 | do_detach(alias_data); |
24100055 JR |
2015 | } |
2016 | ||
7f760ddd | 2017 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2018 | do_detach(dev_data); |
7f760ddd | 2019 | |
2ca76279 | 2020 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2021 | |
2022 | /* | |
2023 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2024 | * passthrough domain if it is detached from any other domain. |
2025 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2026 | */ |
5abcdba4 | 2027 | if (dev_data->passthrough && |
d3ad9373 | 2028 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2029 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2030 | } |
2031 | ||
2032 | /* | |
2033 | * Removes a device from a protection domain (with devtable_lock held) | |
2034 | */ | |
15898bbc | 2035 | static void detach_device(struct device *dev) |
355bf553 | 2036 | { |
52815b75 | 2037 | struct protection_domain *domain; |
ea61cddb | 2038 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2039 | unsigned long flags; |
2040 | ||
ec9e79ef | 2041 | dev_data = get_dev_data(dev); |
52815b75 | 2042 | domain = dev_data->domain; |
ec9e79ef | 2043 | |
355bf553 JR |
2044 | /* lock device table */ |
2045 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2046 | __detach_device(dev_data); |
355bf553 | 2047 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2048 | |
52815b75 JR |
2049 | if (domain->flags & PD_IOMMUV2_MASK) |
2050 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2051 | else if (dev_data->ats.enabled) | |
ea61cddb | 2052 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2053 | |
2054 | dev_data->ats.enabled = false; | |
355bf553 | 2055 | } |
e275a2a0 | 2056 | |
15898bbc JR |
2057 | /* |
2058 | * Find out the protection domain structure for a given PCI device. This | |
2059 | * will give us the pointer to the page table root for example. | |
2060 | */ | |
2061 | static struct protection_domain *domain_for_device(struct device *dev) | |
2062 | { | |
71f77580 | 2063 | struct iommu_dev_data *dev_data; |
2b02b091 | 2064 | struct protection_domain *dom = NULL; |
15898bbc | 2065 | unsigned long flags; |
15898bbc | 2066 | |
657cbb6b | 2067 | dev_data = get_dev_data(dev); |
15898bbc | 2068 | |
2b02b091 JR |
2069 | if (dev_data->domain) |
2070 | return dev_data->domain; | |
15898bbc | 2071 | |
71f77580 JR |
2072 | if (dev_data->alias_data != NULL) { |
2073 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2074 | |
2075 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2076 | if (alias_data->domain != NULL) { | |
2077 | __attach_device(dev_data, alias_data->domain); | |
2078 | dom = alias_data->domain; | |
2079 | } | |
2080 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2081 | } | |
15898bbc JR |
2082 | |
2083 | return dom; | |
2084 | } | |
2085 | ||
e275a2a0 JR |
2086 | static int device_change_notifier(struct notifier_block *nb, |
2087 | unsigned long action, void *data) | |
2088 | { | |
e275a2a0 | 2089 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2090 | struct protection_domain *domain; |
2091 | struct iommu_dev_data *dev_data; | |
2092 | struct device *dev = data; | |
e275a2a0 | 2093 | struct amd_iommu *iommu; |
1ac4cbbc | 2094 | unsigned long flags; |
5abcdba4 | 2095 | u16 devid; |
e275a2a0 | 2096 | |
98fc5a69 JR |
2097 | if (!check_device(dev)) |
2098 | return 0; | |
e275a2a0 | 2099 | |
5abcdba4 JR |
2100 | devid = get_device_id(dev); |
2101 | iommu = amd_iommu_rlookup_table[devid]; | |
2102 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2103 | |
2104 | switch (action) { | |
c1eee67b | 2105 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2106 | |
2107 | domain = domain_for_device(dev); | |
2108 | ||
e275a2a0 JR |
2109 | if (!domain) |
2110 | goto out; | |
5abcdba4 | 2111 | if (dev_data->passthrough) |
a1ca331c | 2112 | break; |
15898bbc | 2113 | detach_device(dev); |
1ac4cbbc JR |
2114 | break; |
2115 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2116 | |
2117 | iommu_init_device(dev); | |
2118 | ||
2119 | domain = domain_for_device(dev); | |
2120 | ||
1ac4cbbc JR |
2121 | /* allocate a protection domain if a device is added */ |
2122 | dma_domain = find_protection_domain(devid); | |
2123 | if (dma_domain) | |
2124 | goto out; | |
87a64d52 | 2125 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
2126 | if (!dma_domain) |
2127 | goto out; | |
2128 | dma_domain->target_dev = devid; | |
2129 | ||
2130 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2131 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2132 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2133 | ||
e275a2a0 | 2134 | break; |
657cbb6b JR |
2135 | case BUS_NOTIFY_DEL_DEVICE: |
2136 | ||
2137 | iommu_uninit_device(dev); | |
2138 | ||
e275a2a0 JR |
2139 | default: |
2140 | goto out; | |
2141 | } | |
2142 | ||
e275a2a0 JR |
2143 | iommu_completion_wait(iommu); |
2144 | ||
2145 | out: | |
2146 | return 0; | |
2147 | } | |
2148 | ||
b25ae679 | 2149 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2150 | .notifier_call = device_change_notifier, |
2151 | }; | |
355bf553 | 2152 | |
8638c491 JR |
2153 | void amd_iommu_init_notifier(void) |
2154 | { | |
2155 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2156 | } | |
2157 | ||
431b2a20 JR |
2158 | /***************************************************************************** |
2159 | * | |
2160 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2161 | * | |
2162 | *****************************************************************************/ | |
2163 | ||
2164 | /* | |
2165 | * In the dma_ops path we only have the struct device. This function | |
2166 | * finds the corresponding IOMMU, the protection domain and the | |
2167 | * requestor id for a given device. | |
2168 | * If the device is not yet associated with a domain this is also done | |
2169 | * in this function. | |
2170 | */ | |
94f6d190 | 2171 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2172 | { |
94f6d190 | 2173 | struct protection_domain *domain; |
b20ac0d4 | 2174 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2175 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2176 | |
f99c0f1c | 2177 | if (!check_device(dev)) |
94f6d190 | 2178 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2179 | |
94f6d190 JR |
2180 | domain = domain_for_device(dev); |
2181 | if (domain != NULL && !dma_ops_domain(domain)) | |
2182 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2183 | |
94f6d190 JR |
2184 | if (domain != NULL) |
2185 | return domain; | |
b20ac0d4 | 2186 | |
15898bbc | 2187 | /* Device not bount yet - bind it */ |
94f6d190 | 2188 | dma_dom = find_protection_domain(devid); |
15898bbc | 2189 | if (!dma_dom) |
94f6d190 JR |
2190 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2191 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2192 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2193 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2194 | |
94f6d190 | 2195 | return &dma_dom->domain; |
b20ac0d4 JR |
2196 | } |
2197 | ||
04bfdd84 JR |
2198 | static void update_device_table(struct protection_domain *domain) |
2199 | { | |
492667da | 2200 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2201 | |
ea61cddb JR |
2202 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2203 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2204 | } |
2205 | ||
2206 | static void update_domain(struct protection_domain *domain) | |
2207 | { | |
2208 | if (!domain->updated) | |
2209 | return; | |
2210 | ||
2211 | update_device_table(domain); | |
17b124bf JR |
2212 | |
2213 | domain_flush_devices(domain); | |
2214 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2215 | |
2216 | domain->updated = false; | |
2217 | } | |
2218 | ||
8bda3092 JR |
2219 | /* |
2220 | * This function fetches the PTE for a given address in the aperture | |
2221 | */ | |
2222 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2223 | unsigned long address) | |
2224 | { | |
384de729 | 2225 | struct aperture_range *aperture; |
8bda3092 JR |
2226 | u64 *pte, *pte_page; |
2227 | ||
384de729 JR |
2228 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2229 | if (!aperture) | |
2230 | return NULL; | |
2231 | ||
2232 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2233 | if (!pte) { |
cbb9d729 | 2234 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2235 | GFP_ATOMIC); |
384de729 JR |
2236 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2237 | } else | |
8c8c143c | 2238 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2239 | |
04bfdd84 | 2240 | update_domain(&dom->domain); |
8bda3092 JR |
2241 | |
2242 | return pte; | |
2243 | } | |
2244 | ||
431b2a20 JR |
2245 | /* |
2246 | * This is the generic map function. It maps one 4kb page at paddr to | |
2247 | * the given address in the DMA address space for the domain. | |
2248 | */ | |
680525e0 | 2249 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2250 | unsigned long address, |
2251 | phys_addr_t paddr, | |
2252 | int direction) | |
2253 | { | |
2254 | u64 *pte, __pte; | |
2255 | ||
2256 | WARN_ON(address > dom->aperture_size); | |
2257 | ||
2258 | paddr &= PAGE_MASK; | |
2259 | ||
8bda3092 | 2260 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2261 | if (!pte) |
8fd524b3 | 2262 | return DMA_ERROR_CODE; |
cb76c322 JR |
2263 | |
2264 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2265 | ||
2266 | if (direction == DMA_TO_DEVICE) | |
2267 | __pte |= IOMMU_PTE_IR; | |
2268 | else if (direction == DMA_FROM_DEVICE) | |
2269 | __pte |= IOMMU_PTE_IW; | |
2270 | else if (direction == DMA_BIDIRECTIONAL) | |
2271 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2272 | ||
2273 | WARN_ON(*pte); | |
2274 | ||
2275 | *pte = __pte; | |
2276 | ||
2277 | return (dma_addr_t)address; | |
2278 | } | |
2279 | ||
431b2a20 JR |
2280 | /* |
2281 | * The generic unmapping function for on page in the DMA address space. | |
2282 | */ | |
680525e0 | 2283 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2284 | unsigned long address) |
2285 | { | |
384de729 | 2286 | struct aperture_range *aperture; |
cb76c322 JR |
2287 | u64 *pte; |
2288 | ||
2289 | if (address >= dom->aperture_size) | |
2290 | return; | |
2291 | ||
384de729 JR |
2292 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2293 | if (!aperture) | |
2294 | return; | |
2295 | ||
2296 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2297 | if (!pte) | |
2298 | return; | |
cb76c322 | 2299 | |
8c8c143c | 2300 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2301 | |
2302 | WARN_ON(!*pte); | |
2303 | ||
2304 | *pte = 0ULL; | |
2305 | } | |
2306 | ||
431b2a20 JR |
2307 | /* |
2308 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2309 | * contiguous memory region into DMA address space. It is used by all |
2310 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2311 | * Must be called with the domain lock held. |
2312 | */ | |
cb76c322 | 2313 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2314 | struct dma_ops_domain *dma_dom, |
2315 | phys_addr_t paddr, | |
2316 | size_t size, | |
6d4f343f | 2317 | int dir, |
832a90c3 JR |
2318 | bool align, |
2319 | u64 dma_mask) | |
cb76c322 JR |
2320 | { |
2321 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2322 | dma_addr_t address, start, ret; |
cb76c322 | 2323 | unsigned int pages; |
6d4f343f | 2324 | unsigned long align_mask = 0; |
cb76c322 JR |
2325 | int i; |
2326 | ||
e3c449f5 | 2327 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2328 | paddr &= PAGE_MASK; |
2329 | ||
8ecaf8f1 JR |
2330 | INC_STATS_COUNTER(total_map_requests); |
2331 | ||
c1858976 JR |
2332 | if (pages > 1) |
2333 | INC_STATS_COUNTER(cross_page); | |
2334 | ||
6d4f343f JR |
2335 | if (align) |
2336 | align_mask = (1UL << get_order(size)) - 1; | |
2337 | ||
11b83888 | 2338 | retry: |
832a90c3 JR |
2339 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2340 | dma_mask); | |
8fd524b3 | 2341 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2342 | /* |
2343 | * setting next_address here will let the address | |
2344 | * allocator only scan the new allocated range in the | |
2345 | * first run. This is a small optimization. | |
2346 | */ | |
2347 | dma_dom->next_address = dma_dom->aperture_size; | |
2348 | ||
576175c2 | 2349 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2350 | goto out; |
2351 | ||
2352 | /* | |
af901ca1 | 2353 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2354 | * allocation again |
2355 | */ | |
2356 | goto retry; | |
2357 | } | |
cb76c322 JR |
2358 | |
2359 | start = address; | |
2360 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2361 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2362 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2363 | goto out_unmap; |
2364 | ||
cb76c322 JR |
2365 | paddr += PAGE_SIZE; |
2366 | start += PAGE_SIZE; | |
2367 | } | |
2368 | address += offset; | |
2369 | ||
5774f7c5 JR |
2370 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2371 | ||
afa9fdc2 | 2372 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2373 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2374 | dma_dom->need_flush = false; |
318afd41 | 2375 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2376 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2377 | |
cb76c322 JR |
2378 | out: |
2379 | return address; | |
53812c11 JR |
2380 | |
2381 | out_unmap: | |
2382 | ||
2383 | for (--i; i >= 0; --i) { | |
2384 | start -= PAGE_SIZE; | |
680525e0 | 2385 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2386 | } |
2387 | ||
2388 | dma_ops_free_addresses(dma_dom, address, pages); | |
2389 | ||
8fd524b3 | 2390 | return DMA_ERROR_CODE; |
cb76c322 JR |
2391 | } |
2392 | ||
431b2a20 JR |
2393 | /* |
2394 | * Does the reverse of the __map_single function. Must be called with | |
2395 | * the domain lock held too | |
2396 | */ | |
cd8c82e8 | 2397 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2398 | dma_addr_t dma_addr, |
2399 | size_t size, | |
2400 | int dir) | |
2401 | { | |
04e0463e | 2402 | dma_addr_t flush_addr; |
cb76c322 JR |
2403 | dma_addr_t i, start; |
2404 | unsigned int pages; | |
2405 | ||
8fd524b3 | 2406 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2407 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2408 | return; |
2409 | ||
04e0463e | 2410 | flush_addr = dma_addr; |
e3c449f5 | 2411 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2412 | dma_addr &= PAGE_MASK; |
2413 | start = dma_addr; | |
2414 | ||
2415 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2416 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2417 | start += PAGE_SIZE; |
2418 | } | |
2419 | ||
5774f7c5 JR |
2420 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2421 | ||
cb76c322 | 2422 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2423 | |
80be308d | 2424 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2425 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2426 | dma_dom->need_flush = false; |
2427 | } | |
cb76c322 JR |
2428 | } |
2429 | ||
431b2a20 JR |
2430 | /* |
2431 | * The exported map_single function for dma_ops. | |
2432 | */ | |
51491367 FT |
2433 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2434 | unsigned long offset, size_t size, | |
2435 | enum dma_data_direction dir, | |
2436 | struct dma_attrs *attrs) | |
4da70b9e JR |
2437 | { |
2438 | unsigned long flags; | |
4da70b9e | 2439 | struct protection_domain *domain; |
4da70b9e | 2440 | dma_addr_t addr; |
832a90c3 | 2441 | u64 dma_mask; |
51491367 | 2442 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2443 | |
0f2a86f2 JR |
2444 | INC_STATS_COUNTER(cnt_map_single); |
2445 | ||
94f6d190 JR |
2446 | domain = get_domain(dev); |
2447 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2448 | return (dma_addr_t)paddr; |
94f6d190 JR |
2449 | else if (IS_ERR(domain)) |
2450 | return DMA_ERROR_CODE; | |
4da70b9e | 2451 | |
f99c0f1c JR |
2452 | dma_mask = *dev->dma_mask; |
2453 | ||
4da70b9e | 2454 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2455 | |
cd8c82e8 | 2456 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2457 | dma_mask); |
8fd524b3 | 2458 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2459 | goto out; |
2460 | ||
17b124bf | 2461 | domain_flush_complete(domain); |
4da70b9e JR |
2462 | |
2463 | out: | |
2464 | spin_unlock_irqrestore(&domain->lock, flags); | |
2465 | ||
2466 | return addr; | |
2467 | } | |
2468 | ||
431b2a20 JR |
2469 | /* |
2470 | * The exported unmap_single function for dma_ops. | |
2471 | */ | |
51491367 FT |
2472 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2473 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2474 | { |
2475 | unsigned long flags; | |
4da70b9e | 2476 | struct protection_domain *domain; |
4da70b9e | 2477 | |
146a6917 JR |
2478 | INC_STATS_COUNTER(cnt_unmap_single); |
2479 | ||
94f6d190 JR |
2480 | domain = get_domain(dev); |
2481 | if (IS_ERR(domain)) | |
5b28df6f JR |
2482 | return; |
2483 | ||
4da70b9e JR |
2484 | spin_lock_irqsave(&domain->lock, flags); |
2485 | ||
cd8c82e8 | 2486 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2487 | |
17b124bf | 2488 | domain_flush_complete(domain); |
4da70b9e JR |
2489 | |
2490 | spin_unlock_irqrestore(&domain->lock, flags); | |
2491 | } | |
2492 | ||
431b2a20 JR |
2493 | /* |
2494 | * This is a special map_sg function which is used if we should map a | |
2495 | * device which is not handled by an AMD IOMMU in the system. | |
2496 | */ | |
65b050ad JR |
2497 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2498 | int nelems, int dir) | |
2499 | { | |
2500 | struct scatterlist *s; | |
2501 | int i; | |
2502 | ||
2503 | for_each_sg(sglist, s, nelems, i) { | |
2504 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2505 | s->dma_length = s->length; | |
2506 | } | |
2507 | ||
2508 | return nelems; | |
2509 | } | |
2510 | ||
431b2a20 JR |
2511 | /* |
2512 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2513 | * lists). | |
2514 | */ | |
65b050ad | 2515 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2516 | int nelems, enum dma_data_direction dir, |
2517 | struct dma_attrs *attrs) | |
65b050ad JR |
2518 | { |
2519 | unsigned long flags; | |
65b050ad | 2520 | struct protection_domain *domain; |
65b050ad JR |
2521 | int i; |
2522 | struct scatterlist *s; | |
2523 | phys_addr_t paddr; | |
2524 | int mapped_elems = 0; | |
832a90c3 | 2525 | u64 dma_mask; |
65b050ad | 2526 | |
d03f067a JR |
2527 | INC_STATS_COUNTER(cnt_map_sg); |
2528 | ||
94f6d190 JR |
2529 | domain = get_domain(dev); |
2530 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2531 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2532 | else if (IS_ERR(domain)) |
2533 | return 0; | |
dbcc112e | 2534 | |
832a90c3 | 2535 | dma_mask = *dev->dma_mask; |
65b050ad | 2536 | |
65b050ad JR |
2537 | spin_lock_irqsave(&domain->lock, flags); |
2538 | ||
2539 | for_each_sg(sglist, s, nelems, i) { | |
2540 | paddr = sg_phys(s); | |
2541 | ||
cd8c82e8 | 2542 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2543 | paddr, s->length, dir, false, |
2544 | dma_mask); | |
65b050ad JR |
2545 | |
2546 | if (s->dma_address) { | |
2547 | s->dma_length = s->length; | |
2548 | mapped_elems++; | |
2549 | } else | |
2550 | goto unmap; | |
65b050ad JR |
2551 | } |
2552 | ||
17b124bf | 2553 | domain_flush_complete(domain); |
65b050ad JR |
2554 | |
2555 | out: | |
2556 | spin_unlock_irqrestore(&domain->lock, flags); | |
2557 | ||
2558 | return mapped_elems; | |
2559 | unmap: | |
2560 | for_each_sg(sglist, s, mapped_elems, i) { | |
2561 | if (s->dma_address) | |
cd8c82e8 | 2562 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2563 | s->dma_length, dir); |
2564 | s->dma_address = s->dma_length = 0; | |
2565 | } | |
2566 | ||
2567 | mapped_elems = 0; | |
2568 | ||
2569 | goto out; | |
2570 | } | |
2571 | ||
431b2a20 JR |
2572 | /* |
2573 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2574 | * lists). | |
2575 | */ | |
65b050ad | 2576 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2577 | int nelems, enum dma_data_direction dir, |
2578 | struct dma_attrs *attrs) | |
65b050ad JR |
2579 | { |
2580 | unsigned long flags; | |
65b050ad JR |
2581 | struct protection_domain *domain; |
2582 | struct scatterlist *s; | |
65b050ad JR |
2583 | int i; |
2584 | ||
55877a6b JR |
2585 | INC_STATS_COUNTER(cnt_unmap_sg); |
2586 | ||
94f6d190 JR |
2587 | domain = get_domain(dev); |
2588 | if (IS_ERR(domain)) | |
5b28df6f JR |
2589 | return; |
2590 | ||
65b050ad JR |
2591 | spin_lock_irqsave(&domain->lock, flags); |
2592 | ||
2593 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2594 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2595 | s->dma_length, dir); |
65b050ad JR |
2596 | s->dma_address = s->dma_length = 0; |
2597 | } | |
2598 | ||
17b124bf | 2599 | domain_flush_complete(domain); |
65b050ad JR |
2600 | |
2601 | spin_unlock_irqrestore(&domain->lock, flags); | |
2602 | } | |
2603 | ||
431b2a20 JR |
2604 | /* |
2605 | * The exported alloc_coherent function for dma_ops. | |
2606 | */ | |
5d8b53cf JR |
2607 | static void *alloc_coherent(struct device *dev, size_t size, |
2608 | dma_addr_t *dma_addr, gfp_t flag) | |
2609 | { | |
2610 | unsigned long flags; | |
2611 | void *virt_addr; | |
5d8b53cf | 2612 | struct protection_domain *domain; |
5d8b53cf | 2613 | phys_addr_t paddr; |
832a90c3 | 2614 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2615 | |
c8f0fb36 JR |
2616 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2617 | ||
94f6d190 JR |
2618 | domain = get_domain(dev); |
2619 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2620 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2621 | *dma_addr = __pa(virt_addr); | |
2622 | return virt_addr; | |
94f6d190 JR |
2623 | } else if (IS_ERR(domain)) |
2624 | return NULL; | |
5d8b53cf | 2625 | |
f99c0f1c JR |
2626 | dma_mask = dev->coherent_dma_mask; |
2627 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2628 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2629 | |
2630 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2631 | if (!virt_addr) | |
b25ae679 | 2632 | return NULL; |
5d8b53cf | 2633 | |
5d8b53cf JR |
2634 | paddr = virt_to_phys(virt_addr); |
2635 | ||
832a90c3 JR |
2636 | if (!dma_mask) |
2637 | dma_mask = *dev->dma_mask; | |
2638 | ||
5d8b53cf JR |
2639 | spin_lock_irqsave(&domain->lock, flags); |
2640 | ||
cd8c82e8 | 2641 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2642 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2643 | |
8fd524b3 | 2644 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2645 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2646 | goto out_free; |
367d04c4 | 2647 | } |
5d8b53cf | 2648 | |
17b124bf | 2649 | domain_flush_complete(domain); |
5d8b53cf | 2650 | |
5d8b53cf JR |
2651 | spin_unlock_irqrestore(&domain->lock, flags); |
2652 | ||
2653 | return virt_addr; | |
5b28df6f JR |
2654 | |
2655 | out_free: | |
2656 | ||
2657 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2658 | ||
2659 | return NULL; | |
5d8b53cf JR |
2660 | } |
2661 | ||
431b2a20 JR |
2662 | /* |
2663 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2664 | */ |
5d8b53cf JR |
2665 | static void free_coherent(struct device *dev, size_t size, |
2666 | void *virt_addr, dma_addr_t dma_addr) | |
2667 | { | |
2668 | unsigned long flags; | |
5d8b53cf | 2669 | struct protection_domain *domain; |
5d8b53cf | 2670 | |
5d31ee7e JR |
2671 | INC_STATS_COUNTER(cnt_free_coherent); |
2672 | ||
94f6d190 JR |
2673 | domain = get_domain(dev); |
2674 | if (IS_ERR(domain)) | |
5b28df6f JR |
2675 | goto free_mem; |
2676 | ||
5d8b53cf JR |
2677 | spin_lock_irqsave(&domain->lock, flags); |
2678 | ||
cd8c82e8 | 2679 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2680 | |
17b124bf | 2681 | domain_flush_complete(domain); |
5d8b53cf JR |
2682 | |
2683 | spin_unlock_irqrestore(&domain->lock, flags); | |
2684 | ||
2685 | free_mem: | |
2686 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2687 | } | |
2688 | ||
b39ba6ad JR |
2689 | /* |
2690 | * This function is called by the DMA layer to find out if we can handle a | |
2691 | * particular device. It is part of the dma_ops. | |
2692 | */ | |
2693 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2694 | { | |
420aef8a | 2695 | return check_device(dev); |
b39ba6ad JR |
2696 | } |
2697 | ||
c432f3df | 2698 | /* |
431b2a20 JR |
2699 | * The function for pre-allocating protection domains. |
2700 | * | |
c432f3df JR |
2701 | * If the driver core informs the DMA layer if a driver grabs a device |
2702 | * we don't need to preallocate the protection domains anymore. | |
2703 | * For now we have to. | |
2704 | */ | |
0e93dd88 | 2705 | static void prealloc_protection_domains(void) |
c432f3df | 2706 | { |
5abcdba4 | 2707 | struct iommu_dev_data *dev_data; |
c432f3df | 2708 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 2709 | struct pci_dev *dev = NULL; |
98fc5a69 | 2710 | u16 devid; |
c432f3df | 2711 | |
d18c69d3 | 2712 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2713 | |
2714 | /* Do we handle this device? */ | |
2715 | if (!check_device(&dev->dev)) | |
c432f3df | 2716 | continue; |
98fc5a69 | 2717 | |
5abcdba4 JR |
2718 | dev_data = get_dev_data(&dev->dev); |
2719 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
2720 | /* Make sure passthrough domain is allocated */ | |
2721 | alloc_passthrough_domain(); | |
2722 | dev_data->passthrough = true; | |
2723 | attach_device(&dev->dev, pt_domain); | |
2724 | pr_info("AMD-Vi: Using passthough domain for device %s\n", | |
2725 | dev_name(&dev->dev)); | |
2726 | } | |
2727 | ||
98fc5a69 | 2728 | /* Is there already any domain for it? */ |
15898bbc | 2729 | if (domain_for_device(&dev->dev)) |
c432f3df | 2730 | continue; |
98fc5a69 JR |
2731 | |
2732 | devid = get_device_id(&dev->dev); | |
2733 | ||
87a64d52 | 2734 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2735 | if (!dma_dom) |
2736 | continue; | |
2737 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2738 | dma_dom->target_dev = devid; |
2739 | ||
15898bbc | 2740 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2741 | |
bd60b735 | 2742 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2743 | } |
2744 | } | |
2745 | ||
160c1d8e | 2746 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2747 | .alloc_coherent = alloc_coherent, |
2748 | .free_coherent = free_coherent, | |
51491367 FT |
2749 | .map_page = map_page, |
2750 | .unmap_page = unmap_page, | |
6631ee9d JR |
2751 | .map_sg = map_sg, |
2752 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2753 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2754 | }; |
2755 | ||
27c2127a JR |
2756 | static unsigned device_dma_ops_init(void) |
2757 | { | |
5abcdba4 | 2758 | struct iommu_dev_data *dev_data; |
27c2127a JR |
2759 | struct pci_dev *pdev = NULL; |
2760 | unsigned unhandled = 0; | |
2761 | ||
2762 | for_each_pci_dev(pdev) { | |
2763 | if (!check_device(&pdev->dev)) { | |
2764 | unhandled += 1; | |
2765 | continue; | |
2766 | } | |
2767 | ||
5abcdba4 JR |
2768 | dev_data = get_dev_data(&pdev->dev); |
2769 | ||
2770 | if (!dev_data->passthrough) | |
2771 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2772 | else | |
2773 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
2774 | } |
2775 | ||
2776 | return unhandled; | |
2777 | } | |
2778 | ||
431b2a20 JR |
2779 | /* |
2780 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2781 | */ | |
f5325094 JR |
2782 | |
2783 | void __init amd_iommu_init_api(void) | |
2784 | { | |
2cc21c42 | 2785 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2786 | } |
2787 | ||
6631ee9d JR |
2788 | int __init amd_iommu_init_dma_ops(void) |
2789 | { | |
2790 | struct amd_iommu *iommu; | |
27c2127a | 2791 | int ret, unhandled; |
6631ee9d | 2792 | |
431b2a20 JR |
2793 | /* |
2794 | * first allocate a default protection domain for every IOMMU we | |
2795 | * found in the system. Devices not assigned to any other | |
2796 | * protection domain will be assigned to the default one. | |
2797 | */ | |
3bd22172 | 2798 | for_each_iommu(iommu) { |
87a64d52 | 2799 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2800 | if (iommu->default_dom == NULL) |
2801 | return -ENOMEM; | |
e2dc14a2 | 2802 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2803 | ret = iommu_init_unity_mappings(iommu); |
2804 | if (ret) | |
2805 | goto free_domains; | |
2806 | } | |
2807 | ||
431b2a20 | 2808 | /* |
8793abeb | 2809 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2810 | */ |
8793abeb | 2811 | prealloc_protection_domains(); |
6631ee9d JR |
2812 | |
2813 | iommu_detected = 1; | |
75f1cdf1 | 2814 | swiotlb = 0; |
6631ee9d | 2815 | |
431b2a20 | 2816 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2817 | unhandled = device_dma_ops_init(); |
2818 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2819 | /* There are unhandled devices - initialize swiotlb for them */ | |
2820 | swiotlb = 1; | |
2821 | } | |
6631ee9d | 2822 | |
7f26508b JR |
2823 | amd_iommu_stats_init(); |
2824 | ||
6631ee9d JR |
2825 | return 0; |
2826 | ||
2827 | free_domains: | |
2828 | ||
3bd22172 | 2829 | for_each_iommu(iommu) { |
6631ee9d JR |
2830 | if (iommu->default_dom) |
2831 | dma_ops_domain_free(iommu->default_dom); | |
2832 | } | |
2833 | ||
2834 | return ret; | |
2835 | } | |
6d98cd80 JR |
2836 | |
2837 | /***************************************************************************** | |
2838 | * | |
2839 | * The following functions belong to the exported interface of AMD IOMMU | |
2840 | * | |
2841 | * This interface allows access to lower level functions of the IOMMU | |
2842 | * like protection domain handling and assignement of devices to domains | |
2843 | * which is not possible with the dma_ops interface. | |
2844 | * | |
2845 | *****************************************************************************/ | |
2846 | ||
6d98cd80 JR |
2847 | static void cleanup_domain(struct protection_domain *domain) |
2848 | { | |
492667da | 2849 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2850 | unsigned long flags; |
6d98cd80 JR |
2851 | |
2852 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2853 | ||
492667da | 2854 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 2855 | __detach_device(dev_data); |
492667da JR |
2856 | atomic_set(&dev_data->bind, 0); |
2857 | } | |
6d98cd80 JR |
2858 | |
2859 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2860 | } | |
2861 | ||
2650815f JR |
2862 | static void protection_domain_free(struct protection_domain *domain) |
2863 | { | |
2864 | if (!domain) | |
2865 | return; | |
2866 | ||
aeb26f55 JR |
2867 | del_domain_from_list(domain); |
2868 | ||
2650815f JR |
2869 | if (domain->id) |
2870 | domain_id_free(domain->id); | |
2871 | ||
2872 | kfree(domain); | |
2873 | } | |
2874 | ||
2875 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2876 | { |
2877 | struct protection_domain *domain; | |
2878 | ||
2879 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2880 | if (!domain) | |
2650815f | 2881 | return NULL; |
c156e347 JR |
2882 | |
2883 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2884 | mutex_init(&domain->api_lock); |
c156e347 JR |
2885 | domain->id = domain_id_alloc(); |
2886 | if (!domain->id) | |
2650815f | 2887 | goto out_err; |
7c392cbe | 2888 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2889 | |
aeb26f55 JR |
2890 | add_domain_to_list(domain); |
2891 | ||
2650815f JR |
2892 | return domain; |
2893 | ||
2894 | out_err: | |
2895 | kfree(domain); | |
2896 | ||
2897 | return NULL; | |
2898 | } | |
2899 | ||
5abcdba4 JR |
2900 | static int __init alloc_passthrough_domain(void) |
2901 | { | |
2902 | if (pt_domain != NULL) | |
2903 | return 0; | |
2904 | ||
2905 | /* allocate passthrough domain */ | |
2906 | pt_domain = protection_domain_alloc(); | |
2907 | if (!pt_domain) | |
2908 | return -ENOMEM; | |
2909 | ||
2910 | pt_domain->mode = PAGE_MODE_NONE; | |
2911 | ||
2912 | return 0; | |
2913 | } | |
2650815f JR |
2914 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
2915 | { | |
2916 | struct protection_domain *domain; | |
2917 | ||
2918 | domain = protection_domain_alloc(); | |
2919 | if (!domain) | |
c156e347 | 2920 | goto out_free; |
2650815f JR |
2921 | |
2922 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2923 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2924 | if (!domain->pt_root) | |
2925 | goto out_free; | |
2926 | ||
2927 | dom->priv = domain; | |
2928 | ||
2929 | return 0; | |
2930 | ||
2931 | out_free: | |
2650815f | 2932 | protection_domain_free(domain); |
c156e347 JR |
2933 | |
2934 | return -ENOMEM; | |
2935 | } | |
2936 | ||
98383fc3 JR |
2937 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2938 | { | |
2939 | struct protection_domain *domain = dom->priv; | |
2940 | ||
2941 | if (!domain) | |
2942 | return; | |
2943 | ||
2944 | if (domain->dev_cnt > 0) | |
2945 | cleanup_domain(domain); | |
2946 | ||
2947 | BUG_ON(domain->dev_cnt != 0); | |
2948 | ||
132bd68f JR |
2949 | if (domain->mode != PAGE_MODE_NONE) |
2950 | free_pagetable(domain); | |
98383fc3 | 2951 | |
52815b75 JR |
2952 | if (domain->flags & PD_IOMMUV2_MASK) |
2953 | free_gcr3_table(domain); | |
2954 | ||
8b408fe4 | 2955 | protection_domain_free(domain); |
98383fc3 JR |
2956 | |
2957 | dom->priv = NULL; | |
2958 | } | |
2959 | ||
684f2888 JR |
2960 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2961 | struct device *dev) | |
2962 | { | |
657cbb6b | 2963 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2964 | struct amd_iommu *iommu; |
684f2888 JR |
2965 | u16 devid; |
2966 | ||
98fc5a69 | 2967 | if (!check_device(dev)) |
684f2888 JR |
2968 | return; |
2969 | ||
98fc5a69 | 2970 | devid = get_device_id(dev); |
684f2888 | 2971 | |
657cbb6b | 2972 | if (dev_data->domain != NULL) |
15898bbc | 2973 | detach_device(dev); |
684f2888 JR |
2974 | |
2975 | iommu = amd_iommu_rlookup_table[devid]; | |
2976 | if (!iommu) | |
2977 | return; | |
2978 | ||
684f2888 JR |
2979 | iommu_completion_wait(iommu); |
2980 | } | |
2981 | ||
01106066 JR |
2982 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2983 | struct device *dev) | |
2984 | { | |
2985 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2986 | struct iommu_dev_data *dev_data; |
01106066 | 2987 | struct amd_iommu *iommu; |
15898bbc | 2988 | int ret; |
01106066 | 2989 | |
98fc5a69 | 2990 | if (!check_device(dev)) |
01106066 JR |
2991 | return -EINVAL; |
2992 | ||
657cbb6b JR |
2993 | dev_data = dev->archdata.iommu; |
2994 | ||
f62dda66 | 2995 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
2996 | if (!iommu) |
2997 | return -EINVAL; | |
2998 | ||
657cbb6b | 2999 | if (dev_data->domain) |
15898bbc | 3000 | detach_device(dev); |
01106066 | 3001 | |
15898bbc | 3002 | ret = attach_device(dev, domain); |
01106066 JR |
3003 | |
3004 | iommu_completion_wait(iommu); | |
3005 | ||
15898bbc | 3006 | return ret; |
01106066 JR |
3007 | } |
3008 | ||
468e2366 JR |
3009 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
3010 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 3011 | { |
468e2366 | 3012 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 3013 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
3014 | int prot = 0; |
3015 | int ret; | |
3016 | ||
132bd68f JR |
3017 | if (domain->mode == PAGE_MODE_NONE) |
3018 | return -EINVAL; | |
3019 | ||
c6229ca6 JR |
3020 | if (iommu_prot & IOMMU_READ) |
3021 | prot |= IOMMU_PROT_IR; | |
3022 | if (iommu_prot & IOMMU_WRITE) | |
3023 | prot |= IOMMU_PROT_IW; | |
3024 | ||
5d214fe6 | 3025 | mutex_lock(&domain->api_lock); |
795e74f7 | 3026 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3027 | mutex_unlock(&domain->api_lock); |
3028 | ||
795e74f7 | 3029 | return ret; |
c6229ca6 JR |
3030 | } |
3031 | ||
468e2366 JR |
3032 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3033 | int gfp_order) | |
eb74ff6c | 3034 | { |
eb74ff6c | 3035 | struct protection_domain *domain = dom->priv; |
468e2366 | 3036 | unsigned long page_size, unmap_size; |
eb74ff6c | 3037 | |
132bd68f JR |
3038 | if (domain->mode == PAGE_MODE_NONE) |
3039 | return -EINVAL; | |
3040 | ||
468e2366 | 3041 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 3042 | |
5d214fe6 | 3043 | mutex_lock(&domain->api_lock); |
468e2366 | 3044 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3045 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3046 | |
17b124bf | 3047 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3048 | |
468e2366 | 3049 | return get_order(unmap_size); |
eb74ff6c JR |
3050 | } |
3051 | ||
645c4c8d JR |
3052 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
3053 | unsigned long iova) | |
3054 | { | |
3055 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3056 | unsigned long offset_mask; |
645c4c8d | 3057 | phys_addr_t paddr; |
f03152bb | 3058 | u64 *pte, __pte; |
645c4c8d | 3059 | |
132bd68f JR |
3060 | if (domain->mode == PAGE_MODE_NONE) |
3061 | return iova; | |
3062 | ||
24cd7723 | 3063 | pte = fetch_pte(domain, iova); |
645c4c8d | 3064 | |
a6d41a40 | 3065 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3066 | return 0; |
3067 | ||
f03152bb JR |
3068 | if (PM_PTE_LEVEL(*pte) == 0) |
3069 | offset_mask = PAGE_SIZE - 1; | |
3070 | else | |
3071 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3072 | ||
3073 | __pte = *pte & PM_ADDR_MASK; | |
3074 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3075 | |
3076 | return paddr; | |
3077 | } | |
3078 | ||
dbb9fd86 SY |
3079 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
3080 | unsigned long cap) | |
3081 | { | |
80a506b8 JR |
3082 | switch (cap) { |
3083 | case IOMMU_CAP_CACHE_COHERENCY: | |
3084 | return 1; | |
3085 | } | |
3086 | ||
dbb9fd86 SY |
3087 | return 0; |
3088 | } | |
3089 | ||
26961efe JR |
3090 | static struct iommu_ops amd_iommu_ops = { |
3091 | .domain_init = amd_iommu_domain_init, | |
3092 | .domain_destroy = amd_iommu_domain_destroy, | |
3093 | .attach_dev = amd_iommu_attach_device, | |
3094 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3095 | .map = amd_iommu_map, |
3096 | .unmap = amd_iommu_unmap, | |
26961efe | 3097 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 3098 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
3099 | }; |
3100 | ||
0feae533 JR |
3101 | /***************************************************************************** |
3102 | * | |
3103 | * The next functions do a basic initialization of IOMMU for pass through | |
3104 | * mode | |
3105 | * | |
3106 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3107 | * DMA-API translation. | |
3108 | * | |
3109 | *****************************************************************************/ | |
3110 | ||
3111 | int __init amd_iommu_init_passthrough(void) | |
3112 | { | |
5abcdba4 | 3113 | struct iommu_dev_data *dev_data; |
0feae533 | 3114 | struct pci_dev *dev = NULL; |
5abcdba4 | 3115 | struct amd_iommu *iommu; |
15898bbc | 3116 | u16 devid; |
5abcdba4 | 3117 | int ret; |
0feae533 | 3118 | |
5abcdba4 JR |
3119 | ret = alloc_passthrough_domain(); |
3120 | if (ret) | |
3121 | return ret; | |
0feae533 | 3122 | |
6c54aabd | 3123 | for_each_pci_dev(dev) { |
98fc5a69 | 3124 | if (!check_device(&dev->dev)) |
0feae533 JR |
3125 | continue; |
3126 | ||
5abcdba4 JR |
3127 | dev_data = get_dev_data(&dev->dev); |
3128 | dev_data->passthrough = true; | |
3129 | ||
98fc5a69 JR |
3130 | devid = get_device_id(&dev->dev); |
3131 | ||
15898bbc | 3132 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
3133 | if (!iommu) |
3134 | continue; | |
3135 | ||
15898bbc | 3136 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3137 | } |
3138 | ||
3139 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
3140 | ||
3141 | return 0; | |
3142 | } | |
72e1dcc4 JR |
3143 | |
3144 | /* IOMMUv2 specific functions */ | |
3145 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3146 | { | |
3147 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3148 | } | |
3149 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3150 | ||
3151 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3152 | { | |
3153 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3154 | } | |
3155 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3156 | |
3157 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3158 | { | |
3159 | struct protection_domain *domain = dom->priv; | |
3160 | unsigned long flags; | |
3161 | ||
3162 | spin_lock_irqsave(&domain->lock, flags); | |
3163 | ||
3164 | /* Update data structure */ | |
3165 | domain->mode = PAGE_MODE_NONE; | |
3166 | domain->updated = true; | |
3167 | ||
3168 | /* Make changes visible to IOMMUs */ | |
3169 | update_domain(domain); | |
3170 | ||
3171 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3172 | free_pagetable(domain); | |
3173 | ||
3174 | spin_unlock_irqrestore(&domain->lock, flags); | |
3175 | } | |
3176 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3177 | |
3178 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3179 | { | |
3180 | struct protection_domain *domain = dom->priv; | |
3181 | unsigned long flags; | |
3182 | int levels, ret; | |
3183 | ||
3184 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3185 | return -EINVAL; | |
3186 | ||
3187 | /* Number of GCR3 table levels required */ | |
3188 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3189 | levels += 1; | |
3190 | ||
3191 | if (levels > amd_iommu_max_glx_val) | |
3192 | return -EINVAL; | |
3193 | ||
3194 | spin_lock_irqsave(&domain->lock, flags); | |
3195 | ||
3196 | /* | |
3197 | * Save us all sanity checks whether devices already in the | |
3198 | * domain support IOMMUv2. Just force that the domain has no | |
3199 | * devices attached when it is switched into IOMMUv2 mode. | |
3200 | */ | |
3201 | ret = -EBUSY; | |
3202 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3203 | goto out; | |
3204 | ||
3205 | ret = -ENOMEM; | |
3206 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3207 | if (domain->gcr3_tbl == NULL) | |
3208 | goto out; | |
3209 | ||
3210 | domain->glx = levels; | |
3211 | domain->flags |= PD_IOMMUV2_MASK; | |
3212 | domain->updated = true; | |
3213 | ||
3214 | update_domain(domain); | |
3215 | ||
3216 | ret = 0; | |
3217 | ||
3218 | out: | |
3219 | spin_unlock_irqrestore(&domain->lock, flags); | |
3220 | ||
3221 | return ret; | |
3222 | } | |
3223 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3224 | |
3225 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3226 | u64 address, bool size) | |
3227 | { | |
3228 | struct iommu_dev_data *dev_data; | |
3229 | struct iommu_cmd cmd; | |
3230 | int i, ret; | |
3231 | ||
3232 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3233 | return -EINVAL; | |
3234 | ||
3235 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3236 | ||
3237 | /* | |
3238 | * IOMMU TLB needs to be flushed before Device TLB to | |
3239 | * prevent device TLB refill from IOMMU TLB | |
3240 | */ | |
3241 | for (i = 0; i < amd_iommus_present; ++i) { | |
3242 | if (domain->dev_iommu[i] == 0) | |
3243 | continue; | |
3244 | ||
3245 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3246 | if (ret != 0) | |
3247 | goto out; | |
3248 | } | |
3249 | ||
3250 | /* Wait until IOMMU TLB flushes are complete */ | |
3251 | domain_flush_complete(domain); | |
3252 | ||
3253 | /* Now flush device TLBs */ | |
3254 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3255 | struct amd_iommu *iommu; | |
3256 | int qdep; | |
3257 | ||
3258 | BUG_ON(!dev_data->ats.enabled); | |
3259 | ||
3260 | qdep = dev_data->ats.qdep; | |
3261 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3262 | ||
3263 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3264 | qdep, address, size); | |
3265 | ||
3266 | ret = iommu_queue_command(iommu, &cmd); | |
3267 | if (ret != 0) | |
3268 | goto out; | |
3269 | } | |
3270 | ||
3271 | /* Wait until all device TLBs are flushed */ | |
3272 | domain_flush_complete(domain); | |
3273 | ||
3274 | ret = 0; | |
3275 | ||
3276 | out: | |
3277 | ||
3278 | return ret; | |
3279 | } | |
3280 | ||
3281 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3282 | u64 address) | |
3283 | { | |
3284 | return __flush_pasid(domain, pasid, address, false); | |
3285 | } | |
3286 | ||
3287 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3288 | u64 address) | |
3289 | { | |
3290 | struct protection_domain *domain = dom->priv; | |
3291 | unsigned long flags; | |
3292 | int ret; | |
3293 | ||
3294 | spin_lock_irqsave(&domain->lock, flags); | |
3295 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3296 | spin_unlock_irqrestore(&domain->lock, flags); | |
3297 | ||
3298 | return ret; | |
3299 | } | |
3300 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3301 | ||
3302 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3303 | { | |
3304 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3305 | true); | |
3306 | } | |
3307 | ||
3308 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3309 | { | |
3310 | struct protection_domain *domain = dom->priv; | |
3311 | unsigned long flags; | |
3312 | int ret; | |
3313 | ||
3314 | spin_lock_irqsave(&domain->lock, flags); | |
3315 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3316 | spin_unlock_irqrestore(&domain->lock, flags); | |
3317 | ||
3318 | return ret; | |
3319 | } | |
3320 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3321 | ||
b16137b1 JR |
3322 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3323 | { | |
3324 | int index; | |
3325 | u64 *pte; | |
3326 | ||
3327 | while (true) { | |
3328 | ||
3329 | index = (pasid >> (9 * level)) & 0x1ff; | |
3330 | pte = &root[index]; | |
3331 | ||
3332 | if (level == 0) | |
3333 | break; | |
3334 | ||
3335 | if (!(*pte & GCR3_VALID)) { | |
3336 | if (!alloc) | |
3337 | return NULL; | |
3338 | ||
3339 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3340 | if (root == NULL) | |
3341 | return NULL; | |
3342 | ||
3343 | *pte = __pa(root) | GCR3_VALID; | |
3344 | } | |
3345 | ||
3346 | root = __va(*pte & PAGE_MASK); | |
3347 | ||
3348 | level -= 1; | |
3349 | } | |
3350 | ||
3351 | return pte; | |
3352 | } | |
3353 | ||
3354 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3355 | unsigned long cr3) | |
3356 | { | |
3357 | u64 *pte; | |
3358 | ||
3359 | if (domain->mode != PAGE_MODE_NONE) | |
3360 | return -EINVAL; | |
3361 | ||
3362 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3363 | if (pte == NULL) | |
3364 | return -ENOMEM; | |
3365 | ||
3366 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3367 | ||
3368 | return __amd_iommu_flush_tlb(domain, pasid); | |
3369 | } | |
3370 | ||
3371 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3372 | { | |
3373 | u64 *pte; | |
3374 | ||
3375 | if (domain->mode != PAGE_MODE_NONE) | |
3376 | return -EINVAL; | |
3377 | ||
3378 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3379 | if (pte == NULL) | |
3380 | return 0; | |
3381 | ||
3382 | *pte = 0; | |
3383 | ||
3384 | return __amd_iommu_flush_tlb(domain, pasid); | |
3385 | } | |
3386 | ||
3387 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3388 | unsigned long cr3) | |
3389 | { | |
3390 | struct protection_domain *domain = dom->priv; | |
3391 | unsigned long flags; | |
3392 | int ret; | |
3393 | ||
3394 | spin_lock_irqsave(&domain->lock, flags); | |
3395 | ret = __set_gcr3(domain, pasid, cr3); | |
3396 | spin_unlock_irqrestore(&domain->lock, flags); | |
3397 | ||
3398 | return ret; | |
3399 | } | |
3400 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3401 | ||
3402 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3403 | { | |
3404 | struct protection_domain *domain = dom->priv; | |
3405 | unsigned long flags; | |
3406 | int ret; | |
3407 | ||
3408 | spin_lock_irqsave(&domain->lock, flags); | |
3409 | ret = __clear_gcr3(domain, pasid); | |
3410 | spin_unlock_irqrestore(&domain->lock, flags); | |
3411 | ||
3412 | return ret; | |
3413 | } | |
3414 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); |