Commit | Line | Data |
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45051539 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b6c02715 | 2 | /* |
5d0d7156 | 3 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 4 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 | 5 | * Leo Duran <leo.duran@amd.com> |
b6c02715 JR |
6 | */ |
7 | ||
101fa037 | 8 | #define pr_fmt(fmt) "AMD-Vi: " fmt |
5f226da1 | 9 | #define dev_fmt(fmt) pr_fmt(fmt) |
101fa037 | 10 | |
72e1dcc4 | 11 | #include <linux/ratelimit.h> |
b6c02715 | 12 | #include <linux/pci.h> |
2bf9a0a1 | 13 | #include <linux/acpi.h> |
9a4d3bf5 | 14 | #include <linux/amba/bus.h> |
0076cd3d | 15 | #include <linux/platform_device.h> |
cb41ed85 | 16 | #include <linux/pci-ats.h> |
a66022c4 | 17 | #include <linux/bitmap.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
7f26508b | 19 | #include <linux/debugfs.h> |
b6c02715 | 20 | #include <linux/scatterlist.h> |
51491367 | 21 | #include <linux/dma-mapping.h> |
fec777c3 | 22 | #include <linux/dma-direct.h> |
b6c02715 | 23 | #include <linux/iommu-helper.h> |
c156e347 | 24 | #include <linux/iommu.h> |
815b33fd | 25 | #include <linux/delay.h> |
403f81d8 | 26 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
27 | #include <linux/notifier.h> |
28 | #include <linux/export.h> | |
2b324506 JR |
29 | #include <linux/irq.h> |
30 | #include <linux/msi.h> | |
3b839a57 | 31 | #include <linux/dma-contiguous.h> |
7c71d306 | 32 | #include <linux/irqdomain.h> |
5f6bed50 | 33 | #include <linux/percpu.h> |
307d5851 | 34 | #include <linux/iova.h> |
2b324506 JR |
35 | #include <asm/irq_remapping.h> |
36 | #include <asm/io_apic.h> | |
37 | #include <asm/apic.h> | |
38 | #include <asm/hw_irq.h> | |
17f5b569 | 39 | #include <asm/msidef.h> |
b6c02715 | 40 | #include <asm/proto.h> |
46a7fa27 | 41 | #include <asm/iommu.h> |
1d9b16d1 | 42 | #include <asm/gart.h> |
27c2127a | 43 | #include <asm/dma.h> |
403f81d8 JR |
44 | |
45 | #include "amd_iommu_proto.h" | |
46 | #include "amd_iommu_types.h" | |
6b474b82 | 47 | #include "irq_remapping.h" |
b6c02715 JR |
48 | |
49 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
50 | ||
815b33fd | 51 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 52 | |
307d5851 JR |
53 | /* IO virtual address start page frame number */ |
54 | #define IOVA_START_PFN (1) | |
55 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
307d5851 | 56 | |
81cd07b9 JR |
57 | /* Reserved IOVA ranges */ |
58 | #define MSI_RANGE_START (0xfee00000) | |
59 | #define MSI_RANGE_END (0xfeefffff) | |
60 | #define HT_RANGE_START (0xfd00000000ULL) | |
61 | #define HT_RANGE_END (0xffffffffffULL) | |
62 | ||
aa3de9c0 OBC |
63 | /* |
64 | * This bitmap is used to advertise the page sizes our hardware support | |
65 | * to the IOMMU core, which will then use this information to split | |
66 | * physically contiguous memory regions it is mapping into page sizes | |
67 | * that we support. | |
68 | * | |
954e3dd8 | 69 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 70 | */ |
954e3dd8 | 71 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 72 | |
2cd1083d | 73 | static DEFINE_SPINLOCK(amd_iommu_devtable_lock); |
2bc00180 | 74 | static DEFINE_SPINLOCK(pd_bitmap_lock); |
b6c02715 | 75 | |
8fa5f802 | 76 | /* List of all available dev_data structures */ |
779da732 | 77 | static LLIST_HEAD(dev_data_list); |
8fa5f802 | 78 | |
6efed63b JR |
79 | LIST_HEAD(ioapic_map); |
80 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 81 | LIST_HEAD(acpihid_map); |
6efed63b | 82 | |
0feae533 JR |
83 | /* |
84 | * Domain for untranslated devices - only allocated | |
85 | * if iommu=pt passed on kernel cmd line. | |
86 | */ | |
b0119e87 | 87 | const struct iommu_ops amd_iommu_ops; |
26961efe | 88 | |
72e1dcc4 | 89 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 90 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 91 | |
5299709d | 92 | static const struct dma_map_ops amd_iommu_dma_ops; |
ac1534a5 | 93 | |
431b2a20 JR |
94 | /* |
95 | * general struct to manage commands send to an IOMMU | |
96 | */ | |
d6449536 | 97 | struct iommu_cmd { |
b6c02715 JR |
98 | u32 data[4]; |
99 | }; | |
100 | ||
05152a04 JR |
101 | struct kmem_cache *amd_iommu_irq_cache; |
102 | ||
04bfdd84 | 103 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 104 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 105 | static void detach_device(struct device *dev); |
9003d618 | 106 | static void iova_domain_flush_tlb(struct iova_domain *iovad); |
d4241a27 | 107 | |
007b74ba JR |
108 | /* |
109 | * Data container for a dma_ops specific protection domain | |
110 | */ | |
111 | struct dma_ops_domain { | |
112 | /* generic protection domain information */ | |
113 | struct protection_domain domain; | |
114 | ||
307d5851 JR |
115 | /* IOVA RB-Tree */ |
116 | struct iova_domain iovad; | |
007b74ba JR |
117 | }; |
118 | ||
81cd07b9 JR |
119 | static struct iova_domain reserved_iova_ranges; |
120 | static struct lock_class_key reserved_rbtree_key; | |
121 | ||
15898bbc JR |
122 | /**************************************************************************** |
123 | * | |
124 | * Helper functions | |
125 | * | |
126 | ****************************************************************************/ | |
127 | ||
2bf9a0a1 WZ |
128 | static inline int match_hid_uid(struct device *dev, |
129 | struct acpihid_map_entry *entry) | |
3f4b87b9 | 130 | { |
bb6bccba | 131 | struct acpi_device *adev = ACPI_COMPANION(dev); |
2bf9a0a1 WZ |
132 | const char *hid, *uid; |
133 | ||
bb6bccba AM |
134 | if (!adev) |
135 | return -ENODEV; | |
136 | ||
137 | hid = acpi_device_hid(adev); | |
138 | uid = acpi_device_uid(adev); | |
2bf9a0a1 WZ |
139 | |
140 | if (!hid || !(*hid)) | |
141 | return -ENODEV; | |
142 | ||
143 | if (!uid || !(*uid)) | |
144 | return strcmp(hid, entry->hid); | |
145 | ||
146 | if (!(*entry->uid)) | |
147 | return strcmp(hid, entry->hid); | |
148 | ||
149 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
3f4b87b9 JR |
150 | } |
151 | ||
2bf9a0a1 | 152 | static inline u16 get_pci_device_id(struct device *dev) |
e3156048 JR |
153 | { |
154 | struct pci_dev *pdev = to_pci_dev(dev); | |
155 | ||
775c068c | 156 | return pci_dev_id(pdev); |
e3156048 JR |
157 | } |
158 | ||
2bf9a0a1 WZ |
159 | static inline int get_acpihid_device_id(struct device *dev, |
160 | struct acpihid_map_entry **entry) | |
161 | { | |
162 | struct acpihid_map_entry *p; | |
163 | ||
164 | list_for_each_entry(p, &acpihid_map, list) { | |
165 | if (!match_hid_uid(dev, p)) { | |
166 | if (entry) | |
167 | *entry = p; | |
168 | return p->devid; | |
169 | } | |
170 | } | |
171 | return -EINVAL; | |
172 | } | |
173 | ||
174 | static inline int get_device_id(struct device *dev) | |
175 | { | |
176 | int devid; | |
177 | ||
178 | if (dev_is_pci(dev)) | |
179 | devid = get_pci_device_id(dev); | |
180 | else | |
181 | devid = get_acpihid_device_id(dev, NULL); | |
182 | ||
183 | return devid; | |
184 | } | |
185 | ||
3f4b87b9 JR |
186 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
187 | { | |
188 | return container_of(dom, struct protection_domain, domain); | |
189 | } | |
190 | ||
b3311b06 JR |
191 | static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain) |
192 | { | |
193 | BUG_ON(domain->flags != PD_DMA_OPS_MASK); | |
194 | return container_of(domain, struct dma_ops_domain, domain); | |
195 | } | |
196 | ||
f62dda66 | 197 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
198 | { |
199 | struct iommu_dev_data *dev_data; | |
8fa5f802 JR |
200 | |
201 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
202 | if (!dev_data) | |
203 | return NULL; | |
204 | ||
f62dda66 | 205 | dev_data->devid = devid; |
30bf2df6 JR |
206 | ratelimit_default_init(&dev_data->rs); |
207 | ||
779da732 | 208 | llist_add(&dev_data->dev_data_list, &dev_data_list); |
8fa5f802 JR |
209 | return dev_data; |
210 | } | |
211 | ||
3b03bb74 JR |
212 | static struct iommu_dev_data *search_dev_data(u16 devid) |
213 | { | |
214 | struct iommu_dev_data *dev_data; | |
779da732 | 215 | struct llist_node *node; |
3b03bb74 | 216 | |
779da732 SAS |
217 | if (llist_empty(&dev_data_list)) |
218 | return NULL; | |
3b03bb74 | 219 | |
779da732 SAS |
220 | node = dev_data_list.first; |
221 | llist_for_each_entry(dev_data, node, dev_data_list) { | |
3b03bb74 | 222 | if (dev_data->devid == devid) |
779da732 | 223 | return dev_data; |
3b03bb74 JR |
224 | } |
225 | ||
779da732 | 226 | return NULL; |
3b03bb74 JR |
227 | } |
228 | ||
e3156048 JR |
229 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
230 | { | |
231 | *(u16 *)data = alias; | |
232 | return 0; | |
233 | } | |
234 | ||
235 | static u16 get_alias(struct device *dev) | |
236 | { | |
237 | struct pci_dev *pdev = to_pci_dev(dev); | |
238 | u16 devid, ivrs_alias, pci_alias; | |
239 | ||
6c0b43df | 240 | /* The callers make sure that get_device_id() does not fail here */ |
e3156048 | 241 | devid = get_device_id(dev); |
5ebb1bc2 AN |
242 | |
243 | /* For ACPI HID devices, we simply return the devid as such */ | |
244 | if (!dev_is_pci(dev)) | |
245 | return devid; | |
246 | ||
e3156048 | 247 | ivrs_alias = amd_iommu_alias_table[devid]; |
5ebb1bc2 | 248 | |
e3156048 JR |
249 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); |
250 | ||
251 | if (ivrs_alias == pci_alias) | |
252 | return ivrs_alias; | |
253 | ||
254 | /* | |
255 | * DMA alias showdown | |
256 | * | |
257 | * The IVRS is fairly reliable in telling us about aliases, but it | |
258 | * can't know about every screwy device. If we don't have an IVRS | |
259 | * reported alias, use the PCI reported alias. In that case we may | |
260 | * still need to initialize the rlookup and dev_table entries if the | |
261 | * alias is to a non-existent device. | |
262 | */ | |
263 | if (ivrs_alias == devid) { | |
264 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
265 | amd_iommu_rlookup_table[pci_alias] = | |
266 | amd_iommu_rlookup_table[devid]; | |
267 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
268 | amd_iommu_dev_table[devid].data, | |
269 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
270 | } | |
271 | ||
272 | return pci_alias; | |
273 | } | |
274 | ||
5f226da1 BH |
275 | pci_info(pdev, "Using IVRS reported alias %02x:%02x.%d " |
276 | "for device [%04x:%04x], kernel reported alias " | |
e3156048 | 277 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), |
5f226da1 | 278 | PCI_FUNC(ivrs_alias), pdev->vendor, pdev->device, |
e3156048 JR |
279 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), |
280 | PCI_FUNC(pci_alias)); | |
281 | ||
282 | /* | |
283 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
284 | * bus, then the IVRS table may know about a quirk that we don't. | |
285 | */ | |
286 | if (pci_alias == devid && | |
287 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
7afd16f8 | 288 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); |
5f226da1 BH |
289 | pci_info(pdev, "Added PCI DMA alias %02x.%d\n", |
290 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias)); | |
e3156048 JR |
291 | } |
292 | ||
293 | return ivrs_alias; | |
294 | } | |
295 | ||
3b03bb74 JR |
296 | static struct iommu_dev_data *find_dev_data(u16 devid) |
297 | { | |
298 | struct iommu_dev_data *dev_data; | |
df3f7a6e | 299 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3b03bb74 JR |
300 | |
301 | dev_data = search_dev_data(devid); | |
302 | ||
df3f7a6e | 303 | if (dev_data == NULL) { |
3b03bb74 | 304 | dev_data = alloc_dev_data(devid); |
39ffe395 SAS |
305 | if (!dev_data) |
306 | return NULL; | |
3b03bb74 | 307 | |
df3f7a6e BH |
308 | if (translation_pre_enabled(iommu)) |
309 | dev_data->defer_attach = true; | |
310 | } | |
311 | ||
3b03bb74 JR |
312 | return dev_data; |
313 | } | |
314 | ||
daae2d25 | 315 | struct iommu_dev_data *get_dev_data(struct device *dev) |
657cbb6b JR |
316 | { |
317 | return dev->archdata.iommu; | |
318 | } | |
daae2d25 | 319 | EXPORT_SYMBOL(get_dev_data); |
657cbb6b | 320 | |
b097d11a WZ |
321 | /* |
322 | * Find or create an IOMMU group for a acpihid device. | |
323 | */ | |
324 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 325 | { |
b097d11a | 326 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 327 | int devid; |
b097d11a WZ |
328 | |
329 | devid = get_acpihid_device_id(dev, &entry); | |
330 | if (devid < 0) | |
331 | return ERR_PTR(devid); | |
332 | ||
333 | list_for_each_entry(p, &acpihid_map, list) { | |
334 | if ((devid == p->devid) && p->group) | |
335 | entry->group = p->group; | |
336 | } | |
337 | ||
338 | if (!entry->group) | |
339 | entry->group = generic_device_group(dev); | |
f2f101f6 RM |
340 | else |
341 | iommu_group_ref_get(entry->group); | |
b097d11a WZ |
342 | |
343 | return entry->group; | |
657cbb6b JR |
344 | } |
345 | ||
5abcdba4 JR |
346 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
347 | { | |
348 | static const int caps[] = { | |
349 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
350 | PCI_EXT_CAP_ID_PRI, |
351 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
352 | }; |
353 | int i, pos; | |
354 | ||
cef74409 GK |
355 | if (pci_ats_disabled()) |
356 | return false; | |
357 | ||
5abcdba4 JR |
358 | for (i = 0; i < 3; ++i) { |
359 | pos = pci_find_ext_capability(pdev, caps[i]); | |
360 | if (pos == 0) | |
361 | return false; | |
362 | } | |
363 | ||
364 | return true; | |
365 | } | |
366 | ||
6a113ddc JR |
367 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
368 | { | |
369 | struct iommu_dev_data *dev_data; | |
370 | ||
371 | dev_data = get_dev_data(&pdev->dev); | |
372 | ||
373 | return dev_data->errata & (1 << erratum) ? true : false; | |
374 | } | |
375 | ||
98fc5a69 JR |
376 | /* |
377 | * This function checks if the driver got a valid device from the caller to | |
378 | * avoid dereferencing invalid pointers. | |
379 | */ | |
380 | static bool check_device(struct device *dev) | |
381 | { | |
7aba6cb9 | 382 | int devid; |
98fc5a69 JR |
383 | |
384 | if (!dev || !dev->dma_mask) | |
385 | return false; | |
386 | ||
98fc5a69 | 387 | devid = get_device_id(dev); |
9ee35e4c | 388 | if (devid < 0) |
7aba6cb9 | 389 | return false; |
98fc5a69 JR |
390 | |
391 | /* Out of our scope? */ | |
392 | if (devid > amd_iommu_last_bdf) | |
393 | return false; | |
394 | ||
395 | if (amd_iommu_rlookup_table[devid] == NULL) | |
396 | return false; | |
397 | ||
398 | return true; | |
399 | } | |
400 | ||
25b11ce2 | 401 | static void init_iommu_group(struct device *dev) |
2851db21 | 402 | { |
2851db21 | 403 | struct iommu_group *group; |
2851db21 | 404 | |
65d5352f | 405 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
406 | if (IS_ERR(group)) |
407 | return; | |
408 | ||
0bb6e243 | 409 | iommu_group_put(group); |
eb9c9527 AW |
410 | } |
411 | ||
412 | static int iommu_init_device(struct device *dev) | |
413 | { | |
eb9c9527 | 414 | struct iommu_dev_data *dev_data; |
39ab9555 | 415 | struct amd_iommu *iommu; |
7aba6cb9 | 416 | int devid; |
eb9c9527 AW |
417 | |
418 | if (dev->archdata.iommu) | |
419 | return 0; | |
420 | ||
7aba6cb9 | 421 | devid = get_device_id(dev); |
9ee35e4c | 422 | if (devid < 0) |
7aba6cb9 WZ |
423 | return devid; |
424 | ||
39ab9555 JR |
425 | iommu = amd_iommu_rlookup_table[devid]; |
426 | ||
7aba6cb9 | 427 | dev_data = find_dev_data(devid); |
eb9c9527 AW |
428 | if (!dev_data) |
429 | return -ENOMEM; | |
430 | ||
e3156048 JR |
431 | dev_data->alias = get_alias(dev); |
432 | ||
c12b08eb YZ |
433 | /* |
434 | * By default we use passthrough mode for IOMMUv2 capable device. | |
435 | * But if amd_iommu=force_isolation is set (e.g. to debug DMA to | |
436 | * invalid address), we ignore the capability for the device so | |
437 | * it'll be forced to go into translation mode. | |
438 | */ | |
439 | if ((iommu_pass_through || !amd_iommu_force_isolation) && | |
440 | dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { | |
5abcdba4 JR |
441 | struct amd_iommu *iommu; |
442 | ||
2bf9a0a1 | 443 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
444 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
445 | } | |
446 | ||
657cbb6b JR |
447 | dev->archdata.iommu = dev_data; |
448 | ||
e3d10af1 | 449 | iommu_device_link(&iommu->iommu, dev); |
066f2e98 | 450 | |
657cbb6b JR |
451 | return 0; |
452 | } | |
453 | ||
26018874 JR |
454 | static void iommu_ignore_device(struct device *dev) |
455 | { | |
7aba6cb9 WZ |
456 | u16 alias; |
457 | int devid; | |
26018874 JR |
458 | |
459 | devid = get_device_id(dev); | |
9ee35e4c | 460 | if (devid < 0) |
7aba6cb9 WZ |
461 | return; |
462 | ||
e3156048 | 463 | alias = get_alias(dev); |
26018874 JR |
464 | |
465 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
466 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
467 | ||
468 | amd_iommu_rlookup_table[devid] = NULL; | |
469 | amd_iommu_rlookup_table[alias] = NULL; | |
470 | } | |
471 | ||
657cbb6b JR |
472 | static void iommu_uninit_device(struct device *dev) |
473 | { | |
7aba6cb9 | 474 | struct iommu_dev_data *dev_data; |
39ab9555 JR |
475 | struct amd_iommu *iommu; |
476 | int devid; | |
c1931090 | 477 | |
7aba6cb9 | 478 | devid = get_device_id(dev); |
9ee35e4c | 479 | if (devid < 0) |
7aba6cb9 | 480 | return; |
c1931090 | 481 | |
39ab9555 JR |
482 | iommu = amd_iommu_rlookup_table[devid]; |
483 | ||
7aba6cb9 | 484 | dev_data = search_dev_data(devid); |
c1931090 AW |
485 | if (!dev_data) |
486 | return; | |
487 | ||
b6809ee5 JR |
488 | if (dev_data->domain) |
489 | detach_device(dev); | |
490 | ||
e3d10af1 | 491 | iommu_device_unlink(&iommu->iommu, dev); |
066f2e98 | 492 | |
9dcd6130 AW |
493 | iommu_group_remove_device(dev); |
494 | ||
aafd8ba0 | 495 | /* Remove dma-ops */ |
5657933d | 496 | dev->dma_ops = NULL; |
aafd8ba0 | 497 | |
8fa5f802 | 498 | /* |
c1931090 AW |
499 | * We keep dev_data around for unplugged devices and reuse it when the |
500 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 501 | */ |
657cbb6b | 502 | } |
b7cc9554 | 503 | |
a80dc3e0 JR |
504 | /**************************************************************************** |
505 | * | |
506 | * Interrupt handling functions | |
507 | * | |
508 | ****************************************************************************/ | |
509 | ||
e3e59876 JR |
510 | static void dump_dte_entry(u16 devid) |
511 | { | |
512 | int i; | |
513 | ||
ee6c2868 | 514 | for (i = 0; i < 4; ++i) |
101fa037 | 515 | pr_err("DTE[%d]: %016llx\n", i, |
e3e59876 JR |
516 | amd_iommu_dev_table[devid].data[i]); |
517 | } | |
518 | ||
945b4ac4 JR |
519 | static void dump_command(unsigned long phys_addr) |
520 | { | |
2543a786 | 521 | struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr); |
945b4ac4 JR |
522 | int i; |
523 | ||
524 | for (i = 0; i < 4; ++i) | |
101fa037 | 525 | pr_err("CMD[%d]: %08x\n", i, cmd->data[i]); |
945b4ac4 JR |
526 | } |
527 | ||
30bf2df6 JR |
528 | static void amd_iommu_report_page_fault(u16 devid, u16 domain_id, |
529 | u64 address, int flags) | |
530 | { | |
531 | struct iommu_dev_data *dev_data = NULL; | |
532 | struct pci_dev *pdev; | |
533 | ||
d5bf0f4f SK |
534 | pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid), |
535 | devid & 0xff); | |
30bf2df6 JR |
536 | if (pdev) |
537 | dev_data = get_dev_data(&pdev->dev); | |
538 | ||
539 | if (dev_data && __ratelimit(&dev_data->rs)) { | |
5f226da1 | 540 | pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n", |
30bf2df6 JR |
541 | domain_id, address, flags); |
542 | } else if (printk_ratelimit()) { | |
6f5086a6 | 543 | pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n", |
30bf2df6 JR |
544 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
545 | domain_id, address, flags); | |
546 | } | |
547 | ||
548 | if (pdev) | |
549 | pci_dev_put(pdev); | |
550 | } | |
551 | ||
a345b23b | 552 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 553 | { |
90ca3859 | 554 | struct device *dev = iommu->iommu.dev; |
e7f63ffc | 555 | int type, devid, pasid, flags, tag; |
3d06fca8 JR |
556 | volatile u32 *event = __evt; |
557 | int count = 0; | |
558 | u64 address; | |
559 | ||
560 | retry: | |
561 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
562 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
d64c0486 | 563 | pasid = PPR_PASID(*(u64 *)&event[0]); |
3d06fca8 JR |
564 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; |
565 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
566 | ||
567 | if (type == 0) { | |
568 | /* Did we hit the erratum? */ | |
569 | if (++count == LOOP_TIMEOUT) { | |
101fa037 | 570 | pr_err("No event written to event log\n"); |
3d06fca8 JR |
571 | return; |
572 | } | |
573 | udelay(1); | |
574 | goto retry; | |
575 | } | |
90008ee4 | 576 | |
30bf2df6 | 577 | if (type == EVENT_TYPE_IO_FAULT) { |
d64c0486 | 578 | amd_iommu_report_page_fault(devid, pasid, address, flags); |
30bf2df6 | 579 | return; |
30bf2df6 | 580 | } |
90008ee4 JR |
581 | |
582 | switch (type) { | |
583 | case EVENT_TYPE_ILL_DEV: | |
6f5086a6 | 584 | dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", |
90ca3859 | 585 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
d64c0486 | 586 | pasid, address, flags); |
e3e59876 | 587 | dump_dte_entry(devid); |
90008ee4 | 588 | break; |
90008ee4 | 589 | case EVENT_TYPE_DEV_TAB_ERR: |
1a21ee1a | 590 | dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " |
6f5086a6 | 591 | "address=0x%llx flags=0x%04x]\n", |
90ca3859 GH |
592 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
593 | address, flags); | |
90008ee4 JR |
594 | break; |
595 | case EVENT_TYPE_PAGE_TAB_ERR: | |
6f5086a6 | 596 | dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n", |
90ca3859 | 597 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
d64c0486 | 598 | pasid, address, flags); |
90008ee4 JR |
599 | break; |
600 | case EVENT_TYPE_ILL_CMD: | |
6f5086a6 | 601 | dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address); |
945b4ac4 | 602 | dump_command(address); |
90008ee4 JR |
603 | break; |
604 | case EVENT_TYPE_CMD_HARD_ERR: | |
6f5086a6 | 605 | dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n", |
d64c0486 | 606 | address, flags); |
90008ee4 JR |
607 | break; |
608 | case EVENT_TYPE_IOTLB_INV_TO: | |
6f5086a6 | 609 | dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n", |
90ca3859 GH |
610 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
611 | address); | |
90008ee4 JR |
612 | break; |
613 | case EVENT_TYPE_INV_DEV_REQ: | |
6f5086a6 | 614 | dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", |
90ca3859 | 615 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
d64c0486 | 616 | pasid, address, flags); |
90008ee4 | 617 | break; |
e7f63ffc GH |
618 | case EVENT_TYPE_INV_PPR_REQ: |
619 | pasid = ((event[0] >> 16) & 0xFFFF) | |
620 | | ((event[1] << 6) & 0xF0000); | |
621 | tag = event[1] & 0x03FF; | |
c1ddcf1c | 622 | dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n", |
e7f63ffc | 623 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
c1ddcf1c | 624 | pasid, address, flags, tag); |
90008ee4 JR |
625 | break; |
626 | default: | |
1a21ee1a | 627 | dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n", |
90ca3859 | 628 | event[0], event[1], event[2], event[3]); |
90008ee4 | 629 | } |
3d06fca8 JR |
630 | |
631 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
632 | } |
633 | ||
634 | static void iommu_poll_events(struct amd_iommu *iommu) | |
635 | { | |
636 | u32 head, tail; | |
90008ee4 JR |
637 | |
638 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
639 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
640 | ||
641 | while (head != tail) { | |
a345b23b | 642 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 643 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
644 | } |
645 | ||
646 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
647 | } |
648 | ||
eee53537 | 649 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
650 | { |
651 | struct amd_iommu_fault fault; | |
72e1dcc4 | 652 | |
72e1dcc4 | 653 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
101fa037 | 654 | pr_err_ratelimited("Unknown PPR request received\n"); |
72e1dcc4 JR |
655 | return; |
656 | } | |
657 | ||
658 | fault.address = raw[1]; | |
659 | fault.pasid = PPR_PASID(raw[0]); | |
660 | fault.device_id = PPR_DEVID(raw[0]); | |
661 | fault.tag = PPR_TAG(raw[0]); | |
662 | fault.flags = PPR_FLAGS(raw[0]); | |
663 | ||
72e1dcc4 JR |
664 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
665 | } | |
666 | ||
667 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
668 | { | |
72e1dcc4 JR |
669 | u32 head, tail; |
670 | ||
671 | if (iommu->ppr_log == NULL) | |
672 | return; | |
673 | ||
72e1dcc4 JR |
674 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
675 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
676 | ||
677 | while (head != tail) { | |
eee53537 JR |
678 | volatile u64 *raw; |
679 | u64 entry[2]; | |
680 | int i; | |
681 | ||
682 | raw = (u64 *)(iommu->ppr_log + head); | |
683 | ||
684 | /* | |
685 | * Hardware bug: Interrupt may arrive before the entry is | |
686 | * written to memory. If this happens we need to wait for the | |
687 | * entry to arrive. | |
688 | */ | |
689 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
690 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
691 | break; | |
692 | udelay(1); | |
693 | } | |
72e1dcc4 | 694 | |
eee53537 JR |
695 | /* Avoid memcpy function-call overhead */ |
696 | entry[0] = raw[0]; | |
697 | entry[1] = raw[1]; | |
72e1dcc4 | 698 | |
eee53537 JR |
699 | /* |
700 | * To detect the hardware bug we need to clear the entry | |
701 | * back to zero. | |
702 | */ | |
703 | raw[0] = raw[1] = 0UL; | |
704 | ||
705 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
706 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
707 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 708 | |
eee53537 JR |
709 | /* Handle PPR entry */ |
710 | iommu_handle_ppr_entry(iommu, entry); | |
711 | ||
eee53537 JR |
712 | /* Refresh ring-buffer information */ |
713 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
714 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
715 | } | |
72e1dcc4 JR |
716 | } |
717 | ||
bd6fcefc SS |
718 | #ifdef CONFIG_IRQ_REMAP |
719 | static int (*iommu_ga_log_notifier)(u32); | |
720 | ||
721 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) | |
722 | { | |
723 | iommu_ga_log_notifier = notifier; | |
724 | ||
725 | return 0; | |
726 | } | |
727 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); | |
728 | ||
729 | static void iommu_poll_ga_log(struct amd_iommu *iommu) | |
730 | { | |
731 | u32 head, tail, cnt = 0; | |
732 | ||
733 | if (iommu->ga_log == NULL) | |
734 | return; | |
735 | ||
736 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
737 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); | |
738 | ||
739 | while (head != tail) { | |
740 | volatile u64 *raw; | |
741 | u64 log_entry; | |
742 | ||
743 | raw = (u64 *)(iommu->ga_log + head); | |
744 | cnt++; | |
745 | ||
746 | /* Avoid memcpy function-call overhead */ | |
747 | log_entry = *raw; | |
748 | ||
749 | /* Update head pointer of hardware ring-buffer */ | |
750 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; | |
751 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
752 | ||
753 | /* Handle GA entry */ | |
754 | switch (GA_REQ_TYPE(log_entry)) { | |
755 | case GA_GUEST_NR: | |
756 | if (!iommu_ga_log_notifier) | |
757 | break; | |
758 | ||
101fa037 | 759 | pr_debug("%s: devid=%#x, ga_tag=%#x\n", |
bd6fcefc SS |
760 | __func__, GA_DEVID(log_entry), |
761 | GA_TAG(log_entry)); | |
762 | ||
763 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) | |
101fa037 | 764 | pr_err("GA log notifier failed.\n"); |
bd6fcefc SS |
765 | break; |
766 | default: | |
767 | break; | |
768 | } | |
769 | } | |
770 | } | |
771 | #endif /* CONFIG_IRQ_REMAP */ | |
772 | ||
773 | #define AMD_IOMMU_INT_MASK \ | |
774 | (MMIO_STATUS_EVT_INT_MASK | \ | |
775 | MMIO_STATUS_PPR_INT_MASK | \ | |
776 | MMIO_STATUS_GALOG_INT_MASK) | |
777 | ||
72fe00f0 | 778 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 779 | { |
3f398bc7 SS |
780 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
781 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 782 | |
bd6fcefc SS |
783 | while (status & AMD_IOMMU_INT_MASK) { |
784 | /* Enable EVT and PPR and GA interrupts again */ | |
785 | writel(AMD_IOMMU_INT_MASK, | |
3f398bc7 | 786 | iommu->mmio_base + MMIO_STATUS_OFFSET); |
90008ee4 | 787 | |
3f398bc7 | 788 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
101fa037 | 789 | pr_devel("Processing IOMMU Event Log\n"); |
3f398bc7 SS |
790 | iommu_poll_events(iommu); |
791 | } | |
90008ee4 | 792 | |
3f398bc7 | 793 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
101fa037 | 794 | pr_devel("Processing IOMMU PPR Log\n"); |
3f398bc7 SS |
795 | iommu_poll_ppr_log(iommu); |
796 | } | |
90008ee4 | 797 | |
bd6fcefc SS |
798 | #ifdef CONFIG_IRQ_REMAP |
799 | if (status & MMIO_STATUS_GALOG_INT_MASK) { | |
101fa037 | 800 | pr_devel("Processing IOMMU GA Log\n"); |
bd6fcefc SS |
801 | iommu_poll_ga_log(iommu); |
802 | } | |
803 | #endif | |
804 | ||
3f398bc7 SS |
805 | /* |
806 | * Hardware bug: ERBT1312 | |
807 | * When re-enabling interrupt (by writing 1 | |
808 | * to clear the bit), the hardware might also try to set | |
809 | * the interrupt bit in the event status register. | |
810 | * In this scenario, the bit will be set, and disable | |
811 | * subsequent interrupts. | |
812 | * | |
813 | * Workaround: The IOMMU driver should read back the | |
814 | * status register and check if the interrupt bits are cleared. | |
815 | * If not, driver will need to go through the interrupt handler | |
816 | * again and re-clear the bits | |
817 | */ | |
818 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
819 | } | |
90008ee4 | 820 | return IRQ_HANDLED; |
a80dc3e0 JR |
821 | } |
822 | ||
72fe00f0 JR |
823 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
824 | { | |
825 | return IRQ_WAKE_THREAD; | |
826 | } | |
827 | ||
431b2a20 JR |
828 | /**************************************************************************** |
829 | * | |
830 | * IOMMU command queuing functions | |
831 | * | |
832 | ****************************************************************************/ | |
833 | ||
ac0ea6e9 JR |
834 | static int wait_on_sem(volatile u64 *sem) |
835 | { | |
836 | int i = 0; | |
837 | ||
838 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
839 | udelay(1); | |
840 | i += 1; | |
841 | } | |
842 | ||
843 | if (i == LOOP_TIMEOUT) { | |
101fa037 | 844 | pr_alert("Completion-Wait loop timed out\n"); |
ac0ea6e9 JR |
845 | return -EIO; |
846 | } | |
847 | ||
848 | return 0; | |
849 | } | |
850 | ||
851 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
d334a563 | 852 | struct iommu_cmd *cmd) |
a19ae1ec | 853 | { |
a19ae1ec JR |
854 | u8 *target; |
855 | ||
d334a563 TL |
856 | target = iommu->cmd_buf + iommu->cmd_buf_tail; |
857 | ||
858 | iommu->cmd_buf_tail += sizeof(*cmd); | |
859 | iommu->cmd_buf_tail %= CMD_BUFFER_SIZE; | |
ac0ea6e9 JR |
860 | |
861 | /* Copy command to buffer */ | |
862 | memcpy(target, cmd, sizeof(*cmd)); | |
863 | ||
864 | /* Tell the IOMMU about it */ | |
d334a563 | 865 | writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 866 | } |
a19ae1ec | 867 | |
815b33fd | 868 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 869 | { |
2543a786 TL |
870 | u64 paddr = iommu_virt_to_phys((void *)address); |
871 | ||
815b33fd JR |
872 | WARN_ON(address & 0x7ULL); |
873 | ||
ded46737 | 874 | memset(cmd, 0, sizeof(*cmd)); |
2543a786 TL |
875 | cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; |
876 | cmd->data[1] = upper_32_bits(paddr); | |
815b33fd | 877 | cmd->data[2] = 1; |
ded46737 JR |
878 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
879 | } | |
880 | ||
94fe79e2 JR |
881 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
882 | { | |
883 | memset(cmd, 0, sizeof(*cmd)); | |
884 | cmd->data[0] = devid; | |
885 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
886 | } | |
887 | ||
11b6402c JR |
888 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
889 | size_t size, u16 domid, int pde) | |
890 | { | |
891 | u64 pages; | |
ae0cbbb1 | 892 | bool s; |
11b6402c JR |
893 | |
894 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 895 | s = false; |
11b6402c JR |
896 | |
897 | if (pages > 1) { | |
898 | /* | |
899 | * If we have to flush more than one page, flush all | |
900 | * TLB entries for this domain | |
901 | */ | |
902 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 903 | s = true; |
11b6402c JR |
904 | } |
905 | ||
906 | address &= PAGE_MASK; | |
907 | ||
908 | memset(cmd, 0, sizeof(*cmd)); | |
909 | cmd->data[1] |= domid; | |
910 | cmd->data[2] = lower_32_bits(address); | |
911 | cmd->data[3] = upper_32_bits(address); | |
912 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
913 | if (s) /* size bit - we flush more than one 4kb page */ | |
914 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 915 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
916 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
917 | } | |
918 | ||
cb41ed85 JR |
919 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
920 | u64 address, size_t size) | |
921 | { | |
922 | u64 pages; | |
ae0cbbb1 | 923 | bool s; |
cb41ed85 JR |
924 | |
925 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 926 | s = false; |
cb41ed85 JR |
927 | |
928 | if (pages > 1) { | |
929 | /* | |
930 | * If we have to flush more than one page, flush all | |
931 | * TLB entries for this domain | |
932 | */ | |
933 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 934 | s = true; |
cb41ed85 JR |
935 | } |
936 | ||
937 | address &= PAGE_MASK; | |
938 | ||
939 | memset(cmd, 0, sizeof(*cmd)); | |
940 | cmd->data[0] = devid; | |
941 | cmd->data[0] |= (qdep & 0xff) << 24; | |
942 | cmd->data[1] = devid; | |
943 | cmd->data[2] = lower_32_bits(address); | |
944 | cmd->data[3] = upper_32_bits(address); | |
945 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
946 | if (s) | |
947 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
948 | } | |
949 | ||
22e266c7 JR |
950 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
951 | u64 address, bool size) | |
952 | { | |
953 | memset(cmd, 0, sizeof(*cmd)); | |
954 | ||
955 | address &= ~(0xfffULL); | |
956 | ||
a919a018 | 957 | cmd->data[0] = pasid; |
22e266c7 JR |
958 | cmd->data[1] = domid; |
959 | cmd->data[2] = lower_32_bits(address); | |
960 | cmd->data[3] = upper_32_bits(address); | |
961 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
962 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
963 | if (size) | |
964 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
965 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
966 | } | |
967 | ||
968 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
969 | int qdep, u64 address, bool size) | |
970 | { | |
971 | memset(cmd, 0, sizeof(*cmd)); | |
972 | ||
973 | address &= ~(0xfffULL); | |
974 | ||
975 | cmd->data[0] = devid; | |
e8d2d82d | 976 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
977 | cmd->data[0] |= (qdep & 0xff) << 24; |
978 | cmd->data[1] = devid; | |
e8d2d82d | 979 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
980 | cmd->data[2] = lower_32_bits(address); |
981 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
982 | cmd->data[3] = upper_32_bits(address); | |
983 | if (size) | |
984 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
985 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
986 | } | |
987 | ||
c99afa25 JR |
988 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
989 | int status, int tag, bool gn) | |
990 | { | |
991 | memset(cmd, 0, sizeof(*cmd)); | |
992 | ||
993 | cmd->data[0] = devid; | |
994 | if (gn) { | |
a919a018 | 995 | cmd->data[1] = pasid; |
c99afa25 JR |
996 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
997 | } | |
998 | cmd->data[3] = tag & 0x1ff; | |
999 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
1000 | ||
1001 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
1002 | } | |
1003 | ||
58fc7f14 JR |
1004 | static void build_inv_all(struct iommu_cmd *cmd) |
1005 | { | |
1006 | memset(cmd, 0, sizeof(*cmd)); | |
1007 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
1008 | } |
1009 | ||
7ef2798d JR |
1010 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
1011 | { | |
1012 | memset(cmd, 0, sizeof(*cmd)); | |
1013 | cmd->data[0] = devid; | |
1014 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1015 | } | |
1016 | ||
431b2a20 | 1017 | /* |
431b2a20 | 1018 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 1019 | * hardware about the new command. |
431b2a20 | 1020 | */ |
4bf5beef JR |
1021 | static int __iommu_queue_command_sync(struct amd_iommu *iommu, |
1022 | struct iommu_cmd *cmd, | |
1023 | bool sync) | |
a19ae1ec | 1024 | { |
23e967e1 | 1025 | unsigned int count = 0; |
d334a563 | 1026 | u32 left, next_tail; |
a19ae1ec | 1027 | |
d334a563 | 1028 | next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 | 1029 | again: |
d334a563 | 1030 | left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; |
a19ae1ec | 1031 | |
432abf68 | 1032 | if (left <= 0x20) { |
23e967e1 TL |
1033 | /* Skip udelay() the first time around */ |
1034 | if (count++) { | |
1035 | if (count == LOOP_TIMEOUT) { | |
101fa037 | 1036 | pr_err("Command buffer timeout\n"); |
23e967e1 TL |
1037 | return -EIO; |
1038 | } | |
da49f6df | 1039 | |
23e967e1 TL |
1040 | udelay(1); |
1041 | } | |
ac0ea6e9 | 1042 | |
23e967e1 TL |
1043 | /* Update head and recheck remaining space */ |
1044 | iommu->cmd_buf_head = readl(iommu->mmio_base + | |
1045 | MMIO_CMD_HEAD_OFFSET); | |
ac0ea6e9 JR |
1046 | |
1047 | goto again; | |
8d201968 JR |
1048 | } |
1049 | ||
d334a563 | 1050 | copy_cmd_to_buffer(iommu, cmd); |
ac0ea6e9 | 1051 | |
23e967e1 | 1052 | /* Do we need to make sure all commands are processed? */ |
f1ca1512 | 1053 | iommu->need_sync = sync; |
ac0ea6e9 | 1054 | |
4bf5beef JR |
1055 | return 0; |
1056 | } | |
1057 | ||
1058 | static int iommu_queue_command_sync(struct amd_iommu *iommu, | |
1059 | struct iommu_cmd *cmd, | |
1060 | bool sync) | |
1061 | { | |
1062 | unsigned long flags; | |
1063 | int ret; | |
1064 | ||
27790398 | 1065 | raw_spin_lock_irqsave(&iommu->lock, flags); |
4bf5beef | 1066 | ret = __iommu_queue_command_sync(iommu, cmd, sync); |
27790398 | 1067 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1068 | |
4bf5beef | 1069 | return ret; |
8d201968 JR |
1070 | } |
1071 | ||
f1ca1512 JR |
1072 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1073 | { | |
1074 | return iommu_queue_command_sync(iommu, cmd, true); | |
1075 | } | |
1076 | ||
8d201968 JR |
1077 | /* |
1078 | * This function queues a completion wait command into the command | |
1079 | * buffer of an IOMMU | |
1080 | */ | |
a19ae1ec | 1081 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1082 | { |
1083 | struct iommu_cmd cmd; | |
4bf5beef | 1084 | unsigned long flags; |
ac0ea6e9 | 1085 | int ret; |
8d201968 | 1086 | |
09ee17eb | 1087 | if (!iommu->need_sync) |
815b33fd | 1088 | return 0; |
09ee17eb | 1089 | |
a19ae1ec | 1090 | |
4bf5beef JR |
1091 | build_completion_wait(&cmd, (u64)&iommu->cmd_sem); |
1092 | ||
27790398 | 1093 | raw_spin_lock_irqsave(&iommu->lock, flags); |
4bf5beef JR |
1094 | |
1095 | iommu->cmd_sem = 0; | |
1096 | ||
1097 | ret = __iommu_queue_command_sync(iommu, &cmd, false); | |
a19ae1ec | 1098 | if (ret) |
4bf5beef JR |
1099 | goto out_unlock; |
1100 | ||
1101 | ret = wait_on_sem(&iommu->cmd_sem); | |
1102 | ||
1103 | out_unlock: | |
27790398 | 1104 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1105 | |
4bf5beef | 1106 | return ret; |
8d201968 JR |
1107 | } |
1108 | ||
d8c13085 | 1109 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1110 | { |
d8c13085 | 1111 | struct iommu_cmd cmd; |
a19ae1ec | 1112 | |
d8c13085 | 1113 | build_inv_dte(&cmd, devid); |
7e4f88da | 1114 | |
d8c13085 JR |
1115 | return iommu_queue_command(iommu, &cmd); |
1116 | } | |
09ee17eb | 1117 | |
0688a099 | 1118 | static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1119 | { |
1120 | u32 devid; | |
09ee17eb | 1121 | |
7d0c5cc5 JR |
1122 | for (devid = 0; devid <= 0xffff; ++devid) |
1123 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1124 | |
7d0c5cc5 JR |
1125 | iommu_completion_wait(iommu); |
1126 | } | |
84df8175 | 1127 | |
7d0c5cc5 JR |
1128 | /* |
1129 | * This function uses heavy locking and may disable irqs for some time. But | |
1130 | * this is no issue because it is only called during resume. | |
1131 | */ | |
0688a099 | 1132 | static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1133 | { |
1134 | u32 dom_id; | |
a19ae1ec | 1135 | |
7d0c5cc5 JR |
1136 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1137 | struct iommu_cmd cmd; | |
1138 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1139 | dom_id, 1); | |
1140 | iommu_queue_command(iommu, &cmd); | |
1141 | } | |
8eed9833 | 1142 | |
7d0c5cc5 | 1143 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1144 | } |
1145 | ||
0688a099 | 1146 | static void amd_iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1147 | { |
58fc7f14 | 1148 | struct iommu_cmd cmd; |
0518a3a4 | 1149 | |
58fc7f14 | 1150 | build_inv_all(&cmd); |
0518a3a4 | 1151 | |
58fc7f14 JR |
1152 | iommu_queue_command(iommu, &cmd); |
1153 | iommu_completion_wait(iommu); | |
1154 | } | |
1155 | ||
7ef2798d JR |
1156 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1157 | { | |
1158 | struct iommu_cmd cmd; | |
1159 | ||
1160 | build_inv_irt(&cmd, devid); | |
1161 | ||
1162 | iommu_queue_command(iommu, &cmd); | |
1163 | } | |
1164 | ||
0688a099 | 1165 | static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) |
7ef2798d JR |
1166 | { |
1167 | u32 devid; | |
1168 | ||
1169 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1170 | iommu_flush_irt(iommu, devid); | |
1171 | ||
1172 | iommu_completion_wait(iommu); | |
1173 | } | |
1174 | ||
7d0c5cc5 JR |
1175 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1176 | { | |
58fc7f14 | 1177 | if (iommu_feature(iommu, FEATURE_IA)) { |
0688a099 | 1178 | amd_iommu_flush_all(iommu); |
58fc7f14 | 1179 | } else { |
0688a099 JR |
1180 | amd_iommu_flush_dte_all(iommu); |
1181 | amd_iommu_flush_irt_all(iommu); | |
1182 | amd_iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
1183 | } |
1184 | } | |
1185 | ||
431b2a20 | 1186 | /* |
cb41ed85 | 1187 | * Command send function for flushing on-device TLB |
431b2a20 | 1188 | */ |
6c542047 JR |
1189 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1190 | u64 address, size_t size) | |
3fa43655 JR |
1191 | { |
1192 | struct amd_iommu *iommu; | |
b00d3bcf | 1193 | struct iommu_cmd cmd; |
cb41ed85 | 1194 | int qdep; |
3fa43655 | 1195 | |
ea61cddb JR |
1196 | qdep = dev_data->ats.qdep; |
1197 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1198 | |
ea61cddb | 1199 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1200 | |
1201 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1202 | } |
1203 | ||
431b2a20 | 1204 | /* |
431b2a20 | 1205 | * Command send function for invalidating a device table entry |
431b2a20 | 1206 | */ |
6c542047 | 1207 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1208 | { |
3fa43655 | 1209 | struct amd_iommu *iommu; |
e25bfb56 | 1210 | u16 alias; |
ee2fa743 | 1211 | int ret; |
a19ae1ec | 1212 | |
6c542047 | 1213 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1214 | alias = dev_data->alias; |
a19ae1ec | 1215 | |
f62dda66 | 1216 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1217 | if (!ret && alias != dev_data->devid) |
1218 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1219 | if (ret) |
1220 | return ret; | |
1221 | ||
ea61cddb | 1222 | if (dev_data->ats.enabled) |
6c542047 | 1223 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1224 | |
ee2fa743 | 1225 | return ret; |
a19ae1ec JR |
1226 | } |
1227 | ||
431b2a20 JR |
1228 | /* |
1229 | * TLB invalidation function which is called from the mapping functions. | |
1230 | * It invalidates a single PTE if the range to flush is within a single | |
1231 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1232 | */ | |
17b124bf JR |
1233 | static void __domain_flush_pages(struct protection_domain *domain, |
1234 | u64 address, size_t size, int pde) | |
a19ae1ec | 1235 | { |
cb41ed85 | 1236 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1237 | struct iommu_cmd cmd; |
1238 | int ret = 0, i; | |
a19ae1ec | 1239 | |
11b6402c | 1240 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1241 | |
6b9376e3 | 1242 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
6de8ad9b JR |
1243 | if (!domain->dev_iommu[i]) |
1244 | continue; | |
1245 | ||
1246 | /* | |
1247 | * Devices of this domain are behind this IOMMU | |
1248 | * We need a TLB flush | |
1249 | */ | |
11b6402c | 1250 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1251 | } |
1252 | ||
cb41ed85 | 1253 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1254 | |
ea61cddb | 1255 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1256 | continue; |
1257 | ||
6c542047 | 1258 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1259 | } |
1260 | ||
11b6402c | 1261 | WARN_ON(ret); |
6de8ad9b JR |
1262 | } |
1263 | ||
17b124bf JR |
1264 | static void domain_flush_pages(struct protection_domain *domain, |
1265 | u64 address, size_t size) | |
6de8ad9b | 1266 | { |
17b124bf | 1267 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1268 | } |
b6c02715 | 1269 | |
1c655773 | 1270 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1271 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1272 | { |
17b124bf | 1273 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1274 | } |
1275 | ||
42a49f96 | 1276 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1277 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1278 | { |
17b124bf | 1279 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1280 | } |
1281 | ||
17b124bf | 1282 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1283 | { |
17b124bf | 1284 | int i; |
18811f55 | 1285 | |
6b9376e3 | 1286 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
f1eae7c5 | 1287 | if (domain && !domain->dev_iommu[i]) |
17b124bf | 1288 | continue; |
bfd1be18 | 1289 | |
17b124bf JR |
1290 | /* |
1291 | * Devices of this domain are behind this IOMMU | |
1292 | * We need to wait for completion of all commands. | |
1293 | */ | |
1294 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1295 | } |
e394d72a JR |
1296 | } |
1297 | ||
5cd3f2e9 TM |
1298 | /* Flush the not present cache if it exists */ |
1299 | static void domain_flush_np_cache(struct protection_domain *domain, | |
1300 | dma_addr_t iova, size_t size) | |
1301 | { | |
1302 | if (unlikely(amd_iommu_np_cache)) { | |
1303 | domain_flush_pages(domain, iova, size); | |
1304 | domain_flush_complete(domain); | |
1305 | } | |
1306 | } | |
1307 | ||
b00d3bcf | 1308 | |
09b42804 | 1309 | /* |
b00d3bcf | 1310 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1311 | */ |
17b124bf | 1312 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1313 | { |
b00d3bcf | 1314 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1315 | |
b00d3bcf | 1316 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1317 | device_flush_dte(dev_data); |
a345b23b JR |
1318 | } |
1319 | ||
431b2a20 JR |
1320 | /**************************************************************************** |
1321 | * | |
1322 | * The functions below are used the create the page table mappings for | |
1323 | * unity mapped regions. | |
1324 | * | |
1325 | ****************************************************************************/ | |
1326 | ||
ac3a7092 JR |
1327 | static void free_page_list(struct page *freelist) |
1328 | { | |
1329 | while (freelist != NULL) { | |
1330 | unsigned long p = (unsigned long)page_address(freelist); | |
1331 | freelist = freelist->freelist; | |
1332 | free_page(p); | |
1333 | } | |
1334 | } | |
1335 | ||
1336 | static struct page *free_pt_page(unsigned long pt, struct page *freelist) | |
1337 | { | |
1338 | struct page *p = virt_to_page((void *)pt); | |
1339 | ||
1340 | p->freelist = freelist; | |
1341 | ||
1342 | return p; | |
1343 | } | |
1344 | ||
1345 | #define DEFINE_FREE_PT_FN(LVL, FN) \ | |
1346 | static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \ | |
1347 | { \ | |
1348 | unsigned long p; \ | |
1349 | u64 *pt; \ | |
1350 | int i; \ | |
1351 | \ | |
1352 | pt = (u64 *)__pt; \ | |
1353 | \ | |
1354 | for (i = 0; i < 512; ++i) { \ | |
1355 | /* PTE present? */ \ | |
1356 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1357 | continue; \ | |
1358 | \ | |
1359 | /* Large PTE? */ \ | |
1360 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1361 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1362 | continue; \ | |
1363 | \ | |
1364 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1365 | freelist = FN(p, freelist); \ | |
1366 | } \ | |
1367 | \ | |
1368 | return free_pt_page((unsigned long)pt, freelist); \ | |
1369 | } | |
1370 | ||
1371 | DEFINE_FREE_PT_FN(l2, free_pt_page) | |
1372 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1373 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1374 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1375 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1376 | ||
409afa44 JR |
1377 | static struct page *free_sub_pt(unsigned long root, int mode, |
1378 | struct page *freelist) | |
ac3a7092 | 1379 | { |
409afa44 | 1380 | switch (mode) { |
ac3a7092 | 1381 | case PAGE_MODE_NONE: |
69be8852 | 1382 | case PAGE_MODE_7_LEVEL: |
ac3a7092 JR |
1383 | break; |
1384 | case PAGE_MODE_1_LEVEL: | |
1385 | freelist = free_pt_page(root, freelist); | |
1386 | break; | |
1387 | case PAGE_MODE_2_LEVEL: | |
1388 | freelist = free_pt_l2(root, freelist); | |
1389 | break; | |
1390 | case PAGE_MODE_3_LEVEL: | |
1391 | freelist = free_pt_l3(root, freelist); | |
1392 | break; | |
1393 | case PAGE_MODE_4_LEVEL: | |
1394 | freelist = free_pt_l4(root, freelist); | |
1395 | break; | |
1396 | case PAGE_MODE_5_LEVEL: | |
1397 | freelist = free_pt_l5(root, freelist); | |
1398 | break; | |
1399 | case PAGE_MODE_6_LEVEL: | |
1400 | freelist = free_pt_l6(root, freelist); | |
1401 | break; | |
1402 | default: | |
1403 | BUG(); | |
1404 | } | |
1405 | ||
409afa44 JR |
1406 | return freelist; |
1407 | } | |
1408 | ||
1409 | static void free_pagetable(struct protection_domain *domain) | |
1410 | { | |
1411 | unsigned long root = (unsigned long)domain->pt_root; | |
1412 | struct page *freelist = NULL; | |
1413 | ||
69be8852 JR |
1414 | BUG_ON(domain->mode < PAGE_MODE_NONE || |
1415 | domain->mode > PAGE_MODE_6_LEVEL); | |
1416 | ||
409afa44 JR |
1417 | free_sub_pt(root, domain->mode, freelist); |
1418 | ||
ac3a7092 JR |
1419 | free_page_list(freelist); |
1420 | } | |
1421 | ||
308973d3 JR |
1422 | /* |
1423 | * This function is used to add another level to an IO page table. Adding | |
1424 | * another level increases the size of the address space by 9 bits to a size up | |
1425 | * to 64 bits. | |
1426 | */ | |
1427 | static bool increase_address_space(struct protection_domain *domain, | |
1428 | gfp_t gfp) | |
1429 | { | |
1430 | u64 *pte; | |
1431 | ||
1432 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1433 | /* address space already 64 bit large */ | |
1434 | return false; | |
1435 | ||
1436 | pte = (void *)get_zeroed_page(gfp); | |
1437 | if (!pte) | |
1438 | return false; | |
1439 | ||
1440 | *pte = PM_LEVEL_PDE(domain->mode, | |
2543a786 | 1441 | iommu_virt_to_phys(domain->pt_root)); |
308973d3 JR |
1442 | domain->pt_root = pte; |
1443 | domain->mode += 1; | |
1444 | domain->updated = true; | |
1445 | ||
1446 | return true; | |
1447 | } | |
1448 | ||
1449 | static u64 *alloc_pte(struct protection_domain *domain, | |
1450 | unsigned long address, | |
cbb9d729 | 1451 | unsigned long page_size, |
308973d3 JR |
1452 | u64 **pte_page, |
1453 | gfp_t gfp) | |
1454 | { | |
cbb9d729 | 1455 | int level, end_lvl; |
308973d3 | 1456 | u64 *pte, *page; |
cbb9d729 JR |
1457 | |
1458 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1459 | |
1460 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1461 | increase_address_space(domain, gfp); | |
1462 | ||
cbb9d729 JR |
1463 | level = domain->mode - 1; |
1464 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1465 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1466 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1467 | |
1468 | while (level > end_lvl) { | |
7bfa5bd2 | 1469 | u64 __pte, __npte; |
6d568ef9 | 1470 | int pte_level; |
7bfa5bd2 | 1471 | |
6d568ef9 JR |
1472 | __pte = *pte; |
1473 | pte_level = PM_PTE_LEVEL(__pte); | |
7bfa5bd2 | 1474 | |
6d568ef9 JR |
1475 | if (!IOMMU_PTE_PRESENT(__pte) || |
1476 | pte_level == PAGE_MODE_7_LEVEL) { | |
308973d3 JR |
1477 | page = (u64 *)get_zeroed_page(gfp); |
1478 | if (!page) | |
1479 | return NULL; | |
7bfa5bd2 | 1480 | |
2543a786 | 1481 | __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page)); |
7bfa5bd2 | 1482 | |
134414ff | 1483 | /* pte could have been changed somewhere. */ |
9db034d5 | 1484 | if (cmpxchg64(pte, __pte, __npte) != __pte) |
7bfa5bd2 | 1485 | free_page((unsigned long)page); |
9db034d5 | 1486 | else if (pte_level == PAGE_MODE_7_LEVEL) |
6d568ef9 | 1487 | domain->updated = true; |
9db034d5 JR |
1488 | |
1489 | continue; | |
308973d3 JR |
1490 | } |
1491 | ||
cbb9d729 | 1492 | /* No level skipping support yet */ |
6d568ef9 | 1493 | if (pte_level != level) |
cbb9d729 JR |
1494 | return NULL; |
1495 | ||
308973d3 JR |
1496 | level -= 1; |
1497 | ||
9db034d5 | 1498 | pte = IOMMU_PTE_PAGE(__pte); |
308973d3 JR |
1499 | |
1500 | if (pte_page && level == end_lvl) | |
1501 | *pte_page = pte; | |
1502 | ||
1503 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1504 | } | |
1505 | ||
1506 | return pte; | |
1507 | } | |
1508 | ||
1509 | /* | |
1510 | * This function checks if there is a PTE for a given dma address. If | |
1511 | * there is one, it returns the pointer to it. | |
1512 | */ | |
3039ca1b JR |
1513 | static u64 *fetch_pte(struct protection_domain *domain, |
1514 | unsigned long address, | |
1515 | unsigned long *page_size) | |
308973d3 JR |
1516 | { |
1517 | int level; | |
1518 | u64 *pte; | |
1519 | ||
4674686d | 1520 | *page_size = 0; |
1521 | ||
24cd7723 JR |
1522 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1523 | return NULL; | |
1524 | ||
3039ca1b JR |
1525 | level = domain->mode - 1; |
1526 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1527 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1528 | |
24cd7723 JR |
1529 | while (level > 0) { |
1530 | ||
1531 | /* Not Present */ | |
308973d3 JR |
1532 | if (!IOMMU_PTE_PRESENT(*pte)) |
1533 | return NULL; | |
1534 | ||
24cd7723 | 1535 | /* Large PTE */ |
3039ca1b JR |
1536 | if (PM_PTE_LEVEL(*pte) == 7 || |
1537 | PM_PTE_LEVEL(*pte) == 0) | |
1538 | break; | |
24cd7723 JR |
1539 | |
1540 | /* No level skipping support yet */ | |
1541 | if (PM_PTE_LEVEL(*pte) != level) | |
1542 | return NULL; | |
1543 | ||
308973d3 JR |
1544 | level -= 1; |
1545 | ||
24cd7723 | 1546 | /* Walk to the next level */ |
3039ca1b JR |
1547 | pte = IOMMU_PTE_PAGE(*pte); |
1548 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1549 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1550 | } | |
1551 | ||
1552 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1553 | unsigned long pte_mask; | |
1554 | ||
1555 | /* | |
1556 | * If we have a series of large PTEs, make | |
1557 | * sure to return a pointer to the first one. | |
1558 | */ | |
1559 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1560 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1561 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1562 | } |
1563 | ||
1564 | return pte; | |
1565 | } | |
1566 | ||
6f820bb9 JR |
1567 | static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist) |
1568 | { | |
1569 | unsigned long pt; | |
1570 | int mode; | |
1571 | ||
1572 | while (cmpxchg64(pte, pteval, 0) != pteval) { | |
1573 | pr_warn("AMD-Vi: IOMMU pte changed since we read it\n"); | |
1574 | pteval = *pte; | |
1575 | } | |
1576 | ||
1577 | if (!IOMMU_PTE_PRESENT(pteval)) | |
1578 | return freelist; | |
1579 | ||
1580 | pt = (unsigned long)IOMMU_PTE_PAGE(pteval); | |
1581 | mode = IOMMU_PTE_MODE(pteval); | |
1582 | ||
1583 | return free_sub_pt(pt, mode, freelist); | |
1584 | } | |
1585 | ||
431b2a20 JR |
1586 | /* |
1587 | * Generic mapping functions. It maps a physical address into a DMA | |
1588 | * address space. It allocates the page table pages if necessary. | |
1589 | * In the future it can be extended to a generic mapping function | |
1590 | * supporting all features of AMD IOMMU page tables like level skipping | |
1591 | * and full 64 bit address spaces. | |
1592 | */ | |
38e817fe JR |
1593 | static int iommu_map_page(struct protection_domain *dom, |
1594 | unsigned long bus_addr, | |
1595 | unsigned long phys_addr, | |
b911b89b | 1596 | unsigned long page_size, |
abdc5eb3 | 1597 | int prot, |
b911b89b | 1598 | gfp_t gfp) |
bd0e5211 | 1599 | { |
6f820bb9 | 1600 | struct page *freelist = NULL; |
8bda3092 | 1601 | u64 __pte, *pte; |
cbb9d729 | 1602 | int i, count; |
abdc5eb3 | 1603 | |
d4b03664 JR |
1604 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1605 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1606 | ||
bad1cac2 | 1607 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1608 | return -EINVAL; |
1609 | ||
d4b03664 | 1610 | count = PAGE_SIZE_PTE_COUNT(page_size); |
b911b89b | 1611 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); |
cbb9d729 | 1612 | |
63eaa75e ML |
1613 | if (!pte) |
1614 | return -ENOMEM; | |
1615 | ||
cbb9d729 | 1616 | for (i = 0; i < count; ++i) |
6f820bb9 JR |
1617 | freelist = free_clear_pte(&pte[i], pte[i], freelist); |
1618 | ||
1619 | if (freelist != NULL) | |
1620 | dom->updated = true; | |
bd0e5211 | 1621 | |
d4b03664 | 1622 | if (count > 1) { |
2543a786 | 1623 | __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size); |
07a80a6b | 1624 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
cbb9d729 | 1625 | } else |
4dfc2788 | 1626 | __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
bd0e5211 | 1627 | |
bd0e5211 JR |
1628 | if (prot & IOMMU_PROT_IR) |
1629 | __pte |= IOMMU_PTE_IR; | |
1630 | if (prot & IOMMU_PROT_IW) | |
1631 | __pte |= IOMMU_PTE_IW; | |
1632 | ||
cbb9d729 JR |
1633 | for (i = 0; i < count; ++i) |
1634 | pte[i] = __pte; | |
bd0e5211 | 1635 | |
04bfdd84 JR |
1636 | update_domain(dom); |
1637 | ||
6f820bb9 JR |
1638 | /* Everything flushed out, free pages now */ |
1639 | free_page_list(freelist); | |
1640 | ||
bd0e5211 JR |
1641 | return 0; |
1642 | } | |
1643 | ||
24cd7723 JR |
1644 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1645 | unsigned long bus_addr, | |
1646 | unsigned long page_size) | |
eb74ff6c | 1647 | { |
71b390e9 JR |
1648 | unsigned long long unmapped; |
1649 | unsigned long unmap_size; | |
24cd7723 JR |
1650 | u64 *pte; |
1651 | ||
1652 | BUG_ON(!is_power_of_2(page_size)); | |
1653 | ||
1654 | unmapped = 0; | |
eb74ff6c | 1655 | |
24cd7723 JR |
1656 | while (unmapped < page_size) { |
1657 | ||
71b390e9 JR |
1658 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1659 | ||
1660 | if (pte) { | |
1661 | int i, count; | |
1662 | ||
1663 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1664 | for (i = 0; i < count; i++) |
1665 | pte[i] = 0ULL; | |
1666 | } | |
1667 | ||
1668 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1669 | unmapped += unmap_size; | |
1670 | } | |
1671 | ||
60d0ca3c | 1672 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1673 | |
24cd7723 | 1674 | return unmapped; |
eb74ff6c | 1675 | } |
eb74ff6c | 1676 | |
431b2a20 JR |
1677 | /**************************************************************************** |
1678 | * | |
1679 | * The next functions belong to the address allocator for the dma_ops | |
2d4c515b | 1680 | * interface functions. |
431b2a20 JR |
1681 | * |
1682 | ****************************************************************************/ | |
d3086444 | 1683 | |
9cabe89b | 1684 | |
256e4621 JR |
1685 | static unsigned long dma_ops_alloc_iova(struct device *dev, |
1686 | struct dma_ops_domain *dma_dom, | |
1687 | unsigned int pages, u64 dma_mask) | |
384de729 | 1688 | { |
256e4621 | 1689 | unsigned long pfn = 0; |
384de729 | 1690 | |
256e4621 | 1691 | pages = __roundup_pow_of_two(pages); |
ccb50e03 | 1692 | |
256e4621 JR |
1693 | if (dma_mask > DMA_BIT_MASK(32)) |
1694 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, | |
538d5b33 | 1695 | IOVA_PFN(DMA_BIT_MASK(32)), false); |
7b5e25b8 | 1696 | |
256e4621 | 1697 | if (!pfn) |
538d5b33 TN |
1698 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, |
1699 | IOVA_PFN(dma_mask), true); | |
5f6bed50 | 1700 | |
256e4621 | 1701 | return (pfn << PAGE_SHIFT); |
384de729 JR |
1702 | } |
1703 | ||
256e4621 JR |
1704 | static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, |
1705 | unsigned long address, | |
1706 | unsigned int pages) | |
d3086444 | 1707 | { |
256e4621 JR |
1708 | pages = __roundup_pow_of_two(pages); |
1709 | address >>= PAGE_SHIFT; | |
384de729 | 1710 | |
256e4621 | 1711 | free_iova_fast(&dma_dom->iovad, address, pages); |
d3086444 JR |
1712 | } |
1713 | ||
431b2a20 JR |
1714 | /**************************************************************************** |
1715 | * | |
1716 | * The next functions belong to the domain allocation. A domain is | |
1717 | * allocated for every IOMMU as the default domain. If device isolation | |
1718 | * is enabled, every device get its own domain. The most important thing | |
1719 | * about domains is the page table mapping the DMA address space they | |
1720 | * contain. | |
1721 | * | |
1722 | ****************************************************************************/ | |
1723 | ||
ec487d1a JR |
1724 | static u16 domain_id_alloc(void) |
1725 | { | |
ec487d1a JR |
1726 | int id; |
1727 | ||
2bc00180 | 1728 | spin_lock(&pd_bitmap_lock); |
ec487d1a JR |
1729 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); |
1730 | BUG_ON(id == 0); | |
1731 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1732 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1733 | else | |
1734 | id = 0; | |
2bc00180 | 1735 | spin_unlock(&pd_bitmap_lock); |
ec487d1a JR |
1736 | |
1737 | return id; | |
1738 | } | |
1739 | ||
a2acfb75 JR |
1740 | static void domain_id_free(int id) |
1741 | { | |
2bc00180 | 1742 | spin_lock(&pd_bitmap_lock); |
a2acfb75 JR |
1743 | if (id > 0 && id < MAX_DOMAIN_ID) |
1744 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
2bc00180 | 1745 | spin_unlock(&pd_bitmap_lock); |
a2acfb75 | 1746 | } |
a2acfb75 | 1747 | |
b16137b1 JR |
1748 | static void free_gcr3_tbl_level1(u64 *tbl) |
1749 | { | |
1750 | u64 *ptr; | |
1751 | int i; | |
1752 | ||
1753 | for (i = 0; i < 512; ++i) { | |
1754 | if (!(tbl[i] & GCR3_VALID)) | |
1755 | continue; | |
1756 | ||
2543a786 | 1757 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1758 | |
1759 | free_page((unsigned long)ptr); | |
1760 | } | |
1761 | } | |
1762 | ||
1763 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1764 | { | |
1765 | u64 *ptr; | |
1766 | int i; | |
1767 | ||
1768 | for (i = 0; i < 512; ++i) { | |
1769 | if (!(tbl[i] & GCR3_VALID)) | |
1770 | continue; | |
1771 | ||
2543a786 | 1772 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1773 | |
1774 | free_gcr3_tbl_level1(ptr); | |
1775 | } | |
1776 | } | |
1777 | ||
52815b75 JR |
1778 | static void free_gcr3_table(struct protection_domain *domain) |
1779 | { | |
b16137b1 JR |
1780 | if (domain->glx == 2) |
1781 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1782 | else if (domain->glx == 1) | |
1783 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1784 | else |
1785 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1786 | |
52815b75 JR |
1787 | free_page((unsigned long)domain->gcr3_tbl); |
1788 | } | |
1789 | ||
fca6af6a JR |
1790 | static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom) |
1791 | { | |
fca6af6a JR |
1792 | domain_flush_tlb(&dom->domain); |
1793 | domain_flush_complete(&dom->domain); | |
fd62190a JR |
1794 | } |
1795 | ||
9003d618 | 1796 | static void iova_domain_flush_tlb(struct iova_domain *iovad) |
fd62190a | 1797 | { |
9003d618 | 1798 | struct dma_ops_domain *dom; |
fd62190a | 1799 | |
9003d618 | 1800 | dom = container_of(iovad, struct dma_ops_domain, iovad); |
fca6af6a JR |
1801 | |
1802 | dma_ops_domain_flush_tlb(dom); | |
fca6af6a JR |
1803 | } |
1804 | ||
431b2a20 JR |
1805 | /* |
1806 | * Free a domain, only used if something went wrong in the | |
1807 | * allocation path and we need to free an already allocated page table | |
1808 | */ | |
ec487d1a JR |
1809 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1810 | { | |
1811 | if (!dom) | |
1812 | return; | |
1813 | ||
2d4c515b | 1814 | put_iova_domain(&dom->iovad); |
ec487d1a | 1815 | |
2d4c515b | 1816 | free_pagetable(&dom->domain); |
ec487d1a | 1817 | |
c3db901c BH |
1818 | if (dom->domain.id) |
1819 | domain_id_free(dom->domain.id); | |
1820 | ||
ec487d1a JR |
1821 | kfree(dom); |
1822 | } | |
1823 | ||
431b2a20 JR |
1824 | /* |
1825 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1826 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1827 | * structures required for the dma_ops interface |
1828 | */ | |
87a64d52 | 1829 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1830 | { |
1831 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1832 | |
1833 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1834 | if (!dma_dom) | |
1835 | return NULL; | |
1836 | ||
7a5a566e | 1837 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1838 | goto free_dma_dom; |
7a5a566e | 1839 | |
ffec2197 | 1840 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; |
ec487d1a | 1841 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1842 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1843 | if (!dma_dom->domain.pt_root) |
1844 | goto free_dma_dom; | |
ec487d1a | 1845 | |
aa3ac946 | 1846 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN); |
307d5851 | 1847 | |
9003d618 | 1848 | if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL)) |
d4241a27 JR |
1849 | goto free_dma_dom; |
1850 | ||
9003d618 JR |
1851 | /* Initialize reserved ranges */ |
1852 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); | |
fca6af6a | 1853 | |
ec487d1a JR |
1854 | return dma_dom; |
1855 | ||
1856 | free_dma_dom: | |
1857 | dma_ops_domain_free(dma_dom); | |
1858 | ||
1859 | return NULL; | |
1860 | } | |
1861 | ||
5b28df6f JR |
1862 | /* |
1863 | * little helper function to check whether a given protection domain is a | |
1864 | * dma_ops domain | |
1865 | */ | |
1866 | static bool dma_ops_domain(struct protection_domain *domain) | |
1867 | { | |
1868 | return domain->flags & PD_DMA_OPS_MASK; | |
1869 | } | |
1870 | ||
ff18c4e5 GH |
1871 | static void set_dte_entry(u16 devid, struct protection_domain *domain, |
1872 | bool ats, bool ppr) | |
b20ac0d4 | 1873 | { |
132bd68f | 1874 | u64 pte_root = 0; |
ee6c2868 | 1875 | u64 flags = 0; |
863c74eb | 1876 | |
132bd68f | 1877 | if (domain->mode != PAGE_MODE_NONE) |
2543a786 | 1878 | pte_root = iommu_virt_to_phys(domain->pt_root); |
132bd68f | 1879 | |
38ddf41b JR |
1880 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1881 | << DEV_ENTRY_MODE_SHIFT; | |
07a80a6b | 1882 | pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV; |
b20ac0d4 | 1883 | |
ee6c2868 JR |
1884 | flags = amd_iommu_dev_table[devid].data[1]; |
1885 | ||
fd7b5535 JR |
1886 | if (ats) |
1887 | flags |= DTE_FLAG_IOTLB; | |
1888 | ||
ff18c4e5 GH |
1889 | if (ppr) { |
1890 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1891 | ||
1892 | if (iommu_feature(iommu, FEATURE_EPHSUP)) | |
1893 | pte_root |= 1ULL << DEV_ENTRY_PPR; | |
1894 | } | |
1895 | ||
52815b75 | 1896 | if (domain->flags & PD_IOMMUV2_MASK) { |
2543a786 | 1897 | u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); |
52815b75 JR |
1898 | u64 glx = domain->glx; |
1899 | u64 tmp; | |
1900 | ||
1901 | pte_root |= DTE_FLAG_GV; | |
1902 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1903 | ||
1904 | /* First mask out possible old values for GCR3 table */ | |
1905 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1906 | flags &= ~tmp; | |
1907 | ||
1908 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1909 | flags &= ~tmp; | |
1910 | ||
1911 | /* Encode GCR3 table into DTE */ | |
1912 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1913 | pte_root |= tmp; | |
1914 | ||
1915 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1916 | flags |= tmp; | |
1917 | ||
1918 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1919 | flags |= tmp; | |
1920 | } | |
1921 | ||
45a01c42 | 1922 | flags &= ~DEV_DOMID_MASK; |
ee6c2868 JR |
1923 | flags |= domain->id; |
1924 | ||
1925 | amd_iommu_dev_table[devid].data[1] = flags; | |
1926 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1927 | } |
1928 | ||
1929 | static void clear_dte_entry(u16 devid) | |
1930 | { | |
15898bbc | 1931 | /* remove entry from the device table seen by the hardware */ |
07a80a6b | 1932 | amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV; |
cbf3ccd0 | 1933 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; |
15898bbc JR |
1934 | |
1935 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1936 | } |
1937 | ||
ec9e79ef JR |
1938 | static void do_attach(struct iommu_dev_data *dev_data, |
1939 | struct protection_domain *domain) | |
7f760ddd | 1940 | { |
7f760ddd | 1941 | struct amd_iommu *iommu; |
e25bfb56 | 1942 | u16 alias; |
ec9e79ef | 1943 | bool ats; |
fd7b5535 | 1944 | |
ec9e79ef | 1945 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1946 | alias = dev_data->alias; |
ec9e79ef | 1947 | ats = dev_data->ats.enabled; |
7f760ddd JR |
1948 | |
1949 | /* Update data structures */ | |
1950 | dev_data->domain = domain; | |
1951 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
1952 | |
1953 | /* Do reference counting */ | |
1954 | domain->dev_iommu[iommu->index] += 1; | |
1955 | domain->dev_cnt += 1; | |
1956 | ||
e25bfb56 | 1957 | /* Update device table */ |
ff18c4e5 | 1958 | set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2); |
e25bfb56 | 1959 | if (alias != dev_data->devid) |
ff18c4e5 | 1960 | set_dte_entry(alias, domain, ats, dev_data->iommu_v2); |
e25bfb56 | 1961 | |
6c542047 | 1962 | device_flush_dte(dev_data); |
7f760ddd JR |
1963 | } |
1964 | ||
ec9e79ef | 1965 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1966 | { |
9825bd94 | 1967 | struct protection_domain *domain = dev_data->domain; |
7f760ddd | 1968 | struct amd_iommu *iommu; |
e25bfb56 | 1969 | u16 alias; |
7f760ddd | 1970 | |
ec9e79ef | 1971 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1972 | alias = dev_data->alias; |
15898bbc | 1973 | |
7f760ddd JR |
1974 | /* Update data structures */ |
1975 | dev_data->domain = NULL; | |
1976 | list_del(&dev_data->list); | |
f62dda66 | 1977 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
1978 | if (alias != dev_data->devid) |
1979 | clear_dte_entry(alias); | |
15898bbc | 1980 | |
7f760ddd | 1981 | /* Flush the DTE entry */ |
6c542047 | 1982 | device_flush_dte(dev_data); |
9825bd94 SS |
1983 | |
1984 | /* Flush IOTLB */ | |
1985 | domain_flush_tlb_pde(domain); | |
1986 | ||
1987 | /* Wait for the flushes to finish */ | |
1988 | domain_flush_complete(domain); | |
1989 | ||
1990 | /* decrease reference counters - needs to happen after the flushes */ | |
1991 | domain->dev_iommu[iommu->index] -= 1; | |
1992 | domain->dev_cnt -= 1; | |
2b681faf JR |
1993 | } |
1994 | ||
1995 | /* | |
29a0c415 AMG |
1996 | * If a device is not yet associated with a domain, this function makes the |
1997 | * device visible in the domain | |
2b681faf | 1998 | */ |
ec9e79ef | 1999 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2000 | struct protection_domain *domain) |
2b681faf | 2001 | { |
84fe6c19 | 2002 | int ret; |
657cbb6b | 2003 | |
2b681faf JR |
2004 | /* lock domain */ |
2005 | spin_lock(&domain->lock); | |
2006 | ||
397111ab | 2007 | ret = -EBUSY; |
150952f9 | 2008 | if (dev_data->domain != NULL) |
397111ab | 2009 | goto out_unlock; |
15898bbc | 2010 | |
397111ab | 2011 | /* Attach alias group root */ |
150952f9 | 2012 | do_attach(dev_data, domain); |
24100055 | 2013 | |
84fe6c19 JL |
2014 | ret = 0; |
2015 | ||
2016 | out_unlock: | |
2017 | ||
eba6ac60 JR |
2018 | /* ready */ |
2019 | spin_unlock(&domain->lock); | |
15898bbc | 2020 | |
84fe6c19 | 2021 | return ret; |
0feae533 | 2022 | } |
b20ac0d4 | 2023 | |
52815b75 JR |
2024 | |
2025 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2026 | { | |
2027 | pci_disable_ats(pdev); | |
2028 | pci_disable_pri(pdev); | |
2029 | pci_disable_pasid(pdev); | |
2030 | } | |
2031 | ||
6a113ddc JR |
2032 | /* FIXME: Change generic reset-function to do the same */ |
2033 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2034 | { | |
2035 | u16 control; | |
2036 | int pos; | |
2037 | ||
46277b75 | 2038 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2039 | if (!pos) |
2040 | return -EINVAL; | |
2041 | ||
46277b75 JR |
2042 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2043 | control |= PCI_PRI_CTRL_RESET; | |
2044 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2045 | |
2046 | return 0; | |
2047 | } | |
2048 | ||
52815b75 JR |
2049 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2050 | { | |
6a113ddc JR |
2051 | bool reset_enable; |
2052 | int reqs, ret; | |
2053 | ||
2054 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2055 | reqs = 32; | |
2056 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2057 | reqs = 1; | |
2058 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2059 | |
2060 | /* Only allow access to user-accessible pages */ | |
2061 | ret = pci_enable_pasid(pdev, 0); | |
2062 | if (ret) | |
2063 | goto out_err; | |
2064 | ||
2065 | /* First reset the PRI state of the device */ | |
2066 | ret = pci_reset_pri(pdev); | |
2067 | if (ret) | |
2068 | goto out_err; | |
2069 | ||
6a113ddc JR |
2070 | /* Enable PRI */ |
2071 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2072 | if (ret) |
2073 | goto out_err; | |
2074 | ||
6a113ddc JR |
2075 | if (reset_enable) { |
2076 | ret = pri_reset_while_enabled(pdev); | |
2077 | if (ret) | |
2078 | goto out_err; | |
2079 | } | |
2080 | ||
52815b75 JR |
2081 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2082 | if (ret) | |
2083 | goto out_err; | |
2084 | ||
2085 | return 0; | |
2086 | ||
2087 | out_err: | |
2088 | pci_disable_pri(pdev); | |
2089 | pci_disable_pasid(pdev); | |
2090 | ||
2091 | return ret; | |
2092 | } | |
2093 | ||
407d733e | 2094 | /* |
29a0c415 AMG |
2095 | * If a device is not yet associated with a domain, this function makes the |
2096 | * device visible in the domain | |
407d733e | 2097 | */ |
15898bbc JR |
2098 | static int attach_device(struct device *dev, |
2099 | struct protection_domain *domain) | |
0feae533 | 2100 | { |
2bf9a0a1 | 2101 | struct pci_dev *pdev; |
ea61cddb | 2102 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2103 | unsigned long flags; |
15898bbc | 2104 | int ret; |
eba6ac60 | 2105 | |
ea61cddb JR |
2106 | dev_data = get_dev_data(dev); |
2107 | ||
2bf9a0a1 WZ |
2108 | if (!dev_is_pci(dev)) |
2109 | goto skip_ats_check; | |
2110 | ||
2111 | pdev = to_pci_dev(dev); | |
52815b75 | 2112 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2113 | if (!dev_data->passthrough) |
52815b75 JR |
2114 | return -EINVAL; |
2115 | ||
02ca2021 JR |
2116 | if (dev_data->iommu_v2) { |
2117 | if (pdev_iommuv2_enable(pdev) != 0) | |
2118 | return -EINVAL; | |
52815b75 | 2119 | |
02ca2021 JR |
2120 | dev_data->ats.enabled = true; |
2121 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
83d18bdf | 2122 | dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev); |
02ca2021 | 2123 | } |
52815b75 JR |
2124 | } else if (amd_iommu_iotlb_sup && |
2125 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2126 | dev_data->ats.enabled = true; |
2127 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2128 | } | |
fd7b5535 | 2129 | |
2bf9a0a1 | 2130 | skip_ats_check: |
2cd1083d | 2131 | spin_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2132 | ret = __attach_device(dev_data, domain); |
2cd1083d | 2133 | spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
b20ac0d4 | 2134 | |
0feae533 JR |
2135 | /* |
2136 | * We might boot into a crash-kernel here. The crashed kernel | |
2137 | * left the caches in the IOMMU dirty. So we have to flush | |
2138 | * here to evict all dirty stuff. | |
2139 | */ | |
17b124bf | 2140 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2141 | |
2142 | return ret; | |
b20ac0d4 JR |
2143 | } |
2144 | ||
355bf553 JR |
2145 | /* |
2146 | * Removes a device from a protection domain (unlocked) | |
2147 | */ | |
ec9e79ef | 2148 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2149 | { |
2ca76279 | 2150 | struct protection_domain *domain; |
c4596114 | 2151 | |
2ca76279 | 2152 | domain = dev_data->domain; |
71f77580 | 2153 | |
f1dd0a8b | 2154 | spin_lock(&domain->lock); |
24100055 | 2155 | |
150952f9 | 2156 | do_detach(dev_data); |
7f760ddd | 2157 | |
f1dd0a8b | 2158 | spin_unlock(&domain->lock); |
355bf553 JR |
2159 | } |
2160 | ||
2161 | /* | |
2162 | * Removes a device from a protection domain (with devtable_lock held) | |
2163 | */ | |
15898bbc | 2164 | static void detach_device(struct device *dev) |
355bf553 | 2165 | { |
52815b75 | 2166 | struct protection_domain *domain; |
ea61cddb | 2167 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2168 | unsigned long flags; |
2169 | ||
ec9e79ef | 2170 | dev_data = get_dev_data(dev); |
52815b75 | 2171 | domain = dev_data->domain; |
ec9e79ef | 2172 | |
ea3fd040 AMG |
2173 | /* |
2174 | * First check if the device is still attached. It might already | |
2175 | * be detached from its domain because the generic | |
2176 | * iommu_detach_group code detached it and we try again here in | |
2177 | * our alias handling. | |
2178 | */ | |
2179 | if (WARN_ON(!dev_data->domain)) | |
2180 | return; | |
2181 | ||
355bf553 | 2182 | /* lock device table */ |
2cd1083d | 2183 | spin_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2184 | __detach_device(dev_data); |
2cd1083d | 2185 | spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2186 | |
2bf9a0a1 WZ |
2187 | if (!dev_is_pci(dev)) |
2188 | return; | |
2189 | ||
02ca2021 | 2190 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2191 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2192 | else if (dev_data->ats.enabled) | |
ea61cddb | 2193 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2194 | |
2195 | dev_data->ats.enabled = false; | |
355bf553 | 2196 | } |
e275a2a0 | 2197 | |
aafd8ba0 | 2198 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2199 | { |
5abcdba4 | 2200 | struct iommu_dev_data *dev_data; |
07ee8694 | 2201 | struct iommu_domain *domain; |
e275a2a0 | 2202 | struct amd_iommu *iommu; |
7aba6cb9 | 2203 | int ret, devid; |
e275a2a0 | 2204 | |
aafd8ba0 | 2205 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2206 | return 0; |
e275a2a0 | 2207 | |
aafd8ba0 | 2208 | devid = get_device_id(dev); |
9ee35e4c | 2209 | if (devid < 0) |
7aba6cb9 WZ |
2210 | return devid; |
2211 | ||
aafd8ba0 | 2212 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2213 | |
aafd8ba0 | 2214 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2215 | if (ret) { |
2216 | if (ret != -ENOTSUPP) | |
5f226da1 | 2217 | dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); |
657cbb6b | 2218 | |
aafd8ba0 | 2219 | iommu_ignore_device(dev); |
356da6d0 | 2220 | dev->dma_ops = NULL; |
aafd8ba0 JR |
2221 | goto out; |
2222 | } | |
2223 | init_iommu_group(dev); | |
2c9195e9 | 2224 | |
07ee8694 | 2225 | dev_data = get_dev_data(dev); |
2c9195e9 | 2226 | |
4d58b8a6 | 2227 | BUG_ON(!dev_data); |
657cbb6b | 2228 | |
1e6a7b04 | 2229 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2230 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2231 | |
07ee8694 JR |
2232 | /* Domains are initialized for this device - have a look what we ended up with */ |
2233 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2234 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2235 | dev_data->passthrough = true; |
32302324 | 2236 | else |
5657933d | 2237 | dev->dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2238 | |
aafd8ba0 | 2239 | out: |
e275a2a0 JR |
2240 | iommu_completion_wait(iommu); |
2241 | ||
e275a2a0 JR |
2242 | return 0; |
2243 | } | |
2244 | ||
aafd8ba0 | 2245 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2246 | { |
aafd8ba0 | 2247 | struct amd_iommu *iommu; |
7aba6cb9 | 2248 | int devid; |
aafd8ba0 JR |
2249 | |
2250 | if (!check_device(dev)) | |
2251 | return; | |
2252 | ||
2253 | devid = get_device_id(dev); | |
9ee35e4c | 2254 | if (devid < 0) |
7aba6cb9 WZ |
2255 | return; |
2256 | ||
aafd8ba0 JR |
2257 | iommu = amd_iommu_rlookup_table[devid]; |
2258 | ||
2259 | iommu_uninit_device(dev); | |
2260 | iommu_completion_wait(iommu); | |
8638c491 JR |
2261 | } |
2262 | ||
b097d11a WZ |
2263 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2264 | { | |
2265 | if (dev_is_pci(dev)) | |
2266 | return pci_device_group(dev); | |
2267 | ||
2268 | return acpihid_device_group(dev); | |
2269 | } | |
2270 | ||
431b2a20 JR |
2271 | /***************************************************************************** |
2272 | * | |
2273 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2274 | * | |
2275 | *****************************************************************************/ | |
2276 | ||
2277 | /* | |
2278 | * In the dma_ops path we only have the struct device. This function | |
2279 | * finds the corresponding IOMMU, the protection domain and the | |
2280 | * requestor id for a given device. | |
2281 | * If the device is not yet associated with a domain this is also done | |
2282 | * in this function. | |
2283 | */ | |
94f6d190 | 2284 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2285 | { |
94f6d190 | 2286 | struct protection_domain *domain; |
df3f7a6e | 2287 | struct iommu_domain *io_domain; |
b20ac0d4 | 2288 | |
f99c0f1c | 2289 | if (!check_device(dev)) |
94f6d190 | 2290 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2291 | |
d26592a9 | 2292 | domain = get_dev_data(dev)->domain; |
df3f7a6e BH |
2293 | if (domain == NULL && get_dev_data(dev)->defer_attach) { |
2294 | get_dev_data(dev)->defer_attach = false; | |
2295 | io_domain = iommu_get_domain_for_dev(dev); | |
2296 | domain = to_pdomain(io_domain); | |
2297 | attach_device(dev, domain); | |
2298 | } | |
ec62b1ab BH |
2299 | if (domain == NULL) |
2300 | return ERR_PTR(-EBUSY); | |
2301 | ||
0bb6e243 | 2302 | if (!dma_ops_domain(domain)) |
94f6d190 | 2303 | return ERR_PTR(-EBUSY); |
f91ba190 | 2304 | |
0bb6e243 | 2305 | return domain; |
b20ac0d4 JR |
2306 | } |
2307 | ||
04bfdd84 JR |
2308 | static void update_device_table(struct protection_domain *domain) |
2309 | { | |
492667da | 2310 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2311 | |
3254de6b | 2312 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
ff18c4e5 GH |
2313 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled, |
2314 | dev_data->iommu_v2); | |
3254de6b JR |
2315 | |
2316 | if (dev_data->devid == dev_data->alias) | |
2317 | continue; | |
2318 | ||
2319 | /* There is an alias, update device table entry for it */ | |
ff18c4e5 GH |
2320 | set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled, |
2321 | dev_data->iommu_v2); | |
3254de6b | 2322 | } |
04bfdd84 JR |
2323 | } |
2324 | ||
2325 | static void update_domain(struct protection_domain *domain) | |
2326 | { | |
2327 | if (!domain->updated) | |
2328 | return; | |
2329 | ||
2330 | update_device_table(domain); | |
17b124bf JR |
2331 | |
2332 | domain_flush_devices(domain); | |
2333 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2334 | |
2335 | domain->updated = false; | |
2336 | } | |
2337 | ||
f37f7f33 JR |
2338 | static int dir2prot(enum dma_data_direction direction) |
2339 | { | |
2340 | if (direction == DMA_TO_DEVICE) | |
2341 | return IOMMU_PROT_IR; | |
2342 | else if (direction == DMA_FROM_DEVICE) | |
2343 | return IOMMU_PROT_IW; | |
2344 | else if (direction == DMA_BIDIRECTIONAL) | |
2345 | return IOMMU_PROT_IW | IOMMU_PROT_IR; | |
2346 | else | |
2347 | return 0; | |
2348 | } | |
daae2d25 | 2349 | |
431b2a20 JR |
2350 | /* |
2351 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2352 | * contiguous memory region into DMA address space. It is used by all |
2353 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2354 | * Must be called with the domain lock held. |
2355 | */ | |
cb76c322 | 2356 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2357 | struct dma_ops_domain *dma_dom, |
2358 | phys_addr_t paddr, | |
2359 | size_t size, | |
f37f7f33 | 2360 | enum dma_data_direction direction, |
832a90c3 | 2361 | u64 dma_mask) |
cb76c322 JR |
2362 | { |
2363 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2364 | dma_addr_t address, start, ret; |
cb76c322 | 2365 | unsigned int pages; |
518d9b45 | 2366 | int prot = 0; |
cb76c322 JR |
2367 | int i; |
2368 | ||
e3c449f5 | 2369 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2370 | paddr &= PAGE_MASK; |
2371 | ||
256e4621 | 2372 | address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask); |
b3aa14f0 | 2373 | if (!address) |
266a3bd2 | 2374 | goto out; |
cb76c322 | 2375 | |
f37f7f33 | 2376 | prot = dir2prot(direction); |
518d9b45 | 2377 | |
cb76c322 JR |
2378 | start = address; |
2379 | for (i = 0; i < pages; ++i) { | |
518d9b45 JR |
2380 | ret = iommu_map_page(&dma_dom->domain, start, paddr, |
2381 | PAGE_SIZE, prot, GFP_ATOMIC); | |
2382 | if (ret) | |
53812c11 JR |
2383 | goto out_unmap; |
2384 | ||
cb76c322 JR |
2385 | paddr += PAGE_SIZE; |
2386 | start += PAGE_SIZE; | |
2387 | } | |
2388 | address += offset; | |
2389 | ||
5cd3f2e9 | 2390 | domain_flush_np_cache(&dma_dom->domain, address, size); |
270cab24 | 2391 | |
cb76c322 JR |
2392 | out: |
2393 | return address; | |
53812c11 JR |
2394 | |
2395 | out_unmap: | |
2396 | ||
2397 | for (--i; i >= 0; --i) { | |
2398 | start -= PAGE_SIZE; | |
518d9b45 | 2399 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
53812c11 JR |
2400 | } |
2401 | ||
256e4621 JR |
2402 | domain_flush_tlb(&dma_dom->domain); |
2403 | domain_flush_complete(&dma_dom->domain); | |
2404 | ||
2405 | dma_ops_free_iova(dma_dom, address, pages); | |
53812c11 | 2406 | |
b3aa14f0 | 2407 | return DMA_MAPPING_ERROR; |
cb76c322 JR |
2408 | } |
2409 | ||
431b2a20 JR |
2410 | /* |
2411 | * Does the reverse of the __map_single function. Must be called with | |
2412 | * the domain lock held too | |
2413 | */ | |
cd8c82e8 | 2414 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2415 | dma_addr_t dma_addr, |
2416 | size_t size, | |
2417 | int dir) | |
2418 | { | |
2419 | dma_addr_t i, start; | |
2420 | unsigned int pages; | |
2421 | ||
e3c449f5 | 2422 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2423 | dma_addr &= PAGE_MASK; |
2424 | start = dma_addr; | |
2425 | ||
2426 | for (i = 0; i < pages; ++i) { | |
518d9b45 | 2427 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
cb76c322 JR |
2428 | start += PAGE_SIZE; |
2429 | } | |
2430 | ||
b1516a14 | 2431 | if (amd_iommu_unmap_flush) { |
b1516a14 JR |
2432 | domain_flush_tlb(&dma_dom->domain); |
2433 | domain_flush_complete(&dma_dom->domain); | |
3c120143 | 2434 | dma_ops_free_iova(dma_dom, dma_addr, pages); |
b1516a14 | 2435 | } else { |
9003d618 JR |
2436 | pages = __roundup_pow_of_two(pages); |
2437 | queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0); | |
b1516a14 | 2438 | } |
cb76c322 JR |
2439 | } |
2440 | ||
431b2a20 JR |
2441 | /* |
2442 | * The exported map_single function for dma_ops. | |
2443 | */ | |
51491367 FT |
2444 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2445 | unsigned long offset, size_t size, | |
2446 | enum dma_data_direction dir, | |
00085f1e | 2447 | unsigned long attrs) |
4da70b9e | 2448 | { |
92d420ec | 2449 | phys_addr_t paddr = page_to_phys(page) + offset; |
89736a0e JR |
2450 | struct protection_domain *domain; |
2451 | struct dma_ops_domain *dma_dom; | |
2452 | u64 dma_mask; | |
2453 | ||
2454 | domain = get_domain(dev); | |
2455 | if (PTR_ERR(domain) == -EINVAL) | |
2456 | return (dma_addr_t)paddr; | |
2457 | else if (IS_ERR(domain)) | |
2458 | return DMA_MAPPING_ERROR; | |
2459 | ||
2460 | dma_mask = *dev->dma_mask; | |
2461 | dma_dom = to_dma_ops_domain(domain); | |
f99c0f1c | 2462 | |
89736a0e | 2463 | return __map_single(dev, dma_dom, paddr, size, dir, dma_mask); |
4da70b9e JR |
2464 | } |
2465 | ||
431b2a20 JR |
2466 | /* |
2467 | * The exported unmap_single function for dma_ops. | |
2468 | */ | |
51491367 | 2469 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
00085f1e | 2470 | enum dma_data_direction dir, unsigned long attrs) |
4da70b9e | 2471 | { |
89736a0e JR |
2472 | struct protection_domain *domain; |
2473 | struct dma_ops_domain *dma_dom; | |
2474 | ||
2475 | domain = get_domain(dev); | |
2476 | if (IS_ERR(domain)) | |
2477 | return; | |
2478 | ||
2479 | dma_dom = to_dma_ops_domain(domain); | |
b3311b06 JR |
2480 | |
2481 | __unmap_single(dma_dom, dma_addr, size, dir); | |
4da70b9e JR |
2482 | } |
2483 | ||
80187fd3 JR |
2484 | static int sg_num_pages(struct device *dev, |
2485 | struct scatterlist *sglist, | |
2486 | int nelems) | |
2487 | { | |
2488 | unsigned long mask, boundary_size; | |
2489 | struct scatterlist *s; | |
2490 | int i, npages = 0; | |
2491 | ||
2492 | mask = dma_get_seg_boundary(dev); | |
2493 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
2494 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
2495 | ||
2496 | for_each_sg(sglist, s, nelems, i) { | |
2497 | int p, n; | |
2498 | ||
2499 | s->dma_address = npages << PAGE_SHIFT; | |
2500 | p = npages % boundary_size; | |
2501 | n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2502 | if (p + n > boundary_size) | |
2503 | npages += boundary_size - p; | |
2504 | npages += n; | |
2505 | } | |
2506 | ||
2507 | return npages; | |
2508 | } | |
2509 | ||
431b2a20 JR |
2510 | /* |
2511 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2512 | * lists). | |
2513 | */ | |
65b050ad | 2514 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
80187fd3 | 2515 | int nelems, enum dma_data_direction direction, |
00085f1e | 2516 | unsigned long attrs) |
65b050ad | 2517 | { |
80187fd3 | 2518 | int mapped_pages = 0, npages = 0, prot = 0, i; |
89736a0e JR |
2519 | struct protection_domain *domain; |
2520 | struct dma_ops_domain *dma_dom; | |
65b050ad | 2521 | struct scatterlist *s; |
80187fd3 | 2522 | unsigned long address; |
89736a0e | 2523 | u64 dma_mask; |
2e6c6a86 | 2524 | int ret; |
65b050ad | 2525 | |
89736a0e JR |
2526 | domain = get_domain(dev); |
2527 | if (IS_ERR(domain)) | |
2528 | return 0; | |
2529 | ||
2530 | dma_dom = to_dma_ops_domain(domain); | |
2531 | dma_mask = *dev->dma_mask; | |
2532 | ||
80187fd3 JR |
2533 | npages = sg_num_pages(dev, sglist, nelems); |
2534 | ||
2535 | address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask); | |
b3aa14f0 | 2536 | if (address == DMA_MAPPING_ERROR) |
80187fd3 JR |
2537 | goto out_err; |
2538 | ||
2539 | prot = dir2prot(direction); | |
2540 | ||
2541 | /* Map all sg entries */ | |
65b050ad | 2542 | for_each_sg(sglist, s, nelems, i) { |
80187fd3 JR |
2543 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); |
2544 | ||
2545 | for (j = 0; j < pages; ++j) { | |
2546 | unsigned long bus_addr, phys_addr; | |
65b050ad | 2547 | |
80187fd3 JR |
2548 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2549 | phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT); | |
2550 | ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC); | |
2551 | if (ret) | |
2552 | goto out_unmap; | |
65b050ad | 2553 | |
80187fd3 JR |
2554 | mapped_pages += 1; |
2555 | } | |
65b050ad JR |
2556 | } |
2557 | ||
80187fd3 JR |
2558 | /* Everything is mapped - write the right values into s->dma_address */ |
2559 | for_each_sg(sglist, s, nelems, i) { | |
4e50ce03 SG |
2560 | /* |
2561 | * Add in the remaining piece of the scatter-gather offset that | |
2562 | * was masked out when we were determining the physical address | |
2563 | * via (sg_phys(s) & PAGE_MASK) earlier. | |
2564 | */ | |
2565 | s->dma_address += address + (s->offset & ~PAGE_MASK); | |
80187fd3 JR |
2566 | s->dma_length = s->length; |
2567 | } | |
2568 | ||
5cd3f2e9 TM |
2569 | if (s) |
2570 | domain_flush_np_cache(domain, s->dma_address, s->dma_length); | |
2571 | ||
80187fd3 JR |
2572 | return nelems; |
2573 | ||
2574 | out_unmap: | |
5f226da1 BH |
2575 | dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n", |
2576 | npages, ret); | |
80187fd3 JR |
2577 | |
2578 | for_each_sg(sglist, s, nelems, i) { | |
2579 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2580 | ||
2581 | for (j = 0; j < pages; ++j) { | |
2582 | unsigned long bus_addr; | |
92d420ec | 2583 | |
80187fd3 JR |
2584 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2585 | iommu_unmap_page(domain, bus_addr, PAGE_SIZE); | |
2586 | ||
f1724c08 | 2587 | if (--mapped_pages == 0) |
80187fd3 JR |
2588 | goto out_free_iova; |
2589 | } | |
65b050ad JR |
2590 | } |
2591 | ||
80187fd3 | 2592 | out_free_iova: |
51d8838d | 2593 | free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages); |
80187fd3 JR |
2594 | |
2595 | out_err: | |
92d420ec | 2596 | return 0; |
65b050ad JR |
2597 | } |
2598 | ||
431b2a20 JR |
2599 | /* |
2600 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2601 | * lists). | |
2602 | */ | |
65b050ad | 2603 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e | 2604 | int nelems, enum dma_data_direction dir, |
00085f1e | 2605 | unsigned long attrs) |
65b050ad | 2606 | { |
89736a0e JR |
2607 | struct protection_domain *domain; |
2608 | struct dma_ops_domain *dma_dom; | |
2609 | unsigned long startaddr; | |
2dbbcce1 | 2610 | int npages; |
89736a0e JR |
2611 | |
2612 | domain = get_domain(dev); | |
2613 | if (IS_ERR(domain)) | |
2614 | return; | |
2615 | ||
2616 | startaddr = sg_dma_address(sglist) & PAGE_MASK; | |
2617 | dma_dom = to_dma_ops_domain(domain); | |
2618 | npages = sg_num_pages(dev, sglist, nelems); | |
80187fd3 | 2619 | |
89736a0e | 2620 | __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir); |
65b050ad JR |
2621 | } |
2622 | ||
431b2a20 JR |
2623 | /* |
2624 | * The exported alloc_coherent function for dma_ops. | |
2625 | */ | |
5d8b53cf | 2626 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc | 2627 | dma_addr_t *dma_addr, gfp_t flag, |
00085f1e | 2628 | unsigned long attrs) |
5d8b53cf | 2629 | { |
832a90c3 | 2630 | u64 dma_mask = dev->coherent_dma_mask; |
89736a0e | 2631 | struct protection_domain *domain; |
e16c4790 LT |
2632 | struct dma_ops_domain *dma_dom; |
2633 | struct page *page; | |
2634 | ||
89736a0e JR |
2635 | domain = get_domain(dev); |
2636 | if (PTR_ERR(domain) == -EINVAL) { | |
2637 | page = alloc_pages(flag, get_order(size)); | |
2638 | *dma_addr = page_to_phys(page); | |
2639 | return page_address(page); | |
2640 | } else if (IS_ERR(domain)) | |
e16c4790 | 2641 | return NULL; |
5d8b53cf | 2642 | |
e16c4790 LT |
2643 | dma_dom = to_dma_ops_domain(domain); |
2644 | size = PAGE_ALIGN(size); | |
2645 | dma_mask = dev->coherent_dma_mask; | |
2646 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2647 | flag |= __GFP_ZERO; | |
2648 | ||
2649 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); | |
2650 | if (!page) { | |
2651 | if (!gfpflags_allow_blocking(flag)) | |
3b839a57 | 2652 | return NULL; |
5d8b53cf | 2653 | |
e16c4790 | 2654 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
d834c5ab | 2655 | get_order(size), flag & __GFP_NOWARN); |
e16c4790 LT |
2656 | if (!page) |
2657 | return NULL; | |
2658 | } | |
b468620f | 2659 | |
832a90c3 JR |
2660 | if (!dma_mask) |
2661 | dma_mask = *dev->dma_mask; | |
2662 | ||
e16c4790 LT |
2663 | *dma_addr = __map_single(dev, dma_dom, page_to_phys(page), |
2664 | size, DMA_BIDIRECTIONAL, dma_mask); | |
2665 | ||
b3aa14f0 | 2666 | if (*dma_addr == DMA_MAPPING_ERROR) |
5b28df6f | 2667 | goto out_free; |
e16c4790 LT |
2668 | |
2669 | return page_address(page); | |
5b28df6f JR |
2670 | |
2671 | out_free: | |
e16c4790 LT |
2672 | |
2673 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) | |
2674 | __free_pages(page, get_order(size)); | |
2675 | ||
5b28df6f | 2676 | return NULL; |
5d8b53cf JR |
2677 | } |
2678 | ||
431b2a20 JR |
2679 | /* |
2680 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2681 | */ |
5d8b53cf | 2682 | static void free_coherent(struct device *dev, size_t size, |
baa676fc | 2683 | void *virt_addr, dma_addr_t dma_addr, |
00085f1e | 2684 | unsigned long attrs) |
5d8b53cf | 2685 | { |
89736a0e JR |
2686 | struct protection_domain *domain; |
2687 | struct dma_ops_domain *dma_dom; | |
2688 | struct page *page; | |
5d8b53cf | 2689 | |
89736a0e | 2690 | page = virt_to_page(virt_addr); |
3b839a57 JR |
2691 | size = PAGE_ALIGN(size); |
2692 | ||
89736a0e JR |
2693 | domain = get_domain(dev); |
2694 | if (IS_ERR(domain)) | |
2695 | goto free_mem; | |
2696 | ||
2697 | dma_dom = to_dma_ops_domain(domain); | |
2698 | ||
e16c4790 | 2699 | __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL); |
89736a0e JR |
2700 | |
2701 | free_mem: | |
e16c4790 LT |
2702 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2703 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2704 | } |
2705 | ||
b39ba6ad JR |
2706 | /* |
2707 | * This function is called by the DMA layer to find out if we can handle a | |
2708 | * particular device. It is part of the dma_ops. | |
2709 | */ | |
2710 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2711 | { | |
fec777c3 | 2712 | if (!dma_direct_supported(dev, mask)) |
5860acc1 | 2713 | return 0; |
420aef8a | 2714 | return check_device(dev); |
b39ba6ad JR |
2715 | } |
2716 | ||
5299709d | 2717 | static const struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2718 | .alloc = alloc_coherent, |
2719 | .free = free_coherent, | |
2720 | .map_page = map_page, | |
2721 | .unmap_page = unmap_page, | |
2722 | .map_sg = map_sg, | |
2723 | .unmap_sg = unmap_sg, | |
2724 | .dma_supported = amd_iommu_dma_supported, | |
6631ee9d JR |
2725 | }; |
2726 | ||
81cd07b9 JR |
2727 | static int init_reserved_iova_ranges(void) |
2728 | { | |
2729 | struct pci_dev *pdev = NULL; | |
2730 | struct iova *val; | |
2731 | ||
aa3ac946 | 2732 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN); |
81cd07b9 JR |
2733 | |
2734 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, | |
2735 | &reserved_rbtree_key); | |
2736 | ||
2737 | /* MSI memory range */ | |
2738 | val = reserve_iova(&reserved_iova_ranges, | |
2739 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); | |
2740 | if (!val) { | |
2741 | pr_err("Reserving MSI range failed\n"); | |
2742 | return -ENOMEM; | |
2743 | } | |
2744 | ||
2745 | /* HT memory range */ | |
2746 | val = reserve_iova(&reserved_iova_ranges, | |
2747 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); | |
2748 | if (!val) { | |
2749 | pr_err("Reserving HT range failed\n"); | |
2750 | return -ENOMEM; | |
2751 | } | |
2752 | ||
2753 | /* | |
2754 | * Memory used for PCI resources | |
2755 | * FIXME: Check whether we can reserve the PCI-hole completly | |
2756 | */ | |
2757 | for_each_pci_dev(pdev) { | |
2758 | int i; | |
2759 | ||
2760 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { | |
2761 | struct resource *r = &pdev->resource[i]; | |
2762 | ||
2763 | if (!(r->flags & IORESOURCE_MEM)) | |
2764 | continue; | |
2765 | ||
2766 | val = reserve_iova(&reserved_iova_ranges, | |
2767 | IOVA_PFN(r->start), | |
2768 | IOVA_PFN(r->end)); | |
2769 | if (!val) { | |
5f226da1 | 2770 | pci_err(pdev, "Reserve pci-resource range %pR failed\n", r); |
81cd07b9 JR |
2771 | return -ENOMEM; |
2772 | } | |
2773 | } | |
2774 | } | |
2775 | ||
2776 | return 0; | |
2777 | } | |
2778 | ||
3a18404c | 2779 | int __init amd_iommu_init_api(void) |
27c2127a | 2780 | { |
460c26d0 | 2781 | int ret, err = 0; |
307d5851 JR |
2782 | |
2783 | ret = iova_cache_get(); | |
2784 | if (ret) | |
2785 | return ret; | |
9a4d3bf5 | 2786 | |
81cd07b9 JR |
2787 | ret = init_reserved_iova_ranges(); |
2788 | if (ret) | |
2789 | return ret; | |
2790 | ||
9a4d3bf5 WZ |
2791 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
2792 | if (err) | |
2793 | return err; | |
2794 | #ifdef CONFIG_ARM_AMBA | |
2795 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
2796 | if (err) | |
2797 | return err; | |
2798 | #endif | |
0076cd3d WZ |
2799 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
2800 | if (err) | |
2801 | return err; | |
c5b5da9c | 2802 | |
460c26d0 | 2803 | return 0; |
f5325094 JR |
2804 | } |
2805 | ||
6631ee9d JR |
2806 | int __init amd_iommu_init_dma_ops(void) |
2807 | { | |
aba2d9a6 | 2808 | swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0; |
6631ee9d | 2809 | iommu_detected = 1; |
6631ee9d | 2810 | |
62410eeb | 2811 | if (amd_iommu_unmap_flush) |
101fa037 | 2812 | pr_info("IO/TLB flush on unmap enabled\n"); |
62410eeb | 2813 | else |
101fa037 | 2814 | pr_info("Lazy IO/TLB flushing enabled\n"); |
62410eeb | 2815 | |
6631ee9d | 2816 | return 0; |
c5b5da9c | 2817 | |
6631ee9d | 2818 | } |
6d98cd80 JR |
2819 | |
2820 | /***************************************************************************** | |
2821 | * | |
2822 | * The following functions belong to the exported interface of AMD IOMMU | |
2823 | * | |
2824 | * This interface allows access to lower level functions of the IOMMU | |
2825 | * like protection domain handling and assignement of devices to domains | |
2826 | * which is not possible with the dma_ops interface. | |
2827 | * | |
2828 | *****************************************************************************/ | |
2829 | ||
6d98cd80 JR |
2830 | static void cleanup_domain(struct protection_domain *domain) |
2831 | { | |
9b29d3c6 | 2832 | struct iommu_dev_data *entry; |
6d98cd80 | 2833 | unsigned long flags; |
6d98cd80 | 2834 | |
2cd1083d | 2835 | spin_lock_irqsave(&amd_iommu_devtable_lock, flags); |
6d98cd80 | 2836 | |
9b29d3c6 JR |
2837 | while (!list_empty(&domain->dev_list)) { |
2838 | entry = list_first_entry(&domain->dev_list, | |
2839 | struct iommu_dev_data, list); | |
ea3fd040 | 2840 | BUG_ON(!entry->domain); |
9b29d3c6 | 2841 | __detach_device(entry); |
492667da | 2842 | } |
6d98cd80 | 2843 | |
2cd1083d | 2844 | spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
6d98cd80 JR |
2845 | } |
2846 | ||
2650815f JR |
2847 | static void protection_domain_free(struct protection_domain *domain) |
2848 | { | |
2849 | if (!domain) | |
2850 | return; | |
2851 | ||
2852 | if (domain->id) | |
2853 | domain_id_free(domain->id); | |
2854 | ||
2855 | kfree(domain); | |
2856 | } | |
2857 | ||
7a5a566e JR |
2858 | static int protection_domain_init(struct protection_domain *domain) |
2859 | { | |
2860 | spin_lock_init(&domain->lock); | |
2861 | mutex_init(&domain->api_lock); | |
2862 | domain->id = domain_id_alloc(); | |
2863 | if (!domain->id) | |
2864 | return -ENOMEM; | |
2865 | INIT_LIST_HEAD(&domain->dev_list); | |
2866 | ||
2867 | return 0; | |
2868 | } | |
2869 | ||
2650815f | 2870 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2871 | { |
2872 | struct protection_domain *domain; | |
2873 | ||
2874 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2875 | if (!domain) | |
2650815f | 2876 | return NULL; |
c156e347 | 2877 | |
7a5a566e | 2878 | if (protection_domain_init(domain)) |
2650815f JR |
2879 | goto out_err; |
2880 | ||
2881 | return domain; | |
2882 | ||
2883 | out_err: | |
2884 | kfree(domain); | |
2885 | ||
2886 | return NULL; | |
2887 | } | |
2888 | ||
3f4b87b9 | 2889 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2890 | { |
3f4b87b9 | 2891 | struct protection_domain *pdomain; |
0bb6e243 | 2892 | struct dma_ops_domain *dma_domain; |
2650815f | 2893 | |
0bb6e243 JR |
2894 | switch (type) { |
2895 | case IOMMU_DOMAIN_UNMANAGED: | |
2896 | pdomain = protection_domain_alloc(); | |
2897 | if (!pdomain) | |
2898 | return NULL; | |
c156e347 | 2899 | |
0bb6e243 JR |
2900 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2901 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2902 | if (!pdomain->pt_root) { | |
2903 | protection_domain_free(pdomain); | |
2904 | return NULL; | |
2905 | } | |
c156e347 | 2906 | |
0bb6e243 JR |
2907 | pdomain->domain.geometry.aperture_start = 0; |
2908 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2909 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2910 | |
0bb6e243 JR |
2911 | break; |
2912 | case IOMMU_DOMAIN_DMA: | |
2913 | dma_domain = dma_ops_domain_alloc(); | |
2914 | if (!dma_domain) { | |
101fa037 | 2915 | pr_err("Failed to allocate\n"); |
0bb6e243 JR |
2916 | return NULL; |
2917 | } | |
2918 | pdomain = &dma_domain->domain; | |
2919 | break; | |
07f643a3 JR |
2920 | case IOMMU_DOMAIN_IDENTITY: |
2921 | pdomain = protection_domain_alloc(); | |
2922 | if (!pdomain) | |
2923 | return NULL; | |
c156e347 | 2924 | |
07f643a3 JR |
2925 | pdomain->mode = PAGE_MODE_NONE; |
2926 | break; | |
0bb6e243 JR |
2927 | default: |
2928 | return NULL; | |
2929 | } | |
c156e347 | 2930 | |
3f4b87b9 | 2931 | return &pdomain->domain; |
c156e347 JR |
2932 | } |
2933 | ||
3f4b87b9 | 2934 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2935 | { |
3f4b87b9 | 2936 | struct protection_domain *domain; |
cda7005b | 2937 | struct dma_ops_domain *dma_dom; |
98383fc3 | 2938 | |
3f4b87b9 JR |
2939 | domain = to_pdomain(dom); |
2940 | ||
98383fc3 JR |
2941 | if (domain->dev_cnt > 0) |
2942 | cleanup_domain(domain); | |
2943 | ||
2944 | BUG_ON(domain->dev_cnt != 0); | |
2945 | ||
cda7005b JR |
2946 | if (!dom) |
2947 | return; | |
98383fc3 | 2948 | |
cda7005b JR |
2949 | switch (dom->type) { |
2950 | case IOMMU_DOMAIN_DMA: | |
281e8ccb | 2951 | /* Now release the domain */ |
b3311b06 | 2952 | dma_dom = to_dma_ops_domain(domain); |
cda7005b JR |
2953 | dma_ops_domain_free(dma_dom); |
2954 | break; | |
2955 | default: | |
2956 | if (domain->mode != PAGE_MODE_NONE) | |
2957 | free_pagetable(domain); | |
52815b75 | 2958 | |
cda7005b JR |
2959 | if (domain->flags & PD_IOMMUV2_MASK) |
2960 | free_gcr3_table(domain); | |
2961 | ||
2962 | protection_domain_free(domain); | |
2963 | break; | |
2964 | } | |
98383fc3 JR |
2965 | } |
2966 | ||
684f2888 JR |
2967 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2968 | struct device *dev) | |
2969 | { | |
657cbb6b | 2970 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2971 | struct amd_iommu *iommu; |
7aba6cb9 | 2972 | int devid; |
684f2888 | 2973 | |
98fc5a69 | 2974 | if (!check_device(dev)) |
684f2888 JR |
2975 | return; |
2976 | ||
98fc5a69 | 2977 | devid = get_device_id(dev); |
9ee35e4c | 2978 | if (devid < 0) |
7aba6cb9 | 2979 | return; |
684f2888 | 2980 | |
657cbb6b | 2981 | if (dev_data->domain != NULL) |
15898bbc | 2982 | detach_device(dev); |
684f2888 JR |
2983 | |
2984 | iommu = amd_iommu_rlookup_table[devid]; | |
2985 | if (!iommu) | |
2986 | return; | |
2987 | ||
d98de49a SS |
2988 | #ifdef CONFIG_IRQ_REMAP |
2989 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && | |
2990 | (dom->type == IOMMU_DOMAIN_UNMANAGED)) | |
2991 | dev_data->use_vapic = 0; | |
2992 | #endif | |
2993 | ||
684f2888 JR |
2994 | iommu_completion_wait(iommu); |
2995 | } | |
2996 | ||
01106066 JR |
2997 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2998 | struct device *dev) | |
2999 | { | |
3f4b87b9 | 3000 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3001 | struct iommu_dev_data *dev_data; |
01106066 | 3002 | struct amd_iommu *iommu; |
15898bbc | 3003 | int ret; |
01106066 | 3004 | |
98fc5a69 | 3005 | if (!check_device(dev)) |
01106066 JR |
3006 | return -EINVAL; |
3007 | ||
657cbb6b JR |
3008 | dev_data = dev->archdata.iommu; |
3009 | ||
f62dda66 | 3010 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3011 | if (!iommu) |
3012 | return -EINVAL; | |
3013 | ||
657cbb6b | 3014 | if (dev_data->domain) |
15898bbc | 3015 | detach_device(dev); |
01106066 | 3016 | |
15898bbc | 3017 | ret = attach_device(dev, domain); |
01106066 | 3018 | |
d98de49a SS |
3019 | #ifdef CONFIG_IRQ_REMAP |
3020 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
3021 | if (dom->type == IOMMU_DOMAIN_UNMANAGED) | |
3022 | dev_data->use_vapic = 1; | |
3023 | else | |
3024 | dev_data->use_vapic = 0; | |
3025 | } | |
3026 | #endif | |
3027 | ||
01106066 JR |
3028 | iommu_completion_wait(iommu); |
3029 | ||
15898bbc | 3030 | return ret; |
01106066 JR |
3031 | } |
3032 | ||
468e2366 | 3033 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3034 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3035 | { |
3f4b87b9 | 3036 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3037 | int prot = 0; |
3038 | int ret; | |
3039 | ||
132bd68f JR |
3040 | if (domain->mode == PAGE_MODE_NONE) |
3041 | return -EINVAL; | |
3042 | ||
c6229ca6 JR |
3043 | if (iommu_prot & IOMMU_READ) |
3044 | prot |= IOMMU_PROT_IR; | |
3045 | if (iommu_prot & IOMMU_WRITE) | |
3046 | prot |= IOMMU_PROT_IW; | |
3047 | ||
5d214fe6 | 3048 | mutex_lock(&domain->api_lock); |
b911b89b | 3049 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); |
5d214fe6 JR |
3050 | mutex_unlock(&domain->api_lock); |
3051 | ||
5cd3f2e9 TM |
3052 | domain_flush_np_cache(domain, iova, page_size); |
3053 | ||
795e74f7 | 3054 | return ret; |
c6229ca6 JR |
3055 | } |
3056 | ||
5009065d OBC |
3057 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3058 | size_t page_size) | |
eb74ff6c | 3059 | { |
3f4b87b9 | 3060 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3061 | size_t unmap_size; |
eb74ff6c | 3062 | |
132bd68f | 3063 | if (domain->mode == PAGE_MODE_NONE) |
c5611a87 | 3064 | return 0; |
132bd68f | 3065 | |
5d214fe6 | 3066 | mutex_lock(&domain->api_lock); |
468e2366 | 3067 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3068 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3069 | |
5009065d | 3070 | return unmap_size; |
eb74ff6c JR |
3071 | } |
3072 | ||
645c4c8d | 3073 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3074 | dma_addr_t iova) |
645c4c8d | 3075 | { |
3f4b87b9 | 3076 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3077 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3078 | u64 *pte, __pte; |
645c4c8d | 3079 | |
132bd68f JR |
3080 | if (domain->mode == PAGE_MODE_NONE) |
3081 | return iova; | |
3082 | ||
3039ca1b | 3083 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3084 | |
a6d41a40 | 3085 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3086 | return 0; |
3087 | ||
b24b1b63 | 3088 | offset_mask = pte_pgsize - 1; |
b3e9b515 | 3089 | __pte = __sme_clr(*pte & PM_ADDR_MASK); |
645c4c8d | 3090 | |
b24b1b63 | 3091 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3092 | } |
3093 | ||
ab636481 | 3094 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3095 | { |
80a506b8 JR |
3096 | switch (cap) { |
3097 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3098 | return true; |
bdddadcb | 3099 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3100 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3101 | case IOMMU_CAP_NOEXEC: |
3102 | return false; | |
e84b7cc4 LB |
3103 | default: |
3104 | break; | |
80a506b8 JR |
3105 | } |
3106 | ||
ab636481 | 3107 | return false; |
dbb9fd86 SY |
3108 | } |
3109 | ||
e5b5234a EA |
3110 | static void amd_iommu_get_resv_regions(struct device *dev, |
3111 | struct list_head *head) | |
35cf248f | 3112 | { |
4397f32c | 3113 | struct iommu_resv_region *region; |
35cf248f | 3114 | struct unity_map_entry *entry; |
7aba6cb9 | 3115 | int devid; |
35cf248f JR |
3116 | |
3117 | devid = get_device_id(dev); | |
9ee35e4c | 3118 | if (devid < 0) |
7aba6cb9 | 3119 | return; |
35cf248f JR |
3120 | |
3121 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
8aafaaf2 | 3122 | int type, prot = 0; |
4397f32c | 3123 | size_t length; |
35cf248f JR |
3124 | |
3125 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3126 | continue; | |
3127 | ||
8aafaaf2 | 3128 | type = IOMMU_RESV_DIRECT; |
4397f32c EA |
3129 | length = entry->address_end - entry->address_start; |
3130 | if (entry->prot & IOMMU_PROT_IR) | |
3131 | prot |= IOMMU_READ; | |
3132 | if (entry->prot & IOMMU_PROT_IW) | |
3133 | prot |= IOMMU_WRITE; | |
8aafaaf2 JR |
3134 | if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE) |
3135 | /* Exclusion range */ | |
3136 | type = IOMMU_RESV_RESERVED; | |
4397f32c EA |
3137 | |
3138 | region = iommu_alloc_resv_region(entry->address_start, | |
8aafaaf2 | 3139 | length, prot, type); |
35cf248f | 3140 | if (!region) { |
5f226da1 | 3141 | dev_err(dev, "Out of memory allocating dm-regions\n"); |
35cf248f JR |
3142 | return; |
3143 | } | |
35cf248f JR |
3144 | list_add_tail(®ion->list, head); |
3145 | } | |
4397f32c EA |
3146 | |
3147 | region = iommu_alloc_resv_region(MSI_RANGE_START, | |
3148 | MSI_RANGE_END - MSI_RANGE_START + 1, | |
9d3a4de4 | 3149 | 0, IOMMU_RESV_MSI); |
4397f32c EA |
3150 | if (!region) |
3151 | return; | |
3152 | list_add_tail(®ion->list, head); | |
3153 | ||
3154 | region = iommu_alloc_resv_region(HT_RANGE_START, | |
3155 | HT_RANGE_END - HT_RANGE_START + 1, | |
3156 | 0, IOMMU_RESV_RESERVED); | |
3157 | if (!region) | |
3158 | return; | |
3159 | list_add_tail(®ion->list, head); | |
35cf248f JR |
3160 | } |
3161 | ||
e5b5234a | 3162 | static void amd_iommu_put_resv_regions(struct device *dev, |
35cf248f JR |
3163 | struct list_head *head) |
3164 | { | |
e5b5234a | 3165 | struct iommu_resv_region *entry, *next; |
35cf248f JR |
3166 | |
3167 | list_for_each_entry_safe(entry, next, head, list) | |
3168 | kfree(entry); | |
3169 | } | |
3170 | ||
e5b5234a | 3171 | static void amd_iommu_apply_resv_region(struct device *dev, |
8d54d6c8 | 3172 | struct iommu_domain *domain, |
e5b5234a | 3173 | struct iommu_resv_region *region) |
8d54d6c8 | 3174 | { |
b3311b06 | 3175 | struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain)); |
8d54d6c8 JR |
3176 | unsigned long start, end; |
3177 | ||
3178 | start = IOVA_PFN(region->start); | |
b92b4fb5 | 3179 | end = IOVA_PFN(region->start + region->length - 1); |
8d54d6c8 JR |
3180 | |
3181 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); | |
3182 | } | |
3183 | ||
df3f7a6e BH |
3184 | static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain, |
3185 | struct device *dev) | |
3186 | { | |
3187 | struct iommu_dev_data *dev_data = dev->archdata.iommu; | |
3188 | return dev_data->defer_attach; | |
3189 | } | |
3190 | ||
eb5ecd1a SS |
3191 | static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain) |
3192 | { | |
3193 | struct protection_domain *dom = to_pdomain(domain); | |
3194 | ||
3195 | domain_flush_tlb_pde(dom); | |
3196 | domain_flush_complete(dom); | |
3197 | } | |
3198 | ||
3199 | static void amd_iommu_iotlb_range_add(struct iommu_domain *domain, | |
3200 | unsigned long iova, size_t size) | |
3201 | { | |
3202 | } | |
3203 | ||
b0119e87 | 3204 | const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3205 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3206 | .domain_alloc = amd_iommu_domain_alloc, |
3207 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3208 | .attach_dev = amd_iommu_attach_device, |
3209 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3210 | .map = amd_iommu_map, |
3211 | .unmap = amd_iommu_unmap, | |
26961efe | 3212 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3213 | .add_device = amd_iommu_add_device, |
3214 | .remove_device = amd_iommu_remove_device, | |
b097d11a | 3215 | .device_group = amd_iommu_device_group, |
e5b5234a EA |
3216 | .get_resv_regions = amd_iommu_get_resv_regions, |
3217 | .put_resv_regions = amd_iommu_put_resv_regions, | |
3218 | .apply_resv_region = amd_iommu_apply_resv_region, | |
df3f7a6e | 3219 | .is_attach_deferred = amd_iommu_is_attach_deferred, |
aa3de9c0 | 3220 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
eb5ecd1a SS |
3221 | .flush_iotlb_all = amd_iommu_flush_iotlb_all, |
3222 | .iotlb_range_add = amd_iommu_iotlb_range_add, | |
3223 | .iotlb_sync = amd_iommu_flush_iotlb_all, | |
26961efe JR |
3224 | }; |
3225 | ||
0feae533 JR |
3226 | /***************************************************************************** |
3227 | * | |
3228 | * The next functions do a basic initialization of IOMMU for pass through | |
3229 | * mode | |
3230 | * | |
3231 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3232 | * DMA-API translation. | |
3233 | * | |
3234 | *****************************************************************************/ | |
3235 | ||
72e1dcc4 JR |
3236 | /* IOMMUv2 specific functions */ |
3237 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3238 | { | |
3239 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3240 | } | |
3241 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3242 | ||
3243 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3244 | { | |
3245 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3246 | } | |
3247 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3248 | |
3249 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3250 | { | |
3f4b87b9 | 3251 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3252 | unsigned long flags; |
3253 | ||
3254 | spin_lock_irqsave(&domain->lock, flags); | |
3255 | ||
3256 | /* Update data structure */ | |
3257 | domain->mode = PAGE_MODE_NONE; | |
3258 | domain->updated = true; | |
3259 | ||
3260 | /* Make changes visible to IOMMUs */ | |
3261 | update_domain(domain); | |
3262 | ||
3263 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3264 | free_pagetable(domain); | |
3265 | ||
3266 | spin_unlock_irqrestore(&domain->lock, flags); | |
3267 | } | |
3268 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3269 | |
3270 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3271 | { | |
3f4b87b9 | 3272 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3273 | unsigned long flags; |
3274 | int levels, ret; | |
3275 | ||
3276 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3277 | return -EINVAL; | |
3278 | ||
3279 | /* Number of GCR3 table levels required */ | |
3280 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3281 | levels += 1; | |
3282 | ||
3283 | if (levels > amd_iommu_max_glx_val) | |
3284 | return -EINVAL; | |
3285 | ||
3286 | spin_lock_irqsave(&domain->lock, flags); | |
3287 | ||
3288 | /* | |
3289 | * Save us all sanity checks whether devices already in the | |
3290 | * domain support IOMMUv2. Just force that the domain has no | |
3291 | * devices attached when it is switched into IOMMUv2 mode. | |
3292 | */ | |
3293 | ret = -EBUSY; | |
3294 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3295 | goto out; | |
3296 | ||
3297 | ret = -ENOMEM; | |
3298 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3299 | if (domain->gcr3_tbl == NULL) | |
3300 | goto out; | |
3301 | ||
3302 | domain->glx = levels; | |
3303 | domain->flags |= PD_IOMMUV2_MASK; | |
3304 | domain->updated = true; | |
3305 | ||
3306 | update_domain(domain); | |
3307 | ||
3308 | ret = 0; | |
3309 | ||
3310 | out: | |
3311 | spin_unlock_irqrestore(&domain->lock, flags); | |
3312 | ||
3313 | return ret; | |
3314 | } | |
3315 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3316 | |
3317 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3318 | u64 address, bool size) | |
3319 | { | |
3320 | struct iommu_dev_data *dev_data; | |
3321 | struct iommu_cmd cmd; | |
3322 | int i, ret; | |
3323 | ||
3324 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3325 | return -EINVAL; | |
3326 | ||
3327 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3328 | ||
3329 | /* | |
3330 | * IOMMU TLB needs to be flushed before Device TLB to | |
3331 | * prevent device TLB refill from IOMMU TLB | |
3332 | */ | |
6b9376e3 | 3333 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
22e266c7 JR |
3334 | if (domain->dev_iommu[i] == 0) |
3335 | continue; | |
3336 | ||
3337 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3338 | if (ret != 0) | |
3339 | goto out; | |
3340 | } | |
3341 | ||
3342 | /* Wait until IOMMU TLB flushes are complete */ | |
3343 | domain_flush_complete(domain); | |
3344 | ||
3345 | /* Now flush device TLBs */ | |
3346 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3347 | struct amd_iommu *iommu; | |
3348 | int qdep; | |
3349 | ||
1c1cc454 JR |
3350 | /* |
3351 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3352 | * domain. | |
3353 | */ | |
3354 | if (!dev_data->ats.enabled) | |
3355 | continue; | |
22e266c7 JR |
3356 | |
3357 | qdep = dev_data->ats.qdep; | |
3358 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3359 | ||
3360 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3361 | qdep, address, size); | |
3362 | ||
3363 | ret = iommu_queue_command(iommu, &cmd); | |
3364 | if (ret != 0) | |
3365 | goto out; | |
3366 | } | |
3367 | ||
3368 | /* Wait until all device TLBs are flushed */ | |
3369 | domain_flush_complete(domain); | |
3370 | ||
3371 | ret = 0; | |
3372 | ||
3373 | out: | |
3374 | ||
3375 | return ret; | |
3376 | } | |
3377 | ||
3378 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3379 | u64 address) | |
3380 | { | |
3381 | return __flush_pasid(domain, pasid, address, false); | |
3382 | } | |
3383 | ||
3384 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3385 | u64 address) | |
3386 | { | |
3f4b87b9 | 3387 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3388 | unsigned long flags; |
3389 | int ret; | |
3390 | ||
3391 | spin_lock_irqsave(&domain->lock, flags); | |
3392 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3393 | spin_unlock_irqrestore(&domain->lock, flags); | |
3394 | ||
3395 | return ret; | |
3396 | } | |
3397 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3398 | ||
3399 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3400 | { | |
3401 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3402 | true); | |
3403 | } | |
3404 | ||
3405 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3406 | { | |
3f4b87b9 | 3407 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3408 | unsigned long flags; |
3409 | int ret; | |
3410 | ||
3411 | spin_lock_irqsave(&domain->lock, flags); | |
3412 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3413 | spin_unlock_irqrestore(&domain->lock, flags); | |
3414 | ||
3415 | return ret; | |
3416 | } | |
3417 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3418 | ||
b16137b1 JR |
3419 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3420 | { | |
3421 | int index; | |
3422 | u64 *pte; | |
3423 | ||
3424 | while (true) { | |
3425 | ||
3426 | index = (pasid >> (9 * level)) & 0x1ff; | |
3427 | pte = &root[index]; | |
3428 | ||
3429 | if (level == 0) | |
3430 | break; | |
3431 | ||
3432 | if (!(*pte & GCR3_VALID)) { | |
3433 | if (!alloc) | |
3434 | return NULL; | |
3435 | ||
3436 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3437 | if (root == NULL) | |
3438 | return NULL; | |
3439 | ||
2543a786 | 3440 | *pte = iommu_virt_to_phys(root) | GCR3_VALID; |
b16137b1 JR |
3441 | } |
3442 | ||
2543a786 | 3443 | root = iommu_phys_to_virt(*pte & PAGE_MASK); |
b16137b1 JR |
3444 | |
3445 | level -= 1; | |
3446 | } | |
3447 | ||
3448 | return pte; | |
3449 | } | |
3450 | ||
3451 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3452 | unsigned long cr3) | |
3453 | { | |
3454 | u64 *pte; | |
3455 | ||
3456 | if (domain->mode != PAGE_MODE_NONE) | |
3457 | return -EINVAL; | |
3458 | ||
3459 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3460 | if (pte == NULL) | |
3461 | return -ENOMEM; | |
3462 | ||
3463 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3464 | ||
3465 | return __amd_iommu_flush_tlb(domain, pasid); | |
3466 | } | |
3467 | ||
3468 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3469 | { | |
3470 | u64 *pte; | |
3471 | ||
3472 | if (domain->mode != PAGE_MODE_NONE) | |
3473 | return -EINVAL; | |
3474 | ||
3475 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3476 | if (pte == NULL) | |
3477 | return 0; | |
3478 | ||
3479 | *pte = 0; | |
3480 | ||
3481 | return __amd_iommu_flush_tlb(domain, pasid); | |
3482 | } | |
3483 | ||
3484 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3485 | unsigned long cr3) | |
3486 | { | |
3f4b87b9 | 3487 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3488 | unsigned long flags; |
3489 | int ret; | |
3490 | ||
3491 | spin_lock_irqsave(&domain->lock, flags); | |
3492 | ret = __set_gcr3(domain, pasid, cr3); | |
3493 | spin_unlock_irqrestore(&domain->lock, flags); | |
3494 | ||
3495 | return ret; | |
3496 | } | |
3497 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3498 | ||
3499 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3500 | { | |
3f4b87b9 | 3501 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3502 | unsigned long flags; |
3503 | int ret; | |
3504 | ||
3505 | spin_lock_irqsave(&domain->lock, flags); | |
3506 | ret = __clear_gcr3(domain, pasid); | |
3507 | spin_unlock_irqrestore(&domain->lock, flags); | |
3508 | ||
3509 | return ret; | |
3510 | } | |
3511 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3512 | |
3513 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3514 | int status, int tag) | |
3515 | { | |
3516 | struct iommu_dev_data *dev_data; | |
3517 | struct amd_iommu *iommu; | |
3518 | struct iommu_cmd cmd; | |
3519 | ||
3520 | dev_data = get_dev_data(&pdev->dev); | |
3521 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3522 | ||
3523 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3524 | tag, dev_data->pri_tlp); | |
3525 | ||
3526 | return iommu_queue_command(iommu, &cmd); | |
3527 | } | |
3528 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3529 | |
3530 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3531 | { | |
3f4b87b9 | 3532 | struct protection_domain *pdomain; |
f3572db8 | 3533 | |
3f4b87b9 JR |
3534 | pdomain = get_domain(&pdev->dev); |
3535 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3536 | return NULL; |
3537 | ||
3538 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3539 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3540 | return NULL; |
3541 | ||
3f4b87b9 | 3542 | return &pdomain->domain; |
f3572db8 JR |
3543 | } |
3544 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3545 | |
3546 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3547 | { | |
3548 | struct iommu_dev_data *dev_data; | |
3549 | ||
3550 | if (!amd_iommu_v2_supported()) | |
3551 | return; | |
3552 | ||
3553 | dev_data = get_dev_data(&pdev->dev); | |
3554 | dev_data->errata |= (1 << erratum); | |
3555 | } | |
3556 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3557 | |
3558 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3559 | struct amd_iommu_device_info *info) | |
3560 | { | |
3561 | int max_pasids; | |
3562 | int pos; | |
3563 | ||
3564 | if (pdev == NULL || info == NULL) | |
3565 | return -EINVAL; | |
3566 | ||
3567 | if (!amd_iommu_v2_supported()) | |
3568 | return -EINVAL; | |
3569 | ||
3570 | memset(info, 0, sizeof(*info)); | |
3571 | ||
cef74409 GK |
3572 | if (!pci_ats_disabled()) { |
3573 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3574 | if (pos) | |
3575 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3576 | } | |
52efdb89 JR |
3577 | |
3578 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3579 | if (pos) | |
3580 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3581 | ||
3582 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3583 | if (pos) { | |
3584 | int features; | |
3585 | ||
3586 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3587 | max_pasids = min(max_pasids, (1 << 20)); | |
3588 | ||
3589 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3590 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3591 | ||
3592 | features = pci_pasid_features(pdev); | |
3593 | if (features & PCI_PASID_CAP_EXEC) | |
3594 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3595 | if (features & PCI_PASID_CAP_PRIV) | |
3596 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3597 | } | |
3598 | ||
3599 | return 0; | |
3600 | } | |
3601 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3602 | |
3603 | #ifdef CONFIG_IRQ_REMAP | |
3604 | ||
3605 | /***************************************************************************** | |
3606 | * | |
3607 | * Interrupt Remapping Implementation | |
3608 | * | |
3609 | *****************************************************************************/ | |
3610 | ||
7c71d306 | 3611 | static struct irq_chip amd_ir_chip; |
94c793ac | 3612 | static DEFINE_SPINLOCK(iommu_table_lock); |
7c71d306 | 3613 | |
2b324506 JR |
3614 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) |
3615 | { | |
3616 | u64 dte; | |
3617 | ||
3618 | dte = amd_iommu_dev_table[devid].data[2]; | |
3619 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
2543a786 | 3620 | dte |= iommu_virt_to_phys(table->table); |
2b324506 JR |
3621 | dte |= DTE_IRQ_REMAP_INTCTL; |
3622 | dte |= DTE_IRQ_TABLE_LEN; | |
3623 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3624 | ||
3625 | amd_iommu_dev_table[devid].data[2] = dte; | |
3626 | } | |
3627 | ||
df42a04b SW |
3628 | static struct irq_remap_table *get_irq_table(u16 devid) |
3629 | { | |
3630 | struct irq_remap_table *table; | |
3631 | ||
3632 | if (WARN_ONCE(!amd_iommu_rlookup_table[devid], | |
3633 | "%s: no iommu for devid %x\n", __func__, devid)) | |
3634 | return NULL; | |
3635 | ||
3636 | table = irq_lookup_table[devid]; | |
3637 | if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid)) | |
3638 | return NULL; | |
3639 | ||
3640 | return table; | |
3641 | } | |
3642 | ||
993ca6e0 SAS |
3643 | static struct irq_remap_table *__alloc_irq_table(void) |
3644 | { | |
3645 | struct irq_remap_table *table; | |
3646 | ||
3647 | table = kzalloc(sizeof(*table), GFP_KERNEL); | |
3648 | if (!table) | |
3649 | return NULL; | |
3650 | ||
3651 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL); | |
3652 | if (!table->table) { | |
3653 | kfree(table); | |
3654 | return NULL; | |
3655 | } | |
3656 | raw_spin_lock_init(&table->lock); | |
3657 | ||
3658 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) | |
3659 | memset(table->table, 0, | |
3660 | MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3661 | else | |
3662 | memset(table->table, 0, | |
3663 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); | |
3664 | return table; | |
3665 | } | |
3666 | ||
2fcc1e8a SAS |
3667 | static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid, |
3668 | struct irq_remap_table *table) | |
3669 | { | |
3670 | irq_lookup_table[devid] = table; | |
3671 | set_dte_irq_entry(devid, table); | |
3672 | iommu_flush_dte(iommu, devid); | |
3673 | } | |
3674 | ||
fde65dd3 | 3675 | static struct irq_remap_table *alloc_irq_table(u16 devid) |
2b324506 JR |
3676 | { |
3677 | struct irq_remap_table *table = NULL; | |
993ca6e0 | 3678 | struct irq_remap_table *new_table = NULL; |
2b324506 JR |
3679 | struct amd_iommu *iommu; |
3680 | unsigned long flags; | |
3681 | u16 alias; | |
3682 | ||
ea6166f4 | 3683 | spin_lock_irqsave(&iommu_table_lock, flags); |
2b324506 JR |
3684 | |
3685 | iommu = amd_iommu_rlookup_table[devid]; | |
3686 | if (!iommu) | |
3687 | goto out_unlock; | |
3688 | ||
3689 | table = irq_lookup_table[devid]; | |
3690 | if (table) | |
09284b9c | 3691 | goto out_unlock; |
2b324506 JR |
3692 | |
3693 | alias = amd_iommu_alias_table[devid]; | |
3694 | table = irq_lookup_table[alias]; | |
3695 | if (table) { | |
2fcc1e8a | 3696 | set_remap_table_entry(iommu, devid, table); |
993ca6e0 | 3697 | goto out_wait; |
2b324506 | 3698 | } |
993ca6e0 | 3699 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
2b324506 JR |
3700 | |
3701 | /* Nothing there yet, allocate new irq remapping table */ | |
993ca6e0 SAS |
3702 | new_table = __alloc_irq_table(); |
3703 | if (!new_table) | |
3704 | return NULL; | |
197887f0 | 3705 | |
993ca6e0 | 3706 | spin_lock_irqsave(&iommu_table_lock, flags); |
2b324506 | 3707 | |
993ca6e0 SAS |
3708 | table = irq_lookup_table[devid]; |
3709 | if (table) | |
09284b9c | 3710 | goto out_unlock; |
2b324506 | 3711 | |
993ca6e0 SAS |
3712 | table = irq_lookup_table[alias]; |
3713 | if (table) { | |
3714 | set_remap_table_entry(iommu, devid, table); | |
3715 | goto out_wait; | |
2b324506 JR |
3716 | } |
3717 | ||
993ca6e0 SAS |
3718 | table = new_table; |
3719 | new_table = NULL; | |
2b324506 | 3720 | |
2fcc1e8a SAS |
3721 | set_remap_table_entry(iommu, devid, table); |
3722 | if (devid != alias) | |
3723 | set_remap_table_entry(iommu, alias, table); | |
2b324506 | 3724 | |
993ca6e0 | 3725 | out_wait: |
2b324506 JR |
3726 | iommu_completion_wait(iommu); |
3727 | ||
3728 | out_unlock: | |
ea6166f4 | 3729 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
2b324506 | 3730 | |
993ca6e0 SAS |
3731 | if (new_table) { |
3732 | kmem_cache_free(amd_iommu_irq_cache, new_table->table); | |
3733 | kfree(new_table); | |
3734 | } | |
2b324506 JR |
3735 | return table; |
3736 | } | |
3737 | ||
37946d95 | 3738 | static int alloc_irq_index(u16 devid, int count, bool align) |
2b324506 JR |
3739 | { |
3740 | struct irq_remap_table *table; | |
37946d95 | 3741 | int index, c, alignment = 1; |
2b324506 | 3742 | unsigned long flags; |
77bdab46 SS |
3743 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3744 | ||
3745 | if (!iommu) | |
3746 | return -ENODEV; | |
2b324506 | 3747 | |
fde65dd3 | 3748 | table = alloc_irq_table(devid); |
2b324506 JR |
3749 | if (!table) |
3750 | return -ENODEV; | |
3751 | ||
37946d95 JR |
3752 | if (align) |
3753 | alignment = roundup_pow_of_two(count); | |
3754 | ||
27790398 | 3755 | raw_spin_lock_irqsave(&table->lock, flags); |
2b324506 JR |
3756 | |
3757 | /* Scan table for free entries */ | |
37946d95 | 3758 | for (index = ALIGN(table->min_index, alignment), c = 0; |
07d1c91b | 3759 | index < MAX_IRQS_PER_TABLE;) { |
37946d95 | 3760 | if (!iommu->irte_ops->is_allocated(table, index)) { |
2b324506 | 3761 | c += 1; |
37946d95 JR |
3762 | } else { |
3763 | c = 0; | |
07d1c91b | 3764 | index = ALIGN(index + 1, alignment); |
37946d95 JR |
3765 | continue; |
3766 | } | |
2b324506 JR |
3767 | |
3768 | if (c == count) { | |
2b324506 | 3769 | for (; c != 0; --c) |
77bdab46 | 3770 | iommu->irte_ops->set_allocated(table, index - c + 1); |
2b324506 JR |
3771 | |
3772 | index -= count - 1; | |
2b324506 JR |
3773 | goto out; |
3774 | } | |
07d1c91b AW |
3775 | |
3776 | index++; | |
2b324506 JR |
3777 | } |
3778 | ||
3779 | index = -ENOSPC; | |
3780 | ||
3781 | out: | |
27790398 | 3782 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3783 | |
3784 | return index; | |
3785 | } | |
3786 | ||
b9fc6b56 SS |
3787 | static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, |
3788 | struct amd_ir_data *data) | |
2b324506 JR |
3789 | { |
3790 | struct irq_remap_table *table; | |
3791 | struct amd_iommu *iommu; | |
3792 | unsigned long flags; | |
880ac60e | 3793 | struct irte_ga *entry; |
2b324506 JR |
3794 | |
3795 | iommu = amd_iommu_rlookup_table[devid]; | |
3796 | if (iommu == NULL) | |
3797 | return -EINVAL; | |
3798 | ||
df42a04b | 3799 | table = get_irq_table(devid); |
2b324506 JR |
3800 | if (!table) |
3801 | return -ENOMEM; | |
3802 | ||
27790398 | 3803 | raw_spin_lock_irqsave(&table->lock, flags); |
880ac60e SS |
3804 | |
3805 | entry = (struct irte_ga *)table->table; | |
3806 | entry = &entry[index]; | |
3807 | entry->lo.fields_remap.valid = 0; | |
3808 | entry->hi.val = irte->hi.val; | |
3809 | entry->lo.val = irte->lo.val; | |
3810 | entry->lo.fields_remap.valid = 1; | |
b9fc6b56 SS |
3811 | if (data) |
3812 | data->ref = entry; | |
880ac60e | 3813 | |
27790398 | 3814 | raw_spin_unlock_irqrestore(&table->lock, flags); |
880ac60e SS |
3815 | |
3816 | iommu_flush_irt(iommu, devid); | |
3817 | iommu_completion_wait(iommu); | |
3818 | ||
3819 | return 0; | |
3820 | } | |
3821 | ||
3822 | static int modify_irte(u16 devid, int index, union irte *irte) | |
2b324506 JR |
3823 | { |
3824 | struct irq_remap_table *table; | |
3825 | struct amd_iommu *iommu; | |
3826 | unsigned long flags; | |
3827 | ||
3828 | iommu = amd_iommu_rlookup_table[devid]; | |
3829 | if (iommu == NULL) | |
3830 | return -EINVAL; | |
3831 | ||
df42a04b | 3832 | table = get_irq_table(devid); |
2b324506 JR |
3833 | if (!table) |
3834 | return -ENOMEM; | |
3835 | ||
27790398 | 3836 | raw_spin_lock_irqsave(&table->lock, flags); |
880ac60e | 3837 | table->table[index] = irte->val; |
27790398 | 3838 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3839 | |
3840 | iommu_flush_irt(iommu, devid); | |
3841 | iommu_completion_wait(iommu); | |
3842 | ||
3843 | return 0; | |
3844 | } | |
3845 | ||
3846 | static void free_irte(u16 devid, int index) | |
3847 | { | |
3848 | struct irq_remap_table *table; | |
3849 | struct amd_iommu *iommu; | |
3850 | unsigned long flags; | |
3851 | ||
3852 | iommu = amd_iommu_rlookup_table[devid]; | |
3853 | if (iommu == NULL) | |
3854 | return; | |
3855 | ||
df42a04b | 3856 | table = get_irq_table(devid); |
2b324506 JR |
3857 | if (!table) |
3858 | return; | |
3859 | ||
27790398 | 3860 | raw_spin_lock_irqsave(&table->lock, flags); |
77bdab46 | 3861 | iommu->irte_ops->clear_allocated(table, index); |
27790398 | 3862 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3863 | |
3864 | iommu_flush_irt(iommu, devid); | |
3865 | iommu_completion_wait(iommu); | |
3866 | } | |
3867 | ||
880ac60e SS |
3868 | static void irte_prepare(void *entry, |
3869 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3870 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3871 | { |
3872 | union irte *irte = (union irte *) entry; | |
3873 | ||
3874 | irte->val = 0; | |
3875 | irte->fields.vector = vector; | |
3876 | irte->fields.int_type = delivery_mode; | |
3877 | irte->fields.destination = dest_apicid; | |
3878 | irte->fields.dm = dest_mode; | |
3879 | irte->fields.valid = 1; | |
3880 | } | |
3881 | ||
3882 | static void irte_ga_prepare(void *entry, | |
3883 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3884 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3885 | { |
3886 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3887 | ||
3888 | irte->lo.val = 0; | |
3889 | irte->hi.val = 0; | |
880ac60e SS |
3890 | irte->lo.fields_remap.int_type = delivery_mode; |
3891 | irte->lo.fields_remap.dm = dest_mode; | |
3892 | irte->hi.fields.vector = vector; | |
90fcffd9 SS |
3893 | irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid); |
3894 | irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid); | |
880ac60e SS |
3895 | irte->lo.fields_remap.valid = 1; |
3896 | } | |
3897 | ||
3898 | static void irte_activate(void *entry, u16 devid, u16 index) | |
3899 | { | |
3900 | union irte *irte = (union irte *) entry; | |
3901 | ||
3902 | irte->fields.valid = 1; | |
3903 | modify_irte(devid, index, irte); | |
3904 | } | |
3905 | ||
3906 | static void irte_ga_activate(void *entry, u16 devid, u16 index) | |
3907 | { | |
3908 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3909 | ||
3910 | irte->lo.fields_remap.valid = 1; | |
b9fc6b56 | 3911 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3912 | } |
3913 | ||
3914 | static void irte_deactivate(void *entry, u16 devid, u16 index) | |
3915 | { | |
3916 | union irte *irte = (union irte *) entry; | |
3917 | ||
3918 | irte->fields.valid = 0; | |
3919 | modify_irte(devid, index, irte); | |
3920 | } | |
3921 | ||
3922 | static void irte_ga_deactivate(void *entry, u16 devid, u16 index) | |
3923 | { | |
3924 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3925 | ||
3926 | irte->lo.fields_remap.valid = 0; | |
b9fc6b56 | 3927 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3928 | } |
3929 | ||
3930 | static void irte_set_affinity(void *entry, u16 devid, u16 index, | |
3931 | u8 vector, u32 dest_apicid) | |
3932 | { | |
3933 | union irte *irte = (union irte *) entry; | |
3934 | ||
3935 | irte->fields.vector = vector; | |
3936 | irte->fields.destination = dest_apicid; | |
3937 | modify_irte(devid, index, irte); | |
3938 | } | |
3939 | ||
3940 | static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, | |
3941 | u8 vector, u32 dest_apicid) | |
3942 | { | |
3943 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3944 | ||
01ee04ba | 3945 | if (!irte->lo.fields_remap.guest_mode) { |
d98de49a | 3946 | irte->hi.fields.vector = vector; |
90fcffd9 SS |
3947 | irte->lo.fields_remap.destination = |
3948 | APICID_TO_IRTE_DEST_LO(dest_apicid); | |
3949 | irte->hi.fields.destination = | |
3950 | APICID_TO_IRTE_DEST_HI(dest_apicid); | |
d98de49a SS |
3951 | modify_irte_ga(devid, index, irte, NULL); |
3952 | } | |
880ac60e SS |
3953 | } |
3954 | ||
77bdab46 | 3955 | #define IRTE_ALLOCATED (~1U) |
880ac60e SS |
3956 | static void irte_set_allocated(struct irq_remap_table *table, int index) |
3957 | { | |
3958 | table->table[index] = IRTE_ALLOCATED; | |
3959 | } | |
3960 | ||
3961 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) | |
3962 | { | |
3963 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3964 | struct irte_ga *irte = &ptr[index]; | |
3965 | ||
3966 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3967 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3968 | irte->hi.fields.vector = 0xff; | |
3969 | } | |
3970 | ||
3971 | static bool irte_is_allocated(struct irq_remap_table *table, int index) | |
3972 | { | |
3973 | union irte *ptr = (union irte *)table->table; | |
3974 | union irte *irte = &ptr[index]; | |
3975 | ||
3976 | return irte->val != 0; | |
3977 | } | |
3978 | ||
3979 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) | |
3980 | { | |
3981 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3982 | struct irte_ga *irte = &ptr[index]; | |
3983 | ||
3984 | return irte->hi.fields.vector != 0; | |
3985 | } | |
3986 | ||
3987 | static void irte_clear_allocated(struct irq_remap_table *table, int index) | |
3988 | { | |
3989 | table->table[index] = 0; | |
3990 | } | |
3991 | ||
3992 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) | |
3993 | { | |
3994 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3995 | struct irte_ga *irte = &ptr[index]; | |
3996 | ||
3997 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3998 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3999 | } | |
4000 | ||
7c71d306 | 4001 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 4002 | { |
7c71d306 | 4003 | int devid = -1; |
5527de74 | 4004 | |
7c71d306 JL |
4005 | switch (info->type) { |
4006 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4007 | devid = get_ioapic_devid(info->ioapic_id); | |
4008 | break; | |
4009 | case X86_IRQ_ALLOC_TYPE_HPET: | |
4010 | devid = get_hpet_devid(info->hpet_id); | |
4011 | break; | |
4012 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4013 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4014 | devid = get_device_id(&info->msi_dev->dev); | |
4015 | break; | |
4016 | default: | |
4017 | BUG_ON(1); | |
4018 | break; | |
4019 | } | |
5527de74 | 4020 | |
7c71d306 JL |
4021 | return devid; |
4022 | } | |
5527de74 | 4023 | |
7c71d306 JL |
4024 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
4025 | { | |
4026 | struct amd_iommu *iommu; | |
4027 | int devid; | |
5527de74 | 4028 | |
7c71d306 JL |
4029 | if (!info) |
4030 | return NULL; | |
5527de74 | 4031 | |
7c71d306 JL |
4032 | devid = get_devid(info); |
4033 | if (devid >= 0) { | |
4034 | iommu = amd_iommu_rlookup_table[devid]; | |
4035 | if (iommu) | |
4036 | return iommu->ir_domain; | |
4037 | } | |
5527de74 | 4038 | |
7c71d306 | 4039 | return NULL; |
5527de74 JR |
4040 | } |
4041 | ||
7c71d306 | 4042 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 4043 | { |
7c71d306 JL |
4044 | struct amd_iommu *iommu; |
4045 | int devid; | |
5527de74 | 4046 | |
7c71d306 JL |
4047 | if (!info) |
4048 | return NULL; | |
5527de74 | 4049 | |
7c71d306 JL |
4050 | switch (info->type) { |
4051 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4052 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4053 | devid = get_device_id(&info->msi_dev->dev); | |
9ee35e4c | 4054 | if (devid < 0) |
7aba6cb9 WZ |
4055 | return NULL; |
4056 | ||
1fb260bc DC |
4057 | iommu = amd_iommu_rlookup_table[devid]; |
4058 | if (iommu) | |
4059 | return iommu->msi_domain; | |
7c71d306 JL |
4060 | break; |
4061 | default: | |
4062 | break; | |
4063 | } | |
5527de74 | 4064 | |
7c71d306 JL |
4065 | return NULL; |
4066 | } | |
5527de74 | 4067 | |
6b474b82 | 4068 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4069 | .prepare = amd_iommu_prepare, |
4070 | .enable = amd_iommu_enable, | |
4071 | .disable = amd_iommu_disable, | |
4072 | .reenable = amd_iommu_reenable, | |
4073 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
4074 | .get_ir_irq_domain = get_ir_irq_domain, |
4075 | .get_irq_domain = get_irq_domain, | |
4076 | }; | |
5527de74 | 4077 | |
7c71d306 JL |
4078 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
4079 | struct irq_cfg *irq_cfg, | |
4080 | struct irq_alloc_info *info, | |
4081 | int devid, int index, int sub_handle) | |
4082 | { | |
4083 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4084 | struct msi_msg *msg = &data->msi_entry; | |
7c71d306 | 4085 | struct IO_APIC_route_entry *entry; |
77bdab46 SS |
4086 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
4087 | ||
4088 | if (!iommu) | |
4089 | return; | |
5527de74 | 4090 | |
7c71d306 JL |
4091 | data->irq_2_irte.devid = devid; |
4092 | data->irq_2_irte.index = index + sub_handle; | |
77bdab46 SS |
4093 | iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, |
4094 | apic->irq_dest_mode, irq_cfg->vector, | |
d98de49a | 4095 | irq_cfg->dest_apicid, devid); |
7c71d306 JL |
4096 | |
4097 | switch (info->type) { | |
4098 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4099 | /* Setup IOAPIC entry */ | |
4100 | entry = info->ioapic_entry; | |
4101 | info->ioapic_entry = NULL; | |
4102 | memset(entry, 0, sizeof(*entry)); | |
4103 | entry->vector = index; | |
4104 | entry->mask = 0; | |
4105 | entry->trigger = info->ioapic_trigger; | |
4106 | entry->polarity = info->ioapic_polarity; | |
4107 | /* Mask level triggered irqs. */ | |
4108 | if (info->ioapic_trigger) | |
4109 | entry->mask = 1; | |
4110 | break; | |
5527de74 | 4111 | |
7c71d306 JL |
4112 | case X86_IRQ_ALLOC_TYPE_HPET: |
4113 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4114 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4115 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4116 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4117 | msg->data = irte_info->index; | |
4118 | break; | |
5527de74 | 4119 | |
7c71d306 JL |
4120 | default: |
4121 | BUG_ON(1); | |
4122 | break; | |
4123 | } | |
5527de74 JR |
4124 | } |
4125 | ||
880ac60e SS |
4126 | struct amd_irte_ops irte_32_ops = { |
4127 | .prepare = irte_prepare, | |
4128 | .activate = irte_activate, | |
4129 | .deactivate = irte_deactivate, | |
4130 | .set_affinity = irte_set_affinity, | |
4131 | .set_allocated = irte_set_allocated, | |
4132 | .is_allocated = irte_is_allocated, | |
4133 | .clear_allocated = irte_clear_allocated, | |
4134 | }; | |
4135 | ||
4136 | struct amd_irte_ops irte_128_ops = { | |
4137 | .prepare = irte_ga_prepare, | |
4138 | .activate = irte_ga_activate, | |
4139 | .deactivate = irte_ga_deactivate, | |
4140 | .set_affinity = irte_ga_set_affinity, | |
4141 | .set_allocated = irte_ga_set_allocated, | |
4142 | .is_allocated = irte_ga_is_allocated, | |
4143 | .clear_allocated = irte_ga_clear_allocated, | |
4144 | }; | |
4145 | ||
7c71d306 JL |
4146 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4147 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4148 | { |
7c71d306 JL |
4149 | struct irq_alloc_info *info = arg; |
4150 | struct irq_data *irq_data; | |
77bdab46 | 4151 | struct amd_ir_data *data = NULL; |
5527de74 | 4152 | struct irq_cfg *cfg; |
7c71d306 | 4153 | int i, ret, devid; |
29d049be | 4154 | int index; |
5527de74 | 4155 | |
7c71d306 JL |
4156 | if (!info) |
4157 | return -EINVAL; | |
4158 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4159 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4160 | return -EINVAL; |
4161 | ||
7c71d306 JL |
4162 | /* |
4163 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4164 | * to support multiple MSI interrupts. | |
4165 | */ | |
4166 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4167 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4168 | |
7c71d306 JL |
4169 | devid = get_devid(info); |
4170 | if (devid < 0) | |
4171 | return -EINVAL; | |
5527de74 | 4172 | |
7c71d306 JL |
4173 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4174 | if (ret < 0) | |
4175 | return ret; | |
0b4d48cb | 4176 | |
7c71d306 | 4177 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
fde65dd3 SAS |
4178 | struct irq_remap_table *table; |
4179 | struct amd_iommu *iommu; | |
4180 | ||
4181 | table = alloc_irq_table(devid); | |
4182 | if (table) { | |
4183 | if (!table->min_index) { | |
4184 | /* | |
4185 | * Keep the first 32 indexes free for IOAPIC | |
4186 | * interrupts. | |
4187 | */ | |
4188 | table->min_index = 32; | |
4189 | iommu = amd_iommu_rlookup_table[devid]; | |
4190 | for (i = 0; i < 32; ++i) | |
4191 | iommu->irte_ops->set_allocated(table, i); | |
4192 | } | |
4193 | WARN_ON(table->min_index != 32); | |
7c71d306 | 4194 | index = info->ioapic_pin; |
fde65dd3 | 4195 | } else { |
29d049be | 4196 | index = -ENOMEM; |
fde65dd3 | 4197 | } |
7c71d306 | 4198 | } else { |
53b9ec3f JR |
4199 | bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI); |
4200 | ||
4201 | index = alloc_irq_index(devid, nr_irqs, align); | |
7c71d306 JL |
4202 | } |
4203 | if (index < 0) { | |
4204 | pr_warn("Failed to allocate IRTE\n"); | |
517abe49 | 4205 | ret = index; |
7c71d306 JL |
4206 | goto out_free_parent; |
4207 | } | |
0b4d48cb | 4208 | |
7c71d306 JL |
4209 | for (i = 0; i < nr_irqs; i++) { |
4210 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4211 | cfg = irqd_cfg(irq_data); | |
4212 | if (!irq_data || !cfg) { | |
4213 | ret = -EINVAL; | |
4214 | goto out_free_data; | |
4215 | } | |
0b4d48cb | 4216 | |
a130e69f JR |
4217 | ret = -ENOMEM; |
4218 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4219 | if (!data) | |
4220 | goto out_free_data; | |
4221 | ||
77bdab46 SS |
4222 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
4223 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); | |
4224 | else | |
4225 | data->entry = kzalloc(sizeof(struct irte_ga), | |
4226 | GFP_KERNEL); | |
4227 | if (!data->entry) { | |
4228 | kfree(data); | |
4229 | goto out_free_data; | |
4230 | } | |
4231 | ||
7c71d306 JL |
4232 | irq_data->hwirq = (devid << 16) + i; |
4233 | irq_data->chip_data = data; | |
4234 | irq_data->chip = &amd_ir_chip; | |
4235 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4236 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4237 | } | |
a130e69f | 4238 | |
7c71d306 | 4239 | return 0; |
0b4d48cb | 4240 | |
7c71d306 JL |
4241 | out_free_data: |
4242 | for (i--; i >= 0; i--) { | |
4243 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4244 | if (irq_data) | |
4245 | kfree(irq_data->chip_data); | |
4246 | } | |
4247 | for (i = 0; i < nr_irqs; i++) | |
4248 | free_irte(devid, index + i); | |
4249 | out_free_parent: | |
4250 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4251 | return ret; | |
0b4d48cb JR |
4252 | } |
4253 | ||
7c71d306 JL |
4254 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4255 | unsigned int nr_irqs) | |
0b4d48cb | 4256 | { |
7c71d306 JL |
4257 | struct irq_2_irte *irte_info; |
4258 | struct irq_data *irq_data; | |
4259 | struct amd_ir_data *data; | |
4260 | int i; | |
0b4d48cb | 4261 | |
7c71d306 JL |
4262 | for (i = 0; i < nr_irqs; i++) { |
4263 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4264 | if (irq_data && irq_data->chip_data) { | |
4265 | data = irq_data->chip_data; | |
4266 | irte_info = &data->irq_2_irte; | |
4267 | free_irte(irte_info->devid, irte_info->index); | |
77bdab46 | 4268 | kfree(data->entry); |
7c71d306 JL |
4269 | kfree(data); |
4270 | } | |
4271 | } | |
4272 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4273 | } | |
0b4d48cb | 4274 | |
5ba204a1 TG |
4275 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, |
4276 | struct amd_ir_data *ir_data, | |
4277 | struct irq_2_irte *irte_info, | |
4278 | struct irq_cfg *cfg); | |
4279 | ||
72491643 | 4280 | static int irq_remapping_activate(struct irq_domain *domain, |
702cb0a0 | 4281 | struct irq_data *irq_data, bool reserve) |
7c71d306 JL |
4282 | { |
4283 | struct amd_ir_data *data = irq_data->chip_data; | |
4284 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4285 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
5ba204a1 | 4286 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
0b4d48cb | 4287 | |
5ba204a1 TG |
4288 | if (!iommu) |
4289 | return 0; | |
4290 | ||
4291 | iommu->irte_ops->activate(data->entry, irte_info->devid, | |
4292 | irte_info->index); | |
4293 | amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg); | |
72491643 | 4294 | return 0; |
0b4d48cb JR |
4295 | } |
4296 | ||
7c71d306 JL |
4297 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4298 | struct irq_data *irq_data) | |
0b4d48cb | 4299 | { |
7c71d306 JL |
4300 | struct amd_ir_data *data = irq_data->chip_data; |
4301 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4302 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
0b4d48cb | 4303 | |
77bdab46 SS |
4304 | if (iommu) |
4305 | iommu->irte_ops->deactivate(data->entry, irte_info->devid, | |
4306 | irte_info->index); | |
7c71d306 | 4307 | } |
0b4d48cb | 4308 | |
e2f9d45f | 4309 | static const struct irq_domain_ops amd_ir_domain_ops = { |
7c71d306 JL |
4310 | .alloc = irq_remapping_alloc, |
4311 | .free = irq_remapping_free, | |
4312 | .activate = irq_remapping_activate, | |
4313 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4314 | }; |
0b4d48cb | 4315 | |
b9fc6b56 SS |
4316 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) |
4317 | { | |
4318 | struct amd_iommu *iommu; | |
4319 | struct amd_iommu_pi_data *pi_data = vcpu_info; | |
4320 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; | |
4321 | struct amd_ir_data *ir_data = data->chip_data; | |
4322 | struct irte_ga *irte = (struct irte_ga *) ir_data->entry; | |
4323 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
d98de49a SS |
4324 | struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); |
4325 | ||
4326 | /* Note: | |
4327 | * This device has never been set up for guest mode. | |
4328 | * we should not modify the IRTE | |
4329 | */ | |
4330 | if (!dev_data || !dev_data->use_vapic) | |
4331 | return 0; | |
b9fc6b56 SS |
4332 | |
4333 | pi_data->ir_data = ir_data; | |
4334 | ||
4335 | /* Note: | |
4336 | * SVM tries to set up for VAPIC mode, but we are in | |
4337 | * legacy mode. So, we force legacy mode instead. | |
4338 | */ | |
4339 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
101fa037 | 4340 | pr_debug("%s: Fall back to using intr legacy remap\n", |
b9fc6b56 SS |
4341 | __func__); |
4342 | pi_data->is_guest_mode = false; | |
4343 | } | |
4344 | ||
4345 | iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4346 | if (iommu == NULL) | |
4347 | return -EINVAL; | |
4348 | ||
4349 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; | |
4350 | if (pi_data->is_guest_mode) { | |
4351 | /* Setting */ | |
4352 | irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); | |
4353 | irte->hi.fields.vector = vcpu_pi_info->vector; | |
efe6f241 | 4354 | irte->lo.fields_vapic.ga_log_intr = 1; |
b9fc6b56 SS |
4355 | irte->lo.fields_vapic.guest_mode = 1; |
4356 | irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; | |
4357 | ||
4358 | ir_data->cached_ga_tag = pi_data->ga_tag; | |
4359 | } else { | |
4360 | /* Un-Setting */ | |
4361 | struct irq_cfg *cfg = irqd_cfg(data); | |
4362 | ||
4363 | irte->hi.val = 0; | |
4364 | irte->lo.val = 0; | |
4365 | irte->hi.fields.vector = cfg->vector; | |
4366 | irte->lo.fields_remap.guest_mode = 0; | |
90fcffd9 SS |
4367 | irte->lo.fields_remap.destination = |
4368 | APICID_TO_IRTE_DEST_LO(cfg->dest_apicid); | |
4369 | irte->hi.fields.destination = | |
4370 | APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); | |
b9fc6b56 SS |
4371 | irte->lo.fields_remap.int_type = apic->irq_delivery_mode; |
4372 | irte->lo.fields_remap.dm = apic->irq_dest_mode; | |
4373 | ||
4374 | /* | |
4375 | * This communicates the ga_tag back to the caller | |
4376 | * so that it can do all the necessary clean up. | |
4377 | */ | |
4378 | ir_data->cached_ga_tag = 0; | |
4379 | } | |
4380 | ||
4381 | return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); | |
4382 | } | |
4383 | ||
5ba204a1 TG |
4384 | |
4385 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, | |
4386 | struct amd_ir_data *ir_data, | |
4387 | struct irq_2_irte *irte_info, | |
4388 | struct irq_cfg *cfg) | |
4389 | { | |
4390 | ||
4391 | /* | |
4392 | * Atomically updates the IRTE with the new destination, vector | |
4393 | * and flushes the interrupt entry cache. | |
4394 | */ | |
4395 | iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid, | |
4396 | irte_info->index, cfg->vector, | |
4397 | cfg->dest_apicid); | |
4398 | } | |
4399 | ||
7c71d306 JL |
4400 | static int amd_ir_set_affinity(struct irq_data *data, |
4401 | const struct cpumask *mask, bool force) | |
4402 | { | |
4403 | struct amd_ir_data *ir_data = data->chip_data; | |
4404 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4405 | struct irq_cfg *cfg = irqd_cfg(data); | |
4406 | struct irq_data *parent = data->parent_data; | |
77bdab46 | 4407 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
7c71d306 | 4408 | int ret; |
0b4d48cb | 4409 | |
77bdab46 SS |
4410 | if (!iommu) |
4411 | return -ENODEV; | |
4412 | ||
7c71d306 JL |
4413 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4414 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4415 | return ret; | |
0b4d48cb | 4416 | |
5ba204a1 | 4417 | amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg); |
7c71d306 JL |
4418 | /* |
4419 | * After this point, all the interrupts will start arriving | |
4420 | * at the new destination. So, time to cleanup the previous | |
4421 | * vector allocation. | |
4422 | */ | |
c6c2002b | 4423 | send_cleanup_vector(cfg); |
7c71d306 JL |
4424 | |
4425 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4426 | } |
4427 | ||
7c71d306 | 4428 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4429 | { |
7c71d306 | 4430 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4431 | |
7c71d306 JL |
4432 | *msg = ir_data->msi_entry; |
4433 | } | |
d976195c | 4434 | |
7c71d306 | 4435 | static struct irq_chip amd_ir_chip = { |
290be194 | 4436 | .name = "AMD-IR", |
8a2b7d14 | 4437 | .irq_ack = apic_ack_irq, |
290be194 TG |
4438 | .irq_set_affinity = amd_ir_set_affinity, |
4439 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, | |
4440 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
7c71d306 | 4441 | }; |
d976195c | 4442 | |
7c71d306 JL |
4443 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4444 | { | |
3e49a818 TG |
4445 | struct fwnode_handle *fn; |
4446 | ||
4447 | fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); | |
4448 | if (!fn) | |
4449 | return -ENOMEM; | |
4450 | iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu); | |
4451 | irq_domain_free_fwnode(fn); | |
7c71d306 JL |
4452 | if (!iommu->ir_domain) |
4453 | return -ENOMEM; | |
d976195c | 4454 | |
7c71d306 | 4455 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
3e49a818 TG |
4456 | iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain, |
4457 | "AMD-IR-MSI", | |
4458 | iommu->index); | |
d976195c JR |
4459 | return 0; |
4460 | } | |
8dbea3fd SS |
4461 | |
4462 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) | |
4463 | { | |
4464 | unsigned long flags; | |
4465 | struct amd_iommu *iommu; | |
4fde541c | 4466 | struct irq_remap_table *table; |
8dbea3fd SS |
4467 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; |
4468 | int devid = ir_data->irq_2_irte.devid; | |
4469 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
4470 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; | |
4471 | ||
4472 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
4473 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) | |
4474 | return 0; | |
4475 | ||
4476 | iommu = amd_iommu_rlookup_table[devid]; | |
4477 | if (!iommu) | |
4478 | return -ENODEV; | |
4479 | ||
4fde541c SAS |
4480 | table = get_irq_table(devid); |
4481 | if (!table) | |
8dbea3fd SS |
4482 | return -ENODEV; |
4483 | ||
4fde541c | 4484 | raw_spin_lock_irqsave(&table->lock, flags); |
8dbea3fd SS |
4485 | |
4486 | if (ref->lo.fields_vapic.guest_mode) { | |
90fcffd9 SS |
4487 | if (cpu >= 0) { |
4488 | ref->lo.fields_vapic.destination = | |
4489 | APICID_TO_IRTE_DEST_LO(cpu); | |
4490 | ref->hi.fields.destination = | |
4491 | APICID_TO_IRTE_DEST_HI(cpu); | |
4492 | } | |
8dbea3fd SS |
4493 | ref->lo.fields_vapic.is_run = is_run; |
4494 | barrier(); | |
4495 | } | |
4496 | ||
4fde541c | 4497 | raw_spin_unlock_irqrestore(&table->lock, flags); |
8dbea3fd SS |
4498 | |
4499 | iommu_flush_irt(iommu, devid); | |
4500 | iommu_completion_wait(iommu); | |
4501 | return 0; | |
4502 | } | |
4503 | EXPORT_SYMBOL(amd_iommu_update_ga); | |
2b324506 | 4504 | #endif |