Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
2bf9a0a1 | 22 | #include <linux/acpi.h> |
9a4d3bf5 | 23 | #include <linux/amba/bus.h> |
0076cd3d | 24 | #include <linux/platform_device.h> |
cb41ed85 | 25 | #include <linux/pci-ats.h> |
a66022c4 | 26 | #include <linux/bitmap.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
7f26508b | 28 | #include <linux/debugfs.h> |
b6c02715 | 29 | #include <linux/scatterlist.h> |
51491367 | 30 | #include <linux/dma-mapping.h> |
b6c02715 | 31 | #include <linux/iommu-helper.h> |
c156e347 | 32 | #include <linux/iommu.h> |
815b33fd | 33 | #include <linux/delay.h> |
403f81d8 | 34 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
35 | #include <linux/notifier.h> |
36 | #include <linux/export.h> | |
2b324506 JR |
37 | #include <linux/irq.h> |
38 | #include <linux/msi.h> | |
3b839a57 | 39 | #include <linux/dma-contiguous.h> |
7c71d306 | 40 | #include <linux/irqdomain.h> |
5f6bed50 | 41 | #include <linux/percpu.h> |
307d5851 | 42 | #include <linux/iova.h> |
2b324506 JR |
43 | #include <asm/irq_remapping.h> |
44 | #include <asm/io_apic.h> | |
45 | #include <asm/apic.h> | |
46 | #include <asm/hw_irq.h> | |
17f5b569 | 47 | #include <asm/msidef.h> |
b6c02715 | 48 | #include <asm/proto.h> |
46a7fa27 | 49 | #include <asm/iommu.h> |
1d9b16d1 | 50 | #include <asm/gart.h> |
27c2127a | 51 | #include <asm/dma.h> |
403f81d8 JR |
52 | |
53 | #include "amd_iommu_proto.h" | |
54 | #include "amd_iommu_types.h" | |
6b474b82 | 55 | #include "irq_remapping.h" |
b6c02715 | 56 | |
a869572c CH |
57 | #define AMD_IOMMU_MAPPING_ERROR 0 |
58 | ||
b6c02715 JR |
59 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) |
60 | ||
815b33fd | 61 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 62 | |
307d5851 JR |
63 | /* IO virtual address start page frame number */ |
64 | #define IOVA_START_PFN (1) | |
65 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
307d5851 | 66 | |
81cd07b9 JR |
67 | /* Reserved IOVA ranges */ |
68 | #define MSI_RANGE_START (0xfee00000) | |
69 | #define MSI_RANGE_END (0xfeefffff) | |
70 | #define HT_RANGE_START (0xfd00000000ULL) | |
71 | #define HT_RANGE_END (0xffffffffffULL) | |
72 | ||
aa3de9c0 OBC |
73 | /* |
74 | * This bitmap is used to advertise the page sizes our hardware support | |
75 | * to the IOMMU core, which will then use this information to split | |
76 | * physically contiguous memory regions it is mapping into page sizes | |
77 | * that we support. | |
78 | * | |
954e3dd8 | 79 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 80 | */ |
954e3dd8 | 81 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 82 | |
b6c02715 JR |
83 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
84 | ||
8fa5f802 JR |
85 | /* List of all available dev_data structures */ |
86 | static LIST_HEAD(dev_data_list); | |
87 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
88 | ||
6efed63b JR |
89 | LIST_HEAD(ioapic_map); |
90 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 91 | LIST_HEAD(acpihid_map); |
6efed63b | 92 | |
0feae533 JR |
93 | /* |
94 | * Domain for untranslated devices - only allocated | |
95 | * if iommu=pt passed on kernel cmd line. | |
96 | */ | |
b0119e87 | 97 | const struct iommu_ops amd_iommu_ops; |
26961efe | 98 | |
72e1dcc4 | 99 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 100 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 101 | |
5299709d | 102 | static const struct dma_map_ops amd_iommu_dma_ops; |
ac1534a5 | 103 | |
431b2a20 JR |
104 | /* |
105 | * general struct to manage commands send to an IOMMU | |
106 | */ | |
d6449536 | 107 | struct iommu_cmd { |
b6c02715 JR |
108 | u32 data[4]; |
109 | }; | |
110 | ||
05152a04 JR |
111 | struct kmem_cache *amd_iommu_irq_cache; |
112 | ||
04bfdd84 | 113 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 114 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 115 | static void detach_device(struct device *dev); |
9003d618 | 116 | static void iova_domain_flush_tlb(struct iova_domain *iovad); |
d4241a27 | 117 | |
007b74ba JR |
118 | /* |
119 | * Data container for a dma_ops specific protection domain | |
120 | */ | |
121 | struct dma_ops_domain { | |
122 | /* generic protection domain information */ | |
123 | struct protection_domain domain; | |
124 | ||
307d5851 JR |
125 | /* IOVA RB-Tree */ |
126 | struct iova_domain iovad; | |
007b74ba JR |
127 | }; |
128 | ||
81cd07b9 JR |
129 | static struct iova_domain reserved_iova_ranges; |
130 | static struct lock_class_key reserved_rbtree_key; | |
131 | ||
15898bbc JR |
132 | /**************************************************************************** |
133 | * | |
134 | * Helper functions | |
135 | * | |
136 | ****************************************************************************/ | |
137 | ||
2bf9a0a1 WZ |
138 | static inline int match_hid_uid(struct device *dev, |
139 | struct acpihid_map_entry *entry) | |
3f4b87b9 | 140 | { |
2bf9a0a1 WZ |
141 | const char *hid, *uid; |
142 | ||
143 | hid = acpi_device_hid(ACPI_COMPANION(dev)); | |
144 | uid = acpi_device_uid(ACPI_COMPANION(dev)); | |
145 | ||
146 | if (!hid || !(*hid)) | |
147 | return -ENODEV; | |
148 | ||
149 | if (!uid || !(*uid)) | |
150 | return strcmp(hid, entry->hid); | |
151 | ||
152 | if (!(*entry->uid)) | |
153 | return strcmp(hid, entry->hid); | |
154 | ||
155 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
3f4b87b9 JR |
156 | } |
157 | ||
2bf9a0a1 | 158 | static inline u16 get_pci_device_id(struct device *dev) |
e3156048 JR |
159 | { |
160 | struct pci_dev *pdev = to_pci_dev(dev); | |
161 | ||
162 | return PCI_DEVID(pdev->bus->number, pdev->devfn); | |
163 | } | |
164 | ||
2bf9a0a1 WZ |
165 | static inline int get_acpihid_device_id(struct device *dev, |
166 | struct acpihid_map_entry **entry) | |
167 | { | |
168 | struct acpihid_map_entry *p; | |
169 | ||
170 | list_for_each_entry(p, &acpihid_map, list) { | |
171 | if (!match_hid_uid(dev, p)) { | |
172 | if (entry) | |
173 | *entry = p; | |
174 | return p->devid; | |
175 | } | |
176 | } | |
177 | return -EINVAL; | |
178 | } | |
179 | ||
180 | static inline int get_device_id(struct device *dev) | |
181 | { | |
182 | int devid; | |
183 | ||
184 | if (dev_is_pci(dev)) | |
185 | devid = get_pci_device_id(dev); | |
186 | else | |
187 | devid = get_acpihid_device_id(dev, NULL); | |
188 | ||
189 | return devid; | |
190 | } | |
191 | ||
3f4b87b9 JR |
192 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
193 | { | |
194 | return container_of(dom, struct protection_domain, domain); | |
195 | } | |
196 | ||
b3311b06 JR |
197 | static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain) |
198 | { | |
199 | BUG_ON(domain->flags != PD_DMA_OPS_MASK); | |
200 | return container_of(domain, struct dma_ops_domain, domain); | |
201 | } | |
202 | ||
f62dda66 | 203 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
204 | { |
205 | struct iommu_dev_data *dev_data; | |
206 | unsigned long flags; | |
207 | ||
208 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
209 | if (!dev_data) | |
210 | return NULL; | |
211 | ||
f62dda66 | 212 | dev_data->devid = devid; |
8fa5f802 JR |
213 | |
214 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
215 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
216 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
217 | ||
30bf2df6 JR |
218 | ratelimit_default_init(&dev_data->rs); |
219 | ||
8fa5f802 JR |
220 | return dev_data; |
221 | } | |
222 | ||
3b03bb74 JR |
223 | static struct iommu_dev_data *search_dev_data(u16 devid) |
224 | { | |
225 | struct iommu_dev_data *dev_data; | |
226 | unsigned long flags; | |
227 | ||
228 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
229 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
230 | if (dev_data->devid == devid) | |
231 | goto out_unlock; | |
232 | } | |
233 | ||
234 | dev_data = NULL; | |
235 | ||
236 | out_unlock: | |
237 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
238 | ||
239 | return dev_data; | |
240 | } | |
241 | ||
e3156048 JR |
242 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
243 | { | |
244 | *(u16 *)data = alias; | |
245 | return 0; | |
246 | } | |
247 | ||
248 | static u16 get_alias(struct device *dev) | |
249 | { | |
250 | struct pci_dev *pdev = to_pci_dev(dev); | |
251 | u16 devid, ivrs_alias, pci_alias; | |
252 | ||
6c0b43df | 253 | /* The callers make sure that get_device_id() does not fail here */ |
e3156048 JR |
254 | devid = get_device_id(dev); |
255 | ivrs_alias = amd_iommu_alias_table[devid]; | |
256 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
257 | ||
258 | if (ivrs_alias == pci_alias) | |
259 | return ivrs_alias; | |
260 | ||
261 | /* | |
262 | * DMA alias showdown | |
263 | * | |
264 | * The IVRS is fairly reliable in telling us about aliases, but it | |
265 | * can't know about every screwy device. If we don't have an IVRS | |
266 | * reported alias, use the PCI reported alias. In that case we may | |
267 | * still need to initialize the rlookup and dev_table entries if the | |
268 | * alias is to a non-existent device. | |
269 | */ | |
270 | if (ivrs_alias == devid) { | |
271 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
272 | amd_iommu_rlookup_table[pci_alias] = | |
273 | amd_iommu_rlookup_table[devid]; | |
274 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
275 | amd_iommu_dev_table[devid].data, | |
276 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
277 | } | |
278 | ||
279 | return pci_alias; | |
280 | } | |
281 | ||
282 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
283 | "for device %s[%04x:%04x], kernel reported alias " | |
284 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
285 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
286 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
287 | PCI_FUNC(pci_alias)); | |
288 | ||
289 | /* | |
290 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
291 | * bus, then the IVRS table may know about a quirk that we don't. | |
292 | */ | |
293 | if (pci_alias == devid && | |
294 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
7afd16f8 | 295 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); |
e3156048 JR |
296 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", |
297 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
298 | dev_name(dev)); | |
299 | } | |
300 | ||
301 | return ivrs_alias; | |
302 | } | |
303 | ||
3b03bb74 JR |
304 | static struct iommu_dev_data *find_dev_data(u16 devid) |
305 | { | |
306 | struct iommu_dev_data *dev_data; | |
df3f7a6e | 307 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3b03bb74 JR |
308 | |
309 | dev_data = search_dev_data(devid); | |
310 | ||
df3f7a6e | 311 | if (dev_data == NULL) { |
3b03bb74 JR |
312 | dev_data = alloc_dev_data(devid); |
313 | ||
df3f7a6e BH |
314 | if (translation_pre_enabled(iommu)) |
315 | dev_data->defer_attach = true; | |
316 | } | |
317 | ||
3b03bb74 JR |
318 | return dev_data; |
319 | } | |
320 | ||
daae2d25 | 321 | struct iommu_dev_data *get_dev_data(struct device *dev) |
657cbb6b JR |
322 | { |
323 | return dev->archdata.iommu; | |
324 | } | |
daae2d25 | 325 | EXPORT_SYMBOL(get_dev_data); |
657cbb6b | 326 | |
b097d11a WZ |
327 | /* |
328 | * Find or create an IOMMU group for a acpihid device. | |
329 | */ | |
330 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 331 | { |
b097d11a | 332 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 333 | int devid; |
b097d11a WZ |
334 | |
335 | devid = get_acpihid_device_id(dev, &entry); | |
336 | if (devid < 0) | |
337 | return ERR_PTR(devid); | |
338 | ||
339 | list_for_each_entry(p, &acpihid_map, list) { | |
340 | if ((devid == p->devid) && p->group) | |
341 | entry->group = p->group; | |
342 | } | |
343 | ||
344 | if (!entry->group) | |
345 | entry->group = generic_device_group(dev); | |
f2f101f6 RM |
346 | else |
347 | iommu_group_ref_get(entry->group); | |
b097d11a WZ |
348 | |
349 | return entry->group; | |
657cbb6b JR |
350 | } |
351 | ||
5abcdba4 JR |
352 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
353 | { | |
354 | static const int caps[] = { | |
355 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
356 | PCI_EXT_CAP_ID_PRI, |
357 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
358 | }; |
359 | int i, pos; | |
360 | ||
361 | for (i = 0; i < 3; ++i) { | |
362 | pos = pci_find_ext_capability(pdev, caps[i]); | |
363 | if (pos == 0) | |
364 | return false; | |
365 | } | |
366 | ||
367 | return true; | |
368 | } | |
369 | ||
6a113ddc JR |
370 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
371 | { | |
372 | struct iommu_dev_data *dev_data; | |
373 | ||
374 | dev_data = get_dev_data(&pdev->dev); | |
375 | ||
376 | return dev_data->errata & (1 << erratum) ? true : false; | |
377 | } | |
378 | ||
98fc5a69 JR |
379 | /* |
380 | * This function checks if the driver got a valid device from the caller to | |
381 | * avoid dereferencing invalid pointers. | |
382 | */ | |
383 | static bool check_device(struct device *dev) | |
384 | { | |
7aba6cb9 | 385 | int devid; |
98fc5a69 JR |
386 | |
387 | if (!dev || !dev->dma_mask) | |
388 | return false; | |
389 | ||
98fc5a69 | 390 | devid = get_device_id(dev); |
9ee35e4c | 391 | if (devid < 0) |
7aba6cb9 | 392 | return false; |
98fc5a69 JR |
393 | |
394 | /* Out of our scope? */ | |
395 | if (devid > amd_iommu_last_bdf) | |
396 | return false; | |
397 | ||
398 | if (amd_iommu_rlookup_table[devid] == NULL) | |
399 | return false; | |
400 | ||
401 | return true; | |
402 | } | |
403 | ||
25b11ce2 | 404 | static void init_iommu_group(struct device *dev) |
2851db21 | 405 | { |
2851db21 | 406 | struct iommu_group *group; |
2851db21 | 407 | |
65d5352f | 408 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
409 | if (IS_ERR(group)) |
410 | return; | |
411 | ||
0bb6e243 | 412 | iommu_group_put(group); |
eb9c9527 AW |
413 | } |
414 | ||
415 | static int iommu_init_device(struct device *dev) | |
416 | { | |
eb9c9527 | 417 | struct iommu_dev_data *dev_data; |
39ab9555 | 418 | struct amd_iommu *iommu; |
7aba6cb9 | 419 | int devid; |
eb9c9527 AW |
420 | |
421 | if (dev->archdata.iommu) | |
422 | return 0; | |
423 | ||
7aba6cb9 | 424 | devid = get_device_id(dev); |
9ee35e4c | 425 | if (devid < 0) |
7aba6cb9 WZ |
426 | return devid; |
427 | ||
39ab9555 JR |
428 | iommu = amd_iommu_rlookup_table[devid]; |
429 | ||
7aba6cb9 | 430 | dev_data = find_dev_data(devid); |
eb9c9527 AW |
431 | if (!dev_data) |
432 | return -ENOMEM; | |
433 | ||
e3156048 JR |
434 | dev_data->alias = get_alias(dev); |
435 | ||
2bf9a0a1 | 436 | if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { |
5abcdba4 JR |
437 | struct amd_iommu *iommu; |
438 | ||
2bf9a0a1 | 439 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
440 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
441 | } | |
442 | ||
657cbb6b JR |
443 | dev->archdata.iommu = dev_data; |
444 | ||
e3d10af1 | 445 | iommu_device_link(&iommu->iommu, dev); |
066f2e98 | 446 | |
657cbb6b JR |
447 | return 0; |
448 | } | |
449 | ||
26018874 JR |
450 | static void iommu_ignore_device(struct device *dev) |
451 | { | |
7aba6cb9 WZ |
452 | u16 alias; |
453 | int devid; | |
26018874 JR |
454 | |
455 | devid = get_device_id(dev); | |
9ee35e4c | 456 | if (devid < 0) |
7aba6cb9 WZ |
457 | return; |
458 | ||
e3156048 | 459 | alias = get_alias(dev); |
26018874 JR |
460 | |
461 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
462 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
463 | ||
464 | amd_iommu_rlookup_table[devid] = NULL; | |
465 | amd_iommu_rlookup_table[alias] = NULL; | |
466 | } | |
467 | ||
657cbb6b JR |
468 | static void iommu_uninit_device(struct device *dev) |
469 | { | |
7aba6cb9 | 470 | struct iommu_dev_data *dev_data; |
39ab9555 JR |
471 | struct amd_iommu *iommu; |
472 | int devid; | |
c1931090 | 473 | |
7aba6cb9 | 474 | devid = get_device_id(dev); |
9ee35e4c | 475 | if (devid < 0) |
7aba6cb9 | 476 | return; |
c1931090 | 477 | |
39ab9555 JR |
478 | iommu = amd_iommu_rlookup_table[devid]; |
479 | ||
7aba6cb9 | 480 | dev_data = search_dev_data(devid); |
c1931090 AW |
481 | if (!dev_data) |
482 | return; | |
483 | ||
b6809ee5 JR |
484 | if (dev_data->domain) |
485 | detach_device(dev); | |
486 | ||
e3d10af1 | 487 | iommu_device_unlink(&iommu->iommu, dev); |
066f2e98 | 488 | |
9dcd6130 AW |
489 | iommu_group_remove_device(dev); |
490 | ||
aafd8ba0 | 491 | /* Remove dma-ops */ |
5657933d | 492 | dev->dma_ops = NULL; |
aafd8ba0 | 493 | |
8fa5f802 | 494 | /* |
c1931090 AW |
495 | * We keep dev_data around for unplugged devices and reuse it when the |
496 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 497 | */ |
657cbb6b | 498 | } |
b7cc9554 | 499 | |
a80dc3e0 JR |
500 | /**************************************************************************** |
501 | * | |
502 | * Interrupt handling functions | |
503 | * | |
504 | ****************************************************************************/ | |
505 | ||
e3e59876 JR |
506 | static void dump_dte_entry(u16 devid) |
507 | { | |
508 | int i; | |
509 | ||
ee6c2868 JR |
510 | for (i = 0; i < 4; ++i) |
511 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
512 | amd_iommu_dev_table[devid].data[i]); |
513 | } | |
514 | ||
945b4ac4 JR |
515 | static void dump_command(unsigned long phys_addr) |
516 | { | |
2543a786 | 517 | struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr); |
945b4ac4 JR |
518 | int i; |
519 | ||
520 | for (i = 0; i < 4; ++i) | |
521 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
522 | } | |
523 | ||
30bf2df6 JR |
524 | static void amd_iommu_report_page_fault(u16 devid, u16 domain_id, |
525 | u64 address, int flags) | |
526 | { | |
527 | struct iommu_dev_data *dev_data = NULL; | |
528 | struct pci_dev *pdev; | |
529 | ||
d5bf0f4f SK |
530 | pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid), |
531 | devid & 0xff); | |
30bf2df6 JR |
532 | if (pdev) |
533 | dev_data = get_dev_data(&pdev->dev); | |
534 | ||
535 | if (dev_data && __ratelimit(&dev_data->rs)) { | |
536 | dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
537 | domain_id, address, flags); | |
538 | } else if (printk_ratelimit()) { | |
539 | pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
540 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
541 | domain_id, address, flags); | |
542 | } | |
543 | ||
544 | if (pdev) | |
545 | pci_dev_put(pdev); | |
546 | } | |
547 | ||
a345b23b | 548 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 549 | { |
3d06fca8 JR |
550 | int type, devid, domid, flags; |
551 | volatile u32 *event = __evt; | |
552 | int count = 0; | |
553 | u64 address; | |
554 | ||
555 | retry: | |
556 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
557 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
558 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
559 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
560 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
561 | ||
562 | if (type == 0) { | |
563 | /* Did we hit the erratum? */ | |
564 | if (++count == LOOP_TIMEOUT) { | |
565 | pr_err("AMD-Vi: No event written to event log\n"); | |
566 | return; | |
567 | } | |
568 | udelay(1); | |
569 | goto retry; | |
570 | } | |
90008ee4 | 571 | |
30bf2df6 JR |
572 | if (type == EVENT_TYPE_IO_FAULT) { |
573 | amd_iommu_report_page_fault(devid, domid, address, flags); | |
574 | return; | |
575 | } else { | |
576 | printk(KERN_ERR "AMD-Vi: Event logged ["); | |
577 | } | |
90008ee4 JR |
578 | |
579 | switch (type) { | |
580 | case EVENT_TYPE_ILL_DEV: | |
581 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
582 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 583 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 584 | address, flags); |
e3e59876 | 585 | dump_dte_entry(devid); |
90008ee4 | 586 | break; |
90008ee4 JR |
587 | case EVENT_TYPE_DEV_TAB_ERR: |
588 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
589 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 590 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
591 | address, flags); |
592 | break; | |
593 | case EVENT_TYPE_PAGE_TAB_ERR: | |
594 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
595 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 596 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
597 | domid, address, flags); |
598 | break; | |
599 | case EVENT_TYPE_ILL_CMD: | |
600 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 601 | dump_command(address); |
90008ee4 JR |
602 | break; |
603 | case EVENT_TYPE_CMD_HARD_ERR: | |
604 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
605 | "flags=0x%04x]\n", address, flags); | |
606 | break; | |
607 | case EVENT_TYPE_IOTLB_INV_TO: | |
608 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
609 | "address=0x%016llx]\n", | |
c5081cd7 | 610 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
611 | address); |
612 | break; | |
613 | case EVENT_TYPE_INV_DEV_REQ: | |
614 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
615 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 616 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
617 | address, flags); |
618 | break; | |
619 | default: | |
f9fc049e GH |
620 | printk(KERN_ERR "UNKNOWN type=0x%02x event[0]=0x%08x " |
621 | "event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n", | |
622 | type, event[0], event[1], event[2], event[3]); | |
90008ee4 | 623 | } |
3d06fca8 JR |
624 | |
625 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
626 | } |
627 | ||
628 | static void iommu_poll_events(struct amd_iommu *iommu) | |
629 | { | |
630 | u32 head, tail; | |
90008ee4 JR |
631 | |
632 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
633 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
634 | ||
635 | while (head != tail) { | |
a345b23b | 636 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 637 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
638 | } |
639 | ||
640 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
641 | } |
642 | ||
eee53537 | 643 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
644 | { |
645 | struct amd_iommu_fault fault; | |
72e1dcc4 | 646 | |
72e1dcc4 JR |
647 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
648 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
649 | return; | |
650 | } | |
651 | ||
652 | fault.address = raw[1]; | |
653 | fault.pasid = PPR_PASID(raw[0]); | |
654 | fault.device_id = PPR_DEVID(raw[0]); | |
655 | fault.tag = PPR_TAG(raw[0]); | |
656 | fault.flags = PPR_FLAGS(raw[0]); | |
657 | ||
72e1dcc4 JR |
658 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
659 | } | |
660 | ||
661 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
662 | { | |
72e1dcc4 JR |
663 | u32 head, tail; |
664 | ||
665 | if (iommu->ppr_log == NULL) | |
666 | return; | |
667 | ||
72e1dcc4 JR |
668 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
669 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
670 | ||
671 | while (head != tail) { | |
eee53537 JR |
672 | volatile u64 *raw; |
673 | u64 entry[2]; | |
674 | int i; | |
675 | ||
676 | raw = (u64 *)(iommu->ppr_log + head); | |
677 | ||
678 | /* | |
679 | * Hardware bug: Interrupt may arrive before the entry is | |
680 | * written to memory. If this happens we need to wait for the | |
681 | * entry to arrive. | |
682 | */ | |
683 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
684 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
685 | break; | |
686 | udelay(1); | |
687 | } | |
72e1dcc4 | 688 | |
eee53537 JR |
689 | /* Avoid memcpy function-call overhead */ |
690 | entry[0] = raw[0]; | |
691 | entry[1] = raw[1]; | |
72e1dcc4 | 692 | |
eee53537 JR |
693 | /* |
694 | * To detect the hardware bug we need to clear the entry | |
695 | * back to zero. | |
696 | */ | |
697 | raw[0] = raw[1] = 0UL; | |
698 | ||
699 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
700 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
701 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 702 | |
eee53537 JR |
703 | /* Handle PPR entry */ |
704 | iommu_handle_ppr_entry(iommu, entry); | |
705 | ||
eee53537 JR |
706 | /* Refresh ring-buffer information */ |
707 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
708 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
709 | } | |
72e1dcc4 JR |
710 | } |
711 | ||
bd6fcefc SS |
712 | #ifdef CONFIG_IRQ_REMAP |
713 | static int (*iommu_ga_log_notifier)(u32); | |
714 | ||
715 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) | |
716 | { | |
717 | iommu_ga_log_notifier = notifier; | |
718 | ||
719 | return 0; | |
720 | } | |
721 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); | |
722 | ||
723 | static void iommu_poll_ga_log(struct amd_iommu *iommu) | |
724 | { | |
725 | u32 head, tail, cnt = 0; | |
726 | ||
727 | if (iommu->ga_log == NULL) | |
728 | return; | |
729 | ||
730 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
731 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); | |
732 | ||
733 | while (head != tail) { | |
734 | volatile u64 *raw; | |
735 | u64 log_entry; | |
736 | ||
737 | raw = (u64 *)(iommu->ga_log + head); | |
738 | cnt++; | |
739 | ||
740 | /* Avoid memcpy function-call overhead */ | |
741 | log_entry = *raw; | |
742 | ||
743 | /* Update head pointer of hardware ring-buffer */ | |
744 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; | |
745 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
746 | ||
747 | /* Handle GA entry */ | |
748 | switch (GA_REQ_TYPE(log_entry)) { | |
749 | case GA_GUEST_NR: | |
750 | if (!iommu_ga_log_notifier) | |
751 | break; | |
752 | ||
753 | pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n", | |
754 | __func__, GA_DEVID(log_entry), | |
755 | GA_TAG(log_entry)); | |
756 | ||
757 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) | |
758 | pr_err("AMD-Vi: GA log notifier failed.\n"); | |
759 | break; | |
760 | default: | |
761 | break; | |
762 | } | |
763 | } | |
764 | } | |
765 | #endif /* CONFIG_IRQ_REMAP */ | |
766 | ||
767 | #define AMD_IOMMU_INT_MASK \ | |
768 | (MMIO_STATUS_EVT_INT_MASK | \ | |
769 | MMIO_STATUS_PPR_INT_MASK | \ | |
770 | MMIO_STATUS_GALOG_INT_MASK) | |
771 | ||
72fe00f0 | 772 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 773 | { |
3f398bc7 SS |
774 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
775 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 776 | |
bd6fcefc SS |
777 | while (status & AMD_IOMMU_INT_MASK) { |
778 | /* Enable EVT and PPR and GA interrupts again */ | |
779 | writel(AMD_IOMMU_INT_MASK, | |
3f398bc7 | 780 | iommu->mmio_base + MMIO_STATUS_OFFSET); |
90008ee4 | 781 | |
3f398bc7 SS |
782 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
783 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
784 | iommu_poll_events(iommu); | |
785 | } | |
90008ee4 | 786 | |
3f398bc7 SS |
787 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
788 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
789 | iommu_poll_ppr_log(iommu); | |
790 | } | |
90008ee4 | 791 | |
bd6fcefc SS |
792 | #ifdef CONFIG_IRQ_REMAP |
793 | if (status & MMIO_STATUS_GALOG_INT_MASK) { | |
794 | pr_devel("AMD-Vi: Processing IOMMU GA Log\n"); | |
795 | iommu_poll_ga_log(iommu); | |
796 | } | |
797 | #endif | |
798 | ||
3f398bc7 SS |
799 | /* |
800 | * Hardware bug: ERBT1312 | |
801 | * When re-enabling interrupt (by writing 1 | |
802 | * to clear the bit), the hardware might also try to set | |
803 | * the interrupt bit in the event status register. | |
804 | * In this scenario, the bit will be set, and disable | |
805 | * subsequent interrupts. | |
806 | * | |
807 | * Workaround: The IOMMU driver should read back the | |
808 | * status register and check if the interrupt bits are cleared. | |
809 | * If not, driver will need to go through the interrupt handler | |
810 | * again and re-clear the bits | |
811 | */ | |
812 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
813 | } | |
90008ee4 | 814 | return IRQ_HANDLED; |
a80dc3e0 JR |
815 | } |
816 | ||
72fe00f0 JR |
817 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
818 | { | |
819 | return IRQ_WAKE_THREAD; | |
820 | } | |
821 | ||
431b2a20 JR |
822 | /**************************************************************************** |
823 | * | |
824 | * IOMMU command queuing functions | |
825 | * | |
826 | ****************************************************************************/ | |
827 | ||
ac0ea6e9 JR |
828 | static int wait_on_sem(volatile u64 *sem) |
829 | { | |
830 | int i = 0; | |
831 | ||
832 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
833 | udelay(1); | |
834 | i += 1; | |
835 | } | |
836 | ||
837 | if (i == LOOP_TIMEOUT) { | |
838 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
839 | return -EIO; | |
840 | } | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
d334a563 | 846 | struct iommu_cmd *cmd) |
a19ae1ec | 847 | { |
a19ae1ec JR |
848 | u8 *target; |
849 | ||
d334a563 TL |
850 | target = iommu->cmd_buf + iommu->cmd_buf_tail; |
851 | ||
852 | iommu->cmd_buf_tail += sizeof(*cmd); | |
853 | iommu->cmd_buf_tail %= CMD_BUFFER_SIZE; | |
ac0ea6e9 JR |
854 | |
855 | /* Copy command to buffer */ | |
856 | memcpy(target, cmd, sizeof(*cmd)); | |
857 | ||
858 | /* Tell the IOMMU about it */ | |
d334a563 | 859 | writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 860 | } |
a19ae1ec | 861 | |
815b33fd | 862 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 863 | { |
2543a786 TL |
864 | u64 paddr = iommu_virt_to_phys((void *)address); |
865 | ||
815b33fd JR |
866 | WARN_ON(address & 0x7ULL); |
867 | ||
ded46737 | 868 | memset(cmd, 0, sizeof(*cmd)); |
2543a786 TL |
869 | cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; |
870 | cmd->data[1] = upper_32_bits(paddr); | |
815b33fd | 871 | cmd->data[2] = 1; |
ded46737 JR |
872 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
873 | } | |
874 | ||
94fe79e2 JR |
875 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
876 | { | |
877 | memset(cmd, 0, sizeof(*cmd)); | |
878 | cmd->data[0] = devid; | |
879 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
880 | } | |
881 | ||
11b6402c JR |
882 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
883 | size_t size, u16 domid, int pde) | |
884 | { | |
885 | u64 pages; | |
ae0cbbb1 | 886 | bool s; |
11b6402c JR |
887 | |
888 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 889 | s = false; |
11b6402c JR |
890 | |
891 | if (pages > 1) { | |
892 | /* | |
893 | * If we have to flush more than one page, flush all | |
894 | * TLB entries for this domain | |
895 | */ | |
896 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 897 | s = true; |
11b6402c JR |
898 | } |
899 | ||
900 | address &= PAGE_MASK; | |
901 | ||
902 | memset(cmd, 0, sizeof(*cmd)); | |
903 | cmd->data[1] |= domid; | |
904 | cmd->data[2] = lower_32_bits(address); | |
905 | cmd->data[3] = upper_32_bits(address); | |
906 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
907 | if (s) /* size bit - we flush more than one 4kb page */ | |
908 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 909 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
910 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
911 | } | |
912 | ||
cb41ed85 JR |
913 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
914 | u64 address, size_t size) | |
915 | { | |
916 | u64 pages; | |
ae0cbbb1 | 917 | bool s; |
cb41ed85 JR |
918 | |
919 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 920 | s = false; |
cb41ed85 JR |
921 | |
922 | if (pages > 1) { | |
923 | /* | |
924 | * If we have to flush more than one page, flush all | |
925 | * TLB entries for this domain | |
926 | */ | |
927 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 928 | s = true; |
cb41ed85 JR |
929 | } |
930 | ||
931 | address &= PAGE_MASK; | |
932 | ||
933 | memset(cmd, 0, sizeof(*cmd)); | |
934 | cmd->data[0] = devid; | |
935 | cmd->data[0] |= (qdep & 0xff) << 24; | |
936 | cmd->data[1] = devid; | |
937 | cmd->data[2] = lower_32_bits(address); | |
938 | cmd->data[3] = upper_32_bits(address); | |
939 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
940 | if (s) | |
941 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
942 | } | |
943 | ||
22e266c7 JR |
944 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
945 | u64 address, bool size) | |
946 | { | |
947 | memset(cmd, 0, sizeof(*cmd)); | |
948 | ||
949 | address &= ~(0xfffULL); | |
950 | ||
a919a018 | 951 | cmd->data[0] = pasid; |
22e266c7 JR |
952 | cmd->data[1] = domid; |
953 | cmd->data[2] = lower_32_bits(address); | |
954 | cmd->data[3] = upper_32_bits(address); | |
955 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
956 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
957 | if (size) | |
958 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
959 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
960 | } | |
961 | ||
962 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
963 | int qdep, u64 address, bool size) | |
964 | { | |
965 | memset(cmd, 0, sizeof(*cmd)); | |
966 | ||
967 | address &= ~(0xfffULL); | |
968 | ||
969 | cmd->data[0] = devid; | |
e8d2d82d | 970 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
971 | cmd->data[0] |= (qdep & 0xff) << 24; |
972 | cmd->data[1] = devid; | |
e8d2d82d | 973 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
974 | cmd->data[2] = lower_32_bits(address); |
975 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
976 | cmd->data[3] = upper_32_bits(address); | |
977 | if (size) | |
978 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
979 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
980 | } | |
981 | ||
c99afa25 JR |
982 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
983 | int status, int tag, bool gn) | |
984 | { | |
985 | memset(cmd, 0, sizeof(*cmd)); | |
986 | ||
987 | cmd->data[0] = devid; | |
988 | if (gn) { | |
a919a018 | 989 | cmd->data[1] = pasid; |
c99afa25 JR |
990 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
991 | } | |
992 | cmd->data[3] = tag & 0x1ff; | |
993 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
994 | ||
995 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
996 | } | |
997 | ||
58fc7f14 JR |
998 | static void build_inv_all(struct iommu_cmd *cmd) |
999 | { | |
1000 | memset(cmd, 0, sizeof(*cmd)); | |
1001 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
1002 | } |
1003 | ||
7ef2798d JR |
1004 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
1005 | { | |
1006 | memset(cmd, 0, sizeof(*cmd)); | |
1007 | cmd->data[0] = devid; | |
1008 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1009 | } | |
1010 | ||
431b2a20 | 1011 | /* |
431b2a20 | 1012 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 1013 | * hardware about the new command. |
431b2a20 | 1014 | */ |
4bf5beef JR |
1015 | static int __iommu_queue_command_sync(struct amd_iommu *iommu, |
1016 | struct iommu_cmd *cmd, | |
1017 | bool sync) | |
a19ae1ec | 1018 | { |
23e967e1 | 1019 | unsigned int count = 0; |
d334a563 | 1020 | u32 left, next_tail; |
a19ae1ec | 1021 | |
d334a563 | 1022 | next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 | 1023 | again: |
d334a563 | 1024 | left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; |
a19ae1ec | 1025 | |
432abf68 | 1026 | if (left <= 0x20) { |
23e967e1 TL |
1027 | /* Skip udelay() the first time around */ |
1028 | if (count++) { | |
1029 | if (count == LOOP_TIMEOUT) { | |
1030 | pr_err("AMD-Vi: Command buffer timeout\n"); | |
1031 | return -EIO; | |
1032 | } | |
da49f6df | 1033 | |
23e967e1 TL |
1034 | udelay(1); |
1035 | } | |
ac0ea6e9 | 1036 | |
23e967e1 TL |
1037 | /* Update head and recheck remaining space */ |
1038 | iommu->cmd_buf_head = readl(iommu->mmio_base + | |
1039 | MMIO_CMD_HEAD_OFFSET); | |
ac0ea6e9 JR |
1040 | |
1041 | goto again; | |
8d201968 JR |
1042 | } |
1043 | ||
d334a563 | 1044 | copy_cmd_to_buffer(iommu, cmd); |
ac0ea6e9 | 1045 | |
23e967e1 | 1046 | /* Do we need to make sure all commands are processed? */ |
f1ca1512 | 1047 | iommu->need_sync = sync; |
ac0ea6e9 | 1048 | |
4bf5beef JR |
1049 | return 0; |
1050 | } | |
1051 | ||
1052 | static int iommu_queue_command_sync(struct amd_iommu *iommu, | |
1053 | struct iommu_cmd *cmd, | |
1054 | bool sync) | |
1055 | { | |
1056 | unsigned long flags; | |
1057 | int ret; | |
1058 | ||
1059 | spin_lock_irqsave(&iommu->lock, flags); | |
1060 | ret = __iommu_queue_command_sync(iommu, cmd, sync); | |
a19ae1ec | 1061 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1062 | |
4bf5beef | 1063 | return ret; |
8d201968 JR |
1064 | } |
1065 | ||
f1ca1512 JR |
1066 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1067 | { | |
1068 | return iommu_queue_command_sync(iommu, cmd, true); | |
1069 | } | |
1070 | ||
8d201968 JR |
1071 | /* |
1072 | * This function queues a completion wait command into the command | |
1073 | * buffer of an IOMMU | |
1074 | */ | |
a19ae1ec | 1075 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1076 | { |
1077 | struct iommu_cmd cmd; | |
4bf5beef | 1078 | unsigned long flags; |
ac0ea6e9 | 1079 | int ret; |
8d201968 | 1080 | |
09ee17eb | 1081 | if (!iommu->need_sync) |
815b33fd | 1082 | return 0; |
09ee17eb | 1083 | |
a19ae1ec | 1084 | |
4bf5beef JR |
1085 | build_completion_wait(&cmd, (u64)&iommu->cmd_sem); |
1086 | ||
1087 | spin_lock_irqsave(&iommu->lock, flags); | |
1088 | ||
1089 | iommu->cmd_sem = 0; | |
1090 | ||
1091 | ret = __iommu_queue_command_sync(iommu, &cmd, false); | |
a19ae1ec | 1092 | if (ret) |
4bf5beef JR |
1093 | goto out_unlock; |
1094 | ||
1095 | ret = wait_on_sem(&iommu->cmd_sem); | |
1096 | ||
1097 | out_unlock: | |
1098 | spin_unlock_irqrestore(&iommu->lock, flags); | |
8d201968 | 1099 | |
4bf5beef | 1100 | return ret; |
8d201968 JR |
1101 | } |
1102 | ||
d8c13085 | 1103 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1104 | { |
d8c13085 | 1105 | struct iommu_cmd cmd; |
a19ae1ec | 1106 | |
d8c13085 | 1107 | build_inv_dte(&cmd, devid); |
7e4f88da | 1108 | |
d8c13085 JR |
1109 | return iommu_queue_command(iommu, &cmd); |
1110 | } | |
09ee17eb | 1111 | |
0688a099 | 1112 | static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1113 | { |
1114 | u32 devid; | |
09ee17eb | 1115 | |
7d0c5cc5 JR |
1116 | for (devid = 0; devid <= 0xffff; ++devid) |
1117 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1118 | |
7d0c5cc5 JR |
1119 | iommu_completion_wait(iommu); |
1120 | } | |
84df8175 | 1121 | |
7d0c5cc5 JR |
1122 | /* |
1123 | * This function uses heavy locking and may disable irqs for some time. But | |
1124 | * this is no issue because it is only called during resume. | |
1125 | */ | |
0688a099 | 1126 | static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1127 | { |
1128 | u32 dom_id; | |
a19ae1ec | 1129 | |
7d0c5cc5 JR |
1130 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1131 | struct iommu_cmd cmd; | |
1132 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1133 | dom_id, 1); | |
1134 | iommu_queue_command(iommu, &cmd); | |
1135 | } | |
8eed9833 | 1136 | |
7d0c5cc5 | 1137 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1138 | } |
1139 | ||
0688a099 | 1140 | static void amd_iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1141 | { |
58fc7f14 | 1142 | struct iommu_cmd cmd; |
0518a3a4 | 1143 | |
58fc7f14 | 1144 | build_inv_all(&cmd); |
0518a3a4 | 1145 | |
58fc7f14 JR |
1146 | iommu_queue_command(iommu, &cmd); |
1147 | iommu_completion_wait(iommu); | |
1148 | } | |
1149 | ||
7ef2798d JR |
1150 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1151 | { | |
1152 | struct iommu_cmd cmd; | |
1153 | ||
1154 | build_inv_irt(&cmd, devid); | |
1155 | ||
1156 | iommu_queue_command(iommu, &cmd); | |
1157 | } | |
1158 | ||
0688a099 | 1159 | static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) |
7ef2798d JR |
1160 | { |
1161 | u32 devid; | |
1162 | ||
1163 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1164 | iommu_flush_irt(iommu, devid); | |
1165 | ||
1166 | iommu_completion_wait(iommu); | |
1167 | } | |
1168 | ||
7d0c5cc5 JR |
1169 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1170 | { | |
58fc7f14 | 1171 | if (iommu_feature(iommu, FEATURE_IA)) { |
0688a099 | 1172 | amd_iommu_flush_all(iommu); |
58fc7f14 | 1173 | } else { |
0688a099 JR |
1174 | amd_iommu_flush_dte_all(iommu); |
1175 | amd_iommu_flush_irt_all(iommu); | |
1176 | amd_iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
1177 | } |
1178 | } | |
1179 | ||
431b2a20 | 1180 | /* |
cb41ed85 | 1181 | * Command send function for flushing on-device TLB |
431b2a20 | 1182 | */ |
6c542047 JR |
1183 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1184 | u64 address, size_t size) | |
3fa43655 JR |
1185 | { |
1186 | struct amd_iommu *iommu; | |
b00d3bcf | 1187 | struct iommu_cmd cmd; |
cb41ed85 | 1188 | int qdep; |
3fa43655 | 1189 | |
ea61cddb JR |
1190 | qdep = dev_data->ats.qdep; |
1191 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1192 | |
ea61cddb | 1193 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1194 | |
1195 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1196 | } |
1197 | ||
431b2a20 | 1198 | /* |
431b2a20 | 1199 | * Command send function for invalidating a device table entry |
431b2a20 | 1200 | */ |
6c542047 | 1201 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1202 | { |
3fa43655 | 1203 | struct amd_iommu *iommu; |
e25bfb56 | 1204 | u16 alias; |
ee2fa743 | 1205 | int ret; |
a19ae1ec | 1206 | |
6c542047 | 1207 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1208 | alias = dev_data->alias; |
a19ae1ec | 1209 | |
f62dda66 | 1210 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1211 | if (!ret && alias != dev_data->devid) |
1212 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1213 | if (ret) |
1214 | return ret; | |
1215 | ||
ea61cddb | 1216 | if (dev_data->ats.enabled) |
6c542047 | 1217 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1218 | |
ee2fa743 | 1219 | return ret; |
a19ae1ec JR |
1220 | } |
1221 | ||
431b2a20 JR |
1222 | /* |
1223 | * TLB invalidation function which is called from the mapping functions. | |
1224 | * It invalidates a single PTE if the range to flush is within a single | |
1225 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1226 | */ | |
17b124bf JR |
1227 | static void __domain_flush_pages(struct protection_domain *domain, |
1228 | u64 address, size_t size, int pde) | |
a19ae1ec | 1229 | { |
cb41ed85 | 1230 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1231 | struct iommu_cmd cmd; |
1232 | int ret = 0, i; | |
a19ae1ec | 1233 | |
11b6402c | 1234 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1235 | |
6b9376e3 | 1236 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
6de8ad9b JR |
1237 | if (!domain->dev_iommu[i]) |
1238 | continue; | |
1239 | ||
1240 | /* | |
1241 | * Devices of this domain are behind this IOMMU | |
1242 | * We need a TLB flush | |
1243 | */ | |
11b6402c | 1244 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1245 | } |
1246 | ||
cb41ed85 | 1247 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1248 | |
ea61cddb | 1249 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1250 | continue; |
1251 | ||
6c542047 | 1252 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1253 | } |
1254 | ||
11b6402c | 1255 | WARN_ON(ret); |
6de8ad9b JR |
1256 | } |
1257 | ||
17b124bf JR |
1258 | static void domain_flush_pages(struct protection_domain *domain, |
1259 | u64 address, size_t size) | |
6de8ad9b | 1260 | { |
17b124bf | 1261 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1262 | } |
b6c02715 | 1263 | |
1c655773 | 1264 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1265 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1266 | { |
17b124bf | 1267 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1268 | } |
1269 | ||
42a49f96 | 1270 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1271 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1272 | { |
17b124bf | 1273 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1274 | } |
1275 | ||
17b124bf | 1276 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1277 | { |
17b124bf | 1278 | int i; |
18811f55 | 1279 | |
6b9376e3 | 1280 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
f1eae7c5 | 1281 | if (domain && !domain->dev_iommu[i]) |
17b124bf | 1282 | continue; |
bfd1be18 | 1283 | |
17b124bf JR |
1284 | /* |
1285 | * Devices of this domain are behind this IOMMU | |
1286 | * We need to wait for completion of all commands. | |
1287 | */ | |
1288 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1289 | } |
e394d72a JR |
1290 | } |
1291 | ||
b00d3bcf | 1292 | |
09b42804 | 1293 | /* |
b00d3bcf | 1294 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1295 | */ |
17b124bf | 1296 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1297 | { |
b00d3bcf | 1298 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1299 | |
b00d3bcf | 1300 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1301 | device_flush_dte(dev_data); |
a345b23b JR |
1302 | } |
1303 | ||
431b2a20 JR |
1304 | /**************************************************************************** |
1305 | * | |
1306 | * The functions below are used the create the page table mappings for | |
1307 | * unity mapped regions. | |
1308 | * | |
1309 | ****************************************************************************/ | |
1310 | ||
308973d3 JR |
1311 | /* |
1312 | * This function is used to add another level to an IO page table. Adding | |
1313 | * another level increases the size of the address space by 9 bits to a size up | |
1314 | * to 64 bits. | |
1315 | */ | |
1316 | static bool increase_address_space(struct protection_domain *domain, | |
1317 | gfp_t gfp) | |
1318 | { | |
1319 | u64 *pte; | |
1320 | ||
1321 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1322 | /* address space already 64 bit large */ | |
1323 | return false; | |
1324 | ||
1325 | pte = (void *)get_zeroed_page(gfp); | |
1326 | if (!pte) | |
1327 | return false; | |
1328 | ||
1329 | *pte = PM_LEVEL_PDE(domain->mode, | |
2543a786 | 1330 | iommu_virt_to_phys(domain->pt_root)); |
308973d3 JR |
1331 | domain->pt_root = pte; |
1332 | domain->mode += 1; | |
1333 | domain->updated = true; | |
1334 | ||
1335 | return true; | |
1336 | } | |
1337 | ||
1338 | static u64 *alloc_pte(struct protection_domain *domain, | |
1339 | unsigned long address, | |
cbb9d729 | 1340 | unsigned long page_size, |
308973d3 JR |
1341 | u64 **pte_page, |
1342 | gfp_t gfp) | |
1343 | { | |
cbb9d729 | 1344 | int level, end_lvl; |
308973d3 | 1345 | u64 *pte, *page; |
cbb9d729 JR |
1346 | |
1347 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1348 | |
1349 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1350 | increase_address_space(domain, gfp); | |
1351 | ||
cbb9d729 JR |
1352 | level = domain->mode - 1; |
1353 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1354 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1355 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1356 | |
1357 | while (level > end_lvl) { | |
7bfa5bd2 JR |
1358 | u64 __pte, __npte; |
1359 | ||
1360 | __pte = *pte; | |
1361 | ||
1362 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
308973d3 JR |
1363 | page = (u64 *)get_zeroed_page(gfp); |
1364 | if (!page) | |
1365 | return NULL; | |
7bfa5bd2 | 1366 | |
2543a786 | 1367 | __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page)); |
7bfa5bd2 | 1368 | |
134414ff BH |
1369 | /* pte could have been changed somewhere. */ |
1370 | if (cmpxchg64(pte, __pte, __npte) != __pte) { | |
7bfa5bd2 JR |
1371 | free_page((unsigned long)page); |
1372 | continue; | |
1373 | } | |
308973d3 JR |
1374 | } |
1375 | ||
cbb9d729 JR |
1376 | /* No level skipping support yet */ |
1377 | if (PM_PTE_LEVEL(*pte) != level) | |
1378 | return NULL; | |
1379 | ||
308973d3 JR |
1380 | level -= 1; |
1381 | ||
1382 | pte = IOMMU_PTE_PAGE(*pte); | |
1383 | ||
1384 | if (pte_page && level == end_lvl) | |
1385 | *pte_page = pte; | |
1386 | ||
1387 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1388 | } | |
1389 | ||
1390 | return pte; | |
1391 | } | |
1392 | ||
1393 | /* | |
1394 | * This function checks if there is a PTE for a given dma address. If | |
1395 | * there is one, it returns the pointer to it. | |
1396 | */ | |
3039ca1b JR |
1397 | static u64 *fetch_pte(struct protection_domain *domain, |
1398 | unsigned long address, | |
1399 | unsigned long *page_size) | |
308973d3 JR |
1400 | { |
1401 | int level; | |
1402 | u64 *pte; | |
1403 | ||
24cd7723 JR |
1404 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1405 | return NULL; | |
1406 | ||
3039ca1b JR |
1407 | level = domain->mode - 1; |
1408 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1409 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1410 | |
24cd7723 JR |
1411 | while (level > 0) { |
1412 | ||
1413 | /* Not Present */ | |
308973d3 JR |
1414 | if (!IOMMU_PTE_PRESENT(*pte)) |
1415 | return NULL; | |
1416 | ||
24cd7723 | 1417 | /* Large PTE */ |
3039ca1b JR |
1418 | if (PM_PTE_LEVEL(*pte) == 7 || |
1419 | PM_PTE_LEVEL(*pte) == 0) | |
1420 | break; | |
24cd7723 JR |
1421 | |
1422 | /* No level skipping support yet */ | |
1423 | if (PM_PTE_LEVEL(*pte) != level) | |
1424 | return NULL; | |
1425 | ||
308973d3 JR |
1426 | level -= 1; |
1427 | ||
24cd7723 | 1428 | /* Walk to the next level */ |
3039ca1b JR |
1429 | pte = IOMMU_PTE_PAGE(*pte); |
1430 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1431 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1432 | } | |
1433 | ||
1434 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1435 | unsigned long pte_mask; | |
1436 | ||
1437 | /* | |
1438 | * If we have a series of large PTEs, make | |
1439 | * sure to return a pointer to the first one. | |
1440 | */ | |
1441 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1442 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1443 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1444 | } |
1445 | ||
1446 | return pte; | |
1447 | } | |
1448 | ||
431b2a20 JR |
1449 | /* |
1450 | * Generic mapping functions. It maps a physical address into a DMA | |
1451 | * address space. It allocates the page table pages if necessary. | |
1452 | * In the future it can be extended to a generic mapping function | |
1453 | * supporting all features of AMD IOMMU page tables like level skipping | |
1454 | * and full 64 bit address spaces. | |
1455 | */ | |
38e817fe JR |
1456 | static int iommu_map_page(struct protection_domain *dom, |
1457 | unsigned long bus_addr, | |
1458 | unsigned long phys_addr, | |
b911b89b | 1459 | unsigned long page_size, |
abdc5eb3 | 1460 | int prot, |
b911b89b | 1461 | gfp_t gfp) |
bd0e5211 | 1462 | { |
8bda3092 | 1463 | u64 __pte, *pte; |
cbb9d729 | 1464 | int i, count; |
abdc5eb3 | 1465 | |
d4b03664 JR |
1466 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1467 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1468 | ||
bad1cac2 | 1469 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1470 | return -EINVAL; |
1471 | ||
d4b03664 | 1472 | count = PAGE_SIZE_PTE_COUNT(page_size); |
b911b89b | 1473 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); |
cbb9d729 | 1474 | |
63eaa75e ML |
1475 | if (!pte) |
1476 | return -ENOMEM; | |
1477 | ||
cbb9d729 JR |
1478 | for (i = 0; i < count; ++i) |
1479 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1480 | return -EBUSY; | |
bd0e5211 | 1481 | |
d4b03664 | 1482 | if (count > 1) { |
2543a786 | 1483 | __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size); |
07a80a6b | 1484 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
cbb9d729 | 1485 | } else |
4dfc2788 | 1486 | __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
bd0e5211 | 1487 | |
bd0e5211 JR |
1488 | if (prot & IOMMU_PROT_IR) |
1489 | __pte |= IOMMU_PTE_IR; | |
1490 | if (prot & IOMMU_PROT_IW) | |
1491 | __pte |= IOMMU_PTE_IW; | |
1492 | ||
cbb9d729 JR |
1493 | for (i = 0; i < count; ++i) |
1494 | pte[i] = __pte; | |
bd0e5211 | 1495 | |
04bfdd84 JR |
1496 | update_domain(dom); |
1497 | ||
bd0e5211 JR |
1498 | return 0; |
1499 | } | |
1500 | ||
24cd7723 JR |
1501 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1502 | unsigned long bus_addr, | |
1503 | unsigned long page_size) | |
eb74ff6c | 1504 | { |
71b390e9 JR |
1505 | unsigned long long unmapped; |
1506 | unsigned long unmap_size; | |
24cd7723 JR |
1507 | u64 *pte; |
1508 | ||
1509 | BUG_ON(!is_power_of_2(page_size)); | |
1510 | ||
1511 | unmapped = 0; | |
eb74ff6c | 1512 | |
24cd7723 JR |
1513 | while (unmapped < page_size) { |
1514 | ||
71b390e9 JR |
1515 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1516 | ||
1517 | if (pte) { | |
1518 | int i, count; | |
1519 | ||
1520 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1521 | for (i = 0; i < count; i++) |
1522 | pte[i] = 0ULL; | |
1523 | } | |
1524 | ||
1525 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1526 | unmapped += unmap_size; | |
1527 | } | |
1528 | ||
60d0ca3c | 1529 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1530 | |
24cd7723 | 1531 | return unmapped; |
eb74ff6c | 1532 | } |
eb74ff6c | 1533 | |
431b2a20 JR |
1534 | /**************************************************************************** |
1535 | * | |
1536 | * The next functions belong to the address allocator for the dma_ops | |
2d4c515b | 1537 | * interface functions. |
431b2a20 JR |
1538 | * |
1539 | ****************************************************************************/ | |
d3086444 | 1540 | |
9cabe89b | 1541 | |
256e4621 JR |
1542 | static unsigned long dma_ops_alloc_iova(struct device *dev, |
1543 | struct dma_ops_domain *dma_dom, | |
1544 | unsigned int pages, u64 dma_mask) | |
384de729 | 1545 | { |
256e4621 | 1546 | unsigned long pfn = 0; |
384de729 | 1547 | |
256e4621 | 1548 | pages = __roundup_pow_of_two(pages); |
ccb50e03 | 1549 | |
256e4621 JR |
1550 | if (dma_mask > DMA_BIT_MASK(32)) |
1551 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, | |
538d5b33 | 1552 | IOVA_PFN(DMA_BIT_MASK(32)), false); |
7b5e25b8 | 1553 | |
256e4621 | 1554 | if (!pfn) |
538d5b33 TN |
1555 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, |
1556 | IOVA_PFN(dma_mask), true); | |
5f6bed50 | 1557 | |
256e4621 | 1558 | return (pfn << PAGE_SHIFT); |
384de729 JR |
1559 | } |
1560 | ||
256e4621 JR |
1561 | static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, |
1562 | unsigned long address, | |
1563 | unsigned int pages) | |
d3086444 | 1564 | { |
256e4621 JR |
1565 | pages = __roundup_pow_of_two(pages); |
1566 | address >>= PAGE_SHIFT; | |
384de729 | 1567 | |
256e4621 | 1568 | free_iova_fast(&dma_dom->iovad, address, pages); |
d3086444 JR |
1569 | } |
1570 | ||
431b2a20 JR |
1571 | /**************************************************************************** |
1572 | * | |
1573 | * The next functions belong to the domain allocation. A domain is | |
1574 | * allocated for every IOMMU as the default domain. If device isolation | |
1575 | * is enabled, every device get its own domain. The most important thing | |
1576 | * about domains is the page table mapping the DMA address space they | |
1577 | * contain. | |
1578 | * | |
1579 | ****************************************************************************/ | |
1580 | ||
aeb26f55 JR |
1581 | /* |
1582 | * This function adds a protection domain to the global protection domain list | |
1583 | */ | |
1584 | static void add_domain_to_list(struct protection_domain *domain) | |
1585 | { | |
1586 | unsigned long flags; | |
1587 | ||
1588 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1589 | list_add(&domain->list, &amd_iommu_pd_list); | |
1590 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1591 | } | |
1592 | ||
1593 | /* | |
1594 | * This function removes a protection domain to the global | |
1595 | * protection domain list | |
1596 | */ | |
1597 | static void del_domain_from_list(struct protection_domain *domain) | |
1598 | { | |
1599 | unsigned long flags; | |
1600 | ||
1601 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1602 | list_del(&domain->list); | |
1603 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1604 | } | |
1605 | ||
ec487d1a JR |
1606 | static u16 domain_id_alloc(void) |
1607 | { | |
1608 | unsigned long flags; | |
1609 | int id; | |
1610 | ||
1611 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1612 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1613 | BUG_ON(id == 0); | |
1614 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1615 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1616 | else | |
1617 | id = 0; | |
1618 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1619 | ||
1620 | return id; | |
1621 | } | |
1622 | ||
a2acfb75 JR |
1623 | static void domain_id_free(int id) |
1624 | { | |
1625 | unsigned long flags; | |
1626 | ||
1627 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1628 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1629 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1630 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1631 | } | |
a2acfb75 | 1632 | |
5c34c403 JR |
1633 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1634 | static void free_pt_##LVL (unsigned long __pt) \ | |
1635 | { \ | |
1636 | unsigned long p; \ | |
1637 | u64 *pt; \ | |
1638 | int i; \ | |
1639 | \ | |
1640 | pt = (u64 *)__pt; \ | |
1641 | \ | |
1642 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1643 | /* PTE present? */ \ |
5c34c403 JR |
1644 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1645 | continue; \ | |
1646 | \ | |
0b3fff54 JR |
1647 | /* Large PTE? */ \ |
1648 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1649 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1650 | continue; \ | |
1651 | \ | |
5c34c403 JR |
1652 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1653 | FN(p); \ | |
1654 | } \ | |
1655 | free_page((unsigned long)pt); \ | |
1656 | } | |
1657 | ||
1658 | DEFINE_FREE_PT_FN(l2, free_page) | |
1659 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1660 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1661 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1662 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1663 | ||
86db2e5d | 1664 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1665 | { |
5c34c403 | 1666 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1667 | |
5c34c403 JR |
1668 | switch (domain->mode) { |
1669 | case PAGE_MODE_NONE: | |
1670 | break; | |
1671 | case PAGE_MODE_1_LEVEL: | |
1672 | free_page(root); | |
1673 | break; | |
1674 | case PAGE_MODE_2_LEVEL: | |
1675 | free_pt_l2(root); | |
1676 | break; | |
1677 | case PAGE_MODE_3_LEVEL: | |
1678 | free_pt_l3(root); | |
1679 | break; | |
1680 | case PAGE_MODE_4_LEVEL: | |
1681 | free_pt_l4(root); | |
1682 | break; | |
1683 | case PAGE_MODE_5_LEVEL: | |
1684 | free_pt_l5(root); | |
1685 | break; | |
1686 | case PAGE_MODE_6_LEVEL: | |
1687 | free_pt_l6(root); | |
1688 | break; | |
1689 | default: | |
1690 | BUG(); | |
ec487d1a | 1691 | } |
ec487d1a JR |
1692 | } |
1693 | ||
b16137b1 JR |
1694 | static void free_gcr3_tbl_level1(u64 *tbl) |
1695 | { | |
1696 | u64 *ptr; | |
1697 | int i; | |
1698 | ||
1699 | for (i = 0; i < 512; ++i) { | |
1700 | if (!(tbl[i] & GCR3_VALID)) | |
1701 | continue; | |
1702 | ||
2543a786 | 1703 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1704 | |
1705 | free_page((unsigned long)ptr); | |
1706 | } | |
1707 | } | |
1708 | ||
1709 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1710 | { | |
1711 | u64 *ptr; | |
1712 | int i; | |
1713 | ||
1714 | for (i = 0; i < 512; ++i) { | |
1715 | if (!(tbl[i] & GCR3_VALID)) | |
1716 | continue; | |
1717 | ||
2543a786 | 1718 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1719 | |
1720 | free_gcr3_tbl_level1(ptr); | |
1721 | } | |
1722 | } | |
1723 | ||
52815b75 JR |
1724 | static void free_gcr3_table(struct protection_domain *domain) |
1725 | { | |
b16137b1 JR |
1726 | if (domain->glx == 2) |
1727 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1728 | else if (domain->glx == 1) | |
1729 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1730 | else |
1731 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1732 | |
52815b75 JR |
1733 | free_page((unsigned long)domain->gcr3_tbl); |
1734 | } | |
1735 | ||
fca6af6a JR |
1736 | static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom) |
1737 | { | |
fca6af6a JR |
1738 | domain_flush_tlb(&dom->domain); |
1739 | domain_flush_complete(&dom->domain); | |
fd62190a JR |
1740 | } |
1741 | ||
9003d618 | 1742 | static void iova_domain_flush_tlb(struct iova_domain *iovad) |
fd62190a | 1743 | { |
9003d618 | 1744 | struct dma_ops_domain *dom; |
fd62190a | 1745 | |
9003d618 | 1746 | dom = container_of(iovad, struct dma_ops_domain, iovad); |
fca6af6a JR |
1747 | |
1748 | dma_ops_domain_flush_tlb(dom); | |
fca6af6a JR |
1749 | } |
1750 | ||
431b2a20 JR |
1751 | /* |
1752 | * Free a domain, only used if something went wrong in the | |
1753 | * allocation path and we need to free an already allocated page table | |
1754 | */ | |
ec487d1a JR |
1755 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1756 | { | |
1757 | if (!dom) | |
1758 | return; | |
1759 | ||
aeb26f55 JR |
1760 | del_domain_from_list(&dom->domain); |
1761 | ||
2d4c515b | 1762 | put_iova_domain(&dom->iovad); |
ec487d1a | 1763 | |
2d4c515b | 1764 | free_pagetable(&dom->domain); |
ec487d1a | 1765 | |
c3db901c BH |
1766 | if (dom->domain.id) |
1767 | domain_id_free(dom->domain.id); | |
1768 | ||
ec487d1a JR |
1769 | kfree(dom); |
1770 | } | |
1771 | ||
431b2a20 JR |
1772 | /* |
1773 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1774 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1775 | * structures required for the dma_ops interface |
1776 | */ | |
87a64d52 | 1777 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1778 | { |
1779 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1780 | |
1781 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1782 | if (!dma_dom) | |
1783 | return NULL; | |
1784 | ||
7a5a566e | 1785 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1786 | goto free_dma_dom; |
7a5a566e | 1787 | |
ffec2197 | 1788 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; |
ec487d1a | 1789 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1790 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1791 | if (!dma_dom->domain.pt_root) |
1792 | goto free_dma_dom; | |
ec487d1a | 1793 | |
aa3ac946 | 1794 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN); |
307d5851 | 1795 | |
9003d618 | 1796 | if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL)) |
d4241a27 JR |
1797 | goto free_dma_dom; |
1798 | ||
9003d618 JR |
1799 | /* Initialize reserved ranges */ |
1800 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); | |
fca6af6a | 1801 | |
2d4c515b JR |
1802 | add_domain_to_list(&dma_dom->domain); |
1803 | ||
ec487d1a JR |
1804 | return dma_dom; |
1805 | ||
1806 | free_dma_dom: | |
1807 | dma_ops_domain_free(dma_dom); | |
1808 | ||
1809 | return NULL; | |
1810 | } | |
1811 | ||
5b28df6f JR |
1812 | /* |
1813 | * little helper function to check whether a given protection domain is a | |
1814 | * dma_ops domain | |
1815 | */ | |
1816 | static bool dma_ops_domain(struct protection_domain *domain) | |
1817 | { | |
1818 | return domain->flags & PD_DMA_OPS_MASK; | |
1819 | } | |
1820 | ||
ff18c4e5 GH |
1821 | static void set_dte_entry(u16 devid, struct protection_domain *domain, |
1822 | bool ats, bool ppr) | |
b20ac0d4 | 1823 | { |
132bd68f | 1824 | u64 pte_root = 0; |
ee6c2868 | 1825 | u64 flags = 0; |
863c74eb | 1826 | |
132bd68f | 1827 | if (domain->mode != PAGE_MODE_NONE) |
2543a786 | 1828 | pte_root = iommu_virt_to_phys(domain->pt_root); |
132bd68f | 1829 | |
38ddf41b JR |
1830 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1831 | << DEV_ENTRY_MODE_SHIFT; | |
07a80a6b | 1832 | pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV; |
b20ac0d4 | 1833 | |
ee6c2868 JR |
1834 | flags = amd_iommu_dev_table[devid].data[1]; |
1835 | ||
fd7b5535 JR |
1836 | if (ats) |
1837 | flags |= DTE_FLAG_IOTLB; | |
1838 | ||
ff18c4e5 GH |
1839 | if (ppr) { |
1840 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1841 | ||
1842 | if (iommu_feature(iommu, FEATURE_EPHSUP)) | |
1843 | pte_root |= 1ULL << DEV_ENTRY_PPR; | |
1844 | } | |
1845 | ||
52815b75 | 1846 | if (domain->flags & PD_IOMMUV2_MASK) { |
2543a786 | 1847 | u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); |
52815b75 JR |
1848 | u64 glx = domain->glx; |
1849 | u64 tmp; | |
1850 | ||
1851 | pte_root |= DTE_FLAG_GV; | |
1852 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1853 | ||
1854 | /* First mask out possible old values for GCR3 table */ | |
1855 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1856 | flags &= ~tmp; | |
1857 | ||
1858 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1859 | flags &= ~tmp; | |
1860 | ||
1861 | /* Encode GCR3 table into DTE */ | |
1862 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1863 | pte_root |= tmp; | |
1864 | ||
1865 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1866 | flags |= tmp; | |
1867 | ||
1868 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1869 | flags |= tmp; | |
1870 | } | |
1871 | ||
45a01c42 | 1872 | flags &= ~DEV_DOMID_MASK; |
ee6c2868 JR |
1873 | flags |= domain->id; |
1874 | ||
1875 | amd_iommu_dev_table[devid].data[1] = flags; | |
1876 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1877 | } |
1878 | ||
1879 | static void clear_dte_entry(u16 devid) | |
1880 | { | |
15898bbc | 1881 | /* remove entry from the device table seen by the hardware */ |
07a80a6b | 1882 | amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV; |
cbf3ccd0 | 1883 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; |
15898bbc JR |
1884 | |
1885 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1886 | } |
1887 | ||
ec9e79ef JR |
1888 | static void do_attach(struct iommu_dev_data *dev_data, |
1889 | struct protection_domain *domain) | |
7f760ddd | 1890 | { |
7f760ddd | 1891 | struct amd_iommu *iommu; |
e25bfb56 | 1892 | u16 alias; |
ec9e79ef | 1893 | bool ats; |
fd7b5535 | 1894 | |
ec9e79ef | 1895 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1896 | alias = dev_data->alias; |
ec9e79ef | 1897 | ats = dev_data->ats.enabled; |
7f760ddd JR |
1898 | |
1899 | /* Update data structures */ | |
1900 | dev_data->domain = domain; | |
1901 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
1902 | |
1903 | /* Do reference counting */ | |
1904 | domain->dev_iommu[iommu->index] += 1; | |
1905 | domain->dev_cnt += 1; | |
1906 | ||
e25bfb56 | 1907 | /* Update device table */ |
ff18c4e5 | 1908 | set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2); |
e25bfb56 | 1909 | if (alias != dev_data->devid) |
ff18c4e5 | 1910 | set_dte_entry(alias, domain, ats, dev_data->iommu_v2); |
e25bfb56 | 1911 | |
6c542047 | 1912 | device_flush_dte(dev_data); |
7f760ddd JR |
1913 | } |
1914 | ||
ec9e79ef | 1915 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1916 | { |
7f760ddd | 1917 | struct amd_iommu *iommu; |
e25bfb56 | 1918 | u16 alias; |
7f760ddd | 1919 | |
5adad991 JR |
1920 | /* |
1921 | * First check if the device is still attached. It might already | |
1922 | * be detached from its domain because the generic | |
1923 | * iommu_detach_group code detached it and we try again here in | |
1924 | * our alias handling. | |
1925 | */ | |
1926 | if (!dev_data->domain) | |
1927 | return; | |
1928 | ||
ec9e79ef | 1929 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1930 | alias = dev_data->alias; |
15898bbc JR |
1931 | |
1932 | /* decrease reference counters */ | |
7f760ddd JR |
1933 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1934 | dev_data->domain->dev_cnt -= 1; | |
1935 | ||
1936 | /* Update data structures */ | |
1937 | dev_data->domain = NULL; | |
1938 | list_del(&dev_data->list); | |
f62dda66 | 1939 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
1940 | if (alias != dev_data->devid) |
1941 | clear_dte_entry(alias); | |
15898bbc | 1942 | |
7f760ddd | 1943 | /* Flush the DTE entry */ |
6c542047 | 1944 | device_flush_dte(dev_data); |
2b681faf JR |
1945 | } |
1946 | ||
1947 | /* | |
1948 | * If a device is not yet associated with a domain, this function does | |
1949 | * assigns it visible for the hardware | |
1950 | */ | |
ec9e79ef | 1951 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1952 | struct protection_domain *domain) |
2b681faf | 1953 | { |
84fe6c19 | 1954 | int ret; |
657cbb6b | 1955 | |
272e4f99 JR |
1956 | /* |
1957 | * Must be called with IRQs disabled. Warn here to detect early | |
1958 | * when its not. | |
1959 | */ | |
1960 | WARN_ON(!irqs_disabled()); | |
1961 | ||
2b681faf JR |
1962 | /* lock domain */ |
1963 | spin_lock(&domain->lock); | |
1964 | ||
397111ab | 1965 | ret = -EBUSY; |
150952f9 | 1966 | if (dev_data->domain != NULL) |
397111ab | 1967 | goto out_unlock; |
15898bbc | 1968 | |
397111ab | 1969 | /* Attach alias group root */ |
150952f9 | 1970 | do_attach(dev_data, domain); |
24100055 | 1971 | |
84fe6c19 JL |
1972 | ret = 0; |
1973 | ||
1974 | out_unlock: | |
1975 | ||
eba6ac60 JR |
1976 | /* ready */ |
1977 | spin_unlock(&domain->lock); | |
15898bbc | 1978 | |
84fe6c19 | 1979 | return ret; |
0feae533 | 1980 | } |
b20ac0d4 | 1981 | |
52815b75 JR |
1982 | |
1983 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
1984 | { | |
1985 | pci_disable_ats(pdev); | |
1986 | pci_disable_pri(pdev); | |
1987 | pci_disable_pasid(pdev); | |
1988 | } | |
1989 | ||
6a113ddc JR |
1990 | /* FIXME: Change generic reset-function to do the same */ |
1991 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
1992 | { | |
1993 | u16 control; | |
1994 | int pos; | |
1995 | ||
46277b75 | 1996 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
1997 | if (!pos) |
1998 | return -EINVAL; | |
1999 | ||
46277b75 JR |
2000 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2001 | control |= PCI_PRI_CTRL_RESET; | |
2002 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2003 | |
2004 | return 0; | |
2005 | } | |
2006 | ||
52815b75 JR |
2007 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2008 | { | |
6a113ddc JR |
2009 | bool reset_enable; |
2010 | int reqs, ret; | |
2011 | ||
2012 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2013 | reqs = 32; | |
2014 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2015 | reqs = 1; | |
2016 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2017 | |
2018 | /* Only allow access to user-accessible pages */ | |
2019 | ret = pci_enable_pasid(pdev, 0); | |
2020 | if (ret) | |
2021 | goto out_err; | |
2022 | ||
2023 | /* First reset the PRI state of the device */ | |
2024 | ret = pci_reset_pri(pdev); | |
2025 | if (ret) | |
2026 | goto out_err; | |
2027 | ||
6a113ddc JR |
2028 | /* Enable PRI */ |
2029 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2030 | if (ret) |
2031 | goto out_err; | |
2032 | ||
6a113ddc JR |
2033 | if (reset_enable) { |
2034 | ret = pri_reset_while_enabled(pdev); | |
2035 | if (ret) | |
2036 | goto out_err; | |
2037 | } | |
2038 | ||
52815b75 JR |
2039 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2040 | if (ret) | |
2041 | goto out_err; | |
2042 | ||
2043 | return 0; | |
2044 | ||
2045 | out_err: | |
2046 | pci_disable_pri(pdev); | |
2047 | pci_disable_pasid(pdev); | |
2048 | ||
2049 | return ret; | |
2050 | } | |
2051 | ||
c99afa25 | 2052 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2053 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2054 | |
98f1ad25 | 2055 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2056 | { |
a3b93121 | 2057 | u16 status; |
c99afa25 JR |
2058 | int pos; |
2059 | ||
46277b75 | 2060 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2061 | if (!pos) |
2062 | return false; | |
2063 | ||
a3b93121 | 2064 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2065 | |
a3b93121 | 2066 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2067 | } |
2068 | ||
407d733e | 2069 | /* |
df805abb | 2070 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2071 | * assigns it visible for the hardware |
2072 | */ | |
15898bbc JR |
2073 | static int attach_device(struct device *dev, |
2074 | struct protection_domain *domain) | |
0feae533 | 2075 | { |
2bf9a0a1 | 2076 | struct pci_dev *pdev; |
ea61cddb | 2077 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2078 | unsigned long flags; |
15898bbc | 2079 | int ret; |
eba6ac60 | 2080 | |
ea61cddb JR |
2081 | dev_data = get_dev_data(dev); |
2082 | ||
2bf9a0a1 WZ |
2083 | if (!dev_is_pci(dev)) |
2084 | goto skip_ats_check; | |
2085 | ||
2086 | pdev = to_pci_dev(dev); | |
52815b75 | 2087 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2088 | if (!dev_data->passthrough) |
52815b75 JR |
2089 | return -EINVAL; |
2090 | ||
02ca2021 JR |
2091 | if (dev_data->iommu_v2) { |
2092 | if (pdev_iommuv2_enable(pdev) != 0) | |
2093 | return -EINVAL; | |
52815b75 | 2094 | |
02ca2021 JR |
2095 | dev_data->ats.enabled = true; |
2096 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2097 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2098 | } | |
52815b75 JR |
2099 | } else if (amd_iommu_iotlb_sup && |
2100 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2101 | dev_data->ats.enabled = true; |
2102 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2103 | } | |
fd7b5535 | 2104 | |
2bf9a0a1 | 2105 | skip_ats_check: |
eba6ac60 | 2106 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2107 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2108 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2109 | ||
0feae533 JR |
2110 | /* |
2111 | * We might boot into a crash-kernel here. The crashed kernel | |
2112 | * left the caches in the IOMMU dirty. So we have to flush | |
2113 | * here to evict all dirty stuff. | |
2114 | */ | |
17b124bf | 2115 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2116 | |
2117 | return ret; | |
b20ac0d4 JR |
2118 | } |
2119 | ||
355bf553 JR |
2120 | /* |
2121 | * Removes a device from a protection domain (unlocked) | |
2122 | */ | |
ec9e79ef | 2123 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2124 | { |
2ca76279 | 2125 | struct protection_domain *domain; |
c4596114 | 2126 | |
272e4f99 JR |
2127 | /* |
2128 | * Must be called with IRQs disabled. Warn here to detect early | |
2129 | * when its not. | |
2130 | */ | |
2131 | WARN_ON(!irqs_disabled()); | |
2ca76279 | 2132 | |
f34c73f5 JR |
2133 | if (WARN_ON(!dev_data->domain)) |
2134 | return; | |
24100055 | 2135 | |
2ca76279 | 2136 | domain = dev_data->domain; |
71f77580 | 2137 | |
f1dd0a8b | 2138 | spin_lock(&domain->lock); |
24100055 | 2139 | |
150952f9 | 2140 | do_detach(dev_data); |
7f760ddd | 2141 | |
f1dd0a8b | 2142 | spin_unlock(&domain->lock); |
355bf553 JR |
2143 | } |
2144 | ||
2145 | /* | |
2146 | * Removes a device from a protection domain (with devtable_lock held) | |
2147 | */ | |
15898bbc | 2148 | static void detach_device(struct device *dev) |
355bf553 | 2149 | { |
52815b75 | 2150 | struct protection_domain *domain; |
ea61cddb | 2151 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2152 | unsigned long flags; |
2153 | ||
ec9e79ef | 2154 | dev_data = get_dev_data(dev); |
52815b75 | 2155 | domain = dev_data->domain; |
ec9e79ef | 2156 | |
355bf553 JR |
2157 | /* lock device table */ |
2158 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2159 | __detach_device(dev_data); |
355bf553 | 2160 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2161 | |
2bf9a0a1 WZ |
2162 | if (!dev_is_pci(dev)) |
2163 | return; | |
2164 | ||
02ca2021 | 2165 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2166 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2167 | else if (dev_data->ats.enabled) | |
ea61cddb | 2168 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2169 | |
2170 | dev_data->ats.enabled = false; | |
355bf553 | 2171 | } |
e275a2a0 | 2172 | |
aafd8ba0 | 2173 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2174 | { |
5abcdba4 | 2175 | struct iommu_dev_data *dev_data; |
07ee8694 | 2176 | struct iommu_domain *domain; |
e275a2a0 | 2177 | struct amd_iommu *iommu; |
7aba6cb9 | 2178 | int ret, devid; |
e275a2a0 | 2179 | |
aafd8ba0 | 2180 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2181 | return 0; |
e275a2a0 | 2182 | |
aafd8ba0 | 2183 | devid = get_device_id(dev); |
9ee35e4c | 2184 | if (devid < 0) |
7aba6cb9 WZ |
2185 | return devid; |
2186 | ||
aafd8ba0 | 2187 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2188 | |
aafd8ba0 | 2189 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2190 | if (ret) { |
2191 | if (ret != -ENOTSUPP) | |
2192 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2193 | dev_name(dev)); | |
657cbb6b | 2194 | |
aafd8ba0 | 2195 | iommu_ignore_device(dev); |
5657933d | 2196 | dev->dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2197 | goto out; |
2198 | } | |
2199 | init_iommu_group(dev); | |
2c9195e9 | 2200 | |
07ee8694 | 2201 | dev_data = get_dev_data(dev); |
2c9195e9 | 2202 | |
4d58b8a6 | 2203 | BUG_ON(!dev_data); |
657cbb6b | 2204 | |
1e6a7b04 | 2205 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2206 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2207 | |
07ee8694 JR |
2208 | /* Domains are initialized for this device - have a look what we ended up with */ |
2209 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2210 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2211 | dev_data->passthrough = true; |
32302324 | 2212 | else |
5657933d | 2213 | dev->dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2214 | |
aafd8ba0 | 2215 | out: |
e275a2a0 JR |
2216 | iommu_completion_wait(iommu); |
2217 | ||
e275a2a0 JR |
2218 | return 0; |
2219 | } | |
2220 | ||
aafd8ba0 | 2221 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2222 | { |
aafd8ba0 | 2223 | struct amd_iommu *iommu; |
7aba6cb9 | 2224 | int devid; |
aafd8ba0 JR |
2225 | |
2226 | if (!check_device(dev)) | |
2227 | return; | |
2228 | ||
2229 | devid = get_device_id(dev); | |
9ee35e4c | 2230 | if (devid < 0) |
7aba6cb9 WZ |
2231 | return; |
2232 | ||
aafd8ba0 JR |
2233 | iommu = amd_iommu_rlookup_table[devid]; |
2234 | ||
2235 | iommu_uninit_device(dev); | |
2236 | iommu_completion_wait(iommu); | |
8638c491 JR |
2237 | } |
2238 | ||
b097d11a WZ |
2239 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2240 | { | |
2241 | if (dev_is_pci(dev)) | |
2242 | return pci_device_group(dev); | |
2243 | ||
2244 | return acpihid_device_group(dev); | |
2245 | } | |
2246 | ||
431b2a20 JR |
2247 | /***************************************************************************** |
2248 | * | |
2249 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2250 | * | |
2251 | *****************************************************************************/ | |
2252 | ||
2253 | /* | |
2254 | * In the dma_ops path we only have the struct device. This function | |
2255 | * finds the corresponding IOMMU, the protection domain and the | |
2256 | * requestor id for a given device. | |
2257 | * If the device is not yet associated with a domain this is also done | |
2258 | * in this function. | |
2259 | */ | |
94f6d190 | 2260 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2261 | { |
94f6d190 | 2262 | struct protection_domain *domain; |
df3f7a6e | 2263 | struct iommu_domain *io_domain; |
b20ac0d4 | 2264 | |
f99c0f1c | 2265 | if (!check_device(dev)) |
94f6d190 | 2266 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2267 | |
d26592a9 | 2268 | domain = get_dev_data(dev)->domain; |
df3f7a6e BH |
2269 | if (domain == NULL && get_dev_data(dev)->defer_attach) { |
2270 | get_dev_data(dev)->defer_attach = false; | |
2271 | io_domain = iommu_get_domain_for_dev(dev); | |
2272 | domain = to_pdomain(io_domain); | |
2273 | attach_device(dev, domain); | |
2274 | } | |
ec62b1ab BH |
2275 | if (domain == NULL) |
2276 | return ERR_PTR(-EBUSY); | |
2277 | ||
0bb6e243 | 2278 | if (!dma_ops_domain(domain)) |
94f6d190 | 2279 | return ERR_PTR(-EBUSY); |
f91ba190 | 2280 | |
0bb6e243 | 2281 | return domain; |
b20ac0d4 JR |
2282 | } |
2283 | ||
04bfdd84 JR |
2284 | static void update_device_table(struct protection_domain *domain) |
2285 | { | |
492667da | 2286 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2287 | |
3254de6b | 2288 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
ff18c4e5 GH |
2289 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled, |
2290 | dev_data->iommu_v2); | |
3254de6b JR |
2291 | |
2292 | if (dev_data->devid == dev_data->alias) | |
2293 | continue; | |
2294 | ||
2295 | /* There is an alias, update device table entry for it */ | |
ff18c4e5 GH |
2296 | set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled, |
2297 | dev_data->iommu_v2); | |
3254de6b | 2298 | } |
04bfdd84 JR |
2299 | } |
2300 | ||
2301 | static void update_domain(struct protection_domain *domain) | |
2302 | { | |
2303 | if (!domain->updated) | |
2304 | return; | |
2305 | ||
2306 | update_device_table(domain); | |
17b124bf JR |
2307 | |
2308 | domain_flush_devices(domain); | |
2309 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2310 | |
2311 | domain->updated = false; | |
2312 | } | |
2313 | ||
f37f7f33 JR |
2314 | static int dir2prot(enum dma_data_direction direction) |
2315 | { | |
2316 | if (direction == DMA_TO_DEVICE) | |
2317 | return IOMMU_PROT_IR; | |
2318 | else if (direction == DMA_FROM_DEVICE) | |
2319 | return IOMMU_PROT_IW; | |
2320 | else if (direction == DMA_BIDIRECTIONAL) | |
2321 | return IOMMU_PROT_IW | IOMMU_PROT_IR; | |
2322 | else | |
2323 | return 0; | |
2324 | } | |
daae2d25 | 2325 | |
431b2a20 JR |
2326 | /* |
2327 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2328 | * contiguous memory region into DMA address space. It is used by all |
2329 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2330 | * Must be called with the domain lock held. |
2331 | */ | |
cb76c322 | 2332 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2333 | struct dma_ops_domain *dma_dom, |
2334 | phys_addr_t paddr, | |
2335 | size_t size, | |
f37f7f33 | 2336 | enum dma_data_direction direction, |
832a90c3 | 2337 | u64 dma_mask) |
cb76c322 JR |
2338 | { |
2339 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2340 | dma_addr_t address, start, ret; |
cb76c322 | 2341 | unsigned int pages; |
518d9b45 | 2342 | int prot = 0; |
cb76c322 JR |
2343 | int i; |
2344 | ||
e3c449f5 | 2345 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2346 | paddr &= PAGE_MASK; |
2347 | ||
256e4621 | 2348 | address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask); |
a869572c | 2349 | if (address == AMD_IOMMU_MAPPING_ERROR) |
266a3bd2 | 2350 | goto out; |
cb76c322 | 2351 | |
f37f7f33 | 2352 | prot = dir2prot(direction); |
518d9b45 | 2353 | |
cb76c322 JR |
2354 | start = address; |
2355 | for (i = 0; i < pages; ++i) { | |
518d9b45 JR |
2356 | ret = iommu_map_page(&dma_dom->domain, start, paddr, |
2357 | PAGE_SIZE, prot, GFP_ATOMIC); | |
2358 | if (ret) | |
53812c11 JR |
2359 | goto out_unmap; |
2360 | ||
cb76c322 JR |
2361 | paddr += PAGE_SIZE; |
2362 | start += PAGE_SIZE; | |
2363 | } | |
2364 | address += offset; | |
2365 | ||
ab7032bb | 2366 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2367 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2368 | domain_flush_complete(&dma_dom->domain); |
2369 | } | |
270cab24 | 2370 | |
cb76c322 JR |
2371 | out: |
2372 | return address; | |
53812c11 JR |
2373 | |
2374 | out_unmap: | |
2375 | ||
2376 | for (--i; i >= 0; --i) { | |
2377 | start -= PAGE_SIZE; | |
518d9b45 | 2378 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
53812c11 JR |
2379 | } |
2380 | ||
256e4621 JR |
2381 | domain_flush_tlb(&dma_dom->domain); |
2382 | domain_flush_complete(&dma_dom->domain); | |
2383 | ||
2384 | dma_ops_free_iova(dma_dom, address, pages); | |
53812c11 | 2385 | |
a869572c | 2386 | return AMD_IOMMU_MAPPING_ERROR; |
cb76c322 JR |
2387 | } |
2388 | ||
431b2a20 JR |
2389 | /* |
2390 | * Does the reverse of the __map_single function. Must be called with | |
2391 | * the domain lock held too | |
2392 | */ | |
cd8c82e8 | 2393 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2394 | dma_addr_t dma_addr, |
2395 | size_t size, | |
2396 | int dir) | |
2397 | { | |
2398 | dma_addr_t i, start; | |
2399 | unsigned int pages; | |
2400 | ||
e3c449f5 | 2401 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2402 | dma_addr &= PAGE_MASK; |
2403 | start = dma_addr; | |
2404 | ||
2405 | for (i = 0; i < pages; ++i) { | |
518d9b45 | 2406 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
cb76c322 JR |
2407 | start += PAGE_SIZE; |
2408 | } | |
2409 | ||
b1516a14 JR |
2410 | if (amd_iommu_unmap_flush) { |
2411 | dma_ops_free_iova(dma_dom, dma_addr, pages); | |
2412 | domain_flush_tlb(&dma_dom->domain); | |
2413 | domain_flush_complete(&dma_dom->domain); | |
2414 | } else { | |
9003d618 JR |
2415 | pages = __roundup_pow_of_two(pages); |
2416 | queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0); | |
b1516a14 | 2417 | } |
cb76c322 JR |
2418 | } |
2419 | ||
431b2a20 JR |
2420 | /* |
2421 | * The exported map_single function for dma_ops. | |
2422 | */ | |
51491367 FT |
2423 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2424 | unsigned long offset, size_t size, | |
2425 | enum dma_data_direction dir, | |
00085f1e | 2426 | unsigned long attrs) |
4da70b9e | 2427 | { |
92d420ec | 2428 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2429 | struct protection_domain *domain; |
b3311b06 | 2430 | struct dma_ops_domain *dma_dom; |
832a90c3 | 2431 | u64 dma_mask; |
4da70b9e | 2432 | |
94f6d190 JR |
2433 | domain = get_domain(dev); |
2434 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2435 | return (dma_addr_t)paddr; |
94f6d190 | 2436 | else if (IS_ERR(domain)) |
a869572c | 2437 | return AMD_IOMMU_MAPPING_ERROR; |
4da70b9e | 2438 | |
f99c0f1c | 2439 | dma_mask = *dev->dma_mask; |
b3311b06 | 2440 | dma_dom = to_dma_ops_domain(domain); |
f99c0f1c | 2441 | |
b3311b06 | 2442 | return __map_single(dev, dma_dom, paddr, size, dir, dma_mask); |
4da70b9e JR |
2443 | } |
2444 | ||
431b2a20 JR |
2445 | /* |
2446 | * The exported unmap_single function for dma_ops. | |
2447 | */ | |
51491367 | 2448 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
00085f1e | 2449 | enum dma_data_direction dir, unsigned long attrs) |
4da70b9e | 2450 | { |
4da70b9e | 2451 | struct protection_domain *domain; |
b3311b06 | 2452 | struct dma_ops_domain *dma_dom; |
4da70b9e | 2453 | |
94f6d190 JR |
2454 | domain = get_domain(dev); |
2455 | if (IS_ERR(domain)) | |
5b28df6f JR |
2456 | return; |
2457 | ||
b3311b06 JR |
2458 | dma_dom = to_dma_ops_domain(domain); |
2459 | ||
2460 | __unmap_single(dma_dom, dma_addr, size, dir); | |
4da70b9e JR |
2461 | } |
2462 | ||
80187fd3 JR |
2463 | static int sg_num_pages(struct device *dev, |
2464 | struct scatterlist *sglist, | |
2465 | int nelems) | |
2466 | { | |
2467 | unsigned long mask, boundary_size; | |
2468 | struct scatterlist *s; | |
2469 | int i, npages = 0; | |
2470 | ||
2471 | mask = dma_get_seg_boundary(dev); | |
2472 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
2473 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
2474 | ||
2475 | for_each_sg(sglist, s, nelems, i) { | |
2476 | int p, n; | |
2477 | ||
2478 | s->dma_address = npages << PAGE_SHIFT; | |
2479 | p = npages % boundary_size; | |
2480 | n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2481 | if (p + n > boundary_size) | |
2482 | npages += boundary_size - p; | |
2483 | npages += n; | |
2484 | } | |
2485 | ||
2486 | return npages; | |
2487 | } | |
2488 | ||
431b2a20 JR |
2489 | /* |
2490 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2491 | * lists). | |
2492 | */ | |
65b050ad | 2493 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
80187fd3 | 2494 | int nelems, enum dma_data_direction direction, |
00085f1e | 2495 | unsigned long attrs) |
65b050ad | 2496 | { |
80187fd3 | 2497 | int mapped_pages = 0, npages = 0, prot = 0, i; |
65b050ad | 2498 | struct protection_domain *domain; |
80187fd3 | 2499 | struct dma_ops_domain *dma_dom; |
65b050ad | 2500 | struct scatterlist *s; |
80187fd3 | 2501 | unsigned long address; |
832a90c3 | 2502 | u64 dma_mask; |
65b050ad | 2503 | |
94f6d190 | 2504 | domain = get_domain(dev); |
a0e191b2 | 2505 | if (IS_ERR(domain)) |
94f6d190 | 2506 | return 0; |
dbcc112e | 2507 | |
b3311b06 | 2508 | dma_dom = to_dma_ops_domain(domain); |
832a90c3 | 2509 | dma_mask = *dev->dma_mask; |
65b050ad | 2510 | |
80187fd3 JR |
2511 | npages = sg_num_pages(dev, sglist, nelems); |
2512 | ||
2513 | address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask); | |
a869572c | 2514 | if (address == AMD_IOMMU_MAPPING_ERROR) |
80187fd3 JR |
2515 | goto out_err; |
2516 | ||
2517 | prot = dir2prot(direction); | |
2518 | ||
2519 | /* Map all sg entries */ | |
65b050ad | 2520 | for_each_sg(sglist, s, nelems, i) { |
80187fd3 JR |
2521 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); |
2522 | ||
2523 | for (j = 0; j < pages; ++j) { | |
2524 | unsigned long bus_addr, phys_addr; | |
2525 | int ret; | |
65b050ad | 2526 | |
80187fd3 JR |
2527 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2528 | phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT); | |
2529 | ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC); | |
2530 | if (ret) | |
2531 | goto out_unmap; | |
65b050ad | 2532 | |
80187fd3 JR |
2533 | mapped_pages += 1; |
2534 | } | |
65b050ad JR |
2535 | } |
2536 | ||
80187fd3 JR |
2537 | /* Everything is mapped - write the right values into s->dma_address */ |
2538 | for_each_sg(sglist, s, nelems, i) { | |
2539 | s->dma_address += address + s->offset; | |
2540 | s->dma_length = s->length; | |
2541 | } | |
2542 | ||
2543 | return nelems; | |
2544 | ||
2545 | out_unmap: | |
2546 | pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n", | |
2547 | dev_name(dev), npages); | |
2548 | ||
2549 | for_each_sg(sglist, s, nelems, i) { | |
2550 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2551 | ||
2552 | for (j = 0; j < pages; ++j) { | |
2553 | unsigned long bus_addr; | |
92d420ec | 2554 | |
80187fd3 JR |
2555 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2556 | iommu_unmap_page(domain, bus_addr, PAGE_SIZE); | |
2557 | ||
2558 | if (--mapped_pages) | |
2559 | goto out_free_iova; | |
2560 | } | |
65b050ad JR |
2561 | } |
2562 | ||
80187fd3 JR |
2563 | out_free_iova: |
2564 | free_iova_fast(&dma_dom->iovad, address, npages); | |
2565 | ||
2566 | out_err: | |
92d420ec | 2567 | return 0; |
65b050ad JR |
2568 | } |
2569 | ||
431b2a20 JR |
2570 | /* |
2571 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2572 | * lists). | |
2573 | */ | |
65b050ad | 2574 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e | 2575 | int nelems, enum dma_data_direction dir, |
00085f1e | 2576 | unsigned long attrs) |
65b050ad | 2577 | { |
65b050ad | 2578 | struct protection_domain *domain; |
b3311b06 | 2579 | struct dma_ops_domain *dma_dom; |
80187fd3 JR |
2580 | unsigned long startaddr; |
2581 | int npages = 2; | |
65b050ad | 2582 | |
94f6d190 JR |
2583 | domain = get_domain(dev); |
2584 | if (IS_ERR(domain)) | |
5b28df6f JR |
2585 | return; |
2586 | ||
80187fd3 | 2587 | startaddr = sg_dma_address(sglist) & PAGE_MASK; |
b3311b06 | 2588 | dma_dom = to_dma_ops_domain(domain); |
80187fd3 JR |
2589 | npages = sg_num_pages(dev, sglist, nelems); |
2590 | ||
b3311b06 | 2591 | __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir); |
65b050ad JR |
2592 | } |
2593 | ||
431b2a20 JR |
2594 | /* |
2595 | * The exported alloc_coherent function for dma_ops. | |
2596 | */ | |
5d8b53cf | 2597 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc | 2598 | dma_addr_t *dma_addr, gfp_t flag, |
00085f1e | 2599 | unsigned long attrs) |
5d8b53cf | 2600 | { |
832a90c3 | 2601 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 | 2602 | struct protection_domain *domain; |
b3311b06 | 2603 | struct dma_ops_domain *dma_dom; |
3b839a57 | 2604 | struct page *page; |
5d8b53cf | 2605 | |
94f6d190 JR |
2606 | domain = get_domain(dev); |
2607 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2608 | page = alloc_pages(flag, get_order(size)); |
2609 | *dma_addr = page_to_phys(page); | |
2610 | return page_address(page); | |
94f6d190 JR |
2611 | } else if (IS_ERR(domain)) |
2612 | return NULL; | |
5d8b53cf | 2613 | |
b3311b06 | 2614 | dma_dom = to_dma_ops_domain(domain); |
3b839a57 | 2615 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2616 | dma_mask = dev->coherent_dma_mask; |
2617 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2618 | flag |= __GFP_ZERO; |
5d8b53cf | 2619 | |
3b839a57 JR |
2620 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2621 | if (!page) { | |
d0164adc | 2622 | if (!gfpflags_allow_blocking(flag)) |
3b839a57 | 2623 | return NULL; |
5d8b53cf | 2624 | |
3b839a57 | 2625 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
712c604d | 2626 | get_order(size), flag); |
3b839a57 JR |
2627 | if (!page) |
2628 | return NULL; | |
2629 | } | |
5d8b53cf | 2630 | |
832a90c3 JR |
2631 | if (!dma_mask) |
2632 | dma_mask = *dev->dma_mask; | |
2633 | ||
b3311b06 | 2634 | *dma_addr = __map_single(dev, dma_dom, page_to_phys(page), |
bda350db | 2635 | size, DMA_BIDIRECTIONAL, dma_mask); |
5d8b53cf | 2636 | |
a869572c | 2637 | if (*dma_addr == AMD_IOMMU_MAPPING_ERROR) |
5b28df6f | 2638 | goto out_free; |
5d8b53cf | 2639 | |
3b839a57 | 2640 | return page_address(page); |
5b28df6f JR |
2641 | |
2642 | out_free: | |
2643 | ||
3b839a57 JR |
2644 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2645 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2646 | |
2647 | return NULL; | |
5d8b53cf JR |
2648 | } |
2649 | ||
431b2a20 JR |
2650 | /* |
2651 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2652 | */ |
5d8b53cf | 2653 | static void free_coherent(struct device *dev, size_t size, |
baa676fc | 2654 | void *virt_addr, dma_addr_t dma_addr, |
00085f1e | 2655 | unsigned long attrs) |
5d8b53cf | 2656 | { |
5d8b53cf | 2657 | struct protection_domain *domain; |
b3311b06 | 2658 | struct dma_ops_domain *dma_dom; |
3b839a57 | 2659 | struct page *page; |
5d8b53cf | 2660 | |
3b839a57 JR |
2661 | page = virt_to_page(virt_addr); |
2662 | size = PAGE_ALIGN(size); | |
2663 | ||
94f6d190 JR |
2664 | domain = get_domain(dev); |
2665 | if (IS_ERR(domain)) | |
5b28df6f JR |
2666 | goto free_mem; |
2667 | ||
b3311b06 JR |
2668 | dma_dom = to_dma_ops_domain(domain); |
2669 | ||
2670 | __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 2671 | |
5d8b53cf | 2672 | free_mem: |
3b839a57 JR |
2673 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2674 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2675 | } |
2676 | ||
b39ba6ad JR |
2677 | /* |
2678 | * This function is called by the DMA layer to find out if we can handle a | |
2679 | * particular device. It is part of the dma_ops. | |
2680 | */ | |
2681 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2682 | { | |
5860acc1 CH |
2683 | if (!x86_dma_supported(dev, mask)) |
2684 | return 0; | |
420aef8a | 2685 | return check_device(dev); |
b39ba6ad JR |
2686 | } |
2687 | ||
a869572c CH |
2688 | static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr) |
2689 | { | |
2690 | return dma_addr == AMD_IOMMU_MAPPING_ERROR; | |
2691 | } | |
2692 | ||
5299709d | 2693 | static const struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2694 | .alloc = alloc_coherent, |
2695 | .free = free_coherent, | |
2696 | .map_page = map_page, | |
2697 | .unmap_page = unmap_page, | |
2698 | .map_sg = map_sg, | |
2699 | .unmap_sg = unmap_sg, | |
2700 | .dma_supported = amd_iommu_dma_supported, | |
a869572c | 2701 | .mapping_error = amd_iommu_mapping_error, |
6631ee9d JR |
2702 | }; |
2703 | ||
81cd07b9 JR |
2704 | static int init_reserved_iova_ranges(void) |
2705 | { | |
2706 | struct pci_dev *pdev = NULL; | |
2707 | struct iova *val; | |
2708 | ||
aa3ac946 | 2709 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN); |
81cd07b9 JR |
2710 | |
2711 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, | |
2712 | &reserved_rbtree_key); | |
2713 | ||
2714 | /* MSI memory range */ | |
2715 | val = reserve_iova(&reserved_iova_ranges, | |
2716 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); | |
2717 | if (!val) { | |
2718 | pr_err("Reserving MSI range failed\n"); | |
2719 | return -ENOMEM; | |
2720 | } | |
2721 | ||
2722 | /* HT memory range */ | |
2723 | val = reserve_iova(&reserved_iova_ranges, | |
2724 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); | |
2725 | if (!val) { | |
2726 | pr_err("Reserving HT range failed\n"); | |
2727 | return -ENOMEM; | |
2728 | } | |
2729 | ||
2730 | /* | |
2731 | * Memory used for PCI resources | |
2732 | * FIXME: Check whether we can reserve the PCI-hole completly | |
2733 | */ | |
2734 | for_each_pci_dev(pdev) { | |
2735 | int i; | |
2736 | ||
2737 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { | |
2738 | struct resource *r = &pdev->resource[i]; | |
2739 | ||
2740 | if (!(r->flags & IORESOURCE_MEM)) | |
2741 | continue; | |
2742 | ||
2743 | val = reserve_iova(&reserved_iova_ranges, | |
2744 | IOVA_PFN(r->start), | |
2745 | IOVA_PFN(r->end)); | |
2746 | if (!val) { | |
2747 | pr_err("Reserve pci-resource range failed\n"); | |
2748 | return -ENOMEM; | |
2749 | } | |
2750 | } | |
2751 | } | |
2752 | ||
2753 | return 0; | |
2754 | } | |
2755 | ||
3a18404c | 2756 | int __init amd_iommu_init_api(void) |
27c2127a | 2757 | { |
460c26d0 | 2758 | int ret, err = 0; |
307d5851 JR |
2759 | |
2760 | ret = iova_cache_get(); | |
2761 | if (ret) | |
2762 | return ret; | |
9a4d3bf5 | 2763 | |
81cd07b9 JR |
2764 | ret = init_reserved_iova_ranges(); |
2765 | if (ret) | |
2766 | return ret; | |
2767 | ||
9a4d3bf5 WZ |
2768 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
2769 | if (err) | |
2770 | return err; | |
2771 | #ifdef CONFIG_ARM_AMBA | |
2772 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
2773 | if (err) | |
2774 | return err; | |
2775 | #endif | |
0076cd3d WZ |
2776 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
2777 | if (err) | |
2778 | return err; | |
c5b5da9c | 2779 | |
460c26d0 | 2780 | return 0; |
f5325094 JR |
2781 | } |
2782 | ||
6631ee9d JR |
2783 | int __init amd_iommu_init_dma_ops(void) |
2784 | { | |
aba2d9a6 | 2785 | swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0; |
6631ee9d | 2786 | iommu_detected = 1; |
6631ee9d | 2787 | |
52717828 JR |
2788 | /* |
2789 | * In case we don't initialize SWIOTLB (actually the common case | |
aba2d9a6 TL |
2790 | * when AMD IOMMU is enabled and SME is not active), make sure there |
2791 | * are global dma_ops set as a fall-back for devices not handled by | |
2792 | * this driver (for example non-PCI devices). When SME is active, | |
2793 | * make sure that swiotlb variable remains set so the global dma_ops | |
2794 | * continue to be SWIOTLB. | |
52717828 JR |
2795 | */ |
2796 | if (!swiotlb) | |
2797 | dma_ops = &nommu_dma_ops; | |
2798 | ||
62410eeb JR |
2799 | if (amd_iommu_unmap_flush) |
2800 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2801 | else | |
2802 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2803 | ||
6631ee9d | 2804 | return 0; |
c5b5da9c | 2805 | |
6631ee9d | 2806 | } |
6d98cd80 JR |
2807 | |
2808 | /***************************************************************************** | |
2809 | * | |
2810 | * The following functions belong to the exported interface of AMD IOMMU | |
2811 | * | |
2812 | * This interface allows access to lower level functions of the IOMMU | |
2813 | * like protection domain handling and assignement of devices to domains | |
2814 | * which is not possible with the dma_ops interface. | |
2815 | * | |
2816 | *****************************************************************************/ | |
2817 | ||
6d98cd80 JR |
2818 | static void cleanup_domain(struct protection_domain *domain) |
2819 | { | |
9b29d3c6 | 2820 | struct iommu_dev_data *entry; |
6d98cd80 | 2821 | unsigned long flags; |
6d98cd80 JR |
2822 | |
2823 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2824 | ||
9b29d3c6 JR |
2825 | while (!list_empty(&domain->dev_list)) { |
2826 | entry = list_first_entry(&domain->dev_list, | |
2827 | struct iommu_dev_data, list); | |
2828 | __detach_device(entry); | |
492667da | 2829 | } |
6d98cd80 JR |
2830 | |
2831 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2832 | } | |
2833 | ||
2650815f JR |
2834 | static void protection_domain_free(struct protection_domain *domain) |
2835 | { | |
2836 | if (!domain) | |
2837 | return; | |
2838 | ||
aeb26f55 JR |
2839 | del_domain_from_list(domain); |
2840 | ||
2650815f JR |
2841 | if (domain->id) |
2842 | domain_id_free(domain->id); | |
2843 | ||
2844 | kfree(domain); | |
2845 | } | |
2846 | ||
7a5a566e JR |
2847 | static int protection_domain_init(struct protection_domain *domain) |
2848 | { | |
2849 | spin_lock_init(&domain->lock); | |
2850 | mutex_init(&domain->api_lock); | |
2851 | domain->id = domain_id_alloc(); | |
2852 | if (!domain->id) | |
2853 | return -ENOMEM; | |
2854 | INIT_LIST_HEAD(&domain->dev_list); | |
2855 | ||
2856 | return 0; | |
2857 | } | |
2858 | ||
2650815f | 2859 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2860 | { |
2861 | struct protection_domain *domain; | |
2862 | ||
2863 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2864 | if (!domain) | |
2650815f | 2865 | return NULL; |
c156e347 | 2866 | |
7a5a566e | 2867 | if (protection_domain_init(domain)) |
2650815f JR |
2868 | goto out_err; |
2869 | ||
aeb26f55 JR |
2870 | add_domain_to_list(domain); |
2871 | ||
2650815f JR |
2872 | return domain; |
2873 | ||
2874 | out_err: | |
2875 | kfree(domain); | |
2876 | ||
2877 | return NULL; | |
2878 | } | |
2879 | ||
3f4b87b9 | 2880 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2881 | { |
3f4b87b9 | 2882 | struct protection_domain *pdomain; |
0bb6e243 | 2883 | struct dma_ops_domain *dma_domain; |
2650815f | 2884 | |
0bb6e243 JR |
2885 | switch (type) { |
2886 | case IOMMU_DOMAIN_UNMANAGED: | |
2887 | pdomain = protection_domain_alloc(); | |
2888 | if (!pdomain) | |
2889 | return NULL; | |
c156e347 | 2890 | |
0bb6e243 JR |
2891 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2892 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2893 | if (!pdomain->pt_root) { | |
2894 | protection_domain_free(pdomain); | |
2895 | return NULL; | |
2896 | } | |
c156e347 | 2897 | |
0bb6e243 JR |
2898 | pdomain->domain.geometry.aperture_start = 0; |
2899 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2900 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2901 | |
0bb6e243 JR |
2902 | break; |
2903 | case IOMMU_DOMAIN_DMA: | |
2904 | dma_domain = dma_ops_domain_alloc(); | |
2905 | if (!dma_domain) { | |
2906 | pr_err("AMD-Vi: Failed to allocate\n"); | |
2907 | return NULL; | |
2908 | } | |
2909 | pdomain = &dma_domain->domain; | |
2910 | break; | |
07f643a3 JR |
2911 | case IOMMU_DOMAIN_IDENTITY: |
2912 | pdomain = protection_domain_alloc(); | |
2913 | if (!pdomain) | |
2914 | return NULL; | |
c156e347 | 2915 | |
07f643a3 JR |
2916 | pdomain->mode = PAGE_MODE_NONE; |
2917 | break; | |
0bb6e243 JR |
2918 | default: |
2919 | return NULL; | |
2920 | } | |
c156e347 | 2921 | |
3f4b87b9 | 2922 | return &pdomain->domain; |
c156e347 JR |
2923 | } |
2924 | ||
3f4b87b9 | 2925 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2926 | { |
3f4b87b9 | 2927 | struct protection_domain *domain; |
cda7005b | 2928 | struct dma_ops_domain *dma_dom; |
98383fc3 | 2929 | |
3f4b87b9 JR |
2930 | domain = to_pdomain(dom); |
2931 | ||
98383fc3 JR |
2932 | if (domain->dev_cnt > 0) |
2933 | cleanup_domain(domain); | |
2934 | ||
2935 | BUG_ON(domain->dev_cnt != 0); | |
2936 | ||
cda7005b JR |
2937 | if (!dom) |
2938 | return; | |
98383fc3 | 2939 | |
cda7005b JR |
2940 | switch (dom->type) { |
2941 | case IOMMU_DOMAIN_DMA: | |
281e8ccb | 2942 | /* Now release the domain */ |
b3311b06 | 2943 | dma_dom = to_dma_ops_domain(domain); |
cda7005b JR |
2944 | dma_ops_domain_free(dma_dom); |
2945 | break; | |
2946 | default: | |
2947 | if (domain->mode != PAGE_MODE_NONE) | |
2948 | free_pagetable(domain); | |
52815b75 | 2949 | |
cda7005b JR |
2950 | if (domain->flags & PD_IOMMUV2_MASK) |
2951 | free_gcr3_table(domain); | |
2952 | ||
2953 | protection_domain_free(domain); | |
2954 | break; | |
2955 | } | |
98383fc3 JR |
2956 | } |
2957 | ||
684f2888 JR |
2958 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2959 | struct device *dev) | |
2960 | { | |
657cbb6b | 2961 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2962 | struct amd_iommu *iommu; |
7aba6cb9 | 2963 | int devid; |
684f2888 | 2964 | |
98fc5a69 | 2965 | if (!check_device(dev)) |
684f2888 JR |
2966 | return; |
2967 | ||
98fc5a69 | 2968 | devid = get_device_id(dev); |
9ee35e4c | 2969 | if (devid < 0) |
7aba6cb9 | 2970 | return; |
684f2888 | 2971 | |
657cbb6b | 2972 | if (dev_data->domain != NULL) |
15898bbc | 2973 | detach_device(dev); |
684f2888 JR |
2974 | |
2975 | iommu = amd_iommu_rlookup_table[devid]; | |
2976 | if (!iommu) | |
2977 | return; | |
2978 | ||
d98de49a SS |
2979 | #ifdef CONFIG_IRQ_REMAP |
2980 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && | |
2981 | (dom->type == IOMMU_DOMAIN_UNMANAGED)) | |
2982 | dev_data->use_vapic = 0; | |
2983 | #endif | |
2984 | ||
684f2888 JR |
2985 | iommu_completion_wait(iommu); |
2986 | } | |
2987 | ||
01106066 JR |
2988 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2989 | struct device *dev) | |
2990 | { | |
3f4b87b9 | 2991 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 2992 | struct iommu_dev_data *dev_data; |
01106066 | 2993 | struct amd_iommu *iommu; |
15898bbc | 2994 | int ret; |
01106066 | 2995 | |
98fc5a69 | 2996 | if (!check_device(dev)) |
01106066 JR |
2997 | return -EINVAL; |
2998 | ||
657cbb6b JR |
2999 | dev_data = dev->archdata.iommu; |
3000 | ||
f62dda66 | 3001 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3002 | if (!iommu) |
3003 | return -EINVAL; | |
3004 | ||
657cbb6b | 3005 | if (dev_data->domain) |
15898bbc | 3006 | detach_device(dev); |
01106066 | 3007 | |
15898bbc | 3008 | ret = attach_device(dev, domain); |
01106066 | 3009 | |
d98de49a SS |
3010 | #ifdef CONFIG_IRQ_REMAP |
3011 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
3012 | if (dom->type == IOMMU_DOMAIN_UNMANAGED) | |
3013 | dev_data->use_vapic = 1; | |
3014 | else | |
3015 | dev_data->use_vapic = 0; | |
3016 | } | |
3017 | #endif | |
3018 | ||
01106066 JR |
3019 | iommu_completion_wait(iommu); |
3020 | ||
15898bbc | 3021 | return ret; |
01106066 JR |
3022 | } |
3023 | ||
468e2366 | 3024 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3025 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3026 | { |
3f4b87b9 | 3027 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3028 | int prot = 0; |
3029 | int ret; | |
3030 | ||
132bd68f JR |
3031 | if (domain->mode == PAGE_MODE_NONE) |
3032 | return -EINVAL; | |
3033 | ||
c6229ca6 JR |
3034 | if (iommu_prot & IOMMU_READ) |
3035 | prot |= IOMMU_PROT_IR; | |
3036 | if (iommu_prot & IOMMU_WRITE) | |
3037 | prot |= IOMMU_PROT_IW; | |
3038 | ||
5d214fe6 | 3039 | mutex_lock(&domain->api_lock); |
b911b89b | 3040 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); |
5d214fe6 JR |
3041 | mutex_unlock(&domain->api_lock); |
3042 | ||
795e74f7 | 3043 | return ret; |
c6229ca6 JR |
3044 | } |
3045 | ||
5009065d OBC |
3046 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3047 | size_t page_size) | |
eb74ff6c | 3048 | { |
3f4b87b9 | 3049 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3050 | size_t unmap_size; |
eb74ff6c | 3051 | |
132bd68f JR |
3052 | if (domain->mode == PAGE_MODE_NONE) |
3053 | return -EINVAL; | |
3054 | ||
5d214fe6 | 3055 | mutex_lock(&domain->api_lock); |
468e2366 | 3056 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3057 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3058 | |
17b124bf | 3059 | domain_flush_tlb_pde(domain); |
ce76353f | 3060 | domain_flush_complete(domain); |
5d214fe6 | 3061 | |
5009065d | 3062 | return unmap_size; |
eb74ff6c JR |
3063 | } |
3064 | ||
645c4c8d | 3065 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3066 | dma_addr_t iova) |
645c4c8d | 3067 | { |
3f4b87b9 | 3068 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3069 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3070 | u64 *pte, __pte; |
645c4c8d | 3071 | |
132bd68f JR |
3072 | if (domain->mode == PAGE_MODE_NONE) |
3073 | return iova; | |
3074 | ||
3039ca1b | 3075 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3076 | |
a6d41a40 | 3077 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3078 | return 0; |
3079 | ||
b24b1b63 JR |
3080 | offset_mask = pte_pgsize - 1; |
3081 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3082 | |
b24b1b63 | 3083 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3084 | } |
3085 | ||
ab636481 | 3086 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3087 | { |
80a506b8 JR |
3088 | switch (cap) { |
3089 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3090 | return true; |
bdddadcb | 3091 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3092 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3093 | case IOMMU_CAP_NOEXEC: |
3094 | return false; | |
80a506b8 JR |
3095 | } |
3096 | ||
ab636481 | 3097 | return false; |
dbb9fd86 SY |
3098 | } |
3099 | ||
e5b5234a EA |
3100 | static void amd_iommu_get_resv_regions(struct device *dev, |
3101 | struct list_head *head) | |
35cf248f | 3102 | { |
4397f32c | 3103 | struct iommu_resv_region *region; |
35cf248f | 3104 | struct unity_map_entry *entry; |
7aba6cb9 | 3105 | int devid; |
35cf248f JR |
3106 | |
3107 | devid = get_device_id(dev); | |
9ee35e4c | 3108 | if (devid < 0) |
7aba6cb9 | 3109 | return; |
35cf248f JR |
3110 | |
3111 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
4397f32c EA |
3112 | size_t length; |
3113 | int prot = 0; | |
35cf248f JR |
3114 | |
3115 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3116 | continue; | |
3117 | ||
4397f32c EA |
3118 | length = entry->address_end - entry->address_start; |
3119 | if (entry->prot & IOMMU_PROT_IR) | |
3120 | prot |= IOMMU_READ; | |
3121 | if (entry->prot & IOMMU_PROT_IW) | |
3122 | prot |= IOMMU_WRITE; | |
3123 | ||
3124 | region = iommu_alloc_resv_region(entry->address_start, | |
3125 | length, prot, | |
3126 | IOMMU_RESV_DIRECT); | |
35cf248f JR |
3127 | if (!region) { |
3128 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3129 | dev_name(dev)); | |
3130 | return; | |
3131 | } | |
35cf248f JR |
3132 | list_add_tail(®ion->list, head); |
3133 | } | |
4397f32c EA |
3134 | |
3135 | region = iommu_alloc_resv_region(MSI_RANGE_START, | |
3136 | MSI_RANGE_END - MSI_RANGE_START + 1, | |
9d3a4de4 | 3137 | 0, IOMMU_RESV_MSI); |
4397f32c EA |
3138 | if (!region) |
3139 | return; | |
3140 | list_add_tail(®ion->list, head); | |
3141 | ||
3142 | region = iommu_alloc_resv_region(HT_RANGE_START, | |
3143 | HT_RANGE_END - HT_RANGE_START + 1, | |
3144 | 0, IOMMU_RESV_RESERVED); | |
3145 | if (!region) | |
3146 | return; | |
3147 | list_add_tail(®ion->list, head); | |
35cf248f JR |
3148 | } |
3149 | ||
e5b5234a | 3150 | static void amd_iommu_put_resv_regions(struct device *dev, |
35cf248f JR |
3151 | struct list_head *head) |
3152 | { | |
e5b5234a | 3153 | struct iommu_resv_region *entry, *next; |
35cf248f JR |
3154 | |
3155 | list_for_each_entry_safe(entry, next, head, list) | |
3156 | kfree(entry); | |
3157 | } | |
3158 | ||
e5b5234a | 3159 | static void amd_iommu_apply_resv_region(struct device *dev, |
8d54d6c8 | 3160 | struct iommu_domain *domain, |
e5b5234a | 3161 | struct iommu_resv_region *region) |
8d54d6c8 | 3162 | { |
b3311b06 | 3163 | struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain)); |
8d54d6c8 JR |
3164 | unsigned long start, end; |
3165 | ||
3166 | start = IOVA_PFN(region->start); | |
b92b4fb5 | 3167 | end = IOVA_PFN(region->start + region->length - 1); |
8d54d6c8 JR |
3168 | |
3169 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); | |
3170 | } | |
3171 | ||
df3f7a6e BH |
3172 | static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain, |
3173 | struct device *dev) | |
3174 | { | |
3175 | struct iommu_dev_data *dev_data = dev->archdata.iommu; | |
3176 | return dev_data->defer_attach; | |
3177 | } | |
3178 | ||
b0119e87 | 3179 | const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3180 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3181 | .domain_alloc = amd_iommu_domain_alloc, |
3182 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3183 | .attach_dev = amd_iommu_attach_device, |
3184 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3185 | .map = amd_iommu_map, |
3186 | .unmap = amd_iommu_unmap, | |
315786eb | 3187 | .map_sg = default_iommu_map_sg, |
26961efe | 3188 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3189 | .add_device = amd_iommu_add_device, |
3190 | .remove_device = amd_iommu_remove_device, | |
b097d11a | 3191 | .device_group = amd_iommu_device_group, |
e5b5234a EA |
3192 | .get_resv_regions = amd_iommu_get_resv_regions, |
3193 | .put_resv_regions = amd_iommu_put_resv_regions, | |
3194 | .apply_resv_region = amd_iommu_apply_resv_region, | |
df3f7a6e | 3195 | .is_attach_deferred = amd_iommu_is_attach_deferred, |
aa3de9c0 | 3196 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3197 | }; |
3198 | ||
0feae533 JR |
3199 | /***************************************************************************** |
3200 | * | |
3201 | * The next functions do a basic initialization of IOMMU for pass through | |
3202 | * mode | |
3203 | * | |
3204 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3205 | * DMA-API translation. | |
3206 | * | |
3207 | *****************************************************************************/ | |
3208 | ||
72e1dcc4 JR |
3209 | /* IOMMUv2 specific functions */ |
3210 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3211 | { | |
3212 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3213 | } | |
3214 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3215 | ||
3216 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3217 | { | |
3218 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3219 | } | |
3220 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3221 | |
3222 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3223 | { | |
3f4b87b9 | 3224 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3225 | unsigned long flags; |
3226 | ||
3227 | spin_lock_irqsave(&domain->lock, flags); | |
3228 | ||
3229 | /* Update data structure */ | |
3230 | domain->mode = PAGE_MODE_NONE; | |
3231 | domain->updated = true; | |
3232 | ||
3233 | /* Make changes visible to IOMMUs */ | |
3234 | update_domain(domain); | |
3235 | ||
3236 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3237 | free_pagetable(domain); | |
3238 | ||
3239 | spin_unlock_irqrestore(&domain->lock, flags); | |
3240 | } | |
3241 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3242 | |
3243 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3244 | { | |
3f4b87b9 | 3245 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3246 | unsigned long flags; |
3247 | int levels, ret; | |
3248 | ||
3249 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3250 | return -EINVAL; | |
3251 | ||
3252 | /* Number of GCR3 table levels required */ | |
3253 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3254 | levels += 1; | |
3255 | ||
3256 | if (levels > amd_iommu_max_glx_val) | |
3257 | return -EINVAL; | |
3258 | ||
3259 | spin_lock_irqsave(&domain->lock, flags); | |
3260 | ||
3261 | /* | |
3262 | * Save us all sanity checks whether devices already in the | |
3263 | * domain support IOMMUv2. Just force that the domain has no | |
3264 | * devices attached when it is switched into IOMMUv2 mode. | |
3265 | */ | |
3266 | ret = -EBUSY; | |
3267 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3268 | goto out; | |
3269 | ||
3270 | ret = -ENOMEM; | |
3271 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3272 | if (domain->gcr3_tbl == NULL) | |
3273 | goto out; | |
3274 | ||
3275 | domain->glx = levels; | |
3276 | domain->flags |= PD_IOMMUV2_MASK; | |
3277 | domain->updated = true; | |
3278 | ||
3279 | update_domain(domain); | |
3280 | ||
3281 | ret = 0; | |
3282 | ||
3283 | out: | |
3284 | spin_unlock_irqrestore(&domain->lock, flags); | |
3285 | ||
3286 | return ret; | |
3287 | } | |
3288 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3289 | |
3290 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3291 | u64 address, bool size) | |
3292 | { | |
3293 | struct iommu_dev_data *dev_data; | |
3294 | struct iommu_cmd cmd; | |
3295 | int i, ret; | |
3296 | ||
3297 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3298 | return -EINVAL; | |
3299 | ||
3300 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3301 | ||
3302 | /* | |
3303 | * IOMMU TLB needs to be flushed before Device TLB to | |
3304 | * prevent device TLB refill from IOMMU TLB | |
3305 | */ | |
6b9376e3 | 3306 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
22e266c7 JR |
3307 | if (domain->dev_iommu[i] == 0) |
3308 | continue; | |
3309 | ||
3310 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3311 | if (ret != 0) | |
3312 | goto out; | |
3313 | } | |
3314 | ||
3315 | /* Wait until IOMMU TLB flushes are complete */ | |
3316 | domain_flush_complete(domain); | |
3317 | ||
3318 | /* Now flush device TLBs */ | |
3319 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3320 | struct amd_iommu *iommu; | |
3321 | int qdep; | |
3322 | ||
1c1cc454 JR |
3323 | /* |
3324 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3325 | * domain. | |
3326 | */ | |
3327 | if (!dev_data->ats.enabled) | |
3328 | continue; | |
22e266c7 JR |
3329 | |
3330 | qdep = dev_data->ats.qdep; | |
3331 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3332 | ||
3333 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3334 | qdep, address, size); | |
3335 | ||
3336 | ret = iommu_queue_command(iommu, &cmd); | |
3337 | if (ret != 0) | |
3338 | goto out; | |
3339 | } | |
3340 | ||
3341 | /* Wait until all device TLBs are flushed */ | |
3342 | domain_flush_complete(domain); | |
3343 | ||
3344 | ret = 0; | |
3345 | ||
3346 | out: | |
3347 | ||
3348 | return ret; | |
3349 | } | |
3350 | ||
3351 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3352 | u64 address) | |
3353 | { | |
3354 | return __flush_pasid(domain, pasid, address, false); | |
3355 | } | |
3356 | ||
3357 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3358 | u64 address) | |
3359 | { | |
3f4b87b9 | 3360 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3361 | unsigned long flags; |
3362 | int ret; | |
3363 | ||
3364 | spin_lock_irqsave(&domain->lock, flags); | |
3365 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3366 | spin_unlock_irqrestore(&domain->lock, flags); | |
3367 | ||
3368 | return ret; | |
3369 | } | |
3370 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3371 | ||
3372 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3373 | { | |
3374 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3375 | true); | |
3376 | } | |
3377 | ||
3378 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3379 | { | |
3f4b87b9 | 3380 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3381 | unsigned long flags; |
3382 | int ret; | |
3383 | ||
3384 | spin_lock_irqsave(&domain->lock, flags); | |
3385 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3386 | spin_unlock_irqrestore(&domain->lock, flags); | |
3387 | ||
3388 | return ret; | |
3389 | } | |
3390 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3391 | ||
b16137b1 JR |
3392 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3393 | { | |
3394 | int index; | |
3395 | u64 *pte; | |
3396 | ||
3397 | while (true) { | |
3398 | ||
3399 | index = (pasid >> (9 * level)) & 0x1ff; | |
3400 | pte = &root[index]; | |
3401 | ||
3402 | if (level == 0) | |
3403 | break; | |
3404 | ||
3405 | if (!(*pte & GCR3_VALID)) { | |
3406 | if (!alloc) | |
3407 | return NULL; | |
3408 | ||
3409 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3410 | if (root == NULL) | |
3411 | return NULL; | |
3412 | ||
2543a786 | 3413 | *pte = iommu_virt_to_phys(root) | GCR3_VALID; |
b16137b1 JR |
3414 | } |
3415 | ||
2543a786 | 3416 | root = iommu_phys_to_virt(*pte & PAGE_MASK); |
b16137b1 JR |
3417 | |
3418 | level -= 1; | |
3419 | } | |
3420 | ||
3421 | return pte; | |
3422 | } | |
3423 | ||
3424 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3425 | unsigned long cr3) | |
3426 | { | |
3427 | u64 *pte; | |
3428 | ||
3429 | if (domain->mode != PAGE_MODE_NONE) | |
3430 | return -EINVAL; | |
3431 | ||
3432 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3433 | if (pte == NULL) | |
3434 | return -ENOMEM; | |
3435 | ||
3436 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3437 | ||
3438 | return __amd_iommu_flush_tlb(domain, pasid); | |
3439 | } | |
3440 | ||
3441 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3442 | { | |
3443 | u64 *pte; | |
3444 | ||
3445 | if (domain->mode != PAGE_MODE_NONE) | |
3446 | return -EINVAL; | |
3447 | ||
3448 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3449 | if (pte == NULL) | |
3450 | return 0; | |
3451 | ||
3452 | *pte = 0; | |
3453 | ||
3454 | return __amd_iommu_flush_tlb(domain, pasid); | |
3455 | } | |
3456 | ||
3457 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3458 | unsigned long cr3) | |
3459 | { | |
3f4b87b9 | 3460 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3461 | unsigned long flags; |
3462 | int ret; | |
3463 | ||
3464 | spin_lock_irqsave(&domain->lock, flags); | |
3465 | ret = __set_gcr3(domain, pasid, cr3); | |
3466 | spin_unlock_irqrestore(&domain->lock, flags); | |
3467 | ||
3468 | return ret; | |
3469 | } | |
3470 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3471 | ||
3472 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3473 | { | |
3f4b87b9 | 3474 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3475 | unsigned long flags; |
3476 | int ret; | |
3477 | ||
3478 | spin_lock_irqsave(&domain->lock, flags); | |
3479 | ret = __clear_gcr3(domain, pasid); | |
3480 | spin_unlock_irqrestore(&domain->lock, flags); | |
3481 | ||
3482 | return ret; | |
3483 | } | |
3484 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3485 | |
3486 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3487 | int status, int tag) | |
3488 | { | |
3489 | struct iommu_dev_data *dev_data; | |
3490 | struct amd_iommu *iommu; | |
3491 | struct iommu_cmd cmd; | |
3492 | ||
3493 | dev_data = get_dev_data(&pdev->dev); | |
3494 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3495 | ||
3496 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3497 | tag, dev_data->pri_tlp); | |
3498 | ||
3499 | return iommu_queue_command(iommu, &cmd); | |
3500 | } | |
3501 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3502 | |
3503 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3504 | { | |
3f4b87b9 | 3505 | struct protection_domain *pdomain; |
f3572db8 | 3506 | |
3f4b87b9 JR |
3507 | pdomain = get_domain(&pdev->dev); |
3508 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3509 | return NULL; |
3510 | ||
3511 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3512 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3513 | return NULL; |
3514 | ||
3f4b87b9 | 3515 | return &pdomain->domain; |
f3572db8 JR |
3516 | } |
3517 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3518 | |
3519 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3520 | { | |
3521 | struct iommu_dev_data *dev_data; | |
3522 | ||
3523 | if (!amd_iommu_v2_supported()) | |
3524 | return; | |
3525 | ||
3526 | dev_data = get_dev_data(&pdev->dev); | |
3527 | dev_data->errata |= (1 << erratum); | |
3528 | } | |
3529 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3530 | |
3531 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3532 | struct amd_iommu_device_info *info) | |
3533 | { | |
3534 | int max_pasids; | |
3535 | int pos; | |
3536 | ||
3537 | if (pdev == NULL || info == NULL) | |
3538 | return -EINVAL; | |
3539 | ||
3540 | if (!amd_iommu_v2_supported()) | |
3541 | return -EINVAL; | |
3542 | ||
3543 | memset(info, 0, sizeof(*info)); | |
3544 | ||
3545 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3546 | if (pos) | |
3547 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3548 | ||
3549 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3550 | if (pos) | |
3551 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3552 | ||
3553 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3554 | if (pos) { | |
3555 | int features; | |
3556 | ||
3557 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3558 | max_pasids = min(max_pasids, (1 << 20)); | |
3559 | ||
3560 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3561 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3562 | ||
3563 | features = pci_pasid_features(pdev); | |
3564 | if (features & PCI_PASID_CAP_EXEC) | |
3565 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3566 | if (features & PCI_PASID_CAP_PRIV) | |
3567 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3568 | } | |
3569 | ||
3570 | return 0; | |
3571 | } | |
3572 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3573 | |
3574 | #ifdef CONFIG_IRQ_REMAP | |
3575 | ||
3576 | /***************************************************************************** | |
3577 | * | |
3578 | * Interrupt Remapping Implementation | |
3579 | * | |
3580 | *****************************************************************************/ | |
3581 | ||
7c71d306 JL |
3582 | static struct irq_chip amd_ir_chip; |
3583 | ||
2b324506 JR |
3584 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) |
3585 | { | |
3586 | u64 dte; | |
3587 | ||
3588 | dte = amd_iommu_dev_table[devid].data[2]; | |
3589 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
2543a786 | 3590 | dte |= iommu_virt_to_phys(table->table); |
2b324506 JR |
3591 | dte |= DTE_IRQ_REMAP_INTCTL; |
3592 | dte |= DTE_IRQ_TABLE_LEN; | |
3593 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3594 | ||
3595 | amd_iommu_dev_table[devid].data[2] = dte; | |
3596 | } | |
3597 | ||
2b324506 JR |
3598 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) |
3599 | { | |
3600 | struct irq_remap_table *table = NULL; | |
3601 | struct amd_iommu *iommu; | |
3602 | unsigned long flags; | |
3603 | u16 alias; | |
3604 | ||
3605 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3606 | ||
3607 | iommu = amd_iommu_rlookup_table[devid]; | |
3608 | if (!iommu) | |
3609 | goto out_unlock; | |
3610 | ||
3611 | table = irq_lookup_table[devid]; | |
3612 | if (table) | |
09284b9c | 3613 | goto out_unlock; |
2b324506 JR |
3614 | |
3615 | alias = amd_iommu_alias_table[devid]; | |
3616 | table = irq_lookup_table[alias]; | |
3617 | if (table) { | |
3618 | irq_lookup_table[devid] = table; | |
3619 | set_dte_irq_entry(devid, table); | |
3620 | iommu_flush_dte(iommu, devid); | |
3621 | goto out; | |
3622 | } | |
3623 | ||
3624 | /* Nothing there yet, allocate new irq remapping table */ | |
3625 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3626 | if (!table) | |
09284b9c | 3627 | goto out_unlock; |
2b324506 | 3628 | |
197887f0 JR |
3629 | /* Initialize table spin-lock */ |
3630 | spin_lock_init(&table->lock); | |
3631 | ||
2b324506 JR |
3632 | if (ioapic) |
3633 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3634 | table->min_index = 32; | |
3635 | ||
3636 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3637 | if (!table->table) { | |
3638 | kfree(table); | |
821f0f68 | 3639 | table = NULL; |
09284b9c | 3640 | goto out_unlock; |
2b324506 JR |
3641 | } |
3642 | ||
77bdab46 SS |
3643 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
3644 | memset(table->table, 0, | |
3645 | MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3646 | else | |
3647 | memset(table->table, 0, | |
3648 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); | |
2b324506 JR |
3649 | |
3650 | if (ioapic) { | |
3651 | int i; | |
3652 | ||
3653 | for (i = 0; i < 32; ++i) | |
77bdab46 | 3654 | iommu->irte_ops->set_allocated(table, i); |
2b324506 JR |
3655 | } |
3656 | ||
3657 | irq_lookup_table[devid] = table; | |
3658 | set_dte_irq_entry(devid, table); | |
3659 | iommu_flush_dte(iommu, devid); | |
3660 | if (devid != alias) { | |
3661 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3662 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3663 | iommu_flush_dte(iommu, alias); |
3664 | } | |
3665 | ||
3666 | out: | |
3667 | iommu_completion_wait(iommu); | |
3668 | ||
3669 | out_unlock: | |
3670 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3671 | ||
3672 | return table; | |
3673 | } | |
3674 | ||
37946d95 | 3675 | static int alloc_irq_index(u16 devid, int count, bool align) |
2b324506 JR |
3676 | { |
3677 | struct irq_remap_table *table; | |
37946d95 | 3678 | int index, c, alignment = 1; |
2b324506 | 3679 | unsigned long flags; |
77bdab46 SS |
3680 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3681 | ||
3682 | if (!iommu) | |
3683 | return -ENODEV; | |
2b324506 JR |
3684 | |
3685 | table = get_irq_table(devid, false); | |
3686 | if (!table) | |
3687 | return -ENODEV; | |
3688 | ||
37946d95 JR |
3689 | if (align) |
3690 | alignment = roundup_pow_of_two(count); | |
3691 | ||
2b324506 JR |
3692 | spin_lock_irqsave(&table->lock, flags); |
3693 | ||
3694 | /* Scan table for free entries */ | |
37946d95 | 3695 | for (index = ALIGN(table->min_index, alignment), c = 0; |
07d1c91b | 3696 | index < MAX_IRQS_PER_TABLE;) { |
37946d95 | 3697 | if (!iommu->irte_ops->is_allocated(table, index)) { |
2b324506 | 3698 | c += 1; |
37946d95 JR |
3699 | } else { |
3700 | c = 0; | |
07d1c91b | 3701 | index = ALIGN(index + 1, alignment); |
37946d95 JR |
3702 | continue; |
3703 | } | |
2b324506 JR |
3704 | |
3705 | if (c == count) { | |
2b324506 | 3706 | for (; c != 0; --c) |
77bdab46 | 3707 | iommu->irte_ops->set_allocated(table, index - c + 1); |
2b324506 JR |
3708 | |
3709 | index -= count - 1; | |
2b324506 JR |
3710 | goto out; |
3711 | } | |
07d1c91b AW |
3712 | |
3713 | index++; | |
2b324506 JR |
3714 | } |
3715 | ||
3716 | index = -ENOSPC; | |
3717 | ||
3718 | out: | |
3719 | spin_unlock_irqrestore(&table->lock, flags); | |
3720 | ||
3721 | return index; | |
3722 | } | |
3723 | ||
b9fc6b56 SS |
3724 | static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, |
3725 | struct amd_ir_data *data) | |
2b324506 JR |
3726 | { |
3727 | struct irq_remap_table *table; | |
3728 | struct amd_iommu *iommu; | |
3729 | unsigned long flags; | |
880ac60e | 3730 | struct irte_ga *entry; |
2b324506 JR |
3731 | |
3732 | iommu = amd_iommu_rlookup_table[devid]; | |
3733 | if (iommu == NULL) | |
3734 | return -EINVAL; | |
3735 | ||
3736 | table = get_irq_table(devid, false); | |
3737 | if (!table) | |
3738 | return -ENOMEM; | |
3739 | ||
3740 | spin_lock_irqsave(&table->lock, flags); | |
880ac60e SS |
3741 | |
3742 | entry = (struct irte_ga *)table->table; | |
3743 | entry = &entry[index]; | |
3744 | entry->lo.fields_remap.valid = 0; | |
3745 | entry->hi.val = irte->hi.val; | |
3746 | entry->lo.val = irte->lo.val; | |
3747 | entry->lo.fields_remap.valid = 1; | |
b9fc6b56 SS |
3748 | if (data) |
3749 | data->ref = entry; | |
880ac60e SS |
3750 | |
3751 | spin_unlock_irqrestore(&table->lock, flags); | |
3752 | ||
3753 | iommu_flush_irt(iommu, devid); | |
3754 | iommu_completion_wait(iommu); | |
3755 | ||
3756 | return 0; | |
3757 | } | |
3758 | ||
3759 | static int modify_irte(u16 devid, int index, union irte *irte) | |
2b324506 JR |
3760 | { |
3761 | struct irq_remap_table *table; | |
3762 | struct amd_iommu *iommu; | |
3763 | unsigned long flags; | |
3764 | ||
3765 | iommu = amd_iommu_rlookup_table[devid]; | |
3766 | if (iommu == NULL) | |
3767 | return -EINVAL; | |
3768 | ||
3769 | table = get_irq_table(devid, false); | |
3770 | if (!table) | |
3771 | return -ENOMEM; | |
3772 | ||
3773 | spin_lock_irqsave(&table->lock, flags); | |
880ac60e | 3774 | table->table[index] = irte->val; |
2b324506 JR |
3775 | spin_unlock_irqrestore(&table->lock, flags); |
3776 | ||
3777 | iommu_flush_irt(iommu, devid); | |
3778 | iommu_completion_wait(iommu); | |
3779 | ||
3780 | return 0; | |
3781 | } | |
3782 | ||
3783 | static void free_irte(u16 devid, int index) | |
3784 | { | |
3785 | struct irq_remap_table *table; | |
3786 | struct amd_iommu *iommu; | |
3787 | unsigned long flags; | |
3788 | ||
3789 | iommu = amd_iommu_rlookup_table[devid]; | |
3790 | if (iommu == NULL) | |
3791 | return; | |
3792 | ||
3793 | table = get_irq_table(devid, false); | |
3794 | if (!table) | |
3795 | return; | |
3796 | ||
3797 | spin_lock_irqsave(&table->lock, flags); | |
77bdab46 | 3798 | iommu->irte_ops->clear_allocated(table, index); |
2b324506 JR |
3799 | spin_unlock_irqrestore(&table->lock, flags); |
3800 | ||
3801 | iommu_flush_irt(iommu, devid); | |
3802 | iommu_completion_wait(iommu); | |
3803 | } | |
3804 | ||
880ac60e SS |
3805 | static void irte_prepare(void *entry, |
3806 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3807 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3808 | { |
3809 | union irte *irte = (union irte *) entry; | |
3810 | ||
3811 | irte->val = 0; | |
3812 | irte->fields.vector = vector; | |
3813 | irte->fields.int_type = delivery_mode; | |
3814 | irte->fields.destination = dest_apicid; | |
3815 | irte->fields.dm = dest_mode; | |
3816 | irte->fields.valid = 1; | |
3817 | } | |
3818 | ||
3819 | static void irte_ga_prepare(void *entry, | |
3820 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3821 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3822 | { |
3823 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3824 | ||
3825 | irte->lo.val = 0; | |
3826 | irte->hi.val = 0; | |
880ac60e SS |
3827 | irte->lo.fields_remap.int_type = delivery_mode; |
3828 | irte->lo.fields_remap.dm = dest_mode; | |
3829 | irte->hi.fields.vector = vector; | |
3830 | irte->lo.fields_remap.destination = dest_apicid; | |
3831 | irte->lo.fields_remap.valid = 1; | |
3832 | } | |
3833 | ||
3834 | static void irte_activate(void *entry, u16 devid, u16 index) | |
3835 | { | |
3836 | union irte *irte = (union irte *) entry; | |
3837 | ||
3838 | irte->fields.valid = 1; | |
3839 | modify_irte(devid, index, irte); | |
3840 | } | |
3841 | ||
3842 | static void irte_ga_activate(void *entry, u16 devid, u16 index) | |
3843 | { | |
3844 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3845 | ||
3846 | irte->lo.fields_remap.valid = 1; | |
b9fc6b56 | 3847 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3848 | } |
3849 | ||
3850 | static void irte_deactivate(void *entry, u16 devid, u16 index) | |
3851 | { | |
3852 | union irte *irte = (union irte *) entry; | |
3853 | ||
3854 | irte->fields.valid = 0; | |
3855 | modify_irte(devid, index, irte); | |
3856 | } | |
3857 | ||
3858 | static void irte_ga_deactivate(void *entry, u16 devid, u16 index) | |
3859 | { | |
3860 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3861 | ||
3862 | irte->lo.fields_remap.valid = 0; | |
b9fc6b56 | 3863 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3864 | } |
3865 | ||
3866 | static void irte_set_affinity(void *entry, u16 devid, u16 index, | |
3867 | u8 vector, u32 dest_apicid) | |
3868 | { | |
3869 | union irte *irte = (union irte *) entry; | |
3870 | ||
3871 | irte->fields.vector = vector; | |
3872 | irte->fields.destination = dest_apicid; | |
3873 | modify_irte(devid, index, irte); | |
3874 | } | |
3875 | ||
3876 | static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, | |
3877 | u8 vector, u32 dest_apicid) | |
3878 | { | |
3879 | struct irte_ga *irte = (struct irte_ga *) entry; | |
d98de49a | 3880 | struct iommu_dev_data *dev_data = search_dev_data(devid); |
880ac60e | 3881 | |
84a21dbd SS |
3882 | if (!dev_data || !dev_data->use_vapic || |
3883 | !irte->lo.fields_remap.guest_mode) { | |
d98de49a SS |
3884 | irte->hi.fields.vector = vector; |
3885 | irte->lo.fields_remap.destination = dest_apicid; | |
d98de49a SS |
3886 | modify_irte_ga(devid, index, irte, NULL); |
3887 | } | |
880ac60e SS |
3888 | } |
3889 | ||
77bdab46 | 3890 | #define IRTE_ALLOCATED (~1U) |
880ac60e SS |
3891 | static void irte_set_allocated(struct irq_remap_table *table, int index) |
3892 | { | |
3893 | table->table[index] = IRTE_ALLOCATED; | |
3894 | } | |
3895 | ||
3896 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) | |
3897 | { | |
3898 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3899 | struct irte_ga *irte = &ptr[index]; | |
3900 | ||
3901 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3902 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3903 | irte->hi.fields.vector = 0xff; | |
3904 | } | |
3905 | ||
3906 | static bool irte_is_allocated(struct irq_remap_table *table, int index) | |
3907 | { | |
3908 | union irte *ptr = (union irte *)table->table; | |
3909 | union irte *irte = &ptr[index]; | |
3910 | ||
3911 | return irte->val != 0; | |
3912 | } | |
3913 | ||
3914 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) | |
3915 | { | |
3916 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3917 | struct irte_ga *irte = &ptr[index]; | |
3918 | ||
3919 | return irte->hi.fields.vector != 0; | |
3920 | } | |
3921 | ||
3922 | static void irte_clear_allocated(struct irq_remap_table *table, int index) | |
3923 | { | |
3924 | table->table[index] = 0; | |
3925 | } | |
3926 | ||
3927 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) | |
3928 | { | |
3929 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3930 | struct irte_ga *irte = &ptr[index]; | |
3931 | ||
3932 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3933 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3934 | } | |
3935 | ||
7c71d306 | 3936 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3937 | { |
7c71d306 | 3938 | int devid = -1; |
5527de74 | 3939 | |
7c71d306 JL |
3940 | switch (info->type) { |
3941 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3942 | devid = get_ioapic_devid(info->ioapic_id); | |
3943 | break; | |
3944 | case X86_IRQ_ALLOC_TYPE_HPET: | |
3945 | devid = get_hpet_devid(info->hpet_id); | |
3946 | break; | |
3947 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3948 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3949 | devid = get_device_id(&info->msi_dev->dev); | |
3950 | break; | |
3951 | default: | |
3952 | BUG_ON(1); | |
3953 | break; | |
3954 | } | |
5527de74 | 3955 | |
7c71d306 JL |
3956 | return devid; |
3957 | } | |
5527de74 | 3958 | |
7c71d306 JL |
3959 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
3960 | { | |
3961 | struct amd_iommu *iommu; | |
3962 | int devid; | |
5527de74 | 3963 | |
7c71d306 JL |
3964 | if (!info) |
3965 | return NULL; | |
5527de74 | 3966 | |
7c71d306 JL |
3967 | devid = get_devid(info); |
3968 | if (devid >= 0) { | |
3969 | iommu = amd_iommu_rlookup_table[devid]; | |
3970 | if (iommu) | |
3971 | return iommu->ir_domain; | |
3972 | } | |
5527de74 | 3973 | |
7c71d306 | 3974 | return NULL; |
5527de74 JR |
3975 | } |
3976 | ||
7c71d306 | 3977 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 3978 | { |
7c71d306 JL |
3979 | struct amd_iommu *iommu; |
3980 | int devid; | |
5527de74 | 3981 | |
7c71d306 JL |
3982 | if (!info) |
3983 | return NULL; | |
5527de74 | 3984 | |
7c71d306 JL |
3985 | switch (info->type) { |
3986 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3987 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3988 | devid = get_device_id(&info->msi_dev->dev); | |
9ee35e4c | 3989 | if (devid < 0) |
7aba6cb9 WZ |
3990 | return NULL; |
3991 | ||
1fb260bc DC |
3992 | iommu = amd_iommu_rlookup_table[devid]; |
3993 | if (iommu) | |
3994 | return iommu->msi_domain; | |
7c71d306 JL |
3995 | break; |
3996 | default: | |
3997 | break; | |
3998 | } | |
5527de74 | 3999 | |
7c71d306 JL |
4000 | return NULL; |
4001 | } | |
5527de74 | 4002 | |
6b474b82 | 4003 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4004 | .prepare = amd_iommu_prepare, |
4005 | .enable = amd_iommu_enable, | |
4006 | .disable = amd_iommu_disable, | |
4007 | .reenable = amd_iommu_reenable, | |
4008 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
4009 | .get_ir_irq_domain = get_ir_irq_domain, |
4010 | .get_irq_domain = get_irq_domain, | |
4011 | }; | |
5527de74 | 4012 | |
7c71d306 JL |
4013 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
4014 | struct irq_cfg *irq_cfg, | |
4015 | struct irq_alloc_info *info, | |
4016 | int devid, int index, int sub_handle) | |
4017 | { | |
4018 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4019 | struct msi_msg *msg = &data->msi_entry; | |
7c71d306 | 4020 | struct IO_APIC_route_entry *entry; |
77bdab46 SS |
4021 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
4022 | ||
4023 | if (!iommu) | |
4024 | return; | |
5527de74 | 4025 | |
7c71d306 JL |
4026 | data->irq_2_irte.devid = devid; |
4027 | data->irq_2_irte.index = index + sub_handle; | |
77bdab46 SS |
4028 | iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, |
4029 | apic->irq_dest_mode, irq_cfg->vector, | |
d98de49a | 4030 | irq_cfg->dest_apicid, devid); |
7c71d306 JL |
4031 | |
4032 | switch (info->type) { | |
4033 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4034 | /* Setup IOAPIC entry */ | |
4035 | entry = info->ioapic_entry; | |
4036 | info->ioapic_entry = NULL; | |
4037 | memset(entry, 0, sizeof(*entry)); | |
4038 | entry->vector = index; | |
4039 | entry->mask = 0; | |
4040 | entry->trigger = info->ioapic_trigger; | |
4041 | entry->polarity = info->ioapic_polarity; | |
4042 | /* Mask level triggered irqs. */ | |
4043 | if (info->ioapic_trigger) | |
4044 | entry->mask = 1; | |
4045 | break; | |
5527de74 | 4046 | |
7c71d306 JL |
4047 | case X86_IRQ_ALLOC_TYPE_HPET: |
4048 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4049 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4050 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4051 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4052 | msg->data = irte_info->index; | |
4053 | break; | |
5527de74 | 4054 | |
7c71d306 JL |
4055 | default: |
4056 | BUG_ON(1); | |
4057 | break; | |
4058 | } | |
5527de74 JR |
4059 | } |
4060 | ||
880ac60e SS |
4061 | struct amd_irte_ops irte_32_ops = { |
4062 | .prepare = irte_prepare, | |
4063 | .activate = irte_activate, | |
4064 | .deactivate = irte_deactivate, | |
4065 | .set_affinity = irte_set_affinity, | |
4066 | .set_allocated = irte_set_allocated, | |
4067 | .is_allocated = irte_is_allocated, | |
4068 | .clear_allocated = irte_clear_allocated, | |
4069 | }; | |
4070 | ||
4071 | struct amd_irte_ops irte_128_ops = { | |
4072 | .prepare = irte_ga_prepare, | |
4073 | .activate = irte_ga_activate, | |
4074 | .deactivate = irte_ga_deactivate, | |
4075 | .set_affinity = irte_ga_set_affinity, | |
4076 | .set_allocated = irte_ga_set_allocated, | |
4077 | .is_allocated = irte_ga_is_allocated, | |
4078 | .clear_allocated = irte_ga_clear_allocated, | |
4079 | }; | |
4080 | ||
7c71d306 JL |
4081 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4082 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4083 | { |
7c71d306 JL |
4084 | struct irq_alloc_info *info = arg; |
4085 | struct irq_data *irq_data; | |
77bdab46 | 4086 | struct amd_ir_data *data = NULL; |
5527de74 | 4087 | struct irq_cfg *cfg; |
7c71d306 JL |
4088 | int i, ret, devid; |
4089 | int index = -1; | |
5527de74 | 4090 | |
7c71d306 JL |
4091 | if (!info) |
4092 | return -EINVAL; | |
4093 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4094 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4095 | return -EINVAL; |
4096 | ||
7c71d306 JL |
4097 | /* |
4098 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4099 | * to support multiple MSI interrupts. | |
4100 | */ | |
4101 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4102 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4103 | |
7c71d306 JL |
4104 | devid = get_devid(info); |
4105 | if (devid < 0) | |
4106 | return -EINVAL; | |
5527de74 | 4107 | |
7c71d306 JL |
4108 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4109 | if (ret < 0) | |
4110 | return ret; | |
0b4d48cb | 4111 | |
7c71d306 JL |
4112 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
4113 | if (get_irq_table(devid, true)) | |
4114 | index = info->ioapic_pin; | |
4115 | else | |
4116 | ret = -ENOMEM; | |
4117 | } else { | |
53b9ec3f JR |
4118 | bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI); |
4119 | ||
4120 | index = alloc_irq_index(devid, nr_irqs, align); | |
7c71d306 JL |
4121 | } |
4122 | if (index < 0) { | |
4123 | pr_warn("Failed to allocate IRTE\n"); | |
517abe49 | 4124 | ret = index; |
7c71d306 JL |
4125 | goto out_free_parent; |
4126 | } | |
0b4d48cb | 4127 | |
7c71d306 JL |
4128 | for (i = 0; i < nr_irqs; i++) { |
4129 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4130 | cfg = irqd_cfg(irq_data); | |
4131 | if (!irq_data || !cfg) { | |
4132 | ret = -EINVAL; | |
4133 | goto out_free_data; | |
4134 | } | |
0b4d48cb | 4135 | |
a130e69f JR |
4136 | ret = -ENOMEM; |
4137 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4138 | if (!data) | |
4139 | goto out_free_data; | |
4140 | ||
77bdab46 SS |
4141 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
4142 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); | |
4143 | else | |
4144 | data->entry = kzalloc(sizeof(struct irte_ga), | |
4145 | GFP_KERNEL); | |
4146 | if (!data->entry) { | |
4147 | kfree(data); | |
4148 | goto out_free_data; | |
4149 | } | |
4150 | ||
7c71d306 JL |
4151 | irq_data->hwirq = (devid << 16) + i; |
4152 | irq_data->chip_data = data; | |
4153 | irq_data->chip = &amd_ir_chip; | |
4154 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4155 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4156 | } | |
a130e69f | 4157 | |
7c71d306 | 4158 | return 0; |
0b4d48cb | 4159 | |
7c71d306 JL |
4160 | out_free_data: |
4161 | for (i--; i >= 0; i--) { | |
4162 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4163 | if (irq_data) | |
4164 | kfree(irq_data->chip_data); | |
4165 | } | |
4166 | for (i = 0; i < nr_irqs; i++) | |
4167 | free_irte(devid, index + i); | |
4168 | out_free_parent: | |
4169 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4170 | return ret; | |
0b4d48cb JR |
4171 | } |
4172 | ||
7c71d306 JL |
4173 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4174 | unsigned int nr_irqs) | |
0b4d48cb | 4175 | { |
7c71d306 JL |
4176 | struct irq_2_irte *irte_info; |
4177 | struct irq_data *irq_data; | |
4178 | struct amd_ir_data *data; | |
4179 | int i; | |
0b4d48cb | 4180 | |
7c71d306 JL |
4181 | for (i = 0; i < nr_irqs; i++) { |
4182 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4183 | if (irq_data && irq_data->chip_data) { | |
4184 | data = irq_data->chip_data; | |
4185 | irte_info = &data->irq_2_irte; | |
4186 | free_irte(irte_info->devid, irte_info->index); | |
77bdab46 | 4187 | kfree(data->entry); |
7c71d306 JL |
4188 | kfree(data); |
4189 | } | |
4190 | } | |
4191 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4192 | } | |
0b4d48cb | 4193 | |
5ba204a1 TG |
4194 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, |
4195 | struct amd_ir_data *ir_data, | |
4196 | struct irq_2_irte *irte_info, | |
4197 | struct irq_cfg *cfg); | |
4198 | ||
72491643 | 4199 | static int irq_remapping_activate(struct irq_domain *domain, |
702cb0a0 | 4200 | struct irq_data *irq_data, bool reserve) |
7c71d306 JL |
4201 | { |
4202 | struct amd_ir_data *data = irq_data->chip_data; | |
4203 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4204 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
5ba204a1 | 4205 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
0b4d48cb | 4206 | |
5ba204a1 TG |
4207 | if (!iommu) |
4208 | return 0; | |
4209 | ||
4210 | iommu->irte_ops->activate(data->entry, irte_info->devid, | |
4211 | irte_info->index); | |
4212 | amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg); | |
72491643 | 4213 | return 0; |
0b4d48cb JR |
4214 | } |
4215 | ||
7c71d306 JL |
4216 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4217 | struct irq_data *irq_data) | |
0b4d48cb | 4218 | { |
7c71d306 JL |
4219 | struct amd_ir_data *data = irq_data->chip_data; |
4220 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4221 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
0b4d48cb | 4222 | |
77bdab46 SS |
4223 | if (iommu) |
4224 | iommu->irte_ops->deactivate(data->entry, irte_info->devid, | |
4225 | irte_info->index); | |
7c71d306 | 4226 | } |
0b4d48cb | 4227 | |
e2f9d45f | 4228 | static const struct irq_domain_ops amd_ir_domain_ops = { |
7c71d306 JL |
4229 | .alloc = irq_remapping_alloc, |
4230 | .free = irq_remapping_free, | |
4231 | .activate = irq_remapping_activate, | |
4232 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4233 | }; |
0b4d48cb | 4234 | |
b9fc6b56 SS |
4235 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) |
4236 | { | |
4237 | struct amd_iommu *iommu; | |
4238 | struct amd_iommu_pi_data *pi_data = vcpu_info; | |
4239 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; | |
4240 | struct amd_ir_data *ir_data = data->chip_data; | |
4241 | struct irte_ga *irte = (struct irte_ga *) ir_data->entry; | |
4242 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
d98de49a SS |
4243 | struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); |
4244 | ||
4245 | /* Note: | |
4246 | * This device has never been set up for guest mode. | |
4247 | * we should not modify the IRTE | |
4248 | */ | |
4249 | if (!dev_data || !dev_data->use_vapic) | |
4250 | return 0; | |
b9fc6b56 SS |
4251 | |
4252 | pi_data->ir_data = ir_data; | |
4253 | ||
4254 | /* Note: | |
4255 | * SVM tries to set up for VAPIC mode, but we are in | |
4256 | * legacy mode. So, we force legacy mode instead. | |
4257 | */ | |
4258 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
4259 | pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n", | |
4260 | __func__); | |
4261 | pi_data->is_guest_mode = false; | |
4262 | } | |
4263 | ||
4264 | iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4265 | if (iommu == NULL) | |
4266 | return -EINVAL; | |
4267 | ||
4268 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; | |
4269 | if (pi_data->is_guest_mode) { | |
4270 | /* Setting */ | |
4271 | irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); | |
4272 | irte->hi.fields.vector = vcpu_pi_info->vector; | |
efe6f241 | 4273 | irte->lo.fields_vapic.ga_log_intr = 1; |
b9fc6b56 SS |
4274 | irte->lo.fields_vapic.guest_mode = 1; |
4275 | irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; | |
4276 | ||
4277 | ir_data->cached_ga_tag = pi_data->ga_tag; | |
4278 | } else { | |
4279 | /* Un-Setting */ | |
4280 | struct irq_cfg *cfg = irqd_cfg(data); | |
4281 | ||
4282 | irte->hi.val = 0; | |
4283 | irte->lo.val = 0; | |
4284 | irte->hi.fields.vector = cfg->vector; | |
4285 | irte->lo.fields_remap.guest_mode = 0; | |
4286 | irte->lo.fields_remap.destination = cfg->dest_apicid; | |
4287 | irte->lo.fields_remap.int_type = apic->irq_delivery_mode; | |
4288 | irte->lo.fields_remap.dm = apic->irq_dest_mode; | |
4289 | ||
4290 | /* | |
4291 | * This communicates the ga_tag back to the caller | |
4292 | * so that it can do all the necessary clean up. | |
4293 | */ | |
4294 | ir_data->cached_ga_tag = 0; | |
4295 | } | |
4296 | ||
4297 | return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); | |
4298 | } | |
4299 | ||
5ba204a1 TG |
4300 | |
4301 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, | |
4302 | struct amd_ir_data *ir_data, | |
4303 | struct irq_2_irte *irte_info, | |
4304 | struct irq_cfg *cfg) | |
4305 | { | |
4306 | ||
4307 | /* | |
4308 | * Atomically updates the IRTE with the new destination, vector | |
4309 | * and flushes the interrupt entry cache. | |
4310 | */ | |
4311 | iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid, | |
4312 | irte_info->index, cfg->vector, | |
4313 | cfg->dest_apicid); | |
4314 | } | |
4315 | ||
7c71d306 JL |
4316 | static int amd_ir_set_affinity(struct irq_data *data, |
4317 | const struct cpumask *mask, bool force) | |
4318 | { | |
4319 | struct amd_ir_data *ir_data = data->chip_data; | |
4320 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4321 | struct irq_cfg *cfg = irqd_cfg(data); | |
4322 | struct irq_data *parent = data->parent_data; | |
77bdab46 | 4323 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
7c71d306 | 4324 | int ret; |
0b4d48cb | 4325 | |
77bdab46 SS |
4326 | if (!iommu) |
4327 | return -ENODEV; | |
4328 | ||
7c71d306 JL |
4329 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4330 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4331 | return ret; | |
0b4d48cb | 4332 | |
5ba204a1 | 4333 | amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg); |
7c71d306 JL |
4334 | /* |
4335 | * After this point, all the interrupts will start arriving | |
4336 | * at the new destination. So, time to cleanup the previous | |
4337 | * vector allocation. | |
4338 | */ | |
c6c2002b | 4339 | send_cleanup_vector(cfg); |
7c71d306 JL |
4340 | |
4341 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4342 | } |
4343 | ||
7c71d306 | 4344 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4345 | { |
7c71d306 | 4346 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4347 | |
7c71d306 JL |
4348 | *msg = ir_data->msi_entry; |
4349 | } | |
d976195c | 4350 | |
7c71d306 | 4351 | static struct irq_chip amd_ir_chip = { |
290be194 TG |
4352 | .name = "AMD-IR", |
4353 | .irq_ack = ir_ack_apic_edge, | |
4354 | .irq_set_affinity = amd_ir_set_affinity, | |
4355 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, | |
4356 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
7c71d306 | 4357 | }; |
d976195c | 4358 | |
7c71d306 JL |
4359 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4360 | { | |
3e49a818 TG |
4361 | struct fwnode_handle *fn; |
4362 | ||
4363 | fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); | |
4364 | if (!fn) | |
4365 | return -ENOMEM; | |
4366 | iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu); | |
4367 | irq_domain_free_fwnode(fn); | |
7c71d306 JL |
4368 | if (!iommu->ir_domain) |
4369 | return -ENOMEM; | |
d976195c | 4370 | |
7c71d306 | 4371 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
3e49a818 TG |
4372 | iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain, |
4373 | "AMD-IR-MSI", | |
4374 | iommu->index); | |
d976195c JR |
4375 | return 0; |
4376 | } | |
8dbea3fd SS |
4377 | |
4378 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) | |
4379 | { | |
4380 | unsigned long flags; | |
4381 | struct amd_iommu *iommu; | |
4382 | struct irq_remap_table *irt; | |
4383 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; | |
4384 | int devid = ir_data->irq_2_irte.devid; | |
4385 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
4386 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; | |
4387 | ||
4388 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
4389 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) | |
4390 | return 0; | |
4391 | ||
4392 | iommu = amd_iommu_rlookup_table[devid]; | |
4393 | if (!iommu) | |
4394 | return -ENODEV; | |
4395 | ||
4396 | irt = get_irq_table(devid, false); | |
4397 | if (!irt) | |
4398 | return -ENODEV; | |
4399 | ||
4400 | spin_lock_irqsave(&irt->lock, flags); | |
4401 | ||
4402 | if (ref->lo.fields_vapic.guest_mode) { | |
4403 | if (cpu >= 0) | |
4404 | ref->lo.fields_vapic.destination = cpu; | |
4405 | ref->lo.fields_vapic.is_run = is_run; | |
4406 | barrier(); | |
4407 | } | |
4408 | ||
4409 | spin_unlock_irqrestore(&irt->lock, flags); | |
4410 | ||
4411 | iommu_flush_irt(iommu, devid); | |
4412 | iommu_completion_wait(iommu); | |
4413 | return 0; | |
4414 | } | |
4415 | EXPORT_SYMBOL(amd_iommu_update_ga); | |
2b324506 | 4416 | #endif |