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Merge tag 'kbuild-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy...
[linux-2.6-block.git] / drivers / iommu / amd_iommu.c
CommitLineData
b6c02715 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
63ce3ae8 3 * Author: Joerg Roedel <jroedel@suse.de>
b6c02715
JR		 4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
72e1dcc4 20#include <linux/ratelimit.h>
b6c02715 21#include <linux/pci.h>
2bf9a0a1 22#include <linux/acpi.h>
9a4d3bf5 23#include <linux/amba/bus.h>
0076cd3d 24#include <linux/platform_device.h>
cb41ed85 25#include <linux/pci-ats.h>
a66022c4 26#include <linux/bitmap.h>
5a0e3ad6 27#include <linux/slab.h>
7f26508b 28#include <linux/debugfs.h>
b6c02715 29#include <linux/scatterlist.h>
51491367 30#include <linux/dma-mapping.h>
fec777c3 31#include <linux/dma-direct.h>
b6c02715 32#include <linux/iommu-helper.h>
c156e347 33#include <linux/iommu.h>
815b33fd 34#include <linux/delay.h>
403f81d8 35#include <linux/amd-iommu.h>
72e1dcc4
JR		 36#include <linux/notifier.h>
37#include <linux/export.h>
2b324506
JR		 38#include <linux/irq.h>
39#include <linux/msi.h>
3b839a57 40#include <linux/dma-contiguous.h>
7c71d306 41#include <linux/irqdomain.h>
5f6bed50 42#include <linux/percpu.h>
307d5851 43#include <linux/iova.h>
2b324506
JR		 44#include <asm/irq_remapping.h>
45#include <asm/io_apic.h>
46#include <asm/apic.h>
47#include <asm/hw_irq.h>
17f5b569 48#include <asm/msidef.h>
b6c02715 49#include <asm/proto.h>
46a7fa27 50#include <asm/iommu.h>
1d9b16d1 51#include <asm/gart.h>
27c2127a 52#include <asm/dma.h>
403f81d8
JR		 53
54#include "amd_iommu_proto.h"
55#include "amd_iommu_types.h"
6b474b82 56#include "irq_remapping.h"
b6c02715 57
a869572c
CH		 58#define AMD_IOMMU_MAPPING_ERROR 0
59
b6c02715
JR		 60#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61
815b33fd 62#define LOOP_TIMEOUT 100000
136f78a1 63
307d5851
JR		 64/* IO virtual address start page frame number */
65#define IOVA_START_PFN (1)
66#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
307d5851 67
81cd07b9
JR		 68/* Reserved IOVA ranges */
69#define MSI_RANGE_START (0xfee00000)
70#define MSI_RANGE_END (0xfeefffff)
71#define HT_RANGE_START (0xfd00000000ULL)
72#define HT_RANGE_END (0xffffffffffULL)
73
aa3de9c0
OBC		 74/*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
954e3dd8 80 * 512GB Pages are not supported due to a hardware bug
aa3de9c0 81 */
954e3dd8 82#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
aa3de9c0 83
2cd1083d 84static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
2bc00180 85static DEFINE_SPINLOCK(pd_bitmap_lock);
b6c02715 86
8fa5f802 87/* List of all available dev_data structures */
779da732 88static LLIST_HEAD(dev_data_list);
8fa5f802 89
6efed63b
JR		 90LIST_HEAD(ioapic_map);
91LIST_HEAD(hpet_map);
2a0cb4e2 92LIST_HEAD(acpihid_map);
6efed63b 93
0feae533
JR		 94/*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
b0119e87 98const struct iommu_ops amd_iommu_ops;
26961efe 99
72e1dcc4 100static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
52815b75 101int amd_iommu_max_glx_val = -1;
72e1dcc4 102
5299709d 103static const struct dma_map_ops amd_iommu_dma_ops;
ac1534a5 104
431b2a20
JR		 105/*
106 * general struct to manage commands send to an IOMMU
107 */
d6449536 108struct iommu_cmd {
b6c02715
JR		 109 u32 data[4];
110};
111
05152a04
JR		 112struct kmem_cache *amd_iommu_irq_cache;
113
04bfdd84 114static void update_domain(struct protection_domain *domain);
7a5a566e 115static int protection_domain_init(struct protection_domain *domain);
b6809ee5 116static void detach_device(struct device *dev);
9003d618 117static void iova_domain_flush_tlb(struct iova_domain *iovad);
d4241a27 118
007b74ba
JR		 119/*
120 * Data container for a dma_ops specific protection domain
121 */
122struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
307d5851
JR		 126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
007b74ba
JR		 128};
129
81cd07b9
JR		 130static struct iova_domain reserved_iova_ranges;
131static struct lock_class_key reserved_rbtree_key;
132
15898bbc
JR		 133/****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
2bf9a0a1
WZ		 139static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
3f4b87b9 141{
2bf9a0a1
WZ		 142 const char *hid, *uid;
143
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
146
147 if (!hid || !(*hid))
148 return -ENODEV;
149
150 if (!uid || !(*uid))
151 return strcmp(hid, entry->hid);
152
153 if (!(*entry->uid))
154 return strcmp(hid, entry->hid);
155
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
3f4b87b9
JR		 157}
158
2bf9a0a1 159static inline u16 get_pci_device_id(struct device *dev)
e3156048
JR		 160{
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164}
165
2bf9a0a1
WZ		 166static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
168{
169 struct acpihid_map_entry *p;
170
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
173 if (entry)
174 *entry = p;
175 return p->devid;
176 }
177 }
178 return -EINVAL;
179}
180
181static inline int get_device_id(struct device *dev)
182{
183 int devid;
184
185 if (dev_is_pci(dev))
186 devid = get_pci_device_id(dev);
187 else
188 devid = get_acpihid_device_id(dev, NULL);
189
190 return devid;
191}
192
3f4b87b9
JR		 193static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194{
195 return container_of(dom, struct protection_domain, domain);
196}
197
b3311b06
JR		 198static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199{
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
202}
203
f62dda66 204static struct iommu_dev_data *alloc_dev_data(u16 devid)
8fa5f802
JR		 205{
206 struct iommu_dev_data *dev_data;
8fa5f802
JR		 207
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
209 if (!dev_data)
210 return NULL;
211
f62dda66 212 dev_data->devid = devid;
30bf2df6
JR		 213 ratelimit_default_init(&dev_data->rs);
214
779da732 215 llist_add(&dev_data->dev_data_list, &dev_data_list);
8fa5f802
JR		 216 return dev_data;
217}
218
3b03bb74
JR		 219static struct iommu_dev_data *search_dev_data(u16 devid)
220{
221 struct iommu_dev_data *dev_data;
779da732 222 struct llist_node *node;
3b03bb74 223
779da732
SAS		 224 if (llist_empty(&dev_data_list))
225 return NULL;
3b03bb74 226
779da732
SAS		 227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
3b03bb74 229 if (dev_data->devid == devid)
779da732 230 return dev_data;
3b03bb74
JR		 231 }
232
779da732 233 return NULL;
3b03bb74
JR		 234}
235
e3156048
JR		 236static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
237{
238 *(u16 *)data = alias;
239 return 0;
240}
241
242static u16 get_alias(struct device *dev)
243{
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
246
6c0b43df 247 /* The callers make sure that get_device_id() does not fail here */
e3156048 248 devid = get_device_id(dev);
5ebb1bc2
AN		 249
250 /* For ACPI HID devices, we simply return the devid as such */
251 if (!dev_is_pci(dev))
252 return devid;
253
e3156048 254 ivrs_alias = amd_iommu_alias_table[devid];
5ebb1bc2 255
e3156048
JR		 256 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
257
258 if (ivrs_alias == pci_alias)
259 return ivrs_alias;
260
261 /*
262 * DMA alias showdown
263 *
264 * The IVRS is fairly reliable in telling us about aliases, but it
265 * can't know about every screwy device. If we don't have an IVRS
266 * reported alias, use the PCI reported alias. In that case we may
267 * still need to initialize the rlookup and dev_table entries if the
268 * alias is to a non-existent device.
269 */
270 if (ivrs_alias == devid) {
271 if (!amd_iommu_rlookup_table[pci_alias]) {
272 amd_iommu_rlookup_table[pci_alias] =
273 amd_iommu_rlookup_table[devid];
274 memcpy(amd_iommu_dev_table[pci_alias].data,
275 amd_iommu_dev_table[devid].data,
276 sizeof(amd_iommu_dev_table[pci_alias].data));
277 }
278
279 return pci_alias;
280 }
281
282 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
283 "for device %s[%04x:%04x], kernel reported alias "
284 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
285 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
286 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
287 PCI_FUNC(pci_alias));
288
289 /*
290 * If we don't have a PCI DMA alias and the IVRS alias is on the same
291 * bus, then the IVRS table may know about a quirk that we don't.
292 */
293 if (pci_alias == devid &&
294 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
7afd16f8 295 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
e3156048
JR		 296 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
297 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
298 dev_name(dev));
299 }
300
301 return ivrs_alias;
302}
303
3b03bb74
JR		 304static struct iommu_dev_data *find_dev_data(u16 devid)
305{
306 struct iommu_dev_data *dev_data;
df3f7a6e 307 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3b03bb74
JR		 308
309 dev_data = search_dev_data(devid);
310
df3f7a6e 311 if (dev_data == NULL) {
3b03bb74 312 dev_data = alloc_dev_data(devid);
39ffe395
SAS		 313 if (!dev_data)
314 return NULL;
3b03bb74 315
df3f7a6e
BH		 316 if (translation_pre_enabled(iommu))
317 dev_data->defer_attach = true;
318 }
319
3b03bb74
JR		 320 return dev_data;
321}
322
daae2d25 323struct iommu_dev_data *get_dev_data(struct device *dev)
657cbb6b
JR		 324{
325 return dev->archdata.iommu;
326}
daae2d25 327EXPORT_SYMBOL(get_dev_data);
657cbb6b 328
b097d11a
WZ		 329/*
330* Find or create an IOMMU group for a acpihid device.
331*/
332static struct iommu_group *acpihid_device_group(struct device *dev)
657cbb6b 333{
b097d11a 334 struct acpihid_map_entry *p, *entry = NULL;
2d8e1f03 335 int devid;
b097d11a
WZ		 336
337 devid = get_acpihid_device_id(dev, &entry);
338 if (devid < 0)
339 return ERR_PTR(devid);
340
341 list_for_each_entry(p, &acpihid_map, list) {
342 if ((devid == p->devid) && p->group)
343 entry->group = p->group;
344 }
345
346 if (!entry->group)
347 entry->group = generic_device_group(dev);
f2f101f6
RM		 348 else
349 iommu_group_ref_get(entry->group);
b097d11a
WZ		 350
351 return entry->group;
657cbb6b
JR		 352}
353
5abcdba4
JR		 354static bool pci_iommuv2_capable(struct pci_dev *pdev)
355{
356 static const int caps[] = {
357 PCI_EXT_CAP_ID_ATS,
46277b75
JR		 358 PCI_EXT_CAP_ID_PRI,
359 PCI_EXT_CAP_ID_PASID,
5abcdba4
JR		 360 };
361 int i, pos;
362
cef74409
GK		 363 if (pci_ats_disabled())
364 return false;
365
5abcdba4
JR		 366 for (i = 0; i < 3; ++i) {
367 pos = pci_find_ext_capability(pdev, caps[i]);
368 if (pos == 0)
369 return false;
370 }
371
372 return true;
373}
374
6a113ddc
JR		 375static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
376{
377 struct iommu_dev_data *dev_data;
378
379 dev_data = get_dev_data(&pdev->dev);
380
381 return dev_data->errata & (1 << erratum) ? true : false;
382}
383
98fc5a69
JR		 384/*
385 * This function checks if the driver got a valid device from the caller to
386 * avoid dereferencing invalid pointers.
387 */
388static bool check_device(struct device *dev)
389{
7aba6cb9 390 int devid;
98fc5a69
JR		 391
392 if (!dev || !dev->dma_mask)
393 return false;
394
98fc5a69 395 devid = get_device_id(dev);
9ee35e4c 396 if (devid < 0)
7aba6cb9 397 return false;
98fc5a69
JR		 398
399 /* Out of our scope? */
400 if (devid > amd_iommu_last_bdf)
401 return false;
402
403 if (amd_iommu_rlookup_table[devid] == NULL)
404 return false;
405
406 return true;
407}
408
25b11ce2 409static void init_iommu_group(struct device *dev)
2851db21 410{
2851db21 411 struct iommu_group *group;
2851db21 412
65d5352f 413 group = iommu_group_get_for_dev(dev);
0bb6e243
JR		 414 if (IS_ERR(group))
415 return;
416
0bb6e243 417 iommu_group_put(group);
eb9c9527
AW		 418}
419
420static int iommu_init_device(struct device *dev)
421{
eb9c9527 422 struct iommu_dev_data *dev_data;
39ab9555 423 struct amd_iommu *iommu;
7aba6cb9 424 int devid;
eb9c9527
AW		 425
426 if (dev->archdata.iommu)
427 return 0;
428
7aba6cb9 429 devid = get_device_id(dev);
9ee35e4c 430 if (devid < 0)
7aba6cb9
WZ		 431 return devid;
432
39ab9555
JR		 433 iommu = amd_iommu_rlookup_table[devid];
434
7aba6cb9 435 dev_data = find_dev_data(devid);
eb9c9527
AW		 436 if (!dev_data)
437 return -ENOMEM;
438
e3156048
JR		 439 dev_data->alias = get_alias(dev);
440
2bf9a0a1 441 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
5abcdba4
JR		 442 struct amd_iommu *iommu;
443
2bf9a0a1 444 iommu = amd_iommu_rlookup_table[dev_data->devid];
5abcdba4
JR		 445 dev_data->iommu_v2 = iommu->is_iommu_v2;
446 }
447
657cbb6b
JR		 448 dev->archdata.iommu = dev_data;
449
e3d10af1 450 iommu_device_link(&iommu->iommu, dev);
066f2e98 451
657cbb6b
JR		 452 return 0;
453}
454
26018874
JR		 455static void iommu_ignore_device(struct device *dev)
456{
7aba6cb9
WZ		 457 u16 alias;
458 int devid;
26018874
JR		 459
460 devid = get_device_id(dev);
9ee35e4c 461 if (devid < 0)
7aba6cb9
WZ		 462 return;
463
e3156048 464 alias = get_alias(dev);
26018874
JR		 465
466 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
467 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
468
469 amd_iommu_rlookup_table[devid] = NULL;
470 amd_iommu_rlookup_table[alias] = NULL;
471}
472
657cbb6b
JR		 473static void iommu_uninit_device(struct device *dev)
474{
7aba6cb9 475 struct iommu_dev_data *dev_data;
39ab9555
JR		 476 struct amd_iommu *iommu;
477 int devid;
c1931090 478
7aba6cb9 479 devid = get_device_id(dev);
9ee35e4c 480 if (devid < 0)
7aba6cb9 481 return;
c1931090 482
39ab9555
JR		 483 iommu = amd_iommu_rlookup_table[devid];
484
7aba6cb9 485 dev_data = search_dev_data(devid);
c1931090
AW		 486 if (!dev_data)
487 return;
488
b6809ee5
JR		 489 if (dev_data->domain)
490 detach_device(dev);
491
e3d10af1 492 iommu_device_unlink(&iommu->iommu, dev);
066f2e98 493
9dcd6130
AW		 494 iommu_group_remove_device(dev);
495
aafd8ba0 496 /* Remove dma-ops */
5657933d 497 dev->dma_ops = NULL;
aafd8ba0 498
8fa5f802 499 /*
c1931090
AW		 500 * We keep dev_data around for unplugged devices and reuse it when the
501 * device is re-plugged - not doing so would introduce a ton of races.
8fa5f802 502 */
657cbb6b 503}
b7cc9554 504
a80dc3e0
JR		 505/****************************************************************************
506 *
507 * Interrupt handling functions
508 *
509 ****************************************************************************/
510
e3e59876
JR		 511static void dump_dte_entry(u16 devid)
512{
513 int i;
514
ee6c2868
JR		 515 for (i = 0; i < 4; ++i)
516 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
e3e59876
JR		 517 amd_iommu_dev_table[devid].data[i]);
518}
519
945b4ac4
JR		 520static void dump_command(unsigned long phys_addr)
521{
2543a786 522 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
945b4ac4
JR		 523 int i;
524
525 for (i = 0; i < 4; ++i)
526 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
527}
528
30bf2df6
JR		 529static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
530 u64 address, int flags)
531{
532 struct iommu_dev_data *dev_data = NULL;
533 struct pci_dev *pdev;
534
d5bf0f4f
SK		 535 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
536 devid & 0xff);
30bf2df6
JR		 537 if (pdev)
538 dev_data = get_dev_data(&pdev->dev);
539
540 if (dev_data && __ratelimit(&dev_data->rs)) {
541 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
542 domain_id, address, flags);
543 } else if (printk_ratelimit()) {
544 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
545 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
546 domain_id, address, flags);
547 }
548
549 if (pdev)
550 pci_dev_put(pdev);
551}
552
a345b23b 553static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
90008ee4 554{
90ca3859 555 struct device *dev = iommu->iommu.dev;
e7f63ffc 556 int type, devid, pasid, flags, tag;
3d06fca8
JR		 557 volatile u32 *event = __evt;
558 int count = 0;
559 u64 address;
560
561retry:
562 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
563 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
d64c0486 564 pasid = PPR_PASID(*(u64 *)&event[0]);
3d06fca8
JR		 565 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
566 address = (u64)(((u64)event[3]) << 32) | event[2];
567
568 if (type == 0) {
569 /* Did we hit the erratum? */
570 if (++count == LOOP_TIMEOUT) {
571 pr_err("AMD-Vi: No event written to event log\n");
572 return;
573 }
574 udelay(1);
575 goto retry;
576 }
90008ee4 577
30bf2df6 578 if (type == EVENT_TYPE_IO_FAULT) {
d64c0486 579 amd_iommu_report_page_fault(devid, pasid, address, flags);
30bf2df6
JR		 580 return;
581 } else {
90ca3859 582 dev_err(dev, "AMD-Vi: Event logged [");
30bf2df6 583 }
90008ee4
JR		 584
585 switch (type) {
586 case EVENT_TYPE_ILL_DEV:
d64c0486 587 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
90ca3859 588 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
d64c0486 589 pasid, address, flags);
e3e59876 590 dump_dte_entry(devid);
90008ee4 591 break;
90008ee4 592 case EVENT_TYPE_DEV_TAB_ERR:
90ca3859
GH		 593 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
594 "address=0x%016llx flags=0x%04x]\n",
595 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
596 address, flags);
90008ee4
JR		 597 break;
598 case EVENT_TYPE_PAGE_TAB_ERR:
d64c0486 599 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
90ca3859 600 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
d64c0486 601 pasid, address, flags);
90008ee4
JR		 602 break;
603 case EVENT_TYPE_ILL_CMD:
90ca3859 604 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
945b4ac4 605 dump_command(address);
90008ee4
JR		 606 break;
607 case EVENT_TYPE_CMD_HARD_ERR:
d64c0486
GH		 608 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
609 address, flags);
90008ee4
JR		 610 break;
611 case EVENT_TYPE_IOTLB_INV_TO:
d64c0486 612 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
90ca3859
GH		 613 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
614 address);
90008ee4
JR		 615 break;
616 case EVENT_TYPE_INV_DEV_REQ:
d64c0486 617 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
90ca3859 618 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
d64c0486 619 pasid, address, flags);
90008ee4 620 break;
e7f63ffc
GH		 621 case EVENT_TYPE_INV_PPR_REQ:
622 pasid = ((event[0] >> 16) & 0xFFFF)
623 | ((event[1] << 6) & 0xF0000);
624 tag = event[1] & 0x03FF;
625 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
626 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
627 pasid, address, flags);
90008ee4
JR		 628 break;
629 default:
d64c0486 630 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
90ca3859 631 event[0], event[1], event[2], event[3]);
90008ee4 632 }
3d06fca8
JR		 633
634 memset(__evt, 0, 4 * sizeof(u32));
90008ee4
JR		 635}
636
637static void iommu_poll_events(struct amd_iommu *iommu)
638{
639 u32 head, tail;
90008ee4
JR		 640
641 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
642 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
643
644 while (head != tail) {
a345b23b 645 iommu_print_event(iommu, iommu->evt_buf + head);
deba4bce 646 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
90008ee4
JR		 647 }
648
649 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
90008ee4
JR		 650}
651
eee53537 652static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
72e1dcc4
JR		 653{
654 struct amd_iommu_fault fault;
72e1dcc4 655
72e1dcc4
JR		 656 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
657 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
658 return;
659 }
660
661 fault.address = raw[1];
662 fault.pasid = PPR_PASID(raw[0]);
663 fault.device_id = PPR_DEVID(raw[0]);
664 fault.tag = PPR_TAG(raw[0]);
665 fault.flags = PPR_FLAGS(raw[0]);
666
72e1dcc4
JR		 667 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
668}
669
670static void iommu_poll_ppr_log(struct amd_iommu *iommu)
671{
72e1dcc4
JR		 672 u32 head, tail;
673
674 if (iommu->ppr_log == NULL)
675 return;
676
72e1dcc4
JR		 677 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
678 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
679
680 while (head != tail) {
eee53537
JR		 681 volatile u64 *raw;
682 u64 entry[2];
683 int i;
684
685 raw = (u64 *)(iommu->ppr_log + head);
686
687 /*
688 * Hardware bug: Interrupt may arrive before the entry is
689 * written to memory. If this happens we need to wait for the
690 * entry to arrive.
691 */
692 for (i = 0; i < LOOP_TIMEOUT; ++i) {
693 if (PPR_REQ_TYPE(raw[0]) != 0)
694 break;
695 udelay(1);
696 }
72e1dcc4 697
eee53537
JR		 698 /* Avoid memcpy function-call overhead */
699 entry[0] = raw[0];
700 entry[1] = raw[1];
72e1dcc4 701
eee53537
JR		 702 /*
703 * To detect the hardware bug we need to clear the entry
704 * back to zero.
705 */
706 raw[0] = raw[1] = 0UL;
707
708 /* Update head pointer of hardware ring-buffer */
72e1dcc4
JR		 709 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
710 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
eee53537 711
eee53537
JR		 712 /* Handle PPR entry */
713 iommu_handle_ppr_entry(iommu, entry);
714
eee53537
JR		 715 /* Refresh ring-buffer information */
716 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
72e1dcc4
JR		 717 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
718 }
72e1dcc4
JR		 719}
720
bd6fcefc
SS		 721#ifdef CONFIG_IRQ_REMAP
722static int (*iommu_ga_log_notifier)(u32);
723
724int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
725{
726 iommu_ga_log_notifier = notifier;
727
728 return 0;
729}
730EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
731
732static void iommu_poll_ga_log(struct amd_iommu *iommu)
733{
734 u32 head, tail, cnt = 0;
735
736 if (iommu->ga_log == NULL)
737 return;
738
739 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
740 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
741
742 while (head != tail) {
743 volatile u64 *raw;
744 u64 log_entry;
745
746 raw = (u64 *)(iommu->ga_log + head);
747 cnt++;
748
749 /* Avoid memcpy function-call overhead */
750 log_entry = *raw;
751
752 /* Update head pointer of hardware ring-buffer */
753 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
754 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
755
756 /* Handle GA entry */
757 switch (GA_REQ_TYPE(log_entry)) {
758 case GA_GUEST_NR:
759 if (!iommu_ga_log_notifier)
760 break;
761
762 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
763 __func__, GA_DEVID(log_entry),
764 GA_TAG(log_entry));
765
766 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
767 pr_err("AMD-Vi: GA log notifier failed.\n");
768 break;
769 default:
770 break;
771 }
772 }
773}
774#endif /* CONFIG_IRQ_REMAP */
775
776#define AMD_IOMMU_INT_MASK \
777 (MMIO_STATUS_EVT_INT_MASK | \
778 MMIO_STATUS_PPR_INT_MASK | \
779 MMIO_STATUS_GALOG_INT_MASK)
780
72fe00f0 781irqreturn_t amd_iommu_int_thread(int irq, void *data)
a80dc3e0 782{
3f398bc7
SS		 783 struct amd_iommu *iommu = (struct amd_iommu *) data;
784 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
90008ee4 785
bd6fcefc
SS		 786 while (status & AMD_IOMMU_INT_MASK) {
787 /* Enable EVT and PPR and GA interrupts again */
788 writel(AMD_IOMMU_INT_MASK,
3f398bc7 789 iommu->mmio_base + MMIO_STATUS_OFFSET);
90008ee4 790
3f398bc7
SS		 791 if (status & MMIO_STATUS_EVT_INT_MASK) {
792 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
793 iommu_poll_events(iommu);
794 }
90008ee4 795
3f398bc7
SS		 796 if (status & MMIO_STATUS_PPR_INT_MASK) {
797 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
798 iommu_poll_ppr_log(iommu);
799 }
90008ee4 800
bd6fcefc
SS		 801#ifdef CONFIG_IRQ_REMAP
802 if (status & MMIO_STATUS_GALOG_INT_MASK) {
803 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
804 iommu_poll_ga_log(iommu);
805 }
806#endif
807
3f398bc7
SS		 808 /*
809 * Hardware bug: ERBT1312
810 * When re-enabling interrupt (by writing 1
811 * to clear the bit), the hardware might also try to set
812 * the interrupt bit in the event status register.
813 * In this scenario, the bit will be set, and disable
814 * subsequent interrupts.
815 *
816 * Workaround: The IOMMU driver should read back the
817 * status register and check if the interrupt bits are cleared.
818 * If not, driver will need to go through the interrupt handler
819 * again and re-clear the bits
820 */
821 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
822 }
90008ee4 823 return IRQ_HANDLED;
a80dc3e0
JR		 824}
825
72fe00f0
JR		 826irqreturn_t amd_iommu_int_handler(int irq, void *data)
827{
828 return IRQ_WAKE_THREAD;
829}
830
431b2a20
JR		 831/****************************************************************************
832 *
833 * IOMMU command queuing functions
834 *
835 ****************************************************************************/
836
ac0ea6e9
JR		 837static int wait_on_sem(volatile u64 *sem)
838{
839 int i = 0;
840
841 while (*sem == 0 && i < LOOP_TIMEOUT) {
842 udelay(1);
843 i += 1;
844 }
845
846 if (i == LOOP_TIMEOUT) {
847 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
848 return -EIO;
849 }
850
851 return 0;
852}
853
854static void copy_cmd_to_buffer(struct amd_iommu *iommu,
d334a563 855 struct iommu_cmd *cmd)
a19ae1ec 856{
a19ae1ec
JR		 857 u8 *target;
858
d334a563
TL		 859 target = iommu->cmd_buf + iommu->cmd_buf_tail;
860
861 iommu->cmd_buf_tail += sizeof(*cmd);
862 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
ac0ea6e9
JR		 863
864 /* Copy command to buffer */
865 memcpy(target, cmd, sizeof(*cmd));
866
867 /* Tell the IOMMU about it */
d334a563 868 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
ac0ea6e9 869}
a19ae1ec 870
815b33fd 871static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
ded46737 872{
2543a786
TL		 873 u64 paddr = iommu_virt_to_phys((void *)address);
874
815b33fd
JR		 875 WARN_ON(address & 0x7ULL);
876
ded46737 877 memset(cmd, 0, sizeof(*cmd));
2543a786
TL		 878 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
879 cmd->data[1] = upper_32_bits(paddr);
815b33fd 880 cmd->data[2] = 1;
ded46737
JR		 881 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
882}
883
94fe79e2
JR		 884static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
885{
886 memset(cmd, 0, sizeof(*cmd));
887 cmd->data[0] = devid;
888 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
889}
890
11b6402c
JR		 891static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
892 size_t size, u16 domid, int pde)
893{
894 u64 pages;
ae0cbbb1 895 bool s;
11b6402c
JR		 896
897 pages = iommu_num_pages(address, size, PAGE_SIZE);
ae0cbbb1 898 s = false;
11b6402c
JR		 899
900 if (pages > 1) {
901 /*
902 * If we have to flush more than one page, flush all
903 * TLB entries for this domain
904 */
905 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
ae0cbbb1 906 s = true;
11b6402c
JR		 907 }
908
909 address &= PAGE_MASK;
910
911 memset(cmd, 0, sizeof(*cmd));
912 cmd->data[1] |= domid;
913 cmd->data[2] = lower_32_bits(address);
914 cmd->data[3] = upper_32_bits(address);
915 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
916 if (s) /* size bit - we flush more than one 4kb page */
917 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
df805abb 918 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
11b6402c
JR		 919 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
920}
921
cb41ed85
JR		 922static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
923 u64 address, size_t size)
924{
925 u64 pages;
ae0cbbb1 926 bool s;
cb41ed85
JR		 927
928 pages = iommu_num_pages(address, size, PAGE_SIZE);
ae0cbbb1 929 s = false;
cb41ed85
JR		 930
931 if (pages > 1) {
932 /*
933 * If we have to flush more than one page, flush all
934 * TLB entries for this domain
935 */
936 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
ae0cbbb1 937 s = true;
cb41ed85
JR		 938 }
939
940 address &= PAGE_MASK;
941
942 memset(cmd, 0, sizeof(*cmd));
943 cmd->data[0] = devid;
944 cmd->data[0] |= (qdep & 0xff) << 24;
945 cmd->data[1] = devid;
946 cmd->data[2] = lower_32_bits(address);
947 cmd->data[3] = upper_32_bits(address);
948 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
949 if (s)
950 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
951}
952
22e266c7
JR		 953static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
954 u64 address, bool size)
955{
956 memset(cmd, 0, sizeof(*cmd));
957
958 address &= ~(0xfffULL);
959
a919a018 960 cmd->data[0] = pasid;
22e266c7
JR		 961 cmd->data[1] = domid;
962 cmd->data[2] = lower_32_bits(address);
963 cmd->data[3] = upper_32_bits(address);
964 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
965 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
966 if (size)
967 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
968 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
969}
970
971static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
972 int qdep, u64 address, bool size)
973{
974 memset(cmd, 0, sizeof(*cmd));
975
976 address &= ~(0xfffULL);
977
978 cmd->data[0] = devid;
e8d2d82d 979 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
22e266c7
JR		 980 cmd->data[0] |= (qdep & 0xff) << 24;
981 cmd->data[1] = devid;
e8d2d82d 982 cmd->data[1] |= (pasid & 0xff) << 16;
22e266c7
JR		 983 cmd->data[2] = lower_32_bits(address);
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
985 cmd->data[3] = upper_32_bits(address);
986 if (size)
987 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
988 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
989}
990
c99afa25
JR		 991static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
992 int status, int tag, bool gn)
993{
994 memset(cmd, 0, sizeof(*cmd));
995
996 cmd->data[0] = devid;
997 if (gn) {
a919a018 998 cmd->data[1] = pasid;
c99afa25
JR		 999 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1000 }
1001 cmd->data[3] = tag & 0x1ff;
1002 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1003
1004 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1005}
1006
58fc7f14
JR		 1007static void build_inv_all(struct iommu_cmd *cmd)
1008{
1009 memset(cmd, 0, sizeof(*cmd));
1010 CMD_SET_TYPE(cmd, CMD_INV_ALL);
a19ae1ec
JR		 1011}
1012
7ef2798d
JR		 1013static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1014{
1015 memset(cmd, 0, sizeof(*cmd));
1016 cmd->data[0] = devid;
1017 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1018}
1019
431b2a20 1020/*
431b2a20 1021 * Writes the command to the IOMMUs command buffer and informs the
ac0ea6e9 1022 * hardware about the new command.
431b2a20 1023 */
4bf5beef
JR		 1024static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1025 struct iommu_cmd *cmd,
1026 bool sync)
a19ae1ec 1027{
23e967e1 1028 unsigned int count = 0;
d334a563 1029 u32 left, next_tail;
a19ae1ec 1030
d334a563 1031 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
ac0ea6e9 1032again:
d334a563 1033 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
a19ae1ec 1034
432abf68 1035 if (left <= 0x20) {
23e967e1
TL		 1036 /* Skip udelay() the first time around */
1037 if (count++) {
1038 if (count == LOOP_TIMEOUT) {
1039 pr_err("AMD-Vi: Command buffer timeout\n");
1040 return -EIO;
1041 }
da49f6df 1042
23e967e1
TL		 1043 udelay(1);
1044 }
ac0ea6e9 1045
23e967e1
TL		 1046 /* Update head and recheck remaining space */
1047 iommu->cmd_buf_head = readl(iommu->mmio_base +
1048 MMIO_CMD_HEAD_OFFSET);
ac0ea6e9
JR		 1049
1050 goto again;
8d201968
JR		 1051 }
1052
d334a563 1053 copy_cmd_to_buffer(iommu, cmd);
ac0ea6e9 1054
23e967e1 1055 /* Do we need to make sure all commands are processed? */
f1ca1512 1056 iommu->need_sync = sync;
ac0ea6e9 1057
4bf5beef
JR		 1058 return 0;
1059}
1060
1061static int iommu_queue_command_sync(struct amd_iommu *iommu,
1062 struct iommu_cmd *cmd,
1063 bool sync)
1064{
1065 unsigned long flags;
1066 int ret;
1067
27790398 1068 raw_spin_lock_irqsave(&iommu->lock, flags);
4bf5beef 1069 ret = __iommu_queue_command_sync(iommu, cmd, sync);
27790398 1070 raw_spin_unlock_irqrestore(&iommu->lock, flags);
8d201968 1071
4bf5beef 1072 return ret;
8d201968
JR		 1073}
1074
f1ca1512
JR		 1075static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1076{
1077 return iommu_queue_command_sync(iommu, cmd, true);
1078}
1079
8d201968
JR		 1080/*
1081 * This function queues a completion wait command into the command
1082 * buffer of an IOMMU
1083 */
a19ae1ec 1084static int iommu_completion_wait(struct amd_iommu *iommu)
8d201968
JR		 1085{
1086 struct iommu_cmd cmd;
4bf5beef 1087 unsigned long flags;
ac0ea6e9 1088 int ret;
8d201968 1089
09ee17eb 1090 if (!iommu->need_sync)
815b33fd 1091 return 0;
09ee17eb 1092
a19ae1ec 1093
4bf5beef
JR		 1094 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1095
27790398 1096 raw_spin_lock_irqsave(&iommu->lock, flags);
4bf5beef
JR		 1097
1098 iommu->cmd_sem = 0;
1099
1100 ret = __iommu_queue_command_sync(iommu, &cmd, false);
a19ae1ec 1101 if (ret)
4bf5beef
JR		 1102 goto out_unlock;
1103
1104 ret = wait_on_sem(&iommu->cmd_sem);
1105
1106out_unlock:
27790398 1107 raw_spin_unlock_irqrestore(&iommu->lock, flags);
8d201968 1108
4bf5beef 1109 return ret;
8d201968
JR		 1110}
1111
d8c13085 1112static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
a19ae1ec 1113{
d8c13085 1114 struct iommu_cmd cmd;
a19ae1ec 1115
d8c13085 1116 build_inv_dte(&cmd, devid);
7e4f88da 1117
d8c13085
JR		 1118 return iommu_queue_command(iommu, &cmd);
1119}
09ee17eb 1120
0688a099 1121static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
7d0c5cc5
JR		 1122{
1123 u32 devid;
09ee17eb 1124
7d0c5cc5
JR		 1125 for (devid = 0; devid <= 0xffff; ++devid)
1126 iommu_flush_dte(iommu, devid);
a19ae1ec 1127
7d0c5cc5
JR		 1128 iommu_completion_wait(iommu);
1129}
84df8175 1130
7d0c5cc5
JR		 1131/*
1132 * This function uses heavy locking and may disable irqs for some time. But
1133 * this is no issue because it is only called during resume.
1134 */
0688a099 1135static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
7d0c5cc5
JR		 1136{
1137 u32 dom_id;
a19ae1ec 1138
7d0c5cc5
JR		 1139 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1140 struct iommu_cmd cmd;
1141 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1142 dom_id, 1);
1143 iommu_queue_command(iommu, &cmd);
1144 }
8eed9833 1145
7d0c5cc5 1146 iommu_completion_wait(iommu);
a19ae1ec
JR		 1147}
1148
0688a099 1149static void amd_iommu_flush_all(struct amd_iommu *iommu)
0518a3a4 1150{
58fc7f14 1151 struct iommu_cmd cmd;
0518a3a4 1152
58fc7f14 1153 build_inv_all(&cmd);
0518a3a4 1154
58fc7f14
JR		 1155 iommu_queue_command(iommu, &cmd);
1156 iommu_completion_wait(iommu);
1157}
1158
7ef2798d
JR		 1159static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1160{
1161 struct iommu_cmd cmd;
1162
1163 build_inv_irt(&cmd, devid);
1164
1165 iommu_queue_command(iommu, &cmd);
1166}
1167
0688a099 1168static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
7ef2798d
JR		 1169{
1170 u32 devid;
1171
1172 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1173 iommu_flush_irt(iommu, devid);
1174
1175 iommu_completion_wait(iommu);
1176}
1177
7d0c5cc5
JR		 1178void iommu_flush_all_caches(struct amd_iommu *iommu)
1179{
58fc7f14 1180 if (iommu_feature(iommu, FEATURE_IA)) {
0688a099 1181 amd_iommu_flush_all(iommu);
58fc7f14 1182 } else {
0688a099
JR		 1183 amd_iommu_flush_dte_all(iommu);
1184 amd_iommu_flush_irt_all(iommu);
1185 amd_iommu_flush_tlb_all(iommu);
0518a3a4
JR		 1186 }
1187}
1188
431b2a20 1189/*
cb41ed85 1190 * Command send function for flushing on-device TLB
431b2a20 1191 */
6c542047
JR		 1192static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1193 u64 address, size_t size)
3fa43655
JR		 1194{
1195 struct amd_iommu *iommu;
b00d3bcf 1196 struct iommu_cmd cmd;
cb41ed85 1197 int qdep;
3fa43655 1198
ea61cddb
JR		 1199 qdep = dev_data->ats.qdep;
1200 iommu = amd_iommu_rlookup_table[dev_data->devid];
3fa43655 1201
ea61cddb 1202 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
b00d3bcf
JR		 1203
1204 return iommu_queue_command(iommu, &cmd);
3fa43655
JR		 1205}
1206
431b2a20 1207/*
431b2a20 1208 * Command send function for invalidating a device table entry
431b2a20 1209 */
6c542047 1210static int device_flush_dte(struct iommu_dev_data *dev_data)
a19ae1ec 1211{
3fa43655 1212 struct amd_iommu *iommu;
e25bfb56 1213 u16 alias;
ee2fa743 1214 int ret;
a19ae1ec 1215
6c542047 1216 iommu = amd_iommu_rlookup_table[dev_data->devid];
e3156048 1217 alias = dev_data->alias;
a19ae1ec 1218
f62dda66 1219 ret = iommu_flush_dte(iommu, dev_data->devid);
e25bfb56
JR		 1220 if (!ret && alias != dev_data->devid)
1221 ret = iommu_flush_dte(iommu, alias);
cb41ed85
JR		 1222 if (ret)
1223 return ret;
1224
ea61cddb 1225 if (dev_data->ats.enabled)
6c542047 1226 ret = device_flush_iotlb(dev_data, 0, ~0UL);
ee2fa743 1227
ee2fa743 1228 return ret;
a19ae1ec
JR		 1229}
1230
431b2a20
JR		 1231/*
1232 * TLB invalidation function which is called from the mapping functions.
1233 * It invalidates a single PTE if the range to flush is within a single
1234 * page. Otherwise it flushes the whole TLB of the IOMMU.
1235 */
17b124bf
JR		 1236static void __domain_flush_pages(struct protection_domain *domain,
1237 u64 address, size_t size, int pde)
a19ae1ec 1238{
cb41ed85 1239 struct iommu_dev_data *dev_data;
11b6402c
JR		 1240 struct iommu_cmd cmd;
1241 int ret = 0, i;
a19ae1ec 1242
11b6402c 1243 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
999ba417 1244
6b9376e3 1245 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
6de8ad9b
JR		 1246 if (!domain->dev_iommu[i])
1247 continue;
1248
1249 /*
1250 * Devices of this domain are behind this IOMMU
1251 * We need a TLB flush
1252 */
11b6402c 1253 ret |= iommu_queue_command(amd_iommus[i], &cmd);
6de8ad9b
JR		 1254 }
1255
cb41ed85 1256 list_for_each_entry(dev_data, &domain->dev_list, list) {
cb41ed85 1257
ea61cddb 1258 if (!dev_data->ats.enabled)
cb41ed85
JR		 1259 continue;
1260
6c542047 1261 ret |= device_flush_iotlb(dev_data, address, size);
cb41ed85
JR		 1262 }
1263
11b6402c 1264 WARN_ON(ret);
6de8ad9b
JR		 1265}
1266
17b124bf
JR		 1267static void domain_flush_pages(struct protection_domain *domain,
1268 u64 address, size_t size)
6de8ad9b 1269{
17b124bf 1270 __domain_flush_pages(domain, address, size, 0);
a19ae1ec 1271}
b6c02715 1272
1c655773 1273/* Flush the whole IO/TLB for a given protection domain */
17b124bf 1274static void domain_flush_tlb(struct protection_domain *domain)
1c655773 1275{
17b124bf 1276 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1c655773
JR		 1277}
1278
42a49f96 1279/* Flush the whole IO/TLB for a given protection domain - including PDE */
17b124bf 1280static void domain_flush_tlb_pde(struct protection_domain *domain)
42a49f96 1281{
17b124bf 1282 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
42a49f96
CW		 1283}
1284
17b124bf 1285static void domain_flush_complete(struct protection_domain *domain)
b00d3bcf 1286{
17b124bf 1287 int i;
18811f55 1288
6b9376e3 1289 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
f1eae7c5 1290 if (domain && !domain->dev_iommu[i])
17b124bf 1291 continue;
bfd1be18 1292
17b124bf
JR		 1293 /*
1294 * Devices of this domain are behind this IOMMU
1295 * We need to wait for completion of all commands.
1296 */
1297 iommu_completion_wait(amd_iommus[i]);
bfd1be18 1298 }
e394d72a
JR		 1299}
1300
b00d3bcf 1301
09b42804 1302/*
b00d3bcf 1303 * This function flushes the DTEs for all devices in domain
09b42804 1304 */
17b124bf 1305static void domain_flush_devices(struct protection_domain *domain)
e394d72a 1306{
b00d3bcf 1307 struct iommu_dev_data *dev_data;
b26e81b8 1308
b00d3bcf 1309 list_for_each_entry(dev_data, &domain->dev_list, list)
6c542047 1310 device_flush_dte(dev_data);
a345b23b
JR		 1311}
1312
431b2a20
JR		 1313/****************************************************************************
1314 *
1315 * The functions below are used the create the page table mappings for
1316 * unity mapped regions.
1317 *
1318 ****************************************************************************/
1319
308973d3
JR		 1320/*
1321 * This function is used to add another level to an IO page table. Adding
1322 * another level increases the size of the address space by 9 bits to a size up
1323 * to 64 bits.
1324 */
1325static bool increase_address_space(struct protection_domain *domain,
1326 gfp_t gfp)
1327{
1328 u64 *pte;
1329
1330 if (domain->mode == PAGE_MODE_6_LEVEL)
1331 /* address space already 64 bit large */
1332 return false;
1333
1334 pte = (void *)get_zeroed_page(gfp);
1335 if (!pte)
1336 return false;
1337
1338 *pte = PM_LEVEL_PDE(domain->mode,
2543a786 1339 iommu_virt_to_phys(domain->pt_root));
308973d3
JR		 1340 domain->pt_root = pte;
1341 domain->mode += 1;
1342 domain->updated = true;
1343
1344 return true;
1345}
1346
1347static u64 *alloc_pte(struct protection_domain *domain,
1348 unsigned long address,
cbb9d729 1349 unsigned long page_size,
308973d3
JR		 1350 u64 **pte_page,
1351 gfp_t gfp)
1352{
cbb9d729 1353 int level, end_lvl;
308973d3 1354 u64 *pte, *page;
cbb9d729
JR		 1355
1356 BUG_ON(!is_power_of_2(page_size));
308973d3
JR		 1357
1358 while (address > PM_LEVEL_SIZE(domain->mode))
1359 increase_address_space(domain, gfp);
1360
cbb9d729
JR		 1361 level = domain->mode - 1;
1362 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1363 address = PAGE_SIZE_ALIGN(address, page_size);
1364 end_lvl = PAGE_SIZE_LEVEL(page_size);
308973d3
JR		 1365
1366 while (level > end_lvl) {
7bfa5bd2
JR		 1367 u64 __pte, __npte;
1368
1369 __pte = *pte;
1370
1371 if (!IOMMU_PTE_PRESENT(__pte)) {
308973d3
JR		 1372 page = (u64 *)get_zeroed_page(gfp);
1373 if (!page)
1374 return NULL;
7bfa5bd2 1375
2543a786 1376 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
7bfa5bd2 1377
134414ff
BH		 1378 /* pte could have been changed somewhere. */
1379 if (cmpxchg64(pte, __pte, __npte) != __pte) {
7bfa5bd2
JR		 1380 free_page((unsigned long)page);
1381 continue;
1382 }
308973d3
JR		 1383 }
1384
cbb9d729
JR		 1385 /* No level skipping support yet */
1386 if (PM_PTE_LEVEL(*pte) != level)
1387 return NULL;
1388
308973d3
JR		 1389 level -= 1;
1390
1391 pte = IOMMU_PTE_PAGE(*pte);
1392
1393 if (pte_page && level == end_lvl)
1394 *pte_page = pte;
1395
1396 pte = &pte[PM_LEVEL_INDEX(level, address)];
1397 }
1398
1399 return pte;
1400}
1401
1402/*
1403 * This function checks if there is a PTE for a given dma address. If
1404 * there is one, it returns the pointer to it.
1405 */
3039ca1b
JR		 1406static u64 *fetch_pte(struct protection_domain *domain,
1407 unsigned long address,
1408 unsigned long *page_size)
308973d3
JR		 1409{
1410 int level;
1411 u64 *pte;
1412
4674686d 1413 *page_size = 0;
1414
24cd7723
JR		 1415 if (address > PM_LEVEL_SIZE(domain->mode))
1416 return NULL;
1417
3039ca1b
JR		 1418 level = domain->mode - 1;
1419 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1420 *page_size = PTE_LEVEL_PAGE_SIZE(level);
308973d3 1421
24cd7723
JR		 1422 while (level > 0) {
1423
1424 /* Not Present */
308973d3
JR		 1425 if (!IOMMU_PTE_PRESENT(*pte))
1426 return NULL;
1427
24cd7723 1428 /* Large PTE */
3039ca1b
JR		 1429 if (PM_PTE_LEVEL(*pte) == 7 ||
1430 PM_PTE_LEVEL(*pte) == 0)
1431 break;
24cd7723
JR		 1432
1433 /* No level skipping support yet */
1434 if (PM_PTE_LEVEL(*pte) != level)
1435 return NULL;
1436
308973d3
JR		 1437 level -= 1;
1438
24cd7723 1439 /* Walk to the next level */
3039ca1b
JR		 1440 pte = IOMMU_PTE_PAGE(*pte);
1441 pte = &pte[PM_LEVEL_INDEX(level, address)];
1442 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1443 }
1444
1445 if (PM_PTE_LEVEL(*pte) == 0x07) {
1446 unsigned long pte_mask;
1447
1448 /*
1449 * If we have a series of large PTEs, make
1450 * sure to return a pointer to the first one.
1451 */
1452 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1453 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1454 pte = (u64 *)(((unsigned long)pte) & pte_mask);
308973d3
JR		 1455 }
1456
1457 return pte;
1458}
1459
431b2a20
JR		 1460/*
1461 * Generic mapping functions. It maps a physical address into a DMA
1462 * address space. It allocates the page table pages if necessary.
1463 * In the future it can be extended to a generic mapping function
1464 * supporting all features of AMD IOMMU page tables like level skipping
1465 * and full 64 bit address spaces.
1466 */
38e817fe
JR		 1467static int iommu_map_page(struct protection_domain *dom,
1468 unsigned long bus_addr,
1469 unsigned long phys_addr,
b911b89b 1470 unsigned long page_size,
abdc5eb3 1471 int prot,
b911b89b 1472 gfp_t gfp)
bd0e5211 1473{
8bda3092 1474 u64 __pte, *pte;
cbb9d729 1475 int i, count;
abdc5eb3 1476
d4b03664
JR		 1477 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1478 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1479
bad1cac2 1480 if (!(prot & IOMMU_PROT_MASK))
bd0e5211
JR		 1481 return -EINVAL;
1482
d4b03664 1483 count = PAGE_SIZE_PTE_COUNT(page_size);
b911b89b 1484 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
cbb9d729 1485
63eaa75e
ML		 1486 if (!pte)
1487 return -ENOMEM;
1488
cbb9d729
JR		 1489 for (i = 0; i < count; ++i)
1490 if (IOMMU_PTE_PRESENT(pte[i]))
1491 return -EBUSY;
bd0e5211 1492
d4b03664 1493 if (count > 1) {
2543a786 1494 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
07a80a6b 1495 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
cbb9d729 1496 } else
4dfc2788 1497 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
bd0e5211 1498
bd0e5211
JR		 1499 if (prot & IOMMU_PROT_IR)
1500 __pte |= IOMMU_PTE_IR;
1501 if (prot & IOMMU_PROT_IW)
1502 __pte |= IOMMU_PTE_IW;
1503
cbb9d729
JR		 1504 for (i = 0; i < count; ++i)
1505 pte[i] = __pte;
bd0e5211 1506
04bfdd84
JR		 1507 update_domain(dom);
1508
bd0e5211
JR		 1509 return 0;
1510}
1511
24cd7723
JR		 1512static unsigned long iommu_unmap_page(struct protection_domain *dom,
1513 unsigned long bus_addr,
1514 unsigned long page_size)
eb74ff6c 1515{
71b390e9
JR		 1516 unsigned long long unmapped;
1517 unsigned long unmap_size;
24cd7723
JR		 1518 u64 *pte;
1519
1520 BUG_ON(!is_power_of_2(page_size));
1521
1522 unmapped = 0;
eb74ff6c 1523
24cd7723
JR		 1524 while (unmapped < page_size) {
1525
71b390e9
JR		 1526 pte = fetch_pte(dom, bus_addr, &unmap_size);
1527
1528 if (pte) {
1529 int i, count;
1530
1531 count = PAGE_SIZE_PTE_COUNT(unmap_size);
24cd7723
JR		 1532 for (i = 0; i < count; i++)
1533 pte[i] = 0ULL;
1534 }
1535
1536 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1537 unmapped += unmap_size;
1538 }
1539
60d0ca3c 1540 BUG_ON(unmapped && !is_power_of_2(unmapped));
eb74ff6c 1541
24cd7723 1542 return unmapped;
eb74ff6c 1543}
eb74ff6c 1544
431b2a20
JR		 1545/****************************************************************************
1546 *
1547 * The next functions belong to the address allocator for the dma_ops
2d4c515b 1548 * interface functions.
431b2a20
JR		 1549 *
1550 ****************************************************************************/
d3086444 1551
9cabe89b 1552
256e4621
JR		 1553static unsigned long dma_ops_alloc_iova(struct device *dev,
1554 struct dma_ops_domain *dma_dom,
1555 unsigned int pages, u64 dma_mask)
384de729 1556{
256e4621 1557 unsigned long pfn = 0;
384de729 1558
256e4621 1559 pages = __roundup_pow_of_two(pages);
ccb50e03 1560
256e4621
JR		 1561 if (dma_mask > DMA_BIT_MASK(32))
1562 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
538d5b33 1563 IOVA_PFN(DMA_BIT_MASK(32)), false);
7b5e25b8 1564
256e4621 1565 if (!pfn)
538d5b33
TN		 1566 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1567 IOVA_PFN(dma_mask), true);
5f6bed50 1568
256e4621 1569 return (pfn << PAGE_SHIFT);
384de729
JR		 1570}
1571
256e4621
JR		 1572static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1573 unsigned long address,
1574 unsigned int pages)
d3086444 1575{
256e4621
JR		 1576 pages = __roundup_pow_of_two(pages);
1577 address >>= PAGE_SHIFT;
384de729 1578
256e4621 1579 free_iova_fast(&dma_dom->iovad, address, pages);
d3086444
JR		 1580}
1581
431b2a20
JR		 1582/****************************************************************************
1583 *
1584 * The next functions belong to the domain allocation. A domain is
1585 * allocated for every IOMMU as the default domain. If device isolation
1586 * is enabled, every device get its own domain. The most important thing
1587 * about domains is the page table mapping the DMA address space they
1588 * contain.
1589 *
1590 ****************************************************************************/
1591
aeb26f55
JR		 1592/*
1593 * This function adds a protection domain to the global protection domain list
1594 */
1595static void add_domain_to_list(struct protection_domain *domain)
1596{
1597 unsigned long flags;
1598
1599 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1600 list_add(&domain->list, &amd_iommu_pd_list);
1601 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1602}
1603
1604/*
1605 * This function removes a protection domain to the global
1606 * protection domain list
1607 */
1608static void del_domain_from_list(struct protection_domain *domain)
1609{
1610 unsigned long flags;
1611
1612 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1613 list_del(&domain->list);
1614 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1615}
1616
ec487d1a
JR		 1617static u16 domain_id_alloc(void)
1618{
ec487d1a
JR		 1619 int id;
1620
2bc00180 1621 spin_lock(&pd_bitmap_lock);
ec487d1a
JR		 1622 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1623 BUG_ON(id == 0);
1624 if (id > 0 && id < MAX_DOMAIN_ID)
1625 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1626 else
1627 id = 0;
2bc00180 1628 spin_unlock(&pd_bitmap_lock);
ec487d1a
JR		 1629
1630 return id;
1631}
1632
a2acfb75
JR		 1633static void domain_id_free(int id)
1634{
2bc00180 1635 spin_lock(&pd_bitmap_lock);
a2acfb75
JR		 1636 if (id > 0 && id < MAX_DOMAIN_ID)
1637 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
2bc00180 1638 spin_unlock(&pd_bitmap_lock);
a2acfb75 1639}
a2acfb75 1640
5c34c403
JR		 1641#define DEFINE_FREE_PT_FN(LVL, FN) \
1642static void free_pt_##LVL (unsigned long __pt) \
1643{ \
1644 unsigned long p; \
1645 u64 *pt; \
1646 int i; \
1647 \
1648 pt = (u64 *)__pt; \
1649 \
1650 for (i = 0; i < 512; ++i) { \
0b3fff54 1651 /* PTE present? */ \
5c34c403
JR		 1652 if (!IOMMU_PTE_PRESENT(pt[i])) \
1653 continue; \
1654 \
0b3fff54
JR		 1655 /* Large PTE? */ \
1656 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1657 PM_PTE_LEVEL(pt[i]) == 7) \
1658 continue; \
1659 \
5c34c403
JR		 1660 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1661 FN(p); \
1662 } \
1663 free_page((unsigned long)pt); \
1664}
1665
1666DEFINE_FREE_PT_FN(l2, free_page)
1667DEFINE_FREE_PT_FN(l3, free_pt_l2)
1668DEFINE_FREE_PT_FN(l4, free_pt_l3)
1669DEFINE_FREE_PT_FN(l5, free_pt_l4)
1670DEFINE_FREE_PT_FN(l6, free_pt_l5)
1671
86db2e5d 1672static void free_pagetable(struct protection_domain *domain)
ec487d1a 1673{
5c34c403 1674 unsigned long root = (unsigned long)domain->pt_root;
ec487d1a 1675
5c34c403
JR		 1676 switch (domain->mode) {
1677 case PAGE_MODE_NONE:
1678 break;
1679 case PAGE_MODE_1_LEVEL:
1680 free_page(root);
1681 break;
1682 case PAGE_MODE_2_LEVEL:
1683 free_pt_l2(root);
1684 break;
1685 case PAGE_MODE_3_LEVEL:
1686 free_pt_l3(root);
1687 break;
1688 case PAGE_MODE_4_LEVEL:
1689 free_pt_l4(root);
1690 break;
1691 case PAGE_MODE_5_LEVEL:
1692 free_pt_l5(root);
1693 break;
1694 case PAGE_MODE_6_LEVEL:
1695 free_pt_l6(root);
1696 break;
1697 default:
1698 BUG();
ec487d1a 1699 }
ec487d1a
JR		 1700}
1701
b16137b1
JR		 1702static void free_gcr3_tbl_level1(u64 *tbl)
1703{
1704 u64 *ptr;
1705 int i;
1706
1707 for (i = 0; i < 512; ++i) {
1708 if (!(tbl[i] & GCR3_VALID))
1709 continue;
1710
2543a786 1711 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
b16137b1
JR		 1712
1713 free_page((unsigned long)ptr);
1714 }
1715}
1716
1717static void free_gcr3_tbl_level2(u64 *tbl)
1718{
1719 u64 *ptr;
1720 int i;
1721
1722 for (i = 0; i < 512; ++i) {
1723 if (!(tbl[i] & GCR3_VALID))
1724 continue;
1725
2543a786 1726 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
b16137b1
JR		 1727
1728 free_gcr3_tbl_level1(ptr);
1729 }
1730}
1731
52815b75
JR		 1732static void free_gcr3_table(struct protection_domain *domain)
1733{
b16137b1
JR		 1734 if (domain->glx == 2)
1735 free_gcr3_tbl_level2(domain->gcr3_tbl);
1736 else if (domain->glx == 1)
1737 free_gcr3_tbl_level1(domain->gcr3_tbl);
23d3a98c
JR		 1738 else
1739 BUG_ON(domain->glx != 0);
b16137b1 1740
52815b75
JR		 1741 free_page((unsigned long)domain->gcr3_tbl);
1742}
1743
fca6af6a
JR		 1744static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1745{
fca6af6a
JR		 1746 domain_flush_tlb(&dom->domain);
1747 domain_flush_complete(&dom->domain);
fd62190a
JR		 1748}
1749
9003d618 1750static void iova_domain_flush_tlb(struct iova_domain *iovad)
fd62190a 1751{
9003d618 1752 struct dma_ops_domain *dom;
fd62190a 1753
9003d618 1754 dom = container_of(iovad, struct dma_ops_domain, iovad);
fca6af6a
JR		 1755
1756 dma_ops_domain_flush_tlb(dom);
fca6af6a
JR		 1757}
1758
431b2a20
JR		 1759/*
1760 * Free a domain, only used if something went wrong in the
1761 * allocation path and we need to free an already allocated page table
1762 */
ec487d1a
JR		 1763static void dma_ops_domain_free(struct dma_ops_domain *dom)
1764{
1765 if (!dom)
1766 return;
1767
aeb26f55
JR		 1768 del_domain_from_list(&dom->domain);
1769
2d4c515b 1770 put_iova_domain(&dom->iovad);
ec487d1a 1771
2d4c515b 1772 free_pagetable(&dom->domain);
ec487d1a 1773
c3db901c
BH		 1774 if (dom->domain.id)
1775 domain_id_free(dom->domain.id);
1776
ec487d1a
JR		 1777 kfree(dom);
1778}
1779
431b2a20
JR		 1780/*
1781 * Allocates a new protection domain usable for the dma_ops functions.
b595076a 1782 * It also initializes the page table and the address allocator data
431b2a20
JR		 1783 * structures required for the dma_ops interface
1784 */
87a64d52 1785static struct dma_ops_domain *dma_ops_domain_alloc(void)
ec487d1a
JR		 1786{
1787 struct dma_ops_domain *dma_dom;
ec487d1a
JR		 1788
1789 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1790 if (!dma_dom)
1791 return NULL;
1792
7a5a566e 1793 if (protection_domain_init(&dma_dom->domain))
ec487d1a 1794 goto free_dma_dom;
7a5a566e 1795
ffec2197 1796 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
ec487d1a 1797 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
9fdb19d6 1798 dma_dom->domain.flags = PD_DMA_OPS_MASK;
ec487d1a
JR		 1799 if (!dma_dom->domain.pt_root)
1800 goto free_dma_dom;
ec487d1a 1801
aa3ac946 1802 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
307d5851 1803
9003d618 1804 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
d4241a27
JR		 1805 goto free_dma_dom;
1806
9003d618
JR		 1807 /* Initialize reserved ranges */
1808 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
fca6af6a 1809
2d4c515b
JR		 1810 add_domain_to_list(&dma_dom->domain);
1811
ec487d1a
JR		 1812 return dma_dom;
1813
1814free_dma_dom:
1815 dma_ops_domain_free(dma_dom);
1816
1817 return NULL;
1818}
1819
5b28df6f
JR		 1820/*
1821 * little helper function to check whether a given protection domain is a
1822 * dma_ops domain
1823 */
1824static bool dma_ops_domain(struct protection_domain *domain)
1825{
1826 return domain->flags & PD_DMA_OPS_MASK;
1827}
1828
ff18c4e5
GH		 1829static void set_dte_entry(u16 devid, struct protection_domain *domain,
1830 bool ats, bool ppr)
b20ac0d4 1831{
132bd68f 1832 u64 pte_root = 0;
ee6c2868 1833 u64 flags = 0;
863c74eb 1834
132bd68f 1835 if (domain->mode != PAGE_MODE_NONE)
2543a786 1836 pte_root = iommu_virt_to_phys(domain->pt_root);
132bd68f 1837
38ddf41b
JR		 1838 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1839 << DEV_ENTRY_MODE_SHIFT;
07a80a6b 1840 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
b20ac0d4 1841
ee6c2868
JR		 1842 flags = amd_iommu_dev_table[devid].data[1];
1843
fd7b5535
JR		 1844 if (ats)
1845 flags |= DTE_FLAG_IOTLB;
1846
ff18c4e5
GH		 1847 if (ppr) {
1848 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1849
1850 if (iommu_feature(iommu, FEATURE_EPHSUP))
1851 pte_root |= 1ULL << DEV_ENTRY_PPR;
1852 }
1853
52815b75 1854 if (domain->flags & PD_IOMMUV2_MASK) {
2543a786 1855 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
52815b75
JR		 1856 u64 glx = domain->glx;
1857 u64 tmp;
1858
1859 pte_root |= DTE_FLAG_GV;
1860 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1861
1862 /* First mask out possible old values for GCR3 table */
1863 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1864 flags &= ~tmp;
1865
1866 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1867 flags &= ~tmp;
1868
1869 /* Encode GCR3 table into DTE */
1870 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1871 pte_root |= tmp;
1872
1873 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1874 flags |= tmp;
1875
1876 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1877 flags |= tmp;
1878 }
1879
45a01c42 1880 flags &= ~DEV_DOMID_MASK;
ee6c2868
JR		 1881 flags |= domain->id;
1882
1883 amd_iommu_dev_table[devid].data[1] = flags;
1884 amd_iommu_dev_table[devid].data[0] = pte_root;
15898bbc
JR		 1885}
1886
1887static void clear_dte_entry(u16 devid)
1888{
15898bbc 1889 /* remove entry from the device table seen by the hardware */
07a80a6b 1890 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
cbf3ccd0 1891 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
15898bbc
JR		 1892
1893 amd_iommu_apply_erratum_63(devid);
7f760ddd
JR		 1894}
1895
ec9e79ef
JR		 1896static void do_attach(struct iommu_dev_data *dev_data,
1897 struct protection_domain *domain)
7f760ddd 1898{
7f760ddd 1899 struct amd_iommu *iommu;
e25bfb56 1900 u16 alias;
ec9e79ef 1901 bool ats;
fd7b5535 1902
ec9e79ef 1903 iommu = amd_iommu_rlookup_table[dev_data->devid];
e3156048 1904 alias = dev_data->alias;
ec9e79ef 1905 ats = dev_data->ats.enabled;
7f760ddd
JR		 1906
1907 /* Update data structures */
1908 dev_data->domain = domain;
1909 list_add(&dev_data->list, &domain->dev_list);
7f760ddd
JR		 1910
1911 /* Do reference counting */
1912 domain->dev_iommu[iommu->index] += 1;
1913 domain->dev_cnt += 1;
1914
e25bfb56 1915 /* Update device table */
ff18c4e5 1916 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
e25bfb56 1917 if (alias != dev_data->devid)
ff18c4e5 1918 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
e25bfb56 1919
6c542047 1920 device_flush_dte(dev_data);
7f760ddd
JR		 1921}
1922
ec9e79ef 1923static void do_detach(struct iommu_dev_data *dev_data)
7f760ddd 1924{
7f760ddd 1925 struct amd_iommu *iommu;
e25bfb56 1926 u16 alias;
7f760ddd 1927
ec9e79ef 1928 iommu = amd_iommu_rlookup_table[dev_data->devid];
e3156048 1929 alias = dev_data->alias;
15898bbc
JR		 1930
1931 /* decrease reference counters */
7f760ddd
JR		 1932 dev_data->domain->dev_iommu[iommu->index] -= 1;
1933 dev_data->domain->dev_cnt -= 1;
1934
1935 /* Update data structures */
1936 dev_data->domain = NULL;
1937 list_del(&dev_data->list);
f62dda66 1938 clear_dte_entry(dev_data->devid);
e25bfb56
JR		 1939 if (alias != dev_data->devid)
1940 clear_dte_entry(alias);
15898bbc 1941
7f760ddd 1942 /* Flush the DTE entry */
6c542047 1943 device_flush_dte(dev_data);
2b681faf
JR		 1944}
1945
1946/*
29a0c415
AMG		 1947 * If a device is not yet associated with a domain, this function makes the
1948 * device visible in the domain
2b681faf 1949 */
ec9e79ef 1950static int __attach_device(struct iommu_dev_data *dev_data,
15898bbc 1951 struct protection_domain *domain)
2b681faf 1952{
84fe6c19 1953 int ret;
657cbb6b 1954
2b681faf
JR		 1955 /* lock domain */
1956 spin_lock(&domain->lock);
1957
397111ab 1958 ret = -EBUSY;
150952f9 1959 if (dev_data->domain != NULL)
397111ab 1960 goto out_unlock;
15898bbc 1961
397111ab 1962 /* Attach alias group root */
150952f9 1963 do_attach(dev_data, domain);
24100055 1964
84fe6c19
JL		 1965 ret = 0;
1966
1967out_unlock:
1968
eba6ac60
JR		 1969 /* ready */
1970 spin_unlock(&domain->lock);
15898bbc 1971
84fe6c19 1972 return ret;
0feae533 1973}
b20ac0d4 1974
52815b75
JR		 1975
1976static void pdev_iommuv2_disable(struct pci_dev *pdev)
1977{
1978 pci_disable_ats(pdev);
1979 pci_disable_pri(pdev);
1980 pci_disable_pasid(pdev);
1981}
1982
6a113ddc
JR		 1983/* FIXME: Change generic reset-function to do the same */
1984static int pri_reset_while_enabled(struct pci_dev *pdev)
1985{
1986 u16 control;
1987 int pos;
1988
46277b75 1989 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
6a113ddc
JR		 1990 if (!pos)
1991 return -EINVAL;
1992
46277b75
JR		 1993 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1994 control |= PCI_PRI_CTRL_RESET;
1995 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
6a113ddc
JR		 1996
1997 return 0;
1998}
1999
52815b75
JR		 2000static int pdev_iommuv2_enable(struct pci_dev *pdev)
2001{
6a113ddc
JR		 2002 bool reset_enable;
2003 int reqs, ret;
2004
2005 /* FIXME: Hardcode number of outstanding requests for now */
2006 reqs = 32;
2007 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2008 reqs = 1;
2009 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
52815b75
JR		 2010
2011 /* Only allow access to user-accessible pages */
2012 ret = pci_enable_pasid(pdev, 0);
2013 if (ret)
2014 goto out_err;
2015
2016 /* First reset the PRI state of the device */
2017 ret = pci_reset_pri(pdev);
2018 if (ret)
2019 goto out_err;
2020
6a113ddc
JR		 2021 /* Enable PRI */
2022 ret = pci_enable_pri(pdev, reqs);
52815b75
JR		 2023 if (ret)
2024 goto out_err;
2025
6a113ddc
JR		 2026 if (reset_enable) {
2027 ret = pri_reset_while_enabled(pdev);
2028 if (ret)
2029 goto out_err;
2030 }
2031
52815b75
JR		 2032 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2033 if (ret)
2034 goto out_err;
2035
2036 return 0;
2037
2038out_err:
2039 pci_disable_pri(pdev);
2040 pci_disable_pasid(pdev);
2041
2042 return ret;
2043}
2044
c99afa25 2045/* FIXME: Move this to PCI code */
a3b93121 2046#define PCI_PRI_TLP_OFF (1 << 15)
c99afa25 2047
98f1ad25 2048static bool pci_pri_tlp_required(struct pci_dev *pdev)
c99afa25 2049{
a3b93121 2050 u16 status;
c99afa25
JR		 2051 int pos;
2052
46277b75 2053 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c99afa25
JR		 2054 if (!pos)
2055 return false;
2056
a3b93121 2057 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
c99afa25 2058
a3b93121 2059 return (status & PCI_PRI_TLP_OFF) ? true : false;
c99afa25
JR		 2060}
2061
407d733e 2062/*
29a0c415
AMG		 2063 * If a device is not yet associated with a domain, this function makes the
2064 * device visible in the domain
407d733e 2065 */
15898bbc
JR		 2066static int attach_device(struct device *dev,
2067 struct protection_domain *domain)
0feae533 2068{
2bf9a0a1 2069 struct pci_dev *pdev;
ea61cddb 2070 struct iommu_dev_data *dev_data;
eba6ac60 2071 unsigned long flags;
15898bbc 2072 int ret;
eba6ac60 2073
ea61cddb
JR		 2074 dev_data = get_dev_data(dev);
2075
2bf9a0a1
WZ		 2076 if (!dev_is_pci(dev))
2077 goto skip_ats_check;
2078
2079 pdev = to_pci_dev(dev);
52815b75 2080 if (domain->flags & PD_IOMMUV2_MASK) {
02ca2021 2081 if (!dev_data->passthrough)
52815b75
JR		 2082 return -EINVAL;
2083
02ca2021
JR		 2084 if (dev_data->iommu_v2) {
2085 if (pdev_iommuv2_enable(pdev) != 0)
2086 return -EINVAL;
52815b75 2087
02ca2021
JR		 2088 dev_data->ats.enabled = true;
2089 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2090 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2091 }
52815b75
JR		 2092 } else if (amd_iommu_iotlb_sup &&
2093 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
ea61cddb
JR		 2094 dev_data->ats.enabled = true;
2095 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2096 }
fd7b5535 2097
2bf9a0a1 2098skip_ats_check:
2cd1083d 2099 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2100 ret = __attach_device(dev_data, domain);
2cd1083d 2101 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
b20ac0d4 2102
0feae533
JR		 2103 /*
2104 * We might boot into a crash-kernel here. The crashed kernel
2105 * left the caches in the IOMMU dirty. So we have to flush
2106 * here to evict all dirty stuff.
2107 */
17b124bf 2108 domain_flush_tlb_pde(domain);
15898bbc
JR		 2109
2110 return ret;
b20ac0d4
JR		 2111}
2112
355bf553
JR		 2113/*
2114 * Removes a device from a protection domain (unlocked)
2115 */
ec9e79ef 2116static void __detach_device(struct iommu_dev_data *dev_data)
355bf553 2117{
2ca76279 2118 struct protection_domain *domain;
c4596114 2119
2ca76279 2120 domain = dev_data->domain;
71f77580 2121
f1dd0a8b 2122 spin_lock(&domain->lock);
24100055 2123
150952f9 2124 do_detach(dev_data);
7f760ddd 2125
f1dd0a8b 2126 spin_unlock(&domain->lock);
355bf553
JR		 2127}
2128
2129/*
2130 * Removes a device from a protection domain (with devtable_lock held)
2131 */
15898bbc 2132static void detach_device(struct device *dev)
355bf553 2133{
52815b75 2134 struct protection_domain *domain;
ea61cddb 2135 struct iommu_dev_data *dev_data;
355bf553
JR		 2136 unsigned long flags;
2137
ec9e79ef 2138 dev_data = get_dev_data(dev);
52815b75 2139 domain = dev_data->domain;
ec9e79ef 2140
ea3fd040
AMG		 2141 /*
2142 * First check if the device is still attached. It might already
2143 * be detached from its domain because the generic
2144 * iommu_detach_group code detached it and we try again here in
2145 * our alias handling.
2146 */
2147 if (WARN_ON(!dev_data->domain))
2148 return;
2149
355bf553 2150 /* lock device table */
2cd1083d 2151 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2152 __detach_device(dev_data);
2cd1083d 2153 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
fd7b5535 2154
2bf9a0a1
WZ		 2155 if (!dev_is_pci(dev))
2156 return;
2157
02ca2021 2158 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
52815b75
JR		 2159 pdev_iommuv2_disable(to_pci_dev(dev));
2160 else if (dev_data->ats.enabled)
ea61cddb 2161 pci_disable_ats(to_pci_dev(dev));
52815b75
JR		 2162
2163 dev_data->ats.enabled = false;
355bf553 2164}
e275a2a0 2165
aafd8ba0 2166static int amd_iommu_add_device(struct device *dev)
e275a2a0 2167{
5abcdba4 2168 struct iommu_dev_data *dev_data;
07ee8694 2169 struct iommu_domain *domain;
e275a2a0 2170 struct amd_iommu *iommu;
7aba6cb9 2171 int ret, devid;
e275a2a0 2172
aafd8ba0 2173 if (!check_device(dev) || get_dev_data(dev))
98fc5a69 2174 return 0;
e275a2a0 2175
aafd8ba0 2176 devid = get_device_id(dev);
9ee35e4c 2177 if (devid < 0)
7aba6cb9
WZ		 2178 return devid;
2179
aafd8ba0 2180 iommu = amd_iommu_rlookup_table[devid];
657cbb6b 2181
aafd8ba0 2182 ret = iommu_init_device(dev);
4d58b8a6
JR		 2183 if (ret) {
2184 if (ret != -ENOTSUPP)
2185 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2186 dev_name(dev));
657cbb6b 2187
aafd8ba0 2188 iommu_ignore_device(dev);
fec777c3 2189 dev->dma_ops = &dma_direct_ops;
aafd8ba0
JR		 2190 goto out;
2191 }
2192 init_iommu_group(dev);
2c9195e9 2193
07ee8694 2194 dev_data = get_dev_data(dev);
2c9195e9 2195
4d58b8a6 2196 BUG_ON(!dev_data);
657cbb6b 2197
1e6a7b04 2198 if (iommu_pass_through || dev_data->iommu_v2)
07ee8694 2199 iommu_request_dm_for_dev(dev);
ac1534a5 2200
07ee8694
JR		 2201 /* Domains are initialized for this device - have a look what we ended up with */
2202 domain = iommu_get_domain_for_dev(dev);
32302324 2203 if (domain->type == IOMMU_DOMAIN_IDENTITY)
07ee8694 2204 dev_data->passthrough = true;
32302324 2205 else
5657933d 2206 dev->dma_ops = &amd_iommu_dma_ops;
e275a2a0 2207
aafd8ba0 2208out:
e275a2a0
JR		 2209 iommu_completion_wait(iommu);
2210
e275a2a0
JR		 2211 return 0;
2212}
2213
aafd8ba0 2214static void amd_iommu_remove_device(struct device *dev)
8638c491 2215{
aafd8ba0 2216 struct amd_iommu *iommu;
7aba6cb9 2217 int devid;
aafd8ba0
JR		 2218
2219 if (!check_device(dev))
2220 return;
2221
2222 devid = get_device_id(dev);
9ee35e4c 2223 if (devid < 0)
7aba6cb9
WZ		 2224 return;
2225
aafd8ba0
JR		 2226 iommu = amd_iommu_rlookup_table[devid];
2227
2228 iommu_uninit_device(dev);
2229 iommu_completion_wait(iommu);
8638c491
JR		 2230}
2231
b097d11a
WZ		 2232static struct iommu_group *amd_iommu_device_group(struct device *dev)
2233{
2234 if (dev_is_pci(dev))
2235 return pci_device_group(dev);
2236
2237 return acpihid_device_group(dev);
2238}
2239
431b2a20
JR		 2240/*****************************************************************************
2241 *
2242 * The next functions belong to the dma_ops mapping/unmapping code.
2243 *
2244 *****************************************************************************/
2245
2246/*
2247 * In the dma_ops path we only have the struct device. This function
2248 * finds the corresponding IOMMU, the protection domain and the
2249 * requestor id for a given device.
2250 * If the device is not yet associated with a domain this is also done
2251 * in this function.
2252 */
94f6d190 2253static struct protection_domain *get_domain(struct device *dev)
b20ac0d4 2254{
94f6d190 2255 struct protection_domain *domain;
df3f7a6e 2256 struct iommu_domain *io_domain;
b20ac0d4 2257
f99c0f1c 2258 if (!check_device(dev))
94f6d190 2259 return ERR_PTR(-EINVAL);
b20ac0d4 2260
d26592a9 2261 domain = get_dev_data(dev)->domain;
df3f7a6e
BH		 2262 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2263 get_dev_data(dev)->defer_attach = false;
2264 io_domain = iommu_get_domain_for_dev(dev);
2265 domain = to_pdomain(io_domain);
2266 attach_device(dev, domain);
2267 }
ec62b1ab
BH		 2268 if (domain == NULL)
2269 return ERR_PTR(-EBUSY);
2270
0bb6e243 2271 if (!dma_ops_domain(domain))
94f6d190 2272 return ERR_PTR(-EBUSY);
f91ba190 2273
0bb6e243 2274 return domain;
b20ac0d4
JR		 2275}
2276
04bfdd84
JR		 2277static void update_device_table(struct protection_domain *domain)
2278{
492667da 2279 struct iommu_dev_data *dev_data;
04bfdd84 2280
3254de6b 2281 list_for_each_entry(dev_data, &domain->dev_list, list) {
ff18c4e5
GH		 2282 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2283 dev_data->iommu_v2);
3254de6b
JR		 2284
2285 if (dev_data->devid == dev_data->alias)
2286 continue;
2287
2288 /* There is an alias, update device table entry for it */
ff18c4e5
GH		 2289 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2290 dev_data->iommu_v2);
3254de6b 2291 }
04bfdd84
JR		 2292}
2293
2294static void update_domain(struct protection_domain *domain)
2295{
2296 if (!domain->updated)
2297 return;
2298
2299 update_device_table(domain);
17b124bf
JR		 2300
2301 domain_flush_devices(domain);
2302 domain_flush_tlb_pde(domain);
04bfdd84
JR		 2303
2304 domain->updated = false;
2305}
2306
f37f7f33
JR		 2307static int dir2prot(enum dma_data_direction direction)
2308{
2309 if (direction == DMA_TO_DEVICE)
2310 return IOMMU_PROT_IR;
2311 else if (direction == DMA_FROM_DEVICE)
2312 return IOMMU_PROT_IW;
2313 else if (direction == DMA_BIDIRECTIONAL)
2314 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2315 else
2316 return 0;
2317}
daae2d25 2318
431b2a20
JR		 2319/*
2320 * This function contains common code for mapping of a physically
24f81160
JR		 2321 * contiguous memory region into DMA address space. It is used by all
2322 * mapping functions provided with this IOMMU driver.
431b2a20
JR		 2323 * Must be called with the domain lock held.
2324 */
cb76c322 2325static dma_addr_t __map_single(struct device *dev,
cb76c322
JR		 2326 struct dma_ops_domain *dma_dom,
2327 phys_addr_t paddr,
2328 size_t size,
f37f7f33 2329 enum dma_data_direction direction,
832a90c3 2330 u64 dma_mask)
cb76c322
JR		 2331{
2332 dma_addr_t offset = paddr & ~PAGE_MASK;
53812c11 2333 dma_addr_t address, start, ret;
cb76c322 2334 unsigned int pages;
518d9b45 2335 int prot = 0;
cb76c322
JR		 2336 int i;
2337
e3c449f5 2338 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
cb76c322
JR		 2339 paddr &= PAGE_MASK;
2340
256e4621 2341 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
a869572c 2342 if (address == AMD_IOMMU_MAPPING_ERROR)
266a3bd2 2343 goto out;
cb76c322 2344
f37f7f33 2345 prot = dir2prot(direction);
518d9b45 2346
cb76c322
JR		 2347 start = address;
2348 for (i = 0; i < pages; ++i) {
518d9b45
JR		 2349 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2350 PAGE_SIZE, prot, GFP_ATOMIC);
2351 if (ret)
53812c11
JR		 2352 goto out_unmap;
2353
cb76c322
JR		 2354 paddr += PAGE_SIZE;
2355 start += PAGE_SIZE;
2356 }
2357 address += offset;
2358
ab7032bb 2359 if (unlikely(amd_iommu_np_cache)) {
17b124bf 2360 domain_flush_pages(&dma_dom->domain, address, size);
ab7032bb
JR		 2361 domain_flush_complete(&dma_dom->domain);
2362 }
270cab24 2363
cb76c322
JR		 2364out:
2365 return address;
53812c11
JR		 2366
2367out_unmap:
2368
2369 for (--i; i >= 0; --i) {
2370 start -= PAGE_SIZE;
518d9b45 2371 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
53812c11
JR		 2372 }
2373
256e4621
JR		 2374 domain_flush_tlb(&dma_dom->domain);
2375 domain_flush_complete(&dma_dom->domain);
2376
2377 dma_ops_free_iova(dma_dom, address, pages);
53812c11 2378
a869572c 2379 return AMD_IOMMU_MAPPING_ERROR;
cb76c322
JR		 2380}
2381
431b2a20
JR		 2382/*
2383 * Does the reverse of the __map_single function. Must be called with
2384 * the domain lock held too
2385 */
cd8c82e8 2386static void __unmap_single(struct dma_ops_domain *dma_dom,
cb76c322
JR		 2387 dma_addr_t dma_addr,
2388 size_t size,
2389 int dir)
2390{
2391 dma_addr_t i, start;
2392 unsigned int pages;
2393
e3c449f5 2394 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
cb76c322
JR		 2395 dma_addr &= PAGE_MASK;
2396 start = dma_addr;
2397
2398 for (i = 0; i < pages; ++i) {
518d9b45 2399 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
cb76c322
JR		 2400 start += PAGE_SIZE;
2401 }
2402
b1516a14 2403 if (amd_iommu_unmap_flush) {
b1516a14
JR		 2404 domain_flush_tlb(&dma_dom->domain);
2405 domain_flush_complete(&dma_dom->domain);
3c120143 2406 dma_ops_free_iova(dma_dom, dma_addr, pages);
b1516a14 2407 } else {
9003d618
JR		 2408 pages = __roundup_pow_of_two(pages);
2409 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
b1516a14 2410 }
cb76c322
JR		 2411}
2412
431b2a20
JR		 2413/*
2414 * The exported map_single function for dma_ops.
2415 */
51491367
FT		 2416static dma_addr_t map_page(struct device *dev, struct page *page,
2417 unsigned long offset, size_t size,
2418 enum dma_data_direction dir,
00085f1e 2419 unsigned long attrs)
4da70b9e 2420{
92d420ec 2421 phys_addr_t paddr = page_to_phys(page) + offset;
4da70b9e 2422 struct protection_domain *domain;
b3311b06 2423 struct dma_ops_domain *dma_dom;
832a90c3 2424 u64 dma_mask;
4da70b9e 2425
94f6d190
JR		 2426 domain = get_domain(dev);
2427 if (PTR_ERR(domain) == -EINVAL)
4da70b9e 2428 return (dma_addr_t)paddr;
94f6d190 2429 else if (IS_ERR(domain))
a869572c 2430 return AMD_IOMMU_MAPPING_ERROR;
4da70b9e 2431
f99c0f1c 2432 dma_mask = *dev->dma_mask;
b3311b06 2433 dma_dom = to_dma_ops_domain(domain);
f99c0f1c 2434
b3311b06 2435 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
4da70b9e
JR		 2436}
2437
431b2a20
JR		 2438/*
2439 * The exported unmap_single function for dma_ops.
2440 */
51491367 2441static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
00085f1e 2442 enum dma_data_direction dir, unsigned long attrs)
4da70b9e 2443{
4da70b9e 2444 struct protection_domain *domain;
b3311b06 2445 struct dma_ops_domain *dma_dom;
4da70b9e 2446
94f6d190
JR		 2447 domain = get_domain(dev);
2448 if (IS_ERR(domain))
5b28df6f
JR		 2449 return;
2450
b3311b06
JR		 2451 dma_dom = to_dma_ops_domain(domain);
2452
2453 __unmap_single(dma_dom, dma_addr, size, dir);
4da70b9e
JR		 2454}
2455
80187fd3
JR		 2456static int sg_num_pages(struct device *dev,
2457 struct scatterlist *sglist,
2458 int nelems)
2459{
2460 unsigned long mask, boundary_size;
2461 struct scatterlist *s;
2462 int i, npages = 0;
2463
2464 mask = dma_get_seg_boundary(dev);
2465 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2466 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2467
2468 for_each_sg(sglist, s, nelems, i) {
2469 int p, n;
2470
2471 s->dma_address = npages << PAGE_SHIFT;
2472 p = npages % boundary_size;
2473 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2474 if (p + n > boundary_size)
2475 npages += boundary_size - p;
2476 npages += n;
2477 }
2478
2479 return npages;
2480}
2481
431b2a20
JR		 2482/*
2483 * The exported map_sg function for dma_ops (handles scatter-gather
2484 * lists).
2485 */
65b050ad 2486static int map_sg(struct device *dev, struct scatterlist *sglist,
80187fd3 2487 int nelems, enum dma_data_direction direction,
00085f1e 2488 unsigned long attrs)
65b050ad 2489{
80187fd3 2490 int mapped_pages = 0, npages = 0, prot = 0, i;
65b050ad 2491 struct protection_domain *domain;
80187fd3 2492 struct dma_ops_domain *dma_dom;
65b050ad 2493 struct scatterlist *s;
80187fd3 2494 unsigned long address;
832a90c3 2495 u64 dma_mask;
65b050ad 2496
94f6d190 2497 domain = get_domain(dev);
a0e191b2 2498 if (IS_ERR(domain))
94f6d190 2499 return 0;
dbcc112e 2500
b3311b06 2501 dma_dom = to_dma_ops_domain(domain);
832a90c3 2502 dma_mask = *dev->dma_mask;
65b050ad 2503
80187fd3
JR		 2504 npages = sg_num_pages(dev, sglist, nelems);
2505
2506 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
a869572c 2507 if (address == AMD_IOMMU_MAPPING_ERROR)
80187fd3
JR		 2508 goto out_err;
2509
2510 prot = dir2prot(direction);
2511
2512 /* Map all sg entries */
65b050ad 2513 for_each_sg(sglist, s, nelems, i) {
80187fd3
JR		 2514 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2515
2516 for (j = 0; j < pages; ++j) {
2517 unsigned long bus_addr, phys_addr;
2518 int ret;
65b050ad 2519
80187fd3
JR		 2520 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2521 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2522 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2523 if (ret)
2524 goto out_unmap;
65b050ad 2525
80187fd3
JR		 2526 mapped_pages += 1;
2527 }
65b050ad
JR		 2528 }
2529
80187fd3
JR		 2530 /* Everything is mapped - write the right values into s->dma_address */
2531 for_each_sg(sglist, s, nelems, i) {
2532 s->dma_address += address + s->offset;
2533 s->dma_length = s->length;
2534 }
2535
2536 return nelems;
2537
2538out_unmap:
2539 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2540 dev_name(dev), npages);
2541
2542 for_each_sg(sglist, s, nelems, i) {
2543 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2544
2545 for (j = 0; j < pages; ++j) {
2546 unsigned long bus_addr;
92d420ec 2547
80187fd3
JR		 2548 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2549 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2550
2551 if (--mapped_pages)
2552 goto out_free_iova;
2553 }
65b050ad
JR		 2554 }
2555
80187fd3
JR		 2556out_free_iova:
2557 free_iova_fast(&dma_dom->iovad, address, npages);
2558
2559out_err:
92d420ec 2560 return 0;
65b050ad
JR		 2561}
2562
431b2a20
JR		 2563/*
2564 * The exported map_sg function for dma_ops (handles scatter-gather
2565 * lists).
2566 */
65b050ad 2567static void unmap_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e 2568 int nelems, enum dma_data_direction dir,
00085f1e 2569 unsigned long attrs)
65b050ad 2570{
65b050ad 2571 struct protection_domain *domain;
b3311b06 2572 struct dma_ops_domain *dma_dom;
80187fd3
JR		 2573 unsigned long startaddr;
2574 int npages = 2;
65b050ad 2575
94f6d190
JR		 2576 domain = get_domain(dev);
2577 if (IS_ERR(domain))
5b28df6f
JR		 2578 return;
2579
80187fd3 2580 startaddr = sg_dma_address(sglist) & PAGE_MASK;
b3311b06 2581 dma_dom = to_dma_ops_domain(domain);
80187fd3
JR		 2582 npages = sg_num_pages(dev, sglist, nelems);
2583
b3311b06 2584 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
65b050ad
JR		 2585}
2586
431b2a20
JR		 2587/*
2588 * The exported alloc_coherent function for dma_ops.
2589 */
5d8b53cf 2590static void *alloc_coherent(struct device *dev, size_t size,
baa676fc 2591 dma_addr_t *dma_addr, gfp_t flag,
00085f1e 2592 unsigned long attrs)
5d8b53cf 2593{
832a90c3 2594 u64 dma_mask = dev->coherent_dma_mask;
e16c4790
LT		 2595 struct protection_domain *domain;
2596 struct dma_ops_domain *dma_dom;
2597 struct page *page;
2598
2599 domain = get_domain(dev);
2600 if (PTR_ERR(domain) == -EINVAL) {
2601 page = alloc_pages(flag, get_order(size));
2602 *dma_addr = page_to_phys(page);
2603 return page_address(page);
2604 } else if (IS_ERR(domain))
2605 return NULL;
5d8b53cf 2606
e16c4790
LT		 2607 dma_dom = to_dma_ops_domain(domain);
2608 size = PAGE_ALIGN(size);
2609 dma_mask = dev->coherent_dma_mask;
2610 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2611 flag |= __GFP_ZERO;
2612
2613 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2614 if (!page) {
2615 if (!gfpflags_allow_blocking(flag))
3b839a57 2616 return NULL;
5d8b53cf 2617
e16c4790 2618 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
d834c5ab 2619 get_order(size), flag & __GFP_NOWARN);
e16c4790
LT		 2620 if (!page)
2621 return NULL;
2622 }
b468620f 2623
832a90c3
JR		 2624 if (!dma_mask)
2625 dma_mask = *dev->dma_mask;
2626
e16c4790
LT		 2627 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2628 size, DMA_BIDIRECTIONAL, dma_mask);
2629
a869572c 2630 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
5b28df6f 2631 goto out_free;
e16c4790
LT		 2632
2633 return page_address(page);
5b28df6f
JR		 2634
2635out_free:
e16c4790
LT		 2636
2637 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2638 __free_pages(page, get_order(size));
2639
5b28df6f 2640 return NULL;
5d8b53cf
JR		 2641}
2642
431b2a20
JR		 2643/*
2644 * The exported free_coherent function for dma_ops.
431b2a20 2645 */
5d8b53cf 2646static void free_coherent(struct device *dev, size_t size,
baa676fc 2647 void *virt_addr, dma_addr_t dma_addr,
00085f1e 2648 unsigned long attrs)
5d8b53cf 2649{
e16c4790
LT		 2650 struct protection_domain *domain;
2651 struct dma_ops_domain *dma_dom;
2652 struct page *page;
5d8b53cf 2653
e16c4790 2654 page = virt_to_page(virt_addr);
3b839a57
JR		 2655 size = PAGE_ALIGN(size);
2656
e16c4790
LT		 2657 domain = get_domain(dev);
2658 if (IS_ERR(domain))
2659 goto free_mem;
5b28df6f 2660
e16c4790
LT		 2661 dma_dom = to_dma_ops_domain(domain);
2662
2663 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
5d8b53cf 2664
e16c4790
LT		 2665free_mem:
2666 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2667 __free_pages(page, get_order(size));
5d8b53cf
JR		 2668}
2669
b39ba6ad
JR		 2670/*
2671 * This function is called by the DMA layer to find out if we can handle a
2672 * particular device. It is part of the dma_ops.
2673 */
2674static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2675{
fec777c3 2676 if (!dma_direct_supported(dev, mask))
5860acc1 2677 return 0;
420aef8a 2678 return check_device(dev);
b39ba6ad
JR		 2679}
2680
a869572c
CH		 2681static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2682{
2683 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2684}
2685
5299709d 2686static const struct dma_map_ops amd_iommu_dma_ops = {
a639a8ee
JR		 2687 .alloc = alloc_coherent,
2688 .free = free_coherent,
2689 .map_page = map_page,
2690 .unmap_page = unmap_page,
2691 .map_sg = map_sg,
2692 .unmap_sg = unmap_sg,
2693 .dma_supported = amd_iommu_dma_supported,
a869572c 2694 .mapping_error = amd_iommu_mapping_error,
6631ee9d
JR		 2695};
2696
81cd07b9
JR		 2697static int init_reserved_iova_ranges(void)
2698{
2699 struct pci_dev *pdev = NULL;
2700 struct iova *val;
2701
aa3ac946 2702 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
81cd07b9
JR		 2703
2704 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2705 &reserved_rbtree_key);
2706
2707 /* MSI memory range */
2708 val = reserve_iova(&reserved_iova_ranges,
2709 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2710 if (!val) {
2711 pr_err("Reserving MSI range failed\n");
2712 return -ENOMEM;
2713 }
2714
2715 /* HT memory range */
2716 val = reserve_iova(&reserved_iova_ranges,
2717 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2718 if (!val) {
2719 pr_err("Reserving HT range failed\n");
2720 return -ENOMEM;
2721 }
2722
2723 /*
2724 * Memory used for PCI resources
2725 * FIXME: Check whether we can reserve the PCI-hole completly
2726 */
2727 for_each_pci_dev(pdev) {
2728 int i;
2729
2730 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2731 struct resource *r = &pdev->resource[i];
2732
2733 if (!(r->flags & IORESOURCE_MEM))
2734 continue;
2735
2736 val = reserve_iova(&reserved_iova_ranges,
2737 IOVA_PFN(r->start),
2738 IOVA_PFN(r->end));
2739 if (!val) {
2740 pr_err("Reserve pci-resource range failed\n");
2741 return -ENOMEM;
2742 }
2743 }
2744 }
2745
2746 return 0;
2747}
2748
3a18404c 2749int __init amd_iommu_init_api(void)
27c2127a 2750{
460c26d0 2751 int ret, err = 0;
307d5851
JR		 2752
2753 ret = iova_cache_get();
2754 if (ret)
2755 return ret;
9a4d3bf5 2756
81cd07b9
JR		 2757 ret = init_reserved_iova_ranges();
2758 if (ret)
2759 return ret;
2760
9a4d3bf5
WZ		 2761 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2762 if (err)
2763 return err;
2764#ifdef CONFIG_ARM_AMBA
2765 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2766 if (err)
2767 return err;
2768#endif
0076cd3d
WZ		 2769 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2770 if (err)
2771 return err;
c5b5da9c 2772
460c26d0 2773 return 0;
f5325094
JR		 2774}
2775
6631ee9d
JR		 2776int __init amd_iommu_init_dma_ops(void)
2777{
aba2d9a6 2778 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
6631ee9d 2779 iommu_detected = 1;
6631ee9d 2780
52717828
JR		 2781 /*
2782 * In case we don't initialize SWIOTLB (actually the common case
aba2d9a6
TL		 2783 * when AMD IOMMU is enabled and SME is not active), make sure there
2784 * are global dma_ops set as a fall-back for devices not handled by
2785 * this driver (for example non-PCI devices). When SME is active,
2786 * make sure that swiotlb variable remains set so the global dma_ops
2787 * continue to be SWIOTLB.
52717828
JR		 2788 */
2789 if (!swiotlb)
fec777c3 2790 dma_ops = &dma_direct_ops;
52717828 2791
62410eeb
JR		 2792 if (amd_iommu_unmap_flush)
2793 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2794 else
2795 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2796
6631ee9d 2797 return 0;
c5b5da9c 2798
6631ee9d 2799}
6d98cd80
JR		 2800
2801/*****************************************************************************
2802 *
2803 * The following functions belong to the exported interface of AMD IOMMU
2804 *
2805 * This interface allows access to lower level functions of the IOMMU
2806 * like protection domain handling and assignement of devices to domains
2807 * which is not possible with the dma_ops interface.
2808 *
2809 *****************************************************************************/
2810
6d98cd80
JR		 2811static void cleanup_domain(struct protection_domain *domain)
2812{
9b29d3c6 2813 struct iommu_dev_data *entry;
6d98cd80 2814 unsigned long flags;
6d98cd80 2815
2cd1083d 2816 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
6d98cd80 2817
9b29d3c6
JR		 2818 while (!list_empty(&domain->dev_list)) {
2819 entry = list_first_entry(&domain->dev_list,
2820 struct iommu_dev_data, list);
ea3fd040 2821 BUG_ON(!entry->domain);
9b29d3c6 2822 __detach_device(entry);
492667da 2823 }
6d98cd80 2824
2cd1083d 2825 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
6d98cd80
JR		 2826}
2827
2650815f
JR		 2828static void protection_domain_free(struct protection_domain *domain)
2829{
2830 if (!domain)
2831 return;
2832
aeb26f55
JR		 2833 del_domain_from_list(domain);
2834
2650815f
JR		 2835 if (domain->id)
2836 domain_id_free(domain->id);
2837
2838 kfree(domain);
2839}
2840
7a5a566e
JR		 2841static int protection_domain_init(struct protection_domain *domain)
2842{
2843 spin_lock_init(&domain->lock);
2844 mutex_init(&domain->api_lock);
2845 domain->id = domain_id_alloc();
2846 if (!domain->id)
2847 return -ENOMEM;
2848 INIT_LIST_HEAD(&domain->dev_list);
2849
2850 return 0;
2851}
2852
2650815f 2853static struct protection_domain *protection_domain_alloc(void)
c156e347
JR		 2854{
2855 struct protection_domain *domain;
2856
2857 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2858 if (!domain)
2650815f 2859 return NULL;
c156e347 2860
7a5a566e 2861 if (protection_domain_init(domain))
2650815f
JR		 2862 goto out_err;
2863
aeb26f55
JR		 2864 add_domain_to_list(domain);
2865
2650815f
JR		 2866 return domain;
2867
2868out_err:
2869 kfree(domain);
2870
2871 return NULL;
2872}
2873
3f4b87b9 2874static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2650815f 2875{
3f4b87b9 2876 struct protection_domain *pdomain;
0bb6e243 2877 struct dma_ops_domain *dma_domain;
2650815f 2878
0bb6e243
JR		 2879 switch (type) {
2880 case IOMMU_DOMAIN_UNMANAGED:
2881 pdomain = protection_domain_alloc();
2882 if (!pdomain)
2883 return NULL;
c156e347 2884
0bb6e243
JR		 2885 pdomain->mode = PAGE_MODE_3_LEVEL;
2886 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2887 if (!pdomain->pt_root) {
2888 protection_domain_free(pdomain);
2889 return NULL;
2890 }
c156e347 2891
0bb6e243
JR		 2892 pdomain->domain.geometry.aperture_start = 0;
2893 pdomain->domain.geometry.aperture_end = ~0ULL;
2894 pdomain->domain.geometry.force_aperture = true;
0ff64f80 2895
0bb6e243
JR		 2896 break;
2897 case IOMMU_DOMAIN_DMA:
2898 dma_domain = dma_ops_domain_alloc();
2899 if (!dma_domain) {
2900 pr_err("AMD-Vi: Failed to allocate\n");
2901 return NULL;
2902 }
2903 pdomain = &dma_domain->domain;
2904 break;
07f643a3
JR		 2905 case IOMMU_DOMAIN_IDENTITY:
2906 pdomain = protection_domain_alloc();
2907 if (!pdomain)
2908 return NULL;
c156e347 2909
07f643a3
JR		 2910 pdomain->mode = PAGE_MODE_NONE;
2911 break;
0bb6e243
JR		 2912 default:
2913 return NULL;
2914 }
c156e347 2915
3f4b87b9 2916 return &pdomain->domain;
c156e347
JR		 2917}
2918
3f4b87b9 2919static void amd_iommu_domain_free(struct iommu_domain *dom)
98383fc3 2920{
3f4b87b9 2921 struct protection_domain *domain;
cda7005b 2922 struct dma_ops_domain *dma_dom;
98383fc3 2923
3f4b87b9
JR		 2924 domain = to_pdomain(dom);
2925
98383fc3
JR		 2926 if (domain->dev_cnt > 0)
2927 cleanup_domain(domain);
2928
2929 BUG_ON(domain->dev_cnt != 0);
2930
cda7005b
JR		 2931 if (!dom)
2932 return;
98383fc3 2933
cda7005b
JR		 2934 switch (dom->type) {
2935 case IOMMU_DOMAIN_DMA:
281e8ccb 2936 /* Now release the domain */
b3311b06 2937 dma_dom = to_dma_ops_domain(domain);
cda7005b
JR		 2938 dma_ops_domain_free(dma_dom);
2939 break;
2940 default:
2941 if (domain->mode != PAGE_MODE_NONE)
2942 free_pagetable(domain);
52815b75 2943
cda7005b
JR		 2944 if (domain->flags & PD_IOMMUV2_MASK)
2945 free_gcr3_table(domain);
2946
2947 protection_domain_free(domain);
2948 break;
2949 }
98383fc3
JR		 2950}
2951
684f2888
JR		 2952static void amd_iommu_detach_device(struct iommu_domain *dom,
2953 struct device *dev)
2954{
657cbb6b 2955 struct iommu_dev_data *dev_data = dev->archdata.iommu;
684f2888 2956 struct amd_iommu *iommu;
7aba6cb9 2957 int devid;
684f2888 2958
98fc5a69 2959 if (!check_device(dev))
684f2888
JR		 2960 return;
2961
98fc5a69 2962 devid = get_device_id(dev);
9ee35e4c 2963 if (devid < 0)
7aba6cb9 2964 return;
684f2888 2965
657cbb6b 2966 if (dev_data->domain != NULL)
15898bbc 2967 detach_device(dev);
684f2888
JR		 2968
2969 iommu = amd_iommu_rlookup_table[devid];
2970 if (!iommu)
2971 return;
2972
d98de49a
SS		 2973#ifdef CONFIG_IRQ_REMAP
2974 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2975 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2976 dev_data->use_vapic = 0;
2977#endif
2978
684f2888
JR		 2979 iommu_completion_wait(iommu);
2980}
2981
01106066
JR		 2982static int amd_iommu_attach_device(struct iommu_domain *dom,
2983 struct device *dev)
2984{
3f4b87b9 2985 struct protection_domain *domain = to_pdomain(dom);
657cbb6b 2986 struct iommu_dev_data *dev_data;
01106066 2987 struct amd_iommu *iommu;
15898bbc 2988 int ret;
01106066 2989
98fc5a69 2990 if (!check_device(dev))
01106066
JR		 2991 return -EINVAL;
2992
657cbb6b
JR		 2993 dev_data = dev->archdata.iommu;
2994
f62dda66 2995 iommu = amd_iommu_rlookup_table[dev_data->devid];
01106066
JR		 2996 if (!iommu)
2997 return -EINVAL;
2998
657cbb6b 2999 if (dev_data->domain)
15898bbc 3000 detach_device(dev);
01106066 3001
15898bbc 3002 ret = attach_device(dev, domain);
01106066 3003
d98de49a
SS		 3004#ifdef CONFIG_IRQ_REMAP
3005 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3006 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3007 dev_data->use_vapic = 1;
3008 else
3009 dev_data->use_vapic = 0;
3010 }
3011#endif
3012
01106066
JR		 3013 iommu_completion_wait(iommu);
3014
15898bbc 3015 return ret;
01106066
JR		 3016}
3017
468e2366 3018static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
5009065d 3019 phys_addr_t paddr, size_t page_size, int iommu_prot)
c6229ca6 3020{
3f4b87b9 3021 struct protection_domain *domain = to_pdomain(dom);
c6229ca6
JR		 3022 int prot = 0;
3023 int ret;
3024
132bd68f
JR		 3025 if (domain->mode == PAGE_MODE_NONE)
3026 return -EINVAL;
3027
c6229ca6
JR		 3028 if (iommu_prot & IOMMU_READ)
3029 prot |= IOMMU_PROT_IR;
3030 if (iommu_prot & IOMMU_WRITE)
3031 prot |= IOMMU_PROT_IW;
3032
5d214fe6 3033 mutex_lock(&domain->api_lock);
b911b89b 3034 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
5d214fe6
JR		 3035 mutex_unlock(&domain->api_lock);
3036
795e74f7 3037 return ret;
c6229ca6
JR		 3038}
3039
5009065d
OBC		 3040static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3041 size_t page_size)
eb74ff6c 3042{
3f4b87b9 3043 struct protection_domain *domain = to_pdomain(dom);
5009065d 3044 size_t unmap_size;
eb74ff6c 3045
132bd68f 3046 if (domain->mode == PAGE_MODE_NONE)
c5611a87 3047 return 0;
132bd68f 3048
5d214fe6 3049 mutex_lock(&domain->api_lock);
468e2366 3050 unmap_size = iommu_unmap_page(domain, iova, page_size);
795e74f7 3051 mutex_unlock(&domain->api_lock);
eb74ff6c 3052
5009065d 3053 return unmap_size;
eb74ff6c
JR		 3054}
3055
645c4c8d 3056static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
bb5547ac 3057 dma_addr_t iova)
645c4c8d 3058{
3f4b87b9 3059 struct protection_domain *domain = to_pdomain(dom);
3039ca1b 3060 unsigned long offset_mask, pte_pgsize;
f03152bb 3061 u64 *pte, __pte;
645c4c8d 3062
132bd68f
JR		 3063 if (domain->mode == PAGE_MODE_NONE)
3064 return iova;
3065
3039ca1b 3066 pte = fetch_pte(domain, iova, &pte_pgsize);
645c4c8d 3067
a6d41a40 3068 if (!pte || !IOMMU_PTE_PRESENT(*pte))
645c4c8d
JR		 3069 return 0;
3070
b24b1b63 3071 offset_mask = pte_pgsize - 1;
b3e9b515 3072 __pte = __sme_clr(*pte & PM_ADDR_MASK);
645c4c8d 3073
b24b1b63 3074 return (__pte & ~offset_mask) | (iova & offset_mask);
645c4c8d
JR		 3075}
3076
ab636481 3077static bool amd_iommu_capable(enum iommu_cap cap)
dbb9fd86 3078{
80a506b8
JR		 3079 switch (cap) {
3080 case IOMMU_CAP_CACHE_COHERENCY:
ab636481 3081 return true;
bdddadcb 3082 case IOMMU_CAP_INTR_REMAP:
ab636481 3083 return (irq_remapping_enabled == 1);
cfdeec22
WD		 3084 case IOMMU_CAP_NOEXEC:
3085 return false;
e84b7cc4
LB		 3086 default:
3087 break;
80a506b8
JR		 3088 }
3089
ab636481 3090 return false;
dbb9fd86
SY		 3091}
3092
e5b5234a
EA		 3093static void amd_iommu_get_resv_regions(struct device *dev,
3094 struct list_head *head)
35cf248f 3095{
4397f32c 3096 struct iommu_resv_region *region;
35cf248f 3097 struct unity_map_entry *entry;
7aba6cb9 3098 int devid;
35cf248f
JR		 3099
3100 devid = get_device_id(dev);
9ee35e4c 3101 if (devid < 0)
7aba6cb9 3102 return;
35cf248f
JR		 3103
3104 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
4397f32c
EA		 3105 size_t length;
3106 int prot = 0;
35cf248f
JR		 3107
3108 if (devid < entry->devid_start || devid > entry->devid_end)
3109 continue;
3110
4397f32c
EA		 3111 length = entry->address_end - entry->address_start;
3112 if (entry->prot & IOMMU_PROT_IR)
3113 prot |= IOMMU_READ;
3114 if (entry->prot & IOMMU_PROT_IW)
3115 prot |= IOMMU_WRITE;
3116
3117 region = iommu_alloc_resv_region(entry->address_start,
3118 length, prot,
3119 IOMMU_RESV_DIRECT);
35cf248f
JR		 3120 if (!region) {
3121 pr_err("Out of memory allocating dm-regions for %s\n",
3122 dev_name(dev));
3123 return;
3124 }
35cf248f
JR		 3125 list_add_tail(&region->list, head);
3126 }
4397f32c
EA		 3127
3128 region = iommu_alloc_resv_region(MSI_RANGE_START,
3129 MSI_RANGE_END - MSI_RANGE_START + 1,
9d3a4de4 3130 0, IOMMU_RESV_MSI);
4397f32c
EA		 3131 if (!region)
3132 return;
3133 list_add_tail(&region->list, head);
3134
3135 region = iommu_alloc_resv_region(HT_RANGE_START,
3136 HT_RANGE_END - HT_RANGE_START + 1,
3137 0, IOMMU_RESV_RESERVED);
3138 if (!region)
3139 return;
3140 list_add_tail(&region->list, head);
35cf248f
JR		 3141}
3142
e5b5234a 3143static void amd_iommu_put_resv_regions(struct device *dev,
35cf248f
JR		 3144 struct list_head *head)
3145{
e5b5234a 3146 struct iommu_resv_region *entry, *next;
35cf248f
JR		 3147
3148 list_for_each_entry_safe(entry, next, head, list)
3149 kfree(entry);
3150}
3151
e5b5234a 3152static void amd_iommu_apply_resv_region(struct device *dev,
8d54d6c8 3153 struct iommu_domain *domain,
e5b5234a 3154 struct iommu_resv_region *region)
8d54d6c8 3155{
b3311b06 3156 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
8d54d6c8
JR		 3157 unsigned long start, end;
3158
3159 start = IOVA_PFN(region->start);
b92b4fb5 3160 end = IOVA_PFN(region->start + region->length - 1);
8d54d6c8
JR		 3161
3162 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3163}
3164
df3f7a6e
BH		 3165static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3166 struct device *dev)
3167{
3168 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3169 return dev_data->defer_attach;
3170}
3171
eb5ecd1a
SS		 3172static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3173{
3174 struct protection_domain *dom = to_pdomain(domain);
3175
3176 domain_flush_tlb_pde(dom);
3177 domain_flush_complete(dom);
3178}
3179
3180static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3181 unsigned long iova, size_t size)
3182{
3183}
3184
b0119e87 3185const struct iommu_ops amd_iommu_ops = {
ab636481 3186 .capable = amd_iommu_capable,
3f4b87b9
JR		 3187 .domain_alloc = amd_iommu_domain_alloc,
3188 .domain_free = amd_iommu_domain_free,
26961efe
JR		 3189 .attach_dev = amd_iommu_attach_device,
3190 .detach_dev = amd_iommu_detach_device,
468e2366
JR		 3191 .map = amd_iommu_map,
3192 .unmap = amd_iommu_unmap,
26961efe 3193 .iova_to_phys = amd_iommu_iova_to_phys,
aafd8ba0
JR		 3194 .add_device = amd_iommu_add_device,
3195 .remove_device = amd_iommu_remove_device,
b097d11a 3196 .device_group = amd_iommu_device_group,
e5b5234a
EA		 3197 .get_resv_regions = amd_iommu_get_resv_regions,
3198 .put_resv_regions = amd_iommu_put_resv_regions,
3199 .apply_resv_region = amd_iommu_apply_resv_region,
df3f7a6e 3200 .is_attach_deferred = amd_iommu_is_attach_deferred,
aa3de9c0 3201 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
eb5ecd1a
SS		 3202 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3203 .iotlb_range_add = amd_iommu_iotlb_range_add,
3204 .iotlb_sync = amd_iommu_flush_iotlb_all,
26961efe
JR		 3205};
3206
0feae533
JR		 3207/*****************************************************************************
3208 *
3209 * The next functions do a basic initialization of IOMMU for pass through
3210 * mode
3211 *
3212 * In passthrough mode the IOMMU is initialized and enabled but not used for
3213 * DMA-API translation.
3214 *
3215 *****************************************************************************/
3216
72e1dcc4
JR		 3217/* IOMMUv2 specific functions */
3218int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3219{
3220 return atomic_notifier_chain_register(&ppr_notifier, nb);
3221}
3222EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3223
3224int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3225{
3226 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3227}
3228EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
132bd68f
JR		 3229
3230void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3231{
3f4b87b9 3232 struct protection_domain *domain = to_pdomain(dom);
132bd68f
JR		 3233 unsigned long flags;
3234
3235 spin_lock_irqsave(&domain->lock, flags);
3236
3237 /* Update data structure */
3238 domain->mode = PAGE_MODE_NONE;
3239 domain->updated = true;
3240
3241 /* Make changes visible to IOMMUs */
3242 update_domain(domain);
3243
3244 /* Page-table is not visible to IOMMU anymore, so free it */
3245 free_pagetable(domain);
3246
3247 spin_unlock_irqrestore(&domain->lock, flags);
3248}
3249EXPORT_SYMBOL(amd_iommu_domain_direct_map);
52815b75
JR		 3250
3251int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3252{
3f4b87b9 3253 struct protection_domain *domain = to_pdomain(dom);
52815b75
JR		 3254 unsigned long flags;
3255 int levels, ret;
3256
3257 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3258 return -EINVAL;
3259
3260 /* Number of GCR3 table levels required */
3261 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3262 levels += 1;
3263
3264 if (levels > amd_iommu_max_glx_val)
3265 return -EINVAL;
3266
3267 spin_lock_irqsave(&domain->lock, flags);
3268
3269 /*
3270 * Save us all sanity checks whether devices already in the
3271 * domain support IOMMUv2. Just force that the domain has no
3272 * devices attached when it is switched into IOMMUv2 mode.
3273 */
3274 ret = -EBUSY;
3275 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3276 goto out;
3277
3278 ret = -ENOMEM;
3279 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3280 if (domain->gcr3_tbl == NULL)
3281 goto out;
3282
3283 domain->glx = levels;
3284 domain->flags |= PD_IOMMUV2_MASK;
3285 domain->updated = true;
3286
3287 update_domain(domain);
3288
3289 ret = 0;
3290
3291out:
3292 spin_unlock_irqrestore(&domain->lock, flags);
3293
3294 return ret;
3295}
3296EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
22e266c7
JR		 3297
3298static int __flush_pasid(struct protection_domain *domain, int pasid,
3299 u64 address, bool size)
3300{
3301 struct iommu_dev_data *dev_data;
3302 struct iommu_cmd cmd;
3303 int i, ret;
3304
3305 if (!(domain->flags & PD_IOMMUV2_MASK))
3306 return -EINVAL;
3307
3308 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3309
3310 /*
3311 * IOMMU TLB needs to be flushed before Device TLB to
3312 * prevent device TLB refill from IOMMU TLB
3313 */
6b9376e3 3314 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
22e266c7
JR		 3315 if (domain->dev_iommu[i] == 0)
3316 continue;
3317
3318 ret = iommu_queue_command(amd_iommus[i], &cmd);
3319 if (ret != 0)
3320 goto out;
3321 }
3322
3323 /* Wait until IOMMU TLB flushes are complete */
3324 domain_flush_complete(domain);
3325
3326 /* Now flush device TLBs */
3327 list_for_each_entry(dev_data, &domain->dev_list, list) {
3328 struct amd_iommu *iommu;
3329 int qdep;
3330
1c1cc454
JR		 3331 /*
3332 There might be non-IOMMUv2 capable devices in an IOMMUv2
3333 * domain.
3334 */
3335 if (!dev_data->ats.enabled)
3336 continue;
22e266c7
JR		 3337
3338 qdep = dev_data->ats.qdep;
3339 iommu = amd_iommu_rlookup_table[dev_data->devid];
3340
3341 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3342 qdep, address, size);
3343
3344 ret = iommu_queue_command(iommu, &cmd);
3345 if (ret != 0)
3346 goto out;
3347 }
3348
3349 /* Wait until all device TLBs are flushed */
3350 domain_flush_complete(domain);
3351
3352 ret = 0;
3353
3354out:
3355
3356 return ret;
3357}
3358
3359static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3360 u64 address)
3361{
3362 return __flush_pasid(domain, pasid, address, false);
3363}
3364
3365int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3366 u64 address)
3367{
3f4b87b9 3368 struct protection_domain *domain = to_pdomain(dom);
22e266c7
JR		 3369 unsigned long flags;
3370 int ret;
3371
3372 spin_lock_irqsave(&domain->lock, flags);
3373 ret = __amd_iommu_flush_page(domain, pasid, address);
3374 spin_unlock_irqrestore(&domain->lock, flags);
3375
3376 return ret;
3377}
3378EXPORT_SYMBOL(amd_iommu_flush_page);
3379
3380static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3381{
3382 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3383 true);
3384}
3385
3386int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3387{
3f4b87b9 3388 struct protection_domain *domain = to_pdomain(dom);
22e266c7
JR		 3389 unsigned long flags;
3390 int ret;
3391
3392 spin_lock_irqsave(&domain->lock, flags);
3393 ret = __amd_iommu_flush_tlb(domain, pasid);
3394 spin_unlock_irqrestore(&domain->lock, flags);
3395
3396 return ret;
3397}
3398EXPORT_SYMBOL(amd_iommu_flush_tlb);
3399
b16137b1
JR		 3400static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3401{
3402 int index;
3403 u64 *pte;
3404
3405 while (true) {
3406
3407 index = (pasid >> (9 * level)) & 0x1ff;
3408 pte = &root[index];
3409
3410 if (level == 0)
3411 break;
3412
3413 if (!(*pte & GCR3_VALID)) {
3414 if (!alloc)
3415 return NULL;
3416
3417 root = (void *)get_zeroed_page(GFP_ATOMIC);
3418 if (root == NULL)
3419 return NULL;
3420
2543a786 3421 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
b16137b1
JR		 3422 }
3423
2543a786 3424 root = iommu_phys_to_virt(*pte & PAGE_MASK);
b16137b1
JR		 3425
3426 level -= 1;
3427 }
3428
3429 return pte;
3430}
3431
3432static int __set_gcr3(struct protection_domain *domain, int pasid,
3433 unsigned long cr3)
3434{
3435 u64 *pte;
3436
3437 if (domain->mode != PAGE_MODE_NONE)
3438 return -EINVAL;
3439
3440 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3441 if (pte == NULL)
3442 return -ENOMEM;
3443
3444 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3445
3446 return __amd_iommu_flush_tlb(domain, pasid);
3447}
3448
3449static int __clear_gcr3(struct protection_domain *domain, int pasid)
3450{
3451 u64 *pte;
3452
3453 if (domain->mode != PAGE_MODE_NONE)
3454 return -EINVAL;
3455
3456 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3457 if (pte == NULL)
3458 return 0;
3459
3460 *pte = 0;
3461
3462 return __amd_iommu_flush_tlb(domain, pasid);
3463}
3464
3465int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3466 unsigned long cr3)
3467{
3f4b87b9 3468 struct protection_domain *domain = to_pdomain(dom);
b16137b1
JR		 3469 unsigned long flags;
3470 int ret;
3471
3472 spin_lock_irqsave(&domain->lock, flags);
3473 ret = __set_gcr3(domain, pasid, cr3);
3474 spin_unlock_irqrestore(&domain->lock, flags);
3475
3476 return ret;
3477}
3478EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3479
3480int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3481{
3f4b87b9 3482 struct protection_domain *domain = to_pdomain(dom);
b16137b1
JR		 3483 unsigned long flags;
3484 int ret;
3485
3486 spin_lock_irqsave(&domain->lock, flags);
3487 ret = __clear_gcr3(domain, pasid);
3488 spin_unlock_irqrestore(&domain->lock, flags);
3489
3490 return ret;
3491}
3492EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
c99afa25
JR		 3493
3494int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3495 int status, int tag)
3496{
3497 struct iommu_dev_data *dev_data;
3498 struct amd_iommu *iommu;
3499 struct iommu_cmd cmd;
3500
3501 dev_data = get_dev_data(&pdev->dev);
3502 iommu = amd_iommu_rlookup_table[dev_data->devid];
3503
3504 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3505 tag, dev_data->pri_tlp);
3506
3507 return iommu_queue_command(iommu, &cmd);
3508}
3509EXPORT_SYMBOL(amd_iommu_complete_ppr);
f3572db8
JR		 3510
3511struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3512{
3f4b87b9 3513 struct protection_domain *pdomain;
f3572db8 3514
3f4b87b9
JR		 3515 pdomain = get_domain(&pdev->dev);
3516 if (IS_ERR(pdomain))
f3572db8
JR		 3517 return NULL;
3518
3519 /* Only return IOMMUv2 domains */
3f4b87b9 3520 if (!(pdomain->flags & PD_IOMMUV2_MASK))
f3572db8
JR		 3521 return NULL;
3522
3f4b87b9 3523 return &pdomain->domain;
f3572db8
JR		 3524}
3525EXPORT_SYMBOL(amd_iommu_get_v2_domain);
6a113ddc
JR		 3526
3527void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3528{
3529 struct iommu_dev_data *dev_data;
3530
3531 if (!amd_iommu_v2_supported())
3532 return;
3533
3534 dev_data = get_dev_data(&pdev->dev);
3535 dev_data->errata |= (1 << erratum);
3536}
3537EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
52efdb89
JR		 3538
3539int amd_iommu_device_info(struct pci_dev *pdev,
3540 struct amd_iommu_device_info *info)
3541{
3542 int max_pasids;
3543 int pos;
3544
3545 if (pdev == NULL || info == NULL)
3546 return -EINVAL;
3547
3548 if (!amd_iommu_v2_supported())
3549 return -EINVAL;
3550
3551 memset(info, 0, sizeof(*info));
3552
cef74409
GK		 3553 if (!pci_ats_disabled()) {
3554 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3555 if (pos)
3556 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3557 }
52efdb89
JR		 3558
3559 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3560 if (pos)
3561 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3562
3563 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3564 if (pos) {
3565 int features;
3566
3567 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3568 max_pasids = min(max_pasids, (1 << 20));
3569
3570 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3571 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3572
3573 features = pci_pasid_features(pdev);
3574 if (features & PCI_PASID_CAP_EXEC)
3575 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3576 if (features & PCI_PASID_CAP_PRIV)
3577 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3578 }
3579
3580 return 0;
3581}
3582EXPORT_SYMBOL(amd_iommu_device_info);
2b324506
JR		 3583
3584#ifdef CONFIG_IRQ_REMAP
3585
3586/*****************************************************************************
3587 *
3588 * Interrupt Remapping Implementation
3589 *
3590 *****************************************************************************/
3591
7c71d306 3592static struct irq_chip amd_ir_chip;
94c793ac 3593static DEFINE_SPINLOCK(iommu_table_lock);
7c71d306 3594
2b324506
JR		 3595static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3596{
3597 u64 dte;
3598
3599 dte = amd_iommu_dev_table[devid].data[2];
3600 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
2543a786 3601 dte |= iommu_virt_to_phys(table->table);
2b324506
JR		 3602 dte |= DTE_IRQ_REMAP_INTCTL;
3603 dte |= DTE_IRQ_TABLE_LEN;
3604 dte |= DTE_IRQ_REMAP_ENABLE;
3605
3606 amd_iommu_dev_table[devid].data[2] = dte;
3607}
3608
df42a04b
SW		 3609static struct irq_remap_table *get_irq_table(u16 devid)
3610{
3611 struct irq_remap_table *table;
3612
3613 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3614 "%s: no iommu for devid %x\n", __func__, devid))
3615 return NULL;
3616
3617 table = irq_lookup_table[devid];
3618 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3619 return NULL;
3620
3621 return table;
3622}
3623
993ca6e0
SAS		 3624static struct irq_remap_table *__alloc_irq_table(void)
3625{
3626 struct irq_remap_table *table;
3627
3628 table = kzalloc(sizeof(*table), GFP_KERNEL);
3629 if (!table)
3630 return NULL;
3631
3632 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3633 if (!table->table) {
3634 kfree(table);
3635 return NULL;
3636 }
3637 raw_spin_lock_init(&table->lock);
3638
3639 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3640 memset(table->table, 0,
3641 MAX_IRQS_PER_TABLE * sizeof(u32));
3642 else
3643 memset(table->table, 0,
3644 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3645 return table;
3646}
3647
2fcc1e8a
SAS		 3648static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3649 struct irq_remap_table *table)
3650{
3651 irq_lookup_table[devid] = table;
3652 set_dte_irq_entry(devid, table);
3653 iommu_flush_dte(iommu, devid);
3654}
3655
fde65dd3 3656static struct irq_remap_table *alloc_irq_table(u16 devid)
2b324506
JR		 3657{
3658 struct irq_remap_table *table = NULL;
993ca6e0 3659 struct irq_remap_table *new_table = NULL;
2b324506
JR		 3660 struct amd_iommu *iommu;
3661 unsigned long flags;
3662 u16 alias;
3663
ea6166f4 3664 spin_lock_irqsave(&iommu_table_lock, flags);
2b324506
JR		 3665
3666 iommu = amd_iommu_rlookup_table[devid];
3667 if (!iommu)
3668 goto out_unlock;
3669
3670 table = irq_lookup_table[devid];
3671 if (table)
09284b9c 3672 goto out_unlock;
2b324506
JR		 3673
3674 alias = amd_iommu_alias_table[devid];
3675 table = irq_lookup_table[alias];
3676 if (table) {
2fcc1e8a 3677 set_remap_table_entry(iommu, devid, table);
993ca6e0 3678 goto out_wait;
2b324506 3679 }
993ca6e0 3680 spin_unlock_irqrestore(&iommu_table_lock, flags);
2b324506
JR		 3681
3682 /* Nothing there yet, allocate new irq remapping table */
993ca6e0
SAS		 3683 new_table = __alloc_irq_table();
3684 if (!new_table)
3685 return NULL;
197887f0 3686
993ca6e0 3687 spin_lock_irqsave(&iommu_table_lock, flags);
2b324506 3688
993ca6e0
SAS		 3689 table = irq_lookup_table[devid];
3690 if (table)
09284b9c 3691 goto out_unlock;
2b324506 3692
993ca6e0
SAS		 3693 table = irq_lookup_table[alias];
3694 if (table) {
3695 set_remap_table_entry(iommu, devid, table);
3696 goto out_wait;
2b324506
JR		 3697 }
3698
993ca6e0
SAS		 3699 table = new_table;
3700 new_table = NULL;
2b324506 3701
2fcc1e8a
SAS		 3702 set_remap_table_entry(iommu, devid, table);
3703 if (devid != alias)
3704 set_remap_table_entry(iommu, alias, table);
2b324506 3705
993ca6e0 3706out_wait:
2b324506
JR		 3707 iommu_completion_wait(iommu);
3708
3709out_unlock:
ea6166f4 3710 spin_unlock_irqrestore(&iommu_table_lock, flags);
2b324506 3711
993ca6e0
SAS		 3712 if (new_table) {
3713 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3714 kfree(new_table);
3715 }
2b324506
JR		 3716 return table;
3717}
3718
37946d95 3719static int alloc_irq_index(u16 devid, int count, bool align)
2b324506
JR		 3720{
3721 struct irq_remap_table *table;
37946d95 3722 int index, c, alignment = 1;
2b324506 3723 unsigned long flags;
77bdab46
SS		 3724 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3725
3726 if (!iommu)
3727 return -ENODEV;
2b324506 3728
fde65dd3 3729 table = alloc_irq_table(devid);
2b324506
JR		 3730 if (!table)
3731 return -ENODEV;
3732
37946d95
JR		 3733 if (align)
3734 alignment = roundup_pow_of_two(count);
3735
27790398 3736 raw_spin_lock_irqsave(&table->lock, flags);
2b324506
JR		 3737
3738 /* Scan table for free entries */
37946d95 3739 for (index = ALIGN(table->min_index, alignment), c = 0;
07d1c91b 3740 index < MAX_IRQS_PER_TABLE;) {
37946d95 3741 if (!iommu->irte_ops->is_allocated(table, index)) {
2b324506 3742 c += 1;
37946d95
JR		 3743 } else {
3744 c = 0;
07d1c91b 3745 index = ALIGN(index + 1, alignment);
37946d95
JR		 3746 continue;
3747 }
2b324506
JR		 3748
3749 if (c == count) {
2b324506 3750 for (; c != 0; --c)
77bdab46 3751 iommu->irte_ops->set_allocated(table, index - c + 1);
2b324506
JR		 3752
3753 index -= count - 1;
2b324506
JR		 3754 goto out;
3755 }
07d1c91b
AW		 3756
3757 index++;
2b324506
JR		 3758 }
3759
3760 index = -ENOSPC;
3761
3762out:
27790398 3763 raw_spin_unlock_irqrestore(&table->lock, flags);
2b324506
JR		 3764
3765 return index;
3766}
3767
b9fc6b56
SS		 3768static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3769 struct amd_ir_data *data)
2b324506
JR		 3770{
3771 struct irq_remap_table *table;
3772 struct amd_iommu *iommu;
3773 unsigned long flags;
880ac60e 3774 struct irte_ga *entry;
2b324506
JR		 3775
3776 iommu = amd_iommu_rlookup_table[devid];
3777 if (iommu == NULL)
3778 return -EINVAL;
3779
df42a04b 3780 table = get_irq_table(devid);
2b324506
JR		 3781 if (!table)
3782 return -ENOMEM;
3783
27790398 3784 raw_spin_lock_irqsave(&table->lock, flags);
880ac60e
SS		 3785
3786 entry = (struct irte_ga *)table->table;
3787 entry = &entry[index];
3788 entry->lo.fields_remap.valid = 0;
3789 entry->hi.val = irte->hi.val;
3790 entry->lo.val = irte->lo.val;
3791 entry->lo.fields_remap.valid = 1;
b9fc6b56
SS		 3792 if (data)
3793 data->ref = entry;
880ac60e 3794
27790398 3795 raw_spin_unlock_irqrestore(&table->lock, flags);
880ac60e
SS		 3796
3797 iommu_flush_irt(iommu, devid);
3798 iommu_completion_wait(iommu);
3799
3800 return 0;
3801}
3802
3803static int modify_irte(u16 devid, int index, union irte *irte)
2b324506
JR		 3804{
3805 struct irq_remap_table *table;
3806 struct amd_iommu *iommu;
3807 unsigned long flags;
3808
3809 iommu = amd_iommu_rlookup_table[devid];
3810 if (iommu == NULL)
3811 return -EINVAL;
3812
df42a04b 3813 table = get_irq_table(devid);
2b324506
JR		 3814 if (!table)
3815 return -ENOMEM;
3816
27790398 3817 raw_spin_lock_irqsave(&table->lock, flags);
880ac60e 3818 table->table[index] = irte->val;
27790398 3819 raw_spin_unlock_irqrestore(&table->lock, flags);
2b324506
JR		 3820
3821 iommu_flush_irt(iommu, devid);
3822 iommu_completion_wait(iommu);
3823
3824 return 0;
3825}
3826
3827static void free_irte(u16 devid, int index)
3828{
3829 struct irq_remap_table *table;
3830 struct amd_iommu *iommu;
3831 unsigned long flags;
3832
3833 iommu = amd_iommu_rlookup_table[devid];
3834 if (iommu == NULL)
3835 return;
3836
df42a04b 3837 table = get_irq_table(devid);
2b324506
JR		 3838 if (!table)
3839 return;
3840
27790398 3841 raw_spin_lock_irqsave(&table->lock, flags);
77bdab46 3842 iommu->irte_ops->clear_allocated(table, index);
27790398 3843 raw_spin_unlock_irqrestore(&table->lock, flags);
2b324506
JR		 3844
3845 iommu_flush_irt(iommu, devid);
3846 iommu_completion_wait(iommu);
3847}
3848
880ac60e
SS		 3849static void irte_prepare(void *entry,
3850 u32 delivery_mode, u32 dest_mode,
d98de49a 3851 u8 vector, u32 dest_apicid, int devid)
880ac60e
SS		 3852{
3853 union irte *irte = (union irte *) entry;
3854
3855 irte->val = 0;
3856 irte->fields.vector = vector;
3857 irte->fields.int_type = delivery_mode;
3858 irte->fields.destination = dest_apicid;
3859 irte->fields.dm = dest_mode;
3860 irte->fields.valid = 1;
3861}
3862
3863static void irte_ga_prepare(void *entry,
3864 u32 delivery_mode, u32 dest_mode,
d98de49a 3865 u8 vector, u32 dest_apicid, int devid)
880ac60e
SS		 3866{
3867 struct irte_ga *irte = (struct irte_ga *) entry;
3868
3869 irte->lo.val = 0;
3870 irte->hi.val = 0;
880ac60e
SS		 3871 irte->lo.fields_remap.int_type = delivery_mode;
3872 irte->lo.fields_remap.dm = dest_mode;
3873 irte->hi.fields.vector = vector;
90fcffd9
SS		 3874 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3875 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
880ac60e
SS		 3876 irte->lo.fields_remap.valid = 1;
3877}
3878
3879static void irte_activate(void *entry, u16 devid, u16 index)
3880{
3881 union irte *irte = (union irte *) entry;
3882
3883 irte->fields.valid = 1;
3884 modify_irte(devid, index, irte);
3885}
3886
3887static void irte_ga_activate(void *entry, u16 devid, u16 index)
3888{
3889 struct irte_ga *irte = (struct irte_ga *) entry;
3890
3891 irte->lo.fields_remap.valid = 1;
b9fc6b56 3892 modify_irte_ga(devid, index, irte, NULL);
880ac60e
SS		 3893}
3894
3895static void irte_deactivate(void *entry, u16 devid, u16 index)
3896{
3897 union irte *irte = (union irte *) entry;
3898
3899 irte->fields.valid = 0;
3900 modify_irte(devid, index, irte);
3901}
3902
3903static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3904{
3905 struct irte_ga *irte = (struct irte_ga *) entry;
3906
3907 irte->lo.fields_remap.valid = 0;
b9fc6b56 3908 modify_irte_ga(devid, index, irte, NULL);
880ac60e
SS		 3909}
3910
3911static void irte_set_affinity(void *entry, u16 devid, u16 index,
3912 u8 vector, u32 dest_apicid)
3913{
3914 union irte *irte = (union irte *) entry;
3915
3916 irte->fields.vector = vector;
3917 irte->fields.destination = dest_apicid;
3918 modify_irte(devid, index, irte);
3919}
3920
3921static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3922 u8 vector, u32 dest_apicid)
3923{
3924 struct irte_ga *irte = (struct irte_ga *) entry;
3925
01ee04ba 3926 if (!irte->lo.fields_remap.guest_mode) {
d98de49a 3927 irte->hi.fields.vector = vector;
90fcffd9
SS		 3928 irte->lo.fields_remap.destination =
3929 APICID_TO_IRTE_DEST_LO(dest_apicid);
3930 irte->hi.fields.destination =
3931 APICID_TO_IRTE_DEST_HI(dest_apicid);
d98de49a
SS		 3932 modify_irte_ga(devid, index, irte, NULL);
3933 }
880ac60e
SS		 3934}
3935
77bdab46 3936#define IRTE_ALLOCATED (~1U)
880ac60e
SS		 3937static void irte_set_allocated(struct irq_remap_table *table, int index)
3938{
3939 table->table[index] = IRTE_ALLOCATED;
3940}
3941
3942static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3943{
3944 struct irte_ga *ptr = (struct irte_ga *)table->table;
3945 struct irte_ga *irte = &ptr[index];
3946
3947 memset(&irte->lo.val, 0, sizeof(u64));
3948 memset(&irte->hi.val, 0, sizeof(u64));
3949 irte->hi.fields.vector = 0xff;
3950}
3951
3952static bool irte_is_allocated(struct irq_remap_table *table, int index)
3953{
3954 union irte *ptr = (union irte *)table->table;
3955 union irte *irte = &ptr[index];
3956
3957 return irte->val != 0;
3958}
3959
3960static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3961{
3962 struct irte_ga *ptr = (struct irte_ga *)table->table;
3963 struct irte_ga *irte = &ptr[index];
3964
3965 return irte->hi.fields.vector != 0;
3966}
3967
3968static void irte_clear_allocated(struct irq_remap_table *table, int index)
3969{
3970 table->table[index] = 0;
3971}
3972
3973static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3974{
3975 struct irte_ga *ptr = (struct irte_ga *)table->table;
3976 struct irte_ga *irte = &ptr[index];
3977
3978 memset(&irte->lo.val, 0, sizeof(u64));
3979 memset(&irte->hi.val, 0, sizeof(u64));
3980}
3981
7c71d306 3982static int get_devid(struct irq_alloc_info *info)
5527de74 3983{
7c71d306 3984 int devid = -1;
5527de74 3985
7c71d306
JL		 3986 switch (info->type) {
3987 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3988 devid = get_ioapic_devid(info->ioapic_id);
3989 break;
3990 case X86_IRQ_ALLOC_TYPE_HPET:
3991 devid = get_hpet_devid(info->hpet_id);
3992 break;
3993 case X86_IRQ_ALLOC_TYPE_MSI:
3994 case X86_IRQ_ALLOC_TYPE_MSIX:
3995 devid = get_device_id(&info->msi_dev->dev);
3996 break;
3997 default:
3998 BUG_ON(1);
3999 break;
4000 }
5527de74 4001
7c71d306
JL		 4002 return devid;
4003}
5527de74 4004
7c71d306
JL		 4005static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4006{
4007 struct amd_iommu *iommu;
4008 int devid;
5527de74 4009
7c71d306
JL		 4010 if (!info)
4011 return NULL;
5527de74 4012
7c71d306
JL		 4013 devid = get_devid(info);
4014 if (devid >= 0) {
4015 iommu = amd_iommu_rlookup_table[devid];
4016 if (iommu)
4017 return iommu->ir_domain;
4018 }
5527de74 4019
7c71d306 4020 return NULL;
5527de74
JR		 4021}
4022
7c71d306 4023static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
5527de74 4024{
7c71d306
JL		 4025 struct amd_iommu *iommu;
4026 int devid;
5527de74 4027
7c71d306
JL		 4028 if (!info)
4029 return NULL;
5527de74 4030
7c71d306
JL		 4031 switch (info->type) {
4032 case X86_IRQ_ALLOC_TYPE_MSI:
4033 case X86_IRQ_ALLOC_TYPE_MSIX:
4034 devid = get_device_id(&info->msi_dev->dev);
9ee35e4c 4035 if (devid < 0)
7aba6cb9
WZ		 4036 return NULL;
4037
1fb260bc
DC		 4038 iommu = amd_iommu_rlookup_table[devid];
4039 if (iommu)
4040 return iommu->msi_domain;
7c71d306
JL		 4041 break;
4042 default:
4043 break;
4044 }
5527de74 4045
7c71d306
JL		 4046 return NULL;
4047}
5527de74 4048
6b474b82 4049struct irq_remap_ops amd_iommu_irq_ops = {
6b474b82
JR		 4050 .prepare = amd_iommu_prepare,
4051 .enable = amd_iommu_enable,
4052 .disable = amd_iommu_disable,
4053 .reenable = amd_iommu_reenable,
4054 .enable_faulting = amd_iommu_enable_faulting,
7c71d306
JL		 4055 .get_ir_irq_domain = get_ir_irq_domain,
4056 .get_irq_domain = get_irq_domain,
4057};
5527de74 4058
7c71d306
JL		 4059static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4060 struct irq_cfg *irq_cfg,
4061 struct irq_alloc_info *info,
4062 int devid, int index, int sub_handle)
4063{
4064 struct irq_2_irte *irte_info = &data->irq_2_irte;
4065 struct msi_msg *msg = &data->msi_entry;
7c71d306 4066 struct IO_APIC_route_entry *entry;
77bdab46
SS		 4067 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4068
4069 if (!iommu)
4070 return;
5527de74 4071
7c71d306
JL		 4072 data->irq_2_irte.devid = devid;
4073 data->irq_2_irte.index = index + sub_handle;
77bdab46
SS		 4074 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4075 apic->irq_dest_mode, irq_cfg->vector,
d98de49a 4076 irq_cfg->dest_apicid, devid);
7c71d306
JL		 4077
4078 switch (info->type) {
4079 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4080 /* Setup IOAPIC entry */
4081 entry = info->ioapic_entry;
4082 info->ioapic_entry = NULL;
4083 memset(entry, 0, sizeof(*entry));
4084 entry->vector = index;
4085 entry->mask = 0;
4086 entry->trigger = info->ioapic_trigger;
4087 entry->polarity = info->ioapic_polarity;
4088 /* Mask level triggered irqs. */
4089 if (info->ioapic_trigger)
4090 entry->mask = 1;
4091 break;
5527de74 4092
7c71d306
JL		 4093 case X86_IRQ_ALLOC_TYPE_HPET:
4094 case X86_IRQ_ALLOC_TYPE_MSI:
4095 case X86_IRQ_ALLOC_TYPE_MSIX:
4096 msg->address_hi = MSI_ADDR_BASE_HI;
4097 msg->address_lo = MSI_ADDR_BASE_LO;
4098 msg->data = irte_info->index;
4099 break;
5527de74 4100
7c71d306
JL		 4101 default:
4102 BUG_ON(1);
4103 break;
4104 }
5527de74
JR		 4105}
4106
880ac60e
SS		 4107struct amd_irte_ops irte_32_ops = {
4108 .prepare = irte_prepare,
4109 .activate = irte_activate,
4110 .deactivate = irte_deactivate,
4111 .set_affinity = irte_set_affinity,
4112 .set_allocated = irte_set_allocated,
4113 .is_allocated = irte_is_allocated,
4114 .clear_allocated = irte_clear_allocated,
4115};
4116
4117struct amd_irte_ops irte_128_ops = {
4118 .prepare = irte_ga_prepare,
4119 .activate = irte_ga_activate,
4120 .deactivate = irte_ga_deactivate,
4121 .set_affinity = irte_ga_set_affinity,
4122 .set_allocated = irte_ga_set_allocated,
4123 .is_allocated = irte_ga_is_allocated,
4124 .clear_allocated = irte_ga_clear_allocated,
4125};
4126
7c71d306
JL		 4127static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4128 unsigned int nr_irqs, void *arg)
5527de74 4129{
7c71d306
JL		 4130 struct irq_alloc_info *info = arg;
4131 struct irq_data *irq_data;
77bdab46 4132 struct amd_ir_data *data = NULL;
5527de74 4133 struct irq_cfg *cfg;
7c71d306 4134 int i, ret, devid;
29d049be 4135 int index;
5527de74 4136
7c71d306
JL		 4137 if (!info)
4138 return -EINVAL;
4139 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4140 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
5527de74
JR		 4141 return -EINVAL;
4142
7c71d306
JL		 4143 /*
4144 * With IRQ remapping enabled, don't need contiguous CPU vectors
4145 * to support multiple MSI interrupts.
4146 */
4147 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4148 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
5527de74 4149
7c71d306
JL		 4150 devid = get_devid(info);
4151 if (devid < 0)
4152 return -EINVAL;
5527de74 4153
7c71d306
JL		 4154 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4155 if (ret < 0)
4156 return ret;
0b4d48cb 4157
7c71d306 4158 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
fde65dd3
SAS		 4159 struct irq_remap_table *table;
4160 struct amd_iommu *iommu;
4161
4162 table = alloc_irq_table(devid);
4163 if (table) {
4164 if (!table->min_index) {
4165 /*
4166 * Keep the first 32 indexes free for IOAPIC
4167 * interrupts.
4168 */
4169 table->min_index = 32;
4170 iommu = amd_iommu_rlookup_table[devid];
4171 for (i = 0; i < 32; ++i)
4172 iommu->irte_ops->set_allocated(table, i);
4173 }
4174 WARN_ON(table->min_index != 32);
7c71d306 4175 index = info->ioapic_pin;
fde65dd3 4176 } else {
29d049be 4177 index = -ENOMEM;
fde65dd3 4178 }
7c71d306 4179 } else {
53b9ec3f
JR		 4180 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4181
4182 index = alloc_irq_index(devid, nr_irqs, align);
7c71d306
JL		 4183 }
4184 if (index < 0) {
4185 pr_warn("Failed to allocate IRTE\n");
517abe49 4186 ret = index;
7c71d306
JL		 4187 goto out_free_parent;
4188 }
0b4d48cb 4189
7c71d306
JL		 4190 for (i = 0; i < nr_irqs; i++) {
4191 irq_data = irq_domain_get_irq_data(domain, virq + i);
4192 cfg = irqd_cfg(irq_data);
4193 if (!irq_data || !cfg) {
4194 ret = -EINVAL;
4195 goto out_free_data;
4196 }
0b4d48cb 4197
a130e69f
JR		 4198 ret = -ENOMEM;
4199 data = kzalloc(sizeof(*data), GFP_KERNEL);
4200 if (!data)
4201 goto out_free_data;
4202
77bdab46
SS		 4203 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4204 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4205 else
4206 data->entry = kzalloc(sizeof(struct irte_ga),
4207 GFP_KERNEL);
4208 if (!data->entry) {
4209 kfree(data);
4210 goto out_free_data;
4211 }
4212
7c71d306
JL		 4213 irq_data->hwirq = (devid << 16) + i;
4214 irq_data->chip_data = data;
4215 irq_data->chip = &amd_ir_chip;
4216 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4217 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4218 }
a130e69f 4219
7c71d306 4220 return 0;
0b4d48cb 4221
7c71d306
JL		 4222out_free_data:
4223 for (i--; i >= 0; i--) {
4224 irq_data = irq_domain_get_irq_data(domain, virq + i);
4225 if (irq_data)
4226 kfree(irq_data->chip_data);
4227 }
4228 for (i = 0; i < nr_irqs; i++)
4229 free_irte(devid, index + i);
4230out_free_parent:
4231 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4232 return ret;
0b4d48cb
JR		 4233}
4234
7c71d306
JL		 4235static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4236 unsigned int nr_irqs)
0b4d48cb 4237{
7c71d306
JL		 4238 struct irq_2_irte *irte_info;
4239 struct irq_data *irq_data;
4240 struct amd_ir_data *data;
4241 int i;
0b4d48cb 4242
7c71d306
JL		 4243 for (i = 0; i < nr_irqs; i++) {
4244 irq_data = irq_domain_get_irq_data(domain, virq + i);
4245 if (irq_data && irq_data->chip_data) {
4246 data = irq_data->chip_data;
4247 irte_info = &data->irq_2_irte;
4248 free_irte(irte_info->devid, irte_info->index);
77bdab46 4249 kfree(data->entry);
7c71d306
JL		 4250 kfree(data);
4251 }
4252 }
4253 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4254}
0b4d48cb 4255
5ba204a1
TG		 4256static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4257 struct amd_ir_data *ir_data,
4258 struct irq_2_irte *irte_info,
4259 struct irq_cfg *cfg);
4260
72491643 4261static int irq_remapping_activate(struct irq_domain *domain,
702cb0a0 4262 struct irq_data *irq_data, bool reserve)
7c71d306
JL		 4263{
4264 struct amd_ir_data *data = irq_data->chip_data;
4265 struct irq_2_irte *irte_info = &data->irq_2_irte;
77bdab46 4266 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
5ba204a1 4267 struct irq_cfg *cfg = irqd_cfg(irq_data);
0b4d48cb 4268
5ba204a1
TG		 4269 if (!iommu)
4270 return 0;
4271
4272 iommu->irte_ops->activate(data->entry, irte_info->devid,
4273 irte_info->index);
4274 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
72491643 4275 return 0;
0b4d48cb
JR		 4276}
4277
7c71d306
JL		 4278static void irq_remapping_deactivate(struct irq_domain *domain,
4279 struct irq_data *irq_data)
0b4d48cb 4280{
7c71d306
JL		 4281 struct amd_ir_data *data = irq_data->chip_data;
4282 struct irq_2_irte *irte_info = &data->irq_2_irte;
77bdab46 4283 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
0b4d48cb 4284
77bdab46
SS		 4285 if (iommu)
4286 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4287 irte_info->index);
7c71d306 4288}
0b4d48cb 4289
e2f9d45f 4290static const struct irq_domain_ops amd_ir_domain_ops = {
7c71d306
JL		 4291 .alloc = irq_remapping_alloc,
4292 .free = irq_remapping_free,
4293 .activate = irq_remapping_activate,
4294 .deactivate = irq_remapping_deactivate,
6b474b82 4295};
0b4d48cb 4296
b9fc6b56
SS		 4297static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4298{
4299 struct amd_iommu *iommu;
4300 struct amd_iommu_pi_data *pi_data = vcpu_info;
4301 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4302 struct amd_ir_data *ir_data = data->chip_data;
4303 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4304 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
d98de49a
SS		 4305 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4306
4307 /* Note:
4308 * This device has never been set up for guest mode.
4309 * we should not modify the IRTE
4310 */
4311 if (!dev_data || !dev_data->use_vapic)
4312 return 0;
b9fc6b56
SS		 4313
4314 pi_data->ir_data = ir_data;
4315
4316 /* Note:
4317 * SVM tries to set up for VAPIC mode, but we are in
4318 * legacy mode. So, we force legacy mode instead.
4319 */
4320 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4321 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4322 __func__);
4323 pi_data->is_guest_mode = false;
4324 }
4325
4326 iommu = amd_iommu_rlookup_table[irte_info->devid];
4327 if (iommu == NULL)
4328 return -EINVAL;
4329
4330 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4331 if (pi_data->is_guest_mode) {
4332 /* Setting */
4333 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4334 irte->hi.fields.vector = vcpu_pi_info->vector;
efe6f241 4335 irte->lo.fields_vapic.ga_log_intr = 1;
b9fc6b56
SS		 4336 irte->lo.fields_vapic.guest_mode = 1;
4337 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4338
4339 ir_data->cached_ga_tag = pi_data->ga_tag;
4340 } else {
4341 /* Un-Setting */
4342 struct irq_cfg *cfg = irqd_cfg(data);
4343
4344 irte->hi.val = 0;
4345 irte->lo.val = 0;
4346 irte->hi.fields.vector = cfg->vector;
4347 irte->lo.fields_remap.guest_mode = 0;
90fcffd9
SS		 4348 irte->lo.fields_remap.destination =
4349 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4350 irte->hi.fields.destination =
4351 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
b9fc6b56
SS		 4352 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4353 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4354
4355 /*
4356 * This communicates the ga_tag back to the caller
4357 * so that it can do all the necessary clean up.
4358 */
4359 ir_data->cached_ga_tag = 0;
4360 }
4361
4362 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4363}
4364
5ba204a1
TG		 4365
4366static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4367 struct amd_ir_data *ir_data,
4368 struct irq_2_irte *irte_info,
4369 struct irq_cfg *cfg)
4370{
4371
4372 /*
4373 * Atomically updates the IRTE with the new destination, vector
4374 * and flushes the interrupt entry cache.
4375 */
4376 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4377 irte_info->index, cfg->vector,
4378 cfg->dest_apicid);
4379}
4380
7c71d306
JL		 4381static int amd_ir_set_affinity(struct irq_data *data,
4382 const struct cpumask *mask, bool force)
4383{
4384 struct amd_ir_data *ir_data = data->chip_data;
4385 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4386 struct irq_cfg *cfg = irqd_cfg(data);
4387 struct irq_data *parent = data->parent_data;
77bdab46 4388 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
7c71d306 4389 int ret;
0b4d48cb 4390
77bdab46
SS		 4391 if (!iommu)
4392 return -ENODEV;
4393
7c71d306
JL		 4394 ret = parent->chip->irq_set_affinity(parent, mask, force);
4395 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4396 return ret;
0b4d48cb 4397
5ba204a1 4398 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
7c71d306
JL		 4399 /*
4400 * After this point, all the interrupts will start arriving
4401 * at the new destination. So, time to cleanup the previous
4402 * vector allocation.
4403 */
c6c2002b 4404 send_cleanup_vector(cfg);
7c71d306
JL		 4405
4406 return IRQ_SET_MASK_OK_DONE;
0b4d48cb
JR		 4407}
4408
7c71d306 4409static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
d976195c 4410{
7c71d306 4411 struct amd_ir_data *ir_data = irq_data->chip_data;
d976195c 4412
7c71d306
JL		 4413 *msg = ir_data->msi_entry;
4414}
d976195c 4415
7c71d306 4416static struct irq_chip amd_ir_chip = {
290be194 4417 .name = "AMD-IR",
8a2b7d14 4418 .irq_ack = apic_ack_irq,
290be194
TG		 4419 .irq_set_affinity = amd_ir_set_affinity,
4420 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4421 .irq_compose_msi_msg = ir_compose_msi_msg,
7c71d306 4422};
d976195c 4423
7c71d306
JL		 4424int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4425{
3e49a818
TG		 4426 struct fwnode_handle *fn;
4427
4428 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4429 if (!fn)
4430 return -ENOMEM;
4431 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4432 irq_domain_free_fwnode(fn);
7c71d306
JL		 4433 if (!iommu->ir_domain)
4434 return -ENOMEM;
d976195c 4435
7c71d306 4436 iommu->ir_domain->parent = arch_get_ir_parent_domain();
3e49a818
TG		 4437 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4438 "AMD-IR-MSI",
4439 iommu->index);
d976195c
JR		 4440 return 0;
4441}
8dbea3fd
SS		 4442
4443int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4444{
4445 unsigned long flags;
4446 struct amd_iommu *iommu;
4fde541c 4447 struct irq_remap_table *table;
8dbea3fd
SS		 4448 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4449 int devid = ir_data->irq_2_irte.devid;
4450 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4451 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4452
4453 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4454 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4455 return 0;
4456
4457 iommu = amd_iommu_rlookup_table[devid];
4458 if (!iommu)
4459 return -ENODEV;
4460
4fde541c
SAS		 4461 table = get_irq_table(devid);
4462 if (!table)
8dbea3fd
SS		 4463 return -ENODEV;
4464
4fde541c 4465 raw_spin_lock_irqsave(&table->lock, flags);
8dbea3fd
SS		 4466
4467 if (ref->lo.fields_vapic.guest_mode) {
90fcffd9
SS		 4468 if (cpu >= 0) {
4469 ref->lo.fields_vapic.destination =
4470 APICID_TO_IRTE_DEST_LO(cpu);
4471 ref->hi.fields.destination =
4472 APICID_TO_IRTE_DEST_HI(cpu);
4473 }
8dbea3fd
SS		 4474 ref->lo.fields_vapic.is_run = is_run;
4475 barrier();
4476 }
4477
4fde541c 4478 raw_spin_unlock_irqrestore(&table->lock, flags);
8dbea3fd
SS		 4479
4480 iommu_flush_irt(iommu, devid);
4481 iommu_completion_wait(iommu);
4482 return 0;
4483}
4484EXPORT_SYMBOL(amd_iommu_update_ga);
2b324506 4485#endif
Linux 6.x block layer and io_uring tree(s)