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9f196772 RN |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. | |
4 | * Copyright (c) 2023, Linaro Limited | |
5 | * | |
6 | */ | |
7 | ||
8 | #include <linux/device.h> | |
9 | #include <linux/interconnect.h> | |
10 | #include <linux/interconnect-provider.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of_platform.h> | |
13 | #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> | |
14 | ||
15 | #include "bcm-voter.h" | |
16 | #include "icc-common.h" | |
17 | #include "icc-rpmh.h" | |
18 | #include "x1e80100.h" | |
19 | ||
20 | static struct qcom_icc_node qhm_qspi = { | |
21 | .name = "qhm_qspi", | |
22 | .id = X1E80100_MASTER_QSPI_0, | |
23 | .channels = 1, | |
24 | .buswidth = 4, | |
25 | .num_links = 1, | |
26 | .links = { X1E80100_SLAVE_A1NOC_SNOC }, | |
27 | }; | |
28 | ||
29 | static struct qcom_icc_node qhm_qup1 = { | |
30 | .name = "qhm_qup1", | |
31 | .id = X1E80100_MASTER_QUP_1, | |
32 | .channels = 1, | |
33 | .buswidth = 4, | |
34 | .num_links = 1, | |
35 | .links = { X1E80100_SLAVE_A1NOC_SNOC }, | |
36 | }; | |
37 | ||
38 | static struct qcom_icc_node xm_sdc4 = { | |
39 | .name = "xm_sdc4", | |
40 | .id = X1E80100_MASTER_SDCC_4, | |
41 | .channels = 1, | |
42 | .buswidth = 8, | |
43 | .num_links = 1, | |
44 | .links = { X1E80100_SLAVE_A1NOC_SNOC }, | |
45 | }; | |
46 | ||
47 | static struct qcom_icc_node xm_ufs_mem = { | |
48 | .name = "xm_ufs_mem", | |
49 | .id = X1E80100_MASTER_UFS_MEM, | |
50 | .channels = 1, | |
51 | .buswidth = 16, | |
52 | .num_links = 1, | |
53 | .links = { X1E80100_SLAVE_A1NOC_SNOC }, | |
54 | }; | |
55 | ||
56 | static struct qcom_icc_node qhm_qup0 = { | |
57 | .name = "qhm_qup0", | |
58 | .id = X1E80100_MASTER_QUP_0, | |
59 | .channels = 1, | |
60 | .buswidth = 4, | |
61 | .num_links = 1, | |
62 | .links = { X1E80100_SLAVE_A2NOC_SNOC }, | |
63 | }; | |
64 | ||
65 | static struct qcom_icc_node qhm_qup2 = { | |
66 | .name = "qhm_qup2", | |
67 | .id = X1E80100_MASTER_QUP_2, | |
68 | .channels = 1, | |
69 | .buswidth = 4, | |
70 | .num_links = 1, | |
71 | .links = { X1E80100_SLAVE_A2NOC_SNOC }, | |
72 | }; | |
73 | ||
74 | static struct qcom_icc_node qxm_crypto = { | |
75 | .name = "qxm_crypto", | |
76 | .id = X1E80100_MASTER_CRYPTO, | |
77 | .channels = 1, | |
78 | .buswidth = 8, | |
79 | .num_links = 1, | |
80 | .links = { X1E80100_SLAVE_A2NOC_SNOC }, | |
81 | }; | |
82 | ||
83 | static struct qcom_icc_node qxm_sp = { | |
84 | .name = "qxm_sp", | |
85 | .id = X1E80100_MASTER_SP, | |
86 | .channels = 1, | |
87 | .buswidth = 8, | |
88 | .num_links = 1, | |
89 | .links = { X1E80100_SLAVE_A2NOC_SNOC }, | |
90 | }; | |
91 | ||
92 | static struct qcom_icc_node xm_qdss_etr_0 = { | |
93 | .name = "xm_qdss_etr_0", | |
94 | .id = X1E80100_MASTER_QDSS_ETR, | |
95 | .channels = 1, | |
96 | .buswidth = 8, | |
97 | .num_links = 1, | |
98 | .links = { X1E80100_SLAVE_A2NOC_SNOC }, | |
99 | }; | |
100 | ||
101 | static struct qcom_icc_node xm_qdss_etr_1 = { | |
102 | .name = "xm_qdss_etr_1", | |
103 | .id = X1E80100_MASTER_QDSS_ETR_1, | |
104 | .channels = 1, | |
105 | .buswidth = 8, | |
106 | .num_links = 1, | |
107 | .links = { X1E80100_SLAVE_A2NOC_SNOC }, | |
108 | }; | |
109 | ||
110 | static struct qcom_icc_node xm_sdc2 = { | |
111 | .name = "xm_sdc2", | |
112 | .id = X1E80100_MASTER_SDCC_2, | |
113 | .channels = 1, | |
114 | .buswidth = 8, | |
115 | .num_links = 1, | |
116 | .links = { X1E80100_SLAVE_A2NOC_SNOC }, | |
117 | }; | |
118 | ||
9f196772 RN |
119 | static struct qcom_icc_node qup0_core_master = { |
120 | .name = "qup0_core_master", | |
121 | .id = X1E80100_MASTER_QUP_CORE_0, | |
122 | .channels = 1, | |
123 | .buswidth = 4, | |
124 | .num_links = 1, | |
125 | .links = { X1E80100_SLAVE_QUP_CORE_0 }, | |
126 | }; | |
127 | ||
128 | static struct qcom_icc_node qup1_core_master = { | |
129 | .name = "qup1_core_master", | |
130 | .id = X1E80100_MASTER_QUP_CORE_1, | |
131 | .channels = 1, | |
132 | .buswidth = 4, | |
133 | .num_links = 1, | |
134 | .links = { X1E80100_SLAVE_QUP_CORE_1 }, | |
135 | }; | |
136 | ||
137 | static struct qcom_icc_node qup2_core_master = { | |
138 | .name = "qup2_core_master", | |
139 | .id = X1E80100_MASTER_QUP_CORE_2, | |
140 | .channels = 1, | |
141 | .buswidth = 4, | |
142 | .num_links = 1, | |
143 | .links = { X1E80100_SLAVE_QUP_CORE_2 }, | |
144 | }; | |
145 | ||
146 | static struct qcom_icc_node qsm_cfg = { | |
147 | .name = "qsm_cfg", | |
148 | .id = X1E80100_MASTER_CNOC_CFG, | |
149 | .channels = 1, | |
150 | .buswidth = 4, | |
151 | .num_links = 47, | |
152 | .links = { X1E80100_SLAVE_AHB2PHY_SOUTH, X1E80100_SLAVE_AHB2PHY_NORTH, | |
153 | X1E80100_SLAVE_AHB2PHY_2, X1E80100_SLAVE_AV1_ENC_CFG, | |
154 | X1E80100_SLAVE_CAMERA_CFG, X1E80100_SLAVE_CLK_CTL, | |
155 | X1E80100_SLAVE_CRYPTO_0_CFG, X1E80100_SLAVE_DISPLAY_CFG, | |
156 | X1E80100_SLAVE_GFX3D_CFG, X1E80100_SLAVE_IMEM_CFG, | |
157 | X1E80100_SLAVE_IPC_ROUTER_CFG, X1E80100_SLAVE_PCIE_0_CFG, | |
158 | X1E80100_SLAVE_PCIE_1_CFG, X1E80100_SLAVE_PCIE_2_CFG, | |
159 | X1E80100_SLAVE_PCIE_3_CFG, X1E80100_SLAVE_PCIE_4_CFG, | |
160 | X1E80100_SLAVE_PCIE_5_CFG, X1E80100_SLAVE_PCIE_6A_CFG, | |
161 | X1E80100_SLAVE_PCIE_6B_CFG, X1E80100_SLAVE_PCIE_RSC_CFG, | |
162 | X1E80100_SLAVE_PDM, X1E80100_SLAVE_PRNG, | |
163 | X1E80100_SLAVE_QDSS_CFG, X1E80100_SLAVE_QSPI_0, | |
164 | X1E80100_SLAVE_QUP_0, X1E80100_SLAVE_QUP_1, | |
165 | X1E80100_SLAVE_QUP_2, X1E80100_SLAVE_SDCC_2, | |
166 | X1E80100_SLAVE_SDCC_4, X1E80100_SLAVE_SMMUV3_CFG, | |
167 | X1E80100_SLAVE_TCSR, X1E80100_SLAVE_TLMM, | |
168 | X1E80100_SLAVE_UFS_MEM_CFG, X1E80100_SLAVE_USB2, | |
169 | X1E80100_SLAVE_USB3_0, X1E80100_SLAVE_USB3_1, | |
170 | X1E80100_SLAVE_USB3_2, X1E80100_SLAVE_USB3_MP, | |
171 | X1E80100_SLAVE_USB4_0, X1E80100_SLAVE_USB4_1, | |
172 | X1E80100_SLAVE_USB4_2, X1E80100_SLAVE_VENUS_CFG, | |
173 | X1E80100_SLAVE_LPASS_QTB_CFG, X1E80100_SLAVE_CNOC_MNOC_CFG, | |
174 | X1E80100_SLAVE_NSP_QTB_CFG, X1E80100_SLAVE_QDSS_STM, | |
175 | X1E80100_SLAVE_TCU }, | |
176 | }; | |
177 | ||
178 | static struct qcom_icc_node qnm_gemnoc_cnoc = { | |
179 | .name = "qnm_gemnoc_cnoc", | |
180 | .id = X1E80100_MASTER_GEM_NOC_CNOC, | |
181 | .channels = 1, | |
182 | .buswidth = 16, | |
183 | .num_links = 6, | |
184 | .links = { X1E80100_SLAVE_AOSS, X1E80100_SLAVE_TME_CFG, | |
185 | X1E80100_SLAVE_APPSS, X1E80100_SLAVE_CNOC_CFG, | |
186 | X1E80100_SLAVE_BOOT_IMEM, X1E80100_SLAVE_IMEM }, | |
187 | }; | |
188 | ||
189 | static struct qcom_icc_node qnm_gemnoc_pcie = { | |
190 | .name = "qnm_gemnoc_pcie", | |
191 | .id = X1E80100_MASTER_GEM_NOC_PCIE_SNOC, | |
192 | .channels = 1, | |
193 | .buswidth = 32, | |
194 | .num_links = 8, | |
195 | .links = { X1E80100_SLAVE_PCIE_0, X1E80100_SLAVE_PCIE_1, | |
196 | X1E80100_SLAVE_PCIE_2, X1E80100_SLAVE_PCIE_3, | |
197 | X1E80100_SLAVE_PCIE_4, X1E80100_SLAVE_PCIE_5, | |
198 | X1E80100_SLAVE_PCIE_6A, X1E80100_SLAVE_PCIE_6B }, | |
199 | }; | |
200 | ||
201 | static struct qcom_icc_node alm_gpu_tcu = { | |
202 | .name = "alm_gpu_tcu", | |
203 | .id = X1E80100_MASTER_GPU_TCU, | |
204 | .channels = 1, | |
205 | .buswidth = 8, | |
206 | .num_links = 2, | |
207 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, | |
208 | }; | |
209 | ||
210 | static struct qcom_icc_node alm_pcie_tcu = { | |
211 | .name = "alm_pcie_tcu", | |
212 | .id = X1E80100_MASTER_PCIE_TCU, | |
213 | .channels = 1, | |
214 | .buswidth = 8, | |
215 | .num_links = 2, | |
216 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, | |
217 | }; | |
218 | ||
219 | static struct qcom_icc_node alm_sys_tcu = { | |
220 | .name = "alm_sys_tcu", | |
221 | .id = X1E80100_MASTER_SYS_TCU, | |
222 | .channels = 1, | |
223 | .buswidth = 8, | |
224 | .num_links = 2, | |
225 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, | |
226 | }; | |
227 | ||
228 | static struct qcom_icc_node chm_apps = { | |
229 | .name = "chm_apps", | |
230 | .id = X1E80100_MASTER_APPSS_PROC, | |
231 | .channels = 6, | |
232 | .buswidth = 32, | |
233 | .num_links = 3, | |
234 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, | |
235 | X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, | |
236 | }; | |
237 | ||
238 | static struct qcom_icc_node qnm_gpu = { | |
239 | .name = "qnm_gpu", | |
240 | .id = X1E80100_MASTER_GFX3D, | |
241 | .channels = 4, | |
242 | .buswidth = 32, | |
243 | .num_links = 2, | |
244 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, | |
245 | }; | |
246 | ||
247 | static struct qcom_icc_node qnm_lpass = { | |
248 | .name = "qnm_lpass", | |
249 | .id = X1E80100_MASTER_LPASS_GEM_NOC, | |
250 | .channels = 1, | |
251 | .buswidth = 16, | |
252 | .num_links = 3, | |
253 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, | |
254 | X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, | |
255 | }; | |
256 | ||
257 | static struct qcom_icc_node qnm_mnoc_hf = { | |
258 | .name = "qnm_mnoc_hf", | |
259 | .id = X1E80100_MASTER_MNOC_HF_MEM_NOC, | |
260 | .channels = 2, | |
261 | .buswidth = 32, | |
262 | .num_links = 2, | |
263 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, | |
264 | }; | |
265 | ||
266 | static struct qcom_icc_node qnm_mnoc_sf = { | |
267 | .name = "qnm_mnoc_sf", | |
268 | .id = X1E80100_MASTER_MNOC_SF_MEM_NOC, | |
269 | .channels = 2, | |
270 | .buswidth = 32, | |
271 | .num_links = 2, | |
272 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, | |
273 | }; | |
274 | ||
275 | static struct qcom_icc_node qnm_nsp_noc = { | |
276 | .name = "qnm_nsp_noc", | |
277 | .id = X1E80100_MASTER_COMPUTE_NOC, | |
278 | .channels = 2, | |
279 | .buswidth = 32, | |
280 | .num_links = 3, | |
281 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, | |
282 | X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, | |
283 | }; | |
284 | ||
285 | static struct qcom_icc_node qnm_pcie = { | |
286 | .name = "qnm_pcie", | |
287 | .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC, | |
288 | .channels = 1, | |
289 | .buswidth = 64, | |
290 | .num_links = 2, | |
291 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, | |
292 | }; | |
293 | ||
294 | static struct qcom_icc_node qnm_snoc_sf = { | |
295 | .name = "qnm_snoc_sf", | |
296 | .id = X1E80100_MASTER_SNOC_SF_MEM_NOC, | |
297 | .channels = 1, | |
298 | .buswidth = 64, | |
299 | .num_links = 3, | |
300 | .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, | |
301 | X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, | |
302 | }; | |
303 | ||
304 | static struct qcom_icc_node xm_gic = { | |
305 | .name = "xm_gic", | |
306 | .id = X1E80100_MASTER_GIC2, | |
307 | .channels = 1, | |
308 | .buswidth = 8, | |
309 | .num_links = 1, | |
310 | .links = { X1E80100_SLAVE_LLCC }, | |
311 | }; | |
312 | ||
313 | static struct qcom_icc_node qnm_lpiaon_noc = { | |
314 | .name = "qnm_lpiaon_noc", | |
315 | .id = X1E80100_MASTER_LPIAON_NOC, | |
316 | .channels = 1, | |
317 | .buswidth = 16, | |
318 | .num_links = 1, | |
319 | .links = { X1E80100_SLAVE_LPASS_GEM_NOC }, | |
320 | }; | |
321 | ||
322 | static struct qcom_icc_node qnm_lpass_lpinoc = { | |
323 | .name = "qnm_lpass_lpinoc", | |
324 | .id = X1E80100_MASTER_LPASS_LPINOC, | |
325 | .channels = 1, | |
326 | .buswidth = 16, | |
327 | .num_links = 1, | |
328 | .links = { X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, | |
329 | }; | |
330 | ||
331 | static struct qcom_icc_node qxm_lpinoc_dsp_axim = { | |
332 | .name = "qxm_lpinoc_dsp_axim", | |
333 | .id = X1E80100_MASTER_LPASS_PROC, | |
334 | .channels = 1, | |
335 | .buswidth = 16, | |
336 | .num_links = 1, | |
337 | .links = { X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC }, | |
338 | }; | |
339 | ||
340 | static struct qcom_icc_node llcc_mc = { | |
341 | .name = "llcc_mc", | |
342 | .id = X1E80100_MASTER_LLCC, | |
343 | .channels = 8, | |
344 | .buswidth = 4, | |
345 | .num_links = 1, | |
346 | .links = { X1E80100_SLAVE_EBI1 }, | |
347 | }; | |
348 | ||
349 | static struct qcom_icc_node qnm_av1_enc = { | |
350 | .name = "qnm_av1_enc", | |
351 | .id = X1E80100_MASTER_AV1_ENC, | |
352 | .channels = 1, | |
353 | .buswidth = 32, | |
354 | .num_links = 1, | |
355 | .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, | |
356 | }; | |
357 | ||
358 | static struct qcom_icc_node qnm_camnoc_hf = { | |
359 | .name = "qnm_camnoc_hf", | |
360 | .id = X1E80100_MASTER_CAMNOC_HF, | |
361 | .channels = 2, | |
362 | .buswidth = 32, | |
363 | .num_links = 1, | |
364 | .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, | |
365 | }; | |
366 | ||
367 | static struct qcom_icc_node qnm_camnoc_icp = { | |
368 | .name = "qnm_camnoc_icp", | |
369 | .id = X1E80100_MASTER_CAMNOC_ICP, | |
370 | .channels = 1, | |
371 | .buswidth = 8, | |
372 | .num_links = 1, | |
373 | .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, | |
374 | }; | |
375 | ||
376 | static struct qcom_icc_node qnm_camnoc_sf = { | |
377 | .name = "qnm_camnoc_sf", | |
378 | .id = X1E80100_MASTER_CAMNOC_SF, | |
379 | .channels = 2, | |
380 | .buswidth = 32, | |
381 | .num_links = 1, | |
382 | .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, | |
383 | }; | |
384 | ||
385 | static struct qcom_icc_node qnm_eva = { | |
386 | .name = "qnm_eva", | |
387 | .id = X1E80100_MASTER_EVA, | |
388 | .channels = 1, | |
389 | .buswidth = 32, | |
390 | .num_links = 1, | |
391 | .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, | |
392 | }; | |
393 | ||
394 | static struct qcom_icc_node qnm_mdp = { | |
395 | .name = "qnm_mdp", | |
396 | .id = X1E80100_MASTER_MDP, | |
397 | .channels = 2, | |
398 | .buswidth = 32, | |
399 | .num_links = 1, | |
400 | .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, | |
401 | }; | |
402 | ||
403 | static struct qcom_icc_node qnm_video = { | |
404 | .name = "qnm_video", | |
405 | .id = X1E80100_MASTER_VIDEO, | |
406 | .channels = 2, | |
407 | .buswidth = 32, | |
408 | .num_links = 1, | |
409 | .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, | |
410 | }; | |
411 | ||
412 | static struct qcom_icc_node qnm_video_cv_cpu = { | |
413 | .name = "qnm_video_cv_cpu", | |
414 | .id = X1E80100_MASTER_VIDEO_CV_PROC, | |
415 | .channels = 1, | |
416 | .buswidth = 8, | |
417 | .num_links = 1, | |
418 | .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, | |
419 | }; | |
420 | ||
421 | static struct qcom_icc_node qnm_video_v_cpu = { | |
422 | .name = "qnm_video_v_cpu", | |
423 | .id = X1E80100_MASTER_VIDEO_V_PROC, | |
424 | .channels = 1, | |
425 | .buswidth = 8, | |
426 | .num_links = 1, | |
427 | .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, | |
428 | }; | |
429 | ||
430 | static struct qcom_icc_node qsm_mnoc_cfg = { | |
431 | .name = "qsm_mnoc_cfg", | |
432 | .id = X1E80100_MASTER_CNOC_MNOC_CFG, | |
433 | .channels = 1, | |
434 | .buswidth = 4, | |
435 | .num_links = 1, | |
436 | .links = { X1E80100_SLAVE_SERVICE_MNOC }, | |
437 | }; | |
438 | ||
439 | static struct qcom_icc_node qxm_nsp = { | |
440 | .name = "qxm_nsp", | |
441 | .id = X1E80100_MASTER_CDSP_PROC, | |
442 | .channels = 2, | |
443 | .buswidth = 32, | |
444 | .num_links = 1, | |
445 | .links = { X1E80100_SLAVE_CDSP_MEM_NOC }, | |
446 | }; | |
447 | ||
448 | static struct qcom_icc_node qnm_pcie_north_gem_noc = { | |
449 | .name = "qnm_pcie_north_gem_noc", | |
450 | .id = X1E80100_MASTER_PCIE_NORTH, | |
451 | .channels = 1, | |
452 | .buswidth = 64, | |
453 | .num_links = 1, | |
454 | .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, | |
455 | }; | |
456 | ||
457 | static struct qcom_icc_node qnm_pcie_south_gem_noc = { | |
458 | .name = "qnm_pcie_south_gem_noc", | |
459 | .id = X1E80100_MASTER_PCIE_SOUTH, | |
460 | .channels = 1, | |
461 | .buswidth = 64, | |
462 | .num_links = 1, | |
463 | .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, | |
464 | }; | |
465 | ||
466 | static struct qcom_icc_node xm_pcie_3 = { | |
467 | .name = "xm_pcie_3", | |
468 | .id = X1E80100_MASTER_PCIE_3, | |
469 | .channels = 1, | |
470 | .buswidth = 64, | |
471 | .num_links = 1, | |
472 | .links = { X1E80100_SLAVE_PCIE_NORTH }, | |
473 | }; | |
474 | ||
475 | static struct qcom_icc_node xm_pcie_4 = { | |
476 | .name = "xm_pcie_4", | |
477 | .id = X1E80100_MASTER_PCIE_4, | |
478 | .channels = 1, | |
479 | .buswidth = 8, | |
480 | .num_links = 1, | |
481 | .links = { X1E80100_SLAVE_PCIE_NORTH }, | |
482 | }; | |
483 | ||
484 | static struct qcom_icc_node xm_pcie_5 = { | |
485 | .name = "xm_pcie_5", | |
486 | .id = X1E80100_MASTER_PCIE_5, | |
487 | .channels = 1, | |
488 | .buswidth = 8, | |
489 | .num_links = 1, | |
490 | .links = { X1E80100_SLAVE_PCIE_NORTH }, | |
491 | }; | |
492 | ||
493 | static struct qcom_icc_node xm_pcie_0 = { | |
494 | .name = "xm_pcie_0", | |
495 | .id = X1E80100_MASTER_PCIE_0, | |
496 | .channels = 1, | |
497 | .buswidth = 16, | |
498 | .num_links = 1, | |
499 | .links = { X1E80100_SLAVE_PCIE_SOUTH }, | |
500 | }; | |
501 | ||
502 | static struct qcom_icc_node xm_pcie_1 = { | |
503 | .name = "xm_pcie_1", | |
504 | .id = X1E80100_MASTER_PCIE_1, | |
505 | .channels = 1, | |
506 | .buswidth = 16, | |
507 | .num_links = 1, | |
508 | .links = { X1E80100_SLAVE_PCIE_SOUTH }, | |
509 | }; | |
510 | ||
511 | static struct qcom_icc_node xm_pcie_2 = { | |
512 | .name = "xm_pcie_2", | |
513 | .id = X1E80100_MASTER_PCIE_2, | |
514 | .channels = 1, | |
515 | .buswidth = 16, | |
516 | .num_links = 1, | |
517 | .links = { X1E80100_SLAVE_PCIE_SOUTH }, | |
518 | }; | |
519 | ||
520 | static struct qcom_icc_node xm_pcie_6a = { | |
521 | .name = "xm_pcie_6a", | |
522 | .id = X1E80100_MASTER_PCIE_6A, | |
523 | .channels = 1, | |
524 | .buswidth = 32, | |
525 | .num_links = 1, | |
526 | .links = { X1E80100_SLAVE_PCIE_SOUTH }, | |
527 | }; | |
528 | ||
529 | static struct qcom_icc_node xm_pcie_6b = { | |
530 | .name = "xm_pcie_6b", | |
531 | .id = X1E80100_MASTER_PCIE_6B, | |
532 | .channels = 1, | |
533 | .buswidth = 16, | |
534 | .num_links = 1, | |
535 | .links = { X1E80100_SLAVE_PCIE_SOUTH }, | |
536 | }; | |
537 | ||
538 | static struct qcom_icc_node qnm_aggre1_noc = { | |
539 | .name = "qnm_aggre1_noc", | |
540 | .id = X1E80100_MASTER_A1NOC_SNOC, | |
541 | .channels = 1, | |
542 | .buswidth = 16, | |
543 | .num_links = 1, | |
544 | .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, | |
545 | }; | |
546 | ||
547 | static struct qcom_icc_node qnm_aggre2_noc = { | |
548 | .name = "qnm_aggre2_noc", | |
549 | .id = X1E80100_MASTER_A2NOC_SNOC, | |
550 | .channels = 1, | |
551 | .buswidth = 16, | |
552 | .num_links = 1, | |
553 | .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, | |
554 | }; | |
555 | ||
556 | static struct qcom_icc_node qnm_gic = { | |
557 | .name = "qnm_gic", | |
558 | .id = X1E80100_MASTER_GIC1, | |
559 | .channels = 1, | |
560 | .buswidth = 8, | |
561 | .num_links = 1, | |
562 | .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, | |
563 | }; | |
564 | ||
565 | static struct qcom_icc_node qnm_usb_anoc = { | |
566 | .name = "qnm_usb_anoc", | |
567 | .id = X1E80100_MASTER_USB_NOC_SNOC, | |
568 | .channels = 1, | |
569 | .buswidth = 64, | |
570 | .num_links = 1, | |
571 | .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, | |
572 | }; | |
573 | ||
574 | static struct qcom_icc_node qnm_aggre_usb_north_snoc = { | |
575 | .name = "qnm_aggre_usb_north_snoc", | |
576 | .id = X1E80100_MASTER_AGGRE_USB_NORTH, | |
577 | .channels = 1, | |
578 | .buswidth = 64, | |
579 | .num_links = 1, | |
580 | .links = { X1E80100_SLAVE_USB_NOC_SNOC }, | |
581 | }; | |
582 | ||
583 | static struct qcom_icc_node qnm_aggre_usb_south_snoc = { | |
584 | .name = "qnm_aggre_usb_south_snoc", | |
585 | .id = X1E80100_MASTER_AGGRE_USB_SOUTH, | |
586 | .channels = 1, | |
587 | .buswidth = 64, | |
588 | .num_links = 1, | |
589 | .links = { X1E80100_SLAVE_USB_NOC_SNOC }, | |
590 | }; | |
591 | ||
592 | static struct qcom_icc_node xm_usb2_0 = { | |
593 | .name = "xm_usb2_0", | |
594 | .id = X1E80100_MASTER_USB2, | |
595 | .channels = 1, | |
596 | .buswidth = 8, | |
597 | .num_links = 1, | |
598 | .links = { X1E80100_SLAVE_AGGRE_USB_NORTH }, | |
599 | }; | |
600 | ||
601 | static struct qcom_icc_node xm_usb3_mp = { | |
602 | .name = "xm_usb3_mp", | |
603 | .id = X1E80100_MASTER_USB3_MP, | |
604 | .channels = 1, | |
605 | .buswidth = 16, | |
606 | .num_links = 1, | |
607 | .links = { X1E80100_SLAVE_AGGRE_USB_NORTH }, | |
608 | }; | |
609 | ||
610 | static struct qcom_icc_node xm_usb3_0 = { | |
611 | .name = "xm_usb3_0", | |
612 | .id = X1E80100_MASTER_USB3_0, | |
613 | .channels = 1, | |
614 | .buswidth = 8, | |
615 | .num_links = 1, | |
616 | .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, | |
617 | }; | |
618 | ||
619 | static struct qcom_icc_node xm_usb3_1 = { | |
620 | .name = "xm_usb3_1", | |
621 | .id = X1E80100_MASTER_USB3_1, | |
622 | .channels = 1, | |
623 | .buswidth = 8, | |
624 | .num_links = 1, | |
625 | .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, | |
626 | }; | |
627 | ||
628 | static struct qcom_icc_node xm_usb3_2 = { | |
629 | .name = "xm_usb3_2", | |
630 | .id = X1E80100_MASTER_USB3_2, | |
631 | .channels = 1, | |
632 | .buswidth = 8, | |
633 | .num_links = 1, | |
634 | .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, | |
635 | }; | |
636 | ||
637 | static struct qcom_icc_node xm_usb4_0 = { | |
638 | .name = "xm_usb4_0", | |
639 | .id = X1E80100_MASTER_USB4_0, | |
640 | .channels = 1, | |
641 | .buswidth = 16, | |
642 | .num_links = 1, | |
643 | .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, | |
644 | }; | |
645 | ||
646 | static struct qcom_icc_node xm_usb4_1 = { | |
647 | .name = "xm_usb4_1", | |
648 | .id = X1E80100_MASTER_USB4_1, | |
649 | .channels = 1, | |
650 | .buswidth = 16, | |
651 | .num_links = 1, | |
652 | .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, | |
653 | }; | |
654 | ||
655 | static struct qcom_icc_node xm_usb4_2 = { | |
656 | .name = "xm_usb4_2", | |
657 | .id = X1E80100_MASTER_USB4_2, | |
658 | .channels = 1, | |
659 | .buswidth = 16, | |
660 | .num_links = 1, | |
661 | .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, | |
662 | }; | |
663 | ||
9f196772 RN |
664 | static struct qcom_icc_node qns_a1noc_snoc = { |
665 | .name = "qns_a1noc_snoc", | |
666 | .id = X1E80100_SLAVE_A1NOC_SNOC, | |
667 | .channels = 1, | |
668 | .buswidth = 16, | |
669 | .num_links = 1, | |
670 | .links = { X1E80100_MASTER_A1NOC_SNOC }, | |
671 | }; | |
672 | ||
673 | static struct qcom_icc_node qns_a2noc_snoc = { | |
674 | .name = "qns_a2noc_snoc", | |
675 | .id = X1E80100_SLAVE_A2NOC_SNOC, | |
676 | .channels = 1, | |
677 | .buswidth = 16, | |
678 | .num_links = 1, | |
679 | .links = { X1E80100_MASTER_A2NOC_SNOC }, | |
680 | }; | |
681 | ||
9f196772 RN |
682 | static struct qcom_icc_node qup0_core_slave = { |
683 | .name = "qup0_core_slave", | |
684 | .id = X1E80100_SLAVE_QUP_CORE_0, | |
685 | .channels = 1, | |
686 | .buswidth = 4, | |
687 | .num_links = 0, | |
688 | }; | |
689 | ||
690 | static struct qcom_icc_node qup1_core_slave = { | |
691 | .name = "qup1_core_slave", | |
692 | .id = X1E80100_SLAVE_QUP_CORE_1, | |
693 | .channels = 1, | |
694 | .buswidth = 4, | |
695 | .num_links = 0, | |
696 | }; | |
697 | ||
698 | static struct qcom_icc_node qup2_core_slave = { | |
699 | .name = "qup2_core_slave", | |
700 | .id = X1E80100_SLAVE_QUP_CORE_2, | |
701 | .channels = 1, | |
702 | .buswidth = 4, | |
703 | .num_links = 0, | |
704 | }; | |
705 | ||
706 | static struct qcom_icc_node qhs_ahb2phy0 = { | |
707 | .name = "qhs_ahb2phy0", | |
708 | .id = X1E80100_SLAVE_AHB2PHY_SOUTH, | |
709 | .channels = 1, | |
710 | .buswidth = 4, | |
711 | .num_links = 0, | |
712 | }; | |
713 | ||
714 | static struct qcom_icc_node qhs_ahb2phy1 = { | |
715 | .name = "qhs_ahb2phy1", | |
716 | .id = X1E80100_SLAVE_AHB2PHY_NORTH, | |
717 | .channels = 1, | |
718 | .buswidth = 4, | |
719 | .num_links = 0, | |
720 | }; | |
721 | ||
722 | static struct qcom_icc_node qhs_ahb2phy2 = { | |
723 | .name = "qhs_ahb2phy2", | |
724 | .id = X1E80100_SLAVE_AHB2PHY_2, | |
725 | .channels = 1, | |
726 | .buswidth = 4, | |
727 | .num_links = 0, | |
728 | }; | |
729 | ||
730 | static struct qcom_icc_node qhs_av1_enc_cfg = { | |
731 | .name = "qhs_av1_enc_cfg", | |
732 | .id = X1E80100_SLAVE_AV1_ENC_CFG, | |
733 | .channels = 1, | |
734 | .buswidth = 4, | |
735 | .num_links = 0, | |
736 | }; | |
737 | ||
738 | static struct qcom_icc_node qhs_camera_cfg = { | |
739 | .name = "qhs_camera_cfg", | |
740 | .id = X1E80100_SLAVE_CAMERA_CFG, | |
741 | .channels = 1, | |
742 | .buswidth = 4, | |
743 | .num_links = 0, | |
744 | }; | |
745 | ||
746 | static struct qcom_icc_node qhs_clk_ctl = { | |
747 | .name = "qhs_clk_ctl", | |
748 | .id = X1E80100_SLAVE_CLK_CTL, | |
749 | .channels = 1, | |
750 | .buswidth = 4, | |
751 | .num_links = 0, | |
752 | }; | |
753 | ||
754 | static struct qcom_icc_node qhs_crypto0_cfg = { | |
755 | .name = "qhs_crypto0_cfg", | |
756 | .id = X1E80100_SLAVE_CRYPTO_0_CFG, | |
757 | .channels = 1, | |
758 | .buswidth = 4, | |
759 | .num_links = 0, | |
760 | }; | |
761 | ||
762 | static struct qcom_icc_node qhs_display_cfg = { | |
763 | .name = "qhs_display_cfg", | |
764 | .id = X1E80100_SLAVE_DISPLAY_CFG, | |
765 | .channels = 1, | |
766 | .buswidth = 4, | |
767 | .num_links = 0, | |
768 | }; | |
769 | ||
770 | static struct qcom_icc_node qhs_gpuss_cfg = { | |
771 | .name = "qhs_gpuss_cfg", | |
772 | .id = X1E80100_SLAVE_GFX3D_CFG, | |
773 | .channels = 1, | |
774 | .buswidth = 8, | |
775 | .num_links = 0, | |
776 | }; | |
777 | ||
778 | static struct qcom_icc_node qhs_imem_cfg = { | |
779 | .name = "qhs_imem_cfg", | |
780 | .id = X1E80100_SLAVE_IMEM_CFG, | |
781 | .channels = 1, | |
782 | .buswidth = 4, | |
783 | .num_links = 0, | |
784 | }; | |
785 | ||
786 | static struct qcom_icc_node qhs_ipc_router = { | |
787 | .name = "qhs_ipc_router", | |
788 | .id = X1E80100_SLAVE_IPC_ROUTER_CFG, | |
789 | .channels = 1, | |
790 | .buswidth = 4, | |
791 | .num_links = 0, | |
792 | }; | |
793 | ||
794 | static struct qcom_icc_node qhs_pcie0_cfg = { | |
795 | .name = "qhs_pcie0_cfg", | |
796 | .id = X1E80100_SLAVE_PCIE_0_CFG, | |
797 | .channels = 1, | |
798 | .buswidth = 4, | |
799 | .num_links = 0, | |
800 | }; | |
801 | ||
802 | static struct qcom_icc_node qhs_pcie1_cfg = { | |
803 | .name = "qhs_pcie1_cfg", | |
804 | .id = X1E80100_SLAVE_PCIE_1_CFG, | |
805 | .channels = 1, | |
806 | .buswidth = 4, | |
807 | .num_links = 0, | |
808 | }; | |
809 | ||
810 | static struct qcom_icc_node qhs_pcie2_cfg = { | |
811 | .name = "qhs_pcie2_cfg", | |
812 | .id = X1E80100_SLAVE_PCIE_2_CFG, | |
813 | .channels = 1, | |
814 | .buswidth = 4, | |
815 | .num_links = 0, | |
816 | }; | |
817 | ||
818 | static struct qcom_icc_node qhs_pcie3_cfg = { | |
819 | .name = "qhs_pcie3_cfg", | |
820 | .id = X1E80100_SLAVE_PCIE_3_CFG, | |
821 | .channels = 1, | |
822 | .buswidth = 4, | |
823 | .num_links = 0, | |
824 | }; | |
825 | ||
826 | static struct qcom_icc_node qhs_pcie4_cfg = { | |
827 | .name = "qhs_pcie4_cfg", | |
828 | .id = X1E80100_SLAVE_PCIE_4_CFG, | |
829 | .channels = 1, | |
830 | .buswidth = 4, | |
831 | .num_links = 0, | |
832 | }; | |
833 | ||
834 | static struct qcom_icc_node qhs_pcie5_cfg = { | |
835 | .name = "qhs_pcie5_cfg", | |
836 | .id = X1E80100_SLAVE_PCIE_5_CFG, | |
837 | .channels = 1, | |
838 | .buswidth = 4, | |
839 | .num_links = 0, | |
840 | }; | |
841 | ||
842 | static struct qcom_icc_node qhs_pcie6a_cfg = { | |
843 | .name = "qhs_pcie6a_cfg", | |
844 | .id = X1E80100_SLAVE_PCIE_6A_CFG, | |
845 | .channels = 1, | |
846 | .buswidth = 4, | |
847 | .num_links = 0, | |
848 | }; | |
849 | ||
850 | static struct qcom_icc_node qhs_pcie6b_cfg = { | |
851 | .name = "qhs_pcie6b_cfg", | |
852 | .id = X1E80100_SLAVE_PCIE_6B_CFG, | |
853 | .channels = 1, | |
854 | .buswidth = 4, | |
855 | .num_links = 0, | |
856 | }; | |
857 | ||
858 | static struct qcom_icc_node qhs_pcie_rsc_cfg = { | |
859 | .name = "qhs_pcie_rsc_cfg", | |
860 | .id = X1E80100_SLAVE_PCIE_RSC_CFG, | |
861 | .channels = 1, | |
862 | .buswidth = 4, | |
863 | .num_links = 0, | |
864 | }; | |
865 | ||
866 | static struct qcom_icc_node qhs_pdm = { | |
867 | .name = "qhs_pdm", | |
868 | .id = X1E80100_SLAVE_PDM, | |
869 | .channels = 1, | |
870 | .buswidth = 4, | |
871 | .num_links = 0, | |
872 | }; | |
873 | ||
874 | static struct qcom_icc_node qhs_prng = { | |
875 | .name = "qhs_prng", | |
876 | .id = X1E80100_SLAVE_PRNG, | |
877 | .channels = 1, | |
878 | .buswidth = 4, | |
879 | .num_links = 0, | |
880 | }; | |
881 | ||
882 | static struct qcom_icc_node qhs_qdss_cfg = { | |
883 | .name = "qhs_qdss_cfg", | |
884 | .id = X1E80100_SLAVE_QDSS_CFG, | |
885 | .channels = 1, | |
886 | .buswidth = 4, | |
887 | .num_links = 0, | |
888 | }; | |
889 | ||
890 | static struct qcom_icc_node qhs_qspi = { | |
891 | .name = "qhs_qspi", | |
892 | .id = X1E80100_SLAVE_QSPI_0, | |
893 | .channels = 1, | |
894 | .buswidth = 4, | |
895 | .num_links = 0, | |
896 | }; | |
897 | ||
898 | static struct qcom_icc_node qhs_qup0 = { | |
899 | .name = "qhs_qup0", | |
900 | .id = X1E80100_SLAVE_QUP_0, | |
901 | .channels = 1, | |
902 | .buswidth = 4, | |
903 | .num_links = 0, | |
904 | }; | |
905 | ||
906 | static struct qcom_icc_node qhs_qup1 = { | |
907 | .name = "qhs_qup1", | |
908 | .id = X1E80100_SLAVE_QUP_1, | |
909 | .channels = 1, | |
910 | .buswidth = 4, | |
911 | .num_links = 0, | |
912 | }; | |
913 | ||
914 | static struct qcom_icc_node qhs_qup2 = { | |
915 | .name = "qhs_qup2", | |
916 | .id = X1E80100_SLAVE_QUP_2, | |
917 | .channels = 1, | |
918 | .buswidth = 4, | |
919 | .num_links = 0, | |
920 | }; | |
921 | ||
922 | static struct qcom_icc_node qhs_sdc2 = { | |
923 | .name = "qhs_sdc2", | |
924 | .id = X1E80100_SLAVE_SDCC_2, | |
925 | .channels = 1, | |
926 | .buswidth = 4, | |
927 | .num_links = 0, | |
928 | }; | |
929 | ||
930 | static struct qcom_icc_node qhs_sdc4 = { | |
931 | .name = "qhs_sdc4", | |
932 | .id = X1E80100_SLAVE_SDCC_4, | |
933 | .channels = 1, | |
934 | .buswidth = 4, | |
935 | .num_links = 0, | |
936 | }; | |
937 | ||
938 | static struct qcom_icc_node qhs_smmuv3_cfg = { | |
939 | .name = "qhs_smmuv3_cfg", | |
940 | .id = X1E80100_SLAVE_SMMUV3_CFG, | |
941 | .channels = 1, | |
942 | .buswidth = 8, | |
943 | .num_links = 0, | |
944 | }; | |
945 | ||
946 | static struct qcom_icc_node qhs_tcsr = { | |
947 | .name = "qhs_tcsr", | |
948 | .id = X1E80100_SLAVE_TCSR, | |
949 | .channels = 1, | |
950 | .buswidth = 4, | |
951 | .num_links = 0, | |
952 | }; | |
953 | ||
954 | static struct qcom_icc_node qhs_tlmm = { | |
955 | .name = "qhs_tlmm", | |
956 | .id = X1E80100_SLAVE_TLMM, | |
957 | .channels = 1, | |
958 | .buswidth = 4, | |
959 | .num_links = 0, | |
960 | }; | |
961 | ||
962 | static struct qcom_icc_node qhs_ufs_mem_cfg = { | |
963 | .name = "qhs_ufs_mem_cfg", | |
964 | .id = X1E80100_SLAVE_UFS_MEM_CFG, | |
965 | .channels = 1, | |
966 | .buswidth = 4, | |
967 | .num_links = 0, | |
968 | }; | |
969 | ||
970 | static struct qcom_icc_node qhs_usb2_0_cfg = { | |
971 | .name = "qhs_usb2_0_cfg", | |
972 | .id = X1E80100_SLAVE_USB2, | |
973 | .channels = 1, | |
974 | .buswidth = 4, | |
975 | .num_links = 0, | |
976 | }; | |
977 | ||
978 | static struct qcom_icc_node qhs_usb3_0_cfg = { | |
979 | .name = "qhs_usb3_0_cfg", | |
980 | .id = X1E80100_SLAVE_USB3_0, | |
981 | .channels = 1, | |
982 | .buswidth = 4, | |
983 | .num_links = 0, | |
984 | }; | |
985 | ||
986 | static struct qcom_icc_node qhs_usb3_1_cfg = { | |
987 | .name = "qhs_usb3_1_cfg", | |
988 | .id = X1E80100_SLAVE_USB3_1, | |
989 | .channels = 1, | |
990 | .buswidth = 4, | |
991 | .num_links = 0, | |
992 | }; | |
993 | ||
994 | static struct qcom_icc_node qhs_usb3_2_cfg = { | |
995 | .name = "qhs_usb3_2_cfg", | |
996 | .id = X1E80100_SLAVE_USB3_2, | |
997 | .channels = 1, | |
998 | .buswidth = 4, | |
999 | .num_links = 0, | |
1000 | }; | |
1001 | ||
1002 | static struct qcom_icc_node qhs_usb3_mp_cfg = { | |
1003 | .name = "qhs_usb3_mp_cfg", | |
1004 | .id = X1E80100_SLAVE_USB3_MP, | |
1005 | .channels = 1, | |
1006 | .buswidth = 4, | |
1007 | .num_links = 0, | |
1008 | }; | |
1009 | ||
1010 | static struct qcom_icc_node qhs_usb4_0_cfg = { | |
1011 | .name = "qhs_usb4_0_cfg", | |
1012 | .id = X1E80100_SLAVE_USB4_0, | |
1013 | .channels = 1, | |
1014 | .buswidth = 4, | |
1015 | .num_links = 0, | |
1016 | }; | |
1017 | ||
1018 | static struct qcom_icc_node qhs_usb4_1_cfg = { | |
1019 | .name = "qhs_usb4_1_cfg", | |
1020 | .id = X1E80100_SLAVE_USB4_1, | |
1021 | .channels = 1, | |
1022 | .buswidth = 4, | |
1023 | .num_links = 0, | |
1024 | }; | |
1025 | ||
1026 | static struct qcom_icc_node qhs_usb4_2_cfg = { | |
1027 | .name = "qhs_usb4_2_cfg", | |
1028 | .id = X1E80100_SLAVE_USB4_2, | |
1029 | .channels = 1, | |
1030 | .buswidth = 4, | |
1031 | .num_links = 0, | |
1032 | }; | |
1033 | ||
1034 | static struct qcom_icc_node qhs_venus_cfg = { | |
1035 | .name = "qhs_venus_cfg", | |
1036 | .id = X1E80100_SLAVE_VENUS_CFG, | |
1037 | .channels = 1, | |
1038 | .buswidth = 4, | |
1039 | .num_links = 0, | |
1040 | }; | |
1041 | ||
1042 | static struct qcom_icc_node qss_lpass_qtb_cfg = { | |
1043 | .name = "qss_lpass_qtb_cfg", | |
1044 | .id = X1E80100_SLAVE_LPASS_QTB_CFG, | |
1045 | .channels = 1, | |
1046 | .buswidth = 4, | |
1047 | .num_links = 0, | |
1048 | }; | |
1049 | ||
1050 | static struct qcom_icc_node qss_mnoc_cfg = { | |
1051 | .name = "qss_mnoc_cfg", | |
1052 | .id = X1E80100_SLAVE_CNOC_MNOC_CFG, | |
1053 | .channels = 1, | |
1054 | .buswidth = 4, | |
1055 | .num_links = 1, | |
1056 | .links = { X1E80100_MASTER_CNOC_MNOC_CFG }, | |
1057 | }; | |
1058 | ||
1059 | static struct qcom_icc_node qss_nsp_qtb_cfg = { | |
1060 | .name = "qss_nsp_qtb_cfg", | |
1061 | .id = X1E80100_SLAVE_NSP_QTB_CFG, | |
1062 | .channels = 1, | |
1063 | .buswidth = 4, | |
1064 | .num_links = 0, | |
1065 | }; | |
1066 | ||
1067 | static struct qcom_icc_node xs_qdss_stm = { | |
1068 | .name = "xs_qdss_stm", | |
1069 | .id = X1E80100_SLAVE_QDSS_STM, | |
1070 | .channels = 1, | |
1071 | .buswidth = 4, | |
1072 | .num_links = 0, | |
1073 | }; | |
1074 | ||
1075 | static struct qcom_icc_node xs_sys_tcu_cfg = { | |
1076 | .name = "xs_sys_tcu_cfg", | |
1077 | .id = X1E80100_SLAVE_TCU, | |
1078 | .channels = 1, | |
1079 | .buswidth = 8, | |
1080 | .num_links = 0, | |
1081 | }; | |
1082 | ||
1083 | static struct qcom_icc_node qhs_aoss = { | |
1084 | .name = "qhs_aoss", | |
1085 | .id = X1E80100_SLAVE_AOSS, | |
1086 | .channels = 1, | |
1087 | .buswidth = 4, | |
1088 | .num_links = 0, | |
1089 | }; | |
1090 | ||
1091 | static struct qcom_icc_node qhs_tme_cfg = { | |
1092 | .name = "qhs_tme_cfg", | |
1093 | .id = X1E80100_SLAVE_TME_CFG, | |
1094 | .channels = 1, | |
1095 | .buswidth = 4, | |
1096 | .num_links = 0, | |
1097 | }; | |
1098 | ||
1099 | static struct qcom_icc_node qns_apss = { | |
1100 | .name = "qns_apss", | |
1101 | .id = X1E80100_SLAVE_APPSS, | |
1102 | .channels = 1, | |
1103 | .buswidth = 8, | |
1104 | .num_links = 0, | |
1105 | }; | |
1106 | ||
1107 | static struct qcom_icc_node qss_cfg = { | |
1108 | .name = "qss_cfg", | |
1109 | .id = X1E80100_SLAVE_CNOC_CFG, | |
1110 | .channels = 1, | |
1111 | .buswidth = 4, | |
1112 | .num_links = 1, | |
1113 | .links = { X1E80100_MASTER_CNOC_CFG }, | |
1114 | }; | |
1115 | ||
1116 | static struct qcom_icc_node qxs_boot_imem = { | |
1117 | .name = "qxs_boot_imem", | |
1118 | .id = X1E80100_SLAVE_BOOT_IMEM, | |
1119 | .channels = 1, | |
1120 | .buswidth = 16, | |
1121 | .num_links = 0, | |
1122 | }; | |
1123 | ||
1124 | static struct qcom_icc_node qxs_imem = { | |
1125 | .name = "qxs_imem", | |
1126 | .id = X1E80100_SLAVE_IMEM, | |
1127 | .channels = 1, | |
1128 | .buswidth = 8, | |
1129 | .num_links = 0, | |
1130 | }; | |
1131 | ||
1132 | static struct qcom_icc_node xs_pcie_0 = { | |
1133 | .name = "xs_pcie_0", | |
1134 | .id = X1E80100_SLAVE_PCIE_0, | |
1135 | .channels = 1, | |
1136 | .buswidth = 16, | |
1137 | .num_links = 0, | |
1138 | }; | |
1139 | ||
1140 | static struct qcom_icc_node xs_pcie_1 = { | |
1141 | .name = "xs_pcie_1", | |
1142 | .id = X1E80100_SLAVE_PCIE_1, | |
1143 | .channels = 1, | |
1144 | .buswidth = 16, | |
1145 | .num_links = 0, | |
1146 | }; | |
1147 | ||
1148 | static struct qcom_icc_node xs_pcie_2 = { | |
1149 | .name = "xs_pcie_2", | |
1150 | .id = X1E80100_SLAVE_PCIE_2, | |
1151 | .channels = 1, | |
1152 | .buswidth = 16, | |
1153 | .num_links = 0, | |
1154 | }; | |
1155 | ||
1156 | static struct qcom_icc_node xs_pcie_3 = { | |
1157 | .name = "xs_pcie_3", | |
1158 | .id = X1E80100_SLAVE_PCIE_3, | |
1159 | .channels = 1, | |
1160 | .buswidth = 64, | |
1161 | .num_links = 0, | |
1162 | }; | |
1163 | ||
1164 | static struct qcom_icc_node xs_pcie_4 = { | |
1165 | .name = "xs_pcie_4", | |
1166 | .id = X1E80100_SLAVE_PCIE_4, | |
1167 | .channels = 1, | |
1168 | .buswidth = 8, | |
1169 | .num_links = 0, | |
1170 | }; | |
1171 | ||
1172 | static struct qcom_icc_node xs_pcie_5 = { | |
1173 | .name = "xs_pcie_5", | |
1174 | .id = X1E80100_SLAVE_PCIE_5, | |
1175 | .channels = 1, | |
1176 | .buswidth = 8, | |
1177 | .num_links = 0, | |
1178 | }; | |
1179 | ||
1180 | static struct qcom_icc_node xs_pcie_6a = { | |
1181 | .name = "xs_pcie_6a", | |
1182 | .id = X1E80100_SLAVE_PCIE_6A, | |
1183 | .channels = 1, | |
1184 | .buswidth = 32, | |
1185 | .num_links = 0, | |
1186 | }; | |
1187 | ||
1188 | static struct qcom_icc_node xs_pcie_6b = { | |
1189 | .name = "xs_pcie_6b", | |
1190 | .id = X1E80100_SLAVE_PCIE_6B, | |
1191 | .channels = 1, | |
1192 | .buswidth = 16, | |
1193 | .num_links = 0, | |
1194 | }; | |
1195 | ||
1196 | static struct qcom_icc_node qns_gem_noc_cnoc = { | |
1197 | .name = "qns_gem_noc_cnoc", | |
1198 | .id = X1E80100_SLAVE_GEM_NOC_CNOC, | |
1199 | .channels = 1, | |
1200 | .buswidth = 16, | |
1201 | .num_links = 1, | |
1202 | .links = { X1E80100_MASTER_GEM_NOC_CNOC }, | |
1203 | }; | |
1204 | ||
1205 | static struct qcom_icc_node qns_llcc = { | |
1206 | .name = "qns_llcc", | |
1207 | .id = X1E80100_SLAVE_LLCC, | |
1208 | .channels = 8, | |
1209 | .buswidth = 16, | |
1210 | .num_links = 1, | |
1211 | .links = { X1E80100_MASTER_LLCC }, | |
1212 | }; | |
1213 | ||
1214 | static struct qcom_icc_node qns_pcie = { | |
1215 | .name = "qns_pcie", | |
1216 | .id = X1E80100_SLAVE_MEM_NOC_PCIE_SNOC, | |
1217 | .channels = 1, | |
1218 | .buswidth = 32, | |
1219 | .num_links = 1, | |
1220 | .links = { X1E80100_MASTER_GEM_NOC_PCIE_SNOC }, | |
1221 | }; | |
1222 | ||
1223 | static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { | |
1224 | .name = "qns_lpass_ag_noc_gemnoc", | |
1225 | .id = X1E80100_SLAVE_LPASS_GEM_NOC, | |
1226 | .channels = 1, | |
1227 | .buswidth = 16, | |
1228 | .num_links = 1, | |
1229 | .links = { X1E80100_MASTER_LPASS_GEM_NOC }, | |
1230 | }; | |
1231 | ||
1232 | static struct qcom_icc_node qns_lpass_aggnoc = { | |
1233 | .name = "qns_lpass_aggnoc", | |
1234 | .id = X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC, | |
1235 | .channels = 1, | |
1236 | .buswidth = 16, | |
1237 | .num_links = 1, | |
1238 | .links = { X1E80100_MASTER_LPIAON_NOC }, | |
1239 | }; | |
1240 | ||
1241 | static struct qcom_icc_node qns_lpi_aon_noc = { | |
1242 | .name = "qns_lpi_aon_noc", | |
1243 | .id = X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC, | |
1244 | .channels = 1, | |
1245 | .buswidth = 16, | |
1246 | .num_links = 1, | |
1247 | .links = { X1E80100_MASTER_LPASS_LPINOC }, | |
1248 | }; | |
1249 | ||
1250 | static struct qcom_icc_node ebi = { | |
1251 | .name = "ebi", | |
1252 | .id = X1E80100_SLAVE_EBI1, | |
1253 | .channels = 8, | |
1254 | .buswidth = 4, | |
1255 | .num_links = 0, | |
1256 | }; | |
1257 | ||
1258 | static struct qcom_icc_node qns_mem_noc_hf = { | |
1259 | .name = "qns_mem_noc_hf", | |
1260 | .id = X1E80100_SLAVE_MNOC_HF_MEM_NOC, | |
1261 | .channels = 2, | |
1262 | .buswidth = 32, | |
1263 | .num_links = 1, | |
1264 | .links = { X1E80100_MASTER_MNOC_HF_MEM_NOC }, | |
1265 | }; | |
1266 | ||
1267 | static struct qcom_icc_node qns_mem_noc_sf = { | |
1268 | .name = "qns_mem_noc_sf", | |
1269 | .id = X1E80100_SLAVE_MNOC_SF_MEM_NOC, | |
1270 | .channels = 2, | |
1271 | .buswidth = 32, | |
1272 | .num_links = 1, | |
1273 | .links = { X1E80100_MASTER_MNOC_SF_MEM_NOC }, | |
1274 | }; | |
1275 | ||
1276 | static struct qcom_icc_node srvc_mnoc = { | |
1277 | .name = "srvc_mnoc", | |
1278 | .id = X1E80100_SLAVE_SERVICE_MNOC, | |
1279 | .channels = 1, | |
1280 | .buswidth = 4, | |
1281 | .num_links = 0, | |
1282 | }; | |
1283 | ||
1284 | static struct qcom_icc_node qns_nsp_gemnoc = { | |
1285 | .name = "qns_nsp_gemnoc", | |
1286 | .id = X1E80100_SLAVE_CDSP_MEM_NOC, | |
1287 | .channels = 2, | |
1288 | .buswidth = 32, | |
1289 | .num_links = 1, | |
1290 | .links = { X1E80100_MASTER_COMPUTE_NOC }, | |
1291 | }; | |
1292 | ||
1293 | static struct qcom_icc_node qns_pcie_mem_noc = { | |
1294 | .name = "qns_pcie_mem_noc", | |
1295 | .id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC, | |
1296 | .channels = 1, | |
1297 | .buswidth = 64, | |
1298 | .num_links = 1, | |
1299 | .links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC }, | |
1300 | }; | |
1301 | ||
1302 | static struct qcom_icc_node qns_pcie_north_gem_noc = { | |
1303 | .name = "qns_pcie_north_gem_noc", | |
1304 | .id = X1E80100_SLAVE_PCIE_NORTH, | |
1305 | .channels = 1, | |
1306 | .buswidth = 64, | |
1307 | .num_links = 1, | |
1308 | .links = { X1E80100_MASTER_PCIE_NORTH }, | |
1309 | }; | |
1310 | ||
1311 | static struct qcom_icc_node qns_pcie_south_gem_noc = { | |
1312 | .name = "qns_pcie_south_gem_noc", | |
1313 | .id = X1E80100_SLAVE_PCIE_SOUTH, | |
1314 | .channels = 1, | |
1315 | .buswidth = 64, | |
1316 | .num_links = 1, | |
1317 | .links = { X1E80100_MASTER_PCIE_SOUTH }, | |
1318 | }; | |
1319 | ||
1320 | static struct qcom_icc_node qns_gemnoc_sf = { | |
1321 | .name = "qns_gemnoc_sf", | |
1322 | .id = X1E80100_SLAVE_SNOC_GEM_NOC_SF, | |
1323 | .channels = 1, | |
1324 | .buswidth = 64, | |
1325 | .num_links = 1, | |
1326 | .links = { X1E80100_MASTER_SNOC_SF_MEM_NOC }, | |
1327 | }; | |
1328 | ||
1329 | static struct qcom_icc_node qns_aggre_usb_snoc = { | |
1330 | .name = "qns_aggre_usb_snoc", | |
1331 | .id = X1E80100_SLAVE_USB_NOC_SNOC, | |
1332 | .channels = 1, | |
1333 | .buswidth = 64, | |
1334 | .num_links = 1, | |
1335 | .links = { X1E80100_MASTER_USB_NOC_SNOC }, | |
1336 | }; | |
1337 | ||
1338 | static struct qcom_icc_node qns_aggre_usb_north_snoc = { | |
1339 | .name = "qns_aggre_usb_north_snoc", | |
1340 | .id = X1E80100_SLAVE_AGGRE_USB_NORTH, | |
1341 | .channels = 1, | |
1342 | .buswidth = 64, | |
1343 | .num_links = 1, | |
1344 | .links = { X1E80100_MASTER_AGGRE_USB_NORTH }, | |
1345 | }; | |
1346 | ||
1347 | static struct qcom_icc_node qns_aggre_usb_south_snoc = { | |
1348 | .name = "qns_aggre_usb_south_snoc", | |
1349 | .id = X1E80100_SLAVE_AGGRE_USB_SOUTH, | |
1350 | .channels = 1, | |
1351 | .buswidth = 64, | |
1352 | .num_links = 1, | |
1353 | .links = { X1E80100_MASTER_AGGRE_USB_SOUTH }, | |
1354 | }; | |
1355 | ||
9f196772 RN |
1356 | static struct qcom_icc_bcm bcm_acv = { |
1357 | .name = "ACV", | |
5464e7ac | 1358 | .enable_mask = BIT(3), |
9f196772 RN |
1359 | .num_nodes = 1, |
1360 | .nodes = { &ebi }, | |
1361 | }; | |
1362 | ||
9f196772 RN |
1363 | static struct qcom_icc_bcm bcm_ce0 = { |
1364 | .name = "CE0", | |
1365 | .num_nodes = 1, | |
1366 | .nodes = { &qxm_crypto }, | |
1367 | }; | |
1368 | ||
1369 | static struct qcom_icc_bcm bcm_cn0 = { | |
1370 | .name = "CN0", | |
1371 | .keepalive = true, | |
1372 | .num_nodes = 63, | |
1373 | .nodes = { &qsm_cfg, &qhs_ahb2phy0, | |
1374 | &qhs_ahb2phy1, &qhs_ahb2phy2, | |
1375 | &qhs_av1_enc_cfg, &qhs_camera_cfg, | |
1376 | &qhs_clk_ctl, &qhs_crypto0_cfg, | |
1377 | &qhs_gpuss_cfg, &qhs_imem_cfg, | |
1378 | &qhs_ipc_router, &qhs_pcie0_cfg, | |
1379 | &qhs_pcie1_cfg, &qhs_pcie2_cfg, | |
1380 | &qhs_pcie3_cfg, &qhs_pcie4_cfg, | |
1381 | &qhs_pcie5_cfg, &qhs_pcie6a_cfg, | |
1382 | &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg, | |
1383 | &qhs_pdm, &qhs_prng, | |
1384 | &qhs_qdss_cfg, &qhs_qspi, | |
1385 | &qhs_qup0, &qhs_qup1, | |
1386 | &qhs_qup2, &qhs_sdc2, | |
1387 | &qhs_sdc4, &qhs_smmuv3_cfg, | |
1388 | &qhs_tcsr, &qhs_tlmm, | |
1389 | &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, | |
1390 | &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, | |
1391 | &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, | |
1392 | &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, | |
1393 | &qhs_usb4_2_cfg, &qhs_venus_cfg, | |
1394 | &qss_lpass_qtb_cfg, &qss_mnoc_cfg, | |
1395 | &qss_nsp_qtb_cfg, &xs_qdss_stm, | |
1396 | &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, | |
1397 | &qnm_gemnoc_pcie, &qhs_aoss, | |
1398 | &qhs_tme_cfg, &qns_apss, | |
1399 | &qss_cfg, &qxs_boot_imem, | |
1400 | &qxs_imem, &xs_pcie_0, | |
1401 | &xs_pcie_1, &xs_pcie_2, | |
1402 | &xs_pcie_3, &xs_pcie_4, | |
1403 | &xs_pcie_5, &xs_pcie_6a, | |
1404 | &xs_pcie_6b }, | |
1405 | }; | |
1406 | ||
1407 | static struct qcom_icc_bcm bcm_cn1 = { | |
1408 | .name = "CN1", | |
1409 | .num_nodes = 1, | |
1410 | .nodes = { &qhs_display_cfg }, | |
1411 | }; | |
1412 | ||
1413 | static struct qcom_icc_bcm bcm_co0 = { | |
1414 | .name = "CO0", | |
1415 | .num_nodes = 2, | |
1416 | .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, | |
1417 | }; | |
1418 | ||
1419 | static struct qcom_icc_bcm bcm_lp0 = { | |
1420 | .name = "LP0", | |
1421 | .num_nodes = 2, | |
1422 | .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, | |
1423 | }; | |
1424 | ||
1425 | static struct qcom_icc_bcm bcm_mc0 = { | |
1426 | .name = "MC0", | |
1427 | .keepalive = true, | |
1428 | .num_nodes = 1, | |
1429 | .nodes = { &ebi }, | |
1430 | }; | |
1431 | ||
1432 | static struct qcom_icc_bcm bcm_mm0 = { | |
1433 | .name = "MM0", | |
1434 | .num_nodes = 1, | |
1435 | .nodes = { &qns_mem_noc_hf }, | |
1436 | }; | |
1437 | ||
1438 | static struct qcom_icc_bcm bcm_mm1 = { | |
1439 | .name = "MM1", | |
1440 | .num_nodes = 10, | |
1441 | .nodes = { &qnm_av1_enc, &qnm_camnoc_hf, | |
1442 | &qnm_camnoc_icp, &qnm_camnoc_sf, | |
1443 | &qnm_eva, &qnm_mdp, | |
1444 | &qnm_video, &qnm_video_cv_cpu, | |
1445 | &qnm_video_v_cpu, &qns_mem_noc_sf }, | |
1446 | }; | |
1447 | ||
1448 | static struct qcom_icc_bcm bcm_pc0 = { | |
1449 | .name = "PC0", | |
1450 | .num_nodes = 1, | |
1451 | .nodes = { &qns_pcie_mem_noc }, | |
1452 | }; | |
1453 | ||
1454 | static struct qcom_icc_bcm bcm_qup0 = { | |
1455 | .name = "QUP0", | |
1456 | .keepalive = true, | |
1457 | .vote_scale = 1, | |
1458 | .num_nodes = 1, | |
1459 | .nodes = { &qup0_core_slave }, | |
1460 | }; | |
1461 | ||
1462 | static struct qcom_icc_bcm bcm_qup1 = { | |
1463 | .name = "QUP1", | |
1464 | .keepalive = true, | |
1465 | .vote_scale = 1, | |
1466 | .num_nodes = 1, | |
1467 | .nodes = { &qup1_core_slave }, | |
1468 | }; | |
1469 | ||
1470 | static struct qcom_icc_bcm bcm_qup2 = { | |
1471 | .name = "QUP2", | |
1472 | .keepalive = true, | |
1473 | .vote_scale = 1, | |
1474 | .num_nodes = 1, | |
1475 | .nodes = { &qup2_core_slave }, | |
1476 | }; | |
1477 | ||
1478 | static struct qcom_icc_bcm bcm_sh0 = { | |
1479 | .name = "SH0", | |
1480 | .keepalive = true, | |
1481 | .num_nodes = 1, | |
1482 | .nodes = { &qns_llcc }, | |
1483 | }; | |
1484 | ||
1485 | static struct qcom_icc_bcm bcm_sh1 = { | |
1486 | .name = "SH1", | |
1487 | .num_nodes = 13, | |
1488 | .nodes = { &alm_gpu_tcu, &alm_pcie_tcu, | |
1489 | &alm_sys_tcu, &chm_apps, | |
1490 | &qnm_gpu, &qnm_lpass, | |
1491 | &qnm_mnoc_hf, &qnm_mnoc_sf, | |
1492 | &qnm_nsp_noc, &qnm_pcie, | |
1493 | &xm_gic, &qns_gem_noc_cnoc, | |
1494 | &qns_pcie }, | |
1495 | }; | |
1496 | ||
1497 | static struct qcom_icc_bcm bcm_sn0 = { | |
1498 | .name = "SN0", | |
1499 | .keepalive = true, | |
1500 | .num_nodes = 1, | |
1501 | .nodes = { &qns_gemnoc_sf }, | |
1502 | }; | |
1503 | ||
1504 | static struct qcom_icc_bcm bcm_sn2 = { | |
1505 | .name = "SN2", | |
1506 | .num_nodes = 1, | |
1507 | .nodes = { &qnm_aggre1_noc }, | |
1508 | }; | |
1509 | ||
1510 | static struct qcom_icc_bcm bcm_sn3 = { | |
1511 | .name = "SN3", | |
1512 | .num_nodes = 1, | |
1513 | .nodes = { &qnm_aggre2_noc }, | |
1514 | }; | |
1515 | ||
1516 | static struct qcom_icc_bcm bcm_sn4 = { | |
1517 | .name = "SN4", | |
1518 | .num_nodes = 1, | |
1519 | .nodes = { &qnm_usb_anoc }, | |
1520 | }; | |
1521 | ||
a804adfb | 1522 | static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { |
9f196772 RN |
1523 | }; |
1524 | ||
1525 | static struct qcom_icc_node * const aggre1_noc_nodes[] = { | |
1526 | [MASTER_QSPI_0] = &qhm_qspi, | |
1527 | [MASTER_QUP_1] = &qhm_qup1, | |
1528 | [MASTER_SDCC_4] = &xm_sdc4, | |
1529 | [MASTER_UFS_MEM] = &xm_ufs_mem, | |
1530 | [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, | |
1531 | }; | |
1532 | ||
1533 | static const struct qcom_icc_desc x1e80100_aggre1_noc = { | |
1534 | .nodes = aggre1_noc_nodes, | |
1535 | .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), | |
1536 | .bcms = aggre1_noc_bcms, | |
1537 | .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), | |
1538 | }; | |
1539 | ||
1540 | static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { | |
1541 | &bcm_ce0, | |
1542 | }; | |
1543 | ||
1544 | static struct qcom_icc_node * const aggre2_noc_nodes[] = { | |
1545 | [MASTER_QUP_0] = &qhm_qup0, | |
1546 | [MASTER_QUP_2] = &qhm_qup2, | |
1547 | [MASTER_CRYPTO] = &qxm_crypto, | |
1548 | [MASTER_SP] = &qxm_sp, | |
1549 | [MASTER_QDSS_ETR] = &xm_qdss_etr_0, | |
1550 | [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, | |
1551 | [MASTER_SDCC_2] = &xm_sdc2, | |
1552 | [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, | |
1553 | }; | |
1554 | ||
1555 | static const struct qcom_icc_desc x1e80100_aggre2_noc = { | |
1556 | .nodes = aggre2_noc_nodes, | |
1557 | .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), | |
1558 | .bcms = aggre2_noc_bcms, | |
1559 | .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), | |
1560 | }; | |
1561 | ||
1562 | static struct qcom_icc_bcm * const clk_virt_bcms[] = { | |
9f196772 RN |
1563 | &bcm_qup0, |
1564 | &bcm_qup1, | |
1565 | &bcm_qup2, | |
1566 | }; | |
1567 | ||
1568 | static struct qcom_icc_node * const clk_virt_nodes[] = { | |
9f196772 RN |
1569 | [MASTER_QUP_CORE_0] = &qup0_core_master, |
1570 | [MASTER_QUP_CORE_1] = &qup1_core_master, | |
1571 | [MASTER_QUP_CORE_2] = &qup2_core_master, | |
9f196772 RN |
1572 | [SLAVE_QUP_CORE_0] = &qup0_core_slave, |
1573 | [SLAVE_QUP_CORE_1] = &qup1_core_slave, | |
1574 | [SLAVE_QUP_CORE_2] = &qup2_core_slave, | |
1575 | }; | |
1576 | ||
1577 | static const struct qcom_icc_desc x1e80100_clk_virt = { | |
1578 | .nodes = clk_virt_nodes, | |
1579 | .num_nodes = ARRAY_SIZE(clk_virt_nodes), | |
1580 | .bcms = clk_virt_bcms, | |
1581 | .num_bcms = ARRAY_SIZE(clk_virt_bcms), | |
1582 | }; | |
1583 | ||
1584 | static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { | |
1585 | &bcm_cn0, | |
1586 | &bcm_cn1, | |
1587 | }; | |
1588 | ||
1589 | static struct qcom_icc_node * const cnoc_cfg_nodes[] = { | |
1590 | [MASTER_CNOC_CFG] = &qsm_cfg, | |
1591 | [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, | |
1592 | [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, | |
1593 | [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, | |
1594 | [SLAVE_AV1_ENC_CFG] = &qhs_av1_enc_cfg, | |
1595 | [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, | |
1596 | [SLAVE_CLK_CTL] = &qhs_clk_ctl, | |
1597 | [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, | |
1598 | [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, | |
1599 | [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, | |
1600 | [SLAVE_IMEM_CFG] = &qhs_imem_cfg, | |
1601 | [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, | |
1602 | [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, | |
1603 | [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, | |
1604 | [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg, | |
1605 | [SLAVE_PCIE_3_CFG] = &qhs_pcie3_cfg, | |
1606 | [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, | |
1607 | [SLAVE_PCIE_5_CFG] = &qhs_pcie5_cfg, | |
1608 | [SLAVE_PCIE_6A_CFG] = &qhs_pcie6a_cfg, | |
1609 | [SLAVE_PCIE_6B_CFG] = &qhs_pcie6b_cfg, | |
1610 | [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, | |
1611 | [SLAVE_PDM] = &qhs_pdm, | |
1612 | [SLAVE_PRNG] = &qhs_prng, | |
1613 | [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, | |
1614 | [SLAVE_QSPI_0] = &qhs_qspi, | |
1615 | [SLAVE_QUP_0] = &qhs_qup0, | |
1616 | [SLAVE_QUP_1] = &qhs_qup1, | |
1617 | [SLAVE_QUP_2] = &qhs_qup2, | |
1618 | [SLAVE_SDCC_2] = &qhs_sdc2, | |
1619 | [SLAVE_SDCC_4] = &qhs_sdc4, | |
1620 | [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, | |
1621 | [SLAVE_TCSR] = &qhs_tcsr, | |
1622 | [SLAVE_TLMM] = &qhs_tlmm, | |
1623 | [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, | |
1624 | [SLAVE_USB2] = &qhs_usb2_0_cfg, | |
1625 | [SLAVE_USB3_0] = &qhs_usb3_0_cfg, | |
1626 | [SLAVE_USB3_1] = &qhs_usb3_1_cfg, | |
1627 | [SLAVE_USB3_2] = &qhs_usb3_2_cfg, | |
1628 | [SLAVE_USB3_MP] = &qhs_usb3_mp_cfg, | |
1629 | [SLAVE_USB4_0] = &qhs_usb4_0_cfg, | |
1630 | [SLAVE_USB4_1] = &qhs_usb4_1_cfg, | |
1631 | [SLAVE_USB4_2] = &qhs_usb4_2_cfg, | |
1632 | [SLAVE_VENUS_CFG] = &qhs_venus_cfg, | |
1633 | [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg, | |
1634 | [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, | |
1635 | [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg, | |
1636 | [SLAVE_QDSS_STM] = &xs_qdss_stm, | |
1637 | [SLAVE_TCU] = &xs_sys_tcu_cfg, | |
1638 | }; | |
1639 | ||
1640 | static const struct qcom_icc_desc x1e80100_cnoc_cfg = { | |
1641 | .nodes = cnoc_cfg_nodes, | |
1642 | .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), | |
1643 | .bcms = cnoc_cfg_bcms, | |
1644 | .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), | |
1645 | }; | |
1646 | ||
1647 | static struct qcom_icc_bcm * const cnoc_main_bcms[] = { | |
1648 | &bcm_cn0, | |
1649 | }; | |
1650 | ||
1651 | static struct qcom_icc_node * const cnoc_main_nodes[] = { | |
1652 | [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, | |
1653 | [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, | |
1654 | [SLAVE_AOSS] = &qhs_aoss, | |
1655 | [SLAVE_TME_CFG] = &qhs_tme_cfg, | |
1656 | [SLAVE_APPSS] = &qns_apss, | |
1657 | [SLAVE_CNOC_CFG] = &qss_cfg, | |
1658 | [SLAVE_BOOT_IMEM] = &qxs_boot_imem, | |
1659 | [SLAVE_IMEM] = &qxs_imem, | |
1660 | [SLAVE_PCIE_0] = &xs_pcie_0, | |
1661 | [SLAVE_PCIE_1] = &xs_pcie_1, | |
1662 | [SLAVE_PCIE_2] = &xs_pcie_2, | |
1663 | [SLAVE_PCIE_3] = &xs_pcie_3, | |
1664 | [SLAVE_PCIE_4] = &xs_pcie_4, | |
1665 | [SLAVE_PCIE_5] = &xs_pcie_5, | |
1666 | [SLAVE_PCIE_6A] = &xs_pcie_6a, | |
1667 | [SLAVE_PCIE_6B] = &xs_pcie_6b, | |
1668 | }; | |
1669 | ||
1670 | static const struct qcom_icc_desc x1e80100_cnoc_main = { | |
1671 | .nodes = cnoc_main_nodes, | |
1672 | .num_nodes = ARRAY_SIZE(cnoc_main_nodes), | |
1673 | .bcms = cnoc_main_bcms, | |
1674 | .num_bcms = ARRAY_SIZE(cnoc_main_bcms), | |
1675 | }; | |
1676 | ||
1677 | static struct qcom_icc_bcm * const gem_noc_bcms[] = { | |
1678 | &bcm_sh0, | |
1679 | &bcm_sh1, | |
9f196772 RN |
1680 | }; |
1681 | ||
1682 | static struct qcom_icc_node * const gem_noc_nodes[] = { | |
1683 | [MASTER_GPU_TCU] = &alm_gpu_tcu, | |
1684 | [MASTER_PCIE_TCU] = &alm_pcie_tcu, | |
1685 | [MASTER_SYS_TCU] = &alm_sys_tcu, | |
1686 | [MASTER_APPSS_PROC] = &chm_apps, | |
1687 | [MASTER_GFX3D] = &qnm_gpu, | |
1688 | [MASTER_LPASS_GEM_NOC] = &qnm_lpass, | |
1689 | [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, | |
1690 | [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, | |
1691 | [MASTER_COMPUTE_NOC] = &qnm_nsp_noc, | |
1692 | [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, | |
1693 | [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, | |
1694 | [MASTER_GIC2] = &xm_gic, | |
1695 | [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, | |
1696 | [SLAVE_LLCC] = &qns_llcc, | |
1697 | [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, | |
9f196772 RN |
1698 | }; |
1699 | ||
1700 | static const struct qcom_icc_desc x1e80100_gem_noc = { | |
1701 | .nodes = gem_noc_nodes, | |
1702 | .num_nodes = ARRAY_SIZE(gem_noc_nodes), | |
1703 | .bcms = gem_noc_bcms, | |
1704 | .num_bcms = ARRAY_SIZE(gem_noc_bcms), | |
1705 | }; | |
1706 | ||
a804adfb | 1707 | static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { |
9f196772 RN |
1708 | }; |
1709 | ||
1710 | static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { | |
1711 | [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, | |
1712 | [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, | |
1713 | }; | |
1714 | ||
1715 | static const struct qcom_icc_desc x1e80100_lpass_ag_noc = { | |
1716 | .nodes = lpass_ag_noc_nodes, | |
1717 | .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), | |
1718 | .bcms = lpass_ag_noc_bcms, | |
1719 | .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), | |
1720 | }; | |
1721 | ||
1722 | static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { | |
1723 | &bcm_lp0, | |
1724 | }; | |
1725 | ||
1726 | static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { | |
1727 | [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, | |
1728 | [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, | |
1729 | }; | |
1730 | ||
1731 | static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = { | |
1732 | .nodes = lpass_lpiaon_noc_nodes, | |
1733 | .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), | |
1734 | .bcms = lpass_lpiaon_noc_bcms, | |
1735 | .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), | |
1736 | }; | |
1737 | ||
1738 | static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = { | |
1739 | }; | |
1740 | ||
1741 | static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { | |
1742 | [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim, | |
1743 | [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, | |
1744 | }; | |
1745 | ||
1746 | static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = { | |
1747 | .nodes = lpass_lpicx_noc_nodes, | |
1748 | .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), | |
1749 | .bcms = lpass_lpicx_noc_bcms, | |
1750 | .num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms), | |
1751 | }; | |
1752 | ||
1753 | static struct qcom_icc_bcm * const mc_virt_bcms[] = { | |
1754 | &bcm_acv, | |
1755 | &bcm_mc0, | |
9f196772 RN |
1756 | }; |
1757 | ||
1758 | static struct qcom_icc_node * const mc_virt_nodes[] = { | |
1759 | [MASTER_LLCC] = &llcc_mc, | |
1760 | [SLAVE_EBI1] = &ebi, | |
9f196772 RN |
1761 | }; |
1762 | ||
1763 | static const struct qcom_icc_desc x1e80100_mc_virt = { | |
1764 | .nodes = mc_virt_nodes, | |
1765 | .num_nodes = ARRAY_SIZE(mc_virt_nodes), | |
1766 | .bcms = mc_virt_bcms, | |
1767 | .num_bcms = ARRAY_SIZE(mc_virt_bcms), | |
1768 | }; | |
1769 | ||
1770 | static struct qcom_icc_bcm * const mmss_noc_bcms[] = { | |
1771 | &bcm_mm0, | |
1772 | &bcm_mm1, | |
9f196772 RN |
1773 | }; |
1774 | ||
1775 | static struct qcom_icc_node * const mmss_noc_nodes[] = { | |
1776 | [MASTER_AV1_ENC] = &qnm_av1_enc, | |
1777 | [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, | |
1778 | [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, | |
1779 | [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, | |
1780 | [MASTER_EVA] = &qnm_eva, | |
1781 | [MASTER_MDP] = &qnm_mdp, | |
1782 | [MASTER_VIDEO] = &qnm_video, | |
1783 | [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, | |
1784 | [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, | |
1785 | [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, | |
1786 | [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, | |
1787 | [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, | |
1788 | [SLAVE_SERVICE_MNOC] = &srvc_mnoc, | |
9f196772 RN |
1789 | }; |
1790 | ||
1791 | static const struct qcom_icc_desc x1e80100_mmss_noc = { | |
1792 | .nodes = mmss_noc_nodes, | |
1793 | .num_nodes = ARRAY_SIZE(mmss_noc_nodes), | |
1794 | .bcms = mmss_noc_bcms, | |
1795 | .num_bcms = ARRAY_SIZE(mmss_noc_bcms), | |
1796 | }; | |
1797 | ||
1798 | static struct qcom_icc_bcm * const nsp_noc_bcms[] = { | |
1799 | &bcm_co0, | |
1800 | }; | |
1801 | ||
1802 | static struct qcom_icc_node * const nsp_noc_nodes[] = { | |
1803 | [MASTER_CDSP_PROC] = &qxm_nsp, | |
1804 | [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, | |
1805 | }; | |
1806 | ||
1807 | static const struct qcom_icc_desc x1e80100_nsp_noc = { | |
1808 | .nodes = nsp_noc_nodes, | |
1809 | .num_nodes = ARRAY_SIZE(nsp_noc_nodes), | |
1810 | .bcms = nsp_noc_bcms, | |
1811 | .num_bcms = ARRAY_SIZE(nsp_noc_bcms), | |
1812 | }; | |
1813 | ||
1814 | static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = { | |
1815 | &bcm_pc0, | |
9f196772 RN |
1816 | }; |
1817 | ||
1818 | static struct qcom_icc_node * const pcie_center_anoc_nodes[] = { | |
1819 | [MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc, | |
1820 | [MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc, | |
1821 | [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, | |
9f196772 RN |
1822 | }; |
1823 | ||
1824 | static const struct qcom_icc_desc x1e80100_pcie_center_anoc = { | |
1825 | .nodes = pcie_center_anoc_nodes, | |
1826 | .num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes), | |
1827 | .bcms = pcie_center_anoc_bcms, | |
1828 | .num_bcms = ARRAY_SIZE(pcie_center_anoc_bcms), | |
1829 | }; | |
1830 | ||
1831 | static struct qcom_icc_bcm * const pcie_north_anoc_bcms[] = { | |
1832 | }; | |
1833 | ||
1834 | static struct qcom_icc_node * const pcie_north_anoc_nodes[] = { | |
1835 | [MASTER_PCIE_3] = &xm_pcie_3, | |
1836 | [MASTER_PCIE_4] = &xm_pcie_4, | |
1837 | [MASTER_PCIE_5] = &xm_pcie_5, | |
1838 | [SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc, | |
9f196772 RN |
1839 | }; |
1840 | ||
1841 | static const struct qcom_icc_desc x1e80100_pcie_north_anoc = { | |
1842 | .nodes = pcie_north_anoc_nodes, | |
1843 | .num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes), | |
1844 | .bcms = pcie_north_anoc_bcms, | |
1845 | .num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms), | |
1846 | }; | |
1847 | ||
a804adfb | 1848 | static struct qcom_icc_bcm * const pcie_south_anoc_bcms[] = { |
9f196772 RN |
1849 | }; |
1850 | ||
1851 | static struct qcom_icc_node * const pcie_south_anoc_nodes[] = { | |
1852 | [MASTER_PCIE_0] = &xm_pcie_0, | |
1853 | [MASTER_PCIE_1] = &xm_pcie_1, | |
1854 | [MASTER_PCIE_2] = &xm_pcie_2, | |
1855 | [MASTER_PCIE_6A] = &xm_pcie_6a, | |
1856 | [MASTER_PCIE_6B] = &xm_pcie_6b, | |
1857 | [SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc, | |
9f196772 RN |
1858 | }; |
1859 | ||
1860 | static const struct qcom_icc_desc x1e80100_pcie_south_anoc = { | |
1861 | .nodes = pcie_south_anoc_nodes, | |
1862 | .num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes), | |
1863 | .bcms = pcie_south_anoc_bcms, | |
1864 | .num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms), | |
1865 | }; | |
1866 | ||
a804adfb | 1867 | static struct qcom_icc_bcm * const system_noc_bcms[] = { |
9f196772 RN |
1868 | &bcm_sn0, |
1869 | &bcm_sn2, | |
1870 | &bcm_sn3, | |
1871 | &bcm_sn4, | |
1872 | }; | |
1873 | ||
1874 | static struct qcom_icc_node * const system_noc_nodes[] = { | |
1875 | [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, | |
1876 | [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, | |
1877 | [MASTER_GIC1] = &qnm_gic, | |
1878 | [MASTER_USB_NOC_SNOC] = &qnm_usb_anoc, | |
1879 | [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, | |
1880 | }; | |
1881 | ||
1882 | static const struct qcom_icc_desc x1e80100_system_noc = { | |
1883 | .nodes = system_noc_nodes, | |
1884 | .num_nodes = ARRAY_SIZE(system_noc_nodes), | |
1885 | .bcms = system_noc_bcms, | |
1886 | .num_bcms = ARRAY_SIZE(system_noc_bcms), | |
1887 | }; | |
1888 | ||
1889 | static struct qcom_icc_bcm * const usb_center_anoc_bcms[] = { | |
1890 | }; | |
1891 | ||
1892 | static struct qcom_icc_node * const usb_center_anoc_nodes[] = { | |
1893 | [MASTER_AGGRE_USB_NORTH] = &qnm_aggre_usb_north_snoc, | |
1894 | [MASTER_AGGRE_USB_SOUTH] = &qnm_aggre_usb_south_snoc, | |
1895 | [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc, | |
1896 | }; | |
1897 | ||
1898 | static const struct qcom_icc_desc x1e80100_usb_center_anoc = { | |
1899 | .nodes = usb_center_anoc_nodes, | |
1900 | .num_nodes = ARRAY_SIZE(usb_center_anoc_nodes), | |
1901 | .bcms = usb_center_anoc_bcms, | |
1902 | .num_bcms = ARRAY_SIZE(usb_center_anoc_bcms), | |
1903 | }; | |
1904 | ||
a804adfb | 1905 | static struct qcom_icc_bcm * const usb_north_anoc_bcms[] = { |
9f196772 RN |
1906 | }; |
1907 | ||
1908 | static struct qcom_icc_node * const usb_north_anoc_nodes[] = { | |
1909 | [MASTER_USB2] = &xm_usb2_0, | |
1910 | [MASTER_USB3_MP] = &xm_usb3_mp, | |
1911 | [SLAVE_AGGRE_USB_NORTH] = &qns_aggre_usb_north_snoc, | |
1912 | }; | |
1913 | ||
1914 | static const struct qcom_icc_desc x1e80100_usb_north_anoc = { | |
1915 | .nodes = usb_north_anoc_nodes, | |
1916 | .num_nodes = ARRAY_SIZE(usb_north_anoc_nodes), | |
1917 | .bcms = usb_north_anoc_bcms, | |
1918 | .num_bcms = ARRAY_SIZE(usb_north_anoc_bcms), | |
1919 | }; | |
1920 | ||
a804adfb | 1921 | static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = { |
9f196772 RN |
1922 | }; |
1923 | ||
1924 | static struct qcom_icc_node * const usb_south_anoc_nodes[] = { | |
1925 | [MASTER_USB3_0] = &xm_usb3_0, | |
1926 | [MASTER_USB3_1] = &xm_usb3_1, | |
1927 | [MASTER_USB3_2] = &xm_usb3_2, | |
1928 | [MASTER_USB4_0] = &xm_usb4_0, | |
1929 | [MASTER_USB4_1] = &xm_usb4_1, | |
1930 | [MASTER_USB4_2] = &xm_usb4_2, | |
1931 | [SLAVE_AGGRE_USB_SOUTH] = &qns_aggre_usb_south_snoc, | |
1932 | }; | |
1933 | ||
1934 | static const struct qcom_icc_desc x1e80100_usb_south_anoc = { | |
1935 | .nodes = usb_south_anoc_nodes, | |
1936 | .num_nodes = ARRAY_SIZE(usb_south_anoc_nodes), | |
1937 | .bcms = usb_south_anoc_bcms, | |
1938 | .num_bcms = ARRAY_SIZE(usb_south_anoc_bcms), | |
1939 | }; | |
1940 | ||
1941 | static const struct of_device_id qnoc_of_match[] = { | |
1942 | { .compatible = "qcom,x1e80100-aggre1-noc", .data = &x1e80100_aggre1_noc}, | |
1943 | { .compatible = "qcom,x1e80100-aggre2-noc", .data = &x1e80100_aggre2_noc}, | |
1944 | { .compatible = "qcom,x1e80100-clk-virt", .data = &x1e80100_clk_virt}, | |
1945 | { .compatible = "qcom,x1e80100-cnoc-cfg", .data = &x1e80100_cnoc_cfg}, | |
1946 | { .compatible = "qcom,x1e80100-cnoc-main", .data = &x1e80100_cnoc_main}, | |
1947 | { .compatible = "qcom,x1e80100-gem-noc", .data = &x1e80100_gem_noc}, | |
1948 | { .compatible = "qcom,x1e80100-lpass-ag-noc", .data = &x1e80100_lpass_ag_noc}, | |
1949 | { .compatible = "qcom,x1e80100-lpass-lpiaon-noc", .data = &x1e80100_lpass_lpiaon_noc}, | |
1950 | { .compatible = "qcom,x1e80100-lpass-lpicx-noc", .data = &x1e80100_lpass_lpicx_noc}, | |
1951 | { .compatible = "qcom,x1e80100-mc-virt", .data = &x1e80100_mc_virt}, | |
1952 | { .compatible = "qcom,x1e80100-mmss-noc", .data = &x1e80100_mmss_noc}, | |
1953 | { .compatible = "qcom,x1e80100-nsp-noc", .data = &x1e80100_nsp_noc}, | |
1954 | { .compatible = "qcom,x1e80100-pcie-center-anoc", .data = &x1e80100_pcie_center_anoc}, | |
1955 | { .compatible = "qcom,x1e80100-pcie-north-anoc", .data = &x1e80100_pcie_north_anoc}, | |
1956 | { .compatible = "qcom,x1e80100-pcie-south-anoc", .data = &x1e80100_pcie_south_anoc}, | |
1957 | { .compatible = "qcom,x1e80100-system-noc", .data = &x1e80100_system_noc}, | |
1958 | { .compatible = "qcom,x1e80100-usb-center-anoc", .data = &x1e80100_usb_center_anoc}, | |
1959 | { .compatible = "qcom,x1e80100-usb-north-anoc", .data = &x1e80100_usb_north_anoc}, | |
1960 | { .compatible = "qcom,x1e80100-usb-south-anoc", .data = &x1e80100_usb_south_anoc}, | |
1961 | { } | |
1962 | }; | |
1963 | MODULE_DEVICE_TABLE(of, qnoc_of_match); | |
1964 | ||
1965 | static struct platform_driver qnoc_driver = { | |
1966 | .probe = qcom_icc_rpmh_probe, | |
1967 | .remove_new = qcom_icc_rpmh_remove, | |
1968 | .driver = { | |
1969 | .name = "qnoc-x1e80100", | |
1970 | .of_match_table = qnoc_of_match, | |
1971 | .sync_state = icc_sync_state, | |
1972 | }, | |
1973 | }; | |
1974 | ||
1975 | static int __init qnoc_driver_init(void) | |
1976 | { | |
1977 | return platform_driver_register(&qnoc_driver); | |
1978 | } | |
1979 | core_initcall(qnoc_driver_init); | |
1980 | ||
1981 | static void __exit qnoc_driver_exit(void) | |
1982 | { | |
1983 | platform_driver_unregister(&qnoc_driver); | |
1984 | } | |
1985 | module_exit(qnoc_driver_exit); | |
1986 | ||
1987 | MODULE_DESCRIPTION("x1e80100 NoC driver"); | |
1988 | MODULE_LICENSE("GPL"); |