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1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2021, The Linux Foundation. All rights reserved. | |
4 | * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. | |
5 | * Copyright (c) 2023, Linaro Limited | |
6 | */ | |
7 | ||
8 | #include <linux/device.h> | |
9 | #include <linux/interconnect.h> | |
10 | #include <linux/interconnect-provider.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of_platform.h> | |
13 | #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> | |
14 | ||
15 | #include "bcm-voter.h" | |
16 | #include "icc-common.h" | |
17 | #include "icc-rpmh.h" | |
18 | #include "sm8650.h" | |
19 | ||
20 | static struct qcom_icc_node qhm_qspi = { | |
21 | .name = "qhm_qspi", | |
22 | .id = SM8650_MASTER_QSPI_0, | |
23 | .channels = 1, | |
24 | .buswidth = 4, | |
25 | .num_links = 1, | |
26 | .links = { SM8650_SLAVE_A1NOC_SNOC }, | |
27 | }; | |
28 | ||
29 | static struct qcom_icc_node qhm_qup1 = { | |
30 | .name = "qhm_qup1", | |
31 | .id = SM8650_MASTER_QUP_1, | |
32 | .channels = 1, | |
33 | .buswidth = 4, | |
34 | .num_links = 1, | |
35 | .links = { SM8650_SLAVE_A1NOC_SNOC }, | |
36 | }; | |
37 | ||
38 | static struct qcom_icc_node qxm_qup02 = { | |
39 | .name = "qxm_qup02", | |
40 | .id = SM8650_MASTER_QUP_3, | |
41 | .channels = 1, | |
42 | .buswidth = 8, | |
43 | .num_links = 1, | |
44 | .links = { SM8650_SLAVE_A1NOC_SNOC }, | |
45 | }; | |
46 | ||
47 | static struct qcom_icc_node xm_sdc4 = { | |
48 | .name = "xm_sdc4", | |
49 | .id = SM8650_MASTER_SDCC_4, | |
50 | .channels = 1, | |
51 | .buswidth = 8, | |
52 | .num_links = 1, | |
53 | .links = { SM8650_SLAVE_A1NOC_SNOC }, | |
54 | }; | |
55 | ||
56 | static struct qcom_icc_node xm_ufs_mem = { | |
57 | .name = "xm_ufs_mem", | |
58 | .id = SM8650_MASTER_UFS_MEM, | |
59 | .channels = 1, | |
60 | .buswidth = 16, | |
61 | .num_links = 1, | |
62 | .links = { SM8650_SLAVE_A1NOC_SNOC }, | |
63 | }; | |
64 | ||
65 | static struct qcom_icc_node xm_usb3_0 = { | |
66 | .name = "xm_usb3_0", | |
67 | .id = SM8650_MASTER_USB3_0, | |
68 | .channels = 1, | |
69 | .buswidth = 8, | |
70 | .num_links = 1, | |
71 | .links = { SM8650_SLAVE_A1NOC_SNOC }, | |
72 | }; | |
73 | ||
74 | static struct qcom_icc_node qhm_qdss_bam = { | |
75 | .name = "qhm_qdss_bam", | |
76 | .id = SM8650_MASTER_QDSS_BAM, | |
77 | .channels = 1, | |
78 | .buswidth = 4, | |
79 | .num_links = 1, | |
80 | .links = { SM8650_SLAVE_A2NOC_SNOC }, | |
81 | }; | |
82 | ||
83 | static struct qcom_icc_node qhm_qup2 = { | |
84 | .name = "qhm_qup2", | |
85 | .id = SM8650_MASTER_QUP_2, | |
86 | .channels = 1, | |
87 | .buswidth = 4, | |
88 | .num_links = 1, | |
89 | .links = { SM8650_SLAVE_A2NOC_SNOC }, | |
90 | }; | |
91 | ||
92 | static struct qcom_icc_node qxm_crypto = { | |
93 | .name = "qxm_crypto", | |
94 | .id = SM8650_MASTER_CRYPTO, | |
95 | .channels = 1, | |
96 | .buswidth = 8, | |
97 | .num_links = 1, | |
98 | .links = { SM8650_SLAVE_A2NOC_SNOC }, | |
99 | }; | |
100 | ||
101 | static struct qcom_icc_node qxm_ipa = { | |
102 | .name = "qxm_ipa", | |
103 | .id = SM8650_MASTER_IPA, | |
104 | .channels = 1, | |
105 | .buswidth = 8, | |
106 | .num_links = 1, | |
107 | .links = { SM8650_SLAVE_A2NOC_SNOC }, | |
108 | }; | |
109 | ||
110 | static struct qcom_icc_node qxm_sp = { | |
111 | .name = "qxm_sp", | |
112 | .id = SM8650_MASTER_SP, | |
113 | .channels = 1, | |
114 | .buswidth = 8, | |
115 | .num_links = 1, | |
116 | .links = { SM8650_SLAVE_A2NOC_SNOC }, | |
117 | }; | |
118 | ||
119 | static struct qcom_icc_node xm_qdss_etr_0 = { | |
120 | .name = "xm_qdss_etr_0", | |
121 | .id = SM8650_MASTER_QDSS_ETR, | |
122 | .channels = 1, | |
123 | .buswidth = 8, | |
124 | .num_links = 1, | |
125 | .links = { SM8650_SLAVE_A2NOC_SNOC }, | |
126 | }; | |
127 | ||
128 | static struct qcom_icc_node xm_qdss_etr_1 = { | |
129 | .name = "xm_qdss_etr_1", | |
130 | .id = SM8650_MASTER_QDSS_ETR_1, | |
131 | .channels = 1, | |
132 | .buswidth = 8, | |
133 | .num_links = 1, | |
134 | .links = { SM8650_SLAVE_A2NOC_SNOC }, | |
135 | }; | |
136 | ||
137 | static struct qcom_icc_node xm_sdc2 = { | |
138 | .name = "xm_sdc2", | |
139 | .id = SM8650_MASTER_SDCC_2, | |
140 | .channels = 1, | |
141 | .buswidth = 8, | |
142 | .num_links = 1, | |
143 | .links = { SM8650_SLAVE_A2NOC_SNOC }, | |
144 | }; | |
145 | ||
146 | static struct qcom_icc_node qup0_core_master = { | |
147 | .name = "qup0_core_master", | |
148 | .id = SM8650_MASTER_QUP_CORE_0, | |
149 | .channels = 1, | |
150 | .buswidth = 4, | |
151 | .num_links = 1, | |
152 | .links = { SM8650_SLAVE_QUP_CORE_0 }, | |
153 | }; | |
154 | ||
155 | static struct qcom_icc_node qup1_core_master = { | |
156 | .name = "qup1_core_master", | |
157 | .id = SM8650_MASTER_QUP_CORE_1, | |
158 | .channels = 1, | |
159 | .buswidth = 4, | |
160 | .num_links = 1, | |
161 | .links = { SM8650_SLAVE_QUP_CORE_1 }, | |
162 | }; | |
163 | ||
164 | static struct qcom_icc_node qup2_core_master = { | |
165 | .name = "qup2_core_master", | |
166 | .id = SM8650_MASTER_QUP_CORE_2, | |
167 | .channels = 1, | |
168 | .buswidth = 4, | |
169 | .num_links = 1, | |
170 | .links = { SM8650_SLAVE_QUP_CORE_2 }, | |
171 | }; | |
172 | ||
173 | static struct qcom_icc_node qsm_cfg = { | |
174 | .name = "qsm_cfg", | |
175 | .id = SM8650_MASTER_CNOC_CFG, | |
176 | .channels = 1, | |
177 | .buswidth = 4, | |
178 | .num_links = 46, | |
179 | .links = { SM8650_SLAVE_AHB2PHY_SOUTH, SM8650_SLAVE_AHB2PHY_NORTH, | |
180 | SM8650_SLAVE_CAMERA_CFG, SM8650_SLAVE_CLK_CTL, | |
181 | SM8650_SLAVE_RBCPR_CX_CFG, SM8650_SLAVE_CPR_HMX, | |
182 | SM8650_SLAVE_RBCPR_MMCX_CFG, SM8650_SLAVE_RBCPR_MXA_CFG, | |
183 | SM8650_SLAVE_RBCPR_MXC_CFG, SM8650_SLAVE_CPR_NSPCX, | |
184 | SM8650_SLAVE_CRYPTO_0_CFG, SM8650_SLAVE_CX_RDPM, | |
185 | SM8650_SLAVE_DISPLAY_CFG, SM8650_SLAVE_GFX3D_CFG, | |
186 | SM8650_SLAVE_I2C, SM8650_SLAVE_I3C_IBI0_CFG, | |
187 | SM8650_SLAVE_I3C_IBI1_CFG, SM8650_SLAVE_IMEM_CFG, | |
188 | SM8650_SLAVE_CNOC_MSS, SM8650_SLAVE_MX_2_RDPM, | |
189 | SM8650_SLAVE_MX_RDPM, SM8650_SLAVE_PCIE_0_CFG, | |
190 | SM8650_SLAVE_PCIE_1_CFG, SM8650_SLAVE_PCIE_RSCC, | |
191 | SM8650_SLAVE_PDM, SM8650_SLAVE_PRNG, | |
192 | SM8650_SLAVE_QDSS_CFG, SM8650_SLAVE_QSPI_0, | |
193 | SM8650_SLAVE_QUP_3, SM8650_SLAVE_QUP_1, | |
194 | SM8650_SLAVE_QUP_2, SM8650_SLAVE_SDCC_2, | |
195 | SM8650_SLAVE_SDCC_4, SM8650_SLAVE_SPSS_CFG, | |
196 | SM8650_SLAVE_TCSR, SM8650_SLAVE_TLMM, | |
197 | SM8650_SLAVE_UFS_MEM_CFG, SM8650_SLAVE_USB3_0, | |
198 | SM8650_SLAVE_VENUS_CFG, SM8650_SLAVE_VSENSE_CTRL_CFG, | |
199 | SM8650_SLAVE_CNOC_MNOC_CFG, SM8650_SLAVE_NSP_QTB_CFG, | |
200 | SM8650_SLAVE_PCIE_ANOC_CFG, SM8650_SLAVE_SERVICE_CNOC_CFG, | |
201 | SM8650_SLAVE_QDSS_STM, SM8650_SLAVE_TCU }, | |
202 | }; | |
203 | ||
204 | static struct qcom_icc_node qnm_gemnoc_cnoc = { | |
205 | .name = "qnm_gemnoc_cnoc", | |
206 | .id = SM8650_MASTER_GEM_NOC_CNOC, | |
207 | .channels = 1, | |
208 | .buswidth = 16, | |
209 | .num_links = 9, | |
210 | .links = { SM8650_SLAVE_AOSS, SM8650_SLAVE_IPA_CFG, | |
211 | SM8650_SLAVE_IPC_ROUTER_CFG, SM8650_SLAVE_TME_CFG, | |
212 | SM8650_SLAVE_APPSS, SM8650_SLAVE_CNOC_CFG, | |
213 | SM8650_SLAVE_DDRSS_CFG, SM8650_SLAVE_IMEM, | |
214 | SM8650_SLAVE_SERVICE_CNOC }, | |
215 | }; | |
216 | ||
217 | static struct qcom_icc_node qnm_gemnoc_pcie = { | |
218 | .name = "qnm_gemnoc_pcie", | |
219 | .id = SM8650_MASTER_GEM_NOC_PCIE_SNOC, | |
220 | .channels = 1, | |
221 | .buswidth = 16, | |
222 | .num_links = 2, | |
223 | .links = { SM8650_SLAVE_PCIE_0, SM8650_SLAVE_PCIE_1 }, | |
224 | }; | |
225 | ||
226 | static struct qcom_icc_node alm_gpu_tcu = { | |
227 | .name = "alm_gpu_tcu", | |
228 | .id = SM8650_MASTER_GPU_TCU, | |
229 | .channels = 1, | |
230 | .buswidth = 8, | |
231 | .num_links = 2, | |
232 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, | |
233 | }; | |
234 | ||
235 | static struct qcom_icc_node alm_sys_tcu = { | |
236 | .name = "alm_sys_tcu", | |
237 | .id = SM8650_MASTER_SYS_TCU, | |
238 | .channels = 1, | |
239 | .buswidth = 8, | |
240 | .num_links = 2, | |
241 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, | |
242 | }; | |
243 | ||
244 | static struct qcom_icc_node alm_ubwc_p_tcu = { | |
245 | .name = "alm_ubwc_p_tcu", | |
246 | .id = SM8650_MASTER_UBWC_P_TCU, | |
247 | .channels = 1, | |
248 | .buswidth = 8, | |
249 | .num_links = 2, | |
250 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, | |
251 | }; | |
252 | ||
253 | static struct qcom_icc_node chm_apps = { | |
254 | .name = "chm_apps", | |
255 | .id = SM8650_MASTER_APPSS_PROC, | |
256 | .channels = 3, | |
257 | .buswidth = 32, | |
258 | .num_links = 3, | |
259 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, | |
260 | SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, | |
261 | }; | |
262 | ||
263 | static struct qcom_icc_node qnm_gpu = { | |
264 | .name = "qnm_gpu", | |
265 | .id = SM8650_MASTER_GFX3D, | |
266 | .channels = 2, | |
267 | .buswidth = 32, | |
268 | .num_links = 2, | |
269 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, | |
270 | }; | |
271 | ||
272 | static struct qcom_icc_node qnm_lpass_gemnoc = { | |
273 | .name = "qnm_lpass_gemnoc", | |
274 | .id = SM8650_MASTER_LPASS_GEM_NOC, | |
275 | .channels = 1, | |
276 | .buswidth = 16, | |
277 | .num_links = 3, | |
278 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, | |
279 | SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, | |
280 | }; | |
281 | ||
282 | static struct qcom_icc_node qnm_mdsp = { | |
283 | .name = "qnm_mdsp", | |
284 | .id = SM8650_MASTER_MSS_PROC, | |
285 | .channels = 1, | |
286 | .buswidth = 16, | |
287 | .num_links = 3, | |
288 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, | |
289 | SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, | |
290 | }; | |
291 | ||
292 | static struct qcom_icc_node qnm_mnoc_hf = { | |
293 | .name = "qnm_mnoc_hf", | |
294 | .id = SM8650_MASTER_MNOC_HF_MEM_NOC, | |
295 | .channels = 2, | |
296 | .buswidth = 32, | |
297 | .num_links = 2, | |
298 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, | |
299 | }; | |
300 | ||
301 | static struct qcom_icc_node qnm_mnoc_sf = { | |
302 | .name = "qnm_mnoc_sf", | |
303 | .id = SM8650_MASTER_MNOC_SF_MEM_NOC, | |
304 | .channels = 2, | |
305 | .buswidth = 32, | |
306 | .num_links = 2, | |
307 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, | |
308 | }; | |
309 | ||
310 | static struct qcom_icc_node qnm_nsp_gemnoc = { | |
311 | .name = "qnm_nsp_gemnoc", | |
312 | .id = SM8650_MASTER_COMPUTE_NOC, | |
313 | .channels = 2, | |
314 | .buswidth = 32, | |
315 | .num_links = 3, | |
316 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, | |
317 | SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, | |
318 | }; | |
319 | ||
320 | static struct qcom_icc_node qnm_pcie = { | |
321 | .name = "qnm_pcie", | |
322 | .id = SM8650_MASTER_ANOC_PCIE_GEM_NOC, | |
323 | .channels = 1, | |
324 | .buswidth = 16, | |
325 | .num_links = 2, | |
326 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, | |
327 | }; | |
328 | ||
329 | static struct qcom_icc_node qnm_snoc_sf = { | |
330 | .name = "qnm_snoc_sf", | |
331 | .id = SM8650_MASTER_SNOC_SF_MEM_NOC, | |
332 | .channels = 1, | |
333 | .buswidth = 16, | |
334 | .num_links = 3, | |
335 | .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, | |
336 | SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, | |
337 | }; | |
338 | ||
339 | static struct qcom_icc_node qnm_ubwc_p = { | |
340 | .name = "qnm_ubwc_p", | |
341 | .id = SM8650_MASTER_UBWC_P, | |
342 | .channels = 1, | |
343 | .buswidth = 32, | |
344 | .num_links = 1, | |
345 | .links = { SM8650_SLAVE_LLCC }, | |
346 | }; | |
347 | ||
348 | static struct qcom_icc_node xm_gic = { | |
349 | .name = "xm_gic", | |
350 | .id = SM8650_MASTER_GIC, | |
351 | .channels = 1, | |
352 | .buswidth = 8, | |
353 | .num_links = 1, | |
354 | .links = { SM8650_SLAVE_LLCC }, | |
355 | }; | |
356 | ||
357 | static struct qcom_icc_node qnm_lpiaon_noc = { | |
358 | .name = "qnm_lpiaon_noc", | |
359 | .id = SM8650_MASTER_LPIAON_NOC, | |
360 | .channels = 1, | |
361 | .buswidth = 16, | |
362 | .num_links = 1, | |
363 | .links = { SM8650_SLAVE_LPASS_GEM_NOC }, | |
364 | }; | |
365 | ||
366 | static struct qcom_icc_node qnm_lpass_lpinoc = { | |
367 | .name = "qnm_lpass_lpinoc", | |
368 | .id = SM8650_MASTER_LPASS_LPINOC, | |
369 | .channels = 1, | |
370 | .buswidth = 16, | |
371 | .num_links = 1, | |
372 | .links = { SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, | |
373 | }; | |
374 | ||
375 | static struct qcom_icc_node qxm_lpinoc_dsp_axim = { | |
376 | .name = "qxm_lpinoc_dsp_axim", | |
377 | .id = SM8650_MASTER_LPASS_PROC, | |
378 | .channels = 1, | |
379 | .buswidth = 16, | |
380 | .num_links = 1, | |
381 | .links = { SM8650_SLAVE_LPICX_NOC_LPIAON_NOC }, | |
382 | }; | |
383 | ||
384 | static struct qcom_icc_node llcc_mc = { | |
385 | .name = "llcc_mc", | |
386 | .id = SM8650_MASTER_LLCC, | |
387 | .channels = 4, | |
388 | .buswidth = 4, | |
389 | .num_links = 1, | |
390 | .links = { SM8650_SLAVE_EBI1 }, | |
391 | }; | |
392 | ||
393 | static struct qcom_icc_node qnm_camnoc_hf = { | |
394 | .name = "qnm_camnoc_hf", | |
395 | .id = SM8650_MASTER_CAMNOC_HF, | |
396 | .channels = 2, | |
397 | .buswidth = 32, | |
398 | .num_links = 1, | |
399 | .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC }, | |
400 | }; | |
401 | ||
402 | static struct qcom_icc_node qnm_camnoc_icp = { | |
403 | .name = "qnm_camnoc_icp", | |
404 | .id = SM8650_MASTER_CAMNOC_ICP, | |
405 | .channels = 1, | |
406 | .buswidth = 8, | |
407 | .num_links = 1, | |
408 | .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, | |
409 | }; | |
410 | ||
411 | static struct qcom_icc_node qnm_camnoc_sf = { | |
412 | .name = "qnm_camnoc_sf", | |
413 | .id = SM8650_MASTER_CAMNOC_SF, | |
414 | .channels = 2, | |
415 | .buswidth = 32, | |
416 | .num_links = 1, | |
417 | .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, | |
418 | }; | |
419 | ||
420 | static struct qcom_icc_node qnm_mdp = { | |
421 | .name = "qnm_mdp", | |
422 | .id = SM8650_MASTER_MDP, | |
423 | .channels = 2, | |
424 | .buswidth = 32, | |
425 | .num_links = 1, | |
426 | .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC }, | |
427 | }; | |
428 | ||
429 | static struct qcom_icc_node qnm_vapss_hcp = { | |
430 | .name = "qnm_vapss_hcp", | |
431 | .id = SM8650_MASTER_CDSP_HCP, | |
432 | .channels = 1, | |
433 | .buswidth = 32, | |
434 | .num_links = 1, | |
435 | .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, | |
436 | }; | |
437 | ||
438 | static struct qcom_icc_node qnm_video = { | |
439 | .name = "qnm_video", | |
440 | .id = SM8650_MASTER_VIDEO, | |
441 | .channels = 2, | |
442 | .buswidth = 32, | |
443 | .num_links = 1, | |
444 | .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, | |
445 | }; | |
446 | ||
447 | static struct qcom_icc_node qnm_video_cv_cpu = { | |
448 | .name = "qnm_video_cv_cpu", | |
449 | .id = SM8650_MASTER_VIDEO_CV_PROC, | |
450 | .channels = 1, | |
451 | .buswidth = 8, | |
452 | .num_links = 1, | |
453 | .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, | |
454 | }; | |
455 | ||
456 | static struct qcom_icc_node qnm_video_cvp = { | |
457 | .name = "qnm_video_cvp", | |
458 | .id = SM8650_MASTER_VIDEO_PROC, | |
459 | .channels = 2, | |
460 | .buswidth = 32, | |
461 | .num_links = 1, | |
462 | .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, | |
463 | }; | |
464 | ||
465 | static struct qcom_icc_node qnm_video_v_cpu = { | |
466 | .name = "qnm_video_v_cpu", | |
467 | .id = SM8650_MASTER_VIDEO_V_PROC, | |
468 | .channels = 1, | |
469 | .buswidth = 8, | |
470 | .num_links = 1, | |
471 | .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, | |
472 | }; | |
473 | ||
474 | static struct qcom_icc_node qsm_mnoc_cfg = { | |
475 | .name = "qsm_mnoc_cfg", | |
476 | .id = SM8650_MASTER_CNOC_MNOC_CFG, | |
477 | .channels = 1, | |
478 | .buswidth = 4, | |
479 | .num_links = 1, | |
480 | .links = { SM8650_SLAVE_SERVICE_MNOC }, | |
481 | }; | |
482 | ||
483 | static struct qcom_icc_node qnm_nsp = { | |
484 | .name = "qnm_nsp", | |
485 | .id = SM8650_MASTER_CDSP_PROC, | |
486 | .channels = 2, | |
487 | .buswidth = 32, | |
488 | .num_links = 1, | |
489 | .links = { SM8650_SLAVE_CDSP_MEM_NOC }, | |
490 | }; | |
491 | ||
492 | static struct qcom_icc_node qsm_pcie_anoc_cfg = { | |
493 | .name = "qsm_pcie_anoc_cfg", | |
494 | .id = SM8650_MASTER_PCIE_ANOC_CFG, | |
495 | .channels = 1, | |
496 | .buswidth = 4, | |
497 | .num_links = 1, | |
498 | .links = { SM8650_SLAVE_SERVICE_PCIE_ANOC }, | |
499 | }; | |
500 | ||
501 | static struct qcom_icc_node xm_pcie3_0 = { | |
502 | .name = "xm_pcie3_0", | |
503 | .id = SM8650_MASTER_PCIE_0, | |
504 | .channels = 1, | |
505 | .buswidth = 8, | |
506 | .num_links = 1, | |
507 | .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, | |
508 | }; | |
509 | ||
510 | static struct qcom_icc_node xm_pcie3_1 = { | |
511 | .name = "xm_pcie3_1", | |
512 | .id = SM8650_MASTER_PCIE_1, | |
513 | .channels = 1, | |
514 | .buswidth = 16, | |
515 | .num_links = 1, | |
516 | .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, | |
517 | }; | |
518 | ||
519 | static struct qcom_icc_node qnm_aggre1_noc = { | |
520 | .name = "qnm_aggre1_noc", | |
521 | .id = SM8650_MASTER_A1NOC_SNOC, | |
522 | .channels = 1, | |
523 | .buswidth = 16, | |
524 | .num_links = 1, | |
525 | .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, | |
526 | }; | |
527 | ||
528 | static struct qcom_icc_node qnm_aggre2_noc = { | |
529 | .name = "qnm_aggre2_noc", | |
530 | .id = SM8650_MASTER_A2NOC_SNOC, | |
531 | .channels = 1, | |
532 | .buswidth = 16, | |
533 | .num_links = 1, | |
534 | .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, | |
535 | }; | |
536 | ||
537 | static struct qcom_icc_node qns_a1noc_snoc = { | |
538 | .name = "qns_a1noc_snoc", | |
539 | .id = SM8650_SLAVE_A1NOC_SNOC, | |
540 | .channels = 1, | |
541 | .buswidth = 16, | |
542 | .num_links = 1, | |
543 | .links = { SM8650_MASTER_A1NOC_SNOC }, | |
544 | }; | |
545 | ||
546 | static struct qcom_icc_node qns_a2noc_snoc = { | |
547 | .name = "qns_a2noc_snoc", | |
548 | .id = SM8650_SLAVE_A2NOC_SNOC, | |
549 | .channels = 1, | |
550 | .buswidth = 16, | |
551 | .num_links = 1, | |
552 | .links = { SM8650_MASTER_A2NOC_SNOC }, | |
553 | }; | |
554 | ||
555 | static struct qcom_icc_node qup0_core_slave = { | |
556 | .name = "qup0_core_slave", | |
557 | .id = SM8650_SLAVE_QUP_CORE_0, | |
558 | .channels = 1, | |
559 | .buswidth = 4, | |
560 | .num_links = 0, | |
561 | }; | |
562 | ||
563 | static struct qcom_icc_node qup1_core_slave = { | |
564 | .name = "qup1_core_slave", | |
565 | .id = SM8650_SLAVE_QUP_CORE_1, | |
566 | .channels = 1, | |
567 | .buswidth = 4, | |
568 | .num_links = 0, | |
569 | }; | |
570 | ||
571 | static struct qcom_icc_node qup2_core_slave = { | |
572 | .name = "qup2_core_slave", | |
573 | .id = SM8650_SLAVE_QUP_CORE_2, | |
574 | .channels = 1, | |
575 | .buswidth = 4, | |
576 | .num_links = 0, | |
577 | }; | |
578 | ||
579 | static struct qcom_icc_node qhs_ahb2phy0 = { | |
580 | .name = "qhs_ahb2phy0", | |
581 | .id = SM8650_SLAVE_AHB2PHY_SOUTH, | |
582 | .channels = 1, | |
583 | .buswidth = 4, | |
584 | .num_links = 0, | |
585 | }; | |
586 | ||
587 | static struct qcom_icc_node qhs_ahb2phy1 = { | |
588 | .name = "qhs_ahb2phy1", | |
589 | .id = SM8650_SLAVE_AHB2PHY_NORTH, | |
590 | .channels = 1, | |
591 | .buswidth = 4, | |
592 | .num_links = 0, | |
593 | }; | |
594 | ||
595 | static struct qcom_icc_node qhs_camera_cfg = { | |
596 | .name = "qhs_camera_cfg", | |
597 | .id = SM8650_SLAVE_CAMERA_CFG, | |
598 | .channels = 1, | |
599 | .buswidth = 4, | |
600 | .num_links = 0, | |
601 | }; | |
602 | ||
603 | static struct qcom_icc_node qhs_clk_ctl = { | |
604 | .name = "qhs_clk_ctl", | |
605 | .id = SM8650_SLAVE_CLK_CTL, | |
606 | .channels = 1, | |
607 | .buswidth = 4, | |
608 | .num_links = 0, | |
609 | }; | |
610 | ||
611 | static struct qcom_icc_node qhs_cpr_cx = { | |
612 | .name = "qhs_cpr_cx", | |
613 | .id = SM8650_SLAVE_RBCPR_CX_CFG, | |
614 | .channels = 1, | |
615 | .buswidth = 4, | |
616 | .num_links = 0, | |
617 | }; | |
618 | ||
619 | static struct qcom_icc_node qhs_cpr_hmx = { | |
620 | .name = "qhs_cpr_hmx", | |
621 | .id = SM8650_SLAVE_CPR_HMX, | |
622 | .channels = 1, | |
623 | .buswidth = 4, | |
624 | .num_links = 0, | |
625 | }; | |
626 | ||
627 | static struct qcom_icc_node qhs_cpr_mmcx = { | |
628 | .name = "qhs_cpr_mmcx", | |
629 | .id = SM8650_SLAVE_RBCPR_MMCX_CFG, | |
630 | .channels = 1, | |
631 | .buswidth = 4, | |
632 | .num_links = 0, | |
633 | }; | |
634 | ||
635 | static struct qcom_icc_node qhs_cpr_mxa = { | |
636 | .name = "qhs_cpr_mxa", | |
637 | .id = SM8650_SLAVE_RBCPR_MXA_CFG, | |
638 | .channels = 1, | |
639 | .buswidth = 4, | |
640 | .num_links = 0, | |
641 | }; | |
642 | ||
643 | static struct qcom_icc_node qhs_cpr_mxc = { | |
644 | .name = "qhs_cpr_mxc", | |
645 | .id = SM8650_SLAVE_RBCPR_MXC_CFG, | |
646 | .channels = 1, | |
647 | .buswidth = 4, | |
648 | .num_links = 0, | |
649 | }; | |
650 | ||
651 | static struct qcom_icc_node qhs_cpr_nspcx = { | |
652 | .name = "qhs_cpr_nspcx", | |
653 | .id = SM8650_SLAVE_CPR_NSPCX, | |
654 | .channels = 1, | |
655 | .buswidth = 4, | |
656 | .num_links = 0, | |
657 | }; | |
658 | ||
659 | static struct qcom_icc_node qhs_crypto0_cfg = { | |
660 | .name = "qhs_crypto0_cfg", | |
661 | .id = SM8650_SLAVE_CRYPTO_0_CFG, | |
662 | .channels = 1, | |
663 | .buswidth = 4, | |
664 | .num_links = 0, | |
665 | }; | |
666 | ||
667 | static struct qcom_icc_node qhs_cx_rdpm = { | |
668 | .name = "qhs_cx_rdpm", | |
669 | .id = SM8650_SLAVE_CX_RDPM, | |
670 | .channels = 1, | |
671 | .buswidth = 4, | |
672 | .num_links = 0, | |
673 | }; | |
674 | ||
675 | static struct qcom_icc_node qhs_display_cfg = { | |
676 | .name = "qhs_display_cfg", | |
677 | .id = SM8650_SLAVE_DISPLAY_CFG, | |
678 | .channels = 1, | |
679 | .buswidth = 4, | |
680 | .num_links = 0, | |
681 | }; | |
682 | ||
683 | static struct qcom_icc_node qhs_gpuss_cfg = { | |
684 | .name = "qhs_gpuss_cfg", | |
685 | .id = SM8650_SLAVE_GFX3D_CFG, | |
686 | .channels = 1, | |
687 | .buswidth = 8, | |
688 | .num_links = 0, | |
689 | }; | |
690 | ||
691 | static struct qcom_icc_node qhs_i2c = { | |
692 | .name = "qhs_i2c", | |
693 | .id = SM8650_SLAVE_I2C, | |
694 | .channels = 1, | |
695 | .buswidth = 4, | |
696 | .num_links = 0, | |
697 | }; | |
698 | ||
699 | static struct qcom_icc_node qhs_i3c_ibi0_cfg = { | |
700 | .name = "qhs_i3c_ibi0_cfg", | |
701 | .id = SM8650_SLAVE_I3C_IBI0_CFG, | |
702 | .channels = 1, | |
703 | .buswidth = 4, | |
704 | .num_links = 0, | |
705 | }; | |
706 | ||
707 | static struct qcom_icc_node qhs_i3c_ibi1_cfg = { | |
708 | .name = "qhs_i3c_ibi1_cfg", | |
709 | .id = SM8650_SLAVE_I3C_IBI1_CFG, | |
710 | .channels = 1, | |
711 | .buswidth = 4, | |
712 | .num_links = 0, | |
713 | }; | |
714 | ||
715 | static struct qcom_icc_node qhs_imem_cfg = { | |
716 | .name = "qhs_imem_cfg", | |
717 | .id = SM8650_SLAVE_IMEM_CFG, | |
718 | .channels = 1, | |
719 | .buswidth = 4, | |
720 | .num_links = 0, | |
721 | }; | |
722 | ||
723 | static struct qcom_icc_node qhs_mss_cfg = { | |
724 | .name = "qhs_mss_cfg", | |
725 | .id = SM8650_SLAVE_CNOC_MSS, | |
726 | .channels = 1, | |
727 | .buswidth = 4, | |
728 | .num_links = 0, | |
729 | }; | |
730 | ||
731 | static struct qcom_icc_node qhs_mx_2_rdpm = { | |
732 | .name = "qhs_mx_2_rdpm", | |
733 | .id = SM8650_SLAVE_MX_2_RDPM, | |
734 | .channels = 1, | |
735 | .buswidth = 4, | |
736 | .num_links = 0, | |
737 | }; | |
738 | ||
739 | static struct qcom_icc_node qhs_mx_rdpm = { | |
740 | .name = "qhs_mx_rdpm", | |
741 | .id = SM8650_SLAVE_MX_RDPM, | |
742 | .channels = 1, | |
743 | .buswidth = 4, | |
744 | .num_links = 0, | |
745 | }; | |
746 | ||
747 | static struct qcom_icc_node qhs_pcie0_cfg = { | |
748 | .name = "qhs_pcie0_cfg", | |
749 | .id = SM8650_SLAVE_PCIE_0_CFG, | |
750 | .channels = 1, | |
751 | .buswidth = 4, | |
752 | .num_links = 0, | |
753 | }; | |
754 | ||
755 | static struct qcom_icc_node qhs_pcie1_cfg = { | |
756 | .name = "qhs_pcie1_cfg", | |
757 | .id = SM8650_SLAVE_PCIE_1_CFG, | |
758 | .channels = 1, | |
759 | .buswidth = 4, | |
760 | .num_links = 0, | |
761 | }; | |
762 | ||
763 | static struct qcom_icc_node qhs_pcie_rscc = { | |
764 | .name = "qhs_pcie_rscc", | |
765 | .id = SM8650_SLAVE_PCIE_RSCC, | |
766 | .channels = 1, | |
767 | .buswidth = 4, | |
768 | .num_links = 0, | |
769 | }; | |
770 | ||
771 | static struct qcom_icc_node qhs_pdm = { | |
772 | .name = "qhs_pdm", | |
773 | .id = SM8650_SLAVE_PDM, | |
774 | .channels = 1, | |
775 | .buswidth = 4, | |
776 | .num_links = 0, | |
777 | }; | |
778 | ||
779 | static struct qcom_icc_node qhs_prng = { | |
780 | .name = "qhs_prng", | |
781 | .id = SM8650_SLAVE_PRNG, | |
782 | .channels = 1, | |
783 | .buswidth = 4, | |
784 | .num_links = 0, | |
785 | }; | |
786 | ||
787 | static struct qcom_icc_node qhs_qdss_cfg = { | |
788 | .name = "qhs_qdss_cfg", | |
789 | .id = SM8650_SLAVE_QDSS_CFG, | |
790 | .channels = 1, | |
791 | .buswidth = 4, | |
792 | .num_links = 0, | |
793 | }; | |
794 | ||
795 | static struct qcom_icc_node qhs_qspi = { | |
796 | .name = "qhs_qspi", | |
797 | .id = SM8650_SLAVE_QSPI_0, | |
798 | .channels = 1, | |
799 | .buswidth = 4, | |
800 | .num_links = 0, | |
801 | }; | |
802 | ||
803 | static struct qcom_icc_node qhs_qup02 = { | |
804 | .name = "qhs_qup02", | |
805 | .id = SM8650_SLAVE_QUP_3, | |
806 | .channels = 1, | |
807 | .buswidth = 4, | |
808 | .num_links = 0, | |
809 | }; | |
810 | ||
811 | static struct qcom_icc_node qhs_qup1 = { | |
812 | .name = "qhs_qup1", | |
813 | .id = SM8650_SLAVE_QUP_1, | |
814 | .channels = 1, | |
815 | .buswidth = 4, | |
816 | .num_links = 0, | |
817 | }; | |
818 | ||
819 | static struct qcom_icc_node qhs_qup2 = { | |
820 | .name = "qhs_qup2", | |
821 | .id = SM8650_SLAVE_QUP_2, | |
822 | .channels = 1, | |
823 | .buswidth = 4, | |
824 | .num_links = 0, | |
825 | }; | |
826 | ||
827 | static struct qcom_icc_node qhs_sdc2 = { | |
828 | .name = "qhs_sdc2", | |
829 | .id = SM8650_SLAVE_SDCC_2, | |
830 | .channels = 1, | |
831 | .buswidth = 4, | |
832 | .num_links = 0, | |
833 | }; | |
834 | ||
835 | static struct qcom_icc_node qhs_sdc4 = { | |
836 | .name = "qhs_sdc4", | |
837 | .id = SM8650_SLAVE_SDCC_4, | |
838 | .channels = 1, | |
839 | .buswidth = 4, | |
840 | .num_links = 0, | |
841 | }; | |
842 | ||
843 | static struct qcom_icc_node qhs_spss_cfg = { | |
844 | .name = "qhs_spss_cfg", | |
845 | .id = SM8650_SLAVE_SPSS_CFG, | |
846 | .channels = 1, | |
847 | .buswidth = 4, | |
848 | .num_links = 0, | |
849 | }; | |
850 | ||
851 | static struct qcom_icc_node qhs_tcsr = { | |
852 | .name = "qhs_tcsr", | |
853 | .id = SM8650_SLAVE_TCSR, | |
854 | .channels = 1, | |
855 | .buswidth = 4, | |
856 | .num_links = 0, | |
857 | }; | |
858 | ||
859 | static struct qcom_icc_node qhs_tlmm = { | |
860 | .name = "qhs_tlmm", | |
861 | .id = SM8650_SLAVE_TLMM, | |
862 | .channels = 1, | |
863 | .buswidth = 4, | |
864 | .num_links = 0, | |
865 | }; | |
866 | ||
867 | static struct qcom_icc_node qhs_ufs_mem_cfg = { | |
868 | .name = "qhs_ufs_mem_cfg", | |
869 | .id = SM8650_SLAVE_UFS_MEM_CFG, | |
870 | .channels = 1, | |
871 | .buswidth = 4, | |
872 | .num_links = 0, | |
873 | }; | |
874 | ||
875 | static struct qcom_icc_node qhs_usb3_0 = { | |
876 | .name = "qhs_usb3_0", | |
877 | .id = SM8650_SLAVE_USB3_0, | |
878 | .channels = 1, | |
879 | .buswidth = 4, | |
880 | .num_links = 0, | |
881 | }; | |
882 | ||
883 | static struct qcom_icc_node qhs_venus_cfg = { | |
884 | .name = "qhs_venus_cfg", | |
885 | .id = SM8650_SLAVE_VENUS_CFG, | |
886 | .channels = 1, | |
887 | .buswidth = 4, | |
888 | .num_links = 0, | |
889 | }; | |
890 | ||
891 | static struct qcom_icc_node qhs_vsense_ctrl_cfg = { | |
892 | .name = "qhs_vsense_ctrl_cfg", | |
893 | .id = SM8650_SLAVE_VSENSE_CTRL_CFG, | |
894 | .channels = 1, | |
895 | .buswidth = 4, | |
896 | .num_links = 0, | |
897 | }; | |
898 | ||
899 | static struct qcom_icc_node qss_mnoc_cfg = { | |
900 | .name = "qss_mnoc_cfg", | |
901 | .id = SM8650_SLAVE_CNOC_MNOC_CFG, | |
902 | .channels = 1, | |
903 | .buswidth = 4, | |
904 | .num_links = 1, | |
905 | .links = { SM8650_MASTER_CNOC_MNOC_CFG }, | |
906 | }; | |
907 | ||
908 | static struct qcom_icc_node qss_nsp_qtb_cfg = { | |
909 | .name = "qss_nsp_qtb_cfg", | |
910 | .id = SM8650_SLAVE_NSP_QTB_CFG, | |
911 | .channels = 1, | |
912 | .buswidth = 4, | |
913 | .num_links = 0, | |
914 | }; | |
915 | ||
916 | static struct qcom_icc_node qss_pcie_anoc_cfg = { | |
917 | .name = "qss_pcie_anoc_cfg", | |
918 | .id = SM8650_SLAVE_PCIE_ANOC_CFG, | |
919 | .channels = 1, | |
920 | .buswidth = 4, | |
921 | .num_links = 1, | |
922 | .links = { SM8650_MASTER_PCIE_ANOC_CFG }, | |
923 | }; | |
924 | ||
925 | static struct qcom_icc_node srvc_cnoc_cfg = { | |
926 | .name = "srvc_cnoc_cfg", | |
927 | .id = SM8650_SLAVE_SERVICE_CNOC_CFG, | |
928 | .channels = 1, | |
929 | .buswidth = 4, | |
930 | .num_links = 0, | |
931 | }; | |
932 | ||
933 | static struct qcom_icc_node xs_qdss_stm = { | |
934 | .name = "xs_qdss_stm", | |
935 | .id = SM8650_SLAVE_QDSS_STM, | |
936 | .channels = 1, | |
937 | .buswidth = 4, | |
938 | .num_links = 0, | |
939 | }; | |
940 | ||
941 | static struct qcom_icc_node xs_sys_tcu_cfg = { | |
942 | .name = "xs_sys_tcu_cfg", | |
943 | .id = SM8650_SLAVE_TCU, | |
944 | .channels = 1, | |
945 | .buswidth = 8, | |
946 | .num_links = 0, | |
947 | }; | |
948 | ||
949 | static struct qcom_icc_node qhs_aoss = { | |
950 | .name = "qhs_aoss", | |
951 | .id = SM8650_SLAVE_AOSS, | |
952 | .channels = 1, | |
953 | .buswidth = 4, | |
954 | .num_links = 0, | |
955 | }; | |
956 | ||
957 | static struct qcom_icc_node qhs_ipa = { | |
958 | .name = "qhs_ipa", | |
959 | .id = SM8650_SLAVE_IPA_CFG, | |
960 | .channels = 1, | |
961 | .buswidth = 4, | |
962 | .num_links = 0, | |
963 | }; | |
964 | ||
965 | static struct qcom_icc_node qhs_ipc_router = { | |
966 | .name = "qhs_ipc_router", | |
967 | .id = SM8650_SLAVE_IPC_ROUTER_CFG, | |
968 | .channels = 1, | |
969 | .buswidth = 4, | |
970 | .num_links = 0, | |
971 | }; | |
972 | ||
973 | static struct qcom_icc_node qhs_tme_cfg = { | |
974 | .name = "qhs_tme_cfg", | |
975 | .id = SM8650_SLAVE_TME_CFG, | |
976 | .channels = 1, | |
977 | .buswidth = 4, | |
978 | .num_links = 0, | |
979 | }; | |
980 | ||
981 | static struct qcom_icc_node qss_apss = { | |
982 | .name = "qss_apss", | |
983 | .id = SM8650_SLAVE_APPSS, | |
984 | .channels = 1, | |
985 | .buswidth = 4, | |
986 | .num_links = 0, | |
987 | }; | |
988 | ||
989 | static struct qcom_icc_node qss_cfg = { | |
990 | .name = "qss_cfg", | |
991 | .id = SM8650_SLAVE_CNOC_CFG, | |
992 | .channels = 1, | |
993 | .buswidth = 4, | |
994 | .num_links = 1, | |
995 | .links = { SM8650_MASTER_CNOC_CFG }, | |
996 | }; | |
997 | ||
998 | static struct qcom_icc_node qss_ddrss_cfg = { | |
999 | .name = "qss_ddrss_cfg", | |
1000 | .id = SM8650_SLAVE_DDRSS_CFG, | |
1001 | .channels = 1, | |
1002 | .buswidth = 4, | |
1003 | .num_links = 0, | |
1004 | }; | |
1005 | ||
1006 | static struct qcom_icc_node qxs_imem = { | |
1007 | .name = "qxs_imem", | |
1008 | .id = SM8650_SLAVE_IMEM, | |
1009 | .channels = 1, | |
1010 | .buswidth = 8, | |
1011 | .num_links = 0, | |
1012 | }; | |
1013 | ||
1014 | static struct qcom_icc_node srvc_cnoc_main = { | |
1015 | .name = "srvc_cnoc_main", | |
1016 | .id = SM8650_SLAVE_SERVICE_CNOC, | |
1017 | .channels = 1, | |
1018 | .buswidth = 4, | |
1019 | .num_links = 0, | |
1020 | }; | |
1021 | ||
1022 | static struct qcom_icc_node xs_pcie_0 = { | |
1023 | .name = "xs_pcie_0", | |
1024 | .id = SM8650_SLAVE_PCIE_0, | |
1025 | .channels = 1, | |
1026 | .buswidth = 8, | |
1027 | .num_links = 0, | |
1028 | }; | |
1029 | ||
1030 | static struct qcom_icc_node xs_pcie_1 = { | |
1031 | .name = "xs_pcie_1", | |
1032 | .id = SM8650_SLAVE_PCIE_1, | |
1033 | .channels = 1, | |
1034 | .buswidth = 16, | |
1035 | .num_links = 0, | |
1036 | }; | |
1037 | ||
1038 | static struct qcom_icc_node qns_gem_noc_cnoc = { | |
1039 | .name = "qns_gem_noc_cnoc", | |
1040 | .id = SM8650_SLAVE_GEM_NOC_CNOC, | |
1041 | .channels = 1, | |
1042 | .buswidth = 16, | |
1043 | .num_links = 1, | |
1044 | .links = { SM8650_MASTER_GEM_NOC_CNOC }, | |
1045 | }; | |
1046 | ||
1047 | static struct qcom_icc_node qns_llcc = { | |
1048 | .name = "qns_llcc", | |
1049 | .id = SM8650_SLAVE_LLCC, | |
1050 | .channels = 4, | |
1051 | .buswidth = 16, | |
1052 | .num_links = 1, | |
1053 | .links = { SM8650_MASTER_LLCC }, | |
1054 | }; | |
1055 | ||
1056 | static struct qcom_icc_node qns_pcie = { | |
1057 | .name = "qns_pcie", | |
1058 | .id = SM8650_SLAVE_MEM_NOC_PCIE_SNOC, | |
1059 | .channels = 1, | |
1060 | .buswidth = 8, | |
1061 | .num_links = 1, | |
1062 | .links = { SM8650_MASTER_GEM_NOC_PCIE_SNOC }, | |
1063 | }; | |
1064 | ||
1065 | static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { | |
1066 | .name = "qns_lpass_ag_noc_gemnoc", | |
1067 | .id = SM8650_SLAVE_LPASS_GEM_NOC, | |
1068 | .channels = 1, | |
1069 | .buswidth = 16, | |
1070 | .num_links = 1, | |
1071 | .links = { SM8650_MASTER_LPASS_GEM_NOC }, | |
1072 | }; | |
1073 | ||
1074 | static struct qcom_icc_node qns_lpass_aggnoc = { | |
1075 | .name = "qns_lpass_aggnoc", | |
1076 | .id = SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC, | |
1077 | .channels = 1, | |
1078 | .buswidth = 16, | |
1079 | .num_links = 1, | |
1080 | .links = { SM8650_MASTER_LPIAON_NOC }, | |
1081 | }; | |
1082 | ||
1083 | static struct qcom_icc_node qns_lpi_aon_noc = { | |
1084 | .name = "qns_lpi_aon_noc", | |
1085 | .id = SM8650_SLAVE_LPICX_NOC_LPIAON_NOC, | |
1086 | .channels = 1, | |
1087 | .buswidth = 16, | |
1088 | .num_links = 1, | |
1089 | .links = { SM8650_MASTER_LPASS_LPINOC }, | |
1090 | }; | |
1091 | ||
1092 | static struct qcom_icc_node ebi = { | |
1093 | .name = "ebi", | |
1094 | .id = SM8650_SLAVE_EBI1, | |
1095 | .channels = 4, | |
1096 | .buswidth = 4, | |
1097 | .num_links = 0, | |
1098 | }; | |
1099 | ||
1100 | static struct qcom_icc_node qns_mem_noc_hf = { | |
1101 | .name = "qns_mem_noc_hf", | |
1102 | .id = SM8650_SLAVE_MNOC_HF_MEM_NOC, | |
1103 | .channels = 2, | |
1104 | .buswidth = 32, | |
1105 | .num_links = 1, | |
1106 | .links = { SM8650_MASTER_MNOC_HF_MEM_NOC }, | |
1107 | }; | |
1108 | ||
1109 | static struct qcom_icc_node qns_mem_noc_sf = { | |
1110 | .name = "qns_mem_noc_sf", | |
1111 | .id = SM8650_SLAVE_MNOC_SF_MEM_NOC, | |
1112 | .channels = 2, | |
1113 | .buswidth = 32, | |
1114 | .num_links = 1, | |
1115 | .links = { SM8650_MASTER_MNOC_SF_MEM_NOC }, | |
1116 | }; | |
1117 | ||
1118 | static struct qcom_icc_node srvc_mnoc = { | |
1119 | .name = "srvc_mnoc", | |
1120 | .id = SM8650_SLAVE_SERVICE_MNOC, | |
1121 | .channels = 1, | |
1122 | .buswidth = 4, | |
1123 | .num_links = 0, | |
1124 | }; | |
1125 | ||
1126 | static struct qcom_icc_node qns_nsp_gemnoc = { | |
1127 | .name = "qns_nsp_gemnoc", | |
1128 | .id = SM8650_SLAVE_CDSP_MEM_NOC, | |
1129 | .channels = 2, | |
1130 | .buswidth = 32, | |
1131 | .num_links = 1, | |
1132 | .links = { SM8650_MASTER_COMPUTE_NOC }, | |
1133 | }; | |
1134 | ||
1135 | static struct qcom_icc_node qns_pcie_mem_noc = { | |
1136 | .name = "qns_pcie_mem_noc", | |
1137 | .id = SM8650_SLAVE_ANOC_PCIE_GEM_NOC, | |
1138 | .channels = 1, | |
1139 | .buswidth = 16, | |
1140 | .num_links = 1, | |
1141 | .links = { SM8650_MASTER_ANOC_PCIE_GEM_NOC }, | |
1142 | }; | |
1143 | ||
1144 | static struct qcom_icc_node srvc_pcie_aggre_noc = { | |
1145 | .name = "srvc_pcie_aggre_noc", | |
1146 | .id = SM8650_SLAVE_SERVICE_PCIE_ANOC, | |
1147 | .channels = 1, | |
1148 | .buswidth = 4, | |
1149 | .num_links = 0, | |
1150 | }; | |
1151 | ||
1152 | static struct qcom_icc_node qns_gemnoc_sf = { | |
1153 | .name = "qns_gemnoc_sf", | |
1154 | .id = SM8650_SLAVE_SNOC_GEM_NOC_SF, | |
1155 | .channels = 1, | |
1156 | .buswidth = 16, | |
1157 | .num_links = 1, | |
1158 | .links = { SM8650_MASTER_SNOC_SF_MEM_NOC }, | |
1159 | }; | |
1160 | ||
1161 | static struct qcom_icc_bcm bcm_acv = { | |
1162 | .name = "ACV", | |
a40f93e9 | 1163 | .enable_mask = BIT(0), |
c062bcab NA |
1164 | .num_nodes = 1, |
1165 | .nodes = { &ebi }, | |
1166 | }; | |
1167 | ||
1168 | static struct qcom_icc_bcm bcm_ce0 = { | |
1169 | .name = "CE0", | |
1170 | .num_nodes = 1, | |
1171 | .nodes = { &qxm_crypto }, | |
1172 | }; | |
1173 | ||
1174 | static struct qcom_icc_bcm bcm_cn0 = { | |
1175 | .name = "CN0", | |
1176 | .enable_mask = BIT(0), | |
1177 | .keepalive = true, | |
1178 | .num_nodes = 59, | |
1179 | .nodes = { &qsm_cfg, &qhs_ahb2phy0, | |
1180 | &qhs_ahb2phy1, &qhs_camera_cfg, | |
1181 | &qhs_clk_ctl, &qhs_cpr_cx, | |
1182 | &qhs_cpr_hmx, &qhs_cpr_mmcx, | |
1183 | &qhs_cpr_mxa, &qhs_cpr_mxc, | |
1184 | &qhs_cpr_nspcx, &qhs_crypto0_cfg, | |
1185 | &qhs_cx_rdpm, &qhs_display_cfg, | |
1186 | &qhs_gpuss_cfg, &qhs_i2c, | |
1187 | &qhs_i3c_ibi0_cfg, &qhs_i3c_ibi1_cfg, | |
1188 | &qhs_imem_cfg, &qhs_mss_cfg, | |
1189 | &qhs_mx_2_rdpm, &qhs_mx_rdpm, | |
1190 | &qhs_pcie0_cfg, &qhs_pcie1_cfg, | |
1191 | &qhs_pcie_rscc, &qhs_pdm, | |
1192 | &qhs_prng, &qhs_qdss_cfg, | |
1193 | &qhs_qspi, &qhs_qup02, | |
1194 | &qhs_qup1, &qhs_qup2, | |
1195 | &qhs_sdc2, &qhs_sdc4, | |
1196 | &qhs_spss_cfg, &qhs_tcsr, | |
1197 | &qhs_tlmm, &qhs_ufs_mem_cfg, | |
1198 | &qhs_usb3_0, &qhs_venus_cfg, | |
1199 | &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, | |
1200 | &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg, | |
1201 | &srvc_cnoc_cfg, &xs_qdss_stm, | |
1202 | &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, | |
1203 | &qnm_gemnoc_pcie, &qhs_aoss, | |
1204 | &qhs_ipa, &qhs_ipc_router, | |
1205 | &qhs_tme_cfg, &qss_apss, | |
1206 | &qss_cfg, &qss_ddrss_cfg, | |
1207 | &qxs_imem, &srvc_cnoc_main, | |
1208 | &xs_pcie_0, &xs_pcie_1 }, | |
1209 | }; | |
1210 | ||
1211 | static struct qcom_icc_bcm bcm_co0 = { | |
1212 | .name = "CO0", | |
1213 | .enable_mask = BIT(0), | |
1214 | .num_nodes = 2, | |
1215 | .nodes = { &qnm_nsp, &qns_nsp_gemnoc }, | |
1216 | }; | |
1217 | ||
1218 | static struct qcom_icc_bcm bcm_lp0 = { | |
1219 | .name = "LP0", | |
1220 | .num_nodes = 2, | |
1221 | .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, | |
1222 | }; | |
1223 | ||
1224 | static struct qcom_icc_bcm bcm_mc0 = { | |
1225 | .name = "MC0", | |
1226 | .keepalive = true, | |
1227 | .num_nodes = 1, | |
1228 | .nodes = { &ebi }, | |
1229 | }; | |
1230 | ||
1231 | static struct qcom_icc_bcm bcm_mm0 = { | |
1232 | .name = "MM0", | |
1233 | .num_nodes = 1, | |
1234 | .nodes = { &qns_mem_noc_hf }, | |
1235 | }; | |
1236 | ||
1237 | static struct qcom_icc_bcm bcm_mm1 = { | |
1238 | .name = "MM1", | |
1239 | .enable_mask = BIT(0), | |
1240 | .num_nodes = 8, | |
1241 | .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, | |
1242 | &qnm_camnoc_sf, &qnm_vapss_hcp, | |
1243 | &qnm_video_cv_cpu, &qnm_video_cvp, | |
1244 | &qnm_video_v_cpu, &qns_mem_noc_sf }, | |
1245 | }; | |
1246 | ||
1247 | static struct qcom_icc_bcm bcm_qup0 = { | |
1248 | .name = "QUP0", | |
1249 | .keepalive = true, | |
1250 | .vote_scale = 1, | |
1251 | .num_nodes = 1, | |
1252 | .nodes = { &qup0_core_slave }, | |
1253 | }; | |
1254 | ||
1255 | static struct qcom_icc_bcm bcm_qup1 = { | |
1256 | .name = "QUP1", | |
1257 | .keepalive = true, | |
1258 | .vote_scale = 1, | |
1259 | .num_nodes = 1, | |
1260 | .nodes = { &qup1_core_slave }, | |
1261 | }; | |
1262 | ||
1263 | static struct qcom_icc_bcm bcm_qup2 = { | |
1264 | .name = "QUP2", | |
1265 | .keepalive = true, | |
1266 | .vote_scale = 1, | |
1267 | .num_nodes = 1, | |
1268 | .nodes = { &qup2_core_slave }, | |
1269 | }; | |
1270 | ||
1271 | static struct qcom_icc_bcm bcm_sh0 = { | |
1272 | .name = "SH0", | |
1273 | .keepalive = true, | |
1274 | .num_nodes = 1, | |
1275 | .nodes = { &qns_llcc }, | |
1276 | }; | |
1277 | ||
1278 | static struct qcom_icc_bcm bcm_sh1 = { | |
1279 | .name = "SH1", | |
1280 | .enable_mask = BIT(0), | |
1281 | .num_nodes = 15, | |
1282 | .nodes = { &alm_gpu_tcu, &alm_sys_tcu, | |
1283 | &alm_ubwc_p_tcu, &chm_apps, | |
1284 | &qnm_gpu, &qnm_mdsp, | |
1285 | &qnm_mnoc_hf, &qnm_mnoc_sf, | |
1286 | &qnm_nsp_gemnoc, &qnm_pcie, | |
1287 | &qnm_snoc_sf, &qnm_ubwc_p, | |
1288 | &xm_gic, &qns_gem_noc_cnoc, | |
1289 | &qns_pcie }, | |
1290 | }; | |
1291 | ||
1292 | static struct qcom_icc_bcm bcm_sn0 = { | |
1293 | .name = "SN0", | |
1294 | .keepalive = true, | |
1295 | .num_nodes = 1, | |
1296 | .nodes = { &qns_gemnoc_sf }, | |
1297 | }; | |
1298 | ||
1299 | static struct qcom_icc_bcm bcm_sn2 = { | |
1300 | .name = "SN2", | |
1301 | .num_nodes = 1, | |
1302 | .nodes = { &qnm_aggre1_noc }, | |
1303 | }; | |
1304 | ||
1305 | static struct qcom_icc_bcm bcm_sn3 = { | |
1306 | .name = "SN3", | |
1307 | .num_nodes = 1, | |
1308 | .nodes = { &qnm_aggre2_noc }, | |
1309 | }; | |
1310 | ||
1311 | static struct qcom_icc_bcm bcm_sn4 = { | |
1312 | .name = "SN4", | |
1313 | .num_nodes = 1, | |
1314 | .nodes = { &qns_pcie_mem_noc }, | |
1315 | }; | |
1316 | ||
1317 | static struct qcom_icc_node * const aggre1_noc_nodes[] = { | |
1318 | [MASTER_QSPI_0] = &qhm_qspi, | |
1319 | [MASTER_QUP_1] = &qhm_qup1, | |
1320 | [MASTER_QUP_3] = &qxm_qup02, | |
1321 | [MASTER_SDCC_4] = &xm_sdc4, | |
1322 | [MASTER_UFS_MEM] = &xm_ufs_mem, | |
1323 | [MASTER_USB3_0] = &xm_usb3_0, | |
1324 | [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, | |
1325 | }; | |
1326 | ||
1327 | static const struct qcom_icc_desc sm8650_aggre1_noc = { | |
1328 | .nodes = aggre1_noc_nodes, | |
1329 | .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), | |
1330 | }; | |
1331 | ||
1332 | static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { | |
1333 | &bcm_ce0, | |
1334 | }; | |
1335 | ||
1336 | static struct qcom_icc_node * const aggre2_noc_nodes[] = { | |
1337 | [MASTER_QDSS_BAM] = &qhm_qdss_bam, | |
1338 | [MASTER_QUP_2] = &qhm_qup2, | |
1339 | [MASTER_CRYPTO] = &qxm_crypto, | |
1340 | [MASTER_IPA] = &qxm_ipa, | |
1341 | [MASTER_SP] = &qxm_sp, | |
1342 | [MASTER_QDSS_ETR] = &xm_qdss_etr_0, | |
1343 | [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, | |
1344 | [MASTER_SDCC_2] = &xm_sdc2, | |
1345 | [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, | |
1346 | }; | |
1347 | ||
1348 | static const struct qcom_icc_desc sm8650_aggre2_noc = { | |
1349 | .nodes = aggre2_noc_nodes, | |
1350 | .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), | |
1351 | .bcms = aggre2_noc_bcms, | |
1352 | .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), | |
1353 | }; | |
1354 | ||
1355 | static struct qcom_icc_bcm * const clk_virt_bcms[] = { | |
1356 | &bcm_qup0, | |
1357 | &bcm_qup1, | |
1358 | &bcm_qup2, | |
1359 | }; | |
1360 | ||
1361 | static struct qcom_icc_node * const clk_virt_nodes[] = { | |
1362 | [MASTER_QUP_CORE_0] = &qup0_core_master, | |
1363 | [MASTER_QUP_CORE_1] = &qup1_core_master, | |
1364 | [MASTER_QUP_CORE_2] = &qup2_core_master, | |
1365 | [SLAVE_QUP_CORE_0] = &qup0_core_slave, | |
1366 | [SLAVE_QUP_CORE_1] = &qup1_core_slave, | |
1367 | [SLAVE_QUP_CORE_2] = &qup2_core_slave, | |
1368 | }; | |
1369 | ||
1370 | static const struct qcom_icc_desc sm8650_clk_virt = { | |
1371 | .nodes = clk_virt_nodes, | |
1372 | .num_nodes = ARRAY_SIZE(clk_virt_nodes), | |
1373 | .bcms = clk_virt_bcms, | |
1374 | .num_bcms = ARRAY_SIZE(clk_virt_bcms), | |
1375 | }; | |
1376 | ||
1377 | static struct qcom_icc_bcm * const config_noc_bcms[] = { | |
1378 | &bcm_cn0, | |
1379 | }; | |
1380 | ||
1381 | static struct qcom_icc_node * const config_noc_nodes[] = { | |
1382 | [MASTER_CNOC_CFG] = &qsm_cfg, | |
1383 | [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, | |
1384 | [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, | |
1385 | [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, | |
1386 | [SLAVE_CLK_CTL] = &qhs_clk_ctl, | |
1387 | [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, | |
1388 | [SLAVE_CPR_HMX] = &qhs_cpr_hmx, | |
1389 | [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, | |
1390 | [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, | |
1391 | [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, | |
1392 | [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, | |
1393 | [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, | |
1394 | [SLAVE_CX_RDPM] = &qhs_cx_rdpm, | |
1395 | [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, | |
1396 | [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, | |
1397 | [SLAVE_I2C] = &qhs_i2c, | |
1398 | [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg, | |
1399 | [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg, | |
1400 | [SLAVE_IMEM_CFG] = &qhs_imem_cfg, | |
1401 | [SLAVE_CNOC_MSS] = &qhs_mss_cfg, | |
1402 | [SLAVE_MX_2_RDPM] = &qhs_mx_2_rdpm, | |
1403 | [SLAVE_MX_RDPM] = &qhs_mx_rdpm, | |
1404 | [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, | |
1405 | [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, | |
1406 | [SLAVE_PCIE_RSCC] = &qhs_pcie_rscc, | |
1407 | [SLAVE_PDM] = &qhs_pdm, | |
1408 | [SLAVE_PRNG] = &qhs_prng, | |
1409 | [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, | |
1410 | [SLAVE_QSPI_0] = &qhs_qspi, | |
1411 | [SLAVE_QUP_3] = &qhs_qup02, | |
1412 | [SLAVE_QUP_1] = &qhs_qup1, | |
1413 | [SLAVE_QUP_2] = &qhs_qup2, | |
1414 | [SLAVE_SDCC_2] = &qhs_sdc2, | |
1415 | [SLAVE_SDCC_4] = &qhs_sdc4, | |
1416 | [SLAVE_SPSS_CFG] = &qhs_spss_cfg, | |
1417 | [SLAVE_TCSR] = &qhs_tcsr, | |
1418 | [SLAVE_TLMM] = &qhs_tlmm, | |
1419 | [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, | |
1420 | [SLAVE_USB3_0] = &qhs_usb3_0, | |
1421 | [SLAVE_VENUS_CFG] = &qhs_venus_cfg, | |
1422 | [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, | |
1423 | [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, | |
1424 | [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg, | |
1425 | [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, | |
1426 | [SLAVE_SERVICE_CNOC_CFG] = &srvc_cnoc_cfg, | |
1427 | [SLAVE_QDSS_STM] = &xs_qdss_stm, | |
1428 | [SLAVE_TCU] = &xs_sys_tcu_cfg, | |
1429 | }; | |
1430 | ||
1431 | static const struct qcom_icc_desc sm8650_config_noc = { | |
1432 | .nodes = config_noc_nodes, | |
1433 | .num_nodes = ARRAY_SIZE(config_noc_nodes), | |
1434 | .bcms = config_noc_bcms, | |
1435 | .num_bcms = ARRAY_SIZE(config_noc_bcms), | |
1436 | }; | |
1437 | ||
1438 | static struct qcom_icc_bcm * const cnoc_main_bcms[] = { | |
1439 | &bcm_cn0, | |
1440 | }; | |
1441 | ||
1442 | static struct qcom_icc_node * const cnoc_main_nodes[] = { | |
1443 | [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, | |
1444 | [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, | |
1445 | [SLAVE_AOSS] = &qhs_aoss, | |
1446 | [SLAVE_IPA_CFG] = &qhs_ipa, | |
1447 | [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, | |
1448 | [SLAVE_TME_CFG] = &qhs_tme_cfg, | |
1449 | [SLAVE_APPSS] = &qss_apss, | |
1450 | [SLAVE_CNOC_CFG] = &qss_cfg, | |
1451 | [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, | |
1452 | [SLAVE_IMEM] = &qxs_imem, | |
1453 | [SLAVE_SERVICE_CNOC] = &srvc_cnoc_main, | |
1454 | [SLAVE_PCIE_0] = &xs_pcie_0, | |
1455 | [SLAVE_PCIE_1] = &xs_pcie_1, | |
1456 | }; | |
1457 | ||
1458 | static const struct qcom_icc_desc sm8650_cnoc_main = { | |
1459 | .nodes = cnoc_main_nodes, | |
1460 | .num_nodes = ARRAY_SIZE(cnoc_main_nodes), | |
1461 | .bcms = cnoc_main_bcms, | |
1462 | .num_bcms = ARRAY_SIZE(cnoc_main_bcms), | |
1463 | }; | |
1464 | ||
1465 | static struct qcom_icc_bcm * const gem_noc_bcms[] = { | |
1466 | &bcm_sh0, | |
1467 | &bcm_sh1, | |
1468 | }; | |
1469 | ||
1470 | static struct qcom_icc_node * const gem_noc_nodes[] = { | |
1471 | [MASTER_GPU_TCU] = &alm_gpu_tcu, | |
1472 | [MASTER_SYS_TCU] = &alm_sys_tcu, | |
1473 | [MASTER_UBWC_P_TCU] = &alm_ubwc_p_tcu, | |
1474 | [MASTER_APPSS_PROC] = &chm_apps, | |
1475 | [MASTER_GFX3D] = &qnm_gpu, | |
1476 | [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, | |
1477 | [MASTER_MSS_PROC] = &qnm_mdsp, | |
1478 | [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, | |
1479 | [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, | |
1480 | [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, | |
1481 | [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, | |
1482 | [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, | |
1483 | [MASTER_UBWC_P] = &qnm_ubwc_p, | |
1484 | [MASTER_GIC] = &xm_gic, | |
1485 | [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, | |
1486 | [SLAVE_LLCC] = &qns_llcc, | |
1487 | [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, | |
1488 | }; | |
1489 | ||
1490 | static const struct qcom_icc_desc sm8650_gem_noc = { | |
1491 | .nodes = gem_noc_nodes, | |
1492 | .num_nodes = ARRAY_SIZE(gem_noc_nodes), | |
1493 | .bcms = gem_noc_bcms, | |
1494 | .num_bcms = ARRAY_SIZE(gem_noc_bcms), | |
1495 | }; | |
1496 | ||
1497 | static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { | |
1498 | [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, | |
1499 | [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, | |
1500 | }; | |
1501 | ||
1502 | static const struct qcom_icc_desc sm8650_lpass_ag_noc = { | |
1503 | .nodes = lpass_ag_noc_nodes, | |
1504 | .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), | |
1505 | }; | |
1506 | ||
1507 | static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { | |
1508 | &bcm_lp0, | |
1509 | }; | |
1510 | ||
1511 | static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { | |
1512 | [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, | |
1513 | [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, | |
1514 | }; | |
1515 | ||
1516 | static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = { | |
1517 | .nodes = lpass_lpiaon_noc_nodes, | |
1518 | .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), | |
1519 | .bcms = lpass_lpiaon_noc_bcms, | |
1520 | .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), | |
1521 | }; | |
1522 | ||
1523 | static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { | |
1524 | [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim, | |
1525 | [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, | |
1526 | }; | |
1527 | ||
1528 | static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = { | |
1529 | .nodes = lpass_lpicx_noc_nodes, | |
1530 | .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), | |
1531 | }; | |
1532 | ||
1533 | static struct qcom_icc_bcm * const mc_virt_bcms[] = { | |
1534 | &bcm_acv, | |
1535 | &bcm_mc0, | |
1536 | }; | |
1537 | ||
1538 | static struct qcom_icc_node * const mc_virt_nodes[] = { | |
1539 | [MASTER_LLCC] = &llcc_mc, | |
1540 | [SLAVE_EBI1] = &ebi, | |
1541 | }; | |
1542 | ||
1543 | static const struct qcom_icc_desc sm8650_mc_virt = { | |
1544 | .nodes = mc_virt_nodes, | |
1545 | .num_nodes = ARRAY_SIZE(mc_virt_nodes), | |
1546 | .bcms = mc_virt_bcms, | |
1547 | .num_bcms = ARRAY_SIZE(mc_virt_bcms), | |
1548 | }; | |
1549 | ||
1550 | static struct qcom_icc_bcm * const mmss_noc_bcms[] = { | |
1551 | &bcm_mm0, | |
1552 | &bcm_mm1, | |
1553 | }; | |
1554 | ||
1555 | static struct qcom_icc_node * const mmss_noc_nodes[] = { | |
1556 | [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, | |
1557 | [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, | |
1558 | [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, | |
1559 | [MASTER_MDP] = &qnm_mdp, | |
1560 | [MASTER_CDSP_HCP] = &qnm_vapss_hcp, | |
1561 | [MASTER_VIDEO] = &qnm_video, | |
1562 | [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, | |
1563 | [MASTER_VIDEO_PROC] = &qnm_video_cvp, | |
1564 | [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, | |
1565 | [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, | |
1566 | [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, | |
1567 | [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, | |
1568 | [SLAVE_SERVICE_MNOC] = &srvc_mnoc, | |
1569 | }; | |
1570 | ||
1571 | static const struct qcom_icc_desc sm8650_mmss_noc = { | |
1572 | .nodes = mmss_noc_nodes, | |
1573 | .num_nodes = ARRAY_SIZE(mmss_noc_nodes), | |
1574 | .bcms = mmss_noc_bcms, | |
1575 | .num_bcms = ARRAY_SIZE(mmss_noc_bcms), | |
1576 | }; | |
1577 | ||
1578 | static struct qcom_icc_bcm * const nsp_noc_bcms[] = { | |
1579 | &bcm_co0, | |
1580 | }; | |
1581 | ||
1582 | static struct qcom_icc_node * const nsp_noc_nodes[] = { | |
1583 | [MASTER_CDSP_PROC] = &qnm_nsp, | |
1584 | [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, | |
1585 | }; | |
1586 | ||
1587 | static const struct qcom_icc_desc sm8650_nsp_noc = { | |
1588 | .nodes = nsp_noc_nodes, | |
1589 | .num_nodes = ARRAY_SIZE(nsp_noc_nodes), | |
1590 | .bcms = nsp_noc_bcms, | |
1591 | .num_bcms = ARRAY_SIZE(nsp_noc_bcms), | |
1592 | }; | |
1593 | ||
1594 | static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { | |
1595 | &bcm_sn4, | |
1596 | }; | |
1597 | ||
1598 | static struct qcom_icc_node * const pcie_anoc_nodes[] = { | |
1599 | [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, | |
1600 | [MASTER_PCIE_0] = &xm_pcie3_0, | |
1601 | [MASTER_PCIE_1] = &xm_pcie3_1, | |
1602 | [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, | |
1603 | [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, | |
1604 | }; | |
1605 | ||
1606 | static const struct qcom_icc_desc sm8650_pcie_anoc = { | |
1607 | .nodes = pcie_anoc_nodes, | |
1608 | .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), | |
1609 | .bcms = pcie_anoc_bcms, | |
1610 | .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), | |
1611 | }; | |
1612 | ||
1613 | static struct qcom_icc_bcm * const system_noc_bcms[] = { | |
1614 | &bcm_sn0, | |
1615 | &bcm_sn2, | |
1616 | &bcm_sn3, | |
1617 | }; | |
1618 | ||
1619 | static struct qcom_icc_node * const system_noc_nodes[] = { | |
1620 | [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, | |
1621 | [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, | |
1622 | [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, | |
1623 | }; | |
1624 | ||
1625 | static const struct qcom_icc_desc sm8650_system_noc = { | |
1626 | .nodes = system_noc_nodes, | |
1627 | .num_nodes = ARRAY_SIZE(system_noc_nodes), | |
1628 | .bcms = system_noc_bcms, | |
1629 | .num_bcms = ARRAY_SIZE(system_noc_bcms), | |
1630 | }; | |
1631 | ||
1632 | static const struct of_device_id qnoc_of_match[] = { | |
1633 | { .compatible = "qcom,sm8650-aggre1-noc", .data = &sm8650_aggre1_noc }, | |
1634 | { .compatible = "qcom,sm8650-aggre2-noc", .data = &sm8650_aggre2_noc }, | |
1635 | { .compatible = "qcom,sm8650-clk-virt", .data = &sm8650_clk_virt }, | |
1636 | { .compatible = "qcom,sm8650-config-noc", .data = &sm8650_config_noc }, | |
1637 | { .compatible = "qcom,sm8650-cnoc-main", .data = &sm8650_cnoc_main }, | |
1638 | { .compatible = "qcom,sm8650-gem-noc", .data = &sm8650_gem_noc }, | |
1639 | { .compatible = "qcom,sm8650-lpass-ag-noc", .data = &sm8650_lpass_ag_noc }, | |
1640 | { .compatible = "qcom,sm8650-lpass-lpiaon-noc", .data = &sm8650_lpass_lpiaon_noc }, | |
1641 | { .compatible = "qcom,sm8650-lpass-lpicx-noc", .data = &sm8650_lpass_lpicx_noc }, | |
1642 | { .compatible = "qcom,sm8650-mc-virt", .data = &sm8650_mc_virt }, | |
1643 | { .compatible = "qcom,sm8650-mmss-noc", .data = &sm8650_mmss_noc }, | |
1644 | { .compatible = "qcom,sm8650-nsp-noc", .data = &sm8650_nsp_noc }, | |
1645 | { .compatible = "qcom,sm8650-pcie-anoc", .data = &sm8650_pcie_anoc }, | |
1646 | { .compatible = "qcom,sm8650-system-noc", .data = &sm8650_system_noc }, | |
1647 | { } | |
1648 | }; | |
1649 | MODULE_DEVICE_TABLE(of, qnoc_of_match); | |
1650 | ||
1651 | static struct platform_driver qnoc_driver = { | |
1652 | .probe = qcom_icc_rpmh_probe, | |
1653 | .remove_new = qcom_icc_rpmh_remove, | |
1654 | .driver = { | |
1655 | .name = "qnoc-sm8650", | |
1656 | .of_match_table = qnoc_of_match, | |
1657 | .sync_state = icc_sync_state, | |
1658 | }, | |
1659 | }; | |
1660 | ||
1661 | static int __init qnoc_driver_init(void) | |
1662 | { | |
1663 | return platform_driver_register(&qnoc_driver); | |
1664 | } | |
1665 | core_initcall(qnoc_driver_init); | |
1666 | ||
1667 | static void __exit qnoc_driver_exit(void) | |
1668 | { | |
1669 | platform_driver_unregister(&qnoc_driver); | |
1670 | } | |
1671 | module_exit(qnoc_driver_exit); | |
1672 | ||
1673 | MODULE_DESCRIPTION("sm8650 NoC driver"); | |
1674 | MODULE_LICENSE("GPL"); |