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1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2021, The Linux Foundation. All rights reserved. | |
4 | * Copyright (c) 2022, Linaro Ltd | |
5 | */ | |
6 | ||
7 | #include <linux/device.h> | |
8 | #include <linux/interconnect.h> | |
9 | #include <linux/interconnect-provider.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of_platform.h> | |
12 | #include <dt-bindings/interconnect/qcom,sc8280xp.h> | |
13 | ||
14 | #include "bcm-voter.h" | |
15 | #include "icc-rpmh.h" | |
16 | #include "sc8280xp.h" | |
17 | ||
18 | static struct qcom_icc_node qhm_qspi = { | |
19 | .name = "qhm_qspi", | |
20 | .id = SC8280XP_MASTER_QSPI_0, | |
21 | .channels = 1, | |
22 | .buswidth = 4, | |
23 | .num_links = 1, | |
24 | .links = { SC8280XP_SLAVE_A1NOC_SNOC }, | |
25 | }; | |
26 | ||
27 | static struct qcom_icc_node qhm_qup1 = { | |
28 | .name = "qhm_qup1", | |
29 | .id = SC8280XP_MASTER_QUP_1, | |
30 | .channels = 1, | |
31 | .buswidth = 4, | |
32 | .num_links = 1, | |
33 | .links = { SC8280XP_SLAVE_A1NOC_SNOC }, | |
34 | }; | |
35 | ||
36 | static struct qcom_icc_node qhm_qup2 = { | |
37 | .name = "qhm_qup2", | |
38 | .id = SC8280XP_MASTER_QUP_2, | |
39 | .channels = 1, | |
40 | .buswidth = 4, | |
41 | .num_links = 1, | |
42 | .links = { SC8280XP_SLAVE_A1NOC_SNOC }, | |
43 | }; | |
44 | ||
45 | static struct qcom_icc_node qnm_a1noc_cfg = { | |
46 | .name = "qnm_a1noc_cfg", | |
47 | .id = SC8280XP_MASTER_A1NOC_CFG, | |
48 | .channels = 1, | |
49 | .buswidth = 4, | |
50 | .links = { SC8280XP_SLAVE_SERVICE_A1NOC }, | |
51 | }; | |
52 | ||
53 | static struct qcom_icc_node qxm_ipa = { | |
54 | .name = "qxm_ipa", | |
55 | .id = SC8280XP_MASTER_IPA, | |
56 | .channels = 1, | |
57 | .buswidth = 8, | |
58 | .num_links = 1, | |
59 | .links = { SC8280XP_SLAVE_A1NOC_SNOC }, | |
60 | }; | |
61 | ||
62 | static struct qcom_icc_node xm_emac_1 = { | |
63 | .name = "xm_emac_1", | |
64 | .id = SC8280XP_MASTER_EMAC_1, | |
65 | .channels = 1, | |
66 | .buswidth = 8, | |
67 | .num_links = 1, | |
68 | .links = { SC8280XP_SLAVE_A1NOC_SNOC }, | |
69 | }; | |
70 | ||
71 | static struct qcom_icc_node xm_sdc4 = { | |
72 | .name = "xm_sdc4", | |
73 | .id = SC8280XP_MASTER_SDCC_4, | |
74 | .channels = 1, | |
75 | .buswidth = 8, | |
76 | .num_links = 1, | |
77 | .links = { SC8280XP_SLAVE_A1NOC_SNOC }, | |
78 | }; | |
79 | ||
80 | static struct qcom_icc_node xm_ufs_mem = { | |
81 | .name = "xm_ufs_mem", | |
82 | .id = SC8280XP_MASTER_UFS_MEM, | |
83 | .channels = 1, | |
84 | .buswidth = 8, | |
85 | .num_links = 1, | |
86 | .links = { SC8280XP_SLAVE_A1NOC_SNOC }, | |
87 | }; | |
88 | ||
89 | static struct qcom_icc_node xm_usb3_0 = { | |
90 | .name = "xm_usb3_0", | |
91 | .id = SC8280XP_MASTER_USB3_0, | |
92 | .channels = 1, | |
93 | .buswidth = 8, | |
94 | .num_links = 1, | |
95 | .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, | |
96 | }; | |
97 | ||
98 | static struct qcom_icc_node xm_usb3_1 = { | |
99 | .name = "xm_usb3_1", | |
100 | .id = SC8280XP_MASTER_USB3_1, | |
101 | .channels = 1, | |
102 | .buswidth = 8, | |
103 | .num_links = 1, | |
104 | .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, | |
105 | }; | |
106 | ||
107 | static struct qcom_icc_node xm_usb3_mp = { | |
108 | .name = "xm_usb3_mp", | |
109 | .id = SC8280XP_MASTER_USB3_MP, | |
110 | .channels = 1, | |
111 | .buswidth = 16, | |
112 | .num_links = 1, | |
113 | .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, | |
114 | }; | |
115 | ||
116 | static struct qcom_icc_node xm_usb4_host0 = { | |
117 | .name = "xm_usb4_host0", | |
118 | .id = SC8280XP_MASTER_USB4_0, | |
119 | .channels = 1, | |
120 | .buswidth = 16, | |
121 | .num_links = 1, | |
122 | .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, | |
123 | }; | |
124 | ||
125 | static struct qcom_icc_node xm_usb4_host1 = { | |
126 | .name = "xm_usb4_host1", | |
127 | .id = SC8280XP_MASTER_USB4_1, | |
128 | .channels = 1, | |
129 | .buswidth = 16, | |
130 | .num_links = 1, | |
131 | .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, | |
132 | }; | |
133 | ||
134 | static struct qcom_icc_node qhm_qdss_bam = { | |
135 | .name = "qhm_qdss_bam", | |
136 | .id = SC8280XP_MASTER_QDSS_BAM, | |
137 | .channels = 1, | |
138 | .buswidth = 4, | |
139 | .num_links = 1, | |
140 | .links = { SC8280XP_SLAVE_A2NOC_SNOC }, | |
141 | }; | |
142 | ||
143 | static struct qcom_icc_node qhm_qup0 = { | |
144 | .name = "qhm_qup0", | |
145 | .id = SC8280XP_MASTER_QUP_0, | |
146 | .channels = 1, | |
147 | .buswidth = 4, | |
148 | .num_links = 1, | |
149 | .links = { SC8280XP_SLAVE_A2NOC_SNOC }, | |
150 | }; | |
151 | ||
152 | static struct qcom_icc_node qnm_a2noc_cfg = { | |
153 | .name = "qnm_a2noc_cfg", | |
154 | .id = SC8280XP_MASTER_A2NOC_CFG, | |
155 | .channels = 1, | |
156 | .buswidth = 4, | |
157 | .num_links = 1, | |
158 | .links = { SC8280XP_SLAVE_SERVICE_A2NOC }, | |
159 | }; | |
160 | ||
161 | static struct qcom_icc_node qxm_crypto = { | |
162 | .name = "qxm_crypto", | |
163 | .id = SC8280XP_MASTER_CRYPTO, | |
164 | .channels = 1, | |
165 | .buswidth = 8, | |
166 | .num_links = 1, | |
167 | .links = { SC8280XP_SLAVE_A2NOC_SNOC }, | |
168 | }; | |
169 | ||
170 | static struct qcom_icc_node qxm_sensorss_q6 = { | |
171 | .name = "qxm_sensorss_q6", | |
172 | .id = SC8280XP_MASTER_SENSORS_PROC, | |
173 | .channels = 1, | |
174 | .buswidth = 8, | |
175 | .num_links = 1, | |
176 | .links = { SC8280XP_SLAVE_A2NOC_SNOC }, | |
177 | }; | |
178 | ||
179 | static struct qcom_icc_node qxm_sp = { | |
180 | .name = "qxm_sp", | |
181 | .id = SC8280XP_MASTER_SP, | |
182 | .channels = 1, | |
183 | .buswidth = 8, | |
184 | .num_links = 1, | |
185 | .links = { SC8280XP_SLAVE_A2NOC_SNOC }, | |
186 | }; | |
187 | ||
188 | static struct qcom_icc_node xm_emac_0 = { | |
189 | .name = "xm_emac_0", | |
190 | .id = SC8280XP_MASTER_EMAC, | |
191 | .channels = 1, | |
192 | .buswidth = 8, | |
193 | .num_links = 1, | |
194 | .links = { SC8280XP_SLAVE_A2NOC_SNOC }, | |
195 | }; | |
196 | ||
197 | static struct qcom_icc_node xm_pcie3_0 = { | |
198 | .name = "xm_pcie3_0", | |
199 | .id = SC8280XP_MASTER_PCIE_0, | |
200 | .channels = 1, | |
201 | .buswidth = 16, | |
202 | .num_links = 1, | |
203 | .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, | |
204 | }; | |
205 | ||
206 | static struct qcom_icc_node xm_pcie3_1 = { | |
207 | .name = "xm_pcie3_1", | |
208 | .id = SC8280XP_MASTER_PCIE_1, | |
209 | .channels = 1, | |
210 | .buswidth = 16, | |
211 | .num_links = 1, | |
212 | .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, | |
213 | }; | |
214 | ||
215 | static struct qcom_icc_node xm_pcie3_2a = { | |
216 | .name = "xm_pcie3_2a", | |
217 | .id = SC8280XP_MASTER_PCIE_2A, | |
218 | .channels = 1, | |
219 | .buswidth = 16, | |
220 | .num_links = 1, | |
221 | .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, | |
222 | }; | |
223 | ||
224 | static struct qcom_icc_node xm_pcie3_2b = { | |
225 | .name = "xm_pcie3_2b", | |
226 | .id = SC8280XP_MASTER_PCIE_2B, | |
227 | .channels = 1, | |
228 | .buswidth = 8, | |
229 | .num_links = 1, | |
230 | .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, | |
231 | }; | |
232 | ||
233 | static struct qcom_icc_node xm_pcie3_3a = { | |
234 | .name = "xm_pcie3_3a", | |
235 | .id = SC8280XP_MASTER_PCIE_3A, | |
236 | .channels = 1, | |
237 | .buswidth = 16, | |
238 | .num_links = 1, | |
239 | .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, | |
240 | }; | |
241 | ||
242 | static struct qcom_icc_node xm_pcie3_3b = { | |
243 | .name = "xm_pcie3_3b", | |
244 | .id = SC8280XP_MASTER_PCIE_3B, | |
245 | .channels = 1, | |
246 | .buswidth = 8, | |
247 | .num_links = 1, | |
248 | .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, | |
249 | }; | |
250 | ||
251 | static struct qcom_icc_node xm_pcie3_4 = { | |
252 | .name = "xm_pcie3_4", | |
253 | .id = SC8280XP_MASTER_PCIE_4, | |
254 | .channels = 1, | |
255 | .buswidth = 8, | |
256 | .num_links = 1, | |
257 | .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, | |
258 | }; | |
259 | ||
260 | static struct qcom_icc_node xm_qdss_etr = { | |
261 | .name = "xm_qdss_etr", | |
262 | .id = SC8280XP_MASTER_QDSS_ETR, | |
263 | .channels = 1, | |
264 | .buswidth = 8, | |
265 | .num_links = 1, | |
266 | .links = { SC8280XP_SLAVE_A2NOC_SNOC }, | |
267 | }; | |
268 | ||
269 | static struct qcom_icc_node xm_sdc2 = { | |
270 | .name = "xm_sdc2", | |
271 | .id = SC8280XP_MASTER_SDCC_2, | |
272 | .channels = 1, | |
273 | .buswidth = 8, | |
274 | .num_links = 1, | |
275 | .links = { SC8280XP_SLAVE_A2NOC_SNOC }, | |
276 | }; | |
277 | ||
278 | static struct qcom_icc_node xm_ufs_card = { | |
279 | .name = "xm_ufs_card", | |
280 | .id = SC8280XP_MASTER_UFS_CARD, | |
281 | .channels = 1, | |
282 | .buswidth = 8, | |
283 | .num_links = 1, | |
284 | .links = { SC8280XP_SLAVE_A2NOC_SNOC }, | |
285 | }; | |
286 | ||
f29dabda BA |
287 | static struct qcom_icc_node qup0_core_master = { |
288 | .name = "qup0_core_master", | |
289 | .id = SC8280XP_MASTER_QUP_CORE_0, | |
290 | .channels = 1, | |
291 | .buswidth = 4, | |
292 | .num_links = 1, | |
293 | .links = { SC8280XP_SLAVE_QUP_CORE_0 }, | |
294 | }; | |
295 | ||
296 | static struct qcom_icc_node qup1_core_master = { | |
297 | .name = "qup1_core_master", | |
298 | .id = SC8280XP_MASTER_QUP_CORE_1, | |
299 | .channels = 1, | |
300 | .buswidth = 4, | |
301 | .num_links = 1, | |
302 | .links = { SC8280XP_SLAVE_QUP_CORE_1 }, | |
303 | }; | |
304 | ||
305 | static struct qcom_icc_node qup2_core_master = { | |
306 | .name = "qup2_core_master", | |
307 | .id = SC8280XP_MASTER_QUP_CORE_2, | |
308 | .channels = 1, | |
309 | .buswidth = 4, | |
310 | .num_links = 1, | |
311 | .links = { SC8280XP_SLAVE_QUP_CORE_2 }, | |
312 | }; | |
313 | ||
314 | static struct qcom_icc_node qnm_gemnoc_cnoc = { | |
315 | .name = "qnm_gemnoc_cnoc", | |
316 | .id = SC8280XP_MASTER_GEM_NOC_CNOC, | |
317 | .channels = 1, | |
318 | .buswidth = 16, | |
319 | .num_links = 76, | |
320 | .links = { SC8280XP_SLAVE_AHB2PHY_0, | |
321 | SC8280XP_SLAVE_AHB2PHY_1, | |
322 | SC8280XP_SLAVE_AHB2PHY_2, | |
323 | SC8280XP_SLAVE_AOSS, | |
324 | SC8280XP_SLAVE_APPSS, | |
325 | SC8280XP_SLAVE_CAMERA_CFG, | |
326 | SC8280XP_SLAVE_CLK_CTL, | |
327 | SC8280XP_SLAVE_CDSP_CFG, | |
328 | SC8280XP_SLAVE_CDSP1_CFG, | |
329 | SC8280XP_SLAVE_RBCPR_CX_CFG, | |
330 | SC8280XP_SLAVE_RBCPR_MMCX_CFG, | |
331 | SC8280XP_SLAVE_RBCPR_MX_CFG, | |
332 | SC8280XP_SLAVE_CPR_NSPCX, | |
333 | SC8280XP_SLAVE_CRYPTO_0_CFG, | |
334 | SC8280XP_SLAVE_CX_RDPM, | |
335 | SC8280XP_SLAVE_DCC_CFG, | |
336 | SC8280XP_SLAVE_DISPLAY_CFG, | |
337 | SC8280XP_SLAVE_DISPLAY1_CFG, | |
338 | SC8280XP_SLAVE_EMAC_CFG, | |
339 | SC8280XP_SLAVE_EMAC1_CFG, | |
340 | SC8280XP_SLAVE_GFX3D_CFG, | |
341 | SC8280XP_SLAVE_HWKM, | |
342 | SC8280XP_SLAVE_IMEM_CFG, | |
343 | SC8280XP_SLAVE_IPA_CFG, | |
344 | SC8280XP_SLAVE_IPC_ROUTER_CFG, | |
345 | SC8280XP_SLAVE_LPASS, | |
346 | SC8280XP_SLAVE_MX_RDPM, | |
347 | SC8280XP_SLAVE_MXC_RDPM, | |
348 | SC8280XP_SLAVE_PCIE_0_CFG, | |
349 | SC8280XP_SLAVE_PCIE_1_CFG, | |
350 | SC8280XP_SLAVE_PCIE_2A_CFG, | |
351 | SC8280XP_SLAVE_PCIE_2B_CFG, | |
352 | SC8280XP_SLAVE_PCIE_3A_CFG, | |
353 | SC8280XP_SLAVE_PCIE_3B_CFG, | |
354 | SC8280XP_SLAVE_PCIE_4_CFG, | |
355 | SC8280XP_SLAVE_PCIE_RSC_CFG, | |
356 | SC8280XP_SLAVE_PDM, | |
357 | SC8280XP_SLAVE_PIMEM_CFG, | |
358 | SC8280XP_SLAVE_PKA_WRAPPER_CFG, | |
359 | SC8280XP_SLAVE_PMU_WRAPPER_CFG, | |
360 | SC8280XP_SLAVE_QDSS_CFG, | |
361 | SC8280XP_SLAVE_QSPI_0, | |
362 | SC8280XP_SLAVE_QUP_0, | |
363 | SC8280XP_SLAVE_QUP_1, | |
364 | SC8280XP_SLAVE_QUP_2, | |
365 | SC8280XP_SLAVE_SDCC_2, | |
366 | SC8280XP_SLAVE_SDCC_4, | |
367 | SC8280XP_SLAVE_SECURITY, | |
368 | SC8280XP_SLAVE_SMMUV3_CFG, | |
369 | SC8280XP_SLAVE_SMSS_CFG, | |
370 | SC8280XP_SLAVE_SPSS_CFG, | |
371 | SC8280XP_SLAVE_TCSR, | |
372 | SC8280XP_SLAVE_TLMM, | |
373 | SC8280XP_SLAVE_UFS_CARD_CFG, | |
374 | SC8280XP_SLAVE_UFS_MEM_CFG, | |
375 | SC8280XP_SLAVE_USB3_0, | |
376 | SC8280XP_SLAVE_USB3_1, | |
377 | SC8280XP_SLAVE_USB3_MP, | |
378 | SC8280XP_SLAVE_USB4_0, | |
379 | SC8280XP_SLAVE_USB4_1, | |
380 | SC8280XP_SLAVE_VENUS_CFG, | |
381 | SC8280XP_SLAVE_VSENSE_CTRL_CFG, | |
382 | SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, | |
383 | SC8280XP_SLAVE_A1NOC_CFG, | |
384 | SC8280XP_SLAVE_A2NOC_CFG, | |
385 | SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, | |
386 | SC8280XP_SLAVE_DDRSS_CFG, | |
387 | SC8280XP_SLAVE_CNOC_MNOC_CFG, | |
388 | SC8280XP_SLAVE_SNOC_CFG, | |
389 | SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, | |
390 | SC8280XP_SLAVE_IMEM, | |
391 | SC8280XP_SLAVE_PIMEM, | |
392 | SC8280XP_SLAVE_SERVICE_CNOC, | |
393 | SC8280XP_SLAVE_QDSS_STM, | |
394 | SC8280XP_SLAVE_SMSS, | |
395 | SC8280XP_SLAVE_TCU | |
396 | }, | |
397 | }; | |
398 | ||
399 | static struct qcom_icc_node qnm_gemnoc_pcie = { | |
400 | .name = "qnm_gemnoc_pcie", | |
401 | .id = SC8280XP_MASTER_GEM_NOC_PCIE_SNOC, | |
402 | .channels = 1, | |
403 | .buswidth = 16, | |
404 | .num_links = 7, | |
405 | .links = { SC8280XP_SLAVE_PCIE_0, | |
406 | SC8280XP_SLAVE_PCIE_1, | |
407 | SC8280XP_SLAVE_PCIE_2A, | |
408 | SC8280XP_SLAVE_PCIE_2B, | |
409 | SC8280XP_SLAVE_PCIE_3A, | |
410 | SC8280XP_SLAVE_PCIE_3B, | |
411 | SC8280XP_SLAVE_PCIE_4 | |
412 | }, | |
413 | }; | |
414 | ||
415 | static struct qcom_icc_node qnm_cnoc_dc_noc = { | |
416 | .name = "qnm_cnoc_dc_noc", | |
417 | .id = SC8280XP_MASTER_CNOC_DC_NOC, | |
418 | .channels = 1, | |
419 | .buswidth = 4, | |
420 | .num_links = 2, | |
421 | .links = { SC8280XP_SLAVE_LLCC_CFG, | |
422 | SC8280XP_SLAVE_GEM_NOC_CFG | |
423 | }, | |
424 | }; | |
425 | ||
426 | static struct qcom_icc_node alm_gpu_tcu = { | |
427 | .name = "alm_gpu_tcu", | |
428 | .id = SC8280XP_MASTER_GPU_TCU, | |
429 | .channels = 1, | |
430 | .buswidth = 8, | |
431 | .num_links = 2, | |
432 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
433 | SC8280XP_SLAVE_LLCC | |
434 | }, | |
435 | }; | |
436 | ||
437 | static struct qcom_icc_node alm_pcie_tcu = { | |
438 | .name = "alm_pcie_tcu", | |
439 | .id = SC8280XP_MASTER_PCIE_TCU, | |
440 | .channels = 1, | |
441 | .buswidth = 8, | |
442 | .num_links = 2, | |
443 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
444 | SC8280XP_SLAVE_LLCC | |
445 | }, | |
446 | }; | |
447 | ||
448 | static struct qcom_icc_node alm_sys_tcu = { | |
449 | .name = "alm_sys_tcu", | |
450 | .id = SC8280XP_MASTER_SYS_TCU, | |
451 | .channels = 1, | |
452 | .buswidth = 8, | |
453 | .num_links = 2, | |
454 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
455 | SC8280XP_SLAVE_LLCC | |
456 | }, | |
457 | }; | |
458 | ||
459 | static struct qcom_icc_node chm_apps = { | |
460 | .name = "chm_apps", | |
461 | .id = SC8280XP_MASTER_APPSS_PROC, | |
462 | .channels = 2, | |
463 | .buswidth = 32, | |
464 | .num_links = 3, | |
465 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
466 | SC8280XP_SLAVE_LLCC, | |
467 | SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC | |
468 | }, | |
469 | }; | |
470 | ||
471 | static struct qcom_icc_node qnm_cmpnoc0 = { | |
472 | .name = "qnm_cmpnoc0", | |
473 | .id = SC8280XP_MASTER_COMPUTE_NOC, | |
474 | .channels = 2, | |
475 | .buswidth = 32, | |
476 | .num_links = 2, | |
477 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
478 | SC8280XP_SLAVE_LLCC | |
479 | }, | |
480 | }; | |
481 | ||
482 | static struct qcom_icc_node qnm_cmpnoc1 = { | |
483 | .name = "qnm_cmpnoc1", | |
484 | .id = SC8280XP_MASTER_COMPUTE_NOC_1, | |
485 | .channels = 2, | |
486 | .buswidth = 32, | |
487 | .num_links = 2, | |
488 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
489 | SC8280XP_SLAVE_LLCC | |
490 | }, | |
491 | }; | |
492 | ||
493 | static struct qcom_icc_node qnm_gemnoc_cfg = { | |
494 | .name = "qnm_gemnoc_cfg", | |
495 | .id = SC8280XP_MASTER_GEM_NOC_CFG, | |
496 | .channels = 1, | |
497 | .buswidth = 4, | |
498 | .num_links = 3, | |
499 | .links = { SC8280XP_SLAVE_SERVICE_GEM_NOC_1, | |
500 | SC8280XP_SLAVE_SERVICE_GEM_NOC_2, | |
501 | SC8280XP_SLAVE_SERVICE_GEM_NOC | |
502 | }, | |
503 | }; | |
504 | ||
505 | static struct qcom_icc_node qnm_gpu = { | |
506 | .name = "qnm_gpu", | |
507 | .id = SC8280XP_MASTER_GFX3D, | |
508 | .channels = 4, | |
509 | .buswidth = 32, | |
510 | .num_links = 2, | |
511 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
512 | SC8280XP_SLAVE_LLCC | |
513 | }, | |
514 | }; | |
515 | ||
516 | static struct qcom_icc_node qnm_mnoc_hf = { | |
517 | .name = "qnm_mnoc_hf", | |
518 | .id = SC8280XP_MASTER_MNOC_HF_MEM_NOC, | |
519 | .channels = 2, | |
520 | .buswidth = 32, | |
521 | .num_links = 2, | |
522 | .links = { SC8280XP_SLAVE_LLCC, | |
523 | SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC | |
524 | }, | |
525 | }; | |
526 | ||
527 | static struct qcom_icc_node qnm_mnoc_sf = { | |
528 | .name = "qnm_mnoc_sf", | |
529 | .id = SC8280XP_MASTER_MNOC_SF_MEM_NOC, | |
530 | .channels = 2, | |
531 | .buswidth = 32, | |
532 | .num_links = 2, | |
533 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
534 | SC8280XP_SLAVE_LLCC | |
535 | }, | |
536 | }; | |
537 | ||
538 | static struct qcom_icc_node qnm_pcie = { | |
539 | .name = "qnm_pcie", | |
540 | .id = SC8280XP_MASTER_ANOC_PCIE_GEM_NOC, | |
541 | .channels = 1, | |
542 | .buswidth = 32, | |
543 | .num_links = 2, | |
544 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
545 | SC8280XP_SLAVE_LLCC | |
546 | }, | |
547 | }; | |
548 | ||
549 | static struct qcom_icc_node qnm_snoc_gc = { | |
550 | .name = "qnm_snoc_gc", | |
551 | .id = SC8280XP_MASTER_SNOC_GC_MEM_NOC, | |
552 | .channels = 1, | |
553 | .buswidth = 8, | |
554 | .num_links = 1, | |
555 | .links = { SC8280XP_SLAVE_LLCC }, | |
556 | }; | |
557 | ||
558 | static struct qcom_icc_node qnm_snoc_sf = { | |
559 | .name = "qnm_snoc_sf", | |
560 | .id = SC8280XP_MASTER_SNOC_SF_MEM_NOC, | |
561 | .channels = 1, | |
562 | .buswidth = 16, | |
563 | .num_links = 3, | |
564 | .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, | |
565 | SC8280XP_SLAVE_LLCC, | |
566 | SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC }, | |
567 | }; | |
568 | ||
569 | static struct qcom_icc_node qhm_config_noc = { | |
570 | .name = "qhm_config_noc", | |
571 | .id = SC8280XP_MASTER_CNOC_LPASS_AG_NOC, | |
572 | .channels = 1, | |
573 | .buswidth = 4, | |
574 | .num_links = 6, | |
575 | .links = { SC8280XP_SLAVE_LPASS_CORE_CFG, | |
576 | SC8280XP_SLAVE_LPASS_LPI_CFG, | |
577 | SC8280XP_SLAVE_LPASS_MPU_CFG, | |
578 | SC8280XP_SLAVE_LPASS_TOP_CFG, | |
579 | SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, | |
580 | SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC | |
581 | }, | |
582 | }; | |
583 | ||
584 | static struct qcom_icc_node qxm_lpass_dsp = { | |
585 | .name = "qxm_lpass_dsp", | |
586 | .id = SC8280XP_MASTER_LPASS_PROC, | |
587 | .channels = 1, | |
588 | .buswidth = 8, | |
589 | .num_links = 4, | |
590 | .links = { SC8280XP_SLAVE_LPASS_TOP_CFG, | |
591 | SC8280XP_SLAVE_LPASS_SNOC, | |
592 | SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, | |
593 | SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC | |
594 | }, | |
595 | }; | |
596 | ||
597 | static struct qcom_icc_node llcc_mc = { | |
598 | .name = "llcc_mc", | |
599 | .id = SC8280XP_MASTER_LLCC, | |
600 | .channels = 8, | |
601 | .buswidth = 4, | |
602 | .num_links = 1, | |
603 | .links = { SC8280XP_SLAVE_EBI1 }, | |
604 | }; | |
605 | ||
606 | static struct qcom_icc_node qnm_camnoc_hf = { | |
607 | .name = "qnm_camnoc_hf", | |
608 | .id = SC8280XP_MASTER_CAMNOC_HF, | |
609 | .channels = 2, | |
610 | .buswidth = 32, | |
611 | .num_links = 1, | |
612 | .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, | |
613 | }; | |
614 | ||
615 | static struct qcom_icc_node qnm_mdp0_0 = { | |
616 | .name = "qnm_mdp0_0", | |
617 | .id = SC8280XP_MASTER_MDP0, | |
618 | .channels = 1, | |
619 | .buswidth = 32, | |
620 | .num_links = 1, | |
621 | .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, | |
622 | }; | |
623 | ||
624 | static struct qcom_icc_node qnm_mdp0_1 = { | |
625 | .name = "qnm_mdp0_1", | |
626 | .id = SC8280XP_MASTER_MDP1, | |
627 | .channels = 1, | |
628 | .buswidth = 32, | |
629 | .num_links = 1, | |
630 | .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, | |
631 | }; | |
632 | ||
633 | static struct qcom_icc_node qnm_mdp1_0 = { | |
634 | .name = "qnm_mdp1_0", | |
635 | .id = SC8280XP_MASTER_MDP_CORE1_0, | |
636 | .channels = 1, | |
637 | .buswidth = 32, | |
638 | .num_links = 1, | |
639 | .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, | |
640 | }; | |
641 | ||
642 | static struct qcom_icc_node qnm_mdp1_1 = { | |
643 | .name = "qnm_mdp1_1", | |
644 | .id = SC8280XP_MASTER_MDP_CORE1_1, | |
645 | .channels = 1, | |
646 | .buswidth = 32, | |
647 | .num_links = 1, | |
648 | .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, | |
649 | }; | |
650 | ||
651 | static struct qcom_icc_node qnm_mnoc_cfg = { | |
652 | .name = "qnm_mnoc_cfg", | |
653 | .id = SC8280XP_MASTER_CNOC_MNOC_CFG, | |
654 | .channels = 1, | |
655 | .buswidth = 4, | |
656 | .num_links = 1, | |
657 | .links = { SC8280XP_SLAVE_SERVICE_MNOC }, | |
658 | }; | |
659 | ||
660 | static struct qcom_icc_node qnm_rot_0 = { | |
661 | .name = "qnm_rot_0", | |
662 | .id = SC8280XP_MASTER_ROTATOR, | |
663 | .channels = 1, | |
664 | .buswidth = 32, | |
665 | .num_links = 1, | |
666 | .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, | |
667 | }; | |
668 | ||
669 | static struct qcom_icc_node qnm_rot_1 = { | |
670 | .name = "qnm_rot_1", | |
671 | .id = SC8280XP_MASTER_ROTATOR_1, | |
672 | .channels = 1, | |
673 | .buswidth = 32, | |
674 | .num_links = 1, | |
675 | .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, | |
676 | }; | |
677 | ||
678 | static struct qcom_icc_node qnm_video0 = { | |
679 | .name = "qnm_video0", | |
680 | .id = SC8280XP_MASTER_VIDEO_P0, | |
681 | .channels = 1, | |
682 | .buswidth = 32, | |
683 | .num_links = 1, | |
684 | .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, | |
685 | }; | |
686 | ||
687 | static struct qcom_icc_node qnm_video1 = { | |
688 | .name = "qnm_video1", | |
689 | .id = SC8280XP_MASTER_VIDEO_P1, | |
690 | .channels = 1, | |
691 | .buswidth = 32, | |
692 | .num_links = 1, | |
693 | .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, | |
694 | }; | |
695 | ||
696 | static struct qcom_icc_node qnm_video_cvp = { | |
697 | .name = "qnm_video_cvp", | |
698 | .id = SC8280XP_MASTER_VIDEO_PROC, | |
699 | .channels = 1, | |
700 | .buswidth = 32, | |
701 | .num_links = 1, | |
702 | .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, | |
703 | }; | |
704 | ||
705 | static struct qcom_icc_node qxm_camnoc_icp = { | |
706 | .name = "qxm_camnoc_icp", | |
707 | .id = SC8280XP_MASTER_CAMNOC_ICP, | |
708 | .channels = 1, | |
709 | .buswidth = 8, | |
710 | .num_links = 1, | |
711 | .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, | |
712 | }; | |
713 | ||
714 | static struct qcom_icc_node qxm_camnoc_sf = { | |
715 | .name = "qxm_camnoc_sf", | |
716 | .id = SC8280XP_MASTER_CAMNOC_SF, | |
717 | .channels = 1, | |
718 | .buswidth = 32, | |
719 | .num_links = 1, | |
720 | .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, | |
721 | }; | |
722 | ||
723 | static struct qcom_icc_node qhm_nsp_noc_config = { | |
724 | .name = "qhm_nsp_noc_config", | |
725 | .id = SC8280XP_MASTER_CDSP_NOC_CFG, | |
726 | .channels = 1, | |
727 | .buswidth = 4, | |
728 | .num_links = 1, | |
729 | .links = { SC8280XP_SLAVE_SERVICE_NSP_NOC }, | |
730 | }; | |
731 | ||
732 | static struct qcom_icc_node qxm_nsp = { | |
733 | .name = "qxm_nsp", | |
734 | .id = SC8280XP_MASTER_CDSP_PROC, | |
735 | .channels = 2, | |
736 | .buswidth = 32, | |
737 | .num_links = 2, | |
738 | .links = { SC8280XP_SLAVE_CDSP_MEM_NOC, | |
739 | SC8280XP_SLAVE_NSP_XFR | |
740 | }, | |
741 | }; | |
742 | ||
743 | static struct qcom_icc_node qhm_nspb_noc_config = { | |
744 | .name = "qhm_nspb_noc_config", | |
745 | .id = SC8280XP_MASTER_CDSPB_NOC_CFG, | |
746 | .channels = 1, | |
747 | .buswidth = 4, | |
748 | .num_links = 1, | |
749 | .links = { SC8280XP_SLAVE_SERVICE_NSPB_NOC }, | |
750 | }; | |
751 | ||
752 | static struct qcom_icc_node qxm_nspb = { | |
753 | .name = "qxm_nspb", | |
754 | .id = SC8280XP_MASTER_CDSP_PROC_B, | |
755 | .channels = 2, | |
756 | .buswidth = 32, | |
757 | .num_links = 2, | |
758 | .links = { SC8280XP_SLAVE_CDSPB_MEM_NOC, | |
759 | SC8280XP_SLAVE_NSPB_XFR | |
760 | }, | |
761 | }; | |
762 | ||
763 | static struct qcom_icc_node qnm_aggre1_noc = { | |
764 | .name = "qnm_aggre1_noc", | |
765 | .id = SC8280XP_MASTER_A1NOC_SNOC, | |
766 | .channels = 1, | |
767 | .buswidth = 16, | |
768 | .num_links = 1, | |
769 | .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, | |
770 | }; | |
771 | ||
772 | static struct qcom_icc_node qnm_aggre2_noc = { | |
773 | .name = "qnm_aggre2_noc", | |
774 | .id = SC8280XP_MASTER_A2NOC_SNOC, | |
775 | .channels = 1, | |
776 | .buswidth = 16, | |
777 | .num_links = 1, | |
778 | .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, | |
779 | }; | |
780 | ||
781 | static struct qcom_icc_node qnm_aggre_usb_noc = { | |
782 | .name = "qnm_aggre_usb_noc", | |
783 | .id = SC8280XP_MASTER_USB_NOC_SNOC, | |
784 | .channels = 1, | |
785 | .buswidth = 16, | |
786 | .num_links = 1, | |
787 | .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, | |
788 | }; | |
789 | ||
790 | static struct qcom_icc_node qnm_lpass_noc = { | |
791 | .name = "qnm_lpass_noc", | |
792 | .id = SC8280XP_MASTER_LPASS_ANOC, | |
793 | .channels = 1, | |
794 | .buswidth = 16, | |
795 | .num_links = 1, | |
796 | .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, | |
797 | }; | |
798 | ||
799 | static struct qcom_icc_node qnm_snoc_cfg = { | |
800 | .name = "qnm_snoc_cfg", | |
801 | .id = SC8280XP_MASTER_SNOC_CFG, | |
802 | .channels = 1, | |
803 | .buswidth = 4, | |
804 | .num_links = 1, | |
805 | .links = { SC8280XP_SLAVE_SERVICE_SNOC }, | |
806 | }; | |
807 | ||
808 | static struct qcom_icc_node qxm_pimem = { | |
809 | .name = "qxm_pimem", | |
810 | .id = SC8280XP_MASTER_PIMEM, | |
811 | .channels = 1, | |
812 | .buswidth = 8, | |
813 | .num_links = 1, | |
814 | .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, | |
815 | }; | |
816 | ||
817 | static struct qcom_icc_node xm_gic = { | |
818 | .name = "xm_gic", | |
819 | .id = SC8280XP_MASTER_GIC, | |
820 | .channels = 1, | |
821 | .buswidth = 8, | |
822 | .num_links = 1, | |
823 | .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, | |
824 | }; | |
825 | ||
826 | static struct qcom_icc_node qns_a1noc_snoc = { | |
827 | .name = "qns_a1noc_snoc", | |
828 | .id = SC8280XP_SLAVE_A1NOC_SNOC, | |
829 | .channels = 1, | |
830 | .buswidth = 16, | |
831 | .num_links = 1, | |
832 | .links = { SC8280XP_MASTER_A1NOC_SNOC }, | |
833 | }; | |
834 | ||
835 | static struct qcom_icc_node qns_aggre_usb_snoc = { | |
836 | .name = "qns_aggre_usb_snoc", | |
837 | .id = SC8280XP_SLAVE_USB_NOC_SNOC, | |
838 | .channels = 1, | |
839 | .buswidth = 16, | |
840 | .num_links = 1, | |
841 | .links = { SC8280XP_MASTER_USB_NOC_SNOC }, | |
842 | }; | |
843 | ||
844 | static struct qcom_icc_node srvc_aggre1_noc = { | |
845 | .name = "srvc_aggre1_noc", | |
846 | .id = SC8280XP_SLAVE_SERVICE_A1NOC, | |
847 | .channels = 1, | |
848 | .buswidth = 4, | |
849 | }; | |
850 | ||
851 | static struct qcom_icc_node qns_a2noc_snoc = { | |
852 | .name = "qns_a2noc_snoc", | |
853 | .id = SC8280XP_SLAVE_A2NOC_SNOC, | |
854 | .channels = 1, | |
855 | .buswidth = 16, | |
856 | .num_links = 1, | |
857 | .links = { SC8280XP_MASTER_A2NOC_SNOC }, | |
858 | }; | |
859 | ||
860 | static struct qcom_icc_node qns_pcie_gem_noc = { | |
861 | .name = "qns_pcie_gem_noc", | |
862 | .id = SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC, | |
863 | .channels = 1, | |
864 | .buswidth = 32, | |
865 | .num_links = 1, | |
866 | .links = { SC8280XP_MASTER_ANOC_PCIE_GEM_NOC }, | |
867 | }; | |
868 | ||
869 | static struct qcom_icc_node srvc_aggre2_noc = { | |
870 | .name = "srvc_aggre2_noc", | |
871 | .id = SC8280XP_SLAVE_SERVICE_A2NOC, | |
872 | .channels = 1, | |
873 | .buswidth = 4, | |
874 | }; | |
875 | ||
f29dabda BA |
876 | static struct qcom_icc_node qup0_core_slave = { |
877 | .name = "qup0_core_slave", | |
878 | .id = SC8280XP_SLAVE_QUP_CORE_0, | |
879 | .channels = 1, | |
880 | .buswidth = 4, | |
881 | }; | |
882 | ||
883 | static struct qcom_icc_node qup1_core_slave = { | |
884 | .name = "qup1_core_slave", | |
885 | .id = SC8280XP_SLAVE_QUP_CORE_1, | |
886 | .channels = 1, | |
887 | .buswidth = 4, | |
888 | }; | |
889 | ||
890 | static struct qcom_icc_node qup2_core_slave = { | |
891 | .name = "qup2_core_slave", | |
892 | .id = SC8280XP_SLAVE_QUP_CORE_2, | |
893 | .channels = 1, | |
894 | .buswidth = 4, | |
895 | }; | |
896 | ||
897 | static struct qcom_icc_node qhs_ahb2phy0 = { | |
898 | .name = "qhs_ahb2phy0", | |
899 | .id = SC8280XP_SLAVE_AHB2PHY_0, | |
900 | .channels = 1, | |
901 | .buswidth = 4, | |
902 | }; | |
903 | ||
904 | static struct qcom_icc_node qhs_ahb2phy1 = { | |
905 | .name = "qhs_ahb2phy1", | |
906 | .id = SC8280XP_SLAVE_AHB2PHY_1, | |
907 | .channels = 1, | |
908 | .buswidth = 4, | |
909 | }; | |
910 | ||
911 | static struct qcom_icc_node qhs_ahb2phy2 = { | |
912 | .name = "qhs_ahb2phy2", | |
913 | .id = SC8280XP_SLAVE_AHB2PHY_2, | |
914 | .channels = 1, | |
915 | .buswidth = 4, | |
916 | }; | |
917 | ||
918 | static struct qcom_icc_node qhs_aoss = { | |
919 | .name = "qhs_aoss", | |
920 | .id = SC8280XP_SLAVE_AOSS, | |
921 | .channels = 1, | |
922 | .buswidth = 4, | |
923 | }; | |
924 | ||
925 | static struct qcom_icc_node qhs_apss = { | |
926 | .name = "qhs_apss", | |
927 | .id = SC8280XP_SLAVE_APPSS, | |
928 | .channels = 1, | |
929 | .buswidth = 8, | |
930 | }; | |
931 | ||
932 | static struct qcom_icc_node qhs_camera_cfg = { | |
933 | .name = "qhs_camera_cfg", | |
934 | .id = SC8280XP_SLAVE_CAMERA_CFG, | |
935 | .channels = 1, | |
936 | .buswidth = 4, | |
937 | }; | |
938 | ||
939 | static struct qcom_icc_node qhs_clk_ctl = { | |
940 | .name = "qhs_clk_ctl", | |
941 | .id = SC8280XP_SLAVE_CLK_CTL, | |
942 | .channels = 1, | |
943 | .buswidth = 4, | |
944 | }; | |
945 | ||
946 | static struct qcom_icc_node qhs_compute0_cfg = { | |
947 | .name = "qhs_compute0_cfg", | |
948 | .id = SC8280XP_SLAVE_CDSP_CFG, | |
949 | .channels = 1, | |
950 | .buswidth = 4, | |
951 | .num_links = 1, | |
952 | .links = { SC8280XP_MASTER_CDSP_NOC_CFG }, | |
953 | }; | |
954 | ||
955 | static struct qcom_icc_node qhs_compute1_cfg = { | |
956 | .name = "qhs_compute1_cfg", | |
957 | .id = SC8280XP_SLAVE_CDSP1_CFG, | |
958 | .channels = 1, | |
959 | .buswidth = 4, | |
960 | .num_links = 1, | |
961 | .links = { SC8280XP_MASTER_CDSPB_NOC_CFG }, | |
962 | }; | |
963 | ||
964 | static struct qcom_icc_node qhs_cpr_cx = { | |
965 | .name = "qhs_cpr_cx", | |
966 | .id = SC8280XP_SLAVE_RBCPR_CX_CFG, | |
967 | .channels = 1, | |
968 | .buswidth = 4, | |
969 | }; | |
970 | ||
971 | static struct qcom_icc_node qhs_cpr_mmcx = { | |
972 | .name = "qhs_cpr_mmcx", | |
973 | .id = SC8280XP_SLAVE_RBCPR_MMCX_CFG, | |
974 | .channels = 1, | |
975 | .buswidth = 4, | |
976 | }; | |
977 | ||
978 | static struct qcom_icc_node qhs_cpr_mx = { | |
979 | .name = "qhs_cpr_mx", | |
980 | .id = SC8280XP_SLAVE_RBCPR_MX_CFG, | |
981 | .channels = 1, | |
982 | .buswidth = 4, | |
983 | }; | |
984 | ||
985 | static struct qcom_icc_node qhs_cpr_nspcx = { | |
986 | .name = "qhs_cpr_nspcx", | |
987 | .id = SC8280XP_SLAVE_CPR_NSPCX, | |
988 | .channels = 1, | |
989 | .buswidth = 4, | |
990 | }; | |
991 | ||
992 | static struct qcom_icc_node qhs_crypto0_cfg = { | |
993 | .name = "qhs_crypto0_cfg", | |
994 | .id = SC8280XP_SLAVE_CRYPTO_0_CFG, | |
995 | .channels = 1, | |
996 | .buswidth = 4, | |
997 | }; | |
998 | ||
999 | static struct qcom_icc_node qhs_cx_rdpm = { | |
1000 | .name = "qhs_cx_rdpm", | |
1001 | .id = SC8280XP_SLAVE_CX_RDPM, | |
1002 | .channels = 1, | |
1003 | .buswidth = 4, | |
1004 | }; | |
1005 | ||
1006 | static struct qcom_icc_node qhs_dcc_cfg = { | |
1007 | .name = "qhs_dcc_cfg", | |
1008 | .id = SC8280XP_SLAVE_DCC_CFG, | |
1009 | .channels = 1, | |
1010 | .buswidth = 4, | |
1011 | }; | |
1012 | ||
1013 | static struct qcom_icc_node qhs_display0_cfg = { | |
1014 | .name = "qhs_display0_cfg", | |
1015 | .id = SC8280XP_SLAVE_DISPLAY_CFG, | |
1016 | .channels = 1, | |
1017 | .buswidth = 4, | |
1018 | }; | |
1019 | ||
1020 | static struct qcom_icc_node qhs_display1_cfg = { | |
1021 | .name = "qhs_display1_cfg", | |
1022 | .id = SC8280XP_SLAVE_DISPLAY1_CFG, | |
1023 | .channels = 1, | |
1024 | .buswidth = 4, | |
1025 | }; | |
1026 | ||
1027 | static struct qcom_icc_node qhs_emac0_cfg = { | |
1028 | .name = "qhs_emac0_cfg", | |
1029 | .id = SC8280XP_SLAVE_EMAC_CFG, | |
1030 | .channels = 1, | |
1031 | .buswidth = 4, | |
1032 | }; | |
1033 | ||
1034 | static struct qcom_icc_node qhs_emac1_cfg = { | |
1035 | .name = "qhs_emac1_cfg", | |
1036 | .id = SC8280XP_SLAVE_EMAC1_CFG, | |
1037 | .channels = 1, | |
1038 | .buswidth = 4, | |
1039 | }; | |
1040 | ||
1041 | static struct qcom_icc_node qhs_gpuss_cfg = { | |
1042 | .name = "qhs_gpuss_cfg", | |
1043 | .id = SC8280XP_SLAVE_GFX3D_CFG, | |
1044 | .channels = 1, | |
1045 | .buswidth = 8, | |
1046 | }; | |
1047 | ||
1048 | static struct qcom_icc_node qhs_hwkm = { | |
1049 | .name = "qhs_hwkm", | |
1050 | .id = SC8280XP_SLAVE_HWKM, | |
1051 | .channels = 1, | |
1052 | .buswidth = 4, | |
1053 | }; | |
1054 | ||
1055 | static struct qcom_icc_node qhs_imem_cfg = { | |
1056 | .name = "qhs_imem_cfg", | |
1057 | .id = SC8280XP_SLAVE_IMEM_CFG, | |
1058 | .channels = 1, | |
1059 | .buswidth = 4, | |
1060 | }; | |
1061 | ||
1062 | static struct qcom_icc_node qhs_ipa = { | |
1063 | .name = "qhs_ipa", | |
1064 | .id = SC8280XP_SLAVE_IPA_CFG, | |
1065 | .channels = 1, | |
1066 | .buswidth = 4, | |
1067 | }; | |
1068 | ||
1069 | static struct qcom_icc_node qhs_ipc_router = { | |
1070 | .name = "qhs_ipc_router", | |
1071 | .id = SC8280XP_SLAVE_IPC_ROUTER_CFG, | |
1072 | .channels = 1, | |
1073 | .buswidth = 4, | |
1074 | }; | |
1075 | ||
1076 | static struct qcom_icc_node qhs_lpass_cfg = { | |
1077 | .name = "qhs_lpass_cfg", | |
1078 | .id = SC8280XP_SLAVE_LPASS, | |
1079 | .channels = 1, | |
1080 | .buswidth = 4, | |
1081 | .num_links = 1, | |
1082 | .links = { SC8280XP_MASTER_CNOC_LPASS_AG_NOC }, | |
1083 | }; | |
1084 | ||
1085 | static struct qcom_icc_node qhs_mx_rdpm = { | |
1086 | .name = "qhs_mx_rdpm", | |
1087 | .id = SC8280XP_SLAVE_MX_RDPM, | |
1088 | .channels = 1, | |
1089 | .buswidth = 4, | |
1090 | }; | |
1091 | ||
1092 | static struct qcom_icc_node qhs_mxc_rdpm = { | |
1093 | .name = "qhs_mxc_rdpm", | |
1094 | .id = SC8280XP_SLAVE_MXC_RDPM, | |
1095 | .channels = 1, | |
1096 | .buswidth = 4, | |
1097 | }; | |
1098 | ||
1099 | static struct qcom_icc_node qhs_pcie0_cfg = { | |
1100 | .name = "qhs_pcie0_cfg", | |
1101 | .id = SC8280XP_SLAVE_PCIE_0_CFG, | |
1102 | .channels = 1, | |
1103 | .buswidth = 4, | |
1104 | }; | |
1105 | ||
1106 | static struct qcom_icc_node qhs_pcie1_cfg = { | |
1107 | .name = "qhs_pcie1_cfg", | |
1108 | .id = SC8280XP_SLAVE_PCIE_1_CFG, | |
1109 | .channels = 1, | |
1110 | .buswidth = 4, | |
1111 | }; | |
1112 | ||
1113 | static struct qcom_icc_node qhs_pcie2a_cfg = { | |
1114 | .name = "qhs_pcie2a_cfg", | |
1115 | .id = SC8280XP_SLAVE_PCIE_2A_CFG, | |
1116 | .channels = 1, | |
1117 | .buswidth = 4, | |
1118 | }; | |
1119 | ||
1120 | static struct qcom_icc_node qhs_pcie2b_cfg = { | |
1121 | .name = "qhs_pcie2b_cfg", | |
1122 | .id = SC8280XP_SLAVE_PCIE_2B_CFG, | |
1123 | .channels = 1, | |
1124 | .buswidth = 4, | |
1125 | }; | |
1126 | ||
1127 | static struct qcom_icc_node qhs_pcie3a_cfg = { | |
1128 | .name = "qhs_pcie3a_cfg", | |
1129 | .id = SC8280XP_SLAVE_PCIE_3A_CFG, | |
1130 | .channels = 1, | |
1131 | .buswidth = 4, | |
1132 | }; | |
1133 | ||
1134 | static struct qcom_icc_node qhs_pcie3b_cfg = { | |
1135 | .name = "qhs_pcie3b_cfg", | |
1136 | .id = SC8280XP_SLAVE_PCIE_3B_CFG, | |
1137 | .channels = 1, | |
1138 | .buswidth = 4, | |
1139 | }; | |
1140 | ||
1141 | static struct qcom_icc_node qhs_pcie4_cfg = { | |
1142 | .name = "qhs_pcie4_cfg", | |
1143 | .id = SC8280XP_SLAVE_PCIE_4_CFG, | |
1144 | .channels = 1, | |
1145 | .buswidth = 4, | |
1146 | }; | |
1147 | ||
1148 | static struct qcom_icc_node qhs_pcie_rsc_cfg = { | |
1149 | .name = "qhs_pcie_rsc_cfg", | |
1150 | .id = SC8280XP_SLAVE_PCIE_RSC_CFG, | |
1151 | .channels = 1, | |
1152 | .buswidth = 4, | |
1153 | }; | |
1154 | ||
1155 | static struct qcom_icc_node qhs_pdm = { | |
1156 | .name = "qhs_pdm", | |
1157 | .id = SC8280XP_SLAVE_PDM, | |
1158 | .channels = 1, | |
1159 | .buswidth = 4, | |
1160 | }; | |
1161 | ||
1162 | static struct qcom_icc_node qhs_pimem_cfg = { | |
1163 | .name = "qhs_pimem_cfg", | |
1164 | .id = SC8280XP_SLAVE_PIMEM_CFG, | |
1165 | .channels = 1, | |
1166 | .buswidth = 4, | |
1167 | }; | |
1168 | ||
1169 | static struct qcom_icc_node qhs_pka_wrapper_cfg = { | |
1170 | .name = "qhs_pka_wrapper_cfg", | |
1171 | .id = SC8280XP_SLAVE_PKA_WRAPPER_CFG, | |
1172 | .channels = 1, | |
1173 | .buswidth = 4, | |
1174 | }; | |
1175 | ||
1176 | static struct qcom_icc_node qhs_pmu_wrapper_cfg = { | |
1177 | .name = "qhs_pmu_wrapper_cfg", | |
1178 | .id = SC8280XP_SLAVE_PMU_WRAPPER_CFG, | |
1179 | .channels = 1, | |
1180 | .buswidth = 4, | |
1181 | }; | |
1182 | ||
1183 | static struct qcom_icc_node qhs_qdss_cfg = { | |
1184 | .name = "qhs_qdss_cfg", | |
1185 | .id = SC8280XP_SLAVE_QDSS_CFG, | |
1186 | .channels = 1, | |
1187 | .buswidth = 4, | |
1188 | }; | |
1189 | ||
1190 | static struct qcom_icc_node qhs_qspi = { | |
1191 | .name = "qhs_qspi", | |
1192 | .id = SC8280XP_SLAVE_QSPI_0, | |
1193 | .channels = 1, | |
1194 | .buswidth = 4, | |
1195 | }; | |
1196 | ||
1197 | static struct qcom_icc_node qhs_qup0 = { | |
1198 | .name = "qhs_qup0", | |
1199 | .id = SC8280XP_SLAVE_QUP_0, | |
1200 | .channels = 1, | |
1201 | .buswidth = 4, | |
1202 | }; | |
1203 | ||
1204 | static struct qcom_icc_node qhs_qup1 = { | |
1205 | .name = "qhs_qup1", | |
1206 | .id = SC8280XP_SLAVE_QUP_1, | |
1207 | .channels = 1, | |
1208 | .buswidth = 4, | |
1209 | }; | |
1210 | ||
1211 | static struct qcom_icc_node qhs_qup2 = { | |
1212 | .name = "qhs_qup2", | |
1213 | .id = SC8280XP_SLAVE_QUP_2, | |
1214 | .channels = 1, | |
1215 | .buswidth = 4, | |
1216 | }; | |
1217 | ||
1218 | static struct qcom_icc_node qhs_sdc2 = { | |
1219 | .name = "qhs_sdc2", | |
1220 | .id = SC8280XP_SLAVE_SDCC_2, | |
1221 | .channels = 1, | |
1222 | .buswidth = 4, | |
1223 | }; | |
1224 | ||
1225 | static struct qcom_icc_node qhs_sdc4 = { | |
1226 | .name = "qhs_sdc4", | |
1227 | .id = SC8280XP_SLAVE_SDCC_4, | |
1228 | .channels = 1, | |
1229 | .buswidth = 4, | |
1230 | }; | |
1231 | ||
1232 | static struct qcom_icc_node qhs_security = { | |
1233 | .name = "qhs_security", | |
1234 | .id = SC8280XP_SLAVE_SECURITY, | |
1235 | .channels = 1, | |
1236 | .buswidth = 4, | |
1237 | }; | |
1238 | ||
1239 | static struct qcom_icc_node qhs_smmuv3_cfg = { | |
1240 | .name = "qhs_smmuv3_cfg", | |
1241 | .id = SC8280XP_SLAVE_SMMUV3_CFG, | |
1242 | .channels = 1, | |
1243 | .buswidth = 8, | |
1244 | }; | |
1245 | ||
1246 | static struct qcom_icc_node qhs_smss_cfg = { | |
1247 | .name = "qhs_smss_cfg", | |
1248 | .id = SC8280XP_SLAVE_SMSS_CFG, | |
1249 | .channels = 1, | |
1250 | .buswidth = 4, | |
1251 | }; | |
1252 | ||
1253 | static struct qcom_icc_node qhs_spss_cfg = { | |
1254 | .name = "qhs_spss_cfg", | |
1255 | .id = SC8280XP_SLAVE_SPSS_CFG, | |
1256 | .channels = 1, | |
1257 | .buswidth = 4, | |
1258 | }; | |
1259 | ||
1260 | static struct qcom_icc_node qhs_tcsr = { | |
1261 | .name = "qhs_tcsr", | |
1262 | .id = SC8280XP_SLAVE_TCSR, | |
1263 | .channels = 1, | |
1264 | .buswidth = 4, | |
1265 | }; | |
1266 | ||
1267 | static struct qcom_icc_node qhs_tlmm = { | |
1268 | .name = "qhs_tlmm", | |
1269 | .id = SC8280XP_SLAVE_TLMM, | |
1270 | .channels = 1, | |
1271 | .buswidth = 4, | |
1272 | }; | |
1273 | ||
1274 | static struct qcom_icc_node qhs_ufs_card_cfg = { | |
1275 | .name = "qhs_ufs_card_cfg", | |
1276 | .id = SC8280XP_SLAVE_UFS_CARD_CFG, | |
1277 | .channels = 1, | |
1278 | .buswidth = 4, | |
1279 | }; | |
1280 | ||
1281 | static struct qcom_icc_node qhs_ufs_mem_cfg = { | |
1282 | .name = "qhs_ufs_mem_cfg", | |
1283 | .id = SC8280XP_SLAVE_UFS_MEM_CFG, | |
1284 | .channels = 1, | |
1285 | .buswidth = 4, | |
1286 | }; | |
1287 | ||
1288 | static struct qcom_icc_node qhs_usb3_0 = { | |
1289 | .name = "qhs_usb3_0", | |
1290 | .id = SC8280XP_SLAVE_USB3_0, | |
1291 | .channels = 1, | |
1292 | .buswidth = 4, | |
1293 | }; | |
1294 | ||
1295 | static struct qcom_icc_node qhs_usb3_1 = { | |
1296 | .name = "qhs_usb3_1", | |
1297 | .id = SC8280XP_SLAVE_USB3_1, | |
1298 | .channels = 1, | |
1299 | .buswidth = 4, | |
1300 | }; | |
1301 | ||
1302 | static struct qcom_icc_node qhs_usb3_mp = { | |
1303 | .name = "qhs_usb3_mp", | |
1304 | .id = SC8280XP_SLAVE_USB3_MP, | |
1305 | .channels = 1, | |
1306 | .buswidth = 4, | |
1307 | }; | |
1308 | ||
1309 | static struct qcom_icc_node qhs_usb4_host_0 = { | |
1310 | .name = "qhs_usb4_host_0", | |
1311 | .id = SC8280XP_SLAVE_USB4_0, | |
1312 | .channels = 1, | |
1313 | .buswidth = 4, | |
1314 | }; | |
1315 | ||
1316 | static struct qcom_icc_node qhs_usb4_host_1 = { | |
1317 | .name = "qhs_usb4_host_1", | |
1318 | .id = SC8280XP_SLAVE_USB4_1, | |
1319 | .channels = 1, | |
1320 | .buswidth = 4, | |
1321 | }; | |
1322 | ||
1323 | static struct qcom_icc_node qhs_venus_cfg = { | |
1324 | .name = "qhs_venus_cfg", | |
1325 | .id = SC8280XP_SLAVE_VENUS_CFG, | |
1326 | .channels = 1, | |
1327 | .buswidth = 4, | |
1328 | }; | |
1329 | ||
1330 | static struct qcom_icc_node qhs_vsense_ctrl_cfg = { | |
1331 | .name = "qhs_vsense_ctrl_cfg", | |
1332 | .id = SC8280XP_SLAVE_VSENSE_CTRL_CFG, | |
1333 | .channels = 1, | |
1334 | .buswidth = 4, | |
1335 | }; | |
1336 | ||
1337 | static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = { | |
1338 | .name = "qhs_vsense_ctrl_r_cfg", | |
1339 | .id = SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, | |
1340 | .channels = 1, | |
1341 | .buswidth = 4, | |
1342 | }; | |
1343 | ||
1344 | static struct qcom_icc_node qns_a1_noc_cfg = { | |
1345 | .name = "qns_a1_noc_cfg", | |
1346 | .id = SC8280XP_SLAVE_A1NOC_CFG, | |
1347 | .channels = 1, | |
1348 | .buswidth = 4, | |
1349 | .num_links = 1, | |
1350 | .links = { SC8280XP_MASTER_A1NOC_CFG }, | |
1351 | }; | |
1352 | ||
1353 | static struct qcom_icc_node qns_a2_noc_cfg = { | |
1354 | .name = "qns_a2_noc_cfg", | |
1355 | .id = SC8280XP_SLAVE_A2NOC_CFG, | |
1356 | .channels = 1, | |
1357 | .buswidth = 4, | |
1358 | .num_links = 1, | |
1359 | .links = { SC8280XP_MASTER_A2NOC_CFG }, | |
1360 | }; | |
1361 | ||
1362 | static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = { | |
1363 | .name = "qns_anoc_pcie_bridge_cfg", | |
1364 | .id = SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, | |
1365 | .channels = 1, | |
1366 | .buswidth = 4, | |
1367 | }; | |
1368 | ||
1369 | static struct qcom_icc_node qns_ddrss_cfg = { | |
1370 | .name = "qns_ddrss_cfg", | |
1371 | .id = SC8280XP_SLAVE_DDRSS_CFG, | |
1372 | .channels = 1, | |
1373 | .buswidth = 4, | |
1374 | .num_links = 1, | |
1375 | .links = { SC8280XP_MASTER_CNOC_DC_NOC }, | |
1376 | }; | |
1377 | ||
1378 | static struct qcom_icc_node qns_mnoc_cfg = { | |
1379 | .name = "qns_mnoc_cfg", | |
1380 | .id = SC8280XP_SLAVE_CNOC_MNOC_CFG, | |
1381 | .channels = 1, | |
1382 | .buswidth = 4, | |
1383 | .num_links = 1, | |
1384 | .links = { SC8280XP_MASTER_CNOC_MNOC_CFG }, | |
1385 | }; | |
1386 | ||
1387 | static struct qcom_icc_node qns_snoc_cfg = { | |
1388 | .name = "qns_snoc_cfg", | |
1389 | .id = SC8280XP_SLAVE_SNOC_CFG, | |
1390 | .channels = 1, | |
1391 | .buswidth = 4, | |
1392 | .num_links = 1, | |
1393 | .links = { SC8280XP_MASTER_SNOC_CFG }, | |
1394 | }; | |
1395 | ||
1396 | static struct qcom_icc_node qns_snoc_sf_bridge_cfg = { | |
1397 | .name = "qns_snoc_sf_bridge_cfg", | |
1398 | .id = SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, | |
1399 | .channels = 1, | |
1400 | .buswidth = 4, | |
1401 | }; | |
1402 | ||
1403 | static struct qcom_icc_node qxs_imem = { | |
1404 | .name = "qxs_imem", | |
1405 | .id = SC8280XP_SLAVE_IMEM, | |
1406 | .channels = 1, | |
1407 | .buswidth = 8, | |
1408 | }; | |
1409 | ||
1410 | static struct qcom_icc_node qxs_pimem = { | |
1411 | .name = "qxs_pimem", | |
1412 | .id = SC8280XP_SLAVE_PIMEM, | |
1413 | .channels = 1, | |
1414 | .buswidth = 8, | |
1415 | }; | |
1416 | ||
1417 | static struct qcom_icc_node srvc_cnoc = { | |
1418 | .name = "srvc_cnoc", | |
1419 | .id = SC8280XP_SLAVE_SERVICE_CNOC, | |
1420 | .channels = 1, | |
1421 | .buswidth = 4, | |
1422 | }; | |
1423 | ||
1424 | static struct qcom_icc_node xs_pcie_0 = { | |
1425 | .name = "xs_pcie_0", | |
1426 | .id = SC8280XP_SLAVE_PCIE_0, | |
1427 | .channels = 1, | |
1428 | .buswidth = 16, | |
1429 | }; | |
1430 | ||
1431 | static struct qcom_icc_node xs_pcie_1 = { | |
1432 | .name = "xs_pcie_1", | |
1433 | .id = SC8280XP_SLAVE_PCIE_1, | |
1434 | .channels = 1, | |
1435 | .buswidth = 16, | |
1436 | }; | |
1437 | ||
1438 | static struct qcom_icc_node xs_pcie_2a = { | |
1439 | .name = "xs_pcie_2a", | |
1440 | .id = SC8280XP_SLAVE_PCIE_2A, | |
1441 | .channels = 1, | |
1442 | .buswidth = 16, | |
1443 | }; | |
1444 | ||
1445 | static struct qcom_icc_node xs_pcie_2b = { | |
1446 | .name = "xs_pcie_2b", | |
1447 | .id = SC8280XP_SLAVE_PCIE_2B, | |
1448 | .channels = 1, | |
1449 | .buswidth = 8, | |
1450 | }; | |
1451 | ||
1452 | static struct qcom_icc_node xs_pcie_3a = { | |
1453 | .name = "xs_pcie_3a", | |
1454 | .id = SC8280XP_SLAVE_PCIE_3A, | |
1455 | .channels = 1, | |
1456 | .buswidth = 16, | |
1457 | }; | |
1458 | ||
1459 | static struct qcom_icc_node xs_pcie_3b = { | |
1460 | .name = "xs_pcie_3b", | |
1461 | .id = SC8280XP_SLAVE_PCIE_3B, | |
1462 | .channels = 1, | |
1463 | .buswidth = 8, | |
1464 | }; | |
1465 | ||
1466 | static struct qcom_icc_node xs_pcie_4 = { | |
1467 | .name = "xs_pcie_4", | |
1468 | .id = SC8280XP_SLAVE_PCIE_4, | |
1469 | .channels = 1, | |
1470 | .buswidth = 8, | |
1471 | }; | |
1472 | ||
1473 | static struct qcom_icc_node xs_qdss_stm = { | |
1474 | .name = "xs_qdss_stm", | |
1475 | .id = SC8280XP_SLAVE_QDSS_STM, | |
1476 | .channels = 1, | |
1477 | .buswidth = 4, | |
1478 | }; | |
1479 | ||
1480 | static struct qcom_icc_node xs_smss = { | |
1481 | .name = "xs_smss", | |
1482 | .id = SC8280XP_SLAVE_SMSS, | |
1483 | .channels = 1, | |
1484 | .buswidth = 8, | |
1485 | }; | |
1486 | ||
1487 | static struct qcom_icc_node xs_sys_tcu_cfg = { | |
1488 | .name = "xs_sys_tcu_cfg", | |
1489 | .id = SC8280XP_SLAVE_TCU, | |
1490 | .channels = 1, | |
1491 | .buswidth = 8, | |
1492 | }; | |
1493 | ||
1494 | static struct qcom_icc_node qhs_llcc = { | |
1495 | .name = "qhs_llcc", | |
1496 | .id = SC8280XP_SLAVE_LLCC_CFG, | |
1497 | .channels = 1, | |
1498 | .buswidth = 4, | |
1499 | }; | |
1500 | ||
1501 | static struct qcom_icc_node qns_gemnoc = { | |
1502 | .name = "qns_gemnoc", | |
1503 | .id = SC8280XP_SLAVE_GEM_NOC_CFG, | |
1504 | .channels = 1, | |
1505 | .buswidth = 4, | |
1506 | .num_links = 1, | |
1507 | .links = { SC8280XP_MASTER_GEM_NOC_CFG }, | |
1508 | }; | |
1509 | ||
1510 | static struct qcom_icc_node qns_gem_noc_cnoc = { | |
1511 | .name = "qns_gem_noc_cnoc", | |
1512 | .id = SC8280XP_SLAVE_GEM_NOC_CNOC, | |
1513 | .channels = 1, | |
1514 | .buswidth = 16, | |
1515 | .num_links = 1, | |
1516 | .links = { SC8280XP_MASTER_GEM_NOC_CNOC }, | |
1517 | }; | |
1518 | ||
1519 | static struct qcom_icc_node qns_llcc = { | |
1520 | .name = "qns_llcc", | |
1521 | .id = SC8280XP_SLAVE_LLCC, | |
1522 | .channels = 8, | |
1523 | .buswidth = 16, | |
1524 | .num_links = 1, | |
1525 | .links = { SC8280XP_MASTER_LLCC }, | |
1526 | }; | |
1527 | ||
1528 | static struct qcom_icc_node qns_pcie = { | |
1529 | .name = "qns_pcie", | |
1530 | .id = SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC, | |
1531 | .channels = 1, | |
1532 | .buswidth = 16, | |
1533 | .num_links = 1, | |
1534 | .links = { SC8280XP_MASTER_GEM_NOC_PCIE_SNOC }, | |
1535 | }; | |
1536 | ||
1537 | static struct qcom_icc_node srvc_even_gemnoc = { | |
1538 | .name = "srvc_even_gemnoc", | |
1539 | .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_1, | |
1540 | .channels = 1, | |
1541 | .buswidth = 4, | |
1542 | }; | |
1543 | ||
1544 | static struct qcom_icc_node srvc_odd_gemnoc = { | |
1545 | .name = "srvc_odd_gemnoc", | |
1546 | .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_2, | |
1547 | .channels = 1, | |
1548 | .buswidth = 4, | |
1549 | }; | |
1550 | ||
1551 | static struct qcom_icc_node srvc_sys_gemnoc = { | |
1552 | .name = "srvc_sys_gemnoc", | |
1553 | .id = SC8280XP_SLAVE_SERVICE_GEM_NOC, | |
1554 | .channels = 1, | |
1555 | .buswidth = 4, | |
1556 | }; | |
1557 | ||
1558 | static struct qcom_icc_node qhs_lpass_core = { | |
1559 | .name = "qhs_lpass_core", | |
1560 | .id = SC8280XP_SLAVE_LPASS_CORE_CFG, | |
1561 | .channels = 1, | |
1562 | .buswidth = 4, | |
1563 | }; | |
1564 | ||
1565 | static struct qcom_icc_node qhs_lpass_lpi = { | |
1566 | .name = "qhs_lpass_lpi", | |
1567 | .id = SC8280XP_SLAVE_LPASS_LPI_CFG, | |
1568 | .channels = 1, | |
1569 | .buswidth = 4, | |
1570 | }; | |
1571 | ||
1572 | static struct qcom_icc_node qhs_lpass_mpu = { | |
1573 | .name = "qhs_lpass_mpu", | |
1574 | .id = SC8280XP_SLAVE_LPASS_MPU_CFG, | |
1575 | .channels = 1, | |
1576 | .buswidth = 4, | |
1577 | }; | |
1578 | ||
1579 | static struct qcom_icc_node qhs_lpass_top = { | |
1580 | .name = "qhs_lpass_top", | |
1581 | .id = SC8280XP_SLAVE_LPASS_TOP_CFG, | |
1582 | .channels = 1, | |
1583 | .buswidth = 4, | |
1584 | }; | |
1585 | ||
1586 | static struct qcom_icc_node qns_sysnoc = { | |
1587 | .name = "qns_sysnoc", | |
1588 | .id = SC8280XP_SLAVE_LPASS_SNOC, | |
1589 | .channels = 1, | |
1590 | .buswidth = 16, | |
1591 | .num_links = 1, | |
1592 | .links = { SC8280XP_MASTER_LPASS_ANOC }, | |
1593 | }; | |
1594 | ||
1595 | static struct qcom_icc_node srvc_niu_aml_noc = { | |
1596 | .name = "srvc_niu_aml_noc", | |
1597 | .id = SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, | |
1598 | .channels = 1, | |
1599 | .buswidth = 4, | |
1600 | }; | |
1601 | ||
1602 | static struct qcom_icc_node srvc_niu_lpass_agnoc = { | |
1603 | .name = "srvc_niu_lpass_agnoc", | |
1604 | .id = SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC, | |
1605 | .channels = 1, | |
1606 | .buswidth = 4, | |
1607 | }; | |
1608 | ||
1609 | static struct qcom_icc_node ebi = { | |
1610 | .name = "ebi", | |
1611 | .id = SC8280XP_SLAVE_EBI1, | |
1612 | .channels = 8, | |
1613 | .buswidth = 4, | |
1614 | }; | |
1615 | ||
1616 | static struct qcom_icc_node qns_mem_noc_hf = { | |
1617 | .name = "qns_mem_noc_hf", | |
1618 | .id = SC8280XP_SLAVE_MNOC_HF_MEM_NOC, | |
1619 | .channels = 2, | |
1620 | .buswidth = 32, | |
1621 | .num_links = 1, | |
1622 | .links = { SC8280XP_MASTER_MNOC_HF_MEM_NOC }, | |
1623 | }; | |
1624 | ||
1625 | static struct qcom_icc_node qns_mem_noc_sf = { | |
1626 | .name = "qns_mem_noc_sf", | |
1627 | .id = SC8280XP_SLAVE_MNOC_SF_MEM_NOC, | |
1628 | .channels = 2, | |
1629 | .buswidth = 32, | |
1630 | .num_links = 1, | |
1631 | .links = { SC8280XP_MASTER_MNOC_SF_MEM_NOC }, | |
1632 | }; | |
1633 | ||
1634 | static struct qcom_icc_node srvc_mnoc = { | |
1635 | .name = "srvc_mnoc", | |
1636 | .id = SC8280XP_SLAVE_SERVICE_MNOC, | |
1637 | .channels = 1, | |
1638 | .buswidth = 4, | |
1639 | }; | |
1640 | ||
1641 | static struct qcom_icc_node qns_nsp_gemnoc = { | |
1642 | .name = "qns_nsp_gemnoc", | |
1643 | .id = SC8280XP_SLAVE_CDSP_MEM_NOC, | |
1644 | .channels = 2, | |
1645 | .buswidth = 32, | |
1646 | .num_links = 1, | |
1647 | .links = { SC8280XP_MASTER_COMPUTE_NOC }, | |
1648 | }; | |
1649 | ||
1650 | static struct qcom_icc_node qxs_nsp_xfr = { | |
1651 | .name = "qxs_nsp_xfr", | |
1652 | .id = SC8280XP_SLAVE_NSP_XFR, | |
1653 | .channels = 1, | |
1654 | .buswidth = 32, | |
1655 | }; | |
1656 | ||
1657 | static struct qcom_icc_node service_nsp_noc = { | |
1658 | .name = "service_nsp_noc", | |
1659 | .id = SC8280XP_SLAVE_SERVICE_NSP_NOC, | |
1660 | .channels = 1, | |
1661 | .buswidth = 4, | |
1662 | }; | |
1663 | ||
1664 | static struct qcom_icc_node qns_nspb_gemnoc = { | |
1665 | .name = "qns_nspb_gemnoc", | |
1666 | .id = SC8280XP_SLAVE_CDSPB_MEM_NOC, | |
1667 | .channels = 2, | |
1668 | .buswidth = 32, | |
1669 | .num_links = 1, | |
1670 | .links = { SC8280XP_MASTER_COMPUTE_NOC_1 }, | |
1671 | }; | |
1672 | ||
1673 | static struct qcom_icc_node qxs_nspb_xfr = { | |
1674 | .name = "qxs_nspb_xfr", | |
1675 | .id = SC8280XP_SLAVE_NSPB_XFR, | |
1676 | .channels = 1, | |
1677 | .buswidth = 32, | |
1678 | }; | |
1679 | ||
1680 | static struct qcom_icc_node service_nspb_noc = { | |
1681 | .name = "service_nspb_noc", | |
1682 | .id = SC8280XP_SLAVE_SERVICE_NSPB_NOC, | |
1683 | .channels = 1, | |
1684 | .buswidth = 4, | |
1685 | }; | |
1686 | ||
1687 | static struct qcom_icc_node qns_gemnoc_gc = { | |
1688 | .name = "qns_gemnoc_gc", | |
1689 | .id = SC8280XP_SLAVE_SNOC_GEM_NOC_GC, | |
1690 | .channels = 1, | |
1691 | .buswidth = 8, | |
1692 | .num_links = 1, | |
1693 | .links = { SC8280XP_MASTER_SNOC_GC_MEM_NOC }, | |
1694 | }; | |
1695 | ||
1696 | static struct qcom_icc_node qns_gemnoc_sf = { | |
1697 | .name = "qns_gemnoc_sf", | |
1698 | .id = SC8280XP_SLAVE_SNOC_GEM_NOC_SF, | |
1699 | .channels = 1, | |
1700 | .buswidth = 16, | |
1701 | .num_links = 1, | |
1702 | .links = { SC8280XP_MASTER_SNOC_SF_MEM_NOC }, | |
1703 | }; | |
1704 | ||
1705 | static struct qcom_icc_node srvc_snoc = { | |
1706 | .name = "srvc_snoc", | |
1707 | .id = SC8280XP_SLAVE_SERVICE_SNOC, | |
1708 | .channels = 1, | |
1709 | .buswidth = 4, | |
1710 | }; | |
1711 | ||
1712 | static struct qcom_icc_bcm bcm_acv = { | |
1713 | .name = "ACV", | |
1714 | .num_nodes = 1, | |
1715 | .nodes = { &ebi }, | |
1716 | }; | |
1717 | ||
1718 | static struct qcom_icc_bcm bcm_ce0 = { | |
1719 | .name = "CE0", | |
1720 | .num_nodes = 1, | |
1721 | .nodes = { &qxm_crypto }, | |
1722 | }; | |
1723 | ||
1724 | static struct qcom_icc_bcm bcm_cn0 = { | |
1725 | .name = "CN0", | |
1726 | .keepalive = true, | |
1727 | .num_nodes = 9, | |
1728 | .nodes = { &qnm_gemnoc_cnoc, | |
1729 | &qnm_gemnoc_pcie, | |
1730 | &xs_pcie_0, | |
1731 | &xs_pcie_1, | |
1732 | &xs_pcie_2a, | |
1733 | &xs_pcie_2b, | |
1734 | &xs_pcie_3a, | |
1735 | &xs_pcie_3b, | |
1736 | &xs_pcie_4 | |
1737 | }, | |
1738 | }; | |
1739 | ||
1740 | static struct qcom_icc_bcm bcm_cn1 = { | |
1741 | .name = "CN1", | |
1742 | .num_nodes = 67, | |
1743 | .nodes = { &qhs_ahb2phy0, | |
1744 | &qhs_ahb2phy1, | |
1745 | &qhs_ahb2phy2, | |
1746 | &qhs_aoss, | |
1747 | &qhs_apss, | |
1748 | &qhs_camera_cfg, | |
1749 | &qhs_clk_ctl, | |
1750 | &qhs_compute0_cfg, | |
1751 | &qhs_compute1_cfg, | |
1752 | &qhs_cpr_cx, | |
1753 | &qhs_cpr_mmcx, | |
1754 | &qhs_cpr_mx, | |
1755 | &qhs_cpr_nspcx, | |
1756 | &qhs_crypto0_cfg, | |
1757 | &qhs_cx_rdpm, | |
1758 | &qhs_dcc_cfg, | |
1759 | &qhs_display0_cfg, | |
1760 | &qhs_display1_cfg, | |
1761 | &qhs_emac0_cfg, | |
1762 | &qhs_emac1_cfg, | |
1763 | &qhs_gpuss_cfg, | |
1764 | &qhs_hwkm, | |
1765 | &qhs_imem_cfg, | |
1766 | &qhs_ipa, | |
1767 | &qhs_ipc_router, | |
1768 | &qhs_lpass_cfg, | |
1769 | &qhs_mx_rdpm, | |
1770 | &qhs_mxc_rdpm, | |
1771 | &qhs_pcie0_cfg, | |
1772 | &qhs_pcie1_cfg, | |
1773 | &qhs_pcie2a_cfg, | |
1774 | &qhs_pcie2b_cfg, | |
1775 | &qhs_pcie3a_cfg, | |
1776 | &qhs_pcie3b_cfg, | |
1777 | &qhs_pcie4_cfg, | |
1778 | &qhs_pcie_rsc_cfg, | |
1779 | &qhs_pdm, | |
1780 | &qhs_pimem_cfg, | |
1781 | &qhs_pka_wrapper_cfg, | |
1782 | &qhs_pmu_wrapper_cfg, | |
1783 | &qhs_qdss_cfg, | |
1784 | &qhs_sdc2, | |
1785 | &qhs_sdc4, | |
1786 | &qhs_security, | |
1787 | &qhs_smmuv3_cfg, | |
1788 | &qhs_smss_cfg, | |
1789 | &qhs_spss_cfg, | |
1790 | &qhs_tcsr, | |
1791 | &qhs_tlmm, | |
1792 | &qhs_ufs_card_cfg, | |
1793 | &qhs_ufs_mem_cfg, | |
1794 | &qhs_usb3_0, | |
1795 | &qhs_usb3_1, | |
1796 | &qhs_usb3_mp, | |
1797 | &qhs_usb4_host_0, | |
1798 | &qhs_usb4_host_1, | |
1799 | &qhs_venus_cfg, | |
1800 | &qhs_vsense_ctrl_cfg, | |
1801 | &qhs_vsense_ctrl_r_cfg, | |
1802 | &qns_a1_noc_cfg, | |
1803 | &qns_a2_noc_cfg, | |
1804 | &qns_anoc_pcie_bridge_cfg, | |
1805 | &qns_ddrss_cfg, | |
1806 | &qns_mnoc_cfg, | |
1807 | &qns_snoc_cfg, | |
1808 | &qns_snoc_sf_bridge_cfg, | |
1809 | &srvc_cnoc | |
1810 | }, | |
1811 | }; | |
1812 | ||
1813 | static struct qcom_icc_bcm bcm_cn2 = { | |
1814 | .name = "CN2", | |
1815 | .num_nodes = 4, | |
1816 | .nodes = { &qhs_qspi, | |
1817 | &qhs_qup0, | |
1818 | &qhs_qup1, | |
1819 | &qhs_qup2 | |
1820 | }, | |
1821 | }; | |
1822 | ||
1823 | static struct qcom_icc_bcm bcm_cn3 = { | |
1824 | .name = "CN3", | |
1825 | .num_nodes = 3, | |
1826 | .nodes = { &qxs_imem, | |
1827 | &xs_smss, | |
1828 | &xs_sys_tcu_cfg | |
1829 | }, | |
1830 | }; | |
1831 | ||
f29dabda BA |
1832 | static struct qcom_icc_bcm bcm_mc0 = { |
1833 | .name = "MC0", | |
1834 | .keepalive = true, | |
1835 | .num_nodes = 1, | |
1836 | .nodes = { &ebi }, | |
1837 | }; | |
1838 | ||
1839 | static struct qcom_icc_bcm bcm_mm0 = { | |
1840 | .name = "MM0", | |
1841 | .keepalive = true, | |
1842 | .num_nodes = 5, | |
1843 | .nodes = { &qnm_camnoc_hf, | |
1844 | &qnm_mdp0_0, | |
1845 | &qnm_mdp0_1, | |
1846 | &qnm_mdp1_0, | |
1847 | &qns_mem_noc_hf | |
1848 | }, | |
1849 | }; | |
1850 | ||
1851 | static struct qcom_icc_bcm bcm_mm1 = { | |
1852 | .name = "MM1", | |
1853 | .num_nodes = 8, | |
1854 | .nodes = { &qnm_rot_0, | |
1855 | &qnm_rot_1, | |
1856 | &qnm_video0, | |
1857 | &qnm_video1, | |
1858 | &qnm_video_cvp, | |
1859 | &qxm_camnoc_icp, | |
1860 | &qxm_camnoc_sf, | |
1861 | &qns_mem_noc_sf | |
1862 | }, | |
1863 | }; | |
1864 | ||
1865 | static struct qcom_icc_bcm bcm_nsa0 = { | |
1866 | .name = "NSA0", | |
1867 | .num_nodes = 2, | |
1868 | .nodes = { &qns_nsp_gemnoc, | |
1869 | &qxs_nsp_xfr | |
1870 | }, | |
1871 | }; | |
1872 | ||
1873 | static struct qcom_icc_bcm bcm_nsa1 = { | |
1874 | .name = "NSA1", | |
1875 | .num_nodes = 1, | |
1876 | .nodes = { &qxm_nsp }, | |
1877 | }; | |
1878 | ||
1879 | static struct qcom_icc_bcm bcm_nsb0 = { | |
1880 | .name = "NSB0", | |
1881 | .num_nodes = 2, | |
1882 | .nodes = { &qns_nspb_gemnoc, | |
1883 | &qxs_nspb_xfr | |
1884 | }, | |
1885 | }; | |
1886 | ||
1887 | static struct qcom_icc_bcm bcm_nsb1 = { | |
1888 | .name = "NSB1", | |
1889 | .num_nodes = 1, | |
1890 | .nodes = { &qxm_nspb }, | |
1891 | }; | |
1892 | ||
1893 | static struct qcom_icc_bcm bcm_pci0 = { | |
1894 | .name = "PCI0", | |
1895 | .num_nodes = 1, | |
1896 | .nodes = { &qns_pcie_gem_noc }, | |
1897 | }; | |
1898 | ||
1899 | static struct qcom_icc_bcm bcm_qup0 = { | |
1900 | .name = "QUP0", | |
1901 | .vote_scale = 1, | |
1902 | .num_nodes = 1, | |
1903 | .nodes = { &qup0_core_slave }, | |
1904 | }; | |
1905 | ||
1906 | static struct qcom_icc_bcm bcm_qup1 = { | |
1907 | .name = "QUP1", | |
1908 | .vote_scale = 1, | |
1909 | .num_nodes = 1, | |
1910 | .nodes = { &qup1_core_slave }, | |
1911 | }; | |
1912 | ||
1913 | static struct qcom_icc_bcm bcm_qup2 = { | |
1914 | .name = "QUP2", | |
1915 | .vote_scale = 1, | |
1916 | .num_nodes = 1, | |
1917 | .nodes = { &qup2_core_slave }, | |
1918 | }; | |
1919 | ||
1920 | static struct qcom_icc_bcm bcm_sh0 = { | |
1921 | .name = "SH0", | |
1922 | .keepalive = true, | |
1923 | .num_nodes = 1, | |
1924 | .nodes = { &qns_llcc }, | |
1925 | }; | |
1926 | ||
1927 | static struct qcom_icc_bcm bcm_sh2 = { | |
1928 | .name = "SH2", | |
1929 | .num_nodes = 1, | |
1930 | .nodes = { &chm_apps }, | |
1931 | }; | |
1932 | ||
1933 | static struct qcom_icc_bcm bcm_sn0 = { | |
1934 | .name = "SN0", | |
1935 | .keepalive = true, | |
1936 | .num_nodes = 1, | |
1937 | .nodes = { &qns_gemnoc_sf }, | |
1938 | }; | |
1939 | ||
1940 | static struct qcom_icc_bcm bcm_sn1 = { | |
1941 | .name = "SN1", | |
1942 | .num_nodes = 1, | |
1943 | .nodes = { &qns_gemnoc_gc }, | |
1944 | }; | |
1945 | ||
1946 | static struct qcom_icc_bcm bcm_sn2 = { | |
1947 | .name = "SN2", | |
1948 | .num_nodes = 1, | |
1949 | .nodes = { &qxs_pimem }, | |
1950 | }; | |
1951 | ||
1952 | static struct qcom_icc_bcm bcm_sn3 = { | |
1953 | .name = "SN3", | |
1954 | .num_nodes = 2, | |
1955 | .nodes = { &qns_a1noc_snoc, | |
1956 | &qnm_aggre1_noc | |
1957 | }, | |
1958 | }; | |
1959 | ||
1960 | static struct qcom_icc_bcm bcm_sn4 = { | |
1961 | .name = "SN4", | |
1962 | .num_nodes = 2, | |
1963 | .nodes = { &qns_a2noc_snoc, | |
1964 | &qnm_aggre2_noc | |
1965 | }, | |
1966 | }; | |
1967 | ||
1968 | static struct qcom_icc_bcm bcm_sn5 = { | |
1969 | .name = "SN5", | |
1970 | .num_nodes = 2, | |
1971 | .nodes = { &qns_aggre_usb_snoc, | |
1972 | &qnm_aggre_usb_noc | |
1973 | }, | |
1974 | }; | |
1975 | ||
1976 | static struct qcom_icc_bcm bcm_sn9 = { | |
1977 | .name = "SN9", | |
1978 | .num_nodes = 2, | |
1979 | .nodes = { &qns_sysnoc, | |
1980 | &qnm_lpass_noc | |
1981 | }, | |
1982 | }; | |
1983 | ||
1984 | static struct qcom_icc_bcm bcm_sn10 = { | |
1985 | .name = "SN10", | |
1986 | .num_nodes = 1, | |
1987 | .nodes = { &xs_qdss_stm }, | |
1988 | }; | |
1989 | ||
01c3f038 | 1990 | static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { |
f29dabda BA |
1991 | &bcm_sn3, |
1992 | &bcm_sn5, | |
1993 | }; | |
1994 | ||
fcb3cd7e | 1995 | static struct qcom_icc_node * const aggre1_noc_nodes[] = { |
f29dabda BA |
1996 | [MASTER_QSPI_0] = &qhm_qspi, |
1997 | [MASTER_QUP_1] = &qhm_qup1, | |
1998 | [MASTER_QUP_2] = &qhm_qup2, | |
1999 | [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, | |
2000 | [MASTER_IPA] = &qxm_ipa, | |
2001 | [MASTER_EMAC_1] = &xm_emac_1, | |
2002 | [MASTER_SDCC_4] = &xm_sdc4, | |
2003 | [MASTER_UFS_MEM] = &xm_ufs_mem, | |
2004 | [MASTER_USB3_0] = &xm_usb3_0, | |
2005 | [MASTER_USB3_1] = &xm_usb3_1, | |
2006 | [MASTER_USB3_MP] = &xm_usb3_mp, | |
2007 | [MASTER_USB4_0] = &xm_usb4_host0, | |
2008 | [MASTER_USB4_1] = &xm_usb4_host1, | |
2009 | [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, | |
2010 | [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc, | |
2011 | [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, | |
2012 | }; | |
2013 | ||
3d28502d | 2014 | static const struct qcom_icc_desc sc8280xp_aggre1_noc = { |
f29dabda BA |
2015 | .nodes = aggre1_noc_nodes, |
2016 | .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), | |
2017 | .bcms = aggre1_noc_bcms, | |
2018 | .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), | |
2019 | }; | |
2020 | ||
01c3f038 | 2021 | static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { |
f29dabda BA |
2022 | &bcm_ce0, |
2023 | &bcm_pci0, | |
2024 | &bcm_sn4, | |
2025 | }; | |
2026 | ||
fcb3cd7e | 2027 | static struct qcom_icc_node * const aggre2_noc_nodes[] = { |
f29dabda BA |
2028 | [MASTER_QDSS_BAM] = &qhm_qdss_bam, |
2029 | [MASTER_QUP_0] = &qhm_qup0, | |
2030 | [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, | |
2031 | [MASTER_CRYPTO] = &qxm_crypto, | |
2032 | [MASTER_SENSORS_PROC] = &qxm_sensorss_q6, | |
2033 | [MASTER_SP] = &qxm_sp, | |
2034 | [MASTER_EMAC] = &xm_emac_0, | |
2035 | [MASTER_PCIE_0] = &xm_pcie3_0, | |
2036 | [MASTER_PCIE_1] = &xm_pcie3_1, | |
2037 | [MASTER_PCIE_2A] = &xm_pcie3_2a, | |
2038 | [MASTER_PCIE_2B] = &xm_pcie3_2b, | |
2039 | [MASTER_PCIE_3A] = &xm_pcie3_3a, | |
2040 | [MASTER_PCIE_3B] = &xm_pcie3_3b, | |
2041 | [MASTER_PCIE_4] = &xm_pcie3_4, | |
2042 | [MASTER_QDSS_ETR] = &xm_qdss_etr, | |
2043 | [MASTER_SDCC_2] = &xm_sdc2, | |
2044 | [MASTER_UFS_CARD] = &xm_ufs_card, | |
2045 | [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, | |
2046 | [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gem_noc, | |
2047 | [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, | |
2048 | }; | |
2049 | ||
3d28502d | 2050 | static const struct qcom_icc_desc sc8280xp_aggre2_noc = { |
f29dabda BA |
2051 | .nodes = aggre2_noc_nodes, |
2052 | .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), | |
2053 | .bcms = aggre2_noc_bcms, | |
2054 | .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), | |
2055 | }; | |
2056 | ||
01c3f038 | 2057 | static struct qcom_icc_bcm * const clk_virt_bcms[] = { |
f29dabda BA |
2058 | &bcm_qup0, |
2059 | &bcm_qup1, | |
2060 | &bcm_qup2, | |
2061 | }; | |
2062 | ||
fcb3cd7e | 2063 | static struct qcom_icc_node * const clk_virt_nodes[] = { |
f29dabda BA |
2064 | [MASTER_QUP_CORE_0] = &qup0_core_master, |
2065 | [MASTER_QUP_CORE_1] = &qup1_core_master, | |
2066 | [MASTER_QUP_CORE_2] = &qup2_core_master, | |
f29dabda BA |
2067 | [SLAVE_QUP_CORE_0] = &qup0_core_slave, |
2068 | [SLAVE_QUP_CORE_1] = &qup1_core_slave, | |
2069 | [SLAVE_QUP_CORE_2] = &qup2_core_slave, | |
2070 | }; | |
2071 | ||
3d28502d | 2072 | static const struct qcom_icc_desc sc8280xp_clk_virt = { |
f29dabda BA |
2073 | .nodes = clk_virt_nodes, |
2074 | .num_nodes = ARRAY_SIZE(clk_virt_nodes), | |
2075 | .bcms = clk_virt_bcms, | |
2076 | .num_bcms = ARRAY_SIZE(clk_virt_bcms), | |
2077 | }; | |
2078 | ||
01c3f038 | 2079 | static struct qcom_icc_bcm * const config_noc_bcms[] = { |
f29dabda BA |
2080 | &bcm_cn0, |
2081 | &bcm_cn1, | |
2082 | &bcm_cn2, | |
2083 | &bcm_cn3, | |
2084 | &bcm_sn2, | |
2085 | &bcm_sn10, | |
2086 | }; | |
2087 | ||
fcb3cd7e | 2088 | static struct qcom_icc_node * const config_noc_nodes[] = { |
f29dabda BA |
2089 | [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, |
2090 | [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, | |
2091 | [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, | |
2092 | [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, | |
2093 | [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, | |
2094 | [SLAVE_AOSS] = &qhs_aoss, | |
2095 | [SLAVE_APPSS] = &qhs_apss, | |
2096 | [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, | |
2097 | [SLAVE_CLK_CTL] = &qhs_clk_ctl, | |
2098 | [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, | |
2099 | [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg, | |
2100 | [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, | |
2101 | [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, | |
2102 | [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, | |
2103 | [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, | |
2104 | [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, | |
2105 | [SLAVE_CX_RDPM] = &qhs_cx_rdpm, | |
2106 | [SLAVE_DCC_CFG] = &qhs_dcc_cfg, | |
2107 | [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, | |
2108 | [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg, | |
2109 | [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, | |
2110 | [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, | |
2111 | [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, | |
2112 | [SLAVE_HWKM] = &qhs_hwkm, | |
2113 | [SLAVE_IMEM_CFG] = &qhs_imem_cfg, | |
2114 | [SLAVE_IPA_CFG] = &qhs_ipa, | |
2115 | [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, | |
2116 | [SLAVE_LPASS] = &qhs_lpass_cfg, | |
2117 | [SLAVE_MX_RDPM] = &qhs_mx_rdpm, | |
2118 | [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, | |
2119 | [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, | |
2120 | [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, | |
2121 | [SLAVE_PCIE_2A_CFG] = &qhs_pcie2a_cfg, | |
2122 | [SLAVE_PCIE_2B_CFG] = &qhs_pcie2b_cfg, | |
2123 | [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg, | |
2124 | [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg, | |
2125 | [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, | |
2126 | [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, | |
2127 | [SLAVE_PDM] = &qhs_pdm, | |
2128 | [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, | |
2129 | [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, | |
2130 | [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, | |
2131 | [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, | |
2132 | [SLAVE_QSPI_0] = &qhs_qspi, | |
2133 | [SLAVE_QUP_0] = &qhs_qup0, | |
2134 | [SLAVE_QUP_1] = &qhs_qup1, | |
2135 | [SLAVE_QUP_2] = &qhs_qup2, | |
2136 | [SLAVE_SDCC_2] = &qhs_sdc2, | |
2137 | [SLAVE_SDCC_4] = &qhs_sdc4, | |
2138 | [SLAVE_SECURITY] = &qhs_security, | |
2139 | [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, | |
2140 | [SLAVE_SMSS_CFG] = &qhs_smss_cfg, | |
2141 | [SLAVE_SPSS_CFG] = &qhs_spss_cfg, | |
2142 | [SLAVE_TCSR] = &qhs_tcsr, | |
2143 | [SLAVE_TLMM] = &qhs_tlmm, | |
2144 | [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, | |
2145 | [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, | |
2146 | [SLAVE_USB3_0] = &qhs_usb3_0, | |
2147 | [SLAVE_USB3_1] = &qhs_usb3_1, | |
2148 | [SLAVE_USB3_MP] = &qhs_usb3_mp, | |
2149 | [SLAVE_USB4_0] = &qhs_usb4_host_0, | |
2150 | [SLAVE_USB4_1] = &qhs_usb4_host_1, | |
2151 | [SLAVE_VENUS_CFG] = &qhs_venus_cfg, | |
2152 | [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, | |
2153 | [SLAVE_VSENSE_CTRL_R_CFG] = &qhs_vsense_ctrl_r_cfg, | |
2154 | [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, | |
2155 | [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, | |
2156 | [SLAVE_ANOC_PCIE_BRIDGE_CFG] = &qns_anoc_pcie_bridge_cfg, | |
2157 | [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, | |
2158 | [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, | |
2159 | [SLAVE_SNOC_CFG] = &qns_snoc_cfg, | |
2160 | [SLAVE_SNOC_SF_BRIDGE_CFG] = &qns_snoc_sf_bridge_cfg, | |
2161 | [SLAVE_IMEM] = &qxs_imem, | |
2162 | [SLAVE_PIMEM] = &qxs_pimem, | |
2163 | [SLAVE_SERVICE_CNOC] = &srvc_cnoc, | |
2164 | [SLAVE_PCIE_0] = &xs_pcie_0, | |
2165 | [SLAVE_PCIE_1] = &xs_pcie_1, | |
2166 | [SLAVE_PCIE_2A] = &xs_pcie_2a, | |
2167 | [SLAVE_PCIE_2B] = &xs_pcie_2b, | |
2168 | [SLAVE_PCIE_3A] = &xs_pcie_3a, | |
2169 | [SLAVE_PCIE_3B] = &xs_pcie_3b, | |
2170 | [SLAVE_PCIE_4] = &xs_pcie_4, | |
2171 | [SLAVE_QDSS_STM] = &xs_qdss_stm, | |
2172 | [SLAVE_SMSS] = &xs_smss, | |
2173 | [SLAVE_TCU] = &xs_sys_tcu_cfg, | |
2174 | }; | |
2175 | ||
3d28502d | 2176 | static const struct qcom_icc_desc sc8280xp_config_noc = { |
f29dabda BA |
2177 | .nodes = config_noc_nodes, |
2178 | .num_nodes = ARRAY_SIZE(config_noc_nodes), | |
2179 | .bcms = config_noc_bcms, | |
2180 | .num_bcms = ARRAY_SIZE(config_noc_bcms), | |
2181 | }; | |
2182 | ||
01c3f038 | 2183 | static struct qcom_icc_bcm * const dc_noc_bcms[] = { |
f29dabda BA |
2184 | }; |
2185 | ||
fcb3cd7e | 2186 | static struct qcom_icc_node * const dc_noc_nodes[] = { |
f29dabda BA |
2187 | [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, |
2188 | [SLAVE_LLCC_CFG] = &qhs_llcc, | |
2189 | [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, | |
2190 | }; | |
2191 | ||
3d28502d | 2192 | static const struct qcom_icc_desc sc8280xp_dc_noc = { |
f29dabda BA |
2193 | .nodes = dc_noc_nodes, |
2194 | .num_nodes = ARRAY_SIZE(dc_noc_nodes), | |
2195 | .bcms = dc_noc_bcms, | |
2196 | .num_bcms = ARRAY_SIZE(dc_noc_bcms), | |
2197 | }; | |
2198 | ||
01c3f038 | 2199 | static struct qcom_icc_bcm * const gem_noc_bcms[] = { |
f29dabda BA |
2200 | &bcm_sh0, |
2201 | &bcm_sh2, | |
2202 | }; | |
2203 | ||
fcb3cd7e | 2204 | static struct qcom_icc_node * const gem_noc_nodes[] = { |
f29dabda BA |
2205 | [MASTER_GPU_TCU] = &alm_gpu_tcu, |
2206 | [MASTER_PCIE_TCU] = &alm_pcie_tcu, | |
2207 | [MASTER_SYS_TCU] = &alm_sys_tcu, | |
2208 | [MASTER_APPSS_PROC] = &chm_apps, | |
2209 | [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, | |
2210 | [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1, | |
2211 | [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, | |
2212 | [MASTER_GFX3D] = &qnm_gpu, | |
2213 | [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, | |
2214 | [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, | |
2215 | [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, | |
2216 | [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, | |
2217 | [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, | |
2218 | [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, | |
2219 | [SLAVE_LLCC] = &qns_llcc, | |
2220 | [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, | |
2221 | [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, | |
2222 | [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, | |
2223 | [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, | |
2224 | }; | |
2225 | ||
3d28502d | 2226 | static const struct qcom_icc_desc sc8280xp_gem_noc = { |
f29dabda BA |
2227 | .nodes = gem_noc_nodes, |
2228 | .num_nodes = ARRAY_SIZE(gem_noc_nodes), | |
2229 | .bcms = gem_noc_bcms, | |
2230 | .num_bcms = ARRAY_SIZE(gem_noc_bcms), | |
2231 | }; | |
2232 | ||
01c3f038 | 2233 | static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { |
f29dabda BA |
2234 | &bcm_sn9, |
2235 | }; | |
2236 | ||
fcb3cd7e | 2237 | static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { |
f29dabda BA |
2238 | [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, |
2239 | [MASTER_LPASS_PROC] = &qxm_lpass_dsp, | |
2240 | [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, | |
2241 | [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, | |
2242 | [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, | |
2243 | [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, | |
2244 | [SLAVE_LPASS_SNOC] = &qns_sysnoc, | |
2245 | [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, | |
2246 | [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, | |
2247 | }; | |
2248 | ||
3d28502d | 2249 | static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = { |
f29dabda BA |
2250 | .nodes = lpass_ag_noc_nodes, |
2251 | .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), | |
2252 | .bcms = lpass_ag_noc_bcms, | |
2253 | .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), | |
2254 | }; | |
2255 | ||
01c3f038 | 2256 | static struct qcom_icc_bcm * const mc_virt_bcms[] = { |
f29dabda BA |
2257 | &bcm_acv, |
2258 | &bcm_mc0, | |
2259 | }; | |
2260 | ||
fcb3cd7e | 2261 | static struct qcom_icc_node * const mc_virt_nodes[] = { |
f29dabda BA |
2262 | [MASTER_LLCC] = &llcc_mc, |
2263 | [SLAVE_EBI1] = &ebi, | |
2264 | }; | |
2265 | ||
3d28502d | 2266 | static const struct qcom_icc_desc sc8280xp_mc_virt = { |
f29dabda BA |
2267 | .nodes = mc_virt_nodes, |
2268 | .num_nodes = ARRAY_SIZE(mc_virt_nodes), | |
2269 | .bcms = mc_virt_bcms, | |
2270 | .num_bcms = ARRAY_SIZE(mc_virt_bcms), | |
2271 | }; | |
2272 | ||
01c3f038 | 2273 | static struct qcom_icc_bcm * const mmss_noc_bcms[] = { |
f29dabda BA |
2274 | &bcm_mm0, |
2275 | &bcm_mm1, | |
2276 | }; | |
2277 | ||
fcb3cd7e | 2278 | static struct qcom_icc_node * const mmss_noc_nodes[] = { |
f29dabda BA |
2279 | [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, |
2280 | [MASTER_MDP0] = &qnm_mdp0_0, | |
2281 | [MASTER_MDP1] = &qnm_mdp0_1, | |
2282 | [MASTER_MDP_CORE1_0] = &qnm_mdp1_0, | |
2283 | [MASTER_MDP_CORE1_1] = &qnm_mdp1_1, | |
2284 | [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, | |
2285 | [MASTER_ROTATOR] = &qnm_rot_0, | |
2286 | [MASTER_ROTATOR_1] = &qnm_rot_1, | |
2287 | [MASTER_VIDEO_P0] = &qnm_video0, | |
2288 | [MASTER_VIDEO_P1] = &qnm_video1, | |
2289 | [MASTER_VIDEO_PROC] = &qnm_video_cvp, | |
2290 | [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, | |
2291 | [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, | |
2292 | [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, | |
2293 | [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, | |
2294 | [SLAVE_SERVICE_MNOC] = &srvc_mnoc, | |
2295 | }; | |
2296 | ||
3d28502d | 2297 | static const struct qcom_icc_desc sc8280xp_mmss_noc = { |
f29dabda BA |
2298 | .nodes = mmss_noc_nodes, |
2299 | .num_nodes = ARRAY_SIZE(mmss_noc_nodes), | |
2300 | .bcms = mmss_noc_bcms, | |
2301 | .num_bcms = ARRAY_SIZE(mmss_noc_bcms), | |
2302 | }; | |
2303 | ||
01c3f038 | 2304 | static struct qcom_icc_bcm * const nspa_noc_bcms[] = { |
f29dabda BA |
2305 | &bcm_nsa0, |
2306 | &bcm_nsa1, | |
2307 | }; | |
2308 | ||
fcb3cd7e | 2309 | static struct qcom_icc_node * const nspa_noc_nodes[] = { |
f29dabda BA |
2310 | [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, |
2311 | [MASTER_CDSP_PROC] = &qxm_nsp, | |
2312 | [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, | |
2313 | [SLAVE_NSP_XFR] = &qxs_nsp_xfr, | |
2314 | [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, | |
2315 | }; | |
2316 | ||
3d28502d | 2317 | static const struct qcom_icc_desc sc8280xp_nspa_noc = { |
f29dabda BA |
2318 | .nodes = nspa_noc_nodes, |
2319 | .num_nodes = ARRAY_SIZE(nspa_noc_nodes), | |
2320 | .bcms = nspa_noc_bcms, | |
2321 | .num_bcms = ARRAY_SIZE(nspa_noc_bcms), | |
2322 | }; | |
2323 | ||
01c3f038 | 2324 | static struct qcom_icc_bcm * const nspb_noc_bcms[] = { |
f29dabda BA |
2325 | &bcm_nsb0, |
2326 | &bcm_nsb1, | |
2327 | }; | |
2328 | ||
fcb3cd7e | 2329 | static struct qcom_icc_node * const nspb_noc_nodes[] = { |
f29dabda BA |
2330 | [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, |
2331 | [MASTER_CDSP_PROC_B] = &qxm_nspb, | |
2332 | [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc, | |
2333 | [SLAVE_NSPB_XFR] = &qxs_nspb_xfr, | |
2334 | [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc, | |
2335 | }; | |
2336 | ||
3d28502d | 2337 | static const struct qcom_icc_desc sc8280xp_nspb_noc = { |
f29dabda BA |
2338 | .nodes = nspb_noc_nodes, |
2339 | .num_nodes = ARRAY_SIZE(nspb_noc_nodes), | |
2340 | .bcms = nspb_noc_bcms, | |
2341 | .num_bcms = ARRAY_SIZE(nspb_noc_bcms), | |
2342 | }; | |
2343 | ||
01c3f038 | 2344 | static struct qcom_icc_bcm * const system_noc_main_bcms[] = { |
f29dabda BA |
2345 | &bcm_sn0, |
2346 | &bcm_sn1, | |
2347 | &bcm_sn3, | |
2348 | &bcm_sn4, | |
2349 | &bcm_sn5, | |
2350 | &bcm_sn9, | |
2351 | }; | |
2352 | ||
fcb3cd7e | 2353 | static struct qcom_icc_node * const system_noc_main_nodes[] = { |
f29dabda BA |
2354 | [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, |
2355 | [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, | |
2356 | [MASTER_USB_NOC_SNOC] = &qnm_aggre_usb_noc, | |
2357 | [MASTER_LPASS_ANOC] = &qnm_lpass_noc, | |
2358 | [MASTER_SNOC_CFG] = &qnm_snoc_cfg, | |
2359 | [MASTER_PIMEM] = &qxm_pimem, | |
2360 | [MASTER_GIC] = &xm_gic, | |
2361 | [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, | |
2362 | [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, | |
2363 | [SLAVE_SERVICE_SNOC] = &srvc_snoc, | |
2364 | }; | |
2365 | ||
3d28502d | 2366 | static const struct qcom_icc_desc sc8280xp_system_noc_main = { |
f29dabda BA |
2367 | .nodes = system_noc_main_nodes, |
2368 | .num_nodes = ARRAY_SIZE(system_noc_main_nodes), | |
2369 | .bcms = system_noc_main_bcms, | |
2370 | .num_bcms = ARRAY_SIZE(system_noc_main_bcms), | |
2371 | }; | |
2372 | ||
2373 | static const struct of_device_id qnoc_of_match[] = { | |
2374 | { .compatible = "qcom,sc8280xp-aggre1-noc", .data = &sc8280xp_aggre1_noc, }, | |
2375 | { .compatible = "qcom,sc8280xp-aggre2-noc", .data = &sc8280xp_aggre2_noc, }, | |
2376 | { .compatible = "qcom,sc8280xp-clk-virt", .data = &sc8280xp_clk_virt, }, | |
2377 | { .compatible = "qcom,sc8280xp-config-noc", .data = &sc8280xp_config_noc, }, | |
2378 | { .compatible = "qcom,sc8280xp-dc-noc", .data = &sc8280xp_dc_noc, }, | |
2379 | { .compatible = "qcom,sc8280xp-gem-noc", .data = &sc8280xp_gem_noc, }, | |
2380 | { .compatible = "qcom,sc8280xp-lpass-ag-noc", .data = &sc8280xp_lpass_ag_noc, }, | |
2381 | { .compatible = "qcom,sc8280xp-mc-virt", .data = &sc8280xp_mc_virt, }, | |
2382 | { .compatible = "qcom,sc8280xp-mmss-noc", .data = &sc8280xp_mmss_noc, }, | |
2383 | { .compatible = "qcom,sc8280xp-nspa-noc", .data = &sc8280xp_nspa_noc, }, | |
2384 | { .compatible = "qcom,sc8280xp-nspb-noc", .data = &sc8280xp_nspb_noc, }, | |
2385 | { .compatible = "qcom,sc8280xp-system-noc", .data = &sc8280xp_system_noc_main, }, | |
2386 | { } | |
2387 | }; | |
2388 | MODULE_DEVICE_TABLE(of, qnoc_of_match); | |
2389 | ||
2390 | static struct platform_driver qnoc_driver = { | |
2391 | .probe = qcom_icc_rpmh_probe, | |
2392 | .remove = qcom_icc_rpmh_remove, | |
2393 | .driver = { | |
2394 | .name = "qnoc-sc8280xp", | |
2395 | .of_match_table = qnoc_of_match, | |
2396 | .sync_state = icc_sync_state, | |
2397 | }, | |
2398 | }; | |
2399 | ||
2400 | static int __init qnoc_driver_init(void) | |
2401 | { | |
2402 | return platform_driver_register(&qnoc_driver); | |
2403 | } | |
2404 | core_initcall(qnoc_driver_init); | |
2405 | ||
2406 | static void __exit qnoc_driver_exit(void) | |
2407 | { | |
2408 | platform_driver_unregister(&qnoc_driver); | |
2409 | } | |
2410 | module_exit(qnoc_driver_exit); | |
2411 | ||
2412 | MODULE_DESCRIPTION("Qualcomm SC8280XP NoC driver"); | |
2413 | MODULE_LICENSE("GPL"); |