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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) 2019 Brian Masney <masneyb@onstation.org> | |
4 | * | |
5 | * Based on MSM bus code from downstream MSM kernel sources. | |
6 | * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. | |
7 | * | |
8 | * Based on qcs404.c | |
9 | * Copyright (C) 2019 Linaro Ltd | |
10 | * | |
11 | * Here's a rough representation that shows the various buses that form the | |
12 | * Network On Chip (NOC) for the msm8974: | |
13 | * | |
14 | * Multimedia Subsystem (MMSS) | |
15 | * |----------+-----------------------------------+-----------| | |
16 | * | | | |
17 | * | | | |
18 | * Config | Bus Interface | Memory Controller | |
19 | * |------------+-+-----------| |------------+-+-----------| | |
20 | * | | | |
21 | * | | | |
22 | * | System | | |
23 | * |--------------+-+---------------------------------+-+-------------| | |
24 | * | | | |
25 | * | | | |
26 | * Peripheral | On Chip | Memory (OCMEM) | |
27 | * |------------+-------------| |------------+-------------| | |
28 | */ | |
29 | ||
30 | #include <dt-bindings/interconnect/qcom,msm8974.h> | |
31 | #include <linux/clk.h> | |
32 | #include <linux/device.h> | |
33 | #include <linux/interconnect-provider.h> | |
34 | #include <linux/io.h> | |
35 | #include <linux/module.h> | |
cff66ace | 36 | #include <linux/of.h> |
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37 | #include <linux/platform_device.h> |
38 | #include <linux/slab.h> | |
39 | ||
19ced2ae | 40 | #include "icc-rpm.h" |
4e60a956 BM |
41 | |
42 | enum { | |
43 | MSM8974_BIMC_MAS_AMPSS_M0 = 1, | |
44 | MSM8974_BIMC_MAS_AMPSS_M1, | |
45 | MSM8974_BIMC_MAS_MSS_PROC, | |
46 | MSM8974_BIMC_TO_MNOC, | |
47 | MSM8974_BIMC_TO_SNOC, | |
48 | MSM8974_BIMC_SLV_EBI_CH0, | |
49 | MSM8974_BIMC_SLV_AMPSS_L2, | |
50 | MSM8974_CNOC_MAS_RPM_INST, | |
51 | MSM8974_CNOC_MAS_RPM_DATA, | |
52 | MSM8974_CNOC_MAS_RPM_SYS, | |
53 | MSM8974_CNOC_MAS_DEHR, | |
54 | MSM8974_CNOC_MAS_QDSS_DAP, | |
55 | MSM8974_CNOC_MAS_SPDM, | |
56 | MSM8974_CNOC_MAS_TIC, | |
57 | MSM8974_CNOC_SLV_CLK_CTL, | |
58 | MSM8974_CNOC_SLV_CNOC_MSS, | |
59 | MSM8974_CNOC_SLV_SECURITY, | |
60 | MSM8974_CNOC_SLV_TCSR, | |
61 | MSM8974_CNOC_SLV_TLMM, | |
62 | MSM8974_CNOC_SLV_CRYPTO_0_CFG, | |
63 | MSM8974_CNOC_SLV_CRYPTO_1_CFG, | |
64 | MSM8974_CNOC_SLV_IMEM_CFG, | |
65 | MSM8974_CNOC_SLV_MESSAGE_RAM, | |
66 | MSM8974_CNOC_SLV_BIMC_CFG, | |
67 | MSM8974_CNOC_SLV_BOOT_ROM, | |
68 | MSM8974_CNOC_SLV_PMIC_ARB, | |
69 | MSM8974_CNOC_SLV_SPDM_WRAPPER, | |
70 | MSM8974_CNOC_SLV_DEHR_CFG, | |
71 | MSM8974_CNOC_SLV_MPM, | |
72 | MSM8974_CNOC_SLV_QDSS_CFG, | |
73 | MSM8974_CNOC_SLV_RBCPR_CFG, | |
74 | MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, | |
75 | MSM8974_CNOC_TO_SNOC, | |
76 | MSM8974_CNOC_SLV_CNOC_ONOC_CFG, | |
77 | MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, | |
78 | MSM8974_CNOC_SLV_CNOC_MNOC_CFG, | |
79 | MSM8974_CNOC_SLV_PNOC_CFG, | |
80 | MSM8974_CNOC_SLV_SNOC_MPU_CFG, | |
81 | MSM8974_CNOC_SLV_SNOC_CFG, | |
82 | MSM8974_CNOC_SLV_EBI1_DLL_CFG, | |
83 | MSM8974_CNOC_SLV_PHY_APU_CFG, | |
84 | MSM8974_CNOC_SLV_EBI1_PHY_CFG, | |
85 | MSM8974_CNOC_SLV_RPM, | |
86 | MSM8974_CNOC_SLV_SERVICE_CNOC, | |
87 | MSM8974_MNOC_MAS_GRAPHICS_3D, | |
88 | MSM8974_MNOC_MAS_JPEG, | |
89 | MSM8974_MNOC_MAS_MDP_PORT0, | |
90 | MSM8974_MNOC_MAS_VIDEO_P0, | |
91 | MSM8974_MNOC_MAS_VIDEO_P1, | |
92 | MSM8974_MNOC_MAS_VFE, | |
93 | MSM8974_MNOC_TO_CNOC, | |
94 | MSM8974_MNOC_TO_BIMC, | |
95 | MSM8974_MNOC_SLV_CAMERA_CFG, | |
96 | MSM8974_MNOC_SLV_DISPLAY_CFG, | |
97 | MSM8974_MNOC_SLV_OCMEM_CFG, | |
98 | MSM8974_MNOC_SLV_CPR_CFG, | |
99 | MSM8974_MNOC_SLV_CPR_XPU_CFG, | |
100 | MSM8974_MNOC_SLV_MISC_CFG, | |
101 | MSM8974_MNOC_SLV_MISC_XPU_CFG, | |
102 | MSM8974_MNOC_SLV_VENUS_CFG, | |
103 | MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, | |
104 | MSM8974_MNOC_SLV_MMSS_CLK_CFG, | |
105 | MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, | |
106 | MSM8974_MNOC_SLV_MNOC_MPU_CFG, | |
107 | MSM8974_MNOC_SLV_ONOC_MPU_CFG, | |
108 | MSM8974_MNOC_SLV_SERVICE_MNOC, | |
109 | MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, | |
110 | MSM8974_OCMEM_MAS_JPEG_OCMEM, | |
111 | MSM8974_OCMEM_MAS_MDP_OCMEM, | |
112 | MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, | |
113 | MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, | |
114 | MSM8974_OCMEM_MAS_VFE_OCMEM, | |
115 | MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, | |
116 | MSM8974_OCMEM_SLV_SERVICE_ONOC, | |
117 | MSM8974_OCMEM_VNOC_TO_SNOC, | |
118 | MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, | |
119 | MSM8974_OCMEM_VNOC_MAS_GFX3D, | |
120 | MSM8974_OCMEM_SLV_OCMEM, | |
121 | MSM8974_PNOC_MAS_PNOC_CFG, | |
122 | MSM8974_PNOC_MAS_SDCC_1, | |
123 | MSM8974_PNOC_MAS_SDCC_3, | |
124 | MSM8974_PNOC_MAS_SDCC_4, | |
125 | MSM8974_PNOC_MAS_SDCC_2, | |
126 | MSM8974_PNOC_MAS_TSIF, | |
127 | MSM8974_PNOC_MAS_BAM_DMA, | |
128 | MSM8974_PNOC_MAS_BLSP_2, | |
129 | MSM8974_PNOC_MAS_USB_HSIC, | |
130 | MSM8974_PNOC_MAS_BLSP_1, | |
131 | MSM8974_PNOC_MAS_USB_HS, | |
132 | MSM8974_PNOC_TO_SNOC, | |
133 | MSM8974_PNOC_SLV_SDCC_1, | |
134 | MSM8974_PNOC_SLV_SDCC_3, | |
135 | MSM8974_PNOC_SLV_SDCC_2, | |
136 | MSM8974_PNOC_SLV_SDCC_4, | |
137 | MSM8974_PNOC_SLV_TSIF, | |
138 | MSM8974_PNOC_SLV_BAM_DMA, | |
139 | MSM8974_PNOC_SLV_BLSP_2, | |
140 | MSM8974_PNOC_SLV_USB_HSIC, | |
141 | MSM8974_PNOC_SLV_BLSP_1, | |
142 | MSM8974_PNOC_SLV_USB_HS, | |
143 | MSM8974_PNOC_SLV_PDM, | |
144 | MSM8974_PNOC_SLV_PERIPH_APU_CFG, | |
145 | MSM8974_PNOC_SLV_PNOC_MPU_CFG, | |
146 | MSM8974_PNOC_SLV_PRNG, | |
147 | MSM8974_PNOC_SLV_SERVICE_PNOC, | |
148 | MSM8974_SNOC_MAS_LPASS_AHB, | |
149 | MSM8974_SNOC_MAS_QDSS_BAM, | |
150 | MSM8974_SNOC_MAS_SNOC_CFG, | |
151 | MSM8974_SNOC_TO_BIMC, | |
152 | MSM8974_SNOC_TO_CNOC, | |
153 | MSM8974_SNOC_TO_PNOC, | |
154 | MSM8974_SNOC_TO_OCMEM_VNOC, | |
155 | MSM8974_SNOC_MAS_CRYPTO_CORE0, | |
156 | MSM8974_SNOC_MAS_CRYPTO_CORE1, | |
157 | MSM8974_SNOC_MAS_LPASS_PROC, | |
158 | MSM8974_SNOC_MAS_MSS, | |
159 | MSM8974_SNOC_MAS_MSS_NAV, | |
160 | MSM8974_SNOC_MAS_OCMEM_DMA, | |
161 | MSM8974_SNOC_MAS_WCSS, | |
162 | MSM8974_SNOC_MAS_QDSS_ETR, | |
163 | MSM8974_SNOC_MAS_USB3, | |
164 | MSM8974_SNOC_SLV_AMPSS, | |
165 | MSM8974_SNOC_SLV_LPASS, | |
166 | MSM8974_SNOC_SLV_USB3, | |
167 | MSM8974_SNOC_SLV_WCSS, | |
168 | MSM8974_SNOC_SLV_OCIMEM, | |
169 | MSM8974_SNOC_SLV_SNOC_OCMEM, | |
170 | MSM8974_SNOC_SLV_SERVICE_SNOC, | |
171 | MSM8974_SNOC_SLV_QDSS_STM, | |
172 | }; | |
173 | ||
174 | #define RPM_BUS_MASTER_REQ 0x73616d62 | |
175 | #define RPM_BUS_SLAVE_REQ 0x766c7362 | |
176 | ||
177 | #define to_msm8974_icc_provider(_provider) \ | |
178 | container_of(_provider, struct msm8974_icc_provider, provider) | |
179 | ||
180 | static const struct clk_bulk_data msm8974_icc_bus_clocks[] = { | |
181 | { .id = "bus" }, | |
182 | { .id = "bus_a" }, | |
183 | }; | |
184 | ||
185 | /** | |
186 | * struct msm8974_icc_provider - Qualcomm specific interconnect provider | |
187 | * @provider: generic interconnect provider | |
188 | * @bus_clks: the clk_bulk_data table of bus clocks | |
189 | * @num_clks: the total number of clk_bulk_data entries | |
190 | */ | |
191 | struct msm8974_icc_provider { | |
192 | struct icc_provider provider; | |
193 | struct clk_bulk_data *bus_clks; | |
194 | int num_clks; | |
195 | }; | |
196 | ||
197 | #define MSM8974_ICC_MAX_LINKS 3 | |
198 | ||
199 | /** | |
200 | * struct msm8974_icc_node - Qualcomm specific interconnect nodes | |
201 | * @name: the node name used in debugfs | |
202 | * @id: a unique node identifier | |
203 | * @links: an array of nodes where we can go next while traversing | |
204 | * @num_links: the total number of @links | |
205 | * @buswidth: width of the interconnect between a node and the bus (bytes) | |
206 | * @mas_rpm_id: RPM ID for devices that are bus masters | |
207 | * @slv_rpm_id: RPM ID for devices that are bus slaves | |
208 | * @rate: current bus clock rate in Hz | |
209 | */ | |
210 | struct msm8974_icc_node { | |
211 | unsigned char *name; | |
212 | u16 id; | |
213 | u16 links[MSM8974_ICC_MAX_LINKS]; | |
214 | u16 num_links; | |
215 | u16 buswidth; | |
216 | int mas_rpm_id; | |
217 | int slv_rpm_id; | |
218 | u64 rate; | |
219 | }; | |
220 | ||
221 | struct msm8974_icc_desc { | |
2ccf33c0 | 222 | struct msm8974_icc_node * const *nodes; |
4e60a956 BM |
223 | size_t num_nodes; |
224 | }; | |
225 | ||
226 | #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ | |
227 | ...) \ | |
228 | static struct msm8974_icc_node _name = { \ | |
229 | .name = #_name, \ | |
230 | .id = _id, \ | |
231 | .buswidth = _buswidth, \ | |
232 | .mas_rpm_id = _mas_rpm_id, \ | |
233 | .slv_rpm_id = _slv_rpm_id, \ | |
234 | .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ | |
235 | .links = { __VA_ARGS__ }, \ | |
236 | } | |
237 | ||
238 | DEFINE_QNODE(mas_ampss_m0, MSM8974_BIMC_MAS_AMPSS_M0, 8, 0, -1); | |
239 | DEFINE_QNODE(mas_ampss_m1, MSM8974_BIMC_MAS_AMPSS_M1, 8, 0, -1); | |
240 | DEFINE_QNODE(mas_mss_proc, MSM8974_BIMC_MAS_MSS_PROC, 8, 1, -1); | |
241 | DEFINE_QNODE(bimc_to_mnoc, MSM8974_BIMC_TO_MNOC, 8, 2, -1, MSM8974_BIMC_SLV_EBI_CH0); | |
242 | DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, 2, MSM8974_SNOC_TO_BIMC, MSM8974_BIMC_SLV_EBI_CH0, MSM8974_BIMC_MAS_AMPSS_M0); | |
243 | DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0); | |
244 | DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1); | |
245 | ||
2ccf33c0 | 246 | static struct msm8974_icc_node * const msm8974_bimc_nodes[] = { |
4e60a956 BM |
247 | [BIMC_MAS_AMPSS_M0] = &mas_ampss_m0, |
248 | [BIMC_MAS_AMPSS_M1] = &mas_ampss_m1, | |
249 | [BIMC_MAS_MSS_PROC] = &mas_mss_proc, | |
250 | [BIMC_TO_MNOC] = &bimc_to_mnoc, | |
251 | [BIMC_TO_SNOC] = &bimc_to_snoc, | |
252 | [BIMC_SLV_EBI_CH0] = &slv_ebi_ch0, | |
253 | [BIMC_SLV_AMPSS_L2] = &slv_ampss_l2, | |
254 | }; | |
255 | ||
1625aaa3 | 256 | static const struct msm8974_icc_desc msm8974_bimc = { |
4e60a956 BM |
257 | .nodes = msm8974_bimc_nodes, |
258 | .num_nodes = ARRAY_SIZE(msm8974_bimc_nodes), | |
259 | }; | |
260 | ||
261 | DEFINE_QNODE(mas_rpm_inst, MSM8974_CNOC_MAS_RPM_INST, 8, 45, -1); | |
262 | DEFINE_QNODE(mas_rpm_data, MSM8974_CNOC_MAS_RPM_DATA, 8, 46, -1); | |
263 | DEFINE_QNODE(mas_rpm_sys, MSM8974_CNOC_MAS_RPM_SYS, 8, 47, -1); | |
264 | DEFINE_QNODE(mas_dehr, MSM8974_CNOC_MAS_DEHR, 8, 48, -1); | |
265 | DEFINE_QNODE(mas_qdss_dap, MSM8974_CNOC_MAS_QDSS_DAP, 8, 49, -1); | |
266 | DEFINE_QNODE(mas_spdm, MSM8974_CNOC_MAS_SPDM, 8, 50, -1); | |
267 | DEFINE_QNODE(mas_tic, MSM8974_CNOC_MAS_TIC, 8, 51, -1); | |
268 | DEFINE_QNODE(slv_clk_ctl, MSM8974_CNOC_SLV_CLK_CTL, 8, -1, 47); | |
269 | DEFINE_QNODE(slv_cnoc_mss, MSM8974_CNOC_SLV_CNOC_MSS, 8, -1, 48); | |
270 | DEFINE_QNODE(slv_security, MSM8974_CNOC_SLV_SECURITY, 8, -1, 49); | |
271 | DEFINE_QNODE(slv_tcsr, MSM8974_CNOC_SLV_TCSR, 8, -1, 50); | |
272 | DEFINE_QNODE(slv_tlmm, MSM8974_CNOC_SLV_TLMM, 8, -1, 51); | |
273 | DEFINE_QNODE(slv_crypto_0_cfg, MSM8974_CNOC_SLV_CRYPTO_0_CFG, 8, -1, 52); | |
274 | DEFINE_QNODE(slv_crypto_1_cfg, MSM8974_CNOC_SLV_CRYPTO_1_CFG, 8, -1, 53); | |
275 | DEFINE_QNODE(slv_imem_cfg, MSM8974_CNOC_SLV_IMEM_CFG, 8, -1, 54); | |
276 | DEFINE_QNODE(slv_message_ram, MSM8974_CNOC_SLV_MESSAGE_RAM, 8, -1, 55); | |
277 | DEFINE_QNODE(slv_bimc_cfg, MSM8974_CNOC_SLV_BIMC_CFG, 8, -1, 56); | |
278 | DEFINE_QNODE(slv_boot_rom, MSM8974_CNOC_SLV_BOOT_ROM, 8, -1, 57); | |
279 | DEFINE_QNODE(slv_pmic_arb, MSM8974_CNOC_SLV_PMIC_ARB, 8, -1, 59); | |
280 | DEFINE_QNODE(slv_spdm_wrapper, MSM8974_CNOC_SLV_SPDM_WRAPPER, 8, -1, 60); | |
281 | DEFINE_QNODE(slv_dehr_cfg, MSM8974_CNOC_SLV_DEHR_CFG, 8, -1, 61); | |
282 | DEFINE_QNODE(slv_mpm, MSM8974_CNOC_SLV_MPM, 8, -1, 62); | |
283 | DEFINE_QNODE(slv_qdss_cfg, MSM8974_CNOC_SLV_QDSS_CFG, 8, -1, 63); | |
284 | DEFINE_QNODE(slv_rbcpr_cfg, MSM8974_CNOC_SLV_RBCPR_CFG, 8, -1, 64); | |
285 | DEFINE_QNODE(slv_rbcpr_qdss_apu_cfg, MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, 8, -1, 65); | |
286 | DEFINE_QNODE(cnoc_to_snoc, MSM8974_CNOC_TO_SNOC, 8, 52, 75); | |
287 | DEFINE_QNODE(slv_cnoc_onoc_cfg, MSM8974_CNOC_SLV_CNOC_ONOC_CFG, 8, -1, 68); | |
288 | DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, 8, -1, 58); | |
289 | DEFINE_QNODE(slv_cnoc_mnoc_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_CFG, 8, -1, 66); | |
290 | DEFINE_QNODE(slv_pnoc_cfg, MSM8974_CNOC_SLV_PNOC_CFG, 8, -1, 69); | |
291 | DEFINE_QNODE(slv_snoc_mpu_cfg, MSM8974_CNOC_SLV_SNOC_MPU_CFG, 8, -1, 67); | |
292 | DEFINE_QNODE(slv_snoc_cfg, MSM8974_CNOC_SLV_SNOC_CFG, 8, -1, 70); | |
293 | DEFINE_QNODE(slv_ebi1_dll_cfg, MSM8974_CNOC_SLV_EBI1_DLL_CFG, 8, -1, 71); | |
294 | DEFINE_QNODE(slv_phy_apu_cfg, MSM8974_CNOC_SLV_PHY_APU_CFG, 8, -1, 72); | |
295 | DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PHY_CFG, 8, -1, 73); | |
296 | DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74); | |
297 | DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76); | |
298 | ||
2ccf33c0 | 299 | static struct msm8974_icc_node * const msm8974_cnoc_nodes[] = { |
4e60a956 BM |
300 | [CNOC_MAS_RPM_INST] = &mas_rpm_inst, |
301 | [CNOC_MAS_RPM_DATA] = &mas_rpm_data, | |
302 | [CNOC_MAS_RPM_SYS] = &mas_rpm_sys, | |
303 | [CNOC_MAS_DEHR] = &mas_dehr, | |
304 | [CNOC_MAS_QDSS_DAP] = &mas_qdss_dap, | |
305 | [CNOC_MAS_SPDM] = &mas_spdm, | |
306 | [CNOC_MAS_TIC] = &mas_tic, | |
307 | [CNOC_SLV_CLK_CTL] = &slv_clk_ctl, | |
308 | [CNOC_SLV_CNOC_MSS] = &slv_cnoc_mss, | |
309 | [CNOC_SLV_SECURITY] = &slv_security, | |
310 | [CNOC_SLV_TCSR] = &slv_tcsr, | |
311 | [CNOC_SLV_TLMM] = &slv_tlmm, | |
312 | [CNOC_SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg, | |
313 | [CNOC_SLV_CRYPTO_1_CFG] = &slv_crypto_1_cfg, | |
314 | [CNOC_SLV_IMEM_CFG] = &slv_imem_cfg, | |
315 | [CNOC_SLV_MESSAGE_RAM] = &slv_message_ram, | |
316 | [CNOC_SLV_BIMC_CFG] = &slv_bimc_cfg, | |
317 | [CNOC_SLV_BOOT_ROM] = &slv_boot_rom, | |
318 | [CNOC_SLV_PMIC_ARB] = &slv_pmic_arb, | |
319 | [CNOC_SLV_SPDM_WRAPPER] = &slv_spdm_wrapper, | |
320 | [CNOC_SLV_DEHR_CFG] = &slv_dehr_cfg, | |
321 | [CNOC_SLV_MPM] = &slv_mpm, | |
322 | [CNOC_SLV_QDSS_CFG] = &slv_qdss_cfg, | |
323 | [CNOC_SLV_RBCPR_CFG] = &slv_rbcpr_cfg, | |
324 | [CNOC_SLV_RBCPR_QDSS_APU_CFG] = &slv_rbcpr_qdss_apu_cfg, | |
325 | [CNOC_TO_SNOC] = &cnoc_to_snoc, | |
326 | [CNOC_SLV_CNOC_ONOC_CFG] = &slv_cnoc_onoc_cfg, | |
327 | [CNOC_SLV_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg, | |
328 | [CNOC_SLV_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, | |
329 | [CNOC_SLV_PNOC_CFG] = &slv_pnoc_cfg, | |
330 | [CNOC_SLV_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg, | |
331 | [CNOC_SLV_SNOC_CFG] = &slv_snoc_cfg, | |
332 | [CNOC_SLV_EBI1_DLL_CFG] = &slv_ebi1_dll_cfg, | |
333 | [CNOC_SLV_PHY_APU_CFG] = &slv_phy_apu_cfg, | |
334 | [CNOC_SLV_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg, | |
335 | [CNOC_SLV_RPM] = &slv_rpm, | |
336 | [CNOC_SLV_SERVICE_CNOC] = &slv_service_cnoc, | |
337 | }; | |
338 | ||
1625aaa3 | 339 | static const struct msm8974_icc_desc msm8974_cnoc = { |
4e60a956 BM |
340 | .nodes = msm8974_cnoc_nodes, |
341 | .num_nodes = ARRAY_SIZE(msm8974_cnoc_nodes), | |
342 | }; | |
343 | ||
344 | DEFINE_QNODE(mas_graphics_3d, MSM8974_MNOC_MAS_GRAPHICS_3D, 16, 6, -1, MSM8974_MNOC_TO_BIMC); | |
345 | DEFINE_QNODE(mas_jpeg, MSM8974_MNOC_MAS_JPEG, 16, 7, -1, MSM8974_MNOC_TO_BIMC); | |
346 | DEFINE_QNODE(mas_mdp_port0, MSM8974_MNOC_MAS_MDP_PORT0, 16, 8, -1, MSM8974_MNOC_TO_BIMC); | |
347 | DEFINE_QNODE(mas_video_p0, MSM8974_MNOC_MAS_VIDEO_P0, 16, 9, -1); | |
348 | DEFINE_QNODE(mas_video_p1, MSM8974_MNOC_MAS_VIDEO_P1, 16, 10, -1); | |
349 | DEFINE_QNODE(mas_vfe, MSM8974_MNOC_MAS_VFE, 16, 11, -1, MSM8974_MNOC_TO_BIMC); | |
350 | DEFINE_QNODE(mnoc_to_cnoc, MSM8974_MNOC_TO_CNOC, 16, 4, -1); | |
351 | DEFINE_QNODE(mnoc_to_bimc, MSM8974_MNOC_TO_BIMC, 16, -1, 16, MSM8974_BIMC_TO_MNOC); | |
352 | DEFINE_QNODE(slv_camera_cfg, MSM8974_MNOC_SLV_CAMERA_CFG, 16, -1, 3); | |
353 | DEFINE_QNODE(slv_display_cfg, MSM8974_MNOC_SLV_DISPLAY_CFG, 16, -1, 4); | |
354 | DEFINE_QNODE(slv_ocmem_cfg, MSM8974_MNOC_SLV_OCMEM_CFG, 16, -1, 5); | |
355 | DEFINE_QNODE(slv_cpr_cfg, MSM8974_MNOC_SLV_CPR_CFG, 16, -1, 6); | |
356 | DEFINE_QNODE(slv_cpr_xpu_cfg, MSM8974_MNOC_SLV_CPR_XPU_CFG, 16, -1, 7); | |
357 | DEFINE_QNODE(slv_misc_cfg, MSM8974_MNOC_SLV_MISC_CFG, 16, -1, 8); | |
358 | DEFINE_QNODE(slv_misc_xpu_cfg, MSM8974_MNOC_SLV_MISC_XPU_CFG, 16, -1, 9); | |
359 | DEFINE_QNODE(slv_venus_cfg, MSM8974_MNOC_SLV_VENUS_CFG, 16, -1, 10); | |
360 | DEFINE_QNODE(slv_graphics_3d_cfg, MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, 16, -1, 11); | |
361 | DEFINE_QNODE(slv_mmss_clk_cfg, MSM8974_MNOC_SLV_MMSS_CLK_CFG, 16, -1, 12); | |
362 | DEFINE_QNODE(slv_mmss_clk_xpu_cfg, MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, 16, -1, 13); | |
363 | DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MPU_CFG, 16, -1, 14); | |
364 | DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15); | |
365 | DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17); | |
366 | ||
2ccf33c0 | 367 | static struct msm8974_icc_node * const msm8974_mnoc_nodes[] = { |
4e60a956 BM |
368 | [MNOC_MAS_GRAPHICS_3D] = &mas_graphics_3d, |
369 | [MNOC_MAS_JPEG] = &mas_jpeg, | |
370 | [MNOC_MAS_MDP_PORT0] = &mas_mdp_port0, | |
371 | [MNOC_MAS_VIDEO_P0] = &mas_video_p0, | |
372 | [MNOC_MAS_VIDEO_P1] = &mas_video_p1, | |
373 | [MNOC_MAS_VFE] = &mas_vfe, | |
374 | [MNOC_TO_CNOC] = &mnoc_to_cnoc, | |
375 | [MNOC_TO_BIMC] = &mnoc_to_bimc, | |
376 | [MNOC_SLV_CAMERA_CFG] = &slv_camera_cfg, | |
377 | [MNOC_SLV_DISPLAY_CFG] = &slv_display_cfg, | |
378 | [MNOC_SLV_OCMEM_CFG] = &slv_ocmem_cfg, | |
379 | [MNOC_SLV_CPR_CFG] = &slv_cpr_cfg, | |
380 | [MNOC_SLV_CPR_XPU_CFG] = &slv_cpr_xpu_cfg, | |
381 | [MNOC_SLV_MISC_CFG] = &slv_misc_cfg, | |
382 | [MNOC_SLV_MISC_XPU_CFG] = &slv_misc_xpu_cfg, | |
383 | [MNOC_SLV_VENUS_CFG] = &slv_venus_cfg, | |
384 | [MNOC_SLV_GRAPHICS_3D_CFG] = &slv_graphics_3d_cfg, | |
385 | [MNOC_SLV_MMSS_CLK_CFG] = &slv_mmss_clk_cfg, | |
386 | [MNOC_SLV_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg, | |
387 | [MNOC_SLV_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, | |
388 | [MNOC_SLV_ONOC_MPU_CFG] = &slv_onoc_mpu_cfg, | |
389 | [MNOC_SLV_SERVICE_MNOC] = &slv_service_mnoc, | |
390 | }; | |
391 | ||
1625aaa3 | 392 | static const struct msm8974_icc_desc msm8974_mnoc = { |
4e60a956 BM |
393 | .nodes = msm8974_mnoc_nodes, |
394 | .num_nodes = ARRAY_SIZE(msm8974_mnoc_nodes), | |
395 | }; | |
396 | ||
397 | DEFINE_QNODE(ocmem_noc_to_ocmem_vnoc, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, 16, 54, 78, MSM8974_OCMEM_SLV_OCMEM); | |
398 | DEFINE_QNODE(mas_jpeg_ocmem, MSM8974_OCMEM_MAS_JPEG_OCMEM, 16, 13, -1); | |
399 | DEFINE_QNODE(mas_mdp_ocmem, MSM8974_OCMEM_MAS_MDP_OCMEM, 16, 14, -1); | |
400 | DEFINE_QNODE(mas_video_p0_ocmem, MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, 16, 15, -1); | |
401 | DEFINE_QNODE(mas_video_p1_ocmem, MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, 16, 16, -1); | |
402 | DEFINE_QNODE(mas_vfe_ocmem, MSM8974_OCMEM_MAS_VFE_OCMEM, 16, 17, -1); | |
403 | DEFINE_QNODE(mas_cnoc_onoc_cfg, MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, 16, 12, -1); | |
404 | DEFINE_QNODE(slv_service_onoc, MSM8974_OCMEM_SLV_SERVICE_ONOC, 16, -1, 19); | |
405 | DEFINE_QNODE(slv_ocmem, MSM8974_OCMEM_SLV_OCMEM, 16, -1, 18); | |
406 | ||
407 | /* Virtual NoC is needed for connection to OCMEM */ | |
408 | DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 16, 56, 79, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC); | |
409 | DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80); | |
410 | DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC); | |
411 | ||
2ccf33c0 | 412 | static struct msm8974_icc_node * const msm8974_onoc_nodes[] = { |
4e60a956 BM |
413 | [OCMEM_NOC_TO_OCMEM_VNOC] = &ocmem_noc_to_ocmem_vnoc, |
414 | [OCMEM_MAS_JPEG_OCMEM] = &mas_jpeg_ocmem, | |
415 | [OCMEM_MAS_MDP_OCMEM] = &mas_mdp_ocmem, | |
416 | [OCMEM_MAS_VIDEO_P0_OCMEM] = &mas_video_p0_ocmem, | |
417 | [OCMEM_MAS_VIDEO_P1_OCMEM] = &mas_video_p1_ocmem, | |
418 | [OCMEM_MAS_VFE_OCMEM] = &mas_vfe_ocmem, | |
419 | [OCMEM_MAS_CNOC_ONOC_CFG] = &mas_cnoc_onoc_cfg, | |
420 | [OCMEM_SLV_SERVICE_ONOC] = &slv_service_onoc, | |
421 | [OCMEM_VNOC_TO_SNOC] = &ocmem_vnoc_to_snoc, | |
422 | [OCMEM_VNOC_TO_OCMEM_NOC] = &ocmem_vnoc_to_onoc, | |
423 | [OCMEM_VNOC_MAS_GFX3D] = &mas_v_ocmem_gfx3d, | |
424 | [OCMEM_SLV_OCMEM] = &slv_ocmem, | |
425 | }; | |
426 | ||
1625aaa3 | 427 | static const struct msm8974_icc_desc msm8974_onoc = { |
4e60a956 BM |
428 | .nodes = msm8974_onoc_nodes, |
429 | .num_nodes = ARRAY_SIZE(msm8974_onoc_nodes), | |
430 | }; | |
431 | ||
432 | DEFINE_QNODE(mas_pnoc_cfg, MSM8974_PNOC_MAS_PNOC_CFG, 8, 43, -1); | |
433 | DEFINE_QNODE(mas_sdcc_1, MSM8974_PNOC_MAS_SDCC_1, 8, 33, -1, MSM8974_PNOC_TO_SNOC); | |
434 | DEFINE_QNODE(mas_sdcc_3, MSM8974_PNOC_MAS_SDCC_3, 8, 34, -1, MSM8974_PNOC_TO_SNOC); | |
435 | DEFINE_QNODE(mas_sdcc_4, MSM8974_PNOC_MAS_SDCC_4, 8, 36, -1, MSM8974_PNOC_TO_SNOC); | |
436 | DEFINE_QNODE(mas_sdcc_2, MSM8974_PNOC_MAS_SDCC_2, 8, 35, -1, MSM8974_PNOC_TO_SNOC); | |
437 | DEFINE_QNODE(mas_tsif, MSM8974_PNOC_MAS_TSIF, 8, 37, -1, MSM8974_PNOC_TO_SNOC); | |
438 | DEFINE_QNODE(mas_bam_dma, MSM8974_PNOC_MAS_BAM_DMA, 8, 38, -1); | |
439 | DEFINE_QNODE(mas_blsp_2, MSM8974_PNOC_MAS_BLSP_2, 8, 39, -1, MSM8974_PNOC_TO_SNOC); | |
440 | DEFINE_QNODE(mas_usb_hsic, MSM8974_PNOC_MAS_USB_HSIC, 8, 40, -1, MSM8974_PNOC_TO_SNOC); | |
441 | DEFINE_QNODE(mas_blsp_1, MSM8974_PNOC_MAS_BLSP_1, 8, 41, -1, MSM8974_PNOC_TO_SNOC); | |
442 | DEFINE_QNODE(mas_usb_hs, MSM8974_PNOC_MAS_USB_HS, 8, 42, -1, MSM8974_PNOC_TO_SNOC); | |
443 | DEFINE_QNODE(pnoc_to_snoc, MSM8974_PNOC_TO_SNOC, 8, 44, 45, MSM8974_SNOC_TO_PNOC, MSM8974_PNOC_SLV_PRNG); | |
444 | DEFINE_QNODE(slv_sdcc_1, MSM8974_PNOC_SLV_SDCC_1, 8, -1, 31); | |
445 | DEFINE_QNODE(slv_sdcc_3, MSM8974_PNOC_SLV_SDCC_3, 8, -1, 32); | |
446 | DEFINE_QNODE(slv_sdcc_2, MSM8974_PNOC_SLV_SDCC_2, 8, -1, 33); | |
447 | DEFINE_QNODE(slv_sdcc_4, MSM8974_PNOC_SLV_SDCC_4, 8, -1, 34); | |
448 | DEFINE_QNODE(slv_tsif, MSM8974_PNOC_SLV_TSIF, 8, -1, 35); | |
449 | DEFINE_QNODE(slv_bam_dma, MSM8974_PNOC_SLV_BAM_DMA, 8, -1, 36); | |
450 | DEFINE_QNODE(slv_blsp_2, MSM8974_PNOC_SLV_BLSP_2, 8, -1, 37); | |
451 | DEFINE_QNODE(slv_usb_hsic, MSM8974_PNOC_SLV_USB_HSIC, 8, -1, 38); | |
452 | DEFINE_QNODE(slv_blsp_1, MSM8974_PNOC_SLV_BLSP_1, 8, -1, 39); | |
453 | DEFINE_QNODE(slv_usb_hs, MSM8974_PNOC_SLV_USB_HS, 8, -1, 40); | |
454 | DEFINE_QNODE(slv_pdm, MSM8974_PNOC_SLV_PDM, 8, -1, 41); | |
455 | DEFINE_QNODE(slv_periph_apu_cfg, MSM8974_PNOC_SLV_PERIPH_APU_CFG, 8, -1, 42); | |
456 | DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MPU_CFG, 8, -1, 43); | |
457 | DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_SNOC); | |
458 | DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46); | |
459 | ||
2ccf33c0 | 460 | static struct msm8974_icc_node * const msm8974_pnoc_nodes[] = { |
4e60a956 BM |
461 | [PNOC_MAS_PNOC_CFG] = &mas_pnoc_cfg, |
462 | [PNOC_MAS_SDCC_1] = &mas_sdcc_1, | |
463 | [PNOC_MAS_SDCC_3] = &mas_sdcc_3, | |
464 | [PNOC_MAS_SDCC_4] = &mas_sdcc_4, | |
465 | [PNOC_MAS_SDCC_2] = &mas_sdcc_2, | |
466 | [PNOC_MAS_TSIF] = &mas_tsif, | |
467 | [PNOC_MAS_BAM_DMA] = &mas_bam_dma, | |
468 | [PNOC_MAS_BLSP_2] = &mas_blsp_2, | |
469 | [PNOC_MAS_USB_HSIC] = &mas_usb_hsic, | |
470 | [PNOC_MAS_BLSP_1] = &mas_blsp_1, | |
471 | [PNOC_MAS_USB_HS] = &mas_usb_hs, | |
472 | [PNOC_TO_SNOC] = &pnoc_to_snoc, | |
473 | [PNOC_SLV_SDCC_1] = &slv_sdcc_1, | |
474 | [PNOC_SLV_SDCC_3] = &slv_sdcc_3, | |
475 | [PNOC_SLV_SDCC_2] = &slv_sdcc_2, | |
476 | [PNOC_SLV_SDCC_4] = &slv_sdcc_4, | |
477 | [PNOC_SLV_TSIF] = &slv_tsif, | |
478 | [PNOC_SLV_BAM_DMA] = &slv_bam_dma, | |
479 | [PNOC_SLV_BLSP_2] = &slv_blsp_2, | |
480 | [PNOC_SLV_USB_HSIC] = &slv_usb_hsic, | |
481 | [PNOC_SLV_BLSP_1] = &slv_blsp_1, | |
482 | [PNOC_SLV_USB_HS] = &slv_usb_hs, | |
483 | [PNOC_SLV_PDM] = &slv_pdm, | |
484 | [PNOC_SLV_PERIPH_APU_CFG] = &slv_periph_apu_cfg, | |
485 | [PNOC_SLV_PNOC_MPU_CFG] = &slv_pnoc_mpu_cfg, | |
486 | [PNOC_SLV_PRNG] = &slv_prng, | |
487 | [PNOC_SLV_SERVICE_PNOC] = &slv_service_pnoc, | |
488 | }; | |
489 | ||
1625aaa3 | 490 | static const struct msm8974_icc_desc msm8974_pnoc = { |
4e60a956 BM |
491 | .nodes = msm8974_pnoc_nodes, |
492 | .num_nodes = ARRAY_SIZE(msm8974_pnoc_nodes), | |
493 | }; | |
494 | ||
495 | DEFINE_QNODE(mas_lpass_ahb, MSM8974_SNOC_MAS_LPASS_AHB, 8, 18, -1); | |
496 | DEFINE_QNODE(mas_qdss_bam, MSM8974_SNOC_MAS_QDSS_BAM, 8, 19, -1); | |
497 | DEFINE_QNODE(mas_snoc_cfg, MSM8974_SNOC_MAS_SNOC_CFG, 8, 20, -1); | |
498 | DEFINE_QNODE(snoc_to_bimc, MSM8974_SNOC_TO_BIMC, 8, 21, 24, MSM8974_BIMC_TO_SNOC); | |
499 | DEFINE_QNODE(snoc_to_cnoc, MSM8974_SNOC_TO_CNOC, 8, 22, 25); | |
500 | DEFINE_QNODE(snoc_to_pnoc, MSM8974_SNOC_TO_PNOC, 8, 29, 28, MSM8974_PNOC_TO_SNOC); | |
501 | DEFINE_QNODE(snoc_to_ocmem_vnoc, MSM8974_SNOC_TO_OCMEM_VNOC, 8, 53, 77, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC); | |
502 | DEFINE_QNODE(mas_crypto_core0, MSM8974_SNOC_MAS_CRYPTO_CORE0, 8, 23, -1, MSM8974_SNOC_TO_BIMC); | |
503 | DEFINE_QNODE(mas_crypto_core1, MSM8974_SNOC_MAS_CRYPTO_CORE1, 8, 24, -1); | |
504 | DEFINE_QNODE(mas_lpass_proc, MSM8974_SNOC_MAS_LPASS_PROC, 8, 25, -1, MSM8974_SNOC_TO_OCMEM_VNOC); | |
505 | DEFINE_QNODE(mas_mss, MSM8974_SNOC_MAS_MSS, 8, 26, -1); | |
506 | DEFINE_QNODE(mas_mss_nav, MSM8974_SNOC_MAS_MSS_NAV, 8, 27, -1); | |
507 | DEFINE_QNODE(mas_ocmem_dma, MSM8974_SNOC_MAS_OCMEM_DMA, 8, 28, -1); | |
508 | DEFINE_QNODE(mas_wcss, MSM8974_SNOC_MAS_WCSS, 8, 30, -1); | |
509 | DEFINE_QNODE(mas_qdss_etr, MSM8974_SNOC_MAS_QDSS_ETR, 8, 31, -1); | |
510 | DEFINE_QNODE(mas_usb3, MSM8974_SNOC_MAS_USB3, 8, 32, -1, MSM8974_SNOC_TO_BIMC); | |
511 | DEFINE_QNODE(slv_ampss, MSM8974_SNOC_SLV_AMPSS, 8, -1, 20); | |
512 | DEFINE_QNODE(slv_lpass, MSM8974_SNOC_SLV_LPASS, 8, -1, 21); | |
513 | DEFINE_QNODE(slv_usb3, MSM8974_SNOC_SLV_USB3, 8, -1, 22); | |
514 | DEFINE_QNODE(slv_wcss, MSM8974_SNOC_SLV_WCSS, 8, -1, 23); | |
515 | DEFINE_QNODE(slv_ocimem, MSM8974_SNOC_SLV_OCIMEM, 8, -1, 26); | |
516 | DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCMEM, 8, -1, 27); | |
517 | DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29); | |
518 | DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30); | |
519 | ||
2ccf33c0 | 520 | static struct msm8974_icc_node * const msm8974_snoc_nodes[] = { |
4e60a956 BM |
521 | [SNOC_MAS_LPASS_AHB] = &mas_lpass_ahb, |
522 | [SNOC_MAS_QDSS_BAM] = &mas_qdss_bam, | |
523 | [SNOC_MAS_SNOC_CFG] = &mas_snoc_cfg, | |
524 | [SNOC_TO_BIMC] = &snoc_to_bimc, | |
525 | [SNOC_TO_CNOC] = &snoc_to_cnoc, | |
526 | [SNOC_TO_PNOC] = &snoc_to_pnoc, | |
527 | [SNOC_TO_OCMEM_VNOC] = &snoc_to_ocmem_vnoc, | |
528 | [SNOC_MAS_CRYPTO_CORE0] = &mas_crypto_core0, | |
529 | [SNOC_MAS_CRYPTO_CORE1] = &mas_crypto_core1, | |
530 | [SNOC_MAS_LPASS_PROC] = &mas_lpass_proc, | |
531 | [SNOC_MAS_MSS] = &mas_mss, | |
532 | [SNOC_MAS_MSS_NAV] = &mas_mss_nav, | |
533 | [SNOC_MAS_OCMEM_DMA] = &mas_ocmem_dma, | |
534 | [SNOC_MAS_WCSS] = &mas_wcss, | |
535 | [SNOC_MAS_QDSS_ETR] = &mas_qdss_etr, | |
536 | [SNOC_MAS_USB3] = &mas_usb3, | |
537 | [SNOC_SLV_AMPSS] = &slv_ampss, | |
538 | [SNOC_SLV_LPASS] = &slv_lpass, | |
539 | [SNOC_SLV_USB3] = &slv_usb3, | |
540 | [SNOC_SLV_WCSS] = &slv_wcss, | |
541 | [SNOC_SLV_OCIMEM] = &slv_ocimem, | |
542 | [SNOC_SLV_SNOC_OCMEM] = &slv_snoc_ocmem, | |
543 | [SNOC_SLV_SERVICE_SNOC] = &slv_service_snoc, | |
544 | [SNOC_SLV_QDSS_STM] = &slv_qdss_stm, | |
545 | }; | |
546 | ||
1625aaa3 | 547 | static const struct msm8974_icc_desc msm8974_snoc = { |
4e60a956 BM |
548 | .nodes = msm8974_snoc_nodes, |
549 | .num_nodes = ARRAY_SIZE(msm8974_snoc_nodes), | |
550 | }; | |
551 | ||
4e60a956 BM |
552 | static void msm8974_icc_rpm_smd_send(struct device *dev, int rsc_type, |
553 | char *name, int id, u64 val) | |
554 | { | |
555 | int ret; | |
556 | ||
557 | if (id == -1) | |
558 | return; | |
559 | ||
560 | /* | |
561 | * Setting the bandwidth requests for some nodes fails and this same | |
562 | * behavior occurs on the downstream MSM 3.4 kernel sources based on | |
563 | * errors like this in that kernel: | |
564 | * | |
565 | * msm_rpm_get_error_from_ack(): RPM NACK Unsupported resource | |
566 | * AXI: msm_bus_rpm_req(): RPM: Ack failed | |
567 | * AXI: msm_bus_rpm_commit_arb(): RPM: Req fail: mas:32, bw:240000000 | |
568 | * | |
569 | * Since there's no publicly available documentation for this hardware, | |
570 | * and the bandwidth for some nodes in the path can be set properly, | |
571 | * let's not return an error. | |
572 | */ | |
573 | ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, rsc_type, id, | |
574 | val); | |
575 | if (ret) | |
576 | dev_dbg(dev, "Cannot set bandwidth for node %s (%d): %d\n", | |
577 | name, id, ret); | |
578 | } | |
579 | ||
580 | static int msm8974_icc_set(struct icc_node *src, struct icc_node *dst) | |
581 | { | |
582 | struct msm8974_icc_node *src_qn, *dst_qn; | |
583 | struct msm8974_icc_provider *qp; | |
584 | u64 sum_bw, max_peak_bw, rate; | |
585 | u32 agg_avg = 0, agg_peak = 0; | |
586 | struct icc_provider *provider; | |
587 | struct icc_node *n; | |
588 | int ret, i; | |
589 | ||
590 | src_qn = src->data; | |
591 | dst_qn = dst->data; | |
592 | provider = src->provider; | |
593 | qp = to_msm8974_icc_provider(provider); | |
594 | ||
595 | list_for_each_entry(n, &provider->nodes, node_list) | |
b92c35e1 GD |
596 | provider->aggregate(n, 0, n->avg_bw, n->peak_bw, |
597 | &agg_avg, &agg_peak); | |
4e60a956 BM |
598 | |
599 | sum_bw = icc_units_to_bps(agg_avg); | |
600 | max_peak_bw = icc_units_to_bps(agg_peak); | |
601 | ||
602 | /* Set bandwidth on source node */ | |
603 | msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ, | |
604 | src_qn->name, src_qn->mas_rpm_id, sum_bw); | |
605 | ||
606 | msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ, | |
607 | src_qn->name, src_qn->slv_rpm_id, sum_bw); | |
608 | ||
609 | /* Set bandwidth on destination node */ | |
610 | msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ, | |
611 | dst_qn->name, dst_qn->mas_rpm_id, sum_bw); | |
612 | ||
613 | msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ, | |
614 | dst_qn->name, dst_qn->slv_rpm_id, sum_bw); | |
615 | ||
616 | rate = max(sum_bw, max_peak_bw); | |
617 | ||
618 | do_div(rate, src_qn->buswidth); | |
619 | ||
7381e27b GD |
620 | rate = min_t(u32, rate, INT_MAX); |
621 | ||
4e60a956 BM |
622 | if (src_qn->rate == rate) |
623 | return 0; | |
624 | ||
625 | for (i = 0; i < qp->num_clks; i++) { | |
626 | ret = clk_set_rate(qp->bus_clks[i].clk, rate); | |
627 | if (ret) { | |
628 | dev_err(provider->dev, "%s clk_set_rate error: %d\n", | |
629 | qp->bus_clks[i].id, ret); | |
630 | ret = 0; | |
631 | } | |
632 | } | |
633 | ||
634 | src_qn->rate = rate; | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
9caf2d95 GD |
639 | static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak) |
640 | { | |
641 | *avg = 0; | |
642 | *peak = 0; | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
4e60a956 BM |
647 | static int msm8974_icc_probe(struct platform_device *pdev) |
648 | { | |
649 | const struct msm8974_icc_desc *desc; | |
2ccf33c0 | 650 | struct msm8974_icc_node * const *qnodes; |
4e60a956 BM |
651 | struct msm8974_icc_provider *qp; |
652 | struct device *dev = &pdev->dev; | |
653 | struct icc_onecell_data *data; | |
654 | struct icc_provider *provider; | |
ad3703ac | 655 | struct icc_node *node; |
4e60a956 BM |
656 | size_t num_nodes, i; |
657 | int ret; | |
658 | ||
659 | /* wait for the RPM proxy */ | |
660 | if (!qcom_icc_rpm_smd_available()) | |
661 | return -EPROBE_DEFER; | |
662 | ||
663 | desc = of_device_get_match_data(dev); | |
664 | if (!desc) | |
665 | return -EINVAL; | |
666 | ||
667 | qnodes = desc->nodes; | |
668 | num_nodes = desc->num_nodes; | |
669 | ||
670 | qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL); | |
671 | if (!qp) | |
672 | return -ENOMEM; | |
673 | ||
674 | data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), | |
675 | GFP_KERNEL); | |
676 | if (!data) | |
677 | return -ENOMEM; | |
678 | ||
679 | qp->bus_clks = devm_kmemdup(dev, msm8974_icc_bus_clocks, | |
680 | sizeof(msm8974_icc_bus_clocks), GFP_KERNEL); | |
681 | if (!qp->bus_clks) | |
682 | return -ENOMEM; | |
683 | ||
684 | qp->num_clks = ARRAY_SIZE(msm8974_icc_bus_clocks); | |
685 | ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); | |
686 | if (ret) | |
687 | return ret; | |
688 | ||
689 | ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks); | |
690 | if (ret) | |
691 | return ret; | |
692 | ||
693 | provider = &qp->provider; | |
4e60a956 BM |
694 | provider->dev = dev; |
695 | provider->set = msm8974_icc_set; | |
b92c35e1 | 696 | provider->aggregate = icc_std_aggregate; |
4e60a956 BM |
697 | provider->xlate = of_icc_xlate_onecell; |
698 | provider->data = data; | |
9caf2d95 | 699 | provider->get_bw = msm8974_get_bw; |
4e60a956 | 700 | |
bfe7bcd2 | 701 | icc_provider_init(provider); |
4e60a956 BM |
702 | |
703 | for (i = 0; i < num_nodes; i++) { | |
704 | size_t j; | |
705 | ||
706 | node = icc_node_create(qnodes[i]->id); | |
707 | if (IS_ERR(node)) { | |
708 | ret = PTR_ERR(node); | |
bfe7bcd2 | 709 | goto err_remove_nodes; |
4e60a956 BM |
710 | } |
711 | ||
712 | node->name = qnodes[i]->name; | |
713 | node->data = qnodes[i]; | |
714 | icc_node_add(node, provider); | |
715 | ||
716 | dev_dbg(dev, "registered node %s\n", node->name); | |
717 | ||
718 | /* populate links */ | |
719 | for (j = 0; j < qnodes[i]->num_links; j++) | |
720 | icc_link_create(node, qnodes[i]->links[j]); | |
721 | ||
722 | data->nodes[i] = node; | |
723 | } | |
724 | data->num_nodes = num_nodes; | |
725 | ||
bfe7bcd2 JH |
726 | ret = icc_provider_register(provider); |
727 | if (ret) | |
728 | goto err_remove_nodes; | |
729 | ||
4e60a956 BM |
730 | platform_set_drvdata(pdev, qp); |
731 | ||
732 | return 0; | |
733 | ||
bfe7bcd2 | 734 | err_remove_nodes: |
ad3703ac | 735 | icc_nodes_remove(provider); |
4e60a956 BM |
736 | clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); |
737 | ||
738 | return ret; | |
739 | } | |
740 | ||
741 | static int msm8974_icc_remove(struct platform_device *pdev) | |
742 | { | |
743 | struct msm8974_icc_provider *qp = platform_get_drvdata(pdev); | |
4e60a956 | 744 | |
bfe7bcd2 | 745 | icc_provider_deregister(&qp->provider); |
ad3703ac | 746 | icc_nodes_remove(&qp->provider); |
4e60a956 | 747 | clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); |
919d4e1a UKK |
748 | |
749 | return 0; | |
4e60a956 BM |
750 | } |
751 | ||
752 | static const struct of_device_id msm8974_noc_of_match[] = { | |
753 | { .compatible = "qcom,msm8974-bimc", .data = &msm8974_bimc}, | |
754 | { .compatible = "qcom,msm8974-cnoc", .data = &msm8974_cnoc}, | |
755 | { .compatible = "qcom,msm8974-mmssnoc", .data = &msm8974_mnoc}, | |
756 | { .compatible = "qcom,msm8974-ocmemnoc", .data = &msm8974_onoc}, | |
757 | { .compatible = "qcom,msm8974-pnoc", .data = &msm8974_pnoc}, | |
758 | { .compatible = "qcom,msm8974-snoc", .data = &msm8974_snoc}, | |
759 | { }, | |
760 | }; | |
761 | MODULE_DEVICE_TABLE(of, msm8974_noc_of_match); | |
762 | ||
763 | static struct platform_driver msm8974_noc_driver = { | |
764 | .probe = msm8974_icc_probe, | |
765 | .remove = msm8974_icc_remove, | |
766 | .driver = { | |
767 | .name = "qnoc-msm8974", | |
768 | .of_match_table = msm8974_noc_of_match, | |
7381e27b | 769 | .sync_state = icc_sync_state, |
4e60a956 BM |
770 | }, |
771 | }; | |
772 | module_platform_driver(msm8974_noc_driver); | |
773 | MODULE_DESCRIPTION("Qualcomm MSM8974 NoC driver"); | |
774 | MODULE_AUTHOR("Brian Masney <masneyb@onstation.org>"); | |
775 | MODULE_LICENSE("GPL v2"); |