Commit | Line | Data |
---|---|---|
62feb14e JN |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (C) 2020 Linaro Ltd | |
4 | */ | |
5 | ||
6 | #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H | |
7 | #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H | |
8 | ||
19ced2ae KD |
9 | #include <linux/soc/qcom/smd-rpm.h> |
10 | ||
6ed0e5e6 | 11 | #include <dt-bindings/interconnect/qcom,rpm-icc.h> |
40cdeed6 KD |
12 | #include <linux/clk.h> |
13 | #include <linux/interconnect-provider.h> | |
14 | #include <linux/platform_device.h> | |
dcbce7b0 | 15 | |
62feb14e JN |
16 | #define RPM_BUS_MASTER_REQ 0x73616d62 |
17 | #define RPM_BUS_SLAVE_REQ 0x766c7362 | |
18 | ||
62feb14e JN |
19 | #define to_qcom_provider(_provider) \ |
20 | container_of(_provider, struct qcom_icc_provider, provider) | |
21 | ||
e9d54c26 SG |
22 | enum qcom_icc_type { |
23 | QCOM_ICC_NOC, | |
24 | QCOM_ICC_BIMC, | |
08c59040 | 25 | QCOM_ICC_QNOC, |
e9d54c26 SG |
26 | }; |
27 | ||
a927eb09 KD |
28 | /** |
29 | * struct rpm_clk_resource - RPM bus clock resource | |
30 | * @resource_type: RPM resource type of the clock resource | |
31 | * @clock_id: index of the clock resource of a specific resource type | |
32 | * @branch: whether the resource represents a branch clock | |
33 | */ | |
34 | struct rpm_clk_resource { | |
35 | u32 resource_type; | |
36 | u32 clock_id; | |
37 | bool branch; | |
38 | }; | |
39 | ||
62feb14e JN |
40 | /** |
41 | * struct qcom_icc_provider - Qualcomm specific interconnect provider | |
42 | * @provider: generic interconnect provider | |
2e2113c8 | 43 | * @num_intf_clks: the total number of intf_clks clk_bulk_data entries |
e9d54c26 | 44 | * @type: the ICC provider type |
2b6c7d64 | 45 | * @regmap: regmap for QoS registers read/write access |
82a4b285 | 46 | * @qos_offset: offset to QoS registers |
dd014803 KD |
47 | * @ab_coeff: a percentage-based coefficient for compensating the AB calculations |
48 | * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations | |
65fac3b3 | 49 | * @bus_clk_rate: bus clock rate in Hz |
11f63efe KD |
50 | * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks |
51 | * @bus_clk: a pointer to a HLOS-owned bus clock | |
2e2113c8 | 52 | * @intf_clks: a clk_bulk_data array of interface clocks |
b979049c | 53 | * @keep_alive: whether to always keep a minimum vote on the bus clocks |
2e2113c8 | 54 | * @is_on: whether the bus is powered on |
62feb14e JN |
55 | */ |
56 | struct qcom_icc_provider { | |
57 | struct icc_provider provider; | |
2e2113c8 | 58 | int num_intf_clks; |
e9d54c26 | 59 | enum qcom_icc_type type; |
2b6c7d64 | 60 | struct regmap *regmap; |
0788f4d5 | 61 | unsigned int qos_offset; |
dd014803 KD |
62 | u16 ab_coeff; |
63 | u16 ib_coeff; | |
11f63efe | 64 | u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; |
a927eb09 | 65 | const struct rpm_clk_resource *bus_clk_desc; |
11f63efe | 66 | struct clk *bus_clk; |
2e2113c8 | 67 | struct clk_bulk_data *intf_clks; |
b979049c | 68 | bool keep_alive; |
2e2113c8 | 69 | bool is_on; |
62feb14e JN |
70 | }; |
71 | ||
2b6c7d64 DB |
72 | /** |
73 | * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters | |
74 | * @areq_prio: node requests priority | |
75 | * @prio_level: priority level for bus communication | |
76 | * @limit_commands: activate/deactivate limiter mode during runtime | |
77 | * @ap_owned: indicates if the node is owned by the AP or by the RPM | |
78 | * @qos_mode: default qos mode for this node | |
79 | * @qos_port: qos port number for finding qos registers of this node | |
08c59040 | 80 | * @urg_fwd_en: enable urgent forwarding |
2b6c7d64 DB |
81 | */ |
82 | struct qcom_icc_qos { | |
83 | u32 areq_prio; | |
84 | u32 prio_level; | |
85 | bool limit_commands; | |
86 | bool ap_owned; | |
87 | int qos_mode; | |
88 | int qos_port; | |
08c59040 | 89 | bool urg_fwd_en; |
2b6c7d64 DB |
90 | }; |
91 | ||
62feb14e JN |
92 | /** |
93 | * struct qcom_icc_node - Qualcomm specific interconnect nodes | |
94 | * @name: the node name used in debugfs | |
95 | * @id: a unique node identifier | |
96 | * @links: an array of nodes where we can go next while traversing | |
97 | * @num_links: the total number of @links | |
02819953 | 98 | * @channels: number of channels at this node (e.g. DDR channels) |
62feb14e | 99 | * @buswidth: width of the interconnect between a node and the bus (bytes) |
919791d8 | 100 | * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks |
dcbce7b0 LY |
101 | * @sum_avg: current sum aggregate value of all avg bw requests |
102 | * @max_peak: current max aggregate value of all peak bw requests | |
62feb14e JN |
103 | * @mas_rpm_id: RPM id for devices that are bus masters |
104 | * @slv_rpm_id: RPM id for devices that are bus slaves | |
2b6c7d64 | 105 | * @qos: NoC QoS setting parameters |
ba3f8266 KD |
106 | * @ab_coeff: a percentage-based coefficient for compensating the AB calculations |
107 | * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations | |
919791d8 | 108 | * @bus_clk_rate: a pointer to an array containing bus clock rates in Hz |
62feb14e JN |
109 | */ |
110 | struct qcom_icc_node { | |
111 | unsigned char *name; | |
112 | u16 id; | |
2b6c7d64 | 113 | const u16 *links; |
62feb14e | 114 | u16 num_links; |
02819953 | 115 | u16 channels; |
62feb14e | 116 | u16 buswidth; |
919791d8 | 117 | const struct rpm_clk_resource *bus_clk_desc; |
6ed0e5e6 KD |
118 | u64 sum_avg[QCOM_SMD_RPM_STATE_NUM]; |
119 | u64 max_peak[QCOM_SMD_RPM_STATE_NUM]; | |
62feb14e JN |
120 | int mas_rpm_id; |
121 | int slv_rpm_id; | |
2b6c7d64 | 122 | struct qcom_icc_qos qos; |
ba3f8266 KD |
123 | u16 ab_coeff; |
124 | u16 ib_coeff; | |
919791d8 | 125 | u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; |
62feb14e JN |
126 | }; |
127 | ||
128 | struct qcom_icc_desc { | |
2ccf33c0 | 129 | struct qcom_icc_node * const *nodes; |
62feb14e | 130 | size_t num_nodes; |
a927eb09 | 131 | const struct rpm_clk_resource *bus_clk_desc; |
2e2113c8 KD |
132 | const char * const *intf_clocks; |
133 | size_t num_intf_clocks; | |
b979049c | 134 | bool keep_alive; |
e9d54c26 | 135 | enum qcom_icc_type type; |
2b6c7d64 | 136 | const struct regmap_config *regmap_cfg; |
0788f4d5 | 137 | unsigned int qos_offset; |
dd014803 KD |
138 | u16 ab_coeff; |
139 | u16 ib_coeff; | |
62feb14e JN |
140 | }; |
141 | ||
1d779317 KD |
142 | /* Valid for all bus types */ |
143 | enum qos_mode { | |
144 | NOC_QOS_MODE_INVALID = 0, | |
145 | NOC_QOS_MODE_FIXED, | |
146 | NOC_QOS_MODE_BYPASS, | |
147 | }; | |
62feb14e | 148 | |
918b8604 KD |
149 | extern const struct rpm_clk_resource aggre1_clk; |
150 | extern const struct rpm_clk_resource aggre2_clk; | |
151 | extern const struct rpm_clk_resource bimc_clk; | |
152 | extern const struct rpm_clk_resource bus_0_clk; | |
153 | extern const struct rpm_clk_resource bus_1_clk; | |
154 | extern const struct rpm_clk_resource bus_2_clk; | |
fa35757a | 155 | extern const struct rpm_clk_resource mem_1_clk; |
918b8604 KD |
156 | extern const struct rpm_clk_resource mmaxi_0_clk; |
157 | extern const struct rpm_clk_resource mmaxi_1_clk; | |
158 | extern const struct rpm_clk_resource qup_clk; | |
159 | ||
160 | extern const struct rpm_clk_resource aggre1_branch_clk; | |
161 | extern const struct rpm_clk_resource aggre2_branch_clk; | |
162 | ||
63e8ab61 | 163 | int qnoc_probe(struct platform_device *pdev); |
62feb14e JN |
164 | int qnoc_remove(struct platform_device *pdev); |
165 | ||
19ced2ae KD |
166 | bool qcom_icc_rpm_smd_available(void); |
167 | int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); | |
a927eb09 | 168 | int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, int ctx, u32 rate); |
19ced2ae | 169 | |
62feb14e | 170 | #endif |