Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
4eb3c30b JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
7e044e05 | 15 | #include <linux/types.h> |
1da177e4 LT |
16 | #include <linux/delay.h> |
17 | #include <linux/module.h> | |
1da177e4 LT |
18 | #include <linux/interrupt.h> |
19 | #include <linux/ioport.h> | |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | #include <linux/serio.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/rcupdate.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
553a05b8 | 25 | #include <linux/i8042.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
1da177e4 LT |
27 | |
28 | #include <asm/io.h> | |
29 | ||
30 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
31 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
32 | MODULE_LICENSE("GPL"); | |
33 | ||
386b3849 | 34 | static bool i8042_nokbd; |
945ef0d4 DT |
35 | module_param_named(nokbd, i8042_nokbd, bool, 0); |
36 | MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); | |
37 | ||
386b3849 | 38 | static bool i8042_noaux; |
1da177e4 LT |
39 | module_param_named(noaux, i8042_noaux, bool, 0); |
40 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
41 | ||
386b3849 | 42 | static bool i8042_nomux; |
1da177e4 | 43 | module_param_named(nomux, i8042_nomux, bool, 0); |
2c860a11 | 44 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); |
1da177e4 | 45 | |
386b3849 | 46 | static bool i8042_unlock; |
1da177e4 LT |
47 | module_param_named(unlock, i8042_unlock, bool, 0); |
48 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
49 | ||
386b3849 | 50 | static bool i8042_reset; |
1da177e4 LT |
51 | module_param_named(reset, i8042_reset, bool, 0); |
52 | MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); | |
53 | ||
386b3849 | 54 | static bool i8042_direct; |
1da177e4 LT |
55 | module_param_named(direct, i8042_direct, bool, 0); |
56 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
57 | ||
386b3849 | 58 | static bool i8042_dumbkbd; |
1da177e4 LT |
59 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); |
60 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
61 | ||
386b3849 | 62 | static bool i8042_noloop; |
1da177e4 LT |
63 | module_param_named(noloop, i8042_noloop, bool, 0); |
64 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
65 | ||
8987fec0 | 66 | #ifdef CONFIG_X86 |
386b3849 | 67 | static bool i8042_dritek; |
8987fec0 CC |
68 | module_param_named(dritek, i8042_dritek, bool, 0); |
69 | MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); | |
70 | #endif | |
71 | ||
1da177e4 | 72 | #ifdef CONFIG_PNP |
386b3849 | 73 | static bool i8042_nopnp; |
1da177e4 LT |
74 | module_param_named(nopnp, i8042_nopnp, bool, 0); |
75 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
76 | #endif | |
77 | ||
78 | #define DEBUG | |
79 | #ifdef DEBUG | |
386b3849 | 80 | static bool i8042_debug; |
1da177e4 LT |
81 | module_param_named(debug, i8042_debug, bool, 0600); |
82 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
83 | #endif | |
84 | ||
1c7827ae DT |
85 | static bool i8042_bypass_aux_irq_test; |
86 | ||
1da177e4 LT |
87 | #include "i8042.h" |
88 | ||
181d683d DT |
89 | /* |
90 | * i8042_lock protects serialization between i8042_command and | |
91 | * the interrupt handler. | |
92 | */ | |
1da177e4 LT |
93 | static DEFINE_SPINLOCK(i8042_lock); |
94 | ||
181d683d DT |
95 | /* |
96 | * Writers to AUX and KBD ports as well as users issuing i8042_command | |
97 | * directly should acquire i8042_mutex (by means of calling | |
98 | * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that | |
99 | * they do not disturb each other (unfortunately in many i8042 | |
100 | * implementations write to one of the ports will immediately abort | |
101 | * command that is being processed by another port). | |
102 | */ | |
103 | static DEFINE_MUTEX(i8042_mutex); | |
104 | ||
1da177e4 LT |
105 | struct i8042_port { |
106 | struct serio *serio; | |
107 | int irq; | |
386b3849 | 108 | bool exists; |
1da177e4 | 109 | signed char mux; |
1da177e4 LT |
110 | }; |
111 | ||
112 | #define I8042_KBD_PORT_NO 0 | |
113 | #define I8042_AUX_PORT_NO 1 | |
114 | #define I8042_MUX_PORT_NO 2 | |
115 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
de9ce703 DT |
116 | |
117 | static struct i8042_port i8042_ports[I8042_NUM_PORTS]; | |
1da177e4 LT |
118 | |
119 | static unsigned char i8042_initial_ctr; | |
120 | static unsigned char i8042_ctr; | |
386b3849 DT |
121 | static bool i8042_mux_present; |
122 | static bool i8042_kbd_irq_registered; | |
123 | static bool i8042_aux_irq_registered; | |
817e6ba3 | 124 | static unsigned char i8042_suppress_kbd_ack; |
1da177e4 LT |
125 | static struct platform_device *i8042_platform_device; |
126 | ||
7d12e780 | 127 | static irqreturn_t i8042_interrupt(int irq, void *dev_id); |
967c9ef9 MG |
128 | static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, |
129 | struct serio *serio); | |
1da177e4 | 130 | |
181d683d DT |
131 | void i8042_lock_chip(void) |
132 | { | |
133 | mutex_lock(&i8042_mutex); | |
134 | } | |
135 | EXPORT_SYMBOL(i8042_lock_chip); | |
136 | ||
137 | void i8042_unlock_chip(void) | |
138 | { | |
139 | mutex_unlock(&i8042_mutex); | |
140 | } | |
141 | EXPORT_SYMBOL(i8042_unlock_chip); | |
142 | ||
967c9ef9 MG |
143 | int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, |
144 | struct serio *serio)) | |
145 | { | |
146 | unsigned long flags; | |
147 | int ret = 0; | |
148 | ||
149 | spin_lock_irqsave(&i8042_lock, flags); | |
150 | ||
151 | if (i8042_platform_filter) { | |
152 | ret = -EBUSY; | |
153 | goto out; | |
154 | } | |
155 | ||
156 | i8042_platform_filter = filter; | |
157 | ||
158 | out: | |
159 | spin_unlock_irqrestore(&i8042_lock, flags); | |
160 | return ret; | |
161 | } | |
162 | EXPORT_SYMBOL(i8042_install_filter); | |
163 | ||
164 | int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, | |
165 | struct serio *port)) | |
166 | { | |
167 | unsigned long flags; | |
168 | int ret = 0; | |
169 | ||
170 | spin_lock_irqsave(&i8042_lock, flags); | |
171 | ||
172 | if (i8042_platform_filter != filter) { | |
173 | ret = -EINVAL; | |
174 | goto out; | |
175 | } | |
176 | ||
177 | i8042_platform_filter = NULL; | |
178 | ||
179 | out: | |
180 | spin_unlock_irqrestore(&i8042_lock, flags); | |
181 | return ret; | |
182 | } | |
183 | EXPORT_SYMBOL(i8042_remove_filter); | |
184 | ||
1da177e4 LT |
185 | /* |
186 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
187 | * be ready for reading values from it / writing values to it. | |
188 | * Called always with i8042_lock held. | |
189 | */ | |
190 | ||
191 | static int i8042_wait_read(void) | |
192 | { | |
193 | int i = 0; | |
de9ce703 | 194 | |
1da177e4 LT |
195 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { |
196 | udelay(50); | |
197 | i++; | |
198 | } | |
199 | return -(i == I8042_CTL_TIMEOUT); | |
200 | } | |
201 | ||
202 | static int i8042_wait_write(void) | |
203 | { | |
204 | int i = 0; | |
de9ce703 | 205 | |
1da177e4 LT |
206 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { |
207 | udelay(50); | |
208 | i++; | |
209 | } | |
210 | return -(i == I8042_CTL_TIMEOUT); | |
211 | } | |
212 | ||
213 | /* | |
214 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
215 | * of the i8042 down the toilet. | |
216 | */ | |
217 | ||
218 | static int i8042_flush(void) | |
219 | { | |
220 | unsigned long flags; | |
221 | unsigned char data, str; | |
222 | int i = 0; | |
223 | ||
224 | spin_lock_irqsave(&i8042_lock, flags); | |
225 | ||
226 | while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { | |
227 | udelay(50); | |
228 | data = i8042_read_data(); | |
229 | i++; | |
4eb3c30b JP |
230 | dbg("%02x <- i8042 (flush, %s)\n", |
231 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
1da177e4 LT |
232 | } |
233 | ||
234 | spin_unlock_irqrestore(&i8042_lock, flags); | |
235 | ||
236 | return i; | |
237 | } | |
238 | ||
239 | /* | |
240 | * i8042_command() executes a command on the i8042. It also sends the input | |
241 | * parameter(s) of the commands to it, and receives the output value(s). The | |
242 | * parameters are to be stored in the param array, and the output is placed | |
243 | * into the same array. The number of the parameters and output values is | |
244 | * encoded in bits 8-11 of the command number. | |
245 | */ | |
246 | ||
de9ce703 | 247 | static int __i8042_command(unsigned char *param, int command) |
1da177e4 | 248 | { |
de9ce703 | 249 | int i, error; |
1da177e4 LT |
250 | |
251 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
252 | return -1; | |
253 | ||
de9ce703 DT |
254 | error = i8042_wait_write(); |
255 | if (error) | |
256 | return error; | |
463a4f76 | 257 | |
4eb3c30b | 258 | dbg("%02x -> i8042 (command)\n", command & 0xff); |
463a4f76 DT |
259 | i8042_write_command(command & 0xff); |
260 | ||
261 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
de9ce703 DT |
262 | error = i8042_wait_write(); |
263 | if (error) | |
264 | return error; | |
4eb3c30b | 265 | dbg("%02x -> i8042 (parameter)\n", param[i]); |
463a4f76 | 266 | i8042_write_data(param[i]); |
1da177e4 LT |
267 | } |
268 | ||
463a4f76 | 269 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
de9ce703 DT |
270 | error = i8042_wait_read(); |
271 | if (error) { | |
4eb3c30b | 272 | dbg(" -- i8042 (timeout)\n"); |
de9ce703 DT |
273 | return error; |
274 | } | |
1da177e4 | 275 | |
463a4f76 DT |
276 | if (command == I8042_CMD_AUX_LOOP && |
277 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | |
4eb3c30b | 278 | dbg(" -- i8042 (auxerr)\n"); |
de9ce703 | 279 | return -1; |
1da177e4 LT |
280 | } |
281 | ||
463a4f76 | 282 | param[i] = i8042_read_data(); |
4eb3c30b | 283 | dbg("%02x <- i8042 (return)\n", param[i]); |
463a4f76 | 284 | } |
1da177e4 | 285 | |
de9ce703 DT |
286 | return 0; |
287 | } | |
1da177e4 | 288 | |
553a05b8 | 289 | int i8042_command(unsigned char *param, int command) |
de9ce703 DT |
290 | { |
291 | unsigned long flags; | |
292 | int retval; | |
293 | ||
294 | spin_lock_irqsave(&i8042_lock, flags); | |
295 | retval = __i8042_command(param, command); | |
463a4f76 | 296 | spin_unlock_irqrestore(&i8042_lock, flags); |
de9ce703 | 297 | |
1da177e4 LT |
298 | return retval; |
299 | } | |
553a05b8 | 300 | EXPORT_SYMBOL(i8042_command); |
1da177e4 LT |
301 | |
302 | /* | |
303 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
304 | */ | |
305 | ||
306 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
307 | { | |
308 | unsigned long flags; | |
309 | int retval = 0; | |
310 | ||
311 | spin_lock_irqsave(&i8042_lock, flags); | |
312 | ||
de9ce703 | 313 | if (!(retval = i8042_wait_write())) { |
4eb3c30b | 314 | dbg("%02x -> i8042 (kbd-data)\n", c); |
1da177e4 LT |
315 | i8042_write_data(c); |
316 | } | |
317 | ||
318 | spin_unlock_irqrestore(&i8042_lock, flags); | |
319 | ||
320 | return retval; | |
321 | } | |
322 | ||
323 | /* | |
324 | * i8042_aux_write() sends a byte out through the aux interface. | |
325 | */ | |
326 | ||
327 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
328 | { | |
329 | struct i8042_port *port = serio->port_data; | |
1da177e4 | 330 | |
f4e3c711 DT |
331 | return i8042_command(&c, port->mux == -1 ? |
332 | I8042_CMD_AUX_SEND : | |
333 | I8042_CMD_MUX_SEND + port->mux); | |
1da177e4 LT |
334 | } |
335 | ||
5ddbc77c DT |
336 | |
337 | /* | |
338 | * i8042_aux_close attempts to clear AUX or KBD port state by disabling | |
339 | * and then re-enabling it. | |
340 | */ | |
341 | ||
342 | static void i8042_port_close(struct serio *serio) | |
343 | { | |
344 | int irq_bit; | |
345 | int disable_bit; | |
346 | const char *port_name; | |
347 | ||
348 | if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { | |
349 | irq_bit = I8042_CTR_AUXINT; | |
350 | disable_bit = I8042_CTR_AUXDIS; | |
351 | port_name = "AUX"; | |
352 | } else { | |
353 | irq_bit = I8042_CTR_KBDINT; | |
354 | disable_bit = I8042_CTR_KBDDIS; | |
355 | port_name = "KBD"; | |
356 | } | |
357 | ||
358 | i8042_ctr &= ~irq_bit; | |
359 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 360 | pr_warn("Can't write CTR while closing %s port\n", port_name); |
5ddbc77c DT |
361 | |
362 | udelay(50); | |
363 | ||
364 | i8042_ctr &= ~disable_bit; | |
365 | i8042_ctr |= irq_bit; | |
366 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 367 | pr_err("Can't reactivate %s port\n", port_name); |
5ddbc77c DT |
368 | |
369 | /* | |
370 | * See if there is any data appeared while we were messing with | |
371 | * port state. | |
372 | */ | |
373 | i8042_interrupt(0, NULL); | |
374 | } | |
375 | ||
1da177e4 LT |
376 | /* |
377 | * i8042_start() is called by serio core when port is about to finish | |
378 | * registering. It will mark port as existing so i8042_interrupt can | |
379 | * start sending data through it. | |
380 | */ | |
381 | static int i8042_start(struct serio *serio) | |
382 | { | |
383 | struct i8042_port *port = serio->port_data; | |
384 | ||
386b3849 | 385 | port->exists = true; |
1da177e4 LT |
386 | mb(); |
387 | return 0; | |
388 | } | |
389 | ||
390 | /* | |
391 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
392 | * will not try to send data to the port that is about to go away. | |
393 | * The function is called by serio core as part of unregister procedure. | |
394 | */ | |
395 | static void i8042_stop(struct serio *serio) | |
396 | { | |
397 | struct i8042_port *port = serio->port_data; | |
398 | ||
386b3849 | 399 | port->exists = false; |
a8399c51 DT |
400 | |
401 | /* | |
402 | * We synchronize with both AUX and KBD IRQs because there is | |
403 | * a (very unlikely) chance that AUX IRQ is raised for KBD port | |
404 | * and vice versa. | |
405 | */ | |
406 | synchronize_irq(I8042_AUX_IRQ); | |
407 | synchronize_irq(I8042_KBD_IRQ); | |
1da177e4 LT |
408 | port->serio = NULL; |
409 | } | |
410 | ||
4e8d340d DT |
411 | /* |
412 | * i8042_filter() filters out unwanted bytes from the input data stream. | |
413 | * It is called from i8042_interrupt and thus is running with interrupts | |
414 | * off and i8042_lock held. | |
415 | */ | |
967c9ef9 MG |
416 | static bool i8042_filter(unsigned char data, unsigned char str, |
417 | struct serio *serio) | |
4e8d340d DT |
418 | { |
419 | if (unlikely(i8042_suppress_kbd_ack)) { | |
420 | if ((~str & I8042_STR_AUXDATA) && | |
421 | (data == 0xfa || data == 0xfe)) { | |
422 | i8042_suppress_kbd_ack--; | |
423 | dbg("Extra keyboard ACK - filtered out\n"); | |
424 | return true; | |
425 | } | |
426 | } | |
427 | ||
967c9ef9 | 428 | if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { |
0747e3bc | 429 | dbg("Filtered out by platform filter\n"); |
967c9ef9 MG |
430 | return true; |
431 | } | |
432 | ||
4e8d340d DT |
433 | return false; |
434 | } | |
435 | ||
1da177e4 LT |
436 | /* |
437 | * i8042_interrupt() is the most important function in this driver - | |
438 | * it handles the interrupts from the i8042, and sends incoming bytes | |
439 | * to the upper layers. | |
440 | */ | |
441 | ||
7d12e780 | 442 | static irqreturn_t i8042_interrupt(int irq, void *dev_id) |
1da177e4 LT |
443 | { |
444 | struct i8042_port *port; | |
967c9ef9 | 445 | struct serio *serio; |
1da177e4 LT |
446 | unsigned long flags; |
447 | unsigned char str, data; | |
448 | unsigned int dfl; | |
449 | unsigned int port_no; | |
4e8d340d | 450 | bool filtered; |
817e6ba3 | 451 | int ret = 1; |
1da177e4 | 452 | |
1da177e4 | 453 | spin_lock_irqsave(&i8042_lock, flags); |
4e8d340d | 454 | |
1da177e4 LT |
455 | str = i8042_read_status(); |
456 | if (unlikely(~str & I8042_STR_OBF)) { | |
457 | spin_unlock_irqrestore(&i8042_lock, flags); | |
4eb3c30b JP |
458 | if (irq) |
459 | dbg("Interrupt %d, without any data\n", irq); | |
1da177e4 LT |
460 | ret = 0; |
461 | goto out; | |
462 | } | |
4e8d340d | 463 | |
1da177e4 | 464 | data = i8042_read_data(); |
1da177e4 LT |
465 | |
466 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
467 | static unsigned long last_transmit; | |
468 | static unsigned char last_str; | |
469 | ||
470 | dfl = 0; | |
471 | if (str & I8042_STR_MUXERR) { | |
4eb3c30b JP |
472 | dbg("MUX error, status is %02x, data is %02x\n", |
473 | str, data); | |
1da177e4 LT |
474 | /* |
475 | * When MUXERR condition is signalled the data register can only contain | |
476 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
a216a4b6 DT |
477 | * it is not always the case. Some KBCs also report 0xfc when there is |
478 | * nothing connected to the port while others sometimes get confused which | |
479 | * port the data came from and signal error leaving the data intact. They | |
480 | * _do not_ revert to legacy mode (actually I've never seen KBC reverting | |
481 | * to legacy mode yet, when we see one we'll add proper handling). | |
482 | * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the | |
483 | * rest assume that the data came from the same serio last byte | |
1da177e4 LT |
484 | * was transmitted (if transmission happened not too long ago). |
485 | */ | |
a216a4b6 DT |
486 | |
487 | switch (data) { | |
488 | default: | |
1da177e4 LT |
489 | if (time_before(jiffies, last_transmit + HZ/10)) { |
490 | str = last_str; | |
491 | break; | |
492 | } | |
493 | /* fall through - report timeout */ | |
a216a4b6 | 494 | case 0xfc: |
1da177e4 LT |
495 | case 0xfd: |
496 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
497 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
498 | } | |
499 | } | |
500 | ||
501 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
502 | last_str = str; | |
503 | last_transmit = jiffies; | |
504 | } else { | |
505 | ||
506 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
507 | ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); | |
508 | ||
509 | port_no = (str & I8042_STR_AUXDATA) ? | |
510 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
511 | } | |
512 | ||
513 | port = &i8042_ports[port_no]; | |
967c9ef9 | 514 | serio = port->exists ? port->serio : NULL; |
1da177e4 | 515 | |
4eb3c30b | 516 | dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n", |
de9ce703 | 517 | data, port_no, irq, |
1da177e4 LT |
518 | dfl & SERIO_PARITY ? ", bad parity" : "", |
519 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
520 | ||
967c9ef9 | 521 | filtered = i8042_filter(data, str, serio); |
4e8d340d DT |
522 | |
523 | spin_unlock_irqrestore(&i8042_lock, flags); | |
817e6ba3 | 524 | |
4e8d340d | 525 | if (likely(port->exists && !filtered)) |
967c9ef9 | 526 | serio_interrupt(serio, data, dfl); |
1da177e4 | 527 | |
0854e52d | 528 | out: |
1da177e4 LT |
529 | return IRQ_RETVAL(ret); |
530 | } | |
531 | ||
de9ce703 | 532 | /* |
5ddbc77c | 533 | * i8042_enable_kbd_port enables keyboard port on chip |
de9ce703 DT |
534 | */ |
535 | ||
536 | static int i8042_enable_kbd_port(void) | |
537 | { | |
538 | i8042_ctr &= ~I8042_CTR_KBDDIS; | |
539 | i8042_ctr |= I8042_CTR_KBDINT; | |
540 | ||
541 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
542 | i8042_ctr &= ~I8042_CTR_KBDINT; |
543 | i8042_ctr |= I8042_CTR_KBDDIS; | |
4eb3c30b | 544 | pr_err("Failed to enable KBD port\n"); |
de9ce703 DT |
545 | return -EIO; |
546 | } | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
551 | /* | |
552 | * i8042_enable_aux_port enables AUX (mouse) port on chip | |
553 | */ | |
554 | ||
555 | static int i8042_enable_aux_port(void) | |
556 | { | |
557 | i8042_ctr &= ~I8042_CTR_AUXDIS; | |
558 | i8042_ctr |= I8042_CTR_AUXINT; | |
559 | ||
560 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
561 | i8042_ctr &= ~I8042_CTR_AUXINT; |
562 | i8042_ctr |= I8042_CTR_AUXDIS; | |
4eb3c30b | 563 | pr_err("Failed to enable AUX port\n"); |
de9ce703 DT |
564 | return -EIO; |
565 | } | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | /* | |
571 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
572 | * the controller has been switched into Multiplexed mode | |
573 | */ | |
574 | ||
575 | static int i8042_enable_mux_ports(void) | |
576 | { | |
577 | unsigned char param; | |
578 | int i; | |
579 | ||
580 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
581 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); | |
582 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
583 | } | |
584 | ||
585 | return i8042_enable_aux_port(); | |
586 | } | |
587 | ||
1da177e4 | 588 | /* |
386b3849 DT |
589 | * i8042_set_mux_mode checks whether the controller has an |
590 | * active multiplexor and puts the chip into Multiplexed (true) | |
591 | * or Legacy (false) mode. | |
1da177e4 LT |
592 | */ |
593 | ||
386b3849 | 594 | static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) |
1da177e4 LT |
595 | { |
596 | ||
386b3849 | 597 | unsigned char param, val; |
1da177e4 LT |
598 | /* |
599 | * Get rid of bytes in the queue. | |
600 | */ | |
601 | ||
602 | i8042_flush(); | |
603 | ||
604 | /* | |
605 | * Internal loopback test - send three bytes, they should come back from the | |
de9ce703 | 606 | * mouse interface, the last should be version. |
1da177e4 LT |
607 | */ |
608 | ||
386b3849 DT |
609 | param = val = 0xf0; |
610 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
611 | return -1; | |
612 | param = val = multiplex ? 0x56 : 0xf6; | |
613 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
1da177e4 | 614 | return -1; |
386b3849 DT |
615 | param = val = multiplex ? 0xa4 : 0xa5; |
616 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) | |
1da177e4 | 617 | return -1; |
386b3849 DT |
618 | |
619 | /* | |
620 | * Workaround for interference with USB Legacy emulation | |
621 | * that causes a v10.12 MUX to be found. | |
622 | */ | |
623 | if (param == 0xac) | |
1da177e4 LT |
624 | return -1; |
625 | ||
626 | if (mux_version) | |
463a4f76 | 627 | *mux_version = param; |
1da177e4 LT |
628 | |
629 | return 0; | |
630 | } | |
631 | ||
1da177e4 | 632 | /* |
de9ce703 DT |
633 | * i8042_check_mux() checks whether the controller supports the PS/2 Active |
634 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
635 | * LCS/Telegraphics. | |
1da177e4 LT |
636 | */ |
637 | ||
f8113416 | 638 | static int __init i8042_check_mux(void) |
1da177e4 | 639 | { |
de9ce703 DT |
640 | unsigned char mux_version; |
641 | ||
386b3849 | 642 | if (i8042_set_mux_mode(true, &mux_version)) |
de9ce703 DT |
643 | return -1; |
644 | ||
4eb3c30b | 645 | pr_info("Detected active multiplexing controller, rev %d.%d\n", |
de9ce703 | 646 | (mux_version >> 4) & 0xf, mux_version & 0xf); |
1da177e4 | 647 | |
de9ce703 DT |
648 | /* |
649 | * Disable all muxed ports by disabling AUX. | |
650 | */ | |
1da177e4 LT |
651 | i8042_ctr |= I8042_CTR_AUXDIS; |
652 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
653 | ||
654 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 655 | pr_err("Failed to disable AUX port, can't use MUX\n"); |
de9ce703 | 656 | return -EIO; |
1da177e4 LT |
657 | } |
658 | ||
386b3849 | 659 | i8042_mux_present = true; |
1da177e4 LT |
660 | |
661 | return 0; | |
662 | } | |
663 | ||
1da177e4 | 664 | /* |
de9ce703 | 665 | * The following is used to test AUX IRQ delivery. |
1da177e4 | 666 | */ |
f8113416 DT |
667 | static struct completion i8042_aux_irq_delivered __initdata; |
668 | static bool i8042_irq_being_tested __initdata; | |
1da177e4 | 669 | |
f8113416 | 670 | static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) |
1da177e4 | 671 | { |
de9ce703 DT |
672 | unsigned long flags; |
673 | unsigned char str, data; | |
e3758b2a | 674 | int ret = 0; |
1da177e4 | 675 | |
de9ce703 DT |
676 | spin_lock_irqsave(&i8042_lock, flags); |
677 | str = i8042_read_status(); | |
678 | if (str & I8042_STR_OBF) { | |
679 | data = i8042_read_data(); | |
4eb3c30b JP |
680 | dbg("%02x <- i8042 (aux_test_irq, %s)\n", |
681 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
de9ce703 DT |
682 | if (i8042_irq_being_tested && |
683 | data == 0xa5 && (str & I8042_STR_AUXDATA)) | |
684 | complete(&i8042_aux_irq_delivered); | |
e3758b2a | 685 | ret = 1; |
de9ce703 DT |
686 | } |
687 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1da177e4 | 688 | |
e3758b2a | 689 | return IRQ_RETVAL(ret); |
1da177e4 LT |
690 | } |
691 | ||
d2ada559 RS |
692 | /* |
693 | * i8042_toggle_aux - enables or disables AUX port on i8042 via command and | |
694 | * verifies success by readinng CTR. Used when testing for presence of AUX | |
695 | * port. | |
696 | */ | |
f8113416 | 697 | static int __init i8042_toggle_aux(bool on) |
d2ada559 RS |
698 | { |
699 | unsigned char param; | |
700 | int i; | |
701 | ||
702 | if (i8042_command(¶m, | |
703 | on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) | |
704 | return -1; | |
705 | ||
706 | /* some chips need some time to set the I8042_CTR_AUXDIS bit */ | |
707 | for (i = 0; i < 100; i++) { | |
708 | udelay(50); | |
709 | ||
710 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) | |
711 | return -1; | |
712 | ||
713 | if (!(param & I8042_CTR_AUXDIS) == on) | |
714 | return 0; | |
715 | } | |
716 | ||
717 | return -1; | |
718 | } | |
1da177e4 LT |
719 | |
720 | /* | |
721 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
722 | * the presence of an AUX interface. | |
723 | */ | |
724 | ||
f8113416 | 725 | static int __init i8042_check_aux(void) |
1da177e4 | 726 | { |
de9ce703 | 727 | int retval = -1; |
386b3849 DT |
728 | bool irq_registered = false; |
729 | bool aux_loop_broken = false; | |
de9ce703 | 730 | unsigned long flags; |
1da177e4 | 731 | unsigned char param; |
1da177e4 LT |
732 | |
733 | /* | |
734 | * Get rid of bytes in the queue. | |
735 | */ | |
736 | ||
737 | i8042_flush(); | |
738 | ||
739 | /* | |
740 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
741 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
742 | * though it has an AUX port. | |
743 | */ | |
744 | ||
745 | param = 0x5a; | |
3ca5de6d DT |
746 | retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); |
747 | if (retval || param != 0x5a) { | |
1da177e4 LT |
748 | |
749 | /* | |
750 | * External connection test - filters out AT-soldered PS/2 i8042's | |
751 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
752 | * 0xfa - no error on some notebooks which ignore the spec | |
753 | * Because it's common for chipsets to return error on perfectly functioning | |
754 | * AUX ports, we test for this only when the LOOP command failed. | |
755 | */ | |
756 | ||
de9ce703 DT |
757 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) || |
758 | (param && param != 0xfa && param != 0xff)) | |
759 | return -1; | |
1e4865f8 | 760 | |
3ca5de6d DT |
761 | /* |
762 | * If AUX_LOOP completed without error but returned unexpected data | |
763 | * mark it as broken | |
764 | */ | |
765 | if (!retval) | |
386b3849 | 766 | aux_loop_broken = true; |
1da177e4 LT |
767 | } |
768 | ||
769 | /* | |
770 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
771 | */ | |
772 | ||
386b3849 | 773 | if (i8042_toggle_aux(false)) { |
4eb3c30b JP |
774 | pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); |
775 | pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); | |
1da177e4 LT |
776 | } |
777 | ||
386b3849 | 778 | if (i8042_toggle_aux(true)) |
1da177e4 LT |
779 | return -1; |
780 | ||
781 | /* | |
de9ce703 DT |
782 | * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and |
783 | * used it for a PCI card or somethig else. | |
1da177e4 LT |
784 | */ |
785 | ||
1c7827ae | 786 | if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { |
de9ce703 DT |
787 | /* |
788 | * Without LOOP command we can't test AUX IRQ delivery. Assume the port | |
789 | * is working and hope we are right. | |
790 | */ | |
791 | retval = 0; | |
792 | goto out; | |
793 | } | |
1da177e4 | 794 | |
de9ce703 DT |
795 | if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, |
796 | "i8042", i8042_platform_device)) | |
797 | goto out; | |
1da177e4 | 798 | |
386b3849 | 799 | irq_registered = true; |
de9ce703 DT |
800 | |
801 | if (i8042_enable_aux_port()) | |
802 | goto out; | |
803 | ||
804 | spin_lock_irqsave(&i8042_lock, flags); | |
1da177e4 | 805 | |
de9ce703 | 806 | init_completion(&i8042_aux_irq_delivered); |
386b3849 | 807 | i8042_irq_being_tested = true; |
de9ce703 DT |
808 | |
809 | param = 0xa5; | |
810 | retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); | |
811 | ||
812 | spin_unlock_irqrestore(&i8042_lock, flags); | |
813 | ||
814 | if (retval) | |
815 | goto out; | |
1da177e4 | 816 | |
de9ce703 DT |
817 | if (wait_for_completion_timeout(&i8042_aux_irq_delivered, |
818 | msecs_to_jiffies(250)) == 0) { | |
1da177e4 | 819 | /* |
de9ce703 DT |
820 | * AUX IRQ was never delivered so we need to flush the controller to |
821 | * get rid of the byte we put there; otherwise keyboard may not work. | |
1da177e4 | 822 | */ |
4eb3c30b | 823 | dbg(" -- i8042 (aux irq test timeout)\n"); |
de9ce703 DT |
824 | i8042_flush(); |
825 | retval = -1; | |
826 | } | |
1da177e4 | 827 | |
de9ce703 | 828 | out: |
1da177e4 | 829 | |
de9ce703 DT |
830 | /* |
831 | * Disable the interface. | |
832 | */ | |
1da177e4 | 833 | |
de9ce703 DT |
834 | i8042_ctr |= I8042_CTR_AUXDIS; |
835 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
1da177e4 | 836 | |
de9ce703 DT |
837 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
838 | retval = -1; | |
1da177e4 | 839 | |
de9ce703 DT |
840 | if (irq_registered) |
841 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1da177e4 | 842 | |
de9ce703 DT |
843 | return retval; |
844 | } | |
1da177e4 | 845 | |
de9ce703 | 846 | static int i8042_controller_check(void) |
1da177e4 | 847 | { |
de9ce703 | 848 | if (i8042_flush() == I8042_BUFFER_SIZE) { |
4eb3c30b | 849 | pr_err("No controller found\n"); |
de9ce703 DT |
850 | return -ENODEV; |
851 | } | |
852 | ||
853 | return 0; | |
1da177e4 LT |
854 | } |
855 | ||
de9ce703 | 856 | static int i8042_controller_selftest(void) |
2673c836 VP |
857 | { |
858 | unsigned char param; | |
5ea2fc64 | 859 | int i = 0; |
2673c836 | 860 | |
5ea2fc64 AV |
861 | /* |
862 | * We try this 5 times; on some really fragile systems this does not | |
863 | * take the first time... | |
864 | */ | |
865 | do { | |
866 | ||
867 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
4eb3c30b | 868 | pr_err("i8042 controller self test timeout\n"); |
5ea2fc64 AV |
869 | return -ENODEV; |
870 | } | |
871 | ||
872 | if (param == I8042_RET_CTL_TEST) | |
873 | return 0; | |
2673c836 | 874 | |
4eb3c30b JP |
875 | pr_err("i8042 controller selftest failed. (%#x != %#x)\n", |
876 | param, I8042_RET_CTL_TEST); | |
5ea2fc64 AV |
877 | msleep(50); |
878 | } while (i++ < 5); | |
2673c836 | 879 | |
5ea2fc64 AV |
880 | #ifdef CONFIG_X86 |
881 | /* | |
882 | * On x86, we don't fail entire i8042 initialization if controller | |
883 | * reset fails in hopes that keyboard port will still be functional | |
884 | * and user will still get a working keyboard. This is especially | |
885 | * important on netbooks. On other arches we trust hardware more. | |
886 | */ | |
4eb3c30b | 887 | pr_info("giving up on controller selftest, continuing anyway...\n"); |
2673c836 | 888 | return 0; |
5ea2fc64 AV |
889 | #else |
890 | return -EIO; | |
891 | #endif | |
2673c836 | 892 | } |
1da177e4 LT |
893 | |
894 | /* | |
895 | * i8042_controller init initializes the i8042 controller, and, | |
896 | * most importantly, sets it into non-xlated mode if that's | |
897 | * desired. | |
898 | */ | |
899 | ||
900 | static int i8042_controller_init(void) | |
901 | { | |
902 | unsigned long flags; | |
ee1e82ce DT |
903 | int n = 0; |
904 | unsigned char ctr[2]; | |
1da177e4 | 905 | |
1da177e4 | 906 | /* |
ee1e82ce | 907 | * Save the CTR for restore on unload / reboot. |
1da177e4 LT |
908 | */ |
909 | ||
ee1e82ce DT |
910 | do { |
911 | if (n >= 10) { | |
4eb3c30b | 912 | pr_err("Unable to get stable CTR read\n"); |
ee1e82ce DT |
913 | return -EIO; |
914 | } | |
915 | ||
916 | if (n != 0) | |
917 | udelay(50); | |
918 | ||
919 | if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { | |
4eb3c30b | 920 | pr_err("Can't read CTR while initializing i8042\n"); |
ee1e82ce DT |
921 | return -EIO; |
922 | } | |
923 | ||
924 | } while (n < 2 || ctr[0] != ctr[1]); | |
1da177e4 | 925 | |
ee1e82ce | 926 | i8042_initial_ctr = i8042_ctr = ctr[0]; |
1da177e4 LT |
927 | |
928 | /* | |
929 | * Disable the keyboard interface and interrupt. | |
930 | */ | |
931 | ||
932 | i8042_ctr |= I8042_CTR_KBDDIS; | |
933 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
934 | ||
935 | /* | |
936 | * Handle keylock. | |
937 | */ | |
938 | ||
939 | spin_lock_irqsave(&i8042_lock, flags); | |
940 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
941 | if (i8042_unlock) | |
942 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
82dd9eff | 943 | else |
4eb3c30b | 944 | pr_warn("Warning: Keylock active\n"); |
1da177e4 LT |
945 | } |
946 | spin_unlock_irqrestore(&i8042_lock, flags); | |
947 | ||
948 | /* | |
949 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
950 | * bother enabling translating and be happy. | |
951 | */ | |
952 | ||
953 | if (~i8042_ctr & I8042_CTR_XLATE) | |
386b3849 | 954 | i8042_direct = true; |
1da177e4 LT |
955 | |
956 | /* | |
957 | * Set nontranslated mode for the kbd interface if requested by an option. | |
958 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
959 | * interface is. We don't do this by default, since it can confuse notebook | |
960 | * BIOSes. | |
961 | */ | |
962 | ||
963 | if (i8042_direct) | |
964 | i8042_ctr &= ~I8042_CTR_XLATE; | |
965 | ||
966 | /* | |
967 | * Write CTR back. | |
968 | */ | |
969 | ||
970 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 971 | pr_err("Can't write CTR while initializing i8042\n"); |
de9ce703 | 972 | return -EIO; |
1da177e4 LT |
973 | } |
974 | ||
ee1e82ce DT |
975 | /* |
976 | * Flush whatever accumulated while we were disabling keyboard port. | |
977 | */ | |
978 | ||
979 | i8042_flush(); | |
980 | ||
1da177e4 LT |
981 | return 0; |
982 | } | |
983 | ||
984 | ||
985 | /* | |
de9ce703 | 986 | * Reset the controller and reset CRT to the original value set by BIOS. |
1da177e4 | 987 | */ |
de9ce703 | 988 | |
1da177e4 LT |
989 | static void i8042_controller_reset(void) |
990 | { | |
de9ce703 | 991 | i8042_flush(); |
1da177e4 | 992 | |
8d04ddb6 DT |
993 | /* |
994 | * Disable both KBD and AUX interfaces so they don't get in the way | |
995 | */ | |
996 | ||
997 | i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; | |
998 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); | |
999 | ||
ee1e82ce | 1000 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
4eb3c30b | 1001 | pr_warn("Can't write CTR while resetting\n"); |
5ddbc77c | 1002 | |
1da177e4 LT |
1003 | /* |
1004 | * Disable MUX mode if present. | |
1005 | */ | |
1006 | ||
1007 | if (i8042_mux_present) | |
386b3849 | 1008 | i8042_set_mux_mode(false, NULL); |
1da177e4 LT |
1009 | |
1010 | /* | |
de9ce703 | 1011 | * Reset the controller if requested. |
1da177e4 LT |
1012 | */ |
1013 | ||
1ca56e51 DT |
1014 | if (i8042_reset) |
1015 | i8042_controller_selftest(); | |
1da177e4 | 1016 | |
de9ce703 DT |
1017 | /* |
1018 | * Restore the original control register setting. | |
1019 | */ | |
1020 | ||
1021 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 1022 | pr_warn("Can't restore CTR\n"); |
1da177e4 LT |
1023 | } |
1024 | ||
1025 | ||
1da177e4 | 1026 | /* |
c7ff0d9c TS |
1027 | * i8042_panic_blink() will turn the keyboard LEDs on or off and is called |
1028 | * when kernel panics. Flashing LEDs is useful for users running X who may | |
1da177e4 LT |
1029 | * not see the console and will help distingushing panics from "real" |
1030 | * lockups. | |
1031 | * | |
1032 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
1033 | * waiting for KBC to free up even if KBD interrupt is off | |
1034 | */ | |
1035 | ||
1036 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
1037 | ||
c7ff0d9c | 1038 | static long i8042_panic_blink(int state) |
1da177e4 LT |
1039 | { |
1040 | long delay = 0; | |
c7ff0d9c | 1041 | char led; |
1da177e4 | 1042 | |
c7ff0d9c | 1043 | led = (state) ? 0x01 | 0x04 : 0; |
1da177e4 LT |
1044 | while (i8042_read_status() & I8042_STR_IBF) |
1045 | DELAY; | |
4eb3c30b | 1046 | dbg("%02x -> i8042 (panic blink)\n", 0xed); |
19f3c3e3 | 1047 | i8042_suppress_kbd_ack = 2; |
1da177e4 LT |
1048 | i8042_write_data(0xed); /* set leds */ |
1049 | DELAY; | |
1050 | while (i8042_read_status() & I8042_STR_IBF) | |
1051 | DELAY; | |
1052 | DELAY; | |
4eb3c30b | 1053 | dbg("%02x -> i8042 (panic blink)\n", led); |
1da177e4 LT |
1054 | i8042_write_data(led); |
1055 | DELAY; | |
1da177e4 LT |
1056 | return delay; |
1057 | } | |
1058 | ||
1059 | #undef DELAY | |
1060 | ||
d35895db BP |
1061 | #ifdef CONFIG_X86 |
1062 | static void i8042_dritek_enable(void) | |
1063 | { | |
594d6363 | 1064 | unsigned char param = 0x90; |
d35895db BP |
1065 | int error; |
1066 | ||
1067 | error = i8042_command(¶m, 0x1059); | |
1068 | if (error) | |
4eb3c30b | 1069 | pr_warn("Failed to enable DRITEK extension: %d\n", error); |
d35895db BP |
1070 | } |
1071 | #endif | |
1072 | ||
82dd9eff | 1073 | #ifdef CONFIG_PM |
7e044e05 | 1074 | |
1da177e4 | 1075 | /* |
ebd7768d DT |
1076 | * Here we try to reset everything back to a state we had |
1077 | * before suspending. | |
1da177e4 LT |
1078 | */ |
1079 | ||
1ca56e51 | 1080 | static int i8042_controller_resume(bool force_reset) |
1da177e4 | 1081 | { |
de9ce703 | 1082 | int error; |
1da177e4 | 1083 | |
de9ce703 DT |
1084 | error = i8042_controller_check(); |
1085 | if (error) | |
1086 | return error; | |
2673c836 | 1087 | |
1ca56e51 DT |
1088 | if (i8042_reset || force_reset) { |
1089 | error = i8042_controller_selftest(); | |
1090 | if (error) | |
1091 | return error; | |
1092 | } | |
1da177e4 LT |
1093 | |
1094 | /* | |
82dd9eff | 1095 | * Restore original CTR value and disable all ports |
1da177e4 LT |
1096 | */ |
1097 | ||
82dd9eff DT |
1098 | i8042_ctr = i8042_initial_ctr; |
1099 | if (i8042_direct) | |
1100 | i8042_ctr &= ~I8042_CTR_XLATE; | |
de9ce703 DT |
1101 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
1102 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | |
1103 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1104 | pr_warn("Can't write CTR to resume, retrying...\n"); |
2f6a77d5 JK |
1105 | msleep(50); |
1106 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1107 | pr_err("CTR write retry failed\n"); |
2f6a77d5 JK |
1108 | return -EIO; |
1109 | } | |
de9ce703 | 1110 | } |
1da177e4 | 1111 | |
d35895db BP |
1112 | |
1113 | #ifdef CONFIG_X86 | |
1114 | if (i8042_dritek) | |
1115 | i8042_dritek_enable(); | |
1116 | #endif | |
1117 | ||
de9ce703 | 1118 | if (i8042_mux_present) { |
386b3849 | 1119 | if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) |
4eb3c30b | 1120 | pr_warn("failed to resume active multiplexor, mouse won't work\n"); |
de9ce703 DT |
1121 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) |
1122 | i8042_enable_aux_port(); | |
1da177e4 | 1123 | |
de9ce703 DT |
1124 | if (i8042_ports[I8042_KBD_PORT_NO].serio) |
1125 | i8042_enable_kbd_port(); | |
1126 | ||
7d12e780 | 1127 | i8042_interrupt(0, NULL); |
1da177e4 LT |
1128 | |
1129 | return 0; | |
1da177e4 | 1130 | } |
ebd7768d | 1131 | |
1ca56e51 DT |
1132 | /* |
1133 | * Here we try to restore the original BIOS settings to avoid | |
1134 | * upsetting it. | |
1135 | */ | |
1136 | ||
1137 | static int i8042_pm_reset(struct device *dev) | |
1138 | { | |
1139 | i8042_controller_reset(); | |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | static int i8042_pm_resume(struct device *dev) | |
1145 | { | |
1146 | /* | |
1147 | * On resume from S2R we always try to reset the controller | |
1148 | * to bring it in a sane state. (In case of S2D we expect | |
1149 | * BIOS to reset the controller for us.) | |
1150 | */ | |
1151 | return i8042_controller_resume(true); | |
1152 | } | |
1153 | ||
c2d1a2a1 AJ |
1154 | static int i8042_pm_thaw(struct device *dev) |
1155 | { | |
1156 | i8042_interrupt(0, NULL); | |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
1ca56e51 DT |
1161 | static int i8042_pm_restore(struct device *dev) |
1162 | { | |
1163 | return i8042_controller_resume(false); | |
1164 | } | |
1165 | ||
ebd7768d DT |
1166 | static const struct dev_pm_ops i8042_pm_ops = { |
1167 | .suspend = i8042_pm_reset, | |
1ca56e51 | 1168 | .resume = i8042_pm_resume, |
c2d1a2a1 | 1169 | .thaw = i8042_pm_thaw, |
ebd7768d DT |
1170 | .poweroff = i8042_pm_reset, |
1171 | .restore = i8042_pm_restore, | |
1172 | }; | |
1173 | ||
82dd9eff | 1174 | #endif /* CONFIG_PM */ |
1da177e4 LT |
1175 | |
1176 | /* | |
1177 | * We need to reset the 8042 back to original mode on system shutdown, | |
1178 | * because otherwise BIOSes will be confused. | |
1179 | */ | |
1180 | ||
3ae5eaec | 1181 | static void i8042_shutdown(struct platform_device *dev) |
1da177e4 | 1182 | { |
82dd9eff | 1183 | i8042_controller_reset(); |
1da177e4 LT |
1184 | } |
1185 | ||
f8113416 | 1186 | static int __init i8042_create_kbd_port(void) |
1da177e4 LT |
1187 | { |
1188 | struct serio *serio; | |
1189 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
1190 | ||
d39969de | 1191 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1192 | if (!serio) |
1193 | return -ENOMEM; | |
1194 | ||
1195 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
1196 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
0854e52d DT |
1197 | serio->start = i8042_start; |
1198 | serio->stop = i8042_stop; | |
5ddbc77c | 1199 | serio->close = i8042_port_close; |
0854e52d DT |
1200 | serio->port_data = port; |
1201 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 | 1202 | strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); |
0854e52d DT |
1203 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); |
1204 | ||
1205 | port->serio = serio; | |
de9ce703 | 1206 | port->irq = I8042_KBD_IRQ; |
0854e52d | 1207 | |
de9ce703 | 1208 | return 0; |
1da177e4 LT |
1209 | } |
1210 | ||
f8113416 | 1211 | static int __init i8042_create_aux_port(int idx) |
1da177e4 LT |
1212 | { |
1213 | struct serio *serio; | |
de9ce703 DT |
1214 | int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; |
1215 | struct i8042_port *port = &i8042_ports[port_no]; | |
1da177e4 | 1216 | |
d39969de | 1217 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1218 | if (!serio) |
1219 | return -ENOMEM; | |
1220 | ||
1221 | serio->id.type = SERIO_8042; | |
1222 | serio->write = i8042_aux_write; | |
0854e52d DT |
1223 | serio->start = i8042_start; |
1224 | serio->stop = i8042_stop; | |
1225 | serio->port_data = port; | |
1226 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 DT |
1227 | if (idx < 0) { |
1228 | strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); | |
1229 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
5ddbc77c | 1230 | serio->close = i8042_port_close; |
de9ce703 DT |
1231 | } else { |
1232 | snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); | |
1233 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); | |
1234 | } | |
0854e52d DT |
1235 | |
1236 | port->serio = serio; | |
de9ce703 DT |
1237 | port->mux = idx; |
1238 | port->irq = I8042_AUX_IRQ; | |
0854e52d | 1239 | |
de9ce703 | 1240 | return 0; |
1da177e4 LT |
1241 | } |
1242 | ||
f8113416 | 1243 | static void __init i8042_free_kbd_port(void) |
1da177e4 | 1244 | { |
de9ce703 DT |
1245 | kfree(i8042_ports[I8042_KBD_PORT_NO].serio); |
1246 | i8042_ports[I8042_KBD_PORT_NO].serio = NULL; | |
1247 | } | |
1da177e4 | 1248 | |
f8113416 | 1249 | static void __init i8042_free_aux_ports(void) |
de9ce703 DT |
1250 | { |
1251 | int i; | |
0854e52d | 1252 | |
de9ce703 DT |
1253 | for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { |
1254 | kfree(i8042_ports[i].serio); | |
1255 | i8042_ports[i].serio = NULL; | |
1256 | } | |
1257 | } | |
0854e52d | 1258 | |
f8113416 | 1259 | static void __init i8042_register_ports(void) |
de9ce703 DT |
1260 | { |
1261 | int i; | |
0854e52d | 1262 | |
de9ce703 DT |
1263 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1264 | if (i8042_ports[i].serio) { | |
1265 | printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", | |
1266 | i8042_ports[i].serio->name, | |
1267 | (unsigned long) I8042_DATA_REG, | |
1268 | (unsigned long) I8042_COMMAND_REG, | |
1269 | i8042_ports[i].irq); | |
1270 | serio_register_port(i8042_ports[i].serio); | |
1271 | } | |
1272 | } | |
1da177e4 LT |
1273 | } |
1274 | ||
7a1904c3 | 1275 | static void __devexit i8042_unregister_ports(void) |
1da177e4 | 1276 | { |
de9ce703 | 1277 | int i; |
1da177e4 | 1278 | |
de9ce703 DT |
1279 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1280 | if (i8042_ports[i].serio) { | |
1281 | serio_unregister_port(i8042_ports[i].serio); | |
1282 | i8042_ports[i].serio = NULL; | |
1283 | } | |
1284 | } | |
1285 | } | |
1286 | ||
181d683d DT |
1287 | /* |
1288 | * Checks whether port belongs to i8042 controller. | |
1289 | */ | |
1290 | bool i8042_check_port_owner(const struct serio *port) | |
1291 | { | |
1292 | int i; | |
1293 | ||
1294 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
1295 | if (i8042_ports[i].serio == port) | |
1296 | return true; | |
1297 | ||
1298 | return false; | |
1299 | } | |
1300 | EXPORT_SYMBOL(i8042_check_port_owner); | |
1301 | ||
de9ce703 DT |
1302 | static void i8042_free_irqs(void) |
1303 | { | |
1304 | if (i8042_aux_irq_registered) | |
1305 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1306 | if (i8042_kbd_irq_registered) | |
1307 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1308 | ||
386b3849 | 1309 | i8042_aux_irq_registered = i8042_kbd_irq_registered = false; |
de9ce703 DT |
1310 | } |
1311 | ||
f8113416 | 1312 | static int __init i8042_setup_aux(void) |
de9ce703 DT |
1313 | { |
1314 | int (*aux_enable)(void); | |
1315 | int error; | |
1316 | int i; | |
1da177e4 | 1317 | |
de9ce703 | 1318 | if (i8042_check_aux()) |
87fd6318 | 1319 | return -ENODEV; |
1da177e4 | 1320 | |
de9ce703 DT |
1321 | if (i8042_nomux || i8042_check_mux()) { |
1322 | error = i8042_create_aux_port(-1); | |
1323 | if (error) | |
1324 | goto err_free_ports; | |
1325 | aux_enable = i8042_enable_aux_port; | |
1326 | } else { | |
1327 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
1328 | error = i8042_create_aux_port(i); | |
1329 | if (error) | |
1330 | goto err_free_ports; | |
0854e52d | 1331 | } |
de9ce703 | 1332 | aux_enable = i8042_enable_mux_ports; |
1da177e4 LT |
1333 | } |
1334 | ||
de9ce703 DT |
1335 | error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, |
1336 | "i8042", i8042_platform_device); | |
1337 | if (error) | |
1338 | goto err_free_ports; | |
945ef0d4 | 1339 | |
de9ce703 DT |
1340 | if (aux_enable()) |
1341 | goto err_free_irq; | |
1da177e4 | 1342 | |
386b3849 | 1343 | i8042_aux_irq_registered = true; |
1da177e4 | 1344 | return 0; |
0854e52d | 1345 | |
de9ce703 DT |
1346 | err_free_irq: |
1347 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1348 | err_free_ports: | |
1349 | i8042_free_aux_ports(); | |
1350 | return error; | |
1351 | } | |
0854e52d | 1352 | |
f8113416 | 1353 | static int __init i8042_setup_kbd(void) |
de9ce703 DT |
1354 | { |
1355 | int error; | |
1356 | ||
1357 | error = i8042_create_kbd_port(); | |
1358 | if (error) | |
1359 | return error; | |
1360 | ||
1361 | error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, | |
1362 | "i8042", i8042_platform_device); | |
1363 | if (error) | |
1364 | goto err_free_port; | |
1365 | ||
1366 | error = i8042_enable_kbd_port(); | |
1367 | if (error) | |
1368 | goto err_free_irq; | |
1369 | ||
386b3849 | 1370 | i8042_kbd_irq_registered = true; |
de9ce703 DT |
1371 | return 0; |
1372 | ||
1373 | err_free_irq: | |
1374 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1375 | err_free_port: | |
1376 | i8042_free_kbd_port(); | |
1377 | return error; | |
1da177e4 LT |
1378 | } |
1379 | ||
f8113416 | 1380 | static int __init i8042_probe(struct platform_device *dev) |
1da177e4 | 1381 | { |
de9ce703 | 1382 | int error; |
1da177e4 | 1383 | |
ec62e1c8 DT |
1384 | i8042_platform_device = dev; |
1385 | ||
1ca56e51 DT |
1386 | if (i8042_reset) { |
1387 | error = i8042_controller_selftest(); | |
1388 | if (error) | |
1389 | return error; | |
1390 | } | |
1da177e4 | 1391 | |
de9ce703 DT |
1392 | error = i8042_controller_init(); |
1393 | if (error) | |
1394 | return error; | |
1395 | ||
d35895db BP |
1396 | #ifdef CONFIG_X86 |
1397 | if (i8042_dritek) | |
1398 | i8042_dritek_enable(); | |
1399 | #endif | |
1400 | ||
de9ce703 DT |
1401 | if (!i8042_noaux) { |
1402 | error = i8042_setup_aux(); | |
1403 | if (error && error != -ENODEV && error != -EBUSY) | |
1404 | goto out_fail; | |
1405 | } | |
1406 | ||
1407 | if (!i8042_nokbd) { | |
1408 | error = i8042_setup_kbd(); | |
1409 | if (error) | |
1410 | goto out_fail; | |
1411 | } | |
de9ce703 DT |
1412 | /* |
1413 | * Ok, everything is ready, let's register all serio ports | |
1414 | */ | |
1415 | i8042_register_ports(); | |
1416 | ||
1417 | return 0; | |
1418 | ||
1419 | out_fail: | |
1420 | i8042_free_aux_ports(); /* in case KBD failed but AUX not */ | |
1421 | i8042_free_irqs(); | |
1422 | i8042_controller_reset(); | |
ec62e1c8 | 1423 | i8042_platform_device = NULL; |
de9ce703 DT |
1424 | |
1425 | return error; | |
1426 | } | |
1427 | ||
1428 | static int __devexit i8042_remove(struct platform_device *dev) | |
1429 | { | |
1430 | i8042_unregister_ports(); | |
1431 | i8042_free_irqs(); | |
1432 | i8042_controller_reset(); | |
ec62e1c8 | 1433 | i8042_platform_device = NULL; |
1da177e4 | 1434 | |
87fd6318 DT |
1435 | return 0; |
1436 | } | |
1437 | ||
1438 | static struct platform_driver i8042_driver = { | |
1439 | .driver = { | |
1440 | .name = "i8042", | |
1441 | .owner = THIS_MODULE, | |
ebd7768d DT |
1442 | #ifdef CONFIG_PM |
1443 | .pm = &i8042_pm_ops, | |
1444 | #endif | |
87fd6318 | 1445 | }, |
87fd6318 | 1446 | .remove = __devexit_p(i8042_remove), |
82dd9eff | 1447 | .shutdown = i8042_shutdown, |
87fd6318 DT |
1448 | }; |
1449 | ||
1450 | static int __init i8042_init(void) | |
1451 | { | |
ec62e1c8 | 1452 | struct platform_device *pdev; |
87fd6318 DT |
1453 | int err; |
1454 | ||
1455 | dbg_init(); | |
1456 | ||
1457 | err = i8042_platform_init(); | |
1458 | if (err) | |
1459 | return err; | |
1460 | ||
de9ce703 DT |
1461 | err = i8042_controller_check(); |
1462 | if (err) | |
1463 | goto err_platform_exit; | |
87fd6318 | 1464 | |
ec62e1c8 DT |
1465 | pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); |
1466 | if (IS_ERR(pdev)) { | |
1467 | err = PTR_ERR(pdev); | |
f8113416 | 1468 | goto err_platform_exit; |
87fd6318 DT |
1469 | } |
1470 | ||
de9ce703 DT |
1471 | panic_blink = i8042_panic_blink; |
1472 | ||
87fd6318 DT |
1473 | return 0; |
1474 | ||
87fd6318 DT |
1475 | err_platform_exit: |
1476 | i8042_platform_exit(); | |
87fd6318 DT |
1477 | return err; |
1478 | } | |
1479 | ||
1480 | static void __exit i8042_exit(void) | |
1481 | { | |
f8113416 | 1482 | platform_device_unregister(i8042_platform_device); |
af045b86 | 1483 | platform_driver_unregister(&i8042_driver); |
1da177e4 LT |
1484 | i8042_platform_exit(); |
1485 | ||
1486 | panic_blink = NULL; | |
1487 | } | |
1488 | ||
1489 | module_init(i8042_init); | |
1490 | module_exit(i8042_exit); |