Commit | Line | Data |
---|---|---|
f931551b | 1 | /* |
581d01aa | 2 | * Copyright (c) 2012 - 2017 Intel Corporation. All rights reserved. |
1fb9fed6 | 3 | * Copyright (c) 2008 - 2012 QLogic Corporation. All rights reserved. |
f931551b RC |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | /* | |
35 | * This file contains all of the code that is specific to the | |
36 | * InfiniPath 7322 chip | |
37 | */ | |
38 | ||
39 | #include <linux/interrupt.h> | |
40 | #include <linux/pci.h> | |
41 | #include <linux/delay.h> | |
42 | #include <linux/io.h> | |
43 | #include <linux/jiffies.h> | |
e4dd23d7 | 44 | #include <linux/module.h> |
f931551b RC |
45 | #include <rdma/ib_verbs.h> |
46 | #include <rdma/ib_smi.h> | |
8469ba39 MM |
47 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
48 | #include <linux/dca.h> | |
49 | #endif | |
f931551b RC |
50 | |
51 | #include "qib.h" | |
52 | #include "qib_7322_regs.h" | |
53 | #include "qib_qsfp.h" | |
54 | ||
55 | #include "qib_mad.h" | |
1fb9fed6 | 56 | #include "qib_verbs.h" |
f931551b | 57 | |
7fac3301 MM |
58 | #undef pr_fmt |
59 | #define pr_fmt(fmt) QIB_DRV_NAME " " fmt | |
60 | ||
f931551b RC |
61 | static void qib_setup_7322_setextled(struct qib_pportdata *, u32); |
62 | static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t); | |
63 | static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op); | |
64 | static irqreturn_t qib_7322intr(int irq, void *data); | |
65 | static irqreturn_t qib_7322bufavail(int irq, void *data); | |
66 | static irqreturn_t sdma_intr(int irq, void *data); | |
67 | static irqreturn_t sdma_idle_intr(int irq, void *data); | |
68 | static irqreturn_t sdma_progress_intr(int irq, void *data); | |
69 | static irqreturn_t sdma_cleanup_intr(int irq, void *data); | |
70 | static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32, | |
71 | struct qib_ctxtdata *rcd); | |
72 | static u8 qib_7322_phys_portstate(u64); | |
73 | static u32 qib_7322_iblink_state(u64); | |
74 | static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, | |
75 | u16 linitcmd); | |
76 | static void force_h1(struct qib_pportdata *); | |
77 | static void adj_tx_serdes(struct qib_pportdata *); | |
78 | static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8); | |
79 | static void qib_7322_mini_pcs_reset(struct qib_pportdata *); | |
80 | ||
81 | static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32); | |
82 | static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned); | |
a0a234d4 MM |
83 | static void serdes_7322_los_enable(struct qib_pportdata *, int); |
84 | static int serdes_7322_init_old(struct qib_pportdata *); | |
85 | static int serdes_7322_init_new(struct qib_pportdata *); | |
0b3ddf38 | 86 | static void dump_sdma_7322_state(struct qib_pportdata *); |
f931551b RC |
87 | |
88 | #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb)) | |
89 | ||
90 | /* LE2 serdes values for different cases */ | |
91 | #define LE2_DEFAULT 5 | |
92 | #define LE2_5m 4 | |
93 | #define LE2_QME 0 | |
94 | ||
95 | /* Below is special-purpose, so only really works for the IB SerDes blocks. */ | |
96 | #define IBSD(hw_pidx) (hw_pidx + 2) | |
97 | ||
98 | /* these are variables for documentation and experimentation purposes */ | |
99 | static const unsigned rcv_int_timeout = 375; | |
100 | static const unsigned rcv_int_count = 16; | |
101 | static const unsigned sdma_idle_cnt = 64; | |
102 | ||
103 | /* Time to stop altering Rx Equalization parameters, after link up. */ | |
104 | #define RXEQ_DISABLE_MSECS 2500 | |
105 | ||
106 | /* | |
107 | * Number of VLs we are configured to use (to allow for more | |
108 | * credits per vl, etc.) | |
109 | */ | |
110 | ushort qib_num_cfg_vls = 2; | |
111 | module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO); | |
112 | MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)"); | |
113 | ||
114 | static ushort qib_chase = 1; | |
115 | module_param_named(chase, qib_chase, ushort, S_IRUGO); | |
116 | MODULE_PARM_DESC(chase, "Enable state chase handling"); | |
117 | ||
118 | static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */ | |
119 | module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO); | |
a46a2802 | 120 | MODULE_PARM_DESC(long_attenuation, |
f931551b RC |
121 | "attenuation cutoff (dB) for long copper cable setup"); |
122 | ||
123 | static ushort qib_singleport; | |
124 | module_param_named(singleport, qib_singleport, ushort, S_IRUGO); | |
125 | MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space"); | |
126 | ||
e67306a3 MM |
127 | static ushort qib_krcvq01_no_msi; |
128 | module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO); | |
129 | MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2"); | |
130 | ||
0a43e117 MM |
131 | /* |
132 | * Receive header queue sizes | |
133 | */ | |
134 | static unsigned qib_rcvhdrcnt; | |
135 | module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO); | |
136 | MODULE_PARM_DESC(rcvhdrcnt, "receive header count"); | |
137 | ||
138 | static unsigned qib_rcvhdrsize; | |
139 | module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO); | |
140 | MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words"); | |
141 | ||
142 | static unsigned qib_rcvhdrentsize; | |
143 | module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO); | |
144 | MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words"); | |
145 | ||
f931551b RC |
146 | #define MAX_ATTEN_LEN 64 /* plenty for any real system */ |
147 | /* for read back, default index is ~5m copper cable */ | |
a77fcf89 RC |
148 | static char txselect_list[MAX_ATTEN_LEN] = "10"; |
149 | static struct kparam_string kp_txselect = { | |
150 | .string = txselect_list, | |
f931551b RC |
151 | .maxlen = MAX_ATTEN_LEN |
152 | }; | |
e4dca7b7 | 153 | static int setup_txselect(const char *, const struct kernel_param *); |
a77fcf89 RC |
154 | module_param_call(txselect, setup_txselect, param_get_string, |
155 | &kp_txselect, S_IWUSR | S_IRUGO); | |
a46a2802 | 156 | MODULE_PARM_DESC(txselect, |
a77fcf89 | 157 | "Tx serdes indices (for no QSFP or invalid QSFP data)"); |
f931551b RC |
158 | |
159 | #define BOARD_QME7342 5 | |
160 | #define BOARD_QMH7342 6 | |
0e6bbba5 | 161 | #define BOARD_QMH7360 9 |
f931551b RC |
162 | #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ |
163 | BOARD_QMH7342) | |
164 | #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ | |
165 | BOARD_QME7342) | |
166 | ||
167 | #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64)) | |
168 | ||
169 | #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64))) | |
170 | ||
171 | #define MASK_ACROSS(lsb, msb) \ | |
172 | (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb)) | |
173 | ||
174 | #define SYM_RMASK(regname, fldname) ((u64) \ | |
175 | QIB_7322_##regname##_##fldname##_RMASK) | |
176 | ||
177 | #define SYM_MASK(regname, fldname) ((u64) \ | |
178 | QIB_7322_##regname##_##fldname##_RMASK << \ | |
179 | QIB_7322_##regname##_##fldname##_LSB) | |
180 | ||
181 | #define SYM_FIELD(value, regname, fldname) ((u64) \ | |
182 | (((value) >> SYM_LSB(regname, fldname)) & \ | |
183 | SYM_RMASK(regname, fldname))) | |
184 | ||
185 | /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */ | |
186 | #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \ | |
187 | (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits)) | |
188 | ||
189 | #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask) | |
190 | #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask) | |
191 | #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask) | |
192 | #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask) | |
193 | #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port) | |
194 | /* Below because most, but not all, fields of IntMask have that full suffix */ | |
195 | #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port) | |
196 | ||
197 | ||
198 | #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB) | |
199 | ||
200 | /* | |
201 | * the size bits give us 2^N, in KB units. 0 marks as invalid, | |
202 | * and 7 is reserved. We currently use only 2KB and 4KB | |
203 | */ | |
204 | #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB | |
205 | #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */ | |
206 | #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */ | |
207 | #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */ | |
208 | ||
209 | #define SendIBSLIDAssignMask \ | |
210 | QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK | |
211 | #define SendIBSLMCMask \ | |
212 | QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK | |
213 | ||
214 | #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn) | |
215 | #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn) | |
216 | #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn) | |
217 | #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn) | |
218 | #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN) | |
219 | #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN) | |
220 | ||
221 | #define _QIB_GPIO_SDA_NUM 1 | |
222 | #define _QIB_GPIO_SCL_NUM 0 | |
223 | #define QIB_EEPROM_WEN_NUM 14 | |
224 | #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */ | |
225 | ||
226 | /* HW counter clock is at 4nsec */ | |
227 | #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000 | |
228 | ||
229 | /* full speed IB port 1 only */ | |
230 | #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR) | |
231 | #define PORT_SPD_CAP_SHIFT 3 | |
232 | ||
233 | /* full speed featuremask, both ports */ | |
234 | #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT)) | |
235 | ||
236 | /* | |
237 | * This file contains almost all the chip-specific register information and | |
238 | * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip. | |
239 | */ | |
240 | ||
241 | /* Use defines to tie machine-generated names to lower-case names */ | |
242 | #define kr_contextcnt KREG_IDX(ContextCnt) | |
243 | #define kr_control KREG_IDX(Control) | |
244 | #define kr_counterregbase KREG_IDX(CntrRegBase) | |
245 | #define kr_errclear KREG_IDX(ErrClear) | |
246 | #define kr_errmask KREG_IDX(ErrMask) | |
247 | #define kr_errstatus KREG_IDX(ErrStatus) | |
248 | #define kr_extctrl KREG_IDX(EXTCtrl) | |
249 | #define kr_extstatus KREG_IDX(EXTStatus) | |
250 | #define kr_gpio_clear KREG_IDX(GPIOClear) | |
251 | #define kr_gpio_mask KREG_IDX(GPIOMask) | |
252 | #define kr_gpio_out KREG_IDX(GPIOOut) | |
253 | #define kr_gpio_status KREG_IDX(GPIOStatus) | |
254 | #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl) | |
255 | #define kr_debugportval KREG_IDX(DebugPortValueReg) | |
256 | #define kr_fmask KREG_IDX(feature_mask) | |
257 | #define kr_act_fmask KREG_IDX(active_feature_mask) | |
258 | #define kr_hwerrclear KREG_IDX(HwErrClear) | |
259 | #define kr_hwerrmask KREG_IDX(HwErrMask) | |
260 | #define kr_hwerrstatus KREG_IDX(HwErrStatus) | |
261 | #define kr_intclear KREG_IDX(IntClear) | |
262 | #define kr_intmask KREG_IDX(IntMask) | |
263 | #define kr_intredirect KREG_IDX(IntRedirect0) | |
264 | #define kr_intstatus KREG_IDX(IntStatus) | |
265 | #define kr_pagealign KREG_IDX(PageAlign) | |
266 | #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0) | |
267 | #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */ | |
268 | #define kr_rcvegrbase KREG_IDX(RcvEgrBase) | |
269 | #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt) | |
270 | #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt) | |
271 | #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize) | |
272 | #define kr_rcvhdrsize KREG_IDX(RcvHdrSize) | |
273 | #define kr_rcvtidbase KREG_IDX(RcvTIDBase) | |
274 | #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt) | |
275 | #define kr_revision KREG_IDX(Revision) | |
276 | #define kr_scratch KREG_IDX(Scratch) | |
277 | #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */ | |
278 | #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */ | |
279 | #define kr_sendctrl KREG_IDX(SendCtrl) | |
280 | #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */ | |
281 | #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */ | |
282 | #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr) | |
283 | #define kr_sendpiobufbase KREG_IDX(SendBufBase) | |
284 | #define kr_sendpiobufcnt KREG_IDX(SendBufCnt) | |
285 | #define kr_sendpiosize KREG_IDX(SendBufSize) | |
286 | #define kr_sendregbase KREG_IDX(SendRegBase) | |
287 | #define kr_sendbufavail0 KREG_IDX(SendBufAvail0) | |
288 | #define kr_userregbase KREG_IDX(UserRegBase) | |
289 | #define kr_intgranted KREG_IDX(Int_Granted) | |
290 | #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int) | |
291 | #define kr_intblocked KREG_IDX(IntBlocked) | |
292 | #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG) | |
293 | ||
294 | /* | |
295 | * per-port kernel registers. Access only with qib_read_kreg_port() | |
296 | * or qib_write_kreg_port() | |
297 | */ | |
298 | #define krp_errclear KREG_IBPORT_IDX(ErrClear) | |
299 | #define krp_errmask KREG_IBPORT_IDX(ErrMask) | |
300 | #define krp_errstatus KREG_IBPORT_IDX(ErrStatus) | |
301 | #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0) | |
302 | #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit) | |
303 | #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID) | |
304 | #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig) | |
305 | #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA) | |
306 | #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB) | |
307 | #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC) | |
308 | #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA) | |
309 | #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB) | |
310 | #define krp_txestatus KREG_IBPORT_IDX(TXEStatus) | |
311 | #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0) | |
312 | #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl) | |
313 | #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey) | |
314 | #define krp_psinterval KREG_IBPORT_IDX(PSInterval) | |
315 | #define krp_psstart KREG_IBPORT_IDX(PSStart) | |
316 | #define krp_psstat KREG_IBPORT_IDX(PSStat) | |
317 | #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP) | |
318 | #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl) | |
319 | #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt) | |
320 | #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA) | |
321 | #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0) | |
322 | #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15) | |
323 | #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl) | |
324 | #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl) | |
325 | #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase) | |
326 | #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0) | |
327 | #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1) | |
328 | #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2) | |
329 | #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0) | |
330 | #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1) | |
331 | #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2) | |
332 | #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt) | |
333 | #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead) | |
334 | #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr) | |
335 | #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt) | |
336 | #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen) | |
337 | #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld) | |
338 | #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt) | |
339 | #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus) | |
340 | #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail) | |
341 | #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom) | |
342 | #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign) | |
343 | #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask) | |
344 | #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX) | |
345 | #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD) | |
346 | #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE) | |
347 | #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl) | |
348 | ||
349 | /* | |
b595076a | 350 | * Per-context kernel registers. Access only with qib_read_kreg_ctxt() |
f931551b RC |
351 | * or qib_write_kreg_ctxt() |
352 | */ | |
353 | #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0) | |
354 | #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0) | |
355 | ||
356 | /* | |
357 | * TID Flow table, per context. Reduces | |
358 | * number of hdrq updates to one per flow (or on errors). | |
359 | * context 0 and 1 share same memory, but have distinct | |
360 | * addresses. Since for now, we never use expected sends | |
361 | * on kernel contexts, we don't worry about that (we initialize | |
362 | * those entries for ctxt 0/1 on driver load twice, for example). | |
363 | */ | |
364 | #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */ | |
365 | #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0)) | |
366 | ||
367 | /* these are the error bits in the tid flows, and are W1C */ | |
368 | #define TIDFLOW_ERRBITS ( \ | |
369 | (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \ | |
370 | SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \ | |
371 | (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \ | |
372 | SYM_LSB(RcvTIDFlowTable0, SeqMismatch))) | |
373 | ||
374 | /* Most (not all) Counters are per-IBport. | |
375 | * Requires LBIntCnt is at offset 0 in the group | |
376 | */ | |
377 | #define CREG_IDX(regname) \ | |
378 | ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64)) | |
379 | ||
380 | #define crp_badformat CREG_IDX(RxVersionErrCnt) | |
381 | #define crp_err_rlen CREG_IDX(RxLenErrCnt) | |
382 | #define crp_erricrc CREG_IDX(RxICRCErrCnt) | |
383 | #define crp_errlink CREG_IDX(RxLinkMalformCnt) | |
384 | #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt) | |
385 | #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt) | |
386 | #define crp_errvcrc CREG_IDX(RxVCRCErrCnt) | |
387 | #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt) | |
388 | #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt) | |
389 | #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt) | |
390 | #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt) | |
391 | #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt) | |
392 | #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt) | |
393 | #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt) | |
394 | #define crp_pktrcv CREG_IDX(RxDataPktCnt) | |
395 | #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt) | |
396 | #define crp_pktsend CREG_IDX(TxDataPktCnt) | |
397 | #define crp_pktsendflow CREG_IDX(TxFlowPktCnt) | |
398 | #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount) | |
399 | #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount) | |
400 | #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount) | |
401 | #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount) | |
402 | #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount) | |
403 | #define crp_rcvebp CREG_IDX(RxEBPCnt) | |
404 | #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt) | |
405 | #define crp_rcvovfl CREG_IDX(RxBufOvflCnt) | |
406 | #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt) | |
407 | #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt) | |
408 | #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt) | |
409 | #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt) | |
410 | #define crp_rxvlerr CREG_IDX(RxVlErrCnt) | |
411 | #define crp_sendstall CREG_IDX(TxFlowStallCnt) | |
412 | #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt) | |
413 | #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt) | |
414 | #define crp_txlenerr CREG_IDX(TxLenErrCnt) | |
f931551b RC |
415 | #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt) |
416 | #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt) | |
417 | #define crp_txunderrun CREG_IDX(TxUnderrunCnt) | |
418 | #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt) | |
419 | #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt) | |
420 | #define crp_wordrcv CREG_IDX(RxDwordCnt) | |
421 | #define crp_wordsend CREG_IDX(TxDwordCnt) | |
422 | #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut) | |
423 | ||
424 | /* these are the (few) counters that are not port-specific */ | |
425 | #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \ | |
426 | QIB_7322_LBIntCnt_OFFS) / sizeof(u64)) | |
427 | #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt) | |
428 | #define cr_lbint CREG_DEVIDX(LBIntCnt) | |
429 | #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt) | |
430 | #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt) | |
431 | #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt) | |
432 | #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt) | |
433 | #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt) | |
434 | ||
435 | /* no chip register for # of IB ports supported, so define */ | |
436 | #define NUM_IB_PORTS 2 | |
437 | ||
438 | /* 1 VL15 buffer per hardware IB port, no register for this, so define */ | |
439 | #define NUM_VL15_BUFS NUM_IB_PORTS | |
440 | ||
441 | /* | |
442 | * context 0 and 1 are special, and there is no chip register that | |
443 | * defines this value, so we have to define it here. | |
444 | * These are all allocated to either 0 or 1 for single port | |
445 | * hardware configuration, otherwise each gets half | |
446 | */ | |
447 | #define KCTXT0_EGRCNT 2048 | |
448 | ||
449 | /* values for vl and port fields in PBC, 7322-specific */ | |
450 | #define PBC_PORT_SEL_LSB 26 | |
451 | #define PBC_PORT_SEL_RMASK 1 | |
452 | #define PBC_VL_NUM_LSB 27 | |
453 | #define PBC_VL_NUM_RMASK 7 | |
454 | #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */ | |
455 | #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */ | |
456 | ||
457 | static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = { | |
458 | [IB_RATE_2_5_GBPS] = 16, | |
459 | [IB_RATE_5_GBPS] = 8, | |
460 | [IB_RATE_10_GBPS] = 4, | |
461 | [IB_RATE_20_GBPS] = 2, | |
462 | [IB_RATE_30_GBPS] = 2, | |
463 | [IB_RATE_40_GBPS] = 1 | |
464 | }; | |
465 | ||
7f566a91 HG |
466 | static const char * const qib_sdma_state_names[] = { |
467 | [qib_sdma_state_s00_hw_down] = "s00_HwDown", | |
468 | [qib_sdma_state_s10_hw_start_up_wait] = "s10_HwStartUpWait", | |
469 | [qib_sdma_state_s20_idle] = "s20_Idle", | |
470 | [qib_sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait", | |
471 | [qib_sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait", | |
472 | [qib_sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait", | |
473 | [qib_sdma_state_s99_running] = "s99_Running", | |
474 | }; | |
475 | ||
f931551b RC |
476 | #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive) |
477 | #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive) | |
478 | ||
479 | /* link training states, from IBC */ | |
480 | #define IB_7322_LT_STATE_DISABLED 0x00 | |
481 | #define IB_7322_LT_STATE_LINKUP 0x01 | |
482 | #define IB_7322_LT_STATE_POLLACTIVE 0x02 | |
483 | #define IB_7322_LT_STATE_POLLQUIET 0x03 | |
484 | #define IB_7322_LT_STATE_SLEEPDELAY 0x04 | |
485 | #define IB_7322_LT_STATE_SLEEPQUIET 0x05 | |
486 | #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08 | |
487 | #define IB_7322_LT_STATE_CFGRCVFCFG 0x09 | |
488 | #define IB_7322_LT_STATE_CFGWAITRMT 0x0a | |
489 | #define IB_7322_LT_STATE_CFGIDLE 0x0b | |
490 | #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c | |
491 | #define IB_7322_LT_STATE_TXREVLANES 0x0d | |
492 | #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e | |
493 | #define IB_7322_LT_STATE_RECOVERIDLE 0x0f | |
494 | #define IB_7322_LT_STATE_CFGENH 0x10 | |
495 | #define IB_7322_LT_STATE_CFGTEST 0x11 | |
31264484 MH |
496 | #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12 |
497 | #define IB_7322_LT_STATE_CFGWAITENH 0x13 | |
f931551b RC |
498 | |
499 | /* link state machine states from IBC */ | |
500 | #define IB_7322_L_STATE_DOWN 0x0 | |
501 | #define IB_7322_L_STATE_INIT 0x1 | |
502 | #define IB_7322_L_STATE_ARM 0x2 | |
503 | #define IB_7322_L_STATE_ACTIVE 0x3 | |
504 | #define IB_7322_L_STATE_ACT_DEFER 0x4 | |
505 | ||
506 | static const u8 qib_7322_physportstate[0x20] = { | |
507 | [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED, | |
508 | [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP, | |
509 | [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL, | |
510 | [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL, | |
511 | [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP, | |
512 | [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP, | |
513 | [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN, | |
514 | [IB_7322_LT_STATE_CFGRCVFCFG] = | |
515 | IB_PHYSPORTSTATE_CFG_TRAIN, | |
516 | [IB_7322_LT_STATE_CFGWAITRMT] = | |
517 | IB_PHYSPORTSTATE_CFG_TRAIN, | |
518 | [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE, | |
519 | [IB_7322_LT_STATE_RECOVERRETRAIN] = | |
520 | IB_PHYSPORTSTATE_LINK_ERR_RECOVER, | |
521 | [IB_7322_LT_STATE_RECOVERWAITRMT] = | |
522 | IB_PHYSPORTSTATE_LINK_ERR_RECOVER, | |
523 | [IB_7322_LT_STATE_RECOVERIDLE] = | |
524 | IB_PHYSPORTSTATE_LINK_ERR_RECOVER, | |
525 | [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH, | |
526 | [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN, | |
31264484 MH |
527 | [IB_7322_LT_STATE_CFGWAITRMTTEST] = |
528 | IB_PHYSPORTSTATE_CFG_TRAIN, | |
529 | [IB_7322_LT_STATE_CFGWAITENH] = | |
530 | IB_PHYSPORTSTATE_CFG_WAIT_ENH, | |
f931551b RC |
531 | [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN, |
532 | [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN, | |
533 | [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN, | |
534 | [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN | |
535 | }; | |
536 | ||
8469ba39 MM |
537 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
538 | struct qib_irq_notify { | |
539 | int rcv; | |
540 | void *arg; | |
541 | struct irq_affinity_notify notify; | |
542 | }; | |
543 | #endif | |
544 | ||
f931551b RC |
545 | struct qib_chip_specific { |
546 | u64 __iomem *cregbase; | |
547 | u64 *cntrs; | |
548 | spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */ | |
549 | spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */ | |
550 | u64 main_int_mask; /* clear bits which have dedicated handlers */ | |
551 | u64 int_enable_mask; /* for per port interrupts in single port mode */ | |
552 | u64 errormask; | |
553 | u64 hwerrmask; | |
554 | u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */ | |
555 | u64 gpio_mask; /* shadow the gpio mask register */ | |
556 | u64 extctrl; /* shadow the gpio output enable, etc... */ | |
557 | u32 ncntrs; | |
558 | u32 nportcntrs; | |
559 | u32 cntrnamelen; | |
560 | u32 portcntrnamelen; | |
561 | u32 numctxts; | |
562 | u32 rcvegrcnt; | |
563 | u32 updthresh; /* current AvailUpdThld */ | |
564 | u32 updthresh_dflt; /* default AvailUpdThld */ | |
565 | u32 r1; | |
f931551b RC |
566 | u32 num_msix_entries; |
567 | u32 sdmabufcnt; | |
568 | u32 lastbuf_for_pio; | |
569 | u32 stay_in_freeze; | |
570 | u32 recovery_ports_initted; | |
8469ba39 MM |
571 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
572 | u32 dca_ctrl; | |
573 | int rhdr_cpu[18]; | |
574 | int sdma_cpu[2]; | |
575 | u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */ | |
576 | #endif | |
a778f3fd | 577 | struct qib_msix_entry *msix_entries; |
f931551b RC |
578 | unsigned long *sendchkenable; |
579 | unsigned long *sendgrhchk; | |
580 | unsigned long *sendibchk; | |
581 | u32 rcvavail_timeout[18]; | |
582 | char emsgbuf[128]; /* for device error interrupt msg buffer */ | |
583 | }; | |
584 | ||
585 | /* Table of entries in "human readable" form Tx Emphasis. */ | |
586 | struct txdds_ent { | |
587 | u8 amp; | |
588 | u8 pre; | |
589 | u8 main; | |
590 | u8 post; | |
591 | }; | |
592 | ||
593 | struct vendor_txdds_ent { | |
594 | u8 oui[QSFP_VOUI_LEN]; | |
595 | u8 *partnum; | |
596 | struct txdds_ent sdr; | |
597 | struct txdds_ent ddr; | |
598 | struct txdds_ent qdr; | |
599 | }; | |
600 | ||
601 | static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *); | |
602 | ||
603 | #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */ | |
22baa407 | 604 | #define TXDDS_EXTRA_SZ 18 /* number of extra tx settings entries */ |
e706203c | 605 | #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */ |
f931551b RC |
606 | #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */ |
607 | ||
608 | #define H1_FORCE_VAL 8 | |
a77fcf89 RC |
609 | #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */ |
610 | #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */ | |
f931551b RC |
611 | |
612 | /* The static and dynamic registers are paired, and the pairs indexed by spd */ | |
613 | #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \ | |
614 | + ((spd) * 2)) | |
615 | ||
616 | #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */ | |
617 | #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */ | |
618 | #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */ | |
619 | #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */ | |
620 | #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */ | |
621 | ||
f931551b RC |
622 | struct qib_chippport_specific { |
623 | u64 __iomem *kpregbase; | |
624 | u64 __iomem *cpregbase; | |
625 | u64 *portcntrs; | |
626 | struct qib_pportdata *ppd; | |
627 | wait_queue_head_t autoneg_wait; | |
628 | struct delayed_work autoneg_work; | |
629 | struct delayed_work ipg_work; | |
630 | struct timer_list chase_timer; | |
631 | /* | |
632 | * these 5 fields are used to establish deltas for IB symbol | |
633 | * errors and linkrecovery errors. They can be reported on | |
634 | * some chips during link negotiation prior to INIT, and with | |
635 | * DDR when faking DDR negotiations with non-IBTA switches. | |
636 | * The chip counters are adjusted at driver unload if there is | |
637 | * a non-zero delta. | |
638 | */ | |
639 | u64 ibdeltainprog; | |
640 | u64 ibsymdelta; | |
641 | u64 ibsymsnap; | |
642 | u64 iblnkerrdelta; | |
643 | u64 iblnkerrsnap; | |
644 | u64 iblnkdownsnap; | |
645 | u64 iblnkdowndelta; | |
646 | u64 ibmalfdelta; | |
647 | u64 ibmalfsnap; | |
648 | u64 ibcctrl_a; /* krp_ibcctrl_a shadow */ | |
649 | u64 ibcctrl_b; /* krp_ibcctrl_b shadow */ | |
8482d5d1 MM |
650 | unsigned long qdr_dfe_time; |
651 | unsigned long chase_end; | |
f931551b RC |
652 | u32 autoneg_tries; |
653 | u32 recovery_init; | |
654 | u32 qdr_dfe_on; | |
655 | u32 qdr_reforce; | |
656 | /* | |
657 | * Per-bay per-channel rcv QMH H1 values and Tx values for QDR. | |
658 | * entry zero is unused, to simplify indexing | |
659 | */ | |
a77fcf89 RC |
660 | u8 h1_val; |
661 | u8 no_eep; /* txselect table index to use if no qsfp info */ | |
f931551b RC |
662 | u8 ipg_tries; |
663 | u8 ibmalfusesnap; | |
664 | struct qib_qsfp_data qsfp_data; | |
665 | char epmsgbuf[192]; /* for port error interrupt msg buffer */ | |
0b3ddf38 | 666 | char sdmamsgbuf[192]; /* for per-port sdma error messages */ |
f931551b RC |
667 | }; |
668 | ||
669 | static struct { | |
670 | const char *name; | |
671 | irq_handler_t handler; | |
672 | int lsb; | |
673 | int port; /* 0 if not port-specific, else port # */ | |
8469ba39 | 674 | int dca; |
f931551b | 675 | } irq_table[] = { |
8469ba39 | 676 | { "", qib_7322intr, -1, 0, 0 }, |
a778f3fd | 677 | { " (buf avail)", qib_7322bufavail, |
8469ba39 | 678 | SYM_LSB(IntStatus, SendBufAvail), 0, 0}, |
a778f3fd | 679 | { " (sdma 0)", sdma_intr, |
8469ba39 | 680 | SYM_LSB(IntStatus, SDmaInt_0), 1, 1 }, |
a778f3fd | 681 | { " (sdma 1)", sdma_intr, |
8469ba39 | 682 | SYM_LSB(IntStatus, SDmaInt_1), 2, 1 }, |
a778f3fd | 683 | { " (sdmaI 0)", sdma_idle_intr, |
8469ba39 | 684 | SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1}, |
a778f3fd | 685 | { " (sdmaI 1)", sdma_idle_intr, |
8469ba39 | 686 | SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1}, |
a778f3fd | 687 | { " (sdmaP 0)", sdma_progress_intr, |
8469ba39 | 688 | SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 }, |
a778f3fd | 689 | { " (sdmaP 1)", sdma_progress_intr, |
8469ba39 | 690 | SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 }, |
a778f3fd | 691 | { " (sdmaC 0)", sdma_cleanup_intr, |
8469ba39 | 692 | SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 }, |
a778f3fd | 693 | { " (sdmaC 1)", sdma_cleanup_intr, |
8469ba39 | 694 | SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0}, |
f931551b RC |
695 | }; |
696 | ||
8469ba39 MM |
697 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
698 | ||
699 | static const struct dca_reg_map { | |
700 | int shadow_inx; | |
701 | int lsb; | |
702 | u64 mask; | |
703 | u16 regno; | |
704 | } dca_rcvhdr_reg_map[] = { | |
705 | { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH), | |
706 | ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) }, | |
707 | { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH), | |
708 | ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) }, | |
709 | { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH), | |
710 | ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) }, | |
711 | { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH), | |
712 | ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) }, | |
713 | { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH), | |
714 | ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) }, | |
715 | { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH), | |
716 | ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) }, | |
717 | { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH), | |
718 | ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) }, | |
719 | { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH), | |
720 | ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) }, | |
721 | { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH), | |
722 | ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) }, | |
723 | { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH), | |
724 | ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) }, | |
725 | { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH), | |
726 | ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) }, | |
727 | { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH), | |
728 | ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) }, | |
729 | { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH), | |
730 | ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) }, | |
731 | { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH), | |
732 | ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) }, | |
733 | { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH), | |
734 | ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) }, | |
735 | { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH), | |
736 | ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) }, | |
737 | { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH), | |
738 | ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) }, | |
739 | { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH), | |
740 | ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) }, | |
741 | }; | |
742 | #endif | |
743 | ||
f931551b RC |
744 | /* ibcctrl bits */ |
745 | #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1 | |
746 | /* cycle through TS1/TS2 till OK */ | |
747 | #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2 | |
748 | /* wait for TS1, then go on */ | |
749 | #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3 | |
750 | #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16 | |
751 | ||
752 | #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */ | |
753 | #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */ | |
754 | #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */ | |
755 | ||
756 | #define BLOB_7322_IBCHG 0x101 | |
757 | ||
758 | static inline void qib_write_kreg(const struct qib_devdata *dd, | |
759 | const u32 regno, u64 value); | |
760 | static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32); | |
761 | static void write_7322_initregs(struct qib_devdata *); | |
762 | static void write_7322_init_portregs(struct qib_pportdata *); | |
763 | static void setup_7322_link_recovery(struct qib_pportdata *, u32); | |
764 | static void check_7322_rxe_status(struct qib_pportdata *); | |
765 | static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *); | |
8469ba39 MM |
766 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
767 | static void qib_setup_dca(struct qib_devdata *dd); | |
c4bc6156 MR |
768 | static void setup_dca_notifier(struct qib_devdata *dd, int msixnum); |
769 | static void reset_dca_notifier(struct qib_devdata *dd, int msixnum); | |
8469ba39 | 770 | #endif |
f931551b RC |
771 | |
772 | /** | |
773 | * qib_read_ureg32 - read 32-bit virtualized per-context register | |
774 | * @dd: device | |
775 | * @regno: register number | |
776 | * @ctxt: context number | |
777 | * | |
778 | * Return the contents of a register that is virtualized to be per context. | |
779 | * Returns -1 on errors (not distinguishable from valid contents at | |
780 | * runtime; we may add a separate error variable at some point). | |
781 | */ | |
782 | static inline u32 qib_read_ureg32(const struct qib_devdata *dd, | |
783 | enum qib_ureg regno, int ctxt) | |
784 | { | |
785 | if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) | |
786 | return 0; | |
787 | return readl(regno + (u64 __iomem *)( | |
788 | (dd->ureg_align * ctxt) + (dd->userbase ? | |
789 | (char __iomem *)dd->userbase : | |
790 | (char __iomem *)dd->kregbase + dd->uregbase))); | |
791 | } | |
792 | ||
f931551b RC |
793 | /** |
794 | * qib_write_ureg - write virtualized per-context register | |
795 | * @dd: device | |
796 | * @regno: register number | |
797 | * @value: value | |
798 | * @ctxt: context | |
799 | * | |
800 | * Write the contents of a register that is virtualized to be per context. | |
801 | */ | |
802 | static inline void qib_write_ureg(const struct qib_devdata *dd, | |
803 | enum qib_ureg regno, u64 value, int ctxt) | |
804 | { | |
805 | u64 __iomem *ubase; | |
da12c1f6 | 806 | |
f931551b RC |
807 | if (dd->userbase) |
808 | ubase = (u64 __iomem *) | |
809 | ((char __iomem *) dd->userbase + | |
810 | dd->ureg_align * ctxt); | |
811 | else | |
812 | ubase = (u64 __iomem *) | |
813 | (dd->uregbase + | |
814 | (char __iomem *) dd->kregbase + | |
815 | dd->ureg_align * ctxt); | |
816 | ||
817 | if (dd->kregbase && (dd->flags & QIB_PRESENT)) | |
818 | writeq(value, &ubase[regno]); | |
819 | } | |
820 | ||
821 | static inline u32 qib_read_kreg32(const struct qib_devdata *dd, | |
822 | const u32 regno) | |
823 | { | |
824 | if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) | |
825 | return -1; | |
826 | return readl((u32 __iomem *) &dd->kregbase[regno]); | |
827 | } | |
828 | ||
829 | static inline u64 qib_read_kreg64(const struct qib_devdata *dd, | |
830 | const u32 regno) | |
831 | { | |
832 | if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) | |
833 | return -1; | |
834 | return readq(&dd->kregbase[regno]); | |
835 | } | |
836 | ||
837 | static inline void qib_write_kreg(const struct qib_devdata *dd, | |
838 | const u32 regno, u64 value) | |
839 | { | |
840 | if (dd->kregbase && (dd->flags & QIB_PRESENT)) | |
841 | writeq(value, &dd->kregbase[regno]); | |
842 | } | |
843 | ||
844 | /* | |
845 | * not many sanity checks for the port-specific kernel register routines, | |
846 | * since they are only used when it's known to be safe. | |
847 | */ | |
848 | static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd, | |
849 | const u16 regno) | |
850 | { | |
851 | if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT)) | |
852 | return 0ULL; | |
853 | return readq(&ppd->cpspec->kpregbase[regno]); | |
854 | } | |
855 | ||
856 | static inline void qib_write_kreg_port(const struct qib_pportdata *ppd, | |
857 | const u16 regno, u64 value) | |
858 | { | |
859 | if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase && | |
860 | (ppd->dd->flags & QIB_PRESENT)) | |
861 | writeq(value, &ppd->cpspec->kpregbase[regno]); | |
862 | } | |
863 | ||
864 | /** | |
865 | * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register | |
866 | * @dd: the qlogic_ib device | |
867 | * @regno: the register number to write | |
868 | * @ctxt: the context containing the register | |
869 | * @value: the value to write | |
870 | */ | |
871 | static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, | |
872 | const u16 regno, unsigned ctxt, | |
873 | u64 value) | |
874 | { | |
875 | qib_write_kreg(dd, regno + ctxt, value); | |
876 | } | |
877 | ||
878 | static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno) | |
879 | { | |
880 | if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) | |
881 | return 0; | |
882 | return readq(&dd->cspec->cregbase[regno]); | |
883 | ||
884 | ||
885 | } | |
886 | ||
887 | static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno) | |
888 | { | |
889 | if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) | |
890 | return 0; | |
891 | return readl(&dd->cspec->cregbase[regno]); | |
892 | ||
893 | ||
894 | } | |
895 | ||
896 | static inline void write_7322_creg_port(const struct qib_pportdata *ppd, | |
897 | u16 regno, u64 value) | |
898 | { | |
899 | if (ppd->cpspec && ppd->cpspec->cpregbase && | |
900 | (ppd->dd->flags & QIB_PRESENT)) | |
901 | writeq(value, &ppd->cpspec->cpregbase[regno]); | |
902 | } | |
903 | ||
904 | static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd, | |
905 | u16 regno) | |
906 | { | |
907 | if (!ppd->cpspec || !ppd->cpspec->cpregbase || | |
908 | !(ppd->dd->flags & QIB_PRESENT)) | |
909 | return 0; | |
910 | return readq(&ppd->cpspec->cpregbase[regno]); | |
911 | } | |
912 | ||
913 | static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd, | |
914 | u16 regno) | |
915 | { | |
916 | if (!ppd->cpspec || !ppd->cpspec->cpregbase || | |
917 | !(ppd->dd->flags & QIB_PRESENT)) | |
918 | return 0; | |
919 | return readl(&ppd->cpspec->cpregbase[regno]); | |
920 | } | |
921 | ||
922 | /* bits in Control register */ | |
923 | #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset) | |
924 | #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn) | |
925 | ||
926 | /* bits in general interrupt regs */ | |
927 | #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask) | |
928 | #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17) | |
929 | #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB) | |
930 | #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask) | |
931 | #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17) | |
932 | #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB) | |
933 | #define QIB_I_C_ERROR INT_MASK(Err) | |
934 | ||
935 | #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1)) | |
936 | #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail) | |
937 | #define QIB_I_GPIO INT_MASK(AssertGPIO) | |
938 | #define QIB_I_P_SDMAINT(pidx) \ | |
939 | (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \ | |
940 | INT_MASK_P(SDmaProgress, pidx) | \ | |
941 | INT_MASK_PM(SDmaCleanupDone, pidx)) | |
942 | ||
943 | /* Interrupt bits that are "per port" */ | |
944 | #define QIB_I_P_BITSEXTANT(pidx) \ | |
945 | (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \ | |
946 | INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \ | |
947 | INT_MASK_P(SDmaProgress, pidx) | \ | |
948 | INT_MASK_PM(SDmaCleanupDone, pidx)) | |
949 | ||
950 | /* Interrupt bits that are common to a device */ | |
951 | /* currently unused: QIB_I_SPIOSENT */ | |
952 | #define QIB_I_C_BITSEXTANT \ | |
953 | (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \ | |
954 | QIB_I_SPIOSENT | \ | |
955 | QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO) | |
956 | ||
957 | #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \ | |
958 | QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1)) | |
959 | ||
960 | /* | |
961 | * Error bits that are "per port". | |
962 | */ | |
963 | #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged) | |
964 | #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr) | |
965 | #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr) | |
966 | #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr) | |
967 | #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr) | |
968 | #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr) | |
969 | #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr) | |
970 | #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr) | |
971 | #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr) | |
972 | #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr) | |
973 | #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr) | |
974 | #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr) | |
975 | #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr) | |
976 | #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr) | |
977 | #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr) | |
978 | #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr) | |
979 | #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr) | |
980 | #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr) | |
981 | #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr) | |
982 | #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr) | |
983 | #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr) | |
984 | #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr) | |
985 | #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr) | |
986 | #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr) | |
987 | #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr) | |
988 | #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr) | |
989 | #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr) | |
990 | #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr) | |
991 | ||
992 | #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr) | |
993 | #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr) | |
994 | #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr) | |
995 | #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr) | |
996 | #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr) | |
997 | #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr) | |
998 | #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr) | |
999 | #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr) | |
1000 | #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr) | |
1001 | #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr) | |
1002 | #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr) | |
1003 | ||
1004 | /* Error bits that are common to a device */ | |
1005 | #define QIB_E_RESET ERR_MASK(ResetNegated) | |
1006 | #define QIB_E_HARDWARE ERR_MASK(HardwareErr) | |
1007 | #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr) | |
1008 | ||
1009 | ||
1010 | /* | |
1011 | * Per chip (rather than per-port) errors. Most either do | |
1012 | * nothing but trigger a print (because they self-recover, or | |
1013 | * always occur in tandem with other errors that handle the | |
1014 | * issue), or because they indicate errors with no recovery, | |
1015 | * but we want to know that they happened. | |
1016 | */ | |
1017 | #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr) | |
1018 | #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd) | |
1019 | #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr) | |
1020 | #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr) | |
1021 | #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr) | |
1022 | #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr) | |
1023 | #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr) | |
1024 | #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr) | |
1025 | ||
1026 | /* SDMA chip errors (not per port) | |
1027 | * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get | |
1028 | * the SDMAHALT error immediately, so we just print the dup error via the | |
1029 | * E_AUTO mechanism. This is true of most of the per-port fatal errors | |
1030 | * as well, but since this is port-independent, by definition, it's | |
1031 | * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per | |
1032 | * packet send errors, and so are handled in the same manner as other | |
1033 | * per-packet errors. | |
1034 | */ | |
1035 | #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err) | |
1036 | #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr) | |
1037 | #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr) | |
1038 | ||
1039 | /* | |
1040 | * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS | |
1041 | * it is used to print "common" packet errors. | |
1042 | */ | |
1043 | #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\ | |
1044 | QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\ | |
1045 | QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\ | |
1046 | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \ | |
1047 | QIB_E_P_REBP) | |
1048 | ||
1049 | /* Error Bits that Packet-related (Receive, per-port) */ | |
1050 | #define QIB_E_P_RPKTERRS (\ | |
1051 | QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \ | |
1052 | QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \ | |
1053 | QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\ | |
1054 | QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \ | |
1055 | QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \ | |
1056 | QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP) | |
1057 | ||
1058 | /* | |
1059 | * Error bits that are Send-related (per port) | |
1060 | * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling). | |
1061 | * All of these potentially need to have a buffer disarmed | |
1062 | */ | |
1063 | #define QIB_E_P_SPKTERRS (\ | |
1064 | QIB_E_P_SUNEXP_PKTNUM |\ | |
1065 | QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\ | |
1066 | QIB_E_P_SMAXPKTLEN |\ | |
1067 | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \ | |
1068 | QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \ | |
1069 | QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL) | |
1070 | ||
1071 | #define QIB_E_SPKTERRS ( \ | |
1072 | QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \ | |
1073 | ERR_MASK_N(SendUnsupportedVLErr) | \ | |
1074 | QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT) | |
1075 | ||
1076 | #define QIB_E_P_SDMAERRS ( \ | |
1077 | QIB_E_P_SDMAHALT | \ | |
1078 | QIB_E_P_SDMADESCADDRMISALIGN | \ | |
1079 | QIB_E_P_SDMAUNEXPDATA | \ | |
1080 | QIB_E_P_SDMAMISSINGDW | \ | |
1081 | QIB_E_P_SDMADWEN | \ | |
1082 | QIB_E_P_SDMARPYTAG | \ | |
1083 | QIB_E_P_SDMA1STDESC | \ | |
1084 | QIB_E_P_SDMABASE | \ | |
1085 | QIB_E_P_SDMATAILOUTOFBOUND | \ | |
1086 | QIB_E_P_SDMAOUTOFBOUND | \ | |
1087 | QIB_E_P_SDMAGENMISMATCH) | |
1088 | ||
1089 | /* | |
1090 | * This sets some bits more than once, but makes it more obvious which | |
1091 | * bits are not handled under other categories, and the repeat definition | |
1092 | * is not a problem. | |
1093 | */ | |
1094 | #define QIB_E_P_BITSEXTANT ( \ | |
1095 | QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \ | |
1096 | QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \ | |
1097 | QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \ | |
1098 | QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \ | |
1099 | ) | |
1100 | ||
1101 | /* | |
1102 | * These are errors that can occur when the link | |
1103 | * changes state while a packet is being sent or received. This doesn't | |
1104 | * cover things like EBP or VCRC that can be the result of a sending | |
1105 | * having the link change state, so we receive a "known bad" packet. | |
1106 | * All of these are "per port", so renamed: | |
1107 | */ | |
1108 | #define QIB_E_P_LINK_PKTERRS (\ | |
1109 | QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\ | |
1110 | QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\ | |
1111 | QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\ | |
1112 | QIB_E_P_RUNEXPCHAR) | |
1113 | ||
1114 | /* | |
1115 | * This sets some bits more than once, but makes it more obvious which | |
1116 | * bits are not handled under other categories (such as QIB_E_SPKTERRS), | |
1117 | * and the repeat definition is not a problem. | |
1118 | */ | |
1119 | #define QIB_E_C_BITSEXTANT (\ | |
1120 | QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\ | |
1121 | QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\ | |
1122 | QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE) | |
1123 | ||
1124 | /* Likewise Neuter E_SPKT_ERRS_IGNORE */ | |
1125 | #define E_SPKT_ERRS_IGNORE 0 | |
1126 | ||
1127 | #define QIB_EXTS_MEMBIST_DISABLED \ | |
1128 | SYM_MASK(EXTStatus, MemBISTDisabled) | |
1129 | #define QIB_EXTS_MEMBIST_ENDTEST \ | |
1130 | SYM_MASK(EXTStatus, MemBISTEndTest) | |
1131 | ||
1132 | #define QIB_E_SPIOARMLAUNCH \ | |
1133 | ERR_MASK(SendArmLaunchErr) | |
1134 | ||
1135 | #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd) | |
1136 | #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd) | |
1137 | ||
1138 | /* | |
1139 | * IBTA_1_2 is set when multiple speeds are enabled (normal), | |
1140 | * and also if forced QDR (only QDR enabled). It's enabled for the | |
1141 | * forced QDR case so that scrambling will be enabled by the TS3 | |
1142 | * exchange, when supported by both sides of the link. | |
1143 | */ | |
1144 | #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE) | |
1145 | #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED) | |
1146 | #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR) | |
1147 | #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | |
1148 | #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | |
1149 | #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \ | |
1150 | SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)) | |
1151 | #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR) | |
1152 | ||
1153 | #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod) | |
1154 | #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod) | |
1155 | ||
1156 | #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS) | |
1157 | #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS)) | |
1158 | #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS)) | |
1159 | ||
1160 | #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP) | |
1161 | #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP) | |
1162 | #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \ | |
1163 | SYM_MASK(IBCCtrlB_0, HRTBT_ENB)) | |
1164 | #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \ | |
1165 | SYM_LSB(IBCCtrlB_0, HRTBT_ENB)) | |
1166 | #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB) | |
1167 | ||
1168 | #define IBA7322_REDIRECT_VEC_PER_REG 12 | |
1169 | ||
1170 | #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En) | |
1171 | #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En) | |
1172 | #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En) | |
1173 | #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En) | |
1174 | #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En) | |
1175 | ||
1176 | #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */ | |
1177 | ||
1178 | #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \ | |
e67306a3 | 1179 | .msg = #fldname , .sz = sizeof(#fldname) } |
f931551b | 1180 | #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \ |
e67306a3 | 1181 | fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) } |
f931551b RC |
1182 | static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = { |
1183 | HWE_AUTO_P(IBSerdesPClkNotDetect, 1), | |
1184 | HWE_AUTO_P(IBSerdesPClkNotDetect, 0), | |
1185 | HWE_AUTO(PCIESerdesPClkNotDetect), | |
1186 | HWE_AUTO(PowerOnBISTFailed), | |
1187 | HWE_AUTO(TempsenseTholdReached), | |
1188 | HWE_AUTO(MemoryErr), | |
1189 | HWE_AUTO(PCIeBusParityErr), | |
1190 | HWE_AUTO(PcieCplTimeout), | |
1191 | HWE_AUTO(PciePoisonedTLP), | |
1192 | HWE_AUTO_P(SDmaMemReadErr, 1), | |
1193 | HWE_AUTO_P(SDmaMemReadErr, 0), | |
1194 | HWE_AUTO_P(IBCBusFromSPCParityErr, 1), | |
b9e03e04 | 1195 | HWE_AUTO_P(IBCBusToSPCParityErr, 1), |
f931551b | 1196 | HWE_AUTO_P(IBCBusFromSPCParityErr, 0), |
b9e03e04 | 1197 | HWE_AUTO(statusValidNoEop), |
f931551b | 1198 | HWE_AUTO(LATriggered), |
e67306a3 | 1199 | { .mask = 0, .sz = 0 } |
f931551b RC |
1200 | }; |
1201 | ||
1202 | #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \ | |
e67306a3 | 1203 | .msg = #fldname, .sz = sizeof(#fldname) } |
f931551b | 1204 | #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \ |
e67306a3 | 1205 | .msg = #fldname, .sz = sizeof(#fldname) } |
f931551b | 1206 | static const struct qib_hwerror_msgs qib_7322error_msgs[] = { |
e67306a3 MM |
1207 | E_AUTO(RcvEgrFullErr), |
1208 | E_AUTO(RcvHdrFullErr), | |
f931551b RC |
1209 | E_AUTO(ResetNegated), |
1210 | E_AUTO(HardwareErr), | |
1211 | E_AUTO(InvalidAddrErr), | |
1212 | E_AUTO(SDmaVL15Err), | |
1213 | E_AUTO(SBufVL15MisUseErr), | |
1214 | E_AUTO(InvalidEEPCmd), | |
1215 | E_AUTO(RcvContextShareErr), | |
1216 | E_AUTO(SendVLMismatchErr), | |
1217 | E_AUTO(SendArmLaunchErr), | |
1218 | E_AUTO(SendSpecialTriggerErr), | |
1219 | E_AUTO(SDmaWrongPortErr), | |
1220 | E_AUTO(SDmaBufMaskDuplicateErr), | |
e67306a3 | 1221 | { .mask = 0, .sz = 0 } |
f931551b RC |
1222 | }; |
1223 | ||
1224 | static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = { | |
1225 | E_P_AUTO(IBStatusChanged), | |
1226 | E_P_AUTO(SHeadersErr), | |
1227 | E_P_AUTO(VL15BufMisuseErr), | |
1228 | /* | |
1229 | * SDmaHaltErr is not really an error, make it clearer; | |
1230 | */ | |
e67306a3 MM |
1231 | {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted", |
1232 | .sz = 11}, | |
f931551b RC |
1233 | E_P_AUTO(SDmaDescAddrMisalignErr), |
1234 | E_P_AUTO(SDmaUnexpDataErr), | |
1235 | E_P_AUTO(SDmaMissingDwErr), | |
1236 | E_P_AUTO(SDmaDwEnErr), | |
1237 | E_P_AUTO(SDmaRpyTagErr), | |
1238 | E_P_AUTO(SDma1stDescErr), | |
1239 | E_P_AUTO(SDmaBaseErr), | |
1240 | E_P_AUTO(SDmaTailOutOfBoundErr), | |
1241 | E_P_AUTO(SDmaOutOfBoundErr), | |
1242 | E_P_AUTO(SDmaGenMismatchErr), | |
1243 | E_P_AUTO(SendBufMisuseErr), | |
1244 | E_P_AUTO(SendUnsupportedVLErr), | |
1245 | E_P_AUTO(SendUnexpectedPktNumErr), | |
1246 | E_P_AUTO(SendDroppedDataPktErr), | |
1247 | E_P_AUTO(SendDroppedSmpPktErr), | |
1248 | E_P_AUTO(SendPktLenErr), | |
1249 | E_P_AUTO(SendUnderRunErr), | |
1250 | E_P_AUTO(SendMaxPktLenErr), | |
1251 | E_P_AUTO(SendMinPktLenErr), | |
1252 | E_P_AUTO(RcvIBLostLinkErr), | |
1253 | E_P_AUTO(RcvHdrErr), | |
1254 | E_P_AUTO(RcvHdrLenErr), | |
1255 | E_P_AUTO(RcvBadTidErr), | |
1256 | E_P_AUTO(RcvBadVersionErr), | |
1257 | E_P_AUTO(RcvIBFlowErr), | |
1258 | E_P_AUTO(RcvEBPErr), | |
1259 | E_P_AUTO(RcvUnsupportedVLErr), | |
1260 | E_P_AUTO(RcvUnexpectedCharErr), | |
1261 | E_P_AUTO(RcvShortPktLenErr), | |
1262 | E_P_AUTO(RcvLongPktLenErr), | |
1263 | E_P_AUTO(RcvMaxPktLenErr), | |
1264 | E_P_AUTO(RcvMinPktLenErr), | |
1265 | E_P_AUTO(RcvICRCErr), | |
1266 | E_P_AUTO(RcvVCRCErr), | |
1267 | E_P_AUTO(RcvFormatErr), | |
e67306a3 | 1268 | { .mask = 0, .sz = 0 } |
f931551b RC |
1269 | }; |
1270 | ||
1271 | /* | |
1272 | * Below generates "auto-message" for interrupts not specific to any port or | |
1273 | * context | |
1274 | */ | |
1275 | #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \ | |
e67306a3 | 1276 | .msg = #fldname, .sz = sizeof(#fldname) } |
f931551b RC |
1277 | /* Below generates "auto-message" for interrupts specific to a port */ |
1278 | #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\ | |
1279 | SYM_LSB(IntMask, fldname##Mask##_0), \ | |
1280 | SYM_LSB(IntMask, fldname##Mask##_1)), \ | |
e67306a3 | 1281 | .msg = #fldname "_P", .sz = sizeof(#fldname "_P") } |
f931551b RC |
1282 | /* For some reason, the SerDesTrimDone bits are reversed */ |
1283 | #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\ | |
1284 | SYM_LSB(IntMask, fldname##Mask##_1), \ | |
1285 | SYM_LSB(IntMask, fldname##Mask##_0)), \ | |
e67306a3 | 1286 | .msg = #fldname "_P", .sz = sizeof(#fldname "_P") } |
f931551b RC |
1287 | /* |
1288 | * Below generates "auto-message" for interrupts specific to a context, | |
1289 | * with ctxt-number appended | |
1290 | */ | |
1291 | #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\ | |
1292 | SYM_LSB(IntMask, fldname##0IntMask), \ | |
1293 | SYM_LSB(IntMask, fldname##17IntMask)), \ | |
e67306a3 | 1294 | .msg = #fldname "_C", .sz = sizeof(#fldname "_C") } |
f931551b | 1295 | |
f931551b | 1296 | #define TXSYMPTOM_AUTO_P(fldname) \ |
e67306a3 MM |
1297 | { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \ |
1298 | .msg = #fldname, .sz = sizeof(#fldname) } | |
f931551b RC |
1299 | static const struct qib_hwerror_msgs hdrchk_msgs[] = { |
1300 | TXSYMPTOM_AUTO_P(NonKeyPacket), | |
1301 | TXSYMPTOM_AUTO_P(GRHFail), | |
1302 | TXSYMPTOM_AUTO_P(PkeyFail), | |
1303 | TXSYMPTOM_AUTO_P(QPFail), | |
1304 | TXSYMPTOM_AUTO_P(SLIDFail), | |
1305 | TXSYMPTOM_AUTO_P(RawIPV6), | |
1306 | TXSYMPTOM_AUTO_P(PacketTooSmall), | |
e67306a3 | 1307 | { .mask = 0, .sz = 0 } |
f931551b RC |
1308 | }; |
1309 | ||
1310 | #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */ | |
1311 | ||
1312 | /* | |
1313 | * Called when we might have an error that is specific to a particular | |
1314 | * PIO buffer, and may need to cancel that buffer, so it can be re-used, | |
1315 | * because we don't need to force the update of pioavail | |
1316 | */ | |
1317 | static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd) | |
1318 | { | |
1319 | struct qib_devdata *dd = ppd->dd; | |
1320 | u32 i; | |
1321 | int any; | |
1322 | u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; | |
1323 | u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG; | |
1324 | unsigned long sbuf[4]; | |
1325 | ||
1326 | /* | |
1327 | * It's possible that sendbuffererror could have bits set; might | |
1328 | * have already done this as a result of hardware error handling. | |
1329 | */ | |
1330 | any = 0; | |
1331 | for (i = 0; i < regcnt; ++i) { | |
1332 | sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i); | |
1333 | if (sbuf[i]) { | |
1334 | any = 1; | |
1335 | qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]); | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | if (any) | |
1340 | qib_disarm_piobufs_set(dd, sbuf, piobcnt); | |
1341 | } | |
1342 | ||
1343 | /* No txe_recover yet, if ever */ | |
1344 | ||
1345 | /* No decode__errors yet */ | |
1346 | static void err_decode(char *msg, size_t len, u64 errs, | |
1347 | const struct qib_hwerror_msgs *msp) | |
1348 | { | |
1349 | u64 these, lmask; | |
1350 | int took, multi, n = 0; | |
1351 | ||
e67306a3 | 1352 | while (errs && msp && msp->mask) { |
f931551b RC |
1353 | multi = (msp->mask & (msp->mask - 1)); |
1354 | while (errs & msp->mask) { | |
1355 | these = (errs & msp->mask); | |
1356 | lmask = (these & (these - 1)) ^ these; | |
1357 | if (len) { | |
1358 | if (n++) { | |
1359 | /* separate the strings */ | |
1360 | *msg++ = ','; | |
1361 | len--; | |
1362 | } | |
e67306a3 MM |
1363 | /* msp->sz counts the nul */ |
1364 | took = min_t(size_t, msp->sz - (size_t)1, len); | |
1365 | memcpy(msg, msp->msg, took); | |
f931551b RC |
1366 | len -= took; |
1367 | msg += took; | |
e67306a3 MM |
1368 | if (len) |
1369 | *msg = '\0'; | |
f931551b RC |
1370 | } |
1371 | errs &= ~lmask; | |
1372 | if (len && multi) { | |
1373 | /* More than one bit this mask */ | |
1374 | int idx = -1; | |
1375 | ||
1376 | while (lmask & msp->mask) { | |
1377 | ++idx; | |
1378 | lmask >>= 1; | |
1379 | } | |
1380 | took = scnprintf(msg, len, "_%d", idx); | |
1381 | len -= took; | |
1382 | msg += took; | |
1383 | } | |
1384 | } | |
1385 | ++msp; | |
1386 | } | |
1387 | /* If some bits are left, show in hex. */ | |
1388 | if (len && errs) | |
1389 | snprintf(msg, len, "%sMORE:%llX", n ? "," : "", | |
1390 | (unsigned long long) errs); | |
1391 | } | |
1392 | ||
1393 | /* only called if r1 set */ | |
1394 | static void flush_fifo(struct qib_pportdata *ppd) | |
1395 | { | |
1396 | struct qib_devdata *dd = ppd->dd; | |
1397 | u32 __iomem *piobuf; | |
1398 | u32 bufn; | |
1399 | u32 *hdr; | |
1400 | u64 pbc; | |
1401 | const unsigned hdrwords = 7; | |
261a4351 | 1402 | static struct ib_header ibhdr = { |
f931551b RC |
1403 | .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH), |
1404 | .lrh[1] = IB_LID_PERMISSIVE, | |
1405 | .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC), | |
1406 | .lrh[3] = IB_LID_PERMISSIVE, | |
1407 | .u.oth.bth[0] = cpu_to_be32( | |
1408 | (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY), | |
1409 | .u.oth.bth[1] = cpu_to_be32(0), | |
1410 | .u.oth.bth[2] = cpu_to_be32(0), | |
1411 | .u.oth.u.ud.deth[0] = cpu_to_be32(0), | |
1412 | .u.oth.u.ud.deth[1] = cpu_to_be32(0), | |
1413 | }; | |
1414 | ||
1415 | /* | |
1416 | * Send a dummy VL15 packet to flush the launch FIFO. | |
1417 | * This will not actually be sent since the TxeBypassIbc bit is set. | |
1418 | */ | |
1419 | pbc = PBC_7322_VL15_SEND | | |
1420 | (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) | | |
1421 | (hdrwords + SIZE_OF_CRC); | |
1422 | piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn); | |
1423 | if (!piobuf) | |
1424 | return; | |
1425 | writeq(pbc, piobuf); | |
1426 | hdr = (u32 *) &ibhdr; | |
1427 | if (dd->flags & QIB_PIO_FLUSH_WC) { | |
1428 | qib_flush_wc(); | |
1429 | qib_pio_copy(piobuf + 2, hdr, hdrwords - 1); | |
1430 | qib_flush_wc(); | |
1431 | __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1); | |
1432 | qib_flush_wc(); | |
1433 | } else | |
1434 | qib_pio_copy(piobuf + 2, hdr, hdrwords); | |
1435 | qib_sendbuf_done(dd, bufn); | |
1436 | } | |
1437 | ||
1438 | /* | |
1439 | * This is called with interrupts disabled and sdma_lock held. | |
1440 | */ | |
1441 | static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op) | |
1442 | { | |
1443 | struct qib_devdata *dd = ppd->dd; | |
1444 | u64 set_sendctrl = 0; | |
1445 | u64 clr_sendctrl = 0; | |
1446 | ||
1447 | if (op & QIB_SDMA_SENDCTRL_OP_ENABLE) | |
1448 | set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); | |
1449 | else | |
1450 | clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); | |
1451 | ||
1452 | if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE) | |
1453 | set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); | |
1454 | else | |
1455 | clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); | |
1456 | ||
1457 | if (op & QIB_SDMA_SENDCTRL_OP_HALT) | |
1458 | set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); | |
1459 | else | |
1460 | clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); | |
1461 | ||
1462 | if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) | |
1463 | set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | | |
1464 | SYM_MASK(SendCtrl_0, TxeAbortIbc) | | |
1465 | SYM_MASK(SendCtrl_0, TxeDrainRmFifo); | |
1466 | else | |
1467 | clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | | |
1468 | SYM_MASK(SendCtrl_0, TxeAbortIbc) | | |
1469 | SYM_MASK(SendCtrl_0, TxeDrainRmFifo); | |
1470 | ||
1471 | spin_lock(&dd->sendctrl_lock); | |
1472 | ||
1473 | /* If we are draining everything, block sends first */ | |
1474 | if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) { | |
1475 | ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); | |
1476 | qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); | |
1477 | qib_write_kreg(dd, kr_scratch, 0); | |
1478 | } | |
1479 | ||
1480 | ppd->p_sendctrl |= set_sendctrl; | |
1481 | ppd->p_sendctrl &= ~clr_sendctrl; | |
1482 | ||
1483 | if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP) | |
1484 | qib_write_kreg_port(ppd, krp_sendctrl, | |
1485 | ppd->p_sendctrl | | |
1486 | SYM_MASK(SendCtrl_0, SDmaCleanup)); | |
1487 | else | |
1488 | qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); | |
1489 | qib_write_kreg(dd, kr_scratch, 0); | |
1490 | ||
1491 | if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) { | |
1492 | ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); | |
1493 | qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); | |
1494 | qib_write_kreg(dd, kr_scratch, 0); | |
1495 | } | |
1496 | ||
1497 | spin_unlock(&dd->sendctrl_lock); | |
1498 | ||
1499 | if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) | |
1500 | flush_fifo(ppd); | |
1501 | } | |
1502 | ||
1503 | static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd) | |
1504 | { | |
1505 | __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned); | |
1506 | } | |
1507 | ||
1508 | static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd) | |
1509 | { | |
1510 | /* | |
1511 | * Set SendDmaLenGen and clear and set | |
1512 | * the MSB of the generation count to enable generation checking | |
1513 | * and load the internal generation counter. | |
1514 | */ | |
1515 | qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt); | |
1516 | qib_write_kreg_port(ppd, krp_senddmalengen, | |
1517 | ppd->sdma_descq_cnt | | |
1518 | (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB)); | |
1519 | } | |
1520 | ||
1521 | /* | |
1522 | * Must be called with sdma_lock held, or before init finished. | |
1523 | */ | |
1524 | static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail) | |
1525 | { | |
1526 | /* Commit writes to memory and advance the tail on the chip */ | |
1527 | wmb(); | |
1528 | ppd->sdma_descq_tail = tail; | |
1529 | qib_write_kreg_port(ppd, krp_senddmatail, tail); | |
1530 | } | |
1531 | ||
1532 | /* | |
1533 | * This is called with interrupts disabled and sdma_lock held. | |
1534 | */ | |
1535 | static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd) | |
1536 | { | |
1537 | /* | |
1538 | * Drain all FIFOs. | |
1539 | * The hardware doesn't require this but we do it so that verbs | |
1540 | * and user applications don't wait for link active to send stale | |
1541 | * data. | |
1542 | */ | |
1543 | sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH); | |
1544 | ||
1545 | qib_sdma_7322_setlengen(ppd); | |
1546 | qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */ | |
1547 | ppd->sdma_head_dma[0] = 0; | |
1548 | qib_7322_sdma_sendctrl(ppd, | |
1549 | ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP); | |
1550 | } | |
1551 | ||
1552 | #define DISABLES_SDMA ( \ | |
1553 | QIB_E_P_SDMAHALT | \ | |
1554 | QIB_E_P_SDMADESCADDRMISALIGN | \ | |
1555 | QIB_E_P_SDMAMISSINGDW | \ | |
1556 | QIB_E_P_SDMADWEN | \ | |
1557 | QIB_E_P_SDMARPYTAG | \ | |
1558 | QIB_E_P_SDMA1STDESC | \ | |
1559 | QIB_E_P_SDMABASE | \ | |
1560 | QIB_E_P_SDMATAILOUTOFBOUND | \ | |
1561 | QIB_E_P_SDMAOUTOFBOUND | \ | |
1562 | QIB_E_P_SDMAGENMISMATCH) | |
1563 | ||
1564 | static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs) | |
1565 | { | |
1566 | unsigned long flags; | |
1567 | struct qib_devdata *dd = ppd->dd; | |
1568 | ||
1569 | errs &= QIB_E_P_SDMAERRS; | |
b268e4db MM |
1570 | err_decode(ppd->cpspec->sdmamsgbuf, sizeof(ppd->cpspec->sdmamsgbuf), |
1571 | errs, qib_7322p_error_msgs); | |
f931551b RC |
1572 | |
1573 | if (errs & QIB_E_P_SDMAUNEXPDATA) | |
1574 | qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit, | |
1575 | ppd->port); | |
1576 | ||
1577 | spin_lock_irqsave(&ppd->sdma_lock, flags); | |
1578 | ||
0b3ddf38 DL |
1579 | if (errs != QIB_E_P_SDMAHALT) { |
1580 | /* SDMA errors have QIB_E_P_SDMAHALT and another bit set */ | |
1581 | qib_dev_porterr(dd, ppd->port, | |
1582 | "SDMA %s 0x%016llx %s\n", | |
1583 | qib_sdma_state_names[ppd->sdma_state.current_state], | |
1584 | errs, ppd->cpspec->sdmamsgbuf); | |
1585 | dump_sdma_7322_state(ppd); | |
1586 | } | |
1587 | ||
f931551b RC |
1588 | switch (ppd->sdma_state.current_state) { |
1589 | case qib_sdma_state_s00_hw_down: | |
1590 | break; | |
1591 | ||
1592 | case qib_sdma_state_s10_hw_start_up_wait: | |
1593 | if (errs & QIB_E_P_SDMAHALT) | |
1594 | __qib_sdma_process_event(ppd, | |
1595 | qib_sdma_event_e20_hw_started); | |
1596 | break; | |
1597 | ||
1598 | case qib_sdma_state_s20_idle: | |
1599 | break; | |
1600 | ||
1601 | case qib_sdma_state_s30_sw_clean_up_wait: | |
1602 | break; | |
1603 | ||
1604 | case qib_sdma_state_s40_hw_clean_up_wait: | |
1605 | if (errs & QIB_E_P_SDMAHALT) | |
1606 | __qib_sdma_process_event(ppd, | |
1607 | qib_sdma_event_e50_hw_cleaned); | |
1608 | break; | |
1609 | ||
1610 | case qib_sdma_state_s50_hw_halt_wait: | |
1611 | if (errs & QIB_E_P_SDMAHALT) | |
1612 | __qib_sdma_process_event(ppd, | |
1613 | qib_sdma_event_e60_hw_halted); | |
1614 | break; | |
1615 | ||
1616 | case qib_sdma_state_s99_running: | |
1617 | __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted); | |
1618 | __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted); | |
1619 | break; | |
1620 | } | |
1621 | ||
1622 | spin_unlock_irqrestore(&ppd->sdma_lock, flags); | |
1623 | } | |
1624 | ||
1625 | /* | |
1626 | * handle per-device errors (not per-port errors) | |
1627 | */ | |
1628 | static noinline void handle_7322_errors(struct qib_devdata *dd) | |
1629 | { | |
1630 | char *msg; | |
1631 | u64 iserr = 0; | |
1632 | u64 errs; | |
1633 | u64 mask; | |
f931551b RC |
1634 | |
1635 | qib_stats.sps_errints++; | |
1636 | errs = qib_read_kreg64(dd, kr_errstatus); | |
1637 | if (!errs) { | |
7fac3301 MM |
1638 | qib_devinfo(dd->pcidev, |
1639 | "device error interrupt, but no error bits set!\n"); | |
f931551b RC |
1640 | goto done; |
1641 | } | |
1642 | ||
1643 | /* don't report errors that are masked */ | |
1644 | errs &= dd->cspec->errormask; | |
1645 | msg = dd->cspec->emsgbuf; | |
1646 | ||
1647 | /* do these first, they are most important */ | |
1648 | if (errs & QIB_E_HARDWARE) { | |
1649 | *msg = '\0'; | |
041af0bb | 1650 | qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); |
66392615 | 1651 | } |
f931551b RC |
1652 | |
1653 | if (errs & QIB_E_SPKTERRS) { | |
1654 | qib_disarm_7322_senderrbufs(dd->pport); | |
1655 | qib_stats.sps_txerrs++; | |
1656 | } else if (errs & QIB_E_INVALIDADDR) | |
1657 | qib_stats.sps_txerrs++; | |
1658 | else if (errs & QIB_E_ARMLAUNCH) { | |
1659 | qib_stats.sps_txerrs++; | |
1660 | qib_disarm_7322_senderrbufs(dd->pport); | |
1661 | } | |
1662 | qib_write_kreg(dd, kr_errclear, errs); | |
1663 | ||
1664 | /* | |
1665 | * The ones we mask off are handled specially below | |
1666 | * or above. Also mask SDMADISABLED by default as it | |
1667 | * is too chatty. | |
1668 | */ | |
1669 | mask = QIB_E_HARDWARE; | |
1670 | *msg = '\0'; | |
1671 | ||
041af0bb | 1672 | err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask, |
f931551b RC |
1673 | qib_7322error_msgs); |
1674 | ||
1675 | /* | |
1676 | * Getting reset is a tragedy for all ports. Mark the device | |
1677 | * _and_ the ports as "offline" in way meaningful to each. | |
1678 | */ | |
1679 | if (errs & QIB_E_RESET) { | |
1680 | int pidx; | |
1681 | ||
7fac3301 MM |
1682 | qib_dev_err(dd, |
1683 | "Got reset, requires re-init (unload and reload driver)\n"); | |
f931551b RC |
1684 | dd->flags &= ~QIB_INITTED; /* needs re-init */ |
1685 | /* mark as having had error */ | |
1686 | *dd->devstatusp |= QIB_STATUS_HWERROR; | |
1687 | for (pidx = 0; pidx < dd->num_pports; ++pidx) | |
1688 | if (dd->pport[pidx].link_speed_supported) | |
1689 | *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF; | |
1690 | } | |
1691 | ||
1692 | if (*msg && iserr) | |
1693 | qib_dev_err(dd, "%s error\n", msg); | |
1694 | ||
1695 | /* | |
1696 | * If there were hdrq or egrfull errors, wake up any processes | |
1697 | * waiting in poll. We used to try to check which contexts had | |
1698 | * the overflow, but given the cost of that and the chip reads | |
1699 | * to support it, it's better to just wake everybody up if we | |
1700 | * get an overflow; waiters can poll again if it's not them. | |
1701 | */ | |
1702 | if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) { | |
1703 | qib_handle_urcv(dd, ~0U); | |
1704 | if (errs & ERR_MASK(RcvEgrFullErr)) | |
1705 | qib_stats.sps_buffull++; | |
1706 | else | |
1707 | qib_stats.sps_hdrfull++; | |
1708 | } | |
1709 | ||
1710 | done: | |
1711 | return; | |
1712 | } | |
1713 | ||
a23afb44 | 1714 | static void qib_error_tasklet(struct tasklet_struct *t) |
e67306a3 | 1715 | { |
a23afb44 | 1716 | struct qib_devdata *dd = from_tasklet(dd, t, error_tasklet); |
e67306a3 MM |
1717 | |
1718 | handle_7322_errors(dd); | |
1719 | qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); | |
1720 | } | |
1721 | ||
4037c92f | 1722 | static void reenable_chase(struct timer_list *t) |
f931551b | 1723 | { |
4037c92f KC |
1724 | struct qib_chippport_specific *cp = from_timer(cp, t, chase_timer); |
1725 | struct qib_pportdata *ppd = cp->ppd; | |
f931551b RC |
1726 | |
1727 | ppd->cpspec->chase_timer.expires = 0; | |
1728 | qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, | |
1729 | QLOGIC_IB_IBCC_LINKINITCMD_POLL); | |
1730 | } | |
1731 | ||
8482d5d1 MM |
1732 | static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow, |
1733 | u8 ibclt) | |
f931551b RC |
1734 | { |
1735 | ppd->cpspec->chase_end = 0; | |
1736 | ||
1737 | if (!qib_chase) | |
1738 | return; | |
1739 | ||
1740 | qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, | |
1741 | QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); | |
1742 | ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME; | |
1743 | add_timer(&ppd->cpspec->chase_timer); | |
1744 | } | |
1745 | ||
1746 | static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst) | |
1747 | { | |
1748 | u8 ibclt; | |
8482d5d1 | 1749 | unsigned long tnow; |
f931551b RC |
1750 | |
1751 | ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState); | |
1752 | ||
1753 | /* | |
1754 | * Detect and handle the state chase issue, where we can | |
1755 | * get stuck if we are unlucky on timing on both sides of | |
1756 | * the link. If we are, we disable, set a timer, and | |
1757 | * then re-enable. | |
1758 | */ | |
1759 | switch (ibclt) { | |
1760 | case IB_7322_LT_STATE_CFGRCVFCFG: | |
1761 | case IB_7322_LT_STATE_CFGWAITRMT: | |
1762 | case IB_7322_LT_STATE_TXREVLANES: | |
1763 | case IB_7322_LT_STATE_CFGENH: | |
8482d5d1 | 1764 | tnow = jiffies; |
f931551b | 1765 | if (ppd->cpspec->chase_end && |
8482d5d1 | 1766 | time_after(tnow, ppd->cpspec->chase_end)) |
f931551b RC |
1767 | disable_chase(ppd, tnow, ibclt); |
1768 | else if (!ppd->cpspec->chase_end) | |
1769 | ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME; | |
1770 | break; | |
1771 | default: | |
1772 | ppd->cpspec->chase_end = 0; | |
1773 | break; | |
1774 | } | |
1775 | ||
31264484 MH |
1776 | if (((ibclt >= IB_7322_LT_STATE_CFGTEST && |
1777 | ibclt <= IB_7322_LT_STATE_CFGWAITENH) || | |
1778 | ibclt == IB_7322_LT_STATE_LINKUP) && | |
f931551b RC |
1779 | (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) { |
1780 | force_h1(ppd); | |
1781 | ppd->cpspec->qdr_reforce = 1; | |
a0a234d4 MM |
1782 | if (!ppd->dd->cspec->r1) |
1783 | serdes_7322_los_enable(ppd, 0); | |
f931551b RC |
1784 | } else if (ppd->cpspec->qdr_reforce && |
1785 | (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) && | |
1786 | (ibclt == IB_7322_LT_STATE_CFGENH || | |
1787 | ibclt == IB_7322_LT_STATE_CFGIDLE || | |
1788 | ibclt == IB_7322_LT_STATE_LINKUP)) | |
1789 | force_h1(ppd); | |
1790 | ||
1791 | if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) && | |
1792 | ppd->link_speed_enabled == QIB_IB_QDR && | |
1793 | (ibclt == IB_7322_LT_STATE_CFGTEST || | |
1794 | ibclt == IB_7322_LT_STATE_CFGENH || | |
1795 | (ibclt >= IB_7322_LT_STATE_POLLACTIVE && | |
1796 | ibclt <= IB_7322_LT_STATE_SLEEPQUIET))) | |
1797 | adj_tx_serdes(ppd); | |
1798 | ||
a0a234d4 MM |
1799 | if (ibclt != IB_7322_LT_STATE_LINKUP) { |
1800 | u8 ltstate = qib_7322_phys_portstate(ibcst); | |
1801 | u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, | |
1802 | LinkTrainingState); | |
1803 | if (!ppd->dd->cspec->r1 && | |
1804 | pibclt == IB_7322_LT_STATE_LINKUP && | |
1805 | ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER && | |
1806 | ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN && | |
1807 | ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && | |
1808 | ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) | |
1809 | /* If the link went down (but no into recovery, | |
1810 | * turn LOS back on */ | |
1811 | serdes_7322_los_enable(ppd, 1); | |
1812 | if (!ppd->cpspec->qdr_dfe_on && | |
1813 | ibclt <= IB_7322_LT_STATE_SLEEPQUIET) { | |
1814 | ppd->cpspec->qdr_dfe_on = 1; | |
1815 | ppd->cpspec->qdr_dfe_time = 0; | |
1816 | /* On link down, reenable QDR adaptation */ | |
1817 | qib_write_kreg_port(ppd, krp_static_adapt_dis(2), | |
1818 | ppd->dd->cspec->r1 ? | |
1819 | QDR_STATIC_ADAPT_DOWN_R1 : | |
1820 | QDR_STATIC_ADAPT_DOWN); | |
7fac3301 MM |
1821 | pr_info( |
1822 | "IB%u:%u re-enabled QDR adaptation ibclt %x\n", | |
1823 | ppd->dd->unit, ppd->port, ibclt); | |
a0a234d4 | 1824 | } |
f931551b RC |
1825 | } |
1826 | } | |
1827 | ||
f2d255a0 MM |
1828 | static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32); |
1829 | ||
f931551b RC |
1830 | /* |
1831 | * This is per-pport error handling. | |
1832 | * will likely get it's own MSIx interrupt (one for each port, | |
1833 | * although just a single handler). | |
1834 | */ | |
1835 | static noinline void handle_7322_p_errors(struct qib_pportdata *ppd) | |
1836 | { | |
1837 | char *msg; | |
1838 | u64 ignore_this_time = 0, iserr = 0, errs, fmask; | |
1839 | struct qib_devdata *dd = ppd->dd; | |
1840 | ||
1841 | /* do this as soon as possible */ | |
1842 | fmask = qib_read_kreg64(dd, kr_act_fmask); | |
1843 | if (!fmask) | |
1844 | check_7322_rxe_status(ppd); | |
1845 | ||
1846 | errs = qib_read_kreg_port(ppd, krp_errstatus); | |
1847 | if (!errs) | |
1848 | qib_devinfo(dd->pcidev, | |
1849 | "Port%d error interrupt, but no error bits set!\n", | |
1850 | ppd->port); | |
1851 | if (!fmask) | |
1852 | errs &= ~QIB_E_P_IBSTATUSCHANGED; | |
1853 | if (!errs) | |
1854 | goto done; | |
1855 | ||
1856 | msg = ppd->cpspec->epmsgbuf; | |
1857 | *msg = '\0'; | |
1858 | ||
1859 | if (errs & ~QIB_E_P_BITSEXTANT) { | |
041af0bb | 1860 | err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), |
f931551b RC |
1861 | errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs); |
1862 | if (!*msg) | |
041af0bb | 1863 | snprintf(msg, sizeof(ppd->cpspec->epmsgbuf), |
f931551b | 1864 | "no others"); |
7fac3301 MM |
1865 | qib_dev_porterr(dd, ppd->port, |
1866 | "error interrupt with unknown errors 0x%016Lx set (and %s)\n", | |
1867 | (errs & ~QIB_E_P_BITSEXTANT), msg); | |
f931551b RC |
1868 | *msg = '\0'; |
1869 | } | |
1870 | ||
1871 | if (errs & QIB_E_P_SHDR) { | |
1872 | u64 symptom; | |
1873 | ||
1874 | /* determine cause, then write to clear */ | |
1875 | symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom); | |
1876 | qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0); | |
041af0bb | 1877 | err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), symptom, |
f931551b RC |
1878 | hdrchk_msgs); |
1879 | *msg = '\0'; | |
1880 | /* senderrbuf cleared in SPKTERRS below */ | |
1881 | } | |
1882 | ||
1883 | if (errs & QIB_E_P_SPKTERRS) { | |
1884 | if ((errs & QIB_E_P_LINK_PKTERRS) && | |
1885 | !(ppd->lflags & QIBL_LINKACTIVE)) { | |
1886 | /* | |
1887 | * This can happen when trying to bring the link | |
1888 | * up, but the IB link changes state at the "wrong" | |
1889 | * time. The IB logic then complains that the packet | |
1890 | * isn't valid. We don't want to confuse people, so | |
1891 | * we just don't print them, except at debug | |
1892 | */ | |
041af0bb | 1893 | err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), |
f931551b RC |
1894 | (errs & QIB_E_P_LINK_PKTERRS), |
1895 | qib_7322p_error_msgs); | |
1896 | *msg = '\0'; | |
1897 | ignore_this_time = errs & QIB_E_P_LINK_PKTERRS; | |
1898 | } | |
1899 | qib_disarm_7322_senderrbufs(ppd); | |
1900 | } else if ((errs & QIB_E_P_LINK_PKTERRS) && | |
1901 | !(ppd->lflags & QIBL_LINKACTIVE)) { | |
1902 | /* | |
1903 | * This can happen when SMA is trying to bring the link | |
1904 | * up, but the IB link changes state at the "wrong" time. | |
1905 | * The IB logic then complains that the packet isn't | |
1906 | * valid. We don't want to confuse people, so we just | |
1907 | * don't print them, except at debug | |
1908 | */ | |
041af0bb | 1909 | err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), errs, |
f931551b RC |
1910 | qib_7322p_error_msgs); |
1911 | ignore_this_time = errs & QIB_E_P_LINK_PKTERRS; | |
1912 | *msg = '\0'; | |
1913 | } | |
1914 | ||
1915 | qib_write_kreg_port(ppd, krp_errclear, errs); | |
1916 | ||
1917 | errs &= ~ignore_this_time; | |
1918 | if (!errs) | |
1919 | goto done; | |
1920 | ||
1921 | if (errs & QIB_E_P_RPKTERRS) | |
1922 | qib_stats.sps_rcverrs++; | |
1923 | if (errs & QIB_E_P_SPKTERRS) | |
1924 | qib_stats.sps_txerrs++; | |
1925 | ||
1926 | iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS); | |
1927 | ||
1928 | if (errs & QIB_E_P_SDMAERRS) | |
1929 | sdma_7322_p_errors(ppd, errs); | |
1930 | ||
1931 | if (errs & QIB_E_P_IBSTATUSCHANGED) { | |
1932 | u64 ibcs; | |
1933 | u8 ltstate; | |
1934 | ||
1935 | ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a); | |
1936 | ltstate = qib_7322_phys_portstate(ibcs); | |
1937 | ||
1938 | if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) | |
1939 | handle_serdes_issues(ppd, ibcs); | |
1940 | if (!(ppd->cpspec->ibcctrl_a & | |
1941 | SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) { | |
1942 | /* | |
1943 | * We got our interrupt, so init code should be | |
1944 | * happy and not try alternatives. Now squelch | |
1945 | * other "chatter" from link-negotiation (pre Init) | |
1946 | */ | |
1947 | ppd->cpspec->ibcctrl_a |= | |
1948 | SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); | |
1949 | qib_write_kreg_port(ppd, krp_ibcctrl_a, | |
1950 | ppd->cpspec->ibcctrl_a); | |
1951 | } | |
1952 | ||
1953 | /* Update our picture of width and speed from chip */ | |
1954 | ppd->link_width_active = | |
1955 | (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ? | |
1956 | IB_WIDTH_4X : IB_WIDTH_1X; | |
1957 | ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0, | |
1958 | LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs & | |
1959 | SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ? | |
1960 | QIB_IB_DDR : QIB_IB_SDR; | |
1961 | ||
1962 | if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate != | |
1963 | IB_PHYSPORTSTATE_DISABLED) | |
1964 | qib_set_ib_7322_lstate(ppd, 0, | |
1965 | QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); | |
d70585f7 | 1966 | else |
f931551b RC |
1967 | /* |
1968 | * Since going into a recovery state causes the link | |
1969 | * state to go down and since recovery is transitory, | |
1970 | * it is better if we "miss" ever seeing the link | |
1971 | * training state go into recovery (i.e., ignore this | |
1972 | * transition for link state special handling purposes) | |
1973 | * without updating lastibcstat. | |
1974 | */ | |
1975 | if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER && | |
1976 | ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN && | |
1977 | ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && | |
1978 | ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) | |
1979 | qib_handle_e_ibstatuschanged(ppd, ibcs); | |
1980 | } | |
1981 | if (*msg && iserr) | |
1982 | qib_dev_porterr(dd, ppd->port, "%s error\n", msg); | |
1983 | ||
1984 | if (ppd->state_wanted & ppd->lflags) | |
1985 | wake_up_interruptible(&ppd->state_wait); | |
1986 | done: | |
1987 | return; | |
1988 | } | |
1989 | ||
1990 | /* enable/disable chip from delivering interrupts */ | |
1991 | static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable) | |
1992 | { | |
1993 | if (enable) { | |
1994 | if (dd->flags & QIB_BADINTR) | |
1995 | return; | |
1996 | qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); | |
1997 | /* cause any pending enabled interrupts to be re-delivered */ | |
1998 | qib_write_kreg(dd, kr_intclear, 0ULL); | |
1999 | if (dd->cspec->num_msix_entries) { | |
2000 | /* and same for MSIx */ | |
2001 | u64 val = qib_read_kreg64(dd, kr_intgranted); | |
da12c1f6 | 2002 | |
f931551b RC |
2003 | if (val) |
2004 | qib_write_kreg(dd, kr_intgranted, val); | |
2005 | } | |
2006 | } else | |
2007 | qib_write_kreg(dd, kr_intmask, 0ULL); | |
2008 | } | |
2009 | ||
2010 | /* | |
2011 | * Try to cleanup as much as possible for anything that might have gone | |
2012 | * wrong while in freeze mode, such as pio buffers being written by user | |
2013 | * processes (causing armlaunch), send errors due to going into freeze mode, | |
2014 | * etc., and try to avoid causing extra interrupts while doing so. | |
2015 | * Forcibly update the in-memory pioavail register copies after cleanup | |
2016 | * because the chip won't do it while in freeze mode (the register values | |
2017 | * themselves are kept correct). | |
2018 | * Make sure that we don't lose any important interrupts by using the chip | |
2019 | * feature that says that writing 0 to a bit in *clear that is set in | |
2020 | * *status will cause an interrupt to be generated again (if allowed by | |
2021 | * the *mask value). | |
2022 | * This is in chip-specific code because of all of the register accesses, | |
2023 | * even though the details are similar on most chips. | |
2024 | */ | |
2025 | static void qib_7322_clear_freeze(struct qib_devdata *dd) | |
2026 | { | |
2027 | int pidx; | |
2028 | ||
2029 | /* disable error interrupts, to avoid confusion */ | |
2030 | qib_write_kreg(dd, kr_errmask, 0ULL); | |
2031 | ||
2032 | for (pidx = 0; pidx < dd->num_pports; ++pidx) | |
2033 | if (dd->pport[pidx].link_speed_supported) | |
2034 | qib_write_kreg_port(dd->pport + pidx, krp_errmask, | |
2035 | 0ULL); | |
2036 | ||
b8a14f33 | 2037 | /* also disable interrupts; errormask is sometimes overwritten */ |
f931551b RC |
2038 | qib_7322_set_intr_state(dd, 0); |
2039 | ||
2040 | /* clear the freeze, and be sure chip saw it */ | |
2041 | qib_write_kreg(dd, kr_control, dd->control); | |
2042 | qib_read_kreg32(dd, kr_scratch); | |
2043 | ||
2044 | /* | |
2045 | * Force new interrupt if any hwerr, error or interrupt bits are | |
2046 | * still set, and clear "safe" send packet errors related to freeze | |
2047 | * and cancelling sends. Re-enable error interrupts before possible | |
2048 | * force of re-interrupt on pending interrupts. | |
2049 | */ | |
2050 | qib_write_kreg(dd, kr_hwerrclear, 0ULL); | |
2051 | qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE); | |
2052 | qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); | |
2053 | /* We need to purge per-port errs and reset mask, too */ | |
2054 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
2055 | if (!dd->pport[pidx].link_speed_supported) | |
2056 | continue; | |
2057 | qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull); | |
2058 | qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull); | |
2059 | } | |
2060 | qib_7322_set_intr_state(dd, 1); | |
2061 | } | |
2062 | ||
2063 | /* no error handling to speak of */ | |
2064 | /** | |
2065 | * qib_7322_handle_hwerrors - display hardware errors. | |
2066 | * @dd: the qlogic_ib device | |
2067 | * @msg: the output buffer | |
2068 | * @msgl: the size of the output buffer | |
2069 | * | |
2070 | * Use same msg buffer as regular errors to avoid excessive stack | |
2071 | * use. Most hardware errors are catastrophic, but for right now, | |
2072 | * we'll print them and continue. We reuse the same message buffer as | |
2073 | * qib_handle_errors() to avoid excessive stack usage. | |
2074 | */ | |
2075 | static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg, | |
2076 | size_t msgl) | |
2077 | { | |
2078 | u64 hwerrs; | |
2079 | u32 ctrl; | |
2080 | int isfatal = 0; | |
2081 | ||
2082 | hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); | |
2083 | if (!hwerrs) | |
2084 | goto bail; | |
2085 | if (hwerrs == ~0ULL) { | |
7fac3301 MM |
2086 | qib_dev_err(dd, |
2087 | "Read of hardware error status failed (all bits set); ignoring\n"); | |
f931551b RC |
2088 | goto bail; |
2089 | } | |
2090 | qib_stats.sps_hwerrs++; | |
2091 | ||
2092 | /* Always clear the error status register, except BIST fail */ | |
2093 | qib_write_kreg(dd, kr_hwerrclear, hwerrs & | |
2094 | ~HWE_MASK(PowerOnBISTFailed)); | |
2095 | ||
2096 | hwerrs &= dd->cspec->hwerrmask; | |
2097 | ||
2098 | /* no EEPROM logging, yet */ | |
2099 | ||
2100 | if (hwerrs) | |
7fac3301 MM |
2101 | qib_devinfo(dd->pcidev, |
2102 | "Hardware error: hwerr=0x%llx (cleared)\n", | |
2103 | (unsigned long long) hwerrs); | |
f931551b RC |
2104 | |
2105 | ctrl = qib_read_kreg32(dd, kr_control); | |
2106 | if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) { | |
2107 | /* | |
2108 | * No recovery yet... | |
2109 | */ | |
2110 | if ((hwerrs & ~HWE_MASK(LATriggered)) || | |
2111 | dd->cspec->stay_in_freeze) { | |
2112 | /* | |
2113 | * If any set that we aren't ignoring only make the | |
2114 | * complaint once, in case it's stuck or recurring, | |
2115 | * and we get here multiple times | |
2116 | * Force link down, so switch knows, and | |
2117 | * LEDs are turned off. | |
2118 | */ | |
2119 | if (dd->flags & QIB_INITTED) | |
2120 | isfatal = 1; | |
2121 | } else | |
2122 | qib_7322_clear_freeze(dd); | |
2123 | } | |
2124 | ||
2125 | if (hwerrs & HWE_MASK(PowerOnBISTFailed)) { | |
2126 | isfatal = 1; | |
2c34bb6d | 2127 | strscpy(msg, |
7fac3301 MM |
2128 | "[Memory BIST test failed, InfiniPath hardware unusable]", |
2129 | msgl); | |
f931551b RC |
2130 | /* ignore from now on, so disable until driver reloaded */ |
2131 | dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); | |
2132 | qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); | |
2133 | } | |
2134 | ||
2135 | err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs); | |
2136 | ||
2137 | /* Ignore esoteric PLL failures et al. */ | |
2138 | ||
2139 | qib_dev_err(dd, "%s hardware error\n", msg); | |
2140 | ||
0b3ddf38 DL |
2141 | if (hwerrs & |
2142 | (SYM_MASK(HwErrMask, SDmaMemReadErrMask_0) | | |
2143 | SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) { | |
2144 | int pidx = 0; | |
2145 | int err; | |
2146 | unsigned long flags; | |
2147 | struct qib_pportdata *ppd = dd->pport; | |
da12c1f6 | 2148 | |
0b3ddf38 DL |
2149 | for (; pidx < dd->num_pports; ++pidx, ppd++) { |
2150 | err = 0; | |
2151 | if (pidx == 0 && (hwerrs & | |
2152 | SYM_MASK(HwErrMask, SDmaMemReadErrMask_0))) | |
2153 | err++; | |
2154 | if (pidx == 1 && (hwerrs & | |
2155 | SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) | |
2156 | err++; | |
2157 | if (err) { | |
2158 | spin_lock_irqsave(&ppd->sdma_lock, flags); | |
2159 | dump_sdma_7322_state(ppd); | |
2160 | spin_unlock_irqrestore(&ppd->sdma_lock, flags); | |
2161 | } | |
2162 | } | |
2163 | } | |
2164 | ||
f931551b | 2165 | if (isfatal && !dd->diag_client) { |
7fac3301 MM |
2166 | qib_dev_err(dd, |
2167 | "Fatal Hardware Error, no longer usable, SN %.16s\n", | |
2168 | dd->serial); | |
f931551b RC |
2169 | /* |
2170 | * for /sys status file and user programs to print; if no | |
2171 | * trailing brace is copied, we'll know it was truncated. | |
2172 | */ | |
2173 | if (dd->freezemsg) | |
2174 | snprintf(dd->freezemsg, dd->freezelen, | |
2175 | "{%s}", msg); | |
2176 | qib_disable_after_error(dd); | |
2177 | } | |
2178 | bail:; | |
2179 | } | |
2180 | ||
2181 | /** | |
2182 | * qib_7322_init_hwerrors - enable hardware errors | |
2183 | * @dd: the qlogic_ib device | |
2184 | * | |
2185 | * now that we have finished initializing everything that might reasonably | |
2186 | * cause a hardware error, and cleared those errors bits as they occur, | |
2187 | * we can enable hardware errors in the mask (potentially enabling | |
2188 | * freeze mode), and enable hardware errors as errors (along with | |
2189 | * everything else) in errormask | |
2190 | */ | |
2191 | static void qib_7322_init_hwerrors(struct qib_devdata *dd) | |
2192 | { | |
2193 | int pidx; | |
2194 | u64 extsval; | |
2195 | ||
2196 | extsval = qib_read_kreg64(dd, kr_extstatus); | |
2197 | if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED | | |
2198 | QIB_EXTS_MEMBIST_ENDTEST))) | |
2199 | qib_dev_err(dd, "MemBIST did not complete!\n"); | |
2200 | ||
2201 | /* never clear BIST failure, so reported on each driver load */ | |
2202 | qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed)); | |
2203 | qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); | |
2204 | ||
2205 | /* clear all */ | |
2206 | qib_write_kreg(dd, kr_errclear, ~0ULL); | |
2207 | /* enable errors that are masked, at least this first time. */ | |
2208 | qib_write_kreg(dd, kr_errmask, ~0ULL); | |
2209 | dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); | |
2210 | for (pidx = 0; pidx < dd->num_pports; ++pidx) | |
2211 | if (dd->pport[pidx].link_speed_supported) | |
2212 | qib_write_kreg_port(dd->pport + pidx, krp_errmask, | |
2213 | ~0ULL); | |
2214 | } | |
2215 | ||
2216 | /* | |
2217 | * Disable and enable the armlaunch error. Used for PIO bandwidth testing | |
2218 | * on chips that are count-based, rather than trigger-based. There is no | |
2219 | * reference counting, but that's also fine, given the intended use. | |
2220 | * Only chip-specific because it's all register accesses | |
2221 | */ | |
2222 | static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable) | |
2223 | { | |
2224 | if (enable) { | |
2225 | qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH); | |
2226 | dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; | |
2227 | } else | |
2228 | dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; | |
2229 | qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); | |
2230 | } | |
2231 | ||
2232 | /* | |
2233 | * Formerly took parameter <which> in pre-shifted, | |
2234 | * pre-merged form with LinkCmd and LinkInitCmd | |
2235 | * together, and assuming the zero was NOP. | |
2236 | */ | |
2237 | static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, | |
2238 | u16 linitcmd) | |
2239 | { | |
2240 | u64 mod_wd; | |
2241 | struct qib_devdata *dd = ppd->dd; | |
2242 | unsigned long flags; | |
2243 | ||
2244 | if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) { | |
2245 | /* | |
2246 | * If we are told to disable, note that so link-recovery | |
2247 | * code does not attempt to bring us back up. | |
2248 | * Also reset everything that we can, so we start | |
2249 | * completely clean when re-enabled (before we | |
2250 | * actually issue the disable to the IBC) | |
2251 | */ | |
2252 | qib_7322_mini_pcs_reset(ppd); | |
2253 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
2254 | ppd->lflags |= QIBL_IB_LINK_DISABLED; | |
2255 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
2256 | } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) { | |
2257 | /* | |
2258 | * Any other linkinitcmd will lead to LINKDOWN and then | |
2259 | * to INIT (if all is well), so clear flag to let | |
2260 | * link-recovery code attempt to bring us back up. | |
2261 | */ | |
2262 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
2263 | ppd->lflags &= ~QIBL_IB_LINK_DISABLED; | |
2264 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
2265 | /* | |
2266 | * Clear status change interrupt reduction so the | |
2267 | * new state is seen. | |
2268 | */ | |
2269 | ppd->cpspec->ibcctrl_a &= | |
2270 | ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); | |
2271 | } | |
2272 | ||
2273 | mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) | | |
2274 | (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); | |
2275 | ||
2276 | qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a | | |
2277 | mod_wd); | |
2278 | /* write to chip to prevent back-to-back writes of ibc reg */ | |
2279 | qib_write_kreg(dd, kr_scratch, 0); | |
2280 | ||
2281 | } | |
2282 | ||
2283 | /* | |
2284 | * The total RCV buffer memory is 64KB, used for both ports, and is | |
2285 | * in units of 64 bytes (same as IB flow control credit unit). | |
2286 | * The consumedVL unit in the same registers are in 32 byte units! | |
2287 | * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks, | |
2288 | * and we can therefore allocate just 9 IB credits for 2 VL15 packets | |
2289 | * in krp_rxcreditvl15, rather than 10. | |
2290 | */ | |
2291 | #define RCV_BUF_UNITSZ 64 | |
2292 | #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports)) | |
2293 | ||
2294 | static void set_vls(struct qib_pportdata *ppd) | |
2295 | { | |
2296 | int i, numvls, totcred, cred_vl, vl0extra; | |
2297 | struct qib_devdata *dd = ppd->dd; | |
2298 | u64 val; | |
2299 | ||
2300 | numvls = qib_num_vls(ppd->vls_operational); | |
2301 | ||
2302 | /* | |
2303 | * Set up per-VL credits. Below is kluge based on these assumptions: | |
2304 | * 1) port is disabled at the time early_init is called. | |
2305 | * 2) give VL15 17 credits, for two max-plausible packets. | |
2306 | * 3) Give VL0-N the rest, with any rounding excess used for VL0 | |
2307 | */ | |
2308 | /* 2 VL15 packets @ 288 bytes each (including IB headers) */ | |
2309 | totcred = NUM_RCV_BUF_UNITS(dd); | |
2310 | cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ; | |
2311 | totcred -= cred_vl; | |
2312 | qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl); | |
2313 | cred_vl = totcred / numvls; | |
2314 | vl0extra = totcred - cred_vl * numvls; | |
2315 | qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra); | |
2316 | for (i = 1; i < numvls; i++) | |
2317 | qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl); | |
2318 | for (; i < 8; i++) /* no buffer space for other VLs */ | |
2319 | qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0); | |
2320 | ||
2321 | /* Notify IBC that credits need to be recalculated */ | |
2322 | val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); | |
2323 | val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); | |
2324 | qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); | |
2325 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
2326 | val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); | |
2327 | qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); | |
2328 | ||
2329 | for (i = 0; i < numvls; i++) | |
2330 | val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i); | |
2331 | val = qib_read_kreg_port(ppd, krp_rxcreditvl15); | |
2332 | ||
2333 | /* Change the number of operational VLs */ | |
2334 | ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a & | |
2335 | ~SYM_MASK(IBCCtrlA_0, NumVLane)) | | |
2336 | ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane)); | |
2337 | qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); | |
2338 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
2339 | } | |
2340 | ||
2341 | /* | |
2342 | * The code that deals with actual SerDes is in serdes_7322_init(). | |
2343 | * Compared to the code for iba7220, it is minimal. | |
2344 | */ | |
2345 | static int serdes_7322_init(struct qib_pportdata *ppd); | |
2346 | ||
2347 | /** | |
2348 | * qib_7322_bringup_serdes - bring up the serdes | |
2349 | * @ppd: physical port on the qlogic_ib device | |
2350 | */ | |
2351 | static int qib_7322_bringup_serdes(struct qib_pportdata *ppd) | |
2352 | { | |
2353 | struct qib_devdata *dd = ppd->dd; | |
2354 | u64 val, guid, ibc; | |
2355 | unsigned long flags; | |
f931551b RC |
2356 | |
2357 | /* | |
2358 | * SerDes model not in Pd, but still need to | |
2359 | * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere | |
2360 | * eventually. | |
2361 | */ | |
2362 | /* Put IBC in reset, sends disabled (should be in reset already) */ | |
2363 | ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); | |
2364 | qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); | |
2365 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
2366 | ||
2f75e12c MM |
2367 | /* ensure previous Tx parameters are not still forced */ |
2368 | qib_write_kreg_port(ppd, krp_tx_deemph_override, | |
2369 | SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
2370 | reset_tx_deemphasis_override)); | |
2371 | ||
f931551b RC |
2372 | if (qib_compat_ddr_negotiate) { |
2373 | ppd->cpspec->ibdeltainprog = 1; | |
2374 | ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, | |
2375 | crp_ibsymbolerr); | |
2376 | ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, | |
2377 | crp_iblinkerrrecov); | |
2378 | } | |
2379 | ||
2380 | /* flowcontrolwatermark is in units of KBytes */ | |
2381 | ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark); | |
2382 | /* | |
2383 | * Flow control is sent this often, even if no changes in | |
2384 | * buffer space occur. Units are 128ns for this chip. | |
2385 | * Set to 3usec. | |
2386 | */ | |
2387 | ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod); | |
2388 | /* max error tolerance */ | |
2389 | ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold); | |
2390 | /* IB credit flow control. */ | |
2391 | ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold); | |
2392 | /* | |
2393 | * set initial max size pkt IBC will send, including ICRC; it's the | |
2394 | * PIO buffer size in dwords, less 1; also see qib_set_mtu() | |
2395 | */ | |
2396 | ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << | |
2397 | SYM_LSB(IBCCtrlA_0, MaxPktLen); | |
2398 | ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */ | |
2399 | ||
f931551b RC |
2400 | /* |
2401 | * Reset the PCS interface to the serdes (and also ibc, which is still | |
2402 | * in reset from above). Writes new value of ibcctrl_a as last step. | |
2403 | */ | |
2404 | qib_7322_mini_pcs_reset(ppd); | |
f931551b RC |
2405 | |
2406 | if (!ppd->cpspec->ibcctrl_b) { | |
2407 | unsigned lse = ppd->link_speed_enabled; | |
2408 | ||
2409 | /* | |
2410 | * Not on re-init after reset, establish shadow | |
2411 | * and force initial config. | |
2412 | */ | |
2413 | ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd, | |
2414 | krp_ibcctrl_b); | |
2415 | ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR | | |
2416 | IBA7322_IBC_SPEED_DDR | | |
2417 | IBA7322_IBC_SPEED_SDR | | |
2418 | IBA7322_IBC_WIDTH_AUTONEG | | |
2419 | SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED)); | |
2420 | if (lse & (lse - 1)) /* Muliple speeds enabled */ | |
2421 | ppd->cpspec->ibcctrl_b |= | |
2422 | (lse << IBA7322_IBC_SPEED_LSB) | | |
2423 | IBA7322_IBC_IBTA_1_2_MASK | | |
2424 | IBA7322_IBC_MAX_SPEED_MASK; | |
2425 | else | |
2426 | ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ? | |
2427 | IBA7322_IBC_SPEED_QDR | | |
2428 | IBA7322_IBC_IBTA_1_2_MASK : | |
2429 | (lse == QIB_IB_DDR) ? | |
2430 | IBA7322_IBC_SPEED_DDR : | |
2431 | IBA7322_IBC_SPEED_SDR; | |
2432 | if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) == | |
2433 | (IB_WIDTH_1X | IB_WIDTH_4X)) | |
2434 | ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG; | |
2435 | else | |
2436 | ppd->cpspec->ibcctrl_b |= | |
2437 | ppd->link_width_enabled == IB_WIDTH_4X ? | |
2438 | IBA7322_IBC_WIDTH_4X_ONLY : | |
2439 | IBA7322_IBC_WIDTH_1X_ONLY; | |
2440 | ||
2441 | /* always enable these on driver reload, not sticky */ | |
2442 | ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK | | |
2443 | IBA7322_IBC_HRTBT_MASK); | |
2444 | } | |
2445 | qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); | |
2446 | ||
2447 | /* setup so we have more time at CFGTEST to change H1 */ | |
2448 | val = qib_read_kreg_port(ppd, krp_ibcctrl_c); | |
2449 | val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH); | |
2450 | val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH); | |
2451 | qib_write_kreg_port(ppd, krp_ibcctrl_c, val); | |
2452 | ||
2453 | serdes_7322_init(ppd); | |
2454 | ||
2455 | guid = be64_to_cpu(ppd->guid); | |
2456 | if (!guid) { | |
2457 | if (dd->base_guid) | |
2458 | guid = be64_to_cpu(dd->base_guid) + ppd->port - 1; | |
2459 | ppd->guid = cpu_to_be64(guid); | |
2460 | } | |
2461 | ||
2462 | qib_write_kreg_port(ppd, krp_hrtbt_guid, guid); | |
2463 | /* write to chip to prevent back-to-back writes of ibc reg */ | |
2464 | qib_write_kreg(dd, kr_scratch, 0); | |
2465 | ||
2466 | /* Enable port */ | |
2467 | ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn); | |
2468 | set_vls(ppd); | |
2469 | ||
8ee887d7 MM |
2470 | /* initially come up DISABLED, without sending anything. */ |
2471 | val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << | |
2472 | QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); | |
2473 | qib_write_kreg_port(ppd, krp_ibcctrl_a, val); | |
2474 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
2475 | /* clear the linkinit cmds */ | |
2476 | ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd); | |
2477 | ||
f931551b RC |
2478 | /* be paranoid against later code motion, etc. */ |
2479 | spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); | |
2480 | ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable); | |
2481 | qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); | |
2482 | spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); | |
2483 | ||
2484 | /* Also enable IBSTATUSCHG interrupt. */ | |
2485 | val = qib_read_kreg_port(ppd, krp_errmask); | |
2486 | qib_write_kreg_port(ppd, krp_errmask, | |
2487 | val | ERR_MASK_N(IBStatusChanged)); | |
2488 | ||
2489 | /* Always zero until we start messing with SerDes for real */ | |
4f953089 | 2490 | return 0; |
f931551b RC |
2491 | } |
2492 | ||
2493 | /** | |
ae360f41 | 2494 | * qib_7322_mini_quiet_serdes - set serdes to txidle |
a8a47b16 | 2495 | * @ppd: the qlogic_ib device |
f931551b RC |
2496 | * Called when driver is being unloaded |
2497 | */ | |
2498 | static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd) | |
2499 | { | |
2500 | u64 val; | |
2501 | unsigned long flags; | |
2502 | ||
2503 | qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); | |
2504 | ||
2505 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
2506 | ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; | |
2507 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
2508 | wake_up(&ppd->cpspec->autoneg_wait); | |
f0626710 | 2509 | cancel_delayed_work_sync(&ppd->cpspec->autoneg_work); |
f931551b | 2510 | if (ppd->dd->cspec->r1) |
f0626710 | 2511 | cancel_delayed_work_sync(&ppd->cpspec->ipg_work); |
f931551b RC |
2512 | |
2513 | ppd->cpspec->chase_end = 0; | |
4037c92f | 2514 | if (ppd->cpspec->chase_timer.function) /* if initted */ |
f931551b RC |
2515 | del_timer_sync(&ppd->cpspec->chase_timer); |
2516 | ||
2517 | /* | |
2518 | * Despite the name, actually disables IBC as well. Do it when | |
2519 | * we are as sure as possible that no more packets can be | |
2520 | * received, following the down and the PCS reset. | |
2521 | * The actual disabling happens in qib_7322_mini_pci_reset(), | |
2522 | * along with the PCS being reset. | |
2523 | */ | |
2524 | ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); | |
2525 | qib_7322_mini_pcs_reset(ppd); | |
2526 | ||
2527 | /* | |
2528 | * Update the adjusted counters so the adjustment persists | |
2529 | * across driver reload. | |
2530 | */ | |
2531 | if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta || | |
2532 | ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) { | |
2533 | struct qib_devdata *dd = ppd->dd; | |
2534 | u64 diagc; | |
2535 | ||
2536 | /* enable counter writes */ | |
2537 | diagc = qib_read_kreg64(dd, kr_hwdiagctrl); | |
2538 | qib_write_kreg(dd, kr_hwdiagctrl, | |
2539 | diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable)); | |
2540 | ||
2541 | if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) { | |
2542 | val = read_7322_creg32_port(ppd, crp_ibsymbolerr); | |
2543 | if (ppd->cpspec->ibdeltainprog) | |
2544 | val -= val - ppd->cpspec->ibsymsnap; | |
2545 | val -= ppd->cpspec->ibsymdelta; | |
2546 | write_7322_creg_port(ppd, crp_ibsymbolerr, val); | |
2547 | } | |
2548 | if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) { | |
2549 | val = read_7322_creg32_port(ppd, crp_iblinkerrrecov); | |
2550 | if (ppd->cpspec->ibdeltainprog) | |
2551 | val -= val - ppd->cpspec->iblnkerrsnap; | |
2552 | val -= ppd->cpspec->iblnkerrdelta; | |
2553 | write_7322_creg_port(ppd, crp_iblinkerrrecov, val); | |
2554 | } | |
2555 | if (ppd->cpspec->iblnkdowndelta) { | |
2556 | val = read_7322_creg32_port(ppd, crp_iblinkdown); | |
2557 | val += ppd->cpspec->iblnkdowndelta; | |
2558 | write_7322_creg_port(ppd, crp_iblinkdown, val); | |
2559 | } | |
2560 | /* | |
2561 | * No need to save ibmalfdelta since IB perfcounters | |
2562 | * are cleared on driver reload. | |
2563 | */ | |
2564 | ||
2565 | /* and disable counter writes */ | |
2566 | qib_write_kreg(dd, kr_hwdiagctrl, diagc); | |
2567 | } | |
2568 | } | |
2569 | ||
2570 | /** | |
2571 | * qib_setup_7322_setextled - set the state of the two external LEDs | |
2572 | * @ppd: physical port on the qlogic_ib device | |
2573 | * @on: whether the link is up or not | |
2574 | * | |
2575 | * The exact combo of LEDs if on is true is determined by looking | |
2576 | * at the ibcstatus. | |
2577 | * | |
2578 | * These LEDs indicate the physical and logical state of IB link. | |
2579 | * For this chip (at least with recommended board pinouts), LED1 | |
2580 | * is Yellow (logical state) and LED2 is Green (physical state), | |
2581 | * | |
2582 | * Note: We try to match the Mellanox HCA LED behavior as best | |
2583 | * we can. Green indicates physical link state is OK (something is | |
2584 | * plugged in, and we can train). | |
2585 | * Amber indicates the link is logically up (ACTIVE). | |
2586 | * Mellanox further blinks the amber LED to indicate data packet | |
2587 | * activity, but we have no hardware support for that, so it would | |
2588 | * require waking up every 10-20 msecs and checking the counters | |
2589 | * on the chip, and then turning the LED off if appropriate. That's | |
2590 | * visible overhead, so not something we will do. | |
2591 | */ | |
2592 | static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on) | |
2593 | { | |
2594 | struct qib_devdata *dd = ppd->dd; | |
2595 | u64 extctl, ledblink = 0, val; | |
2596 | unsigned long flags; | |
2597 | int yel, grn; | |
2598 | ||
2599 | /* | |
2600 | * The diags use the LED to indicate diag info, so we leave | |
2601 | * the external LED alone when the diags are running. | |
2602 | */ | |
2603 | if (dd->diag_client) | |
2604 | return; | |
2605 | ||
2606 | /* Allow override of LED display for, e.g. Locating system in rack */ | |
2607 | if (ppd->led_override) { | |
2608 | grn = (ppd->led_override & QIB_LED_PHYS); | |
2609 | yel = (ppd->led_override & QIB_LED_LOG); | |
2610 | } else if (on) { | |
2611 | val = qib_read_kreg_port(ppd, krp_ibcstatus_a); | |
2612 | grn = qib_7322_phys_portstate(val) == | |
2613 | IB_PHYSPORTSTATE_LINKUP; | |
2614 | yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE; | |
2615 | } else { | |
2616 | grn = 0; | |
2617 | yel = 0; | |
2618 | } | |
2619 | ||
2620 | spin_lock_irqsave(&dd->cspec->gpio_lock, flags); | |
2621 | extctl = dd->cspec->extctrl & (ppd->port == 1 ? | |
2622 | ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK); | |
2623 | if (grn) { | |
2624 | extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN; | |
2625 | /* | |
2626 | * Counts are in chip clock (4ns) periods. | |
2627 | * This is 1/16 sec (66.6ms) on, | |
2628 | * 3/16 sec (187.5 ms) off, with packets rcvd. | |
2629 | */ | |
2630 | ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) | | |
2631 | ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT); | |
2632 | } | |
2633 | if (yel) | |
2634 | extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL; | |
2635 | dd->cspec->extctrl = extctl; | |
2636 | qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); | |
2637 | spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); | |
2638 | ||
2639 | if (ledblink) /* blink the LED on packet receive */ | |
2640 | qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink); | |
2641 | } | |
2642 | ||
8469ba39 MM |
2643 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
2644 | ||
2645 | static int qib_7322_notify_dca(struct qib_devdata *dd, unsigned long event) | |
2646 | { | |
2647 | switch (event) { | |
2648 | case DCA_PROVIDER_ADD: | |
2649 | if (dd->flags & QIB_DCA_ENABLED) | |
2650 | break; | |
2651 | if (!dca_add_requester(&dd->pcidev->dev)) { | |
2652 | qib_devinfo(dd->pcidev, "DCA enabled\n"); | |
2653 | dd->flags |= QIB_DCA_ENABLED; | |
2654 | qib_setup_dca(dd); | |
2655 | } | |
2656 | break; | |
2657 | case DCA_PROVIDER_REMOVE: | |
2658 | if (dd->flags & QIB_DCA_ENABLED) { | |
2659 | dca_remove_requester(&dd->pcidev->dev); | |
2660 | dd->flags &= ~QIB_DCA_ENABLED; | |
2661 | dd->cspec->dca_ctrl = 0; | |
2662 | qib_write_kreg(dd, KREG_IDX(DCACtrlA), | |
2663 | dd->cspec->dca_ctrl); | |
2664 | } | |
2665 | break; | |
2666 | } | |
2667 | return 0; | |
2668 | } | |
2669 | ||
2670 | static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd, int cpu) | |
2671 | { | |
2672 | struct qib_devdata *dd = rcd->dd; | |
2673 | struct qib_chip_specific *cspec = dd->cspec; | |
2674 | ||
2675 | if (!(dd->flags & QIB_DCA_ENABLED)) | |
2676 | return; | |
2677 | if (cspec->rhdr_cpu[rcd->ctxt] != cpu) { | |
2678 | const struct dca_reg_map *rmp; | |
2679 | ||
2680 | cspec->rhdr_cpu[rcd->ctxt] = cpu; | |
2681 | rmp = &dca_rcvhdr_reg_map[rcd->ctxt]; | |
2682 | cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask; | |
2683 | cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |= | |
2684 | (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb; | |
2685 | qib_devinfo(dd->pcidev, | |
2686 | "Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu, | |
2687 | (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); | |
2688 | qib_write_kreg(dd, rmp->regno, | |
2689 | cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); | |
2690 | cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable); | |
2691 | qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); | |
2692 | } | |
2693 | } | |
2694 | ||
2695 | static void qib_update_sdma_dca(struct qib_pportdata *ppd, int cpu) | |
2696 | { | |
2697 | struct qib_devdata *dd = ppd->dd; | |
2698 | struct qib_chip_specific *cspec = dd->cspec; | |
2699 | unsigned pidx = ppd->port - 1; | |
2700 | ||
2701 | if (!(dd->flags & QIB_DCA_ENABLED)) | |
2702 | return; | |
2703 | if (cspec->sdma_cpu[pidx] != cpu) { | |
2704 | cspec->sdma_cpu[pidx] = cpu; | |
2705 | cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ? | |
2706 | SYM_MASK(DCACtrlF, SendDma1DCAOPH) : | |
2707 | SYM_MASK(DCACtrlF, SendDma0DCAOPH)); | |
2708 | cspec->dca_rcvhdr_ctrl[4] |= | |
2709 | (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << | |
2710 | (ppd->hw_pidx ? | |
2711 | SYM_LSB(DCACtrlF, SendDma1DCAOPH) : | |
2712 | SYM_LSB(DCACtrlF, SendDma0DCAOPH)); | |
2713 | qib_devinfo(dd->pcidev, | |
2714 | "sdma %d cpu %d dca %llx\n", ppd->hw_pidx, cpu, | |
2715 | (long long) cspec->dca_rcvhdr_ctrl[4]); | |
2716 | qib_write_kreg(dd, KREG_IDX(DCACtrlF), | |
2717 | cspec->dca_rcvhdr_ctrl[4]); | |
2718 | cspec->dca_ctrl |= ppd->hw_pidx ? | |
2719 | SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) : | |
2720 | SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable); | |
2721 | qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); | |
2722 | } | |
2723 | } | |
2724 | ||
2725 | static void qib_setup_dca(struct qib_devdata *dd) | |
2726 | { | |
2727 | struct qib_chip_specific *cspec = dd->cspec; | |
2728 | int i; | |
2729 | ||
2730 | for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++) | |
2731 | cspec->rhdr_cpu[i] = -1; | |
2732 | for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) | |
2733 | cspec->sdma_cpu[i] = -1; | |
2734 | cspec->dca_rcvhdr_ctrl[0] = | |
2735 | (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) | | |
2736 | (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) | | |
2737 | (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) | | |
2738 | (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt)); | |
2739 | cspec->dca_rcvhdr_ctrl[1] = | |
2740 | (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) | | |
2741 | (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) | | |
2742 | (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) | | |
2743 | (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt)); | |
2744 | cspec->dca_rcvhdr_ctrl[2] = | |
2745 | (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) | | |
2746 | (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) | | |
2747 | (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) | | |
2748 | (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt)); | |
2749 | cspec->dca_rcvhdr_ctrl[3] = | |
2750 | (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) | | |
2751 | (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) | | |
2752 | (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) | | |
2753 | (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt)); | |
2754 | cspec->dca_rcvhdr_ctrl[4] = | |
2755 | (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) | | |
2756 | (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt)); | |
2757 | for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) | |
2758 | qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i, | |
2759 | cspec->dca_rcvhdr_ctrl[i]); | |
2760 | for (i = 0; i < cspec->num_msix_entries; i++) | |
c4bc6156 | 2761 | setup_dca_notifier(dd, i); |
8469ba39 MM |
2762 | } |
2763 | ||
2764 | static void qib_irq_notifier_notify(struct irq_affinity_notify *notify, | |
2765 | const cpumask_t *mask) | |
2766 | { | |
2767 | struct qib_irq_notify *n = | |
2768 | container_of(notify, struct qib_irq_notify, notify); | |
2769 | int cpu = cpumask_first(mask); | |
2770 | ||
2771 | if (n->rcv) { | |
2772 | struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg; | |
da12c1f6 | 2773 | |
8469ba39 MM |
2774 | qib_update_rhdrq_dca(rcd, cpu); |
2775 | } else { | |
2776 | struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg; | |
da12c1f6 | 2777 | |
8469ba39 MM |
2778 | qib_update_sdma_dca(ppd, cpu); |
2779 | } | |
2780 | } | |
2781 | ||
2782 | static void qib_irq_notifier_release(struct kref *ref) | |
2783 | { | |
2784 | struct qib_irq_notify *n = | |
2785 | container_of(ref, struct qib_irq_notify, notify.kref); | |
2786 | struct qib_devdata *dd; | |
2787 | ||
2788 | if (n->rcv) { | |
2789 | struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg; | |
da12c1f6 | 2790 | |
8469ba39 MM |
2791 | dd = rcd->dd; |
2792 | } else { | |
2793 | struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg; | |
da12c1f6 | 2794 | |
8469ba39 MM |
2795 | dd = ppd->dd; |
2796 | } | |
2797 | qib_devinfo(dd->pcidev, | |
2798 | "release on HCA notify 0x%p n 0x%p\n", ref, n); | |
2799 | kfree(n); | |
2800 | } | |
2801 | #endif | |
2802 | ||
c4bc6156 | 2803 | static void qib_7322_free_irq(struct qib_devdata *dd) |
f931551b RC |
2804 | { |
2805 | u64 intgranted; | |
c4bc6156 | 2806 | int i; |
f931551b RC |
2807 | |
2808 | dd->cspec->main_int_mask = ~0ULL; | |
f931551b | 2809 | |
c4bc6156 MR |
2810 | for (i = 0; i < dd->cspec->num_msix_entries; i++) { |
2811 | /* only free IRQs that were allocated */ | |
2812 | if (dd->cspec->msix_entries[i].arg) { | |
8469ba39 | 2813 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
c4bc6156 | 2814 | reset_dca_notifier(dd, i); |
8469ba39 | 2815 | #endif |
c4bc6156 MR |
2816 | irq_set_affinity_hint(pci_irq_vector(dd->pcidev, i), |
2817 | NULL); | |
a778f3fd | 2818 | free_cpumask_var(dd->cspec->msix_entries[i].mask); |
c4bc6156 MR |
2819 | pci_free_irq(dd->pcidev, i, |
2820 | dd->cspec->msix_entries[i].arg); | |
a778f3fd | 2821 | } |
f931551b | 2822 | } |
c4bc6156 MR |
2823 | |
2824 | /* If num_msix_entries was 0, disable the INTx IRQ */ | |
2825 | if (!dd->cspec->num_msix_entries) | |
2826 | pci_free_irq(dd->pcidev, 0, dd); | |
2827 | else | |
2828 | dd->cspec->num_msix_entries = 0; | |
2829 | ||
2830 | pci_free_irq_vectors(dd->pcidev); | |
2831 | ||
f931551b RC |
2832 | /* make sure no MSIx interrupts are left pending */ |
2833 | intgranted = qib_read_kreg64(dd, kr_intgranted); | |
2834 | if (intgranted) | |
2835 | qib_write_kreg(dd, kr_intgranted, intgranted); | |
2836 | } | |
2837 | ||
f931551b RC |
2838 | static void qib_setup_7322_cleanup(struct qib_devdata *dd) |
2839 | { | |
2840 | int i; | |
2841 | ||
8469ba39 MM |
2842 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
2843 | if (dd->flags & QIB_DCA_ENABLED) { | |
2844 | dca_remove_requester(&dd->pcidev->dev); | |
2845 | dd->flags &= ~QIB_DCA_ENABLED; | |
2846 | dd->cspec->dca_ctrl = 0; | |
2847 | qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl); | |
2848 | } | |
2849 | #endif | |
2850 | ||
f931551b RC |
2851 | qib_7322_free_irq(dd); |
2852 | kfree(dd->cspec->cntrs); | |
ac53e0f5 CJ |
2853 | bitmap_free(dd->cspec->sendchkenable); |
2854 | bitmap_free(dd->cspec->sendgrhchk); | |
2855 | bitmap_free(dd->cspec->sendibchk); | |
f931551b | 2856 | kfree(dd->cspec->msix_entries); |
f931551b RC |
2857 | for (i = 0; i < dd->num_pports; i++) { |
2858 | unsigned long flags; | |
2859 | u32 mask = QSFP_GPIO_MOD_PRS_N | | |
2860 | (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT); | |
2861 | ||
2862 | kfree(dd->pport[i].cpspec->portcntrs); | |
2863 | if (dd->flags & QIB_HAS_QSFP) { | |
2864 | spin_lock_irqsave(&dd->cspec->gpio_lock, flags); | |
2865 | dd->cspec->gpio_mask &= ~mask; | |
2866 | qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); | |
2867 | spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); | |
f931551b | 2868 | } |
f931551b RC |
2869 | } |
2870 | } | |
2871 | ||
2872 | /* handle SDMA interrupts */ | |
2873 | static void sdma_7322_intr(struct qib_devdata *dd, u64 istat) | |
2874 | { | |
2875 | struct qib_pportdata *ppd0 = &dd->pport[0]; | |
2876 | struct qib_pportdata *ppd1 = &dd->pport[1]; | |
2877 | u64 intr0 = istat & (INT_MASK_P(SDma, 0) | | |
2878 | INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0)); | |
2879 | u64 intr1 = istat & (INT_MASK_P(SDma, 1) | | |
2880 | INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1)); | |
2881 | ||
2882 | if (intr0) | |
2883 | qib_sdma_intr(ppd0); | |
2884 | if (intr1) | |
2885 | qib_sdma_intr(ppd1); | |
2886 | ||
2887 | if (istat & INT_MASK_PM(SDmaCleanupDone, 0)) | |
2888 | qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started); | |
2889 | if (istat & INT_MASK_PM(SDmaCleanupDone, 1)) | |
2890 | qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started); | |
2891 | } | |
2892 | ||
2893 | /* | |
2894 | * Set or clear the Send buffer available interrupt enable bit. | |
2895 | */ | |
2896 | static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint) | |
2897 | { | |
2898 | unsigned long flags; | |
2899 | ||
2900 | spin_lock_irqsave(&dd->sendctrl_lock, flags); | |
2901 | if (needint) | |
2902 | dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail); | |
2903 | else | |
2904 | dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail); | |
2905 | qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); | |
2906 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
2907 | spin_unlock_irqrestore(&dd->sendctrl_lock, flags); | |
2908 | } | |
2909 | ||
2910 | /* | |
2911 | * Somehow got an interrupt with reserved bits set in interrupt status. | |
2912 | * Print a message so we know it happened, then clear them. | |
2913 | * keep mainline interrupt handler cache-friendly | |
2914 | */ | |
2915 | static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat) | |
2916 | { | |
2917 | u64 kills; | |
2918 | char msg[128]; | |
2919 | ||
2920 | kills = istat & ~QIB_I_BITSEXTANT; | |
7fac3301 MM |
2921 | qib_dev_err(dd, |
2922 | "Clearing reserved interrupt(s) 0x%016llx: %s\n", | |
2923 | (unsigned long long) kills, msg); | |
f931551b RC |
2924 | qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); |
2925 | } | |
2926 | ||
2927 | /* keep mainline interrupt handler cache-friendly */ | |
2928 | static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd) | |
2929 | { | |
2930 | u32 gpiostatus; | |
2931 | int handled = 0; | |
2932 | int pidx; | |
2933 | ||
2934 | /* | |
2935 | * Boards for this chip currently don't use GPIO interrupts, | |
2936 | * so clear by writing GPIOstatus to GPIOclear, and complain | |
2937 | * to developer. To avoid endless repeats, clear | |
2938 | * the bits in the mask, since there is some kind of | |
2939 | * programming error or chip problem. | |
2940 | */ | |
2941 | gpiostatus = qib_read_kreg32(dd, kr_gpio_status); | |
2942 | /* | |
2943 | * In theory, writing GPIOstatus to GPIOclear could | |
2944 | * have a bad side-effect on some diagnostic that wanted | |
2945 | * to poll for a status-change, but the various shadows | |
2946 | * make that problematic at best. Diags will just suppress | |
2947 | * all GPIO interrupts during such tests. | |
2948 | */ | |
2949 | qib_write_kreg(dd, kr_gpio_clear, gpiostatus); | |
2950 | /* | |
2951 | * Check for QSFP MOD_PRS changes | |
2952 | * only works for single port if IB1 != pidx1 | |
2953 | */ | |
2954 | for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP); | |
2955 | ++pidx) { | |
2956 | struct qib_pportdata *ppd; | |
2957 | struct qib_qsfp_data *qd; | |
2958 | u32 mask; | |
da12c1f6 | 2959 | |
f931551b RC |
2960 | if (!dd->pport[pidx].link_speed_supported) |
2961 | continue; | |
2962 | mask = QSFP_GPIO_MOD_PRS_N; | |
2963 | ppd = dd->pport + pidx; | |
2964 | mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); | |
2965 | if (gpiostatus & dd->cspec->gpio_mask & mask) { | |
2966 | u64 pins; | |
da12c1f6 | 2967 | |
f931551b RC |
2968 | qd = &ppd->cpspec->qsfp_data; |
2969 | gpiostatus &= ~mask; | |
2970 | pins = qib_read_kreg64(dd, kr_extstatus); | |
2971 | pins >>= SYM_LSB(EXTStatus, GPIOIn); | |
2972 | if (!(pins & mask)) { | |
2973 | ++handled; | |
8482d5d1 | 2974 | qd->t_insert = jiffies; |
f0626710 | 2975 | queue_work(ib_wq, &qd->work); |
f931551b RC |
2976 | } |
2977 | } | |
2978 | } | |
2979 | ||
2980 | if (gpiostatus && !handled) { | |
2981 | const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); | |
2982 | u32 gpio_irq = mask & gpiostatus; | |
2983 | ||
2984 | /* | |
2985 | * Clear any troublemakers, and update chip from shadow | |
2986 | */ | |
2987 | dd->cspec->gpio_mask &= ~gpio_irq; | |
2988 | qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); | |
2989 | } | |
2990 | } | |
2991 | ||
2992 | /* | |
2993 | * Handle errors and unusual events first, separate function | |
2994 | * to improve cache hits for fast path interrupt handling. | |
2995 | */ | |
2996 | static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat) | |
2997 | { | |
2998 | if (istat & ~QIB_I_BITSEXTANT) | |
2999 | unknown_7322_ibits(dd, istat); | |
3000 | if (istat & QIB_I_GPIO) | |
3001 | unknown_7322_gpio_intr(dd); | |
e67306a3 MM |
3002 | if (istat & QIB_I_C_ERROR) { |
3003 | qib_write_kreg(dd, kr_errmask, 0ULL); | |
3004 | tasklet_schedule(&dd->error_tasklet); | |
3005 | } | |
f931551b RC |
3006 | if (istat & INT_MASK_P(Err, 0) && dd->rcd[0]) |
3007 | handle_7322_p_errors(dd->rcd[0]->ppd); | |
3008 | if (istat & INT_MASK_P(Err, 1) && dd->rcd[1]) | |
3009 | handle_7322_p_errors(dd->rcd[1]->ppd); | |
3010 | } | |
3011 | ||
3012 | /* | |
3013 | * Dynamically adjust the rcv int timeout for a context based on incoming | |
3014 | * packet rate. | |
3015 | */ | |
3016 | static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts) | |
3017 | { | |
3018 | struct qib_devdata *dd = rcd->dd; | |
3019 | u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; | |
3020 | ||
3021 | /* | |
3022 | * Dynamically adjust idle timeout on chip | |
3023 | * based on number of packets processed. | |
3024 | */ | |
3025 | if (npkts < rcv_int_count && timeout > 2) | |
3026 | timeout >>= 1; | |
3027 | else if (npkts >= rcv_int_count && timeout < rcv_int_timeout) | |
3028 | timeout = min(timeout << 1, rcv_int_timeout); | |
3029 | else | |
3030 | return; | |
3031 | ||
3032 | dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; | |
3033 | qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout); | |
3034 | } | |
3035 | ||
3036 | /* | |
3037 | * This is the main interrupt handler. | |
3038 | * It will normally only be used for low frequency interrupts but may | |
3039 | * have to handle all interrupts if INTx is enabled or fewer than normal | |
3040 | * MSIx interrupts were allocated. | |
3041 | * This routine should ignore the interrupt bits for any of the | |
3042 | * dedicated MSIx handlers. | |
3043 | */ | |
3044 | static irqreturn_t qib_7322intr(int irq, void *data) | |
3045 | { | |
3046 | struct qib_devdata *dd = data; | |
3047 | irqreturn_t ret; | |
3048 | u64 istat; | |
3049 | u64 ctxtrbits; | |
3050 | u64 rmask; | |
3051 | unsigned i; | |
3052 | u32 npkts; | |
3053 | ||
3054 | if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { | |
3055 | /* | |
3056 | * This return value is not great, but we do not want the | |
3057 | * interrupt core code to remove our interrupt handler | |
3058 | * because we don't appear to be handling an interrupt | |
3059 | * during a chip reset. | |
3060 | */ | |
3061 | ret = IRQ_HANDLED; | |
3062 | goto bail; | |
3063 | } | |
3064 | ||
3065 | istat = qib_read_kreg64(dd, kr_intstatus); | |
3066 | ||
3067 | if (unlikely(istat == ~0ULL)) { | |
3068 | qib_bad_intrstatus(dd); | |
3069 | qib_dev_err(dd, "Interrupt status all f's, skipping\n"); | |
3070 | /* don't know if it was our interrupt or not */ | |
3071 | ret = IRQ_NONE; | |
3072 | goto bail; | |
3073 | } | |
3074 | ||
3075 | istat &= dd->cspec->main_int_mask; | |
3076 | if (unlikely(!istat)) { | |
3077 | /* already handled, or shared and not us */ | |
3078 | ret = IRQ_NONE; | |
3079 | goto bail; | |
3080 | } | |
3081 | ||
1ed88dd7 | 3082 | this_cpu_inc(*dd->int_counter); |
f931551b RC |
3083 | |
3084 | /* handle "errors" of various kinds first, device ahead of port */ | |
3085 | if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO | | |
3086 | QIB_I_C_ERROR | INT_MASK_P(Err, 0) | | |
3087 | INT_MASK_P(Err, 1)))) | |
3088 | unlikely_7322_intr(dd, istat); | |
3089 | ||
3090 | /* | |
3091 | * Clear the interrupt bits we found set, relatively early, so we | |
3092 | * "know" know the chip will have seen this by the time we process | |
3093 | * the queue, and will re-interrupt if necessary. The processor | |
3094 | * itself won't take the interrupt again until we return. | |
3095 | */ | |
3096 | qib_write_kreg(dd, kr_intclear, istat); | |
3097 | ||
3098 | /* | |
3099 | * Handle kernel receive queues before checking for pio buffers | |
3100 | * available since receives can overflow; piobuf waiters can afford | |
3101 | * a few extra cycles, since they were waiting anyway. | |
3102 | */ | |
3103 | ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK); | |
3104 | if (ctxtrbits) { | |
3105 | rmask = (1ULL << QIB_I_RCVAVAIL_LSB) | | |
3106 | (1ULL << QIB_I_RCVURG_LSB); | |
3107 | for (i = 0; i < dd->first_user_ctxt; i++) { | |
3108 | if (ctxtrbits & rmask) { | |
3109 | ctxtrbits &= ~rmask; | |
44d75d3d | 3110 | if (dd->rcd[i]) |
f931551b | 3111 | qib_kreceive(dd->rcd[i], NULL, &npkts); |
f931551b RC |
3112 | } |
3113 | rmask <<= 1; | |
3114 | } | |
3115 | if (ctxtrbits) { | |
3116 | ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) | | |
3117 | (ctxtrbits >> QIB_I_RCVURG_LSB); | |
3118 | qib_handle_urcv(dd, ctxtrbits); | |
3119 | } | |
3120 | } | |
3121 | ||
3122 | if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1))) | |
3123 | sdma_7322_intr(dd, istat); | |
3124 | ||
3125 | if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) | |
3126 | qib_ib_piobufavail(dd); | |
3127 | ||
3128 | ret = IRQ_HANDLED; | |
3129 | bail: | |
3130 | return ret; | |
3131 | } | |
3132 | ||
3133 | /* | |
3134 | * Dedicated receive packet available interrupt handler. | |
3135 | */ | |
3136 | static irqreturn_t qib_7322pintr(int irq, void *data) | |
3137 | { | |
3138 | struct qib_ctxtdata *rcd = data; | |
3139 | struct qib_devdata *dd = rcd->dd; | |
3140 | u32 npkts; | |
3141 | ||
3142 | if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) | |
3143 | /* | |
3144 | * This return value is not great, but we do not want the | |
3145 | * interrupt core code to remove our interrupt handler | |
3146 | * because we don't appear to be handling an interrupt | |
3147 | * during a chip reset. | |
3148 | */ | |
3149 | return IRQ_HANDLED; | |
3150 | ||
1ed88dd7 | 3151 | this_cpu_inc(*dd->int_counter); |
f931551b | 3152 | |
f931551b RC |
3153 | /* Clear the interrupt bit we expect to be set. */ |
3154 | qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) | | |
3155 | (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); | |
3156 | ||
3157 | qib_kreceive(rcd, NULL, &npkts); | |
f931551b RC |
3158 | |
3159 | return IRQ_HANDLED; | |
3160 | } | |
3161 | ||
3162 | /* | |
3163 | * Dedicated Send buffer available interrupt handler. | |
3164 | */ | |
3165 | static irqreturn_t qib_7322bufavail(int irq, void *data) | |
3166 | { | |
3167 | struct qib_devdata *dd = data; | |
3168 | ||
3169 | if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) | |
3170 | /* | |
3171 | * This return value is not great, but we do not want the | |
3172 | * interrupt core code to remove our interrupt handler | |
3173 | * because we don't appear to be handling an interrupt | |
3174 | * during a chip reset. | |
3175 | */ | |
3176 | return IRQ_HANDLED; | |
3177 | ||
1ed88dd7 | 3178 | this_cpu_inc(*dd->int_counter); |
f931551b RC |
3179 | |
3180 | /* Clear the interrupt bit we expect to be set. */ | |
3181 | qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL); | |
3182 | ||
3183 | /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */ | |
3184 | if (dd->flags & QIB_INITTED) | |
3185 | qib_ib_piobufavail(dd); | |
3186 | else | |
3187 | qib_wantpiobuf_7322_intr(dd, 0); | |
3188 | ||
3189 | return IRQ_HANDLED; | |
3190 | } | |
3191 | ||
3192 | /* | |
3193 | * Dedicated Send DMA interrupt handler. | |
3194 | */ | |
3195 | static irqreturn_t sdma_intr(int irq, void *data) | |
3196 | { | |
3197 | struct qib_pportdata *ppd = data; | |
3198 | struct qib_devdata *dd = ppd->dd; | |
3199 | ||
3200 | if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) | |
3201 | /* | |
3202 | * This return value is not great, but we do not want the | |
3203 | * interrupt core code to remove our interrupt handler | |
3204 | * because we don't appear to be handling an interrupt | |
3205 | * during a chip reset. | |
3206 | */ | |
3207 | return IRQ_HANDLED; | |
3208 | ||
1ed88dd7 | 3209 | this_cpu_inc(*dd->int_counter); |
f931551b | 3210 | |
f931551b RC |
3211 | /* Clear the interrupt bit we expect to be set. */ |
3212 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? | |
3213 | INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0)); | |
3214 | qib_sdma_intr(ppd); | |
3215 | ||
3216 | return IRQ_HANDLED; | |
3217 | } | |
3218 | ||
3219 | /* | |
3220 | * Dedicated Send DMA idle interrupt handler. | |
3221 | */ | |
3222 | static irqreturn_t sdma_idle_intr(int irq, void *data) | |
3223 | { | |
3224 | struct qib_pportdata *ppd = data; | |
3225 | struct qib_devdata *dd = ppd->dd; | |
3226 | ||
3227 | if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) | |
3228 | /* | |
3229 | * This return value is not great, but we do not want the | |
3230 | * interrupt core code to remove our interrupt handler | |
3231 | * because we don't appear to be handling an interrupt | |
3232 | * during a chip reset. | |
3233 | */ | |
3234 | return IRQ_HANDLED; | |
3235 | ||
1ed88dd7 | 3236 | this_cpu_inc(*dd->int_counter); |
f931551b | 3237 | |
f931551b RC |
3238 | /* Clear the interrupt bit we expect to be set. */ |
3239 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? | |
3240 | INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0)); | |
3241 | qib_sdma_intr(ppd); | |
3242 | ||
3243 | return IRQ_HANDLED; | |
3244 | } | |
3245 | ||
3246 | /* | |
3247 | * Dedicated Send DMA progress interrupt handler. | |
3248 | */ | |
3249 | static irqreturn_t sdma_progress_intr(int irq, void *data) | |
3250 | { | |
3251 | struct qib_pportdata *ppd = data; | |
3252 | struct qib_devdata *dd = ppd->dd; | |
3253 | ||
3254 | if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) | |
3255 | /* | |
3256 | * This return value is not great, but we do not want the | |
3257 | * interrupt core code to remove our interrupt handler | |
3258 | * because we don't appear to be handling an interrupt | |
3259 | * during a chip reset. | |
3260 | */ | |
3261 | return IRQ_HANDLED; | |
3262 | ||
1ed88dd7 | 3263 | this_cpu_inc(*dd->int_counter); |
f931551b | 3264 | |
f931551b RC |
3265 | /* Clear the interrupt bit we expect to be set. */ |
3266 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? | |
3267 | INT_MASK_P(SDmaProgress, 1) : | |
3268 | INT_MASK_P(SDmaProgress, 0)); | |
3269 | qib_sdma_intr(ppd); | |
3270 | ||
3271 | return IRQ_HANDLED; | |
3272 | } | |
3273 | ||
3274 | /* | |
3275 | * Dedicated Send DMA cleanup interrupt handler. | |
3276 | */ | |
3277 | static irqreturn_t sdma_cleanup_intr(int irq, void *data) | |
3278 | { | |
3279 | struct qib_pportdata *ppd = data; | |
3280 | struct qib_devdata *dd = ppd->dd; | |
3281 | ||
3282 | if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) | |
3283 | /* | |
3284 | * This return value is not great, but we do not want the | |
3285 | * interrupt core code to remove our interrupt handler | |
3286 | * because we don't appear to be handling an interrupt | |
3287 | * during a chip reset. | |
3288 | */ | |
3289 | return IRQ_HANDLED; | |
3290 | ||
1ed88dd7 | 3291 | this_cpu_inc(*dd->int_counter); |
f931551b | 3292 | |
f931551b RC |
3293 | /* Clear the interrupt bit we expect to be set. */ |
3294 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? | |
3295 | INT_MASK_PM(SDmaCleanupDone, 1) : | |
3296 | INT_MASK_PM(SDmaCleanupDone, 0)); | |
3297 | qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started); | |
3298 | ||
3299 | return IRQ_HANDLED; | |
3300 | } | |
3301 | ||
8469ba39 MM |
3302 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
3303 | ||
c4bc6156 | 3304 | static void reset_dca_notifier(struct qib_devdata *dd, int msixnum) |
8469ba39 | 3305 | { |
c4bc6156 | 3306 | if (!dd->cspec->msix_entries[msixnum].dca) |
8469ba39 | 3307 | return; |
c4bc6156 MR |
3308 | |
3309 | qib_devinfo(dd->pcidev, "Disabling notifier on HCA %d irq %d\n", | |
3310 | dd->unit, pci_irq_vector(dd->pcidev, msixnum)); | |
3311 | irq_set_affinity_notifier(pci_irq_vector(dd->pcidev, msixnum), NULL); | |
3312 | dd->cspec->msix_entries[msixnum].notifier = NULL; | |
8469ba39 MM |
3313 | } |
3314 | ||
c4bc6156 | 3315 | static void setup_dca_notifier(struct qib_devdata *dd, int msixnum) |
8469ba39 | 3316 | { |
c4bc6156 | 3317 | struct qib_msix_entry *m = &dd->cspec->msix_entries[msixnum]; |
8469ba39 MM |
3318 | struct qib_irq_notify *n; |
3319 | ||
3320 | if (!m->dca) | |
3321 | return; | |
3322 | n = kzalloc(sizeof(*n), GFP_KERNEL); | |
3323 | if (n) { | |
3324 | int ret; | |
3325 | ||
3326 | m->notifier = n; | |
c4bc6156 | 3327 | n->notify.irq = pci_irq_vector(dd->pcidev, msixnum); |
8469ba39 MM |
3328 | n->notify.notify = qib_irq_notifier_notify; |
3329 | n->notify.release = qib_irq_notifier_release; | |
3330 | n->arg = m->arg; | |
3331 | n->rcv = m->rcv; | |
3332 | qib_devinfo(dd->pcidev, | |
3333 | "set notifier irq %d rcv %d notify %p\n", | |
3334 | n->notify.irq, n->rcv, &n->notify); | |
3335 | ret = irq_set_affinity_notifier( | |
3336 | n->notify.irq, | |
3337 | &n->notify); | |
3338 | if (ret) { | |
3339 | m->notifier = NULL; | |
3340 | kfree(n); | |
3341 | } | |
3342 | } | |
3343 | } | |
3344 | ||
3345 | #endif | |
3346 | ||
f931551b RC |
3347 | /* |
3348 | * Set up our chip-specific interrupt handler. | |
3349 | * The interrupt type has already been setup, so | |
3350 | * we just need to do the registration and error checking. | |
3351 | * If we are using MSIx interrupts, we may fall back to | |
3352 | * INTx later, if the interrupt handler doesn't get called | |
3353 | * within 1/2 second (see verify_interrupt()). | |
3354 | */ | |
3355 | static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend) | |
3356 | { | |
3357 | int ret, i, msixnum; | |
3358 | u64 redirect[6]; | |
3359 | u64 mask; | |
a778f3fd MM |
3360 | const struct cpumask *local_mask; |
3361 | int firstcpu, secondcpu = 0, currrcvcpu = 0; | |
f931551b RC |
3362 | |
3363 | if (!dd->num_pports) | |
3364 | return; | |
3365 | ||
3366 | if (clearpend) { | |
3367 | /* | |
3368 | * if not switching interrupt types, be sure interrupts are | |
3369 | * disabled, and then clear anything pending at this point, | |
3370 | * because we are starting clean. | |
3371 | */ | |
3372 | qib_7322_set_intr_state(dd, 0); | |
3373 | ||
3374 | /* clear the reset error, init error/hwerror mask */ | |
3375 | qib_7322_init_hwerrors(dd); | |
3376 | ||
3377 | /* clear any interrupt bits that might be set */ | |
3378 | qib_write_kreg(dd, kr_intclear, ~0ULL); | |
3379 | ||
3380 | /* make sure no pending MSIx intr, and clear diag reg */ | |
3381 | qib_write_kreg(dd, kr_intgranted, ~0ULL); | |
3382 | qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL); | |
3383 | } | |
3384 | ||
3385 | if (!dd->cspec->num_msix_entries) { | |
3386 | /* Try to get INTx interrupt */ | |
3387 | try_intx: | |
c4bc6156 MR |
3388 | ret = pci_request_irq(dd->pcidev, 0, qib_7322intr, NULL, dd, |
3389 | QIB_DRV_NAME); | |
f931551b | 3390 | if (ret) { |
c4bc6156 MR |
3391 | qib_dev_err( |
3392 | dd, | |
7fac3301 | 3393 | "Couldn't setup INTx interrupt (irq=%d): %d\n", |
c4bc6156 MR |
3394 | pci_irq_vector(dd->pcidev, 0), ret); |
3395 | return; | |
f931551b | 3396 | } |
f931551b | 3397 | dd->cspec->main_int_mask = ~0ULL; |
c4bc6156 | 3398 | return; |
f931551b RC |
3399 | } |
3400 | ||
3401 | /* Try to get MSIx interrupts */ | |
041af0bb | 3402 | memset(redirect, 0, sizeof(redirect)); |
f931551b RC |
3403 | mask = ~0ULL; |
3404 | msixnum = 0; | |
a778f3fd MM |
3405 | local_mask = cpumask_of_pcibus(dd->pcidev->bus); |
3406 | firstcpu = cpumask_first(local_mask); | |
3407 | if (firstcpu >= nr_cpu_ids || | |
3408 | cpumask_weight(local_mask) == num_online_cpus()) { | |
3409 | local_mask = topology_core_cpumask(0); | |
3410 | firstcpu = cpumask_first(local_mask); | |
3411 | } | |
3412 | if (firstcpu < nr_cpu_ids) { | |
3413 | secondcpu = cpumask_next(firstcpu, local_mask); | |
3414 | if (secondcpu >= nr_cpu_ids) | |
3415 | secondcpu = firstcpu; | |
3416 | currrcvcpu = secondcpu; | |
3417 | } | |
f931551b RC |
3418 | for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { |
3419 | irq_handler_t handler; | |
f931551b | 3420 | void *arg; |
f931551b | 3421 | int lsb, reg, sh; |
8469ba39 MM |
3422 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
3423 | int dca = 0; | |
3424 | #endif | |
f931551b RC |
3425 | if (i < ARRAY_SIZE(irq_table)) { |
3426 | if (irq_table[i].port) { | |
3427 | /* skip if for a non-configured port */ | |
3428 | if (irq_table[i].port > dd->num_pports) | |
3429 | continue; | |
3430 | arg = dd->pport + irq_table[i].port - 1; | |
3431 | } else | |
3432 | arg = dd; | |
8469ba39 MM |
3433 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
3434 | dca = irq_table[i].dca; | |
3435 | #endif | |
f931551b RC |
3436 | lsb = irq_table[i].lsb; |
3437 | handler = irq_table[i].handler; | |
c4bc6156 MR |
3438 | ret = pci_request_irq(dd->pcidev, msixnum, handler, |
3439 | NULL, arg, QIB_DRV_NAME "%d%s", | |
3440 | dd->unit, | |
3441 | irq_table[i].name); | |
f931551b RC |
3442 | } else { |
3443 | unsigned ctxt; | |
3444 | ||
3445 | ctxt = i - ARRAY_SIZE(irq_table); | |
3446 | /* per krcvq context receive interrupt */ | |
3447 | arg = dd->rcd[ctxt]; | |
3448 | if (!arg) | |
3449 | continue; | |
e67306a3 MM |
3450 | if (qib_krcvq01_no_msi && ctxt < 2) |
3451 | continue; | |
8469ba39 MM |
3452 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
3453 | dca = 1; | |
3454 | #endif | |
f931551b RC |
3455 | lsb = QIB_I_RCVAVAIL_LSB + ctxt; |
3456 | handler = qib_7322pintr; | |
c4bc6156 MR |
3457 | ret = pci_request_irq(dd->pcidev, msixnum, handler, |
3458 | NULL, arg, | |
3459 | QIB_DRV_NAME "%d (kctx)", | |
3460 | dd->unit); | |
f931551b | 3461 | } |
581d01aa | 3462 | |
f931551b RC |
3463 | if (ret) { |
3464 | /* | |
3465 | * Shouldn't happen since the enable said we could | |
3466 | * have as many as we are trying to setup here. | |
3467 | */ | |
7fac3301 | 3468 | qib_dev_err(dd, |
c4bc6156 MR |
3469 | "Couldn't setup MSIx interrupt (vec=%d, irq=%d): %d\n", |
3470 | msixnum, | |
3471 | pci_irq_vector(dd->pcidev, msixnum), | |
3472 | ret); | |
3473 | qib_7322_free_irq(dd); | |
91d343de | 3474 | pci_alloc_irq_vectors(dd->pcidev, 1, 1, PCI_IRQ_INTX); |
f931551b RC |
3475 | goto try_intx; |
3476 | } | |
a778f3fd | 3477 | dd->cspec->msix_entries[msixnum].arg = arg; |
8469ba39 MM |
3478 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
3479 | dd->cspec->msix_entries[msixnum].dca = dca; | |
3480 | dd->cspec->msix_entries[msixnum].rcv = | |
3481 | handler == qib_7322pintr; | |
3482 | #endif | |
f931551b RC |
3483 | if (lsb >= 0) { |
3484 | reg = lsb / IBA7322_REDIRECT_VEC_PER_REG; | |
3485 | sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) * | |
3486 | SYM_LSB(IntRedirect0, vec1); | |
3487 | mask &= ~(1ULL << lsb); | |
3488 | redirect[reg] |= ((u64) msixnum) << sh; | |
3489 | } | |
2055d1f0 BVA |
3490 | qib_read_kreg64(dd, 2 * msixnum + 1 + |
3491 | (QIB_7322_MsixTable_OFFS / sizeof(u64))); | |
a778f3fd MM |
3492 | if (firstcpu < nr_cpu_ids && |
3493 | zalloc_cpumask_var( | |
3494 | &dd->cspec->msix_entries[msixnum].mask, | |
3495 | GFP_KERNEL)) { | |
3496 | if (handler == qib_7322pintr) { | |
3497 | cpumask_set_cpu(currrcvcpu, | |
3498 | dd->cspec->msix_entries[msixnum].mask); | |
3499 | currrcvcpu = cpumask_next(currrcvcpu, | |
3500 | local_mask); | |
3501 | if (currrcvcpu >= nr_cpu_ids) | |
3502 | currrcvcpu = secondcpu; | |
3503 | } else { | |
3504 | cpumask_set_cpu(firstcpu, | |
3505 | dd->cspec->msix_entries[msixnum].mask); | |
3506 | } | |
3507 | irq_set_affinity_hint( | |
c4bc6156 | 3508 | pci_irq_vector(dd->pcidev, msixnum), |
a778f3fd MM |
3509 | dd->cspec->msix_entries[msixnum].mask); |
3510 | } | |
f931551b RC |
3511 | msixnum++; |
3512 | } | |
3513 | /* Initialize the vector mapping */ | |
3514 | for (i = 0; i < ARRAY_SIZE(redirect); i++) | |
3515 | qib_write_kreg(dd, kr_intredirect + i, redirect[i]); | |
3516 | dd->cspec->main_int_mask = mask; | |
a23afb44 | 3517 | tasklet_setup(&dd->error_tasklet, qib_error_tasklet); |
f931551b RC |
3518 | } |
3519 | ||
3520 | /** | |
3521 | * qib_7322_boardname - fill in the board name and note features | |
3522 | * @dd: the qlogic_ib device | |
3523 | * | |
3524 | * info will be based on the board revision register | |
3525 | */ | |
3526 | static unsigned qib_7322_boardname(struct qib_devdata *dd) | |
3527 | { | |
3528 | /* Will need enumeration of board-types here */ | |
3b716933 KA |
3529 | u32 boardid; |
3530 | unsigned int features = DUAL_PORT_CAP; | |
f931551b RC |
3531 | |
3532 | boardid = SYM_FIELD(dd->revision, Revision, BoardID); | |
3533 | ||
3534 | switch (boardid) { | |
3535 | case 0: | |
3b716933 | 3536 | dd->boardname = "InfiniPath_QLE7342_Emulation"; |
f931551b RC |
3537 | break; |
3538 | case 1: | |
3b716933 | 3539 | dd->boardname = "InfiniPath_QLE7340"; |
f931551b RC |
3540 | dd->flags |= QIB_HAS_QSFP; |
3541 | features = PORT_SPD_CAP; | |
3542 | break; | |
3543 | case 2: | |
3b716933 | 3544 | dd->boardname = "InfiniPath_QLE7342"; |
f931551b RC |
3545 | dd->flags |= QIB_HAS_QSFP; |
3546 | break; | |
3547 | case 3: | |
3b716933 | 3548 | dd->boardname = "InfiniPath_QMI7342"; |
f931551b RC |
3549 | break; |
3550 | case 4: | |
3b716933 | 3551 | dd->boardname = "InfiniPath_Unsupported7342"; |
f931551b RC |
3552 | qib_dev_err(dd, "Unsupported version of QMH7342\n"); |
3553 | features = 0; | |
3554 | break; | |
3555 | case BOARD_QMH7342: | |
3b716933 | 3556 | dd->boardname = "InfiniPath_QMH7342"; |
f931551b RC |
3557 | features = 0x24; |
3558 | break; | |
3559 | case BOARD_QME7342: | |
3b716933 | 3560 | dd->boardname = "InfiniPath_QME7342"; |
f931551b | 3561 | break; |
f509f9c1 | 3562 | case 8: |
3b716933 | 3563 | dd->boardname = "InfiniPath_QME7362"; |
f509f9c1 MM |
3564 | dd->flags |= QIB_HAS_QSFP; |
3565 | break; | |
0e6bbba5 | 3566 | case BOARD_QMH7360: |
3b716933 | 3567 | dd->boardname = "Intel IB QDR 1P FLR-QSFP Adptr"; |
0e6bbba5 VA |
3568 | dd->flags |= QIB_HAS_QSFP; |
3569 | break; | |
f931551b | 3570 | case 15: |
3b716933 | 3571 | dd->boardname = "InfiniPath_QLE7342_TEST"; |
f931551b RC |
3572 | dd->flags |= QIB_HAS_QSFP; |
3573 | break; | |
3574 | default: | |
3b716933 | 3575 | dd->boardname = "InfiniPath_QLE73xy_UNKNOWN"; |
f931551b RC |
3576 | qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid); |
3577 | break; | |
3578 | } | |
3579 | dd->board_atten = 1; /* index into txdds_Xdr */ | |
3580 | ||
f931551b RC |
3581 | snprintf(dd->boardversion, sizeof(dd->boardversion), |
3582 | "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n", | |
3583 | QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, | |
3b716933 | 3584 | (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch), |
f931551b | 3585 | dd->majrev, dd->minrev, |
3b716933 | 3586 | (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW)); |
f931551b RC |
3587 | |
3588 | if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) { | |
7fac3301 | 3589 | qib_devinfo(dd->pcidev, |
3b716933 KA |
3590 | "IB%u: Forced to single port mode by module parameter\n", |
3591 | dd->unit); | |
f931551b RC |
3592 | features &= PORT_SPD_CAP; |
3593 | } | |
3594 | ||
3595 | return features; | |
3596 | } | |
3597 | ||
3598 | /* | |
3599 | * This routine sleeps, so it can only be called from user context, not | |
3600 | * from interrupt context. | |
3601 | */ | |
3602 | static int qib_do_7322_reset(struct qib_devdata *dd) | |
3603 | { | |
3604 | u64 val; | |
c40a83b9 | 3605 | u64 *msix_vecsave = NULL; |
f931551b RC |
3606 | int i, msix_entries, ret = 1; |
3607 | u16 cmdval; | |
3608 | u8 int_line, clinesz; | |
3609 | unsigned long flags; | |
3610 | ||
3611 | /* Use dev_err so it shows up in logs, etc. */ | |
3612 | qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); | |
3613 | ||
3614 | qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz); | |
3615 | ||
3616 | msix_entries = dd->cspec->num_msix_entries; | |
3617 | ||
3618 | /* no interrupts till re-initted */ | |
3619 | qib_7322_set_intr_state(dd, 0); | |
3620 | ||
c4bc6156 MR |
3621 | qib_7322_free_irq(dd); |
3622 | ||
f931551b | 3623 | if (msix_entries) { |
f931551b | 3624 | /* can be up to 512 bytes, too big for stack */ |
6da2ec56 KC |
3625 | msix_vecsave = kmalloc_array(2 * dd->cspec->num_msix_entries, |
3626 | sizeof(u64), | |
3627 | GFP_KERNEL); | |
c40a83b9 | 3628 | } |
f931551b RC |
3629 | |
3630 | /* | |
3631 | * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector | |
3632 | * info that is set up by the BIOS, so we have to save and restore | |
3633 | * it ourselves. There is some risk something could change it, | |
3634 | * after we save it, but since we have disabled the MSIx, it | |
3635 | * shouldn't be touched... | |
3636 | */ | |
3637 | for (i = 0; i < msix_entries; i++) { | |
3638 | u64 vecaddr, vecdata; | |
da12c1f6 | 3639 | |
f931551b RC |
3640 | vecaddr = qib_read_kreg64(dd, 2 * i + |
3641 | (QIB_7322_MsixTable_OFFS / sizeof(u64))); | |
3642 | vecdata = qib_read_kreg64(dd, 1 + 2 * i + | |
3643 | (QIB_7322_MsixTable_OFFS / sizeof(u64))); | |
3644 | if (msix_vecsave) { | |
3645 | msix_vecsave[2 * i] = vecaddr; | |
3646 | /* save it without the masked bit set */ | |
3647 | msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL; | |
3648 | } | |
3649 | } | |
3650 | ||
3651 | dd->pport->cpspec->ibdeltainprog = 0; | |
3652 | dd->pport->cpspec->ibsymdelta = 0; | |
3653 | dd->pport->cpspec->iblnkerrdelta = 0; | |
3654 | dd->pport->cpspec->ibmalfdelta = 0; | |
1ed88dd7 MM |
3655 | /* so we check interrupts work again */ |
3656 | dd->z_int_counter = qib_int_counter(dd); | |
f931551b RC |
3657 | |
3658 | /* | |
3659 | * Keep chip from being accessed until we are ready. Use | |
3660 | * writeq() directly, to allow the write even though QIB_PRESENT | |
e9c54999 | 3661 | * isn't set. |
f931551b RC |
3662 | */ |
3663 | dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR); | |
3664 | dd->flags |= QIB_DOING_RESET; | |
3665 | val = dd->control | QLOGIC_IB_C_RESET; | |
3666 | writeq(val, &dd->kregbase[kr_control]); | |
3667 | ||
3668 | for (i = 1; i <= 5; i++) { | |
3669 | /* | |
3670 | * Allow MBIST, etc. to complete; longer on each retry. | |
3671 | * We sometimes get machine checks from bus timeout if no | |
3672 | * response, so for now, make it *really* long. | |
3673 | */ | |
3674 | msleep(1000 + (1 + i) * 3000); | |
3675 | ||
3676 | qib_pcie_reenable(dd, cmdval, int_line, clinesz); | |
3677 | ||
3678 | /* | |
3679 | * Use readq directly, so we don't need to mark it as PRESENT | |
3680 | * until we get a successful indication that all is well. | |
3681 | */ | |
3682 | val = readq(&dd->kregbase[kr_revision]); | |
3683 | if (val == dd->revision) | |
3684 | break; | |
3685 | if (i == 5) { | |
7fac3301 MM |
3686 | qib_dev_err(dd, |
3687 | "Failed to initialize after reset, unusable\n"); | |
f931551b RC |
3688 | ret = 0; |
3689 | goto bail; | |
3690 | } | |
3691 | } | |
3692 | ||
3693 | dd->flags |= QIB_PRESENT; /* it's back */ | |
3694 | ||
3695 | if (msix_entries) { | |
3696 | /* restore the MSIx vector address and data if saved above */ | |
3697 | for (i = 0; i < msix_entries; i++) { | |
f931551b RC |
3698 | if (!msix_vecsave || !msix_vecsave[2 * i]) |
3699 | continue; | |
3700 | qib_write_kreg(dd, 2 * i + | |
3701 | (QIB_7322_MsixTable_OFFS / sizeof(u64)), | |
3702 | msix_vecsave[2 * i]); | |
3703 | qib_write_kreg(dd, 1 + 2 * i + | |
3704 | (QIB_7322_MsixTable_OFFS / sizeof(u64)), | |
3705 | msix_vecsave[1 + 2 * i]); | |
3706 | } | |
3707 | } | |
3708 | ||
3709 | /* initialize the remaining registers. */ | |
3710 | for (i = 0; i < dd->num_pports; ++i) | |
3711 | write_7322_init_portregs(&dd->pport[i]); | |
3712 | write_7322_initregs(dd); | |
3713 | ||
c4bc6156 | 3714 | if (qib_pcie_params(dd, dd->lbus_width, &msix_entries)) |
7fac3301 MM |
3715 | qib_dev_err(dd, |
3716 | "Reset failed to setup PCIe or interrupts; continuing anyway\n"); | |
f931551b | 3717 | |
c4bc6156 | 3718 | dd->cspec->num_msix_entries = msix_entries; |
f931551b RC |
3719 | qib_setup_7322_interrupt(dd, 1); |
3720 | ||
3721 | for (i = 0; i < dd->num_pports; ++i) { | |
3722 | struct qib_pportdata *ppd = &dd->pport[i]; | |
3723 | ||
3724 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
3725 | ppd->lflags |= QIBL_IB_FORCE_NOTIFY; | |
3726 | ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; | |
3727 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
3728 | } | |
3729 | ||
3730 | bail: | |
3731 | dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */ | |
3732 | kfree(msix_vecsave); | |
3733 | return ret; | |
3734 | } | |
3735 | ||
3736 | /** | |
3737 | * qib_7322_put_tid - write a TID to the chip | |
3738 | * @dd: the qlogic_ib device | |
3739 | * @tidptr: pointer to the expected TID (in chip) to update | |
a8a47b16 | 3740 | * @type: 0 for eager, 1 for expected |
f931551b RC |
3741 | * @pa: physical address of in memory buffer; tidinvalid if freeing |
3742 | */ | |
3743 | static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, | |
3744 | u32 type, unsigned long pa) | |
3745 | { | |
3746 | if (!(dd->flags & QIB_PRESENT)) | |
3747 | return; | |
3748 | if (pa != dd->tidinvalid) { | |
3749 | u64 chippa = pa >> IBA7322_TID_PA_SHIFT; | |
3750 | ||
3751 | /* paranoia checks */ | |
3752 | if (pa != (chippa << IBA7322_TID_PA_SHIFT)) { | |
3753 | qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", | |
3754 | pa); | |
3755 | return; | |
3756 | } | |
3757 | if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) { | |
7fac3301 MM |
3758 | qib_dev_err(dd, |
3759 | "Physical page address 0x%lx larger than supported\n", | |
3760 | pa); | |
f931551b RC |
3761 | return; |
3762 | } | |
3763 | ||
3764 | if (type == RCVHQ_RCV_TYPE_EAGER) | |
3765 | chippa |= dd->tidtemplate; | |
3766 | else /* for now, always full 4KB page */ | |
3767 | chippa |= IBA7322_TID_SZ_4K; | |
3768 | pa = chippa; | |
3769 | } | |
3770 | writeq(pa, tidptr); | |
f931551b RC |
3771 | } |
3772 | ||
3773 | /** | |
3774 | * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager | |
3775 | * @dd: the qlogic_ib device | |
a8a47b16 | 3776 | * @rcd: the ctxt |
f931551b RC |
3777 | * |
3778 | * clear all TID entries for a ctxt, expected and eager. | |
3779 | * Used from qib_close(). | |
3780 | */ | |
3781 | static void qib_7322_clear_tids(struct qib_devdata *dd, | |
3782 | struct qib_ctxtdata *rcd) | |
3783 | { | |
3784 | u64 __iomem *tidbase; | |
3785 | unsigned long tidinv; | |
3786 | u32 ctxt; | |
3787 | int i; | |
3788 | ||
3789 | if (!dd->kregbase || !rcd) | |
3790 | return; | |
3791 | ||
3792 | ctxt = rcd->ctxt; | |
3793 | ||
3794 | tidinv = dd->tidinvalid; | |
3795 | tidbase = (u64 __iomem *) | |
3796 | ((char __iomem *) dd->kregbase + | |
3797 | dd->rcvtidbase + | |
3798 | ctxt * dd->rcvtidcnt * sizeof(*tidbase)); | |
3799 | ||
3800 | for (i = 0; i < dd->rcvtidcnt; i++) | |
3801 | qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, | |
3802 | tidinv); | |
3803 | ||
3804 | tidbase = (u64 __iomem *) | |
3805 | ((char __iomem *) dd->kregbase + | |
3806 | dd->rcvegrbase + | |
3807 | rcd->rcvegr_tid_base * sizeof(*tidbase)); | |
3808 | ||
3809 | for (i = 0; i < rcd->rcvegrcnt; i++) | |
3810 | qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, | |
3811 | tidinv); | |
3812 | } | |
3813 | ||
3814 | /** | |
3815 | * qib_7322_tidtemplate - setup constants for TID updates | |
3816 | * @dd: the qlogic_ib device | |
3817 | * | |
3818 | * We setup stuff that we use a lot, to avoid calculating each time | |
3819 | */ | |
3820 | static void qib_7322_tidtemplate(struct qib_devdata *dd) | |
3821 | { | |
3822 | /* | |
3823 | * For now, we always allocate 4KB buffers (at init) so we can | |
3824 | * receive max size packets. We may want a module parameter to | |
3825 | * specify 2KB or 4KB and/or make it per port instead of per device | |
3826 | * for those who want to reduce memory footprint. Note that the | |
3827 | * rcvhdrentsize size must be large enough to hold the largest | |
3828 | * IB header (currently 96 bytes) that we expect to handle (plus of | |
3829 | * course the 2 dwords of RHF). | |
3830 | */ | |
3831 | if (dd->rcvegrbufsize == 2048) | |
3832 | dd->tidtemplate = IBA7322_TID_SZ_2K; | |
3833 | else if (dd->rcvegrbufsize == 4096) | |
3834 | dd->tidtemplate = IBA7322_TID_SZ_4K; | |
3835 | dd->tidinvalid = 0; | |
3836 | } | |
3837 | ||
3838 | /** | |
ae360f41 | 3839 | * qib_7322_get_base_info - set chip-specific flags for user code |
f931551b | 3840 | * @rcd: the qlogic_ib ctxt |
a8a47b16 | 3841 | * @kinfo: qib_base_info pointer |
f931551b RC |
3842 | * |
3843 | * We set the PCIE flag because the lower bandwidth on PCIe vs | |
3844 | * HyperTransport can affect some user packet algorithims. | |
3845 | */ | |
3846 | ||
3847 | static int qib_7322_get_base_info(struct qib_ctxtdata *rcd, | |
3848 | struct qib_base_info *kinfo) | |
3849 | { | |
3850 | kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP | | |
3851 | QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL | | |
3852 | QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA; | |
3853 | if (rcd->dd->cspec->r1) | |
3854 | kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK; | |
3855 | if (rcd->dd->flags & QIB_USE_SPCL_TRIG) | |
3856 | kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER; | |
3857 | ||
3858 | return 0; | |
3859 | } | |
3860 | ||
3861 | static struct qib_message_header * | |
3862 | qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) | |
3863 | { | |
3864 | u32 offset = qib_hdrget_offset(rhf_addr); | |
3865 | ||
3866 | return (struct qib_message_header *) | |
3867 | (rhf_addr - dd->rhf_offset + offset); | |
3868 | } | |
3869 | ||
3870 | /* | |
3871 | * Configure number of contexts. | |
3872 | */ | |
3873 | static void qib_7322_config_ctxts(struct qib_devdata *dd) | |
3874 | { | |
3875 | unsigned long flags; | |
3876 | u32 nchipctxts; | |
3877 | ||
3878 | nchipctxts = qib_read_kreg32(dd, kr_contextcnt); | |
3879 | dd->cspec->numctxts = nchipctxts; | |
3880 | if (qib_n_krcv_queues > 1 && dd->num_pports) { | |
f931551b RC |
3881 | dd->first_user_ctxt = NUM_IB_PORTS + |
3882 | (qib_n_krcv_queues - 1) * dd->num_pports; | |
3883 | if (dd->first_user_ctxt > nchipctxts) | |
3884 | dd->first_user_ctxt = nchipctxts; | |
3885 | dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports; | |
3886 | } else { | |
3887 | dd->first_user_ctxt = NUM_IB_PORTS; | |
3888 | dd->n_krcv_queues = 1; | |
3889 | } | |
3890 | ||
3891 | if (!qib_cfgctxts) { | |
3892 | int nctxts = dd->first_user_ctxt + num_online_cpus(); | |
3893 | ||
3894 | if (nctxts <= 6) | |
3895 | dd->ctxtcnt = 6; | |
3896 | else if (nctxts <= 10) | |
3897 | dd->ctxtcnt = 10; | |
3898 | else if (nctxts <= nchipctxts) | |
3899 | dd->ctxtcnt = nchipctxts; | |
3900 | } else if (qib_cfgctxts < dd->num_pports) | |
3901 | dd->ctxtcnt = dd->num_pports; | |
3902 | else if (qib_cfgctxts <= nchipctxts) | |
3903 | dd->ctxtcnt = qib_cfgctxts; | |
3904 | if (!dd->ctxtcnt) /* none of the above, set to max */ | |
3905 | dd->ctxtcnt = nchipctxts; | |
3906 | ||
3907 | /* | |
3908 | * Chip can be configured for 6, 10, or 18 ctxts, and choice | |
3909 | * affects number of eager TIDs per ctxt (1K, 2K, 4K). | |
3910 | * Lock to be paranoid about later motion, etc. | |
3911 | */ | |
3912 | spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); | |
3913 | if (dd->ctxtcnt > 10) | |
3914 | dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg); | |
3915 | else if (dd->ctxtcnt > 6) | |
3916 | dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg); | |
3917 | /* else configure for default 6 receive ctxts */ | |
3918 | ||
3919 | /* The XRC opcode is 5. */ | |
3920 | dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode); | |
3921 | ||
3922 | /* | |
3923 | * RcvCtrl *must* be written here so that the | |
3924 | * chip understands how to change rcvegrcnt below. | |
3925 | */ | |
3926 | qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); | |
3927 | spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); | |
3928 | ||
3929 | /* kr_rcvegrcnt changes based on the number of contexts enabled */ | |
3930 | dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); | |
0a43e117 MM |
3931 | if (qib_rcvhdrcnt) |
3932 | dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); | |
3933 | else | |
8d4548f2 | 3934 | dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt, |
0a43e117 | 3935 | dd->num_pports > 1 ? 1024U : 2048U); |
f931551b RC |
3936 | } |
3937 | ||
3938 | static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which) | |
3939 | { | |
3940 | ||
3941 | int lsb, ret = 0; | |
3942 | u64 maskr; /* right-justified mask */ | |
3943 | ||
3944 | switch (which) { | |
3945 | ||
3946 | case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */ | |
3947 | ret = ppd->link_width_enabled; | |
3948 | goto done; | |
3949 | ||
3950 | case QIB_IB_CFG_LWID: /* Get currently active Link-width */ | |
3951 | ret = ppd->link_width_active; | |
3952 | goto done; | |
3953 | ||
3954 | case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */ | |
3955 | ret = ppd->link_speed_enabled; | |
3956 | goto done; | |
3957 | ||
3958 | case QIB_IB_CFG_SPD: /* Get current Link spd */ | |
3959 | ret = ppd->link_speed_active; | |
3960 | goto done; | |
3961 | ||
3962 | case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */ | |
3963 | lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); | |
3964 | maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP); | |
3965 | break; | |
3966 | ||
3967 | case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */ | |
3968 | lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); | |
3969 | maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); | |
3970 | break; | |
3971 | ||
3972 | case QIB_IB_CFG_LINKLATENCY: | |
3973 | ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) & | |
3974 | SYM_MASK(IBCStatusB_0, LinkRoundTripLatency); | |
3975 | goto done; | |
3976 | ||
3977 | case QIB_IB_CFG_OP_VLS: | |
3978 | ret = ppd->vls_operational; | |
3979 | goto done; | |
3980 | ||
3981 | case QIB_IB_CFG_VL_HIGH_CAP: | |
3982 | ret = 16; | |
3983 | goto done; | |
3984 | ||
3985 | case QIB_IB_CFG_VL_LOW_CAP: | |
3986 | ret = 16; | |
3987 | goto done; | |
3988 | ||
3989 | case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ | |
3990 | ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, | |
3991 | OverrunThreshold); | |
3992 | goto done; | |
3993 | ||
3994 | case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ | |
3995 | ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, | |
3996 | PhyerrThreshold); | |
3997 | goto done; | |
3998 | ||
3999 | case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ | |
4000 | /* will only take effect when the link state changes */ | |
4001 | ret = (ppd->cpspec->ibcctrl_a & | |
4002 | SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ? | |
4003 | IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL; | |
4004 | goto done; | |
4005 | ||
4006 | case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */ | |
4007 | lsb = IBA7322_IBC_HRTBT_LSB; | |
4008 | maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */ | |
4009 | break; | |
4010 | ||
4011 | case QIB_IB_CFG_PMA_TICKS: | |
4012 | /* | |
4013 | * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs | |
4014 | * Since the clock is always 250MHz, the value is 3, 1 or 0. | |
4015 | */ | |
4016 | if (ppd->link_speed_active == QIB_IB_QDR) | |
4017 | ret = 3; | |
4018 | else if (ppd->link_speed_active == QIB_IB_DDR) | |
4019 | ret = 1; | |
4020 | else | |
4021 | ret = 0; | |
4022 | goto done; | |
4023 | ||
4024 | default: | |
4025 | ret = -EINVAL; | |
4026 | goto done; | |
4027 | } | |
4028 | ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr); | |
4029 | done: | |
4030 | return ret; | |
4031 | } | |
4032 | ||
4033 | /* | |
4034 | * Below again cribbed liberally from older version. Do not lean | |
4035 | * heavily on it. | |
4036 | */ | |
4037 | #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB | |
4038 | #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \ | |
4039 | | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16)) | |
4040 | ||
4041 | static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) | |
4042 | { | |
4043 | struct qib_devdata *dd = ppd->dd; | |
4044 | u64 maskr; /* right-justified mask */ | |
4045 | int lsb, ret = 0; | |
4046 | u16 lcmd, licmd; | |
4047 | unsigned long flags; | |
4048 | ||
4049 | switch (which) { | |
4050 | case QIB_IB_CFG_LIDLMC: | |
4051 | /* | |
4052 | * Set LID and LMC. Combined to avoid possible hazard | |
4053 | * caller puts LMC in 16MSbits, DLID in 16LSbits of val | |
4054 | */ | |
4055 | lsb = IBA7322_IBC_DLIDLMC_SHIFT; | |
4056 | maskr = IBA7322_IBC_DLIDLMC_MASK; | |
4057 | /* | |
4058 | * For header-checking, the SLID in the packet will | |
4059 | * be masked with SendIBSLMCMask, and compared | |
4060 | * with SendIBSLIDAssignMask. Make sure we do not | |
4061 | * set any bits not covered by the mask, or we get | |
4062 | * false-positives. | |
4063 | */ | |
4064 | qib_write_kreg_port(ppd, krp_sendslid, | |
4065 | val & (val >> 16) & SendIBSLIDAssignMask); | |
4066 | qib_write_kreg_port(ppd, krp_sendslidmask, | |
4067 | (val >> 16) & SendIBSLMCMask); | |
4068 | break; | |
4069 | ||
4070 | case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */ | |
4071 | ppd->link_width_enabled = val; | |
4072 | /* convert IB value to chip register value */ | |
4073 | if (val == IB_WIDTH_1X) | |
4074 | val = 0; | |
4075 | else if (val == IB_WIDTH_4X) | |
4076 | val = 1; | |
4077 | else | |
4078 | val = 3; | |
4079 | maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS); | |
4080 | lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS); | |
4081 | break; | |
4082 | ||
4083 | case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */ | |
4084 | /* | |
4085 | * As with width, only write the actual register if the | |
4086 | * link is currently down, otherwise takes effect on next | |
25985edc | 4087 | * link change. Since setting is being explicitly requested |
f931551b RC |
4088 | * (via MAD or sysfs), clear autoneg failure status if speed |
4089 | * autoneg is enabled. | |
4090 | */ | |
4091 | ppd->link_speed_enabled = val; | |
4092 | val <<= IBA7322_IBC_SPEED_LSB; | |
4093 | maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK | | |
4094 | IBA7322_IBC_MAX_SPEED_MASK; | |
4095 | if (val & (val - 1)) { | |
4096 | /* Muliple speeds enabled */ | |
4097 | val |= IBA7322_IBC_IBTA_1_2_MASK | | |
4098 | IBA7322_IBC_MAX_SPEED_MASK; | |
4099 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
4100 | ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; | |
4101 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
4102 | } else if (val & IBA7322_IBC_SPEED_QDR) | |
4103 | val |= IBA7322_IBC_IBTA_1_2_MASK; | |
4104 | /* IBTA 1.2 mode + min/max + speed bits are contiguous */ | |
4105 | lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE); | |
4106 | break; | |
4107 | ||
4108 | case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */ | |
4109 | lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); | |
4110 | maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP); | |
4111 | break; | |
4112 | ||
4113 | case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */ | |
4114 | lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); | |
4115 | maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); | |
4116 | break; | |
4117 | ||
4118 | case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ | |
4119 | maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, | |
4120 | OverrunThreshold); | |
4121 | if (maskr != val) { | |
4122 | ppd->cpspec->ibcctrl_a &= | |
4123 | ~SYM_MASK(IBCCtrlA_0, OverrunThreshold); | |
4124 | ppd->cpspec->ibcctrl_a |= (u64) val << | |
4125 | SYM_LSB(IBCCtrlA_0, OverrunThreshold); | |
4126 | qib_write_kreg_port(ppd, krp_ibcctrl_a, | |
4127 | ppd->cpspec->ibcctrl_a); | |
4128 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
4129 | } | |
4130 | goto bail; | |
4131 | ||
4132 | case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ | |
4133 | maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, | |
4134 | PhyerrThreshold); | |
4135 | if (maskr != val) { | |
4136 | ppd->cpspec->ibcctrl_a &= | |
4137 | ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold); | |
4138 | ppd->cpspec->ibcctrl_a |= (u64) val << | |
4139 | SYM_LSB(IBCCtrlA_0, PhyerrThreshold); | |
4140 | qib_write_kreg_port(ppd, krp_ibcctrl_a, | |
4141 | ppd->cpspec->ibcctrl_a); | |
4142 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
4143 | } | |
4144 | goto bail; | |
4145 | ||
4146 | case QIB_IB_CFG_PKEYS: /* update pkeys */ | |
4147 | maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) | | |
4148 | ((u64) ppd->pkeys[2] << 32) | | |
4149 | ((u64) ppd->pkeys[3] << 48); | |
4150 | qib_write_kreg_port(ppd, krp_partitionkey, maskr); | |
4151 | goto bail; | |
4152 | ||
4153 | case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ | |
4154 | /* will only take effect when the link state changes */ | |
4155 | if (val == IB_LINKINITCMD_POLL) | |
4156 | ppd->cpspec->ibcctrl_a &= | |
4157 | ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); | |
4158 | else /* SLEEP */ | |
4159 | ppd->cpspec->ibcctrl_a |= | |
4160 | SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); | |
4161 | qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); | |
4162 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
4163 | goto bail; | |
4164 | ||
4165 | case QIB_IB_CFG_MTU: /* update the MTU in IBC */ | |
4166 | /* | |
4167 | * Update our housekeeping variables, and set IBC max | |
4168 | * size, same as init code; max IBC is max we allow in | |
4169 | * buffer, less the qword pbc, plus 1 for ICRC, in dwords | |
4170 | * Set even if it's unchanged, print debug message only | |
4171 | * on changes. | |
4172 | */ | |
4173 | val = (ppd->ibmaxlen >> 2) + 1; | |
4174 | ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen); | |
4175 | ppd->cpspec->ibcctrl_a |= (u64)val << | |
4176 | SYM_LSB(IBCCtrlA_0, MaxPktLen); | |
4177 | qib_write_kreg_port(ppd, krp_ibcctrl_a, | |
4178 | ppd->cpspec->ibcctrl_a); | |
4179 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
4180 | goto bail; | |
4181 | ||
4182 | case QIB_IB_CFG_LSTATE: /* set the IB link state */ | |
4183 | switch (val & 0xffff0000) { | |
4184 | case IB_LINKCMD_DOWN: | |
4185 | lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN; | |
4186 | ppd->cpspec->ibmalfusesnap = 1; | |
4187 | ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, | |
4188 | crp_errlink); | |
4189 | if (!ppd->cpspec->ibdeltainprog && | |
4190 | qib_compat_ddr_negotiate) { | |
4191 | ppd->cpspec->ibdeltainprog = 1; | |
4192 | ppd->cpspec->ibsymsnap = | |
4193 | read_7322_creg32_port(ppd, | |
4194 | crp_ibsymbolerr); | |
4195 | ppd->cpspec->iblnkerrsnap = | |
4196 | read_7322_creg32_port(ppd, | |
4197 | crp_iblinkerrrecov); | |
4198 | } | |
4199 | break; | |
4200 | ||
4201 | case IB_LINKCMD_ARMED: | |
4202 | lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED; | |
4203 | if (ppd->cpspec->ibmalfusesnap) { | |
4204 | ppd->cpspec->ibmalfusesnap = 0; | |
4205 | ppd->cpspec->ibmalfdelta += | |
4206 | read_7322_creg32_port(ppd, | |
4207 | crp_errlink) - | |
4208 | ppd->cpspec->ibmalfsnap; | |
4209 | } | |
4210 | break; | |
4211 | ||
4212 | case IB_LINKCMD_ACTIVE: | |
4213 | lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE; | |
4214 | break; | |
4215 | ||
4216 | default: | |
4217 | ret = -EINVAL; | |
4218 | qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); | |
4219 | goto bail; | |
4220 | } | |
4221 | switch (val & 0xffff) { | |
4222 | case IB_LINKINITCMD_NOP: | |
4223 | licmd = 0; | |
4224 | break; | |
4225 | ||
4226 | case IB_LINKINITCMD_POLL: | |
4227 | licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL; | |
4228 | break; | |
4229 | ||
4230 | case IB_LINKINITCMD_SLEEP: | |
4231 | licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP; | |
4232 | break; | |
4233 | ||
4234 | case IB_LINKINITCMD_DISABLE: | |
4235 | licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE; | |
4236 | ppd->cpspec->chase_end = 0; | |
4237 | /* | |
4238 | * stop state chase counter and timer, if running. | |
4239 | * wait forpending timer, but don't clear .data (ppd)! | |
4240 | */ | |
4241 | if (ppd->cpspec->chase_timer.expires) { | |
4242 | del_timer_sync(&ppd->cpspec->chase_timer); | |
4243 | ppd->cpspec->chase_timer.expires = 0; | |
4244 | } | |
4245 | break; | |
4246 | ||
4247 | default: | |
4248 | ret = -EINVAL; | |
4249 | qib_dev_err(dd, "bad linkinitcmd req 0x%x\n", | |
4250 | val & 0xffff); | |
4251 | goto bail; | |
4252 | } | |
4253 | qib_set_ib_7322_lstate(ppd, lcmd, licmd); | |
4254 | goto bail; | |
4255 | ||
4256 | case QIB_IB_CFG_OP_VLS: | |
4257 | if (ppd->vls_operational != val) { | |
4258 | ppd->vls_operational = val; | |
4259 | set_vls(ppd); | |
4260 | } | |
4261 | goto bail; | |
4262 | ||
4263 | case QIB_IB_CFG_VL_HIGH_LIMIT: | |
4264 | qib_write_kreg_port(ppd, krp_highprio_limit, val); | |
4265 | goto bail; | |
4266 | ||
4267 | case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */ | |
4268 | if (val > 3) { | |
4269 | ret = -EINVAL; | |
4270 | goto bail; | |
4271 | } | |
4272 | lsb = IBA7322_IBC_HRTBT_LSB; | |
4273 | maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */ | |
4274 | break; | |
4275 | ||
4276 | case QIB_IB_CFG_PORT: | |
4277 | /* val is the port number of the switch we are connected to. */ | |
4278 | if (ppd->dd->cspec->r1) { | |
4279 | cancel_delayed_work(&ppd->cpspec->ipg_work); | |
4280 | ppd->cpspec->ipg_tries = 0; | |
4281 | } | |
4282 | goto bail; | |
4283 | ||
4284 | default: | |
4285 | ret = -EINVAL; | |
4286 | goto bail; | |
4287 | } | |
4288 | ppd->cpspec->ibcctrl_b &= ~(maskr << lsb); | |
4289 | ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb); | |
4290 | qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); | |
4291 | qib_write_kreg(dd, kr_scratch, 0); | |
4292 | bail: | |
4293 | return ret; | |
4294 | } | |
4295 | ||
4296 | static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what) | |
4297 | { | |
4298 | int ret = 0; | |
4299 | u64 val, ctrlb; | |
4300 | ||
4301 | /* only IBC loopback, may add serdes and xgxs loopbacks later */ | |
4302 | if (!strncmp(what, "ibc", 3)) { | |
4303 | ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, | |
4304 | Loopback); | |
4305 | val = 0; /* disable heart beat, so link will come up */ | |
4306 | qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", | |
4307 | ppd->dd->unit, ppd->port); | |
4308 | } else if (!strncmp(what, "off", 3)) { | |
4309 | ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, | |
4310 | Loopback); | |
4311 | /* enable heart beat again */ | |
4312 | val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB; | |
7fac3301 MM |
4313 | qib_devinfo(ppd->dd->pcidev, |
4314 | "Disabling IB%u:%u IBC loopback (normal)\n", | |
4315 | ppd->dd->unit, ppd->port); | |
f931551b RC |
4316 | } else |
4317 | ret = -EINVAL; | |
4318 | if (!ret) { | |
4319 | qib_write_kreg_port(ppd, krp_ibcctrl_a, | |
4320 | ppd->cpspec->ibcctrl_a); | |
4321 | ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK | |
4322 | << IBA7322_IBC_HRTBT_LSB); | |
4323 | ppd->cpspec->ibcctrl_b = ctrlb | val; | |
4324 | qib_write_kreg_port(ppd, krp_ibcctrl_b, | |
4325 | ppd->cpspec->ibcctrl_b); | |
4326 | qib_write_kreg(ppd->dd, kr_scratch, 0); | |
4327 | } | |
4328 | return ret; | |
4329 | } | |
4330 | ||
4331 | static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno, | |
4332 | struct ib_vl_weight_elem *vl) | |
4333 | { | |
4334 | unsigned i; | |
4335 | ||
4336 | for (i = 0; i < 16; i++, regno++, vl++) { | |
4337 | u32 val = qib_read_kreg_port(ppd, regno); | |
4338 | ||
4339 | vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) & | |
4340 | SYM_RMASK(LowPriority0_0, VirtualLane); | |
4341 | vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) & | |
4342 | SYM_RMASK(LowPriority0_0, Weight); | |
4343 | } | |
4344 | } | |
4345 | ||
4346 | static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno, | |
4347 | struct ib_vl_weight_elem *vl) | |
4348 | { | |
4349 | unsigned i; | |
4350 | ||
4351 | for (i = 0; i < 16; i++, regno++, vl++) { | |
4352 | u64 val; | |
4353 | ||
4354 | val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) << | |
4355 | SYM_LSB(LowPriority0_0, VirtualLane)) | | |
4356 | ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) << | |
4357 | SYM_LSB(LowPriority0_0, Weight)); | |
4358 | qib_write_kreg_port(ppd, regno, val); | |
4359 | } | |
4360 | if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) { | |
4361 | struct qib_devdata *dd = ppd->dd; | |
4362 | unsigned long flags; | |
4363 | ||
4364 | spin_lock_irqsave(&dd->sendctrl_lock, flags); | |
4365 | ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn); | |
4366 | qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); | |
4367 | qib_write_kreg(dd, kr_scratch, 0); | |
4368 | spin_unlock_irqrestore(&dd->sendctrl_lock, flags); | |
4369 | } | |
4370 | } | |
4371 | ||
4372 | static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t) | |
4373 | { | |
4374 | switch (which) { | |
4375 | case QIB_IB_TBL_VL_HIGH_ARB: | |
4376 | get_vl_weights(ppd, krp_highprio_0, t); | |
4377 | break; | |
4378 | ||
4379 | case QIB_IB_TBL_VL_LOW_ARB: | |
4380 | get_vl_weights(ppd, krp_lowprio_0, t); | |
4381 | break; | |
4382 | ||
4383 | default: | |
4384 | return -EINVAL; | |
4385 | } | |
4386 | return 0; | |
4387 | } | |
4388 | ||
4389 | static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t) | |
4390 | { | |
4391 | switch (which) { | |
4392 | case QIB_IB_TBL_VL_HIGH_ARB: | |
4393 | set_vl_weights(ppd, krp_highprio_0, t); | |
4394 | break; | |
4395 | ||
4396 | case QIB_IB_TBL_VL_LOW_ARB: | |
4397 | set_vl_weights(ppd, krp_lowprio_0, t); | |
4398 | break; | |
4399 | ||
4400 | default: | |
4401 | return -EINVAL; | |
4402 | } | |
4403 | return 0; | |
4404 | } | |
4405 | ||
4406 | static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd, | |
19ede2e4 | 4407 | u32 updegr, u32 egrhd, u32 npkts) |
f931551b | 4408 | { |
19ede2e4 MM |
4409 | /* |
4410 | * Need to write timeout register before updating rcvhdrhead to ensure | |
4411 | * that the timer is enabled on reception of a packet. | |
4412 | */ | |
4413 | if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT) | |
4414 | adjust_rcv_timeout(rcd, npkts); | |
f931551b RC |
4415 | if (updegr) |
4416 | qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); | |
eddfb675 RV |
4417 | qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); |
4418 | qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); | |
f931551b RC |
4419 | } |
4420 | ||
4421 | static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd) | |
4422 | { | |
4423 | u32 head, tail; | |
4424 | ||
4425 | head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); | |
4426 | if (rcd->rcvhdrtail_kvaddr) | |
4427 | tail = qib_get_rcvhdrtail(rcd); | |
4428 | else | |
4429 | tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); | |
4430 | return head == tail; | |
4431 | } | |
4432 | ||
4433 | #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \ | |
4434 | QIB_RCVCTRL_CTXT_DIS | \ | |
4435 | QIB_RCVCTRL_TIDFLOW_ENB | \ | |
4436 | QIB_RCVCTRL_TIDFLOW_DIS | \ | |
4437 | QIB_RCVCTRL_TAILUPD_ENB | \ | |
4438 | QIB_RCVCTRL_TAILUPD_DIS | \ | |
4439 | QIB_RCVCTRL_INTRAVAIL_ENB | \ | |
4440 | QIB_RCVCTRL_INTRAVAIL_DIS | \ | |
4441 | QIB_RCVCTRL_BP_ENB | \ | |
4442 | QIB_RCVCTRL_BP_DIS) | |
4443 | ||
4444 | #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \ | |
4445 | QIB_RCVCTRL_CTXT_DIS | \ | |
4446 | QIB_RCVCTRL_PKEY_DIS | \ | |
4447 | QIB_RCVCTRL_PKEY_ENB) | |
4448 | ||
4449 | /* | |
4450 | * Modify the RCVCTRL register in chip-specific way. This | |
4451 | * is a function because bit positions and (future) register | |
4452 | * location is chip-specifc, but the needed operations are | |
4453 | * generic. <op> is a bit-mask because we often want to | |
4454 | * do multiple modifications. | |
4455 | */ | |
4456 | static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op, | |
4457 | int ctxt) | |
4458 | { | |
4459 | struct qib_devdata *dd = ppd->dd; | |
4460 | struct qib_ctxtdata *rcd; | |
4461 | u64 mask, val; | |
4462 | unsigned long flags; | |
4463 | ||
4464 | spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); | |
4465 | ||
4466 | if (op & QIB_RCVCTRL_TIDFLOW_ENB) | |
4467 | dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable); | |
4468 | if (op & QIB_RCVCTRL_TIDFLOW_DIS) | |
4469 | dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable); | |
4470 | if (op & QIB_RCVCTRL_TAILUPD_ENB) | |
4471 | dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); | |
4472 | if (op & QIB_RCVCTRL_TAILUPD_DIS) | |
4473 | dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd); | |
4474 | if (op & QIB_RCVCTRL_PKEY_ENB) | |
4475 | ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); | |
4476 | if (op & QIB_RCVCTRL_PKEY_DIS) | |
4477 | ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); | |
4478 | if (ctxt < 0) { | |
4479 | mask = (1ULL << dd->ctxtcnt) - 1; | |
4480 | rcd = NULL; | |
4481 | } else { | |
4482 | mask = (1ULL << ctxt); | |
4483 | rcd = dd->rcd[ctxt]; | |
4484 | } | |
4485 | if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) { | |
4486 | ppd->p_rcvctrl |= | |
4487 | (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); | |
4488 | if (!(dd->flags & QIB_NODMA_RTAIL)) { | |
4489 | op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */ | |
4490 | dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); | |
4491 | } | |
4492 | /* Write these registers before the context is enabled. */ | |
4493 | qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, | |
4494 | rcd->rcvhdrqtailaddr_phys); | |
4495 | qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, | |
4496 | rcd->rcvhdrq_phys); | |
4497 | rcd->seq_cnt = 1; | |
f931551b RC |
4498 | } |
4499 | if (op & QIB_RCVCTRL_CTXT_DIS) | |
4500 | ppd->p_rcvctrl &= | |
4501 | ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); | |
4502 | if (op & QIB_RCVCTRL_BP_ENB) | |
4503 | dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); | |
4504 | if (op & QIB_RCVCTRL_BP_DIS) | |
4505 | dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); | |
4506 | if (op & QIB_RCVCTRL_INTRAVAIL_ENB) | |
4507 | dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); | |
4508 | if (op & QIB_RCVCTRL_INTRAVAIL_DIS) | |
4509 | dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); | |
4510 | /* | |
4511 | * Decide which registers to write depending on the ops enabled. | |
4512 | * Special case is "flush" (no bits set at all) | |
4513 | * which needs to write both. | |
4514 | */ | |
4515 | if (op == 0 || (op & RCVCTRL_COMMON_MODS)) | |
4516 | qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); | |
4517 | if (op == 0 || (op & RCVCTRL_PORT_MODS)) | |
4518 | qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); | |
4519 | if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) { | |
4520 | /* | |
4521 | * Init the context registers also; if we were | |
4522 | * disabled, tail and head should both be zero | |
4523 | * already from the enable, but since we don't | |
25985edc | 4524 | * know, we have to do it explicitly. |
f931551b RC |
4525 | */ |
4526 | val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); | |
4527 | qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); | |
4528 | ||
4529 | /* be sure enabling write seen; hd/tl should be 0 */ | |
4530 | (void) qib_read_kreg32(dd, kr_scratch); | |
4531 | val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); | |
4532 | dd->rcd[ctxt]->head = val; | |
4533 | /* If kctxt, interrupt on next receive. */ | |
4534 | if (ctxt < dd->first_user_ctxt) | |
4535 | val |= dd->rhdrhead_intr_off; | |
4536 | qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); | |
4537 | } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && | |
4538 | dd->rcd[ctxt] && dd->rhdrhead_intr_off) { | |
4539 | /* arm rcv interrupt */ | |
4540 | val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off; | |
4541 | qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); | |
4542 | } | |
4543 | if (op & QIB_RCVCTRL_CTXT_DIS) { | |
4544 | unsigned f; | |
4545 | ||
4546 | /* Now that the context is disabled, clear these registers. */ | |
4547 | if (ctxt >= 0) { | |
4548 | qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0); | |
4549 | qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0); | |
4550 | for (f = 0; f < NUM_TIDFLOWS_CTXT; f++) | |
4551 | qib_write_ureg(dd, ur_rcvflowtable + f, | |
4552 | TIDFLOW_ERRBITS, ctxt); | |
4553 | } else { | |
4554 | unsigned i; | |
4555 | ||
4556 | for (i = 0; i < dd->cfgctxts; i++) { | |
4557 | qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, | |
4558 | i, 0); | |
4559 | qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0); | |
4560 | for (f = 0; f < NUM_TIDFLOWS_CTXT; f++) | |
4561 | qib_write_ureg(dd, ur_rcvflowtable + f, | |
4562 | TIDFLOW_ERRBITS, i); | |
4563 | } | |
4564 | } | |
4565 | } | |
4566 | spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); | |
4567 | } | |
4568 | ||
4569 | /* | |
4570 | * Modify the SENDCTRL register in chip-specific way. This | |
4571 | * is a function where there are multiple such registers with | |
4572 | * slightly different layouts. | |
4573 | * The chip doesn't allow back-to-back sendctrl writes, so write | |
4574 | * the scratch register after writing sendctrl. | |
4575 | * | |
4576 | * Which register is written depends on the operation. | |
4577 | * Most operate on the common register, while | |
4578 | * SEND_ENB and SEND_DIS operate on the per-port ones. | |
4579 | * SEND_ENB is included in common because it can change SPCL_TRIG | |
4580 | */ | |
4581 | #define SENDCTRL_COMMON_MODS (\ | |
4582 | QIB_SENDCTRL_CLEAR | \ | |
4583 | QIB_SENDCTRL_AVAIL_DIS | \ | |
4584 | QIB_SENDCTRL_AVAIL_ENB | \ | |
4585 | QIB_SENDCTRL_AVAIL_BLIP | \ | |
4586 | QIB_SENDCTRL_DISARM | \ | |
4587 | QIB_SENDCTRL_DISARM_ALL | \ | |
4588 | QIB_SENDCTRL_SEND_ENB) | |
4589 | ||
4590 | #define SENDCTRL_PORT_MODS (\ | |
4591 | QIB_SENDCTRL_CLEAR | \ | |
4592 | QIB_SENDCTRL_SEND_ENB | \ | |
4593 | QIB_SENDCTRL_SEND_DIS | \ | |
4594 | QIB_SENDCTRL_FLUSH) | |
4595 | ||
4596 | static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op) | |
4597 | { | |
4598 | struct qib_devdata *dd = ppd->dd; | |
4599 | u64 tmp_dd_sendctrl; | |
4600 | unsigned long flags; | |
4601 | ||
4602 | spin_lock_irqsave(&dd->sendctrl_lock, flags); | |
4603 | ||
4604 | /* First the dd ones that are "sticky", saved in shadow */ | |
4605 | if (op & QIB_SENDCTRL_CLEAR) | |
4606 | dd->sendctrl = 0; | |
4607 | if (op & QIB_SENDCTRL_AVAIL_DIS) | |
4608 | dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); | |
4609 | else if (op & QIB_SENDCTRL_AVAIL_ENB) { | |
4610 | dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd); | |
4611 | if (dd->flags & QIB_USE_SPCL_TRIG) | |
4612 | dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn); | |
4613 | } | |
4614 | ||
4615 | /* Then the ppd ones that are "sticky", saved in shadow */ | |
4616 | if (op & QIB_SENDCTRL_SEND_DIS) | |
4617 | ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); | |
4618 | else if (op & QIB_SENDCTRL_SEND_ENB) | |
4619 | ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); | |
4620 | ||
4621 | if (op & QIB_SENDCTRL_DISARM_ALL) { | |
4622 | u32 i, last; | |
4623 | ||
4624 | tmp_dd_sendctrl = dd->sendctrl; | |
4625 | last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; | |
4626 | /* | |
4627 | * Disarm any buffers that are not yet launched, | |
4628 | * disabling updates until done. | |
4629 | */ | |
4630 | tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); | |
4631 | for (i = 0; i < last; i++) { | |
4632 | qib_write_kreg(dd, kr_sendctrl, | |
4633 | tmp_dd_sendctrl | | |
4634 | SYM_MASK(SendCtrl, Disarm) | i); | |
4635 | qib_write_kreg(dd, kr_scratch, 0); | |
4636 | } | |
4637 | } | |
4638 | ||
4639 | if (op & QIB_SENDCTRL_FLUSH) { | |
4640 | u64 tmp_ppd_sendctrl = ppd->p_sendctrl; | |
4641 | ||
4642 | /* | |
4643 | * Now drain all the fifos. The Abort bit should never be | |
4644 | * needed, so for now, at least, we don't use it. | |
4645 | */ | |
4646 | tmp_ppd_sendctrl |= | |
4647 | SYM_MASK(SendCtrl_0, TxeDrainRmFifo) | | |
4648 | SYM_MASK(SendCtrl_0, TxeDrainLaFifo) | | |
4649 | SYM_MASK(SendCtrl_0, TxeBypassIbc); | |
4650 | qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl); | |
4651 | qib_write_kreg(dd, kr_scratch, 0); | |
4652 | } | |
4653 | ||
4654 | tmp_dd_sendctrl = dd->sendctrl; | |
4655 | ||
4656 | if (op & QIB_SENDCTRL_DISARM) | |
4657 | tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) | | |
4658 | ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) << | |
4659 | SYM_LSB(SendCtrl, DisarmSendBuf)); | |
4660 | if ((op & QIB_SENDCTRL_AVAIL_BLIP) && | |
4661 | (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd))) | |
4662 | tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); | |
4663 | ||
4664 | if (op == 0 || (op & SENDCTRL_COMMON_MODS)) { | |
4665 | qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl); | |
4666 | qib_write_kreg(dd, kr_scratch, 0); | |
4667 | } | |
4668 | ||
4669 | if (op == 0 || (op & SENDCTRL_PORT_MODS)) { | |
4670 | qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); | |
4671 | qib_write_kreg(dd, kr_scratch, 0); | |
4672 | } | |
4673 | ||
4674 | if (op & QIB_SENDCTRL_AVAIL_BLIP) { | |
4675 | qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); | |
4676 | qib_write_kreg(dd, kr_scratch, 0); | |
4677 | } | |
4678 | ||
4679 | spin_unlock_irqrestore(&dd->sendctrl_lock, flags); | |
4680 | ||
4681 | if (op & QIB_SENDCTRL_FLUSH) { | |
4682 | u32 v; | |
4683 | /* | |
4684 | * ensure writes have hit chip, then do a few | |
4685 | * more reads, to allow DMA of pioavail registers | |
4686 | * to occur, so in-memory copy is in sync with | |
4687 | * the chip. Not always safe to sleep. | |
4688 | */ | |
4689 | v = qib_read_kreg32(dd, kr_scratch); | |
4690 | qib_write_kreg(dd, kr_scratch, v); | |
4691 | v = qib_read_kreg32(dd, kr_scratch); | |
4692 | qib_write_kreg(dd, kr_scratch, v); | |
4693 | qib_read_kreg32(dd, kr_scratch); | |
4694 | } | |
4695 | } | |
4696 | ||
4697 | #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */ | |
4698 | #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */ | |
4699 | #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */ | |
4700 | ||
4701 | /** | |
4702 | * qib_portcntr_7322 - read a per-port chip counter | |
4703 | * @ppd: the qlogic_ib pport | |
a8a47b16 | 4704 | * @reg: the counter to read (not a chip offset) |
f931551b RC |
4705 | */ |
4706 | static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg) | |
4707 | { | |
4708 | struct qib_devdata *dd = ppd->dd; | |
4709 | u64 ret = 0ULL; | |
4710 | u16 creg; | |
4711 | /* 0xffff for unimplemented or synthesized counters */ | |
4712 | static const u32 xlator[] = { | |
4713 | [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG, | |
4714 | [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG, | |
4715 | [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount, | |
4716 | [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount, | |
4717 | [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount, | |
4718 | [QIBPORTCNTR_SENDSTALL] = crp_sendstall, | |
4719 | [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG, | |
4720 | [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount, | |
4721 | [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount, | |
4722 | [QIBPORTCNTR_RCVEBP] = crp_rcvebp, | |
4723 | [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl, | |
4724 | [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG, | |
4725 | [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */ | |
4726 | [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr, | |
4727 | [QIBPORTCNTR_RXVLERR] = crp_rxvlerr, | |
4728 | [QIBPORTCNTR_ERRICRC] = crp_erricrc, | |
4729 | [QIBPORTCNTR_ERRVCRC] = crp_errvcrc, | |
4730 | [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc, | |
4731 | [QIBPORTCNTR_BADFORMAT] = crp_badformat, | |
4732 | [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen, | |
4733 | [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr, | |
4734 | [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen, | |
4735 | [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl, | |
4736 | [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl, | |
4737 | [QIBPORTCNTR_ERRLINK] = crp_errlink, | |
4738 | [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown, | |
4739 | [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov, | |
4740 | [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr, | |
4741 | [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt, | |
4742 | [QIBPORTCNTR_ERRPKEY] = crp_errpkey, | |
4743 | /* | |
4744 | * the next 3 aren't really counters, but were implemented | |
4745 | * as counters in older chips, so still get accessed as | |
4746 | * though they were counters from this code. | |
4747 | */ | |
4748 | [QIBPORTCNTR_PSINTERVAL] = krp_psinterval, | |
4749 | [QIBPORTCNTR_PSSTART] = krp_psstart, | |
4750 | [QIBPORTCNTR_PSSTAT] = krp_psstat, | |
4751 | /* pseudo-counter, summed for all ports */ | |
4752 | [QIBPORTCNTR_KHDROVFL] = 0xffff, | |
4753 | }; | |
4754 | ||
4755 | if (reg >= ARRAY_SIZE(xlator)) { | |
4756 | qib_devinfo(ppd->dd->pcidev, | |
4757 | "Unimplemented portcounter %u\n", reg); | |
4758 | goto done; | |
4759 | } | |
4760 | creg = xlator[reg] & _PORT_CNTR_IDXMASK; | |
4761 | ||
4762 | /* handle non-counters and special cases first */ | |
4763 | if (reg == QIBPORTCNTR_KHDROVFL) { | |
4764 | int i; | |
4765 | ||
4766 | /* sum over all kernel contexts (skip if mini_init) */ | |
4767 | for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) { | |
4768 | struct qib_ctxtdata *rcd = dd->rcd[i]; | |
4769 | ||
4770 | if (!rcd || rcd->ppd != ppd) | |
4771 | continue; | |
4772 | ret += read_7322_creg32(dd, cr_base_egrovfl + i); | |
4773 | } | |
4774 | goto done; | |
4775 | } else if (reg == QIBPORTCNTR_RXDROPPKT) { | |
4776 | /* | |
4777 | * Used as part of the synthesis of port_rcv_errors | |
4778 | * in the verbs code for IBTA counters. Not needed for 7322, | |
4779 | * because all the errors are already counted by other cntrs. | |
4780 | */ | |
4781 | goto done; | |
4782 | } else if (reg == QIBPORTCNTR_PSINTERVAL || | |
4783 | reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) { | |
4784 | /* were counters in older chips, now per-port kernel regs */ | |
4785 | ret = qib_read_kreg_port(ppd, creg); | |
4786 | goto done; | |
4787 | } | |
4788 | ||
4789 | /* | |
4790 | * Only fast increment counters are 64 bits; use 32 bit reads to | |
4791 | * avoid two independent reads when on Opteron. | |
4792 | */ | |
4793 | if (xlator[reg] & _PORT_64BIT_FLAG) | |
4794 | ret = read_7322_creg_port(ppd, creg); | |
4795 | else | |
4796 | ret = read_7322_creg32_port(ppd, creg); | |
4797 | if (creg == crp_ibsymbolerr) { | |
4798 | if (ppd->cpspec->ibdeltainprog) | |
4799 | ret -= ret - ppd->cpspec->ibsymsnap; | |
4800 | ret -= ppd->cpspec->ibsymdelta; | |
4801 | } else if (creg == crp_iblinkerrrecov) { | |
4802 | if (ppd->cpspec->ibdeltainprog) | |
4803 | ret -= ret - ppd->cpspec->iblnkerrsnap; | |
4804 | ret -= ppd->cpspec->iblnkerrdelta; | |
4805 | } else if (creg == crp_errlink) | |
4806 | ret -= ppd->cpspec->ibmalfdelta; | |
4807 | else if (creg == crp_iblinkdown) | |
4808 | ret += ppd->cpspec->iblnkdowndelta; | |
4809 | done: | |
4810 | return ret; | |
4811 | } | |
4812 | ||
4813 | /* | |
4814 | * Device counter names (not port-specific), one line per stat, | |
4815 | * single string. Used by utilities like ipathstats to print the stats | |
4816 | * in a way which works for different versions of drivers, without changing | |
4817 | * the utility. Names need to be 12 chars or less (w/o newline), for proper | |
4818 | * display by utility. | |
4819 | * Non-error counters are first. | |
4820 | * Start of "error" conters is indicated by a leading "E " on the first | |
4821 | * "error" counter, and doesn't count in label length. | |
4822 | * The EgrOvfl list needs to be last so we truncate them at the configured | |
4823 | * context count for the device. | |
4824 | * cntr7322indices contains the corresponding register indices. | |
4825 | */ | |
4826 | static const char cntr7322names[] = | |
4827 | "Interrupts\n" | |
4828 | "HostBusStall\n" | |
4829 | "E RxTIDFull\n" | |
4830 | "RxTIDInvalid\n" | |
4831 | "RxTIDFloDrop\n" /* 7322 only */ | |
4832 | "Ctxt0EgrOvfl\n" | |
4833 | "Ctxt1EgrOvfl\n" | |
4834 | "Ctxt2EgrOvfl\n" | |
4835 | "Ctxt3EgrOvfl\n" | |
4836 | "Ctxt4EgrOvfl\n" | |
4837 | "Ctxt5EgrOvfl\n" | |
4838 | "Ctxt6EgrOvfl\n" | |
4839 | "Ctxt7EgrOvfl\n" | |
4840 | "Ctxt8EgrOvfl\n" | |
4841 | "Ctxt9EgrOvfl\n" | |
4842 | "Ctx10EgrOvfl\n" | |
4843 | "Ctx11EgrOvfl\n" | |
4844 | "Ctx12EgrOvfl\n" | |
4845 | "Ctx13EgrOvfl\n" | |
4846 | "Ctx14EgrOvfl\n" | |
4847 | "Ctx15EgrOvfl\n" | |
4848 | "Ctx16EgrOvfl\n" | |
4849 | "Ctx17EgrOvfl\n" | |
4850 | ; | |
4851 | ||
4852 | static const u32 cntr7322indices[] = { | |
4853 | cr_lbint | _PORT_64BIT_FLAG, | |
4854 | cr_lbstall | _PORT_64BIT_FLAG, | |
4855 | cr_tidfull, | |
4856 | cr_tidinvalid, | |
4857 | cr_rxtidflowdrop, | |
4858 | cr_base_egrovfl + 0, | |
4859 | cr_base_egrovfl + 1, | |
4860 | cr_base_egrovfl + 2, | |
4861 | cr_base_egrovfl + 3, | |
4862 | cr_base_egrovfl + 4, | |
4863 | cr_base_egrovfl + 5, | |
4864 | cr_base_egrovfl + 6, | |
4865 | cr_base_egrovfl + 7, | |
4866 | cr_base_egrovfl + 8, | |
4867 | cr_base_egrovfl + 9, | |
4868 | cr_base_egrovfl + 10, | |
4869 | cr_base_egrovfl + 11, | |
4870 | cr_base_egrovfl + 12, | |
4871 | cr_base_egrovfl + 13, | |
4872 | cr_base_egrovfl + 14, | |
4873 | cr_base_egrovfl + 15, | |
4874 | cr_base_egrovfl + 16, | |
4875 | cr_base_egrovfl + 17, | |
4876 | }; | |
4877 | ||
4878 | /* | |
4879 | * same as cntr7322names and cntr7322indices, but for port-specific counters. | |
4880 | * portcntr7322indices is somewhat complicated by some registers needing | |
4881 | * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG | |
4882 | */ | |
4883 | static const char portcntr7322names[] = | |
4884 | "TxPkt\n" | |
4885 | "TxFlowPkt\n" | |
4886 | "TxWords\n" | |
4887 | "RxPkt\n" | |
4888 | "RxFlowPkt\n" | |
4889 | "RxWords\n" | |
4890 | "TxFlowStall\n" | |
4891 | "TxDmaDesc\n" /* 7220 and 7322-only */ | |
4892 | "E RxDlidFltr\n" /* 7220 and 7322-only */ | |
4893 | "IBStatusChng\n" | |
4894 | "IBLinkDown\n" | |
4895 | "IBLnkRecov\n" | |
4896 | "IBRxLinkErr\n" | |
4897 | "IBSymbolErr\n" | |
4898 | "RxLLIErr\n" | |
4899 | "RxBadFormat\n" | |
4900 | "RxBadLen\n" | |
4901 | "RxBufOvrfl\n" | |
4902 | "RxEBP\n" | |
4903 | "RxFlowCtlErr\n" | |
4904 | "RxICRCerr\n" | |
4905 | "RxLPCRCerr\n" | |
4906 | "RxVCRCerr\n" | |
4907 | "RxInvalLen\n" | |
4908 | "RxInvalPKey\n" | |
4909 | "RxPktDropped\n" | |
4910 | "TxBadLength\n" | |
4911 | "TxDropped\n" | |
4912 | "TxInvalLen\n" | |
4913 | "TxUnderrun\n" | |
4914 | "TxUnsupVL\n" | |
4915 | "RxLclPhyErr\n" /* 7220 and 7322-only from here down */ | |
4916 | "RxVL15Drop\n" | |
4917 | "RxVlErr\n" | |
4918 | "XcessBufOvfl\n" | |
4919 | "RxQPBadCtxt\n" /* 7322-only from here down */ | |
4920 | "TXBadHeader\n" | |
4921 | ; | |
4922 | ||
4923 | static const u32 portcntr7322indices[] = { | |
4924 | QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG, | |
4925 | crp_pktsendflow, | |
4926 | QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG, | |
4927 | QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG, | |
4928 | crp_pktrcvflowctrl, | |
4929 | QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG, | |
4930 | QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG, | |
4931 | crp_txsdmadesc | _PORT_64BIT_FLAG, | |
4932 | crp_rxdlidfltr, | |
4933 | crp_ibstatuschange, | |
4934 | QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG, | |
4935 | QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG, | |
4936 | QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG, | |
4937 | QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG, | |
4938 | QIBPORTCNTR_LLI | _PORT_VIRT_FLAG, | |
4939 | QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG, | |
4940 | QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG, | |
4941 | QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG, | |
4942 | QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG, | |
4943 | crp_rcvflowctrlviol, | |
4944 | QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG, | |
4945 | QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG, | |
4946 | QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG, | |
4947 | QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG, | |
4948 | QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG, | |
4949 | QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG, | |
4950 | crp_txminmaxlenerr, | |
4951 | crp_txdroppedpkt, | |
4952 | crp_txlenerr, | |
4953 | crp_txunderrun, | |
4954 | crp_txunsupvl, | |
4955 | QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG, | |
4956 | QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG, | |
4957 | QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG, | |
4958 | QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG, | |
4959 | crp_rxqpinvalidctxt, | |
4960 | crp_txhdrerr, | |
4961 | }; | |
4962 | ||
4963 | /* do all the setup to make the counter reads efficient later */ | |
4964 | static void init_7322_cntrnames(struct qib_devdata *dd) | |
4965 | { | |
4966 | int i, j = 0; | |
4967 | char *s; | |
4968 | ||
4969 | for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts; | |
4970 | i++) { | |
4971 | /* we always have at least one counter before the egrovfl */ | |
4972 | if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12)) | |
4973 | j = 1; | |
4974 | s = strchr(s + 1, '\n'); | |
4975 | if (s && j) | |
4976 | j++; | |
4977 | } | |
4978 | dd->cspec->ncntrs = i; | |
4979 | if (!s) | |
4980 | /* full list; size is without terminating null */ | |
4981 | dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; | |
4982 | else | |
4983 | dd->cspec->cntrnamelen = 1 + s - cntr7322names; | |
6da2ec56 KC |
4984 | dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64), |
4985 | GFP_KERNEL); | |
f931551b RC |
4986 | |
4987 | for (i = 0, s = (char *)portcntr7322names; s; i++) | |
4988 | s = strchr(s + 1, '\n'); | |
4989 | dd->cspec->nportcntrs = i - 1; | |
4990 | dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; | |
4991 | for (i = 0; i < dd->num_pports; ++i) { | |
6da2ec56 KC |
4992 | dd->pport[i].cpspec->portcntrs = |
4993 | kmalloc_array(dd->cspec->nportcntrs, sizeof(u64), | |
4994 | GFP_KERNEL); | |
f931551b RC |
4995 | } |
4996 | } | |
4997 | ||
4998 | static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep, | |
4999 | u64 **cntrp) | |
5000 | { | |
5001 | u32 ret; | |
5002 | ||
5003 | if (namep) { | |
5004 | ret = dd->cspec->cntrnamelen; | |
5005 | if (pos >= ret) | |
5006 | ret = 0; /* final read after getting everything */ | |
5007 | else | |
5008 | *namep = (char *) cntr7322names; | |
5009 | } else { | |
5010 | u64 *cntr = dd->cspec->cntrs; | |
5011 | int i; | |
5012 | ||
5013 | ret = dd->cspec->ncntrs * sizeof(u64); | |
5014 | if (!cntr || pos >= ret) { | |
5015 | /* everything read, or couldn't get memory */ | |
5016 | ret = 0; | |
5017 | goto done; | |
5018 | } | |
5019 | *cntrp = cntr; | |
5020 | for (i = 0; i < dd->cspec->ncntrs; i++) | |
5021 | if (cntr7322indices[i] & _PORT_64BIT_FLAG) | |
5022 | *cntr++ = read_7322_creg(dd, | |
5023 | cntr7322indices[i] & | |
5024 | _PORT_CNTR_IDXMASK); | |
5025 | else | |
5026 | *cntr++ = read_7322_creg32(dd, | |
5027 | cntr7322indices[i]); | |
5028 | } | |
5029 | done: | |
5030 | return ret; | |
5031 | } | |
5032 | ||
5033 | static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, | |
5034 | char **namep, u64 **cntrp) | |
5035 | { | |
5036 | u32 ret; | |
5037 | ||
5038 | if (namep) { | |
5039 | ret = dd->cspec->portcntrnamelen; | |
5040 | if (pos >= ret) | |
5041 | ret = 0; /* final read after getting everything */ | |
5042 | else | |
5043 | *namep = (char *)portcntr7322names; | |
5044 | } else { | |
5045 | struct qib_pportdata *ppd = &dd->pport[port]; | |
5046 | u64 *cntr = ppd->cpspec->portcntrs; | |
5047 | int i; | |
5048 | ||
5049 | ret = dd->cspec->nportcntrs * sizeof(u64); | |
5050 | if (!cntr || pos >= ret) { | |
5051 | /* everything read, or couldn't get memory */ | |
5052 | ret = 0; | |
5053 | goto done; | |
5054 | } | |
5055 | *cntrp = cntr; | |
5056 | for (i = 0; i < dd->cspec->nportcntrs; i++) { | |
5057 | if (portcntr7322indices[i] & _PORT_VIRT_FLAG) | |
5058 | *cntr++ = qib_portcntr_7322(ppd, | |
5059 | portcntr7322indices[i] & | |
5060 | _PORT_CNTR_IDXMASK); | |
5061 | else if (portcntr7322indices[i] & _PORT_64BIT_FLAG) | |
5062 | *cntr++ = read_7322_creg_port(ppd, | |
5063 | portcntr7322indices[i] & | |
5064 | _PORT_CNTR_IDXMASK); | |
5065 | else | |
5066 | *cntr++ = read_7322_creg32_port(ppd, | |
5067 | portcntr7322indices[i]); | |
5068 | } | |
5069 | } | |
5070 | done: | |
5071 | return ret; | |
5072 | } | |
5073 | ||
5074 | /** | |
5075 | * qib_get_7322_faststats - get word counters from chip before they overflow | |
a8a47b16 | 5076 | * @t: contains a pointer to the qlogic_ib device qib_devdata |
f931551b RC |
5077 | * |
5078 | * VESTIGIAL IBA7322 has no "small fast counters", so the only | |
5079 | * real purpose of this function is to maintain the notion of | |
5080 | * "active time", which in turn is only logged into the eeprom, | |
5081 | * which we don;t have, yet, for 7322-based boards. | |
5082 | * | |
5083 | * called from add_timer | |
5084 | */ | |
4037c92f | 5085 | static void qib_get_7322_faststats(struct timer_list *t) |
f931551b | 5086 | { |
4037c92f | 5087 | struct qib_devdata *dd = from_timer(dd, t, stats_timer); |
f931551b RC |
5088 | struct qib_pportdata *ppd; |
5089 | unsigned long flags; | |
5090 | u64 traffic_wds; | |
5091 | int pidx; | |
5092 | ||
5093 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
5094 | ppd = dd->pport + pidx; | |
5095 | ||
5096 | /* | |
5097 | * If port isn't enabled or not operational ports, or | |
5098 | * diags is running (can cause memory diags to fail) | |
5099 | * skip this port this time. | |
5100 | */ | |
5101 | if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED) | |
5102 | || dd->diag_client) | |
5103 | continue; | |
5104 | ||
5105 | /* | |
5106 | * Maintain an activity timer, based on traffic | |
5107 | * exceeding a threshold, so we need to check the word-counts | |
5108 | * even if they are 64-bit. | |
5109 | */ | |
5110 | traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) + | |
5111 | qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND); | |
5112 | spin_lock_irqsave(&ppd->dd->eep_st_lock, flags); | |
5113 | traffic_wds -= ppd->dd->traffic_wds; | |
5114 | ppd->dd->traffic_wds += traffic_wds; | |
f931551b RC |
5115 | spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags); |
5116 | if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active & | |
5117 | QIB_IB_QDR) && | |
5118 | (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | | |
5119 | QIBL_LINKACTIVE)) && | |
5120 | ppd->cpspec->qdr_dfe_time && | |
8482d5d1 | 5121 | time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) { |
f931551b RC |
5122 | ppd->cpspec->qdr_dfe_on = 0; |
5123 | ||
5124 | qib_write_kreg_port(ppd, krp_static_adapt_dis(2), | |
5125 | ppd->dd->cspec->r1 ? | |
5126 | QDR_STATIC_ADAPT_INIT_R1 : | |
5127 | QDR_STATIC_ADAPT_INIT); | |
5128 | force_h1(ppd); | |
5129 | } | |
5130 | } | |
5131 | mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); | |
5132 | } | |
5133 | ||
5134 | /* | |
5135 | * If we were using MSIx, try to fallback to INTx. | |
5136 | */ | |
5137 | static int qib_7322_intr_fallback(struct qib_devdata *dd) | |
5138 | { | |
5139 | if (!dd->cspec->num_msix_entries) | |
5140 | return 0; /* already using INTx */ | |
5141 | ||
7fac3301 MM |
5142 | qib_devinfo(dd->pcidev, |
5143 | "MSIx interrupt not detected, trying INTx interrupts\n"); | |
c4bc6156 | 5144 | qib_7322_free_irq(dd); |
91d343de | 5145 | if (pci_alloc_irq_vectors(dd->pcidev, 1, 1, PCI_IRQ_INTX) < 0) |
c4bc6156 | 5146 | qib_dev_err(dd, "Failed to enable INTx\n"); |
f931551b RC |
5147 | qib_setup_7322_interrupt(dd, 0); |
5148 | return 1; | |
5149 | } | |
5150 | ||
5151 | /* | |
5152 | * Reset the XGXS (between serdes and IBC). Slightly less intrusive | |
5153 | * than resetting the IBC or external link state, and useful in some | |
5154 | * cases to cause some retraining. To do this right, we reset IBC | |
5155 | * as well, then return to previous state (which may be still in reset) | |
5156 | * NOTE: some callers of this "know" this writes the current value | |
5157 | * of cpspec->ibcctrl_a as part of it's operation, so if that changes, | |
5158 | * check all callers. | |
5159 | */ | |
5160 | static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd) | |
5161 | { | |
5162 | u64 val; | |
5163 | struct qib_devdata *dd = ppd->dd; | |
5164 | const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) | | |
5165 | SYM_MASK(IBPCSConfig_0, xcv_treset) | | |
5166 | SYM_MASK(IBPCSConfig_0, tx_rx_reset); | |
5167 | ||
5168 | val = qib_read_kreg_port(ppd, krp_ib_pcsconfig); | |
b9e03e04 RC |
5169 | qib_write_kreg(dd, kr_hwerrmask, |
5170 | dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); | |
f931551b RC |
5171 | qib_write_kreg_port(ppd, krp_ibcctrl_a, |
5172 | ppd->cpspec->ibcctrl_a & | |
5173 | ~SYM_MASK(IBCCtrlA_0, IBLinkEn)); | |
5174 | ||
5175 | qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits); | |
5176 | qib_read_kreg32(dd, kr_scratch); | |
5177 | qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits); | |
5178 | qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); | |
5179 | qib_write_kreg(dd, kr_scratch, 0ULL); | |
b9e03e04 RC |
5180 | qib_write_kreg(dd, kr_hwerrclear, |
5181 | SYM_MASK(HwErrClear, statusValidNoEopClear)); | |
5182 | qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); | |
f931551b RC |
5183 | } |
5184 | ||
5185 | /* | |
5186 | * This code for non-IBTA-compliant IB speed negotiation is only known to | |
5187 | * work for the SDR to DDR transition, and only between an HCA and a switch | |
5188 | * with recent firmware. It is based on observed heuristics, rather than | |
5189 | * actual knowledge of the non-compliant speed negotiation. | |
5190 | * It has a number of hard-coded fields, since the hope is to rewrite this | |
5191 | * when a spec is available on how the negoation is intended to work. | |
5192 | */ | |
5193 | static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr, | |
5194 | u32 dcnt, u32 *data) | |
5195 | { | |
5196 | int i; | |
5197 | u64 pbc; | |
5198 | u32 __iomem *piobuf; | |
5199 | u32 pnum, control, len; | |
5200 | struct qib_devdata *dd = ppd->dd; | |
5201 | ||
5202 | i = 0; | |
5203 | len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */ | |
5204 | control = qib_7322_setpbc_control(ppd, len, 0, 15); | |
5205 | pbc = ((u64) control << 32) | len; | |
5206 | while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) { | |
5207 | if (i++ > 15) | |
5208 | return; | |
5209 | udelay(2); | |
5210 | } | |
5211 | /* disable header check on this packet, since it can't be valid */ | |
5212 | dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL); | |
5213 | writeq(pbc, piobuf); | |
5214 | qib_flush_wc(); | |
5215 | qib_pio_copy(piobuf + 2, hdr, 7); | |
5216 | qib_pio_copy(piobuf + 9, data, dcnt); | |
5217 | if (dd->flags & QIB_USE_SPCL_TRIG) { | |
5218 | u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023; | |
5219 | ||
5220 | qib_flush_wc(); | |
5221 | __raw_writel(0xaebecede, piobuf + spcl_off); | |
5222 | } | |
5223 | qib_flush_wc(); | |
5224 | qib_sendbuf_done(dd, pnum); | |
5225 | /* and re-enable hdr check */ | |
5226 | dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL); | |
5227 | } | |
5228 | ||
5229 | /* | |
5230 | * _start packet gets sent twice at start, _done gets sent twice at end | |
5231 | */ | |
5232 | static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which) | |
5233 | { | |
5234 | struct qib_devdata *dd = ppd->dd; | |
5235 | static u32 swapped; | |
5236 | u32 dw, i, hcnt, dcnt, *data; | |
5237 | static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba }; | |
5238 | static u32 madpayload_start[0x40] = { | |
5239 | 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0, | |
5240 | 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, | |
5241 | 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */ | |
5242 | }; | |
5243 | static u32 madpayload_done[0x40] = { | |
5244 | 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0, | |
5245 | 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, | |
5246 | 0x40000001, 0x1388, 0x15e, /* rest 0's */ | |
5247 | }; | |
5248 | ||
5249 | dcnt = ARRAY_SIZE(madpayload_start); | |
5250 | hcnt = ARRAY_SIZE(hdr); | |
5251 | if (!swapped) { | |
5252 | /* for maintainability, do it at runtime */ | |
5253 | for (i = 0; i < hcnt; i++) { | |
5254 | dw = (__force u32) cpu_to_be32(hdr[i]); | |
5255 | hdr[i] = dw; | |
5256 | } | |
5257 | for (i = 0; i < dcnt; i++) { | |
5258 | dw = (__force u32) cpu_to_be32(madpayload_start[i]); | |
5259 | madpayload_start[i] = dw; | |
5260 | dw = (__force u32) cpu_to_be32(madpayload_done[i]); | |
5261 | madpayload_done[i] = dw; | |
5262 | } | |
5263 | swapped = 1; | |
5264 | } | |
5265 | ||
5266 | data = which ? madpayload_done : madpayload_start; | |
5267 | ||
5268 | autoneg_7322_sendpkt(ppd, hdr, dcnt, data); | |
5269 | qib_read_kreg64(dd, kr_scratch); | |
5270 | udelay(2); | |
5271 | autoneg_7322_sendpkt(ppd, hdr, dcnt, data); | |
5272 | qib_read_kreg64(dd, kr_scratch); | |
5273 | udelay(2); | |
5274 | } | |
5275 | ||
5276 | /* | |
5277 | * Do the absolute minimum to cause an IB speed change, and make it | |
5278 | * ready, but don't actually trigger the change. The caller will | |
5279 | * do that when ready (if link is in Polling training state, it will | |
5280 | * happen immediately, otherwise when link next goes down) | |
5281 | * | |
5282 | * This routine should only be used as part of the DDR autonegotation | |
5283 | * code for devices that are not compliant with IB 1.2 (or code that | |
5284 | * fixes things up for same). | |
5285 | * | |
5286 | * When link has gone down, and autoneg enabled, or autoneg has | |
5287 | * failed and we give up until next time we set both speeds, and | |
5288 | * then we want IBTA enabled as well as "use max enabled speed. | |
5289 | */ | |
5290 | static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed) | |
5291 | { | |
5292 | u64 newctrlb; | |
da12c1f6 | 5293 | |
f931551b RC |
5294 | newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK | |
5295 | IBA7322_IBC_IBTA_1_2_MASK | | |
5296 | IBA7322_IBC_MAX_SPEED_MASK); | |
5297 | ||
5298 | if (speed & (speed - 1)) /* multiple speeds */ | |
5299 | newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) | | |
5300 | IBA7322_IBC_IBTA_1_2_MASK | | |
5301 | IBA7322_IBC_MAX_SPEED_MASK; | |
5302 | else | |
5303 | newctrlb |= speed == QIB_IB_QDR ? | |
5304 | IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK : | |
5305 | ((speed == QIB_IB_DDR ? | |
5306 | IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR)); | |
5307 | ||
5308 | if (newctrlb == ppd->cpspec->ibcctrl_b) | |
5309 | return; | |
5310 | ||
5311 | ppd->cpspec->ibcctrl_b = newctrlb; | |
5312 | qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); | |
5313 | qib_write_kreg(ppd->dd, kr_scratch, 0); | |
5314 | } | |
5315 | ||
5316 | /* | |
5317 | * This routine is only used when we are not talking to another | |
5318 | * IB 1.2-compliant device that we think can do DDR. | |
5319 | * (This includes all existing switch chips as of Oct 2007.) | |
5320 | * 1.2-compliant devices go directly to DDR prior to reaching INIT | |
5321 | */ | |
5322 | static void try_7322_autoneg(struct qib_pportdata *ppd) | |
5323 | { | |
5324 | unsigned long flags; | |
5325 | ||
5326 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
5327 | ppd->lflags |= QIBL_IB_AUTONEG_INPROG; | |
5328 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
5329 | qib_autoneg_7322_send(ppd, 0); | |
5330 | set_7322_ibspeed_fast(ppd, QIB_IB_DDR); | |
5331 | qib_7322_mini_pcs_reset(ppd); | |
5332 | /* 2 msec is minimum length of a poll cycle */ | |
f0626710 TH |
5333 | queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work, |
5334 | msecs_to_jiffies(2)); | |
f931551b RC |
5335 | } |
5336 | ||
5337 | /* | |
5338 | * Handle the empirically determined mechanism for auto-negotiation | |
5339 | * of DDR speed with switches. | |
5340 | */ | |
5341 | static void autoneg_7322_work(struct work_struct *work) | |
5342 | { | |
5343 | struct qib_pportdata *ppd; | |
f931551b RC |
5344 | u32 i; |
5345 | unsigned long flags; | |
5346 | ||
5347 | ppd = container_of(work, struct qib_chippport_specific, | |
5348 | autoneg_work.work)->ppd; | |
f931551b RC |
5349 | |
5350 | /* | |
5351 | * Busy wait for this first part, it should be at most a | |
5352 | * few hundred usec, since we scheduled ourselves for 2msec. | |
5353 | */ | |
5354 | for (i = 0; i < 25; i++) { | |
5355 | if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState) | |
5356 | == IB_7322_LT_STATE_POLLQUIET) { | |
5357 | qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE); | |
5358 | break; | |
5359 | } | |
5360 | udelay(100); | |
5361 | } | |
5362 | ||
5363 | if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) | |
5364 | goto done; /* we got there early or told to stop */ | |
5365 | ||
5366 | /* we expect this to timeout */ | |
5367 | if (wait_event_timeout(ppd->cpspec->autoneg_wait, | |
5368 | !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), | |
5369 | msecs_to_jiffies(90))) | |
5370 | goto done; | |
5371 | qib_7322_mini_pcs_reset(ppd); | |
5372 | ||
5373 | /* we expect this to timeout */ | |
5374 | if (wait_event_timeout(ppd->cpspec->autoneg_wait, | |
5375 | !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), | |
5376 | msecs_to_jiffies(1700))) | |
5377 | goto done; | |
5378 | qib_7322_mini_pcs_reset(ppd); | |
5379 | ||
5380 | set_7322_ibspeed_fast(ppd, QIB_IB_SDR); | |
5381 | ||
5382 | /* | |
5383 | * Wait up to 250 msec for link to train and get to INIT at DDR; | |
5384 | * this should terminate early. | |
5385 | */ | |
5386 | wait_event_timeout(ppd->cpspec->autoneg_wait, | |
5387 | !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), | |
5388 | msecs_to_jiffies(250)); | |
5389 | done: | |
5390 | if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) { | |
5391 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
5392 | ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; | |
5393 | if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) { | |
5394 | ppd->lflags |= QIBL_IB_AUTONEG_FAILED; | |
5395 | ppd->cpspec->autoneg_tries = 0; | |
5396 | } | |
5397 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
5398 | set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); | |
5399 | } | |
5400 | } | |
5401 | ||
5402 | /* | |
5403 | * This routine is used to request IPG set in the QLogic switch. | |
5404 | * Only called if r1. | |
5405 | */ | |
5406 | static void try_7322_ipg(struct qib_pportdata *ppd) | |
5407 | { | |
5408 | struct qib_ibport *ibp = &ppd->ibport_data; | |
5409 | struct ib_mad_send_buf *send_buf; | |
5410 | struct ib_mad_agent *agent; | |
5411 | struct ib_smp *smp; | |
5412 | unsigned delay; | |
5413 | int ret; | |
5414 | ||
f24a6d48 | 5415 | agent = ibp->rvp.send_agent; |
f931551b RC |
5416 | if (!agent) |
5417 | goto retry; | |
5418 | ||
5419 | send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR, | |
da2dfaa3 IW |
5420 | IB_MGMT_MAD_DATA, GFP_ATOMIC, |
5421 | IB_MGMT_BASE_VERSION); | |
f931551b RC |
5422 | if (IS_ERR(send_buf)) |
5423 | goto retry; | |
5424 | ||
4eadd8ff | 5425 | if (!ibp->smi_ah) { |
f931551b RC |
5426 | struct ib_ah *ah; |
5427 | ||
1fb9fed6 | 5428 | ah = qib_create_qp0_ah(ibp, be16_to_cpu(IB_LID_PERMISSIVE)); |
f931551b | 5429 | if (IS_ERR(ah)) |
1fb9fed6 | 5430 | ret = PTR_ERR(ah); |
f931551b RC |
5431 | else { |
5432 | send_buf->ah = ah; | |
4eadd8ff | 5433 | ibp->smi_ah = ibah_to_rvtah(ah); |
f931551b RC |
5434 | ret = 0; |
5435 | } | |
5436 | } else { | |
4eadd8ff | 5437 | send_buf->ah = &ibp->smi_ah->ibah; |
f931551b RC |
5438 | ret = 0; |
5439 | } | |
5440 | ||
5441 | smp = send_buf->mad; | |
5442 | smp->base_version = IB_MGMT_BASE_VERSION; | |
5443 | smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE; | |
5444 | smp->class_version = 1; | |
5445 | smp->method = IB_MGMT_METHOD_SEND; | |
5446 | smp->hop_cnt = 1; | |
5447 | smp->attr_id = QIB_VENDOR_IPG; | |
5448 | smp->attr_mod = 0; | |
5449 | ||
5450 | if (!ret) | |
5451 | ret = ib_post_send_mad(send_buf, NULL); | |
5452 | if (ret) | |
5453 | ib_free_send_mad(send_buf); | |
5454 | retry: | |
5455 | delay = 2 << ppd->cpspec->ipg_tries; | |
f0626710 TH |
5456 | queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work, |
5457 | msecs_to_jiffies(delay)); | |
f931551b RC |
5458 | } |
5459 | ||
5460 | /* | |
5461 | * Timeout handler for setting IPG. | |
5462 | * Only called if r1. | |
5463 | */ | |
5464 | static void ipg_7322_work(struct work_struct *work) | |
5465 | { | |
5466 | struct qib_pportdata *ppd; | |
5467 | ||
5468 | ppd = container_of(work, struct qib_chippport_specific, | |
5469 | ipg_work.work)->ppd; | |
5470 | if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE)) | |
5471 | && ++ppd->cpspec->ipg_tries <= 10) | |
5472 | try_7322_ipg(ppd); | |
5473 | } | |
5474 | ||
5475 | static u32 qib_7322_iblink_state(u64 ibcs) | |
5476 | { | |
5477 | u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState); | |
5478 | ||
5479 | switch (state) { | |
5480 | case IB_7322_L_STATE_INIT: | |
5481 | state = IB_PORT_INIT; | |
5482 | break; | |
5483 | case IB_7322_L_STATE_ARM: | |
5484 | state = IB_PORT_ARMED; | |
5485 | break; | |
5486 | case IB_7322_L_STATE_ACTIVE: | |
f931551b RC |
5487 | case IB_7322_L_STATE_ACT_DEFER: |
5488 | state = IB_PORT_ACTIVE; | |
5489 | break; | |
df561f66 GS |
5490 | default: |
5491 | fallthrough; | |
f931551b RC |
5492 | case IB_7322_L_STATE_DOWN: |
5493 | state = IB_PORT_DOWN; | |
5494 | break; | |
5495 | } | |
5496 | return state; | |
5497 | } | |
5498 | ||
5499 | /* returns the IBTA port state, rather than the IBC link training state */ | |
5500 | static u8 qib_7322_phys_portstate(u64 ibcs) | |
5501 | { | |
5502 | u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState); | |
5503 | return qib_7322_physportstate[state]; | |
5504 | } | |
5505 | ||
5506 | static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs) | |
5507 | { | |
5508 | int ret = 0, symadj = 0; | |
5509 | unsigned long flags; | |
5510 | int mult; | |
5511 | ||
5512 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
5513 | ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY; | |
5514 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
5515 | ||
5516 | /* Update our picture of width and speed from chip */ | |
5517 | if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) { | |
5518 | ppd->link_speed_active = QIB_IB_QDR; | |
5519 | mult = 4; | |
5520 | } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) { | |
5521 | ppd->link_speed_active = QIB_IB_DDR; | |
5522 | mult = 2; | |
5523 | } else { | |
5524 | ppd->link_speed_active = QIB_IB_SDR; | |
5525 | mult = 1; | |
5526 | } | |
5527 | if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) { | |
5528 | ppd->link_width_active = IB_WIDTH_4X; | |
5529 | mult *= 4; | |
5530 | } else | |
5531 | ppd->link_width_active = IB_WIDTH_1X; | |
5532 | ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)]; | |
5533 | ||
5534 | if (!ibup) { | |
5535 | u64 clr; | |
5536 | ||
5537 | /* Link went down. */ | |
5538 | /* do IPG MAD again after linkdown, even if last time failed */ | |
5539 | ppd->cpspec->ipg_tries = 0; | |
5540 | clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) & | |
5541 | (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) | | |
5542 | SYM_MASK(IBCStatusB_0, heartbeat_crosstalk)); | |
5543 | if (clr) | |
5544 | qib_write_kreg_port(ppd, krp_ibcstatus_b, clr); | |
5545 | if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | | |
5546 | QIBL_IB_AUTONEG_INPROG))) | |
5547 | set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); | |
5548 | if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { | |
dde05cbd MH |
5549 | struct qib_qsfp_data *qd = |
5550 | &ppd->cpspec->qsfp_data; | |
a77fcf89 RC |
5551 | /* unlock the Tx settings, speed may change */ |
5552 | qib_write_kreg_port(ppd, krp_tx_deemph_override, | |
5553 | SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
5554 | reset_tx_deemphasis_override)); | |
f931551b | 5555 | qib_cancel_sends(ppd); |
a77fcf89 RC |
5556 | /* on link down, ensure sane pcs state */ |
5557 | qib_7322_mini_pcs_reset(ppd); | |
dde05cbd MH |
5558 | /* schedule the qsfp refresh which should turn the link |
5559 | off */ | |
5560 | if (ppd->dd->flags & QIB_HAS_QSFP) { | |
8482d5d1 | 5561 | qd->t_insert = jiffies; |
042f36e1 | 5562 | queue_work(ib_wq, &qd->work); |
dde05cbd | 5563 | } |
f931551b RC |
5564 | spin_lock_irqsave(&ppd->sdma_lock, flags); |
5565 | if (__qib_sdma_running(ppd)) | |
5566 | __qib_sdma_process_event(ppd, | |
5567 | qib_sdma_event_e70_go_idle); | |
5568 | spin_unlock_irqrestore(&ppd->sdma_lock, flags); | |
5569 | } | |
5570 | clr = read_7322_creg32_port(ppd, crp_iblinkdown); | |
5571 | if (clr == ppd->cpspec->iblnkdownsnap) | |
5572 | ppd->cpspec->iblnkdowndelta++; | |
5573 | } else { | |
5574 | if (qib_compat_ddr_negotiate && | |
5575 | !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | | |
5576 | QIBL_IB_AUTONEG_INPROG)) && | |
5577 | ppd->link_speed_active == QIB_IB_SDR && | |
5578 | (ppd->link_speed_enabled & QIB_IB_DDR) | |
5579 | && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) { | |
5580 | /* we are SDR, and auto-negotiation enabled */ | |
5581 | ++ppd->cpspec->autoneg_tries; | |
5582 | if (!ppd->cpspec->ibdeltainprog) { | |
5583 | ppd->cpspec->ibdeltainprog = 1; | |
5584 | ppd->cpspec->ibsymdelta += | |
5585 | read_7322_creg32_port(ppd, | |
5586 | crp_ibsymbolerr) - | |
5587 | ppd->cpspec->ibsymsnap; | |
5588 | ppd->cpspec->iblnkerrdelta += | |
5589 | read_7322_creg32_port(ppd, | |
5590 | crp_iblinkerrrecov) - | |
5591 | ppd->cpspec->iblnkerrsnap; | |
5592 | } | |
5593 | try_7322_autoneg(ppd); | |
5594 | ret = 1; /* no other IB status change processing */ | |
5595 | } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && | |
5596 | ppd->link_speed_active == QIB_IB_SDR) { | |
5597 | qib_autoneg_7322_send(ppd, 1); | |
5598 | set_7322_ibspeed_fast(ppd, QIB_IB_DDR); | |
5599 | qib_7322_mini_pcs_reset(ppd); | |
5600 | udelay(2); | |
5601 | ret = 1; /* no other IB status change processing */ | |
5602 | } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && | |
5603 | (ppd->link_speed_active & QIB_IB_DDR)) { | |
5604 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
5605 | ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG | | |
5606 | QIBL_IB_AUTONEG_FAILED); | |
5607 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
5608 | ppd->cpspec->autoneg_tries = 0; | |
5609 | /* re-enable SDR, for next link down */ | |
5610 | set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); | |
5611 | wake_up(&ppd->cpspec->autoneg_wait); | |
5612 | symadj = 1; | |
5613 | } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) { | |
5614 | /* | |
5615 | * Clear autoneg failure flag, and do setup | |
5616 | * so we'll try next time link goes down and | |
5617 | * back to INIT (possibly connected to a | |
5618 | * different device). | |
5619 | */ | |
5620 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
5621 | ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; | |
5622 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
5623 | ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK; | |
5624 | symadj = 1; | |
5625 | } | |
5626 | if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { | |
5627 | symadj = 1; | |
5628 | if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) | |
5629 | try_7322_ipg(ppd); | |
5630 | if (!ppd->cpspec->recovery_init) | |
5631 | setup_7322_link_recovery(ppd, 0); | |
5632 | ppd->cpspec->qdr_dfe_time = jiffies + | |
5633 | msecs_to_jiffies(QDR_DFE_DISABLE_DELAY); | |
5634 | } | |
5635 | ppd->cpspec->ibmalfusesnap = 0; | |
5636 | ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, | |
5637 | crp_errlink); | |
5638 | } | |
5639 | if (symadj) { | |
5640 | ppd->cpspec->iblnkdownsnap = | |
5641 | read_7322_creg32_port(ppd, crp_iblinkdown); | |
5642 | if (ppd->cpspec->ibdeltainprog) { | |
5643 | ppd->cpspec->ibdeltainprog = 0; | |
5644 | ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd, | |
5645 | crp_ibsymbolerr) - ppd->cpspec->ibsymsnap; | |
5646 | ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd, | |
5647 | crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap; | |
5648 | } | |
5649 | } else if (!ibup && qib_compat_ddr_negotiate && | |
5650 | !ppd->cpspec->ibdeltainprog && | |
5651 | !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { | |
5652 | ppd->cpspec->ibdeltainprog = 1; | |
5653 | ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, | |
5654 | crp_ibsymbolerr); | |
5655 | ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, | |
5656 | crp_iblinkerrrecov); | |
5657 | } | |
5658 | ||
5659 | if (!ret) | |
5660 | qib_setup_7322_setextled(ppd, ibup); | |
5661 | return ret; | |
5662 | } | |
5663 | ||
5664 | /* | |
5665 | * Does read/modify/write to appropriate registers to | |
5666 | * set output and direction bits selected by mask. | |
4d2a3c16 | 5667 | * these are in their canonical positions (e.g. lsb of |
f931551b RC |
5668 | * dir will end up in D48 of extctrl on existing chips). |
5669 | * returns contents of GP Inputs. | |
5670 | */ | |
5671 | static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) | |
5672 | { | |
5673 | u64 read_val, new_out; | |
5674 | unsigned long flags; | |
5675 | ||
5676 | if (mask) { | |
5677 | /* some bits being written, lock access to GPIO */ | |
5678 | dir &= mask; | |
5679 | out &= mask; | |
5680 | spin_lock_irqsave(&dd->cspec->gpio_lock, flags); | |
5681 | dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); | |
5682 | dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); | |
5683 | new_out = (dd->cspec->gpio_out & ~mask) | out; | |
5684 | ||
5685 | qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); | |
5686 | qib_write_kreg(dd, kr_gpio_out, new_out); | |
5687 | dd->cspec->gpio_out = new_out; | |
5688 | spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); | |
5689 | } | |
5690 | /* | |
5691 | * It is unlikely that a read at this time would get valid | |
5692 | * data on a pin whose direction line was set in the same | |
5693 | * call to this function. We include the read here because | |
5694 | * that allows us to potentially combine a change on one pin with | |
5695 | * a read on another, and because the old code did something like | |
5696 | * this. | |
5697 | */ | |
5698 | read_val = qib_read_kreg64(dd, kr_extstatus); | |
5699 | return SYM_FIELD(read_val, EXTStatus, GPIOIn); | |
5700 | } | |
5701 | ||
5702 | /* Enable writes to config EEPROM, if possible. Returns previous state */ | |
5703 | static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen) | |
5704 | { | |
5705 | int prev_wen; | |
5706 | u32 mask; | |
5707 | ||
5708 | mask = 1 << QIB_EEPROM_WEN_NUM; | |
5709 | prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM; | |
5710 | gpio_7322_mod(dd, wen ? 0 : mask, mask, mask); | |
5711 | ||
5712 | return prev_wen & 1; | |
5713 | } | |
5714 | ||
5715 | /* | |
5716 | * Read fundamental info we need to use the chip. These are | |
5717 | * the registers that describe chip capabilities, and are | |
5718 | * saved in shadow registers. | |
5719 | */ | |
5720 | static void get_7322_chip_params(struct qib_devdata *dd) | |
5721 | { | |
5722 | u64 val; | |
5723 | u32 piobufs; | |
5724 | int mtu; | |
5725 | ||
5726 | dd->palign = qib_read_kreg32(dd, kr_pagealign); | |
5727 | ||
5728 | dd->uregbase = qib_read_kreg32(dd, kr_userregbase); | |
5729 | ||
5730 | dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); | |
5731 | dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); | |
5732 | dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); | |
5733 | dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); | |
5734 | dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; | |
5735 | ||
5736 | val = qib_read_kreg64(dd, kr_sendpiobufcnt); | |
5737 | dd->piobcnt2k = val & ~0U; | |
5738 | dd->piobcnt4k = val >> 32; | |
5739 | val = qib_read_kreg64(dd, kr_sendpiosize); | |
5740 | dd->piosize2k = val & ~0U; | |
5741 | dd->piosize4k = val >> 32; | |
5742 | ||
5743 | mtu = ib_mtu_enum_to_int(qib_ibmtu); | |
5744 | if (mtu == -1) | |
5745 | mtu = QIB_DEFAULT_MTU; | |
5746 | dd->pport[0].ibmtu = (u32)mtu; | |
5747 | dd->pport[1].ibmtu = (u32)mtu; | |
5748 | ||
5749 | /* these may be adjusted in init_chip_wc_pat() */ | |
5750 | dd->pio2kbase = (u32 __iomem *) | |
5751 | ((char __iomem *) dd->kregbase + dd->pio2k_bufbase); | |
5752 | dd->pio4kbase = (u32 __iomem *) | |
5753 | ((char __iomem *) dd->kregbase + | |
5754 | (dd->piobufbase >> 32)); | |
5755 | /* | |
5756 | * 4K buffers take 2 pages; we use roundup just to be | |
5757 | * paranoid; we calculate it once here, rather than on | |
5758 | * ever buf allocate | |
5759 | */ | |
5760 | dd->align4k = ALIGN(dd->piosize4k, dd->palign); | |
5761 | ||
5762 | piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS; | |
5763 | ||
5764 | dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / | |
5765 | (sizeof(u64) * BITS_PER_BYTE / 2); | |
5766 | } | |
5767 | ||
5768 | /* | |
5769 | * The chip base addresses in cspec and cpspec have to be set | |
5770 | * after possible init_chip_wc_pat(), rather than in | |
5771 | * get_7322_chip_params(), so split out as separate function | |
5772 | */ | |
5773 | static void qib_7322_set_baseaddrs(struct qib_devdata *dd) | |
5774 | { | |
5775 | u32 cregbase; | |
da12c1f6 | 5776 | |
f931551b RC |
5777 | cregbase = qib_read_kreg32(dd, kr_counterregbase); |
5778 | ||
5779 | dd->cspec->cregbase = (u64 __iomem *)(cregbase + | |
5780 | (char __iomem *)dd->kregbase); | |
5781 | ||
5782 | dd->egrtidbase = (u64 __iomem *) | |
5783 | ((char __iomem *) dd->kregbase + dd->rcvegrbase); | |
5784 | ||
5785 | /* port registers are defined as relative to base of chip */ | |
5786 | dd->pport[0].cpspec->kpregbase = | |
5787 | (u64 __iomem *)((char __iomem *)dd->kregbase); | |
5788 | dd->pport[1].cpspec->kpregbase = | |
5789 | (u64 __iomem *)(dd->palign + | |
5790 | (char __iomem *)dd->kregbase); | |
5791 | dd->pport[0].cpspec->cpregbase = | |
5792 | (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0], | |
5793 | kr_counterregbase) + (char __iomem *)dd->kregbase); | |
5794 | dd->pport[1].cpspec->cpregbase = | |
5795 | (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1], | |
5796 | kr_counterregbase) + (char __iomem *)dd->kregbase); | |
5797 | } | |
5798 | ||
5799 | /* | |
5800 | * This is a fairly special-purpose observer, so we only support | |
5801 | * the port-specific parts of SendCtrl | |
5802 | */ | |
5803 | ||
5804 | #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \ | |
5805 | SYM_MASK(SendCtrl_0, SDmaEnable) | \ | |
5806 | SYM_MASK(SendCtrl_0, SDmaIntEnable) | \ | |
5807 | SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \ | |
5808 | SYM_MASK(SendCtrl_0, SDmaHalt) | \ | |
5809 | SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \ | |
5810 | SYM_MASK(SendCtrl_0, ForceCreditUpToDate)) | |
5811 | ||
5812 | static int sendctrl_hook(struct qib_devdata *dd, | |
5813 | const struct diag_observer *op, u32 offs, | |
5814 | u64 *data, u64 mask, int only_32) | |
5815 | { | |
5816 | unsigned long flags; | |
5817 | unsigned idx; | |
5818 | unsigned pidx; | |
5819 | struct qib_pportdata *ppd = NULL; | |
5820 | u64 local_data, all_bits; | |
5821 | ||
5822 | /* | |
5823 | * The fixed correspondence between Physical ports and pports is | |
5824 | * severed. We need to hunt for the ppd that corresponds | |
5825 | * to the offset we got. And we have to do that without admitting | |
5826 | * we know the stride, apparently. | |
5827 | */ | |
5828 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
5829 | u64 __iomem *psptr; | |
5830 | u32 psoffs; | |
5831 | ||
5832 | ppd = dd->pport + pidx; | |
5833 | if (!ppd->cpspec->kpregbase) | |
5834 | continue; | |
5835 | ||
5836 | psptr = ppd->cpspec->kpregbase + krp_sendctrl; | |
5837 | psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr); | |
5838 | if (psoffs == offs) | |
5839 | break; | |
5840 | } | |
5841 | ||
5842 | /* If pport is not being managed by driver, just avoid shadows. */ | |
5843 | if (pidx >= dd->num_pports) | |
5844 | ppd = NULL; | |
5845 | ||
5846 | /* In any case, "idx" is flat index in kreg space */ | |
5847 | idx = offs / sizeof(u64); | |
5848 | ||
5849 | all_bits = ~0ULL; | |
5850 | if (only_32) | |
5851 | all_bits >>= 32; | |
5852 | ||
5853 | spin_lock_irqsave(&dd->sendctrl_lock, flags); | |
5854 | if (!ppd || (mask & all_bits) != all_bits) { | |
5855 | /* | |
5856 | * At least some mask bits are zero, so we need | |
5857 | * to read. The judgement call is whether from | |
5858 | * reg or shadow. First-cut: read reg, and complain | |
5859 | * if any bits which should be shadowed are different | |
5860 | * from their shadowed value. | |
5861 | */ | |
5862 | if (only_32) | |
5863 | local_data = (u64)qib_read_kreg32(dd, idx); | |
5864 | else | |
5865 | local_data = qib_read_kreg64(dd, idx); | |
5866 | *data = (local_data & ~mask) | (*data & mask); | |
5867 | } | |
5868 | if (mask) { | |
5869 | /* | |
5870 | * At least some mask bits are one, so we need | |
5871 | * to write, but only shadow some bits. | |
5872 | */ | |
5873 | u64 sval, tval; /* Shadowed, transient */ | |
5874 | ||
5875 | /* | |
5876 | * New shadow val is bits we don't want to touch, | |
5877 | * ORed with bits we do, that are intended for shadow. | |
5878 | */ | |
5879 | if (ppd) { | |
5880 | sval = ppd->p_sendctrl & ~mask; | |
5881 | sval |= *data & SENDCTRL_SHADOWED & mask; | |
5882 | ppd->p_sendctrl = sval; | |
5883 | } else | |
5884 | sval = *data & SENDCTRL_SHADOWED & mask; | |
5885 | tval = sval | (*data & ~SENDCTRL_SHADOWED & mask); | |
5886 | qib_write_kreg(dd, idx, tval); | |
5887 | qib_write_kreg(dd, kr_scratch, 0Ull); | |
5888 | } | |
5889 | spin_unlock_irqrestore(&dd->sendctrl_lock, flags); | |
5890 | return only_32 ? 4 : 8; | |
5891 | } | |
5892 | ||
5893 | static const struct diag_observer sendctrl_0_observer = { | |
5894 | sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64), | |
5895 | KREG_IDX(SendCtrl_0) * sizeof(u64) | |
5896 | }; | |
5897 | ||
5898 | static const struct diag_observer sendctrl_1_observer = { | |
5899 | sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64), | |
5900 | KREG_IDX(SendCtrl_1) * sizeof(u64) | |
5901 | }; | |
5902 | ||
5903 | static ushort sdma_fetch_prio = 8; | |
5904 | module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO); | |
5905 | MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority"); | |
5906 | ||
5907 | /* Besides logging QSFP events, we set appropriate TxDDS values */ | |
5908 | static void init_txdds_table(struct qib_pportdata *ppd, int override); | |
5909 | ||
5910 | static void qsfp_7322_event(struct work_struct *work) | |
5911 | { | |
5912 | struct qib_qsfp_data *qd; | |
5913 | struct qib_pportdata *ppd; | |
8482d5d1 | 5914 | unsigned long pwrup; |
16d99812 | 5915 | unsigned long flags; |
f931551b RC |
5916 | int ret; |
5917 | u32 le2; | |
5918 | ||
5919 | qd = container_of(work, struct qib_qsfp_data, work); | |
5920 | ppd = qd->ppd; | |
dde05cbd MH |
5921 | pwrup = qd->t_insert + |
5922 | msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC); | |
f931551b | 5923 | |
dde05cbd MH |
5924 | /* Delay for 20 msecs to allow ModPrs resistor to setup */ |
5925 | mdelay(QSFP_MODPRS_LAG_MSEC); | |
5926 | ||
16d99812 MH |
5927 | if (!qib_qsfp_mod_present(ppd)) { |
5928 | ppd->cpspec->qsfp_data.modpresent = 0; | |
dde05cbd MH |
5929 | /* Set the physical link to disabled */ |
5930 | qib_set_ib_7322_lstate(ppd, 0, | |
5931 | QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); | |
16d99812 MH |
5932 | spin_lock_irqsave(&ppd->lflags_lock, flags); |
5933 | ppd->lflags &= ~QIBL_LINKV; | |
5934 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
5935 | } else { | |
dde05cbd MH |
5936 | /* |
5937 | * Some QSFP's not only do not respond until the full power-up | |
5938 | * time, but may behave badly if we try. So hold off responding | |
5939 | * to insertion. | |
5940 | */ | |
5941 | while (1) { | |
8482d5d1 | 5942 | if (time_is_before_jiffies(pwrup)) |
dde05cbd MH |
5943 | break; |
5944 | msleep(20); | |
5945 | } | |
5946 | ||
5947 | ret = qib_refresh_qsfp_cache(ppd, &qd->cache); | |
5948 | ||
5949 | /* | |
5950 | * Need to change LE2 back to defaults if we couldn't | |
5951 | * read the cable type (to handle cable swaps), so do this | |
5952 | * even on failure to read cable information. We don't | |
5953 | * get here for QME, so IS_QME check not needed here. | |
5954 | */ | |
5955 | if (!ret && !ppd->dd->cspec->r1) { | |
5956 | if (QSFP_IS_ACTIVE_FAR(qd->cache.tech)) | |
5957 | le2 = LE2_QME; | |
5958 | else if (qd->cache.atten[1] >= qib_long_atten && | |
5959 | QSFP_IS_CU(qd->cache.tech)) | |
5960 | le2 = LE2_5m; | |
5961 | else | |
5962 | le2 = LE2_DEFAULT; | |
5963 | } else | |
4634b794 | 5964 | le2 = LE2_DEFAULT; |
dde05cbd MH |
5965 | ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7)); |
5966 | /* | |
5967 | * We always change parameteters, since we can choose | |
5968 | * values for cables without eeproms, and the cable may have | |
5969 | * changed from a cable with full or partial eeprom content | |
5970 | * to one with partial or no content. | |
5971 | */ | |
5972 | init_txdds_table(ppd, 0); | |
5973 | /* The physical link is being re-enabled only when the | |
16d99812 MH |
5974 | * previous state was DISABLED and the VALID bit is not |
5975 | * set. This should only happen when the cable has been | |
5976 | * physically pulled. */ | |
5977 | if (!ppd->cpspec->qsfp_data.modpresent && | |
5978 | (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) { | |
5979 | ppd->cpspec->qsfp_data.modpresent = 1; | |
dde05cbd MH |
5980 | qib_set_ib_7322_lstate(ppd, 0, |
5981 | QLOGIC_IB_IBCC_LINKINITCMD_SLEEP); | |
16d99812 MH |
5982 | spin_lock_irqsave(&ppd->lflags_lock, flags); |
5983 | ppd->lflags |= QIBL_LINKV; | |
5984 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
5985 | } | |
dde05cbd | 5986 | } |
f931551b RC |
5987 | } |
5988 | ||
5989 | /* | |
5990 | * There is little we can do but complain to the user if QSFP | |
5991 | * initialization fails. | |
5992 | */ | |
5993 | static void qib_init_7322_qsfp(struct qib_pportdata *ppd) | |
5994 | { | |
5995 | unsigned long flags; | |
5996 | struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data; | |
5997 | struct qib_devdata *dd = ppd->dd; | |
5998 | u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N; | |
5999 | ||
6000 | mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); | |
6001 | qd->ppd = ppd; | |
6002 | qib_qsfp_init(qd, qsfp_7322_event); | |
6003 | spin_lock_irqsave(&dd->cspec->gpio_lock, flags); | |
6004 | dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); | |
6005 | dd->cspec->gpio_mask |= mod_prs_bit; | |
6006 | qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); | |
6007 | qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); | |
6008 | spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); | |
6009 | } | |
6010 | ||
6011 | /* | |
a77fcf89 | 6012 | * called at device initialization time, and also if the txselect |
f931551b RC |
6013 | * module parameter is changed. This is used for cables that don't |
6014 | * have valid QSFP EEPROMs (not present, or attenuation is zero). | |
6015 | * We initialize to the default, then if there is a specific | |
a77fcf89 RC |
6016 | * unit,port match, we use that (and set it immediately, for the |
6017 | * current speed, if the link is at INIT or better). | |
f931551b | 6018 | * String format is "default# unit#,port#=# ... u,p=#", separators must |
a77fcf89 RC |
6019 | * be a SPACE character. A newline terminates. The u,p=# tuples may |
6020 | * optionally have "u,p=#,#", where the final # is the H1 value | |
f931551b RC |
6021 | * The last specific match is used (actually, all are used, but last |
6022 | * one is the one that winds up set); if none at all, fall back on default. | |
6023 | */ | |
6024 | static void set_no_qsfp_atten(struct qib_devdata *dd, int change) | |
6025 | { | |
6026 | char *nxt, *str; | |
a77fcf89 | 6027 | u32 pidx, unit, port, deflt, h1; |
f931551b | 6028 | unsigned long val; |
a77fcf89 | 6029 | int any = 0, seth1; |
e706203c | 6030 | int txdds_size; |
f931551b | 6031 | |
a77fcf89 | 6032 | str = txselect_list; |
f931551b | 6033 | |
a77fcf89 | 6034 | /* default number is validated in setup_txselect() */ |
f931551b RC |
6035 | deflt = simple_strtoul(str, &nxt, 0); |
6036 | for (pidx = 0; pidx < dd->num_pports; ++pidx) | |
6037 | dd->pport[pidx].cpspec->no_eep = deflt; | |
6038 | ||
e706203c MM |
6039 | txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ; |
6040 | if (IS_QME(dd) || IS_QMH(dd)) | |
6041 | txdds_size += TXDDS_MFG_SZ; | |
6042 | ||
f931551b RC |
6043 | while (*nxt && nxt[1]) { |
6044 | str = ++nxt; | |
6045 | unit = simple_strtoul(str, &nxt, 0); | |
6046 | if (nxt == str || !*nxt || *nxt != ',') { | |
6047 | while (*nxt && *nxt++ != ' ') /* skip to next, if any */ | |
6048 | ; | |
6049 | continue; | |
6050 | } | |
6051 | str = ++nxt; | |
6052 | port = simple_strtoul(str, &nxt, 0); | |
6053 | if (nxt == str || *nxt != '=') { | |
6054 | while (*nxt && *nxt++ != ' ') /* skip to next, if any */ | |
6055 | ; | |
6056 | continue; | |
6057 | } | |
6058 | str = ++nxt; | |
6059 | val = simple_strtoul(str, &nxt, 0); | |
6060 | if (nxt == str) { | |
6061 | while (*nxt && *nxt++ != ' ') /* skip to next, if any */ | |
6062 | ; | |
6063 | continue; | |
6064 | } | |
e706203c | 6065 | if (val >= txdds_size) |
f931551b | 6066 | continue; |
a77fcf89 RC |
6067 | seth1 = 0; |
6068 | h1 = 0; /* gcc thinks it might be used uninitted */ | |
6069 | if (*nxt == ',' && nxt[1]) { | |
6070 | str = ++nxt; | |
6071 | h1 = (u32)simple_strtoul(str, &nxt, 0); | |
6072 | if (nxt == str) | |
6073 | while (*nxt && *nxt++ != ' ') /* skip */ | |
6074 | ; | |
6075 | else | |
6076 | seth1 = 1; | |
6077 | } | |
f931551b RC |
6078 | for (pidx = 0; dd->unit == unit && pidx < dd->num_pports; |
6079 | ++pidx) { | |
a77fcf89 RC |
6080 | struct qib_pportdata *ppd = &dd->pport[pidx]; |
6081 | ||
6082 | if (ppd->port != port || !ppd->link_speed_supported) | |
f931551b | 6083 | continue; |
a77fcf89 | 6084 | ppd->cpspec->no_eep = val; |
7c7a416e RC |
6085 | if (seth1) |
6086 | ppd->cpspec->h1_val = h1; | |
f931551b | 6087 | /* now change the IBC and serdes, overriding generic */ |
a77fcf89 | 6088 | init_txdds_table(ppd, 1); |
d70585f7 | 6089 | /* Re-enable the physical state machine on mezz boards |
dde05cbd MH |
6090 | * now that the correct settings have been set. |
6091 | * QSFP boards are handles by the QSFP event handler */ | |
d70585f7 MH |
6092 | if (IS_QMH(dd) || IS_QME(dd)) |
6093 | qib_set_ib_7322_lstate(ppd, 0, | |
6094 | QLOGIC_IB_IBCC_LINKINITCMD_SLEEP); | |
f931551b RC |
6095 | any++; |
6096 | } | |
6097 | if (*nxt == '\n') | |
6098 | break; /* done */ | |
6099 | } | |
6100 | if (change && !any) { | |
6101 | /* no specific setting, use the default. | |
6102 | * Change the IBC and serdes, but since it's | |
6103 | * general, don't override specific settings. | |
6104 | */ | |
a77fcf89 RC |
6105 | for (pidx = 0; pidx < dd->num_pports; ++pidx) |
6106 | if (dd->pport[pidx].link_speed_supported) | |
6107 | init_txdds_table(&dd->pport[pidx], 0); | |
f931551b RC |
6108 | } |
6109 | } | |
6110 | ||
a77fcf89 | 6111 | /* handle the txselect parameter changing */ |
e4dca7b7 | 6112 | static int setup_txselect(const char *str, const struct kernel_param *kp) |
f931551b RC |
6113 | { |
6114 | struct qib_devdata *dd; | |
059d48fb | 6115 | unsigned long index, val; |
2fadd831 | 6116 | char *n; |
da12c1f6 | 6117 | |
6167a5b4 | 6118 | if (strlen(str) >= ARRAY_SIZE(txselect_list)) { |
7fac3301 | 6119 | pr_info("txselect_values string too long\n"); |
f931551b RC |
6120 | return -ENOSPC; |
6121 | } | |
2fadd831 MM |
6122 | val = simple_strtoul(str, &n, 0); |
6123 | if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + | |
e706203c | 6124 | TXDDS_MFG_SZ)) { |
7fac3301 | 6125 | pr_info("txselect_values must start with a number < %d\n", |
e706203c | 6126 | TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ); |
2fadd831 | 6127 | return -EINVAL; |
f931551b | 6128 | } |
cb7ab785 | 6129 | strscpy(txselect_list, str, sizeof(txselect_list)); |
2fadd831 | 6130 | |
059d48fb | 6131 | xa_for_each(&qib_dev_table, index, dd) |
a77fcf89 RC |
6132 | if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322) |
6133 | set_no_qsfp_atten(dd, 1); | |
f931551b RC |
6134 | return 0; |
6135 | } | |
6136 | ||
6137 | /* | |
6138 | * Write the final few registers that depend on some of the | |
6139 | * init setup. Done late in init, just before bringing up | |
6140 | * the serdes. | |
6141 | */ | |
6142 | static int qib_late_7322_initreg(struct qib_devdata *dd) | |
6143 | { | |
6144 | int ret = 0, n; | |
6145 | u64 val; | |
6146 | ||
6147 | qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); | |
6148 | qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); | |
6149 | qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); | |
6150 | qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); | |
6151 | val = qib_read_kreg64(dd, kr_sendpioavailaddr); | |
6152 | if (val != dd->pioavailregs_phys) { | |
7fac3301 MM |
6153 | qib_dev_err(dd, |
6154 | "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n", | |
6155 | (unsigned long) dd->pioavailregs_phys, | |
6156 | (unsigned long long) val); | |
f931551b RC |
6157 | ret = -EINVAL; |
6158 | } | |
6159 | ||
6160 | n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; | |
6161 | qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL); | |
6162 | /* driver sends get pkey, lid, etc. checking also, to catch bugs */ | |
6163 | qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL); | |
6164 | ||
6165 | qib_register_observer(dd, &sendctrl_0_observer); | |
6166 | qib_register_observer(dd, &sendctrl_1_observer); | |
6167 | ||
6168 | dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN; | |
6169 | qib_write_kreg(dd, kr_control, dd->control); | |
6170 | /* | |
6171 | * Set SendDmaFetchPriority and init Tx params, including | |
6172 | * QSFP handler on boards that have QSFP. | |
6173 | * First set our default attenuation entry for cables that | |
6174 | * don't have valid attenuation. | |
6175 | */ | |
6176 | set_no_qsfp_atten(dd, 0); | |
6177 | for (n = 0; n < dd->num_pports; ++n) { | |
6178 | struct qib_pportdata *ppd = dd->pport + n; | |
6179 | ||
6180 | qib_write_kreg_port(ppd, krp_senddmaprioritythld, | |
6181 | sdma_fetch_prio & 0xf); | |
6182 | /* Initialize qsfp if present on board. */ | |
6183 | if (dd->flags & QIB_HAS_QSFP) | |
6184 | qib_init_7322_qsfp(ppd); | |
6185 | } | |
6186 | dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN; | |
6187 | qib_write_kreg(dd, kr_control, dd->control); | |
6188 | ||
6189 | return ret; | |
6190 | } | |
6191 | ||
6192 | /* per IB port errors. */ | |
6193 | #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \ | |
6194 | MASK_ACROSS(8, 15)) | |
6195 | #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41)) | |
6196 | #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \ | |
6197 | MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \ | |
6198 | MASK_ACROSS(0, 11)) | |
6199 | ||
6200 | /* | |
6201 | * Write the initialization per-port registers that need to be done at | |
6202 | * driver load and after reset completes (i.e., that aren't done as part | |
6203 | * of other init procedures called from qib_init.c). | |
6204 | * Some of these should be redundant on reset, but play safe. | |
6205 | */ | |
6206 | static void write_7322_init_portregs(struct qib_pportdata *ppd) | |
6207 | { | |
6208 | u64 val; | |
6209 | int i; | |
6210 | ||
6211 | if (!ppd->link_speed_supported) { | |
6212 | /* no buffer credits for this port */ | |
6213 | for (i = 1; i < 8; i++) | |
6214 | qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0); | |
6215 | qib_write_kreg_port(ppd, krp_ibcctrl_b, 0); | |
6216 | qib_write_kreg(ppd->dd, kr_scratch, 0); | |
6217 | return; | |
6218 | } | |
6219 | ||
6220 | /* | |
6221 | * Set the number of supported virtual lanes in IBC, | |
6222 | * for flow control packet handling on unsupported VLs | |
6223 | */ | |
6224 | val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); | |
6225 | val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP); | |
6226 | val |= (u64)(ppd->vls_supported - 1) << | |
6227 | SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP); | |
6228 | qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); | |
6229 | ||
6230 | qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP); | |
6231 | ||
6232 | /* enable tx header checking */ | |
6233 | qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY | | |
6234 | IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID | | |
6235 | IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ); | |
6236 | ||
6237 | qib_write_kreg_port(ppd, krp_ncmodectrl, | |
6238 | SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal)); | |
6239 | ||
6240 | /* | |
6241 | * Unconditionally clear the bufmask bits. If SDMA is | |
6242 | * enabled, we'll set them appropriately later. | |
6243 | */ | |
6244 | qib_write_kreg_port(ppd, krp_senddmabufmask0, 0); | |
6245 | qib_write_kreg_port(ppd, krp_senddmabufmask1, 0); | |
6246 | qib_write_kreg_port(ppd, krp_senddmabufmask2, 0); | |
6247 | if (ppd->dd->cspec->r1) | |
6248 | ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate); | |
6249 | } | |
6250 | ||
6251 | /* | |
6252 | * Write the initialization per-device registers that need to be done at | |
6253 | * driver load and after reset completes (i.e., that aren't done as part | |
6254 | * of other init procedures called from qib_init.c). Also write per-port | |
6255 | * registers that are affected by overall device config, such as QP mapping | |
6256 | * Some of these should be redundant on reset, but play safe. | |
6257 | */ | |
6258 | static void write_7322_initregs(struct qib_devdata *dd) | |
6259 | { | |
6260 | struct qib_pportdata *ppd; | |
6261 | int i, pidx; | |
6262 | u64 val; | |
6263 | ||
6264 | /* Set Multicast QPs received by port 2 to map to context one. */ | |
6265 | qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1); | |
6266 | ||
6267 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
6268 | unsigned n, regno; | |
6269 | unsigned long flags; | |
6270 | ||
2528ea60 MM |
6271 | if (dd->n_krcv_queues < 2 || |
6272 | !dd->pport[pidx].link_speed_supported) | |
f931551b RC |
6273 | continue; |
6274 | ||
6275 | ppd = &dd->pport[pidx]; | |
6276 | ||
6277 | /* be paranoid against later code motion, etc. */ | |
6278 | spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); | |
6279 | ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable); | |
6280 | spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); | |
6281 | ||
6282 | /* Initialize QP to context mapping */ | |
6283 | regno = krp_rcvqpmaptable; | |
6284 | val = 0; | |
6285 | if (dd->num_pports > 1) | |
6286 | n = dd->first_user_ctxt / dd->num_pports; | |
6287 | else | |
6288 | n = dd->first_user_ctxt - 1; | |
6289 | for (i = 0; i < 32; ) { | |
6290 | unsigned ctxt; | |
6291 | ||
6292 | if (dd->num_pports > 1) | |
6293 | ctxt = (i % n) * dd->num_pports + pidx; | |
6294 | else if (i % n) | |
6295 | ctxt = (i % n) + 1; | |
6296 | else | |
6297 | ctxt = ppd->hw_pidx; | |
6298 | val |= ctxt << (5 * (i % 6)); | |
6299 | i++; | |
6300 | if (i % 6 == 0) { | |
6301 | qib_write_kreg_port(ppd, regno, val); | |
6302 | val = 0; | |
6303 | regno++; | |
6304 | } | |
6305 | } | |
6306 | qib_write_kreg_port(ppd, regno, val); | |
6307 | } | |
6308 | ||
6309 | /* | |
6310 | * Setup up interrupt mitigation for kernel contexts, but | |
6311 | * not user contexts (user contexts use interrupts when | |
6312 | * stalled waiting for any packet, so want those interrupts | |
6313 | * right away). | |
6314 | */ | |
6315 | for (i = 0; i < dd->first_user_ctxt; i++) { | |
6316 | dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; | |
6317 | qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout); | |
6318 | } | |
6319 | ||
6320 | /* | |
6321 | * Initialize as (disabled) rcvflow tables. Application code | |
6322 | * will setup each flow as it uses the flow. | |
6323 | * Doesn't clear any of the error bits that might be set. | |
6324 | */ | |
6325 | val = TIDFLOW_ERRBITS; /* these are W1C */ | |
0502f94c | 6326 | for (i = 0; i < dd->cfgctxts; i++) { |
f931551b | 6327 | int flow; |
da12c1f6 | 6328 | |
f931551b RC |
6329 | for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++) |
6330 | qib_write_ureg(dd, ur_rcvflowtable+flow, val, i); | |
6331 | } | |
6332 | ||
6333 | /* | |
6334 | * dual cards init to dual port recovery, single port cards to | |
6335 | * the one port. Dual port cards may later adjust to 1 port, | |
6336 | * and then back to dual port if both ports are connected | |
6337 | * */ | |
6338 | if (dd->num_pports) | |
6339 | setup_7322_link_recovery(dd->pport, dd->num_pports > 1); | |
6340 | } | |
6341 | ||
6342 | static int qib_init_7322_variables(struct qib_devdata *dd) | |
6343 | { | |
6344 | struct qib_pportdata *ppd; | |
6345 | unsigned features, pidx, sbufcnt; | |
6346 | int ret, mtu; | |
6347 | u32 sbufs, updthresh; | |
d4988623 | 6348 | resource_size_t vl15off; |
f931551b RC |
6349 | |
6350 | /* pport structs are contiguous, allocated after devdata */ | |
6351 | ppd = (struct qib_pportdata *)(dd + 1); | |
6352 | dd->pport = ppd; | |
6353 | ppd[0].dd = dd; | |
6354 | ppd[1].dd = dd; | |
6355 | ||
6356 | dd->cspec = (struct qib_chip_specific *)(ppd + 2); | |
6357 | ||
6358 | ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); | |
6359 | ppd[1].cpspec = &ppd[0].cpspec[1]; | |
6360 | ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */ | |
6361 | ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */ | |
6362 | ||
6363 | spin_lock_init(&dd->cspec->rcvmod_lock); | |
6364 | spin_lock_init(&dd->cspec->gpio_lock); | |
6365 | ||
6366 | /* we haven't yet set QIB_PRESENT, so use read directly */ | |
6367 | dd->revision = readq(&dd->kregbase[kr_revision]); | |
6368 | ||
6369 | if ((dd->revision & 0xffffffffU) == 0xffffffffU) { | |
7fac3301 MM |
6370 | qib_dev_err(dd, |
6371 | "Revision register read failure, giving up initialization\n"); | |
f931551b RC |
6372 | ret = -ENODEV; |
6373 | goto bail; | |
6374 | } | |
6375 | dd->flags |= QIB_PRESENT; /* now register routines work */ | |
6376 | ||
6377 | dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor); | |
6378 | dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor); | |
6379 | dd->cspec->r1 = dd->minrev == 1; | |
6380 | ||
6381 | get_7322_chip_params(dd); | |
6382 | features = qib_7322_boardname(dd); | |
6383 | ||
6384 | /* now that piobcnt2k and 4k set, we can allocate these */ | |
ac53e0f5 CJ |
6385 | sbufcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; |
6386 | ||
6387 | dd->cspec->sendchkenable = bitmap_zalloc(sbufcnt, GFP_KERNEL); | |
6388 | dd->cspec->sendgrhchk = bitmap_zalloc(sbufcnt, GFP_KERNEL); | |
6389 | dd->cspec->sendibchk = bitmap_zalloc(sbufcnt, GFP_KERNEL); | |
f931551b RC |
6390 | if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || |
6391 | !dd->cspec->sendibchk) { | |
f931551b RC |
6392 | ret = -ENOMEM; |
6393 | goto bail; | |
6394 | } | |
6395 | ||
6396 | ppd = dd->pport; | |
6397 | ||
6398 | /* | |
6399 | * GPIO bits for TWSI data and clock, | |
6400 | * used for serial EEPROM. | |
6401 | */ | |
6402 | dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; | |
6403 | dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; | |
6404 | dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV; | |
6405 | ||
6406 | dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY | | |
6407 | QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP | | |
6408 | QIB_HAS_THRESH_UPDATE | | |
6409 | (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0); | |
6410 | dd->flags |= qib_special_trigger ? | |
6411 | QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA; | |
6412 | ||
6413 | /* | |
6414 | * Setup initial values. These may change when PAT is enabled, but | |
6415 | * we need these to do initial chip register accesses. | |
6416 | */ | |
6417 | qib_7322_set_baseaddrs(dd); | |
6418 | ||
6419 | mtu = ib_mtu_enum_to_int(qib_ibmtu); | |
6420 | if (mtu == -1) | |
6421 | mtu = QIB_DEFAULT_MTU; | |
6422 | ||
6423 | dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; | |
6424 | /* all hwerrors become interrupts, unless special purposed */ | |
6425 | dd->cspec->hwerrmask = ~0ULL; | |
6426 | /* link_recovery setup causes these errors, so ignore them, | |
6427 | * other than clearing them when they occur */ | |
6428 | dd->cspec->hwerrmask &= | |
6429 | ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) | | |
6430 | SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) | | |
6431 | HWE_MASK(LATriggered)); | |
6432 | ||
6433 | for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) { | |
6434 | struct qib_chippport_specific *cp = ppd->cpspec; | |
da12c1f6 | 6435 | |
f931551b RC |
6436 | ppd->link_speed_supported = features & PORT_SPD_CAP; |
6437 | features >>= PORT_SPD_CAP_SHIFT; | |
6438 | if (!ppd->link_speed_supported) { | |
6439 | /* single port mode (7340, or configured) */ | |
6440 | dd->skip_kctxt_mask |= 1 << pidx; | |
6441 | if (pidx == 0) { | |
6442 | /* Make sure port is disabled. */ | |
6443 | qib_write_kreg_port(ppd, krp_rcvctrl, 0); | |
6444 | qib_write_kreg_port(ppd, krp_ibcctrl_a, 0); | |
6445 | ppd[0] = ppd[1]; | |
6446 | dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, | |
6447 | IBSerdesPClkNotDetectMask_0) | |
6448 | | SYM_MASK(HwErrMask, | |
6449 | SDmaMemReadErrMask_0)); | |
6450 | dd->cspec->int_enable_mask &= ~( | |
6451 | SYM_MASK(IntMask, SDmaCleanupDoneMask_0) | | |
6452 | SYM_MASK(IntMask, SDmaIdleIntMask_0) | | |
6453 | SYM_MASK(IntMask, SDmaProgressIntMask_0) | | |
6454 | SYM_MASK(IntMask, SDmaIntMask_0) | | |
6455 | SYM_MASK(IntMask, ErrIntMask_0) | | |
6456 | SYM_MASK(IntMask, SendDoneIntMask_0)); | |
6457 | } else { | |
6458 | /* Make sure port is disabled. */ | |
6459 | qib_write_kreg_port(ppd, krp_rcvctrl, 0); | |
6460 | qib_write_kreg_port(ppd, krp_ibcctrl_a, 0); | |
6461 | dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, | |
6462 | IBSerdesPClkNotDetectMask_1) | |
6463 | | SYM_MASK(HwErrMask, | |
6464 | SDmaMemReadErrMask_1)); | |
6465 | dd->cspec->int_enable_mask &= ~( | |
6466 | SYM_MASK(IntMask, SDmaCleanupDoneMask_1) | | |
6467 | SYM_MASK(IntMask, SDmaIdleIntMask_1) | | |
6468 | SYM_MASK(IntMask, SDmaProgressIntMask_1) | | |
6469 | SYM_MASK(IntMask, SDmaIntMask_1) | | |
6470 | SYM_MASK(IntMask, ErrIntMask_1) | | |
6471 | SYM_MASK(IntMask, SendDoneIntMask_1)); | |
6472 | } | |
6473 | continue; | |
6474 | } | |
6475 | ||
6476 | dd->num_pports++; | |
7d7632ad MM |
6477 | ret = qib_init_pportdata(ppd, dd, pidx, dd->num_pports); |
6478 | if (ret) { | |
6479 | dd->num_pports--; | |
6480 | goto bail; | |
6481 | } | |
f931551b RC |
6482 | |
6483 | ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X; | |
6484 | ppd->link_width_enabled = IB_WIDTH_4X; | |
6485 | ppd->link_speed_enabled = ppd->link_speed_supported; | |
6486 | /* | |
6487 | * Set the initial values to reasonable default, will be set | |
6488 | * for real when link is up. | |
6489 | */ | |
6490 | ppd->link_width_active = IB_WIDTH_4X; | |
6491 | ppd->link_speed_active = QIB_IB_SDR; | |
6492 | ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS]; | |
6493 | switch (qib_num_cfg_vls) { | |
6494 | case 1: | |
6495 | ppd->vls_supported = IB_VL_VL0; | |
6496 | break; | |
6497 | case 2: | |
6498 | ppd->vls_supported = IB_VL_VL0_1; | |
6499 | break; | |
6500 | default: | |
6501 | qib_devinfo(dd->pcidev, | |
6502 | "Invalid num_vls %u, using 4 VLs\n", | |
6503 | qib_num_cfg_vls); | |
6504 | qib_num_cfg_vls = 4; | |
df561f66 | 6505 | fallthrough; |
f931551b RC |
6506 | case 4: |
6507 | ppd->vls_supported = IB_VL_VL0_3; | |
6508 | break; | |
6509 | case 8: | |
6510 | if (mtu <= 2048) | |
6511 | ppd->vls_supported = IB_VL_VL0_7; | |
6512 | else { | |
6513 | qib_devinfo(dd->pcidev, | |
a46a2802 | 6514 | "Invalid num_vls %u for MTU %d , using 4 VLs\n", |
f931551b RC |
6515 | qib_num_cfg_vls, mtu); |
6516 | ppd->vls_supported = IB_VL_VL0_3; | |
6517 | qib_num_cfg_vls = 4; | |
6518 | } | |
6519 | break; | |
6520 | } | |
6521 | ppd->vls_operational = ppd->vls_supported; | |
6522 | ||
6523 | init_waitqueue_head(&cp->autoneg_wait); | |
6524 | INIT_DELAYED_WORK(&cp->autoneg_work, | |
6525 | autoneg_7322_work); | |
6526 | if (ppd->dd->cspec->r1) | |
6527 | INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work); | |
6528 | ||
6529 | /* | |
6530 | * For Mez and similar cards, no qsfp info, so do | |
6531 | * the "cable info" setup here. Can be overridden | |
6532 | * in adapter-specific routines. | |
6533 | */ | |
7c7a416e RC |
6534 | if (!(dd->flags & QIB_HAS_QSFP)) { |
6535 | if (!IS_QMH(dd) && !IS_QME(dd)) | |
7fac3301 MM |
6536 | qib_devinfo(dd->pcidev, |
6537 | "IB%u:%u: Unknown mezzanine card type\n", | |
6538 | dd->unit, ppd->port); | |
a77fcf89 | 6539 | cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME; |
f931551b | 6540 | /* |
a77fcf89 RC |
6541 | * Choose center value as default tx serdes setting |
6542 | * until changed through module parameter. | |
f931551b | 6543 | */ |
a77fcf89 RC |
6544 | ppd->cpspec->no_eep = IS_QMH(dd) ? |
6545 | TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4; | |
f931551b RC |
6546 | } else |
6547 | cp->h1_val = H1_FORCE_VAL; | |
6548 | ||
6549 | /* Avoid writes to chip for mini_init */ | |
6550 | if (!qib_mini_init) | |
6551 | write_7322_init_portregs(ppd); | |
6552 | ||
4037c92f | 6553 | timer_setup(&cp->chase_timer, reenable_chase, 0); |
f931551b RC |
6554 | |
6555 | ppd++; | |
6556 | } | |
6557 | ||
0a43e117 MM |
6558 | dd->rcvhdrentsize = qib_rcvhdrentsize ? |
6559 | qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE; | |
6560 | dd->rcvhdrsize = qib_rcvhdrsize ? | |
6561 | qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE; | |
a77fcf89 | 6562 | dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32); |
f931551b RC |
6563 | |
6564 | /* we always allocate at least 2048 bytes for eager buffers */ | |
6565 | dd->rcvegrbufsize = max(mtu, 2048); | |
9e1c0e43 | 6566 | dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); |
f931551b RC |
6567 | |
6568 | qib_7322_tidtemplate(dd); | |
6569 | ||
6570 | /* | |
6571 | * We can request a receive interrupt for 1 or | |
6572 | * more packets from current offset. | |
6573 | */ | |
6574 | dd->rhdrhead_intr_off = | |
6575 | (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT; | |
6576 | ||
6577 | /* setup the stats timer; the add_timer is done at end of init */ | |
4037c92f | 6578 | timer_setup(&dd->stats_timer, qib_get_7322_faststats, 0); |
f931551b RC |
6579 | |
6580 | dd->ureg_align = 0x10000; /* 64KB alignment */ | |
6581 | ||
6582 | dd->piosize2kmax_dwords = dd->piosize2k >> 2; | |
6583 | ||
6584 | qib_7322_config_ctxts(dd); | |
6585 | qib_set_ctxtcnt(dd); | |
6586 | ||
d4988623 LR |
6587 | /* |
6588 | * We do not set WC on the VL15 buffers to avoid | |
6589 | * a rare problem with unaligned writes from | |
6590 | * interrupt-flushed store buffers, so we need | |
6591 | * to map those separately here. We can't solve | |
6592 | * this for the rarely used mtrr case. | |
6593 | */ | |
6594 | ret = init_chip_wc_pat(dd, 0); | |
6595 | if (ret) | |
6596 | goto bail; | |
fce24a9d | 6597 | |
d4988623 LR |
6598 | /* vl15 buffers start just after the 4k buffers */ |
6599 | vl15off = dd->physaddr + (dd->piobufbase >> 32) + | |
6600 | dd->piobcnt4k * dd->align4k; | |
4bdc0d67 | 6601 | dd->piovl15base = ioremap(vl15off, |
d4988623 LR |
6602 | NUM_VL15_BUFS * dd->align4k); |
6603 | if (!dd->piovl15base) { | |
6604 | ret = -ENOMEM; | |
6605 | goto bail; | |
f931551b | 6606 | } |
d4988623 | 6607 | |
f931551b RC |
6608 | qib_7322_set_baseaddrs(dd); /* set chip access pointers now */ |
6609 | ||
6610 | ret = 0; | |
6611 | if (qib_mini_init) | |
6612 | goto bail; | |
6613 | if (!dd->num_pports) { | |
6614 | qib_dev_err(dd, "No ports enabled, giving up initialization\n"); | |
6615 | goto bail; /* no error, so can still figure out why err */ | |
6616 | } | |
6617 | ||
6618 | write_7322_initregs(dd); | |
6619 | ret = qib_create_ctxts(dd); | |
6620 | init_7322_cntrnames(dd); | |
6621 | ||
6622 | updthresh = 8U; /* update threshold */ | |
6623 | ||
6624 | /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA. | |
6625 | * reserve the update threshold amount for other kernel use, such | |
6626 | * as sending SMI, MAD, and ACKs, or 3, whichever is greater, | |
6627 | * unless we aren't enabling SDMA, in which case we want to use | |
6628 | * all the 4k bufs for the kernel. | |
6629 | * if this was less than the update threshold, we could wait | |
6630 | * a long time for an update. Coded this way because we | |
6631 | * sometimes change the update threshold for various reasons, | |
6632 | * and we want this to remain robust. | |
6633 | */ | |
6634 | if (dd->flags & QIB_HAS_SEND_DMA) { | |
6635 | dd->cspec->sdmabufcnt = dd->piobcnt4k; | |
6636 | sbufs = updthresh > 3 ? updthresh : 3; | |
6637 | } else { | |
6638 | dd->cspec->sdmabufcnt = 0; | |
6639 | sbufs = dd->piobcnt4k; | |
6640 | } | |
6641 | dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - | |
6642 | dd->cspec->sdmabufcnt; | |
6643 | dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; | |
6644 | dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ | |
bb77a077 | 6645 | dd->last_pio = dd->cspec->lastbuf_for_pio; |
f931551b RC |
6646 | dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ? |
6647 | dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0; | |
6648 | ||
6649 | /* | |
6650 | * If we have 16 user contexts, we will have 7 sbufs | |
6651 | * per context, so reduce the update threshold to match. We | |
6652 | * want to update before we actually run out, at low pbufs/ctxt | |
6653 | * so give ourselves some margin. | |
6654 | */ | |
6655 | if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh) | |
6656 | updthresh = dd->pbufsctxt - 2; | |
6657 | dd->cspec->updthresh_dflt = updthresh; | |
6658 | dd->cspec->updthresh = updthresh; | |
6659 | ||
6660 | /* before full enable, no interrupts, no locking needed */ | |
6661 | dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld)) | |
6662 | << SYM_LSB(SendCtrl, AvailUpdThld)) | | |
6663 | SYM_MASK(SendCtrl, SendBufAvailPad64Byte); | |
6664 | ||
6665 | dd->psxmitwait_supported = 1; | |
6666 | dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE; | |
6667 | bail: | |
6668 | if (!dd->ctxtcnt) | |
6669 | dd->ctxtcnt = 1; /* for other initialization code */ | |
6670 | ||
6671 | return ret; | |
6672 | } | |
6673 | ||
6674 | static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc, | |
6675 | u32 *pbufnum) | |
6676 | { | |
6677 | u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK; | |
6678 | struct qib_devdata *dd = ppd->dd; | |
6679 | ||
6680 | /* last is same for 2k and 4k, because we use 4k if all 2k busy */ | |
6681 | if (pbc & PBC_7322_VL15_SEND) { | |
6682 | first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx; | |
6683 | last = first; | |
6684 | } else { | |
6685 | if ((plen + 1) > dd->piosize2kmax_dwords) | |
6686 | first = dd->piobcnt2k; | |
6687 | else | |
6688 | first = 0; | |
6689 | last = dd->cspec->lastbuf_for_pio; | |
6690 | } | |
6691 | return qib_getsendbuf_range(dd, pbufnum, first, last); | |
6692 | } | |
6693 | ||
6694 | static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv, | |
6695 | u32 start) | |
6696 | { | |
6697 | qib_write_kreg_port(ppd, krp_psinterval, intv); | |
6698 | qib_write_kreg_port(ppd, krp_psstart, start); | |
6699 | } | |
6700 | ||
6701 | /* | |
6702 | * Must be called with sdma_lock held, or before init finished. | |
6703 | */ | |
6704 | static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt) | |
6705 | { | |
6706 | qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt); | |
6707 | } | |
6708 | ||
0b3ddf38 DL |
6709 | /* |
6710 | * sdma_lock should be acquired before calling this routine | |
6711 | */ | |
6712 | static void dump_sdma_7322_state(struct qib_pportdata *ppd) | |
6713 | { | |
6714 | u64 reg, reg1, reg2; | |
6715 | ||
6716 | reg = qib_read_kreg_port(ppd, krp_senddmastatus); | |
6717 | qib_dev_porterr(ppd->dd, ppd->port, | |
6718 | "SDMA senddmastatus: 0x%016llx\n", reg); | |
6719 | ||
6720 | reg = qib_read_kreg_port(ppd, krp_sendctrl); | |
6721 | qib_dev_porterr(ppd->dd, ppd->port, | |
6722 | "SDMA sendctrl: 0x%016llx\n", reg); | |
6723 | ||
6724 | reg = qib_read_kreg_port(ppd, krp_senddmabase); | |
6725 | qib_dev_porterr(ppd->dd, ppd->port, | |
6726 | "SDMA senddmabase: 0x%016llx\n", reg); | |
6727 | ||
6728 | reg = qib_read_kreg_port(ppd, krp_senddmabufmask0); | |
6729 | reg1 = qib_read_kreg_port(ppd, krp_senddmabufmask1); | |
6730 | reg2 = qib_read_kreg_port(ppd, krp_senddmabufmask2); | |
6731 | qib_dev_porterr(ppd->dd, ppd->port, | |
6732 | "SDMA senddmabufmask 0:%llx 1:%llx 2:%llx\n", | |
6733 | reg, reg1, reg2); | |
6734 | ||
6735 | /* get bufuse bits, clear them, and print them again if non-zero */ | |
6736 | reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0); | |
6737 | qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg); | |
6738 | reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1); | |
6739 | qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg1); | |
6740 | reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2); | |
6741 | qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg2); | |
6742 | /* 0 and 1 should always be zero, so print as short form */ | |
6743 | qib_dev_porterr(ppd->dd, ppd->port, | |
6744 | "SDMA current senddmabuf_use 0:%llx 1:%llx 2:%llx\n", | |
6745 | reg, reg1, reg2); | |
6746 | reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0); | |
6747 | reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1); | |
6748 | reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2); | |
6749 | /* 0 and 1 should always be zero, so print as short form */ | |
6750 | qib_dev_porterr(ppd->dd, ppd->port, | |
6751 | "SDMA cleared senddmabuf_use 0:%llx 1:%llx 2:%llx\n", | |
6752 | reg, reg1, reg2); | |
6753 | ||
6754 | reg = qib_read_kreg_port(ppd, krp_senddmatail); | |
6755 | qib_dev_porterr(ppd->dd, ppd->port, | |
6756 | "SDMA senddmatail: 0x%016llx\n", reg); | |
6757 | ||
6758 | reg = qib_read_kreg_port(ppd, krp_senddmahead); | |
6759 | qib_dev_porterr(ppd->dd, ppd->port, | |
6760 | "SDMA senddmahead: 0x%016llx\n", reg); | |
6761 | ||
6762 | reg = qib_read_kreg_port(ppd, krp_senddmaheadaddr); | |
6763 | qib_dev_porterr(ppd->dd, ppd->port, | |
6764 | "SDMA senddmaheadaddr: 0x%016llx\n", reg); | |
6765 | ||
6766 | reg = qib_read_kreg_port(ppd, krp_senddmalengen); | |
6767 | qib_dev_porterr(ppd->dd, ppd->port, | |
6768 | "SDMA senddmalengen: 0x%016llx\n", reg); | |
6769 | ||
6770 | reg = qib_read_kreg_port(ppd, krp_senddmadesccnt); | |
6771 | qib_dev_porterr(ppd->dd, ppd->port, | |
6772 | "SDMA senddmadesccnt: 0x%016llx\n", reg); | |
6773 | ||
6774 | reg = qib_read_kreg_port(ppd, krp_senddmaidlecnt); | |
6775 | qib_dev_porterr(ppd->dd, ppd->port, | |
6776 | "SDMA senddmaidlecnt: 0x%016llx\n", reg); | |
6777 | ||
6778 | reg = qib_read_kreg_port(ppd, krp_senddmaprioritythld); | |
6779 | qib_dev_porterr(ppd->dd, ppd->port, | |
6780 | "SDMA senddmapriorityhld: 0x%016llx\n", reg); | |
6781 | ||
6782 | reg = qib_read_kreg_port(ppd, krp_senddmareloadcnt); | |
6783 | qib_dev_porterr(ppd->dd, ppd->port, | |
6784 | "SDMA senddmareloadcnt: 0x%016llx\n", reg); | |
6785 | ||
6786 | dump_sdma_state(ppd); | |
6787 | } | |
6788 | ||
f931551b RC |
6789 | static struct sdma_set_state_action sdma_7322_action_table[] = { |
6790 | [qib_sdma_state_s00_hw_down] = { | |
6791 | .go_s99_running_tofalse = 1, | |
6792 | .op_enable = 0, | |
6793 | .op_intenable = 0, | |
6794 | .op_halt = 0, | |
6795 | .op_drain = 0, | |
6796 | }, | |
6797 | [qib_sdma_state_s10_hw_start_up_wait] = { | |
6798 | .op_enable = 0, | |
6799 | .op_intenable = 1, | |
6800 | .op_halt = 1, | |
6801 | .op_drain = 0, | |
6802 | }, | |
6803 | [qib_sdma_state_s20_idle] = { | |
6804 | .op_enable = 1, | |
6805 | .op_intenable = 1, | |
6806 | .op_halt = 1, | |
6807 | .op_drain = 0, | |
6808 | }, | |
6809 | [qib_sdma_state_s30_sw_clean_up_wait] = { | |
6810 | .op_enable = 0, | |
6811 | .op_intenable = 1, | |
6812 | .op_halt = 1, | |
6813 | .op_drain = 0, | |
6814 | }, | |
6815 | [qib_sdma_state_s40_hw_clean_up_wait] = { | |
6816 | .op_enable = 1, | |
6817 | .op_intenable = 1, | |
6818 | .op_halt = 1, | |
6819 | .op_drain = 0, | |
6820 | }, | |
6821 | [qib_sdma_state_s50_hw_halt_wait] = { | |
6822 | .op_enable = 1, | |
6823 | .op_intenable = 1, | |
6824 | .op_halt = 1, | |
6825 | .op_drain = 1, | |
6826 | }, | |
6827 | [qib_sdma_state_s99_running] = { | |
6828 | .op_enable = 1, | |
6829 | .op_intenable = 1, | |
6830 | .op_halt = 0, | |
6831 | .op_drain = 0, | |
6832 | .go_s99_running_totrue = 1, | |
6833 | }, | |
6834 | }; | |
6835 | ||
6836 | static void qib_7322_sdma_init_early(struct qib_pportdata *ppd) | |
6837 | { | |
6838 | ppd->sdma_state.set_state_action = sdma_7322_action_table; | |
6839 | } | |
6840 | ||
6841 | static int init_sdma_7322_regs(struct qib_pportdata *ppd) | |
6842 | { | |
6843 | struct qib_devdata *dd = ppd->dd; | |
6844 | unsigned lastbuf, erstbuf; | |
6845 | u64 senddmabufmask[3] = { 0 }; | |
4f953089 | 6846 | int n; |
f931551b RC |
6847 | |
6848 | qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys); | |
6849 | qib_sdma_7322_setlengen(ppd); | |
6850 | qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */ | |
6851 | qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt); | |
6852 | qib_write_kreg_port(ppd, krp_senddmadesccnt, 0); | |
6853 | qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys); | |
6854 | ||
6855 | if (dd->num_pports) | |
6856 | n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ | |
6857 | else | |
6858 | n = dd->cspec->sdmabufcnt; /* failsafe for init */ | |
6859 | erstbuf = (dd->piobcnt2k + dd->piobcnt4k) - | |
6860 | ((dd->num_pports == 1 || ppd->port == 2) ? n : | |
6861 | dd->cspec->sdmabufcnt); | |
6862 | lastbuf = erstbuf + n; | |
6863 | ||
6864 | ppd->sdma_state.first_sendbuf = erstbuf; | |
6865 | ppd->sdma_state.last_sendbuf = lastbuf; | |
6866 | for (; erstbuf < lastbuf; ++erstbuf) { | |
6867 | unsigned word = erstbuf / BITS_PER_LONG; | |
6868 | unsigned bit = erstbuf & (BITS_PER_LONG - 1); | |
6869 | ||
f931551b RC |
6870 | senddmabufmask[word] |= 1ULL << bit; |
6871 | } | |
6872 | qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]); | |
6873 | qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]); | |
6874 | qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]); | |
4f953089 | 6875 | return 0; |
f931551b RC |
6876 | } |
6877 | ||
6878 | /* sdma_lock must be held */ | |
6879 | static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd) | |
6880 | { | |
6881 | struct qib_devdata *dd = ppd->dd; | |
6882 | int sane; | |
6883 | int use_dmahead; | |
6884 | u16 swhead; | |
6885 | u16 swtail; | |
6886 | u16 cnt; | |
6887 | u16 hwhead; | |
6888 | ||
6889 | use_dmahead = __qib_sdma_running(ppd) && | |
6890 | (dd->flags & QIB_HAS_SDMA_TIMEOUT); | |
6891 | retry: | |
6892 | hwhead = use_dmahead ? | |
6893 | (u16) le64_to_cpu(*ppd->sdma_head_dma) : | |
6894 | (u16) qib_read_kreg_port(ppd, krp_senddmahead); | |
6895 | ||
6896 | swhead = ppd->sdma_descq_head; | |
6897 | swtail = ppd->sdma_descq_tail; | |
6898 | cnt = ppd->sdma_descq_cnt; | |
6899 | ||
6900 | if (swhead < swtail) | |
6901 | /* not wrapped */ | |
6902 | sane = (hwhead >= swhead) & (hwhead <= swtail); | |
6903 | else if (swhead > swtail) | |
6904 | /* wrapped around */ | |
6905 | sane = ((hwhead >= swhead) && (hwhead < cnt)) || | |
6906 | (hwhead <= swtail); | |
6907 | else | |
6908 | /* empty */ | |
6909 | sane = (hwhead == swhead); | |
6910 | ||
6911 | if (unlikely(!sane)) { | |
6912 | if (use_dmahead) { | |
6913 | /* try one more time, directly from the register */ | |
6914 | use_dmahead = 0; | |
6915 | goto retry; | |
6916 | } | |
6917 | /* proceed as if no progress */ | |
6918 | hwhead = swhead; | |
6919 | } | |
6920 | ||
6921 | return hwhead; | |
6922 | } | |
6923 | ||
6924 | static int qib_sdma_7322_busy(struct qib_pportdata *ppd) | |
6925 | { | |
6926 | u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus); | |
6927 | ||
6928 | return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) || | |
6929 | (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) || | |
6930 | !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) || | |
6931 | !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty)); | |
6932 | } | |
6933 | ||
6934 | /* | |
6935 | * Compute the amount of delay before sending the next packet if the | |
6936 | * port's send rate differs from the static rate set for the QP. | |
6937 | * The delay affects the next packet and the amount of the delay is | |
6938 | * based on the length of the this packet. | |
6939 | */ | |
6940 | static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen, | |
6941 | u8 srate, u8 vl) | |
6942 | { | |
6943 | u8 snd_mult = ppd->delay_mult; | |
6944 | u8 rcv_mult = ib_rate_to_delay[srate]; | |
6945 | u32 ret; | |
6946 | ||
6947 | ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0; | |
6948 | ||
6949 | /* Indicate VL15, else set the VL in the control word */ | |
6950 | if (vl == 15) | |
6951 | ret |= PBC_7322_VL15_SEND_CTRL; | |
6952 | else | |
6953 | ret |= vl << PBC_VL_NUM_LSB; | |
6954 | ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB; | |
6955 | ||
6956 | return ret; | |
6957 | } | |
6958 | ||
6959 | /* | |
6960 | * Enable the per-port VL15 send buffers for use. | |
6961 | * They follow the rest of the buffers, without a config parameter. | |
6962 | * This was in initregs, but that is done before the shadow | |
6963 | * is set up, and this has to be done after the shadow is | |
6964 | * set up. | |
6965 | */ | |
6966 | static void qib_7322_initvl15_bufs(struct qib_devdata *dd) | |
6967 | { | |
6968 | unsigned vl15bufs; | |
6969 | ||
6970 | vl15bufs = dd->piobcnt2k + dd->piobcnt4k; | |
6971 | qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS, | |
6972 | TXCHK_CHG_TYPE_KERN, NULL); | |
6973 | } | |
6974 | ||
6975 | static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd) | |
6976 | { | |
6977 | if (rcd->ctxt < NUM_IB_PORTS) { | |
6978 | if (rcd->dd->num_pports > 1) { | |
6979 | rcd->rcvegrcnt = KCTXT0_EGRCNT / 2; | |
6980 | rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0; | |
6981 | } else { | |
6982 | rcd->rcvegrcnt = KCTXT0_EGRCNT; | |
6983 | rcd->rcvegr_tid_base = 0; | |
6984 | } | |
6985 | } else { | |
6986 | rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; | |
6987 | rcd->rcvegr_tid_base = KCTXT0_EGRCNT + | |
6988 | (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt; | |
6989 | } | |
6990 | } | |
6991 | ||
6992 | #define QTXSLEEPS 5000 | |
6993 | static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start, | |
6994 | u32 len, u32 which, struct qib_ctxtdata *rcd) | |
6995 | { | |
6996 | int i; | |
6997 | const int last = start + len - 1; | |
6998 | const int lastr = last / BITS_PER_LONG; | |
6999 | u32 sleeps = 0; | |
7000 | int wait = rcd != NULL; | |
7001 | unsigned long flags; | |
7002 | ||
7003 | while (wait) { | |
f6aafac1 | 7004 | unsigned long shadow = 0; |
f931551b RC |
7005 | int cstart, previ = -1; |
7006 | ||
7007 | /* | |
7008 | * when flipping from kernel to user, we can't change | |
7009 | * the checking type if the buffer is allocated to the | |
7010 | * driver. It's OK the other direction, because it's | |
7011 | * from close, and we have just disarm'ed all the | |
7012 | * buffers. All the kernel to kernel changes are also | |
7013 | * OK. | |
7014 | */ | |
7015 | for (cstart = start; cstart <= last; cstart++) { | |
7016 | i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT) | |
7017 | / BITS_PER_LONG; | |
7018 | if (i != previ) { | |
7019 | shadow = (unsigned long) | |
7020 | le64_to_cpu(dd->pioavailregs_dma[i]); | |
7021 | previ = i; | |
7022 | } | |
7023 | if (test_bit(((2 * cstart) + | |
7024 | QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT) | |
7025 | % BITS_PER_LONG, &shadow)) | |
7026 | break; | |
7027 | } | |
7028 | ||
7029 | if (cstart > last) | |
7030 | break; | |
7031 | ||
7032 | if (sleeps == QTXSLEEPS) | |
7033 | break; | |
7034 | /* make sure we see an updated copy next time around */ | |
7035 | sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); | |
7036 | sleeps++; | |
a0a234d4 | 7037 | msleep(20); |
f931551b RC |
7038 | } |
7039 | ||
7040 | switch (which) { | |
7041 | case TXCHK_CHG_TYPE_DIS1: | |
7042 | /* | |
7043 | * disable checking on a range; used by diags; just | |
7044 | * one buffer, but still written generically | |
7045 | */ | |
7046 | for (i = start; i <= last; i++) | |
7047 | clear_bit(i, dd->cspec->sendchkenable); | |
7048 | break; | |
7049 | ||
7050 | case TXCHK_CHG_TYPE_ENAB1: | |
7051 | /* | |
7052 | * (re)enable checking on a range; used by diags; just | |
7053 | * one buffer, but still written generically; read | |
7054 | * scratch to be sure buffer actually triggered, not | |
7055 | * just flushed from processor. | |
7056 | */ | |
7057 | qib_read_kreg32(dd, kr_scratch); | |
7058 | for (i = start; i <= last; i++) | |
7059 | set_bit(i, dd->cspec->sendchkenable); | |
7060 | break; | |
7061 | ||
7062 | case TXCHK_CHG_TYPE_KERN: | |
7063 | /* usable by kernel */ | |
7064 | for (i = start; i <= last; i++) { | |
7065 | set_bit(i, dd->cspec->sendibchk); | |
7066 | clear_bit(i, dd->cspec->sendgrhchk); | |
7067 | } | |
7068 | spin_lock_irqsave(&dd->uctxt_lock, flags); | |
7069 | /* see if we need to raise avail update threshold */ | |
7070 | for (i = dd->first_user_ctxt; | |
7071 | dd->cspec->updthresh != dd->cspec->updthresh_dflt | |
7072 | && i < dd->cfgctxts; i++) | |
7073 | if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt && | |
7074 | ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1) | |
7075 | < dd->cspec->updthresh_dflt) | |
7076 | break; | |
7077 | spin_unlock_irqrestore(&dd->uctxt_lock, flags); | |
7078 | if (i == dd->cfgctxts) { | |
7079 | spin_lock_irqsave(&dd->sendctrl_lock, flags); | |
7080 | dd->cspec->updthresh = dd->cspec->updthresh_dflt; | |
7081 | dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); | |
7082 | dd->sendctrl |= (dd->cspec->updthresh & | |
7083 | SYM_RMASK(SendCtrl, AvailUpdThld)) << | |
7084 | SYM_LSB(SendCtrl, AvailUpdThld); | |
7085 | spin_unlock_irqrestore(&dd->sendctrl_lock, flags); | |
7086 | sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); | |
7087 | } | |
7088 | break; | |
7089 | ||
7090 | case TXCHK_CHG_TYPE_USER: | |
7091 | /* for user process */ | |
7092 | for (i = start; i <= last; i++) { | |
7093 | clear_bit(i, dd->cspec->sendibchk); | |
7094 | set_bit(i, dd->cspec->sendgrhchk); | |
7095 | } | |
7096 | spin_lock_irqsave(&dd->sendctrl_lock, flags); | |
7097 | if (rcd && rcd->subctxt_cnt && ((rcd->piocnt | |
7098 | / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { | |
7099 | dd->cspec->updthresh = (rcd->piocnt / | |
7100 | rcd->subctxt_cnt) - 1; | |
7101 | dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); | |
7102 | dd->sendctrl |= (dd->cspec->updthresh & | |
7103 | SYM_RMASK(SendCtrl, AvailUpdThld)) | |
7104 | << SYM_LSB(SendCtrl, AvailUpdThld); | |
7105 | spin_unlock_irqrestore(&dd->sendctrl_lock, flags); | |
7106 | sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); | |
7107 | } else | |
7108 | spin_unlock_irqrestore(&dd->sendctrl_lock, flags); | |
7109 | break; | |
7110 | ||
7111 | default: | |
7112 | break; | |
7113 | } | |
7114 | ||
7115 | for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i) | |
7116 | qib_write_kreg(dd, kr_sendcheckmask + i, | |
7117 | dd->cspec->sendchkenable[i]); | |
7118 | ||
7119 | for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) { | |
7120 | qib_write_kreg(dd, kr_sendgrhcheckmask + i, | |
7121 | dd->cspec->sendgrhchk[i]); | |
7122 | qib_write_kreg(dd, kr_sendibpktmask + i, | |
7123 | dd->cspec->sendibchk[i]); | |
7124 | } | |
7125 | ||
7126 | /* | |
7127 | * Be sure whatever we did was seen by the chip and acted upon, | |
7128 | * before we return. Mostly important for which >= 2. | |
7129 | */ | |
7130 | qib_read_kreg32(dd, kr_scratch); | |
7131 | } | |
7132 | ||
7133 | ||
7134 | /* useful for trigger analyzers, etc. */ | |
7135 | static void writescratch(struct qib_devdata *dd, u32 val) | |
7136 | { | |
7137 | qib_write_kreg(dd, kr_scratch, val); | |
7138 | } | |
7139 | ||
7140 | /* Dummy for now, use chip regs soon */ | |
7141 | static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum) | |
7142 | { | |
7143 | return -ENXIO; | |
7144 | } | |
7145 | ||
7146 | /** | |
7147 | * qib_init_iba7322_funcs - set up the chip-specific function pointers | |
a8a47b16 | 7148 | * @pdev: the pci_dev for qlogic_ib device |
f931551b RC |
7149 | * @ent: pci_device_id struct for this dev |
7150 | * | |
7151 | * Also allocates, inits, and returns the devdata struct for this | |
7152 | * device instance | |
7153 | * | |
7154 | * This is global, and is called directly at init to set up the | |
7155 | * chip-specific function pointers for later use. | |
7156 | */ | |
7157 | struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev, | |
7158 | const struct pci_device_id *ent) | |
7159 | { | |
7160 | struct qib_devdata *dd; | |
7161 | int ret, i; | |
7162 | u32 tabsize, actual_cnt = 0; | |
7163 | ||
7164 | dd = qib_alloc_devdata(pdev, | |
7165 | NUM_IB_PORTS * sizeof(struct qib_pportdata) + | |
7166 | sizeof(struct qib_chip_specific) + | |
7167 | NUM_IB_PORTS * sizeof(struct qib_chippport_specific)); | |
7168 | if (IS_ERR(dd)) | |
7169 | goto bail; | |
7170 | ||
7171 | dd->f_bringup_serdes = qib_7322_bringup_serdes; | |
7172 | dd->f_cleanup = qib_setup_7322_cleanup; | |
7173 | dd->f_clear_tids = qib_7322_clear_tids; | |
7174 | dd->f_free_irq = qib_7322_free_irq; | |
7175 | dd->f_get_base_info = qib_7322_get_base_info; | |
7176 | dd->f_get_msgheader = qib_7322_get_msgheader; | |
7177 | dd->f_getsendbuf = qib_7322_getsendbuf; | |
7178 | dd->f_gpio_mod = gpio_7322_mod; | |
7179 | dd->f_eeprom_wen = qib_7322_eeprom_wen; | |
7180 | dd->f_hdrqempty = qib_7322_hdrqempty; | |
7181 | dd->f_ib_updown = qib_7322_ib_updown; | |
7182 | dd->f_init_ctxt = qib_7322_init_ctxt; | |
7183 | dd->f_initvl15_bufs = qib_7322_initvl15_bufs; | |
7184 | dd->f_intr_fallback = qib_7322_intr_fallback; | |
7185 | dd->f_late_initreg = qib_late_7322_initreg; | |
7186 | dd->f_setpbc_control = qib_7322_setpbc_control; | |
7187 | dd->f_portcntr = qib_portcntr_7322; | |
7188 | dd->f_put_tid = qib_7322_put_tid; | |
7189 | dd->f_quiet_serdes = qib_7322_mini_quiet_serdes; | |
7190 | dd->f_rcvctrl = rcvctrl_7322_mod; | |
7191 | dd->f_read_cntrs = qib_read_7322cntrs; | |
7192 | dd->f_read_portcntrs = qib_read_7322portcntrs; | |
7193 | dd->f_reset = qib_do_7322_reset; | |
7194 | dd->f_init_sdma_regs = init_sdma_7322_regs; | |
7195 | dd->f_sdma_busy = qib_sdma_7322_busy; | |
7196 | dd->f_sdma_gethead = qib_sdma_7322_gethead; | |
7197 | dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl; | |
7198 | dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt; | |
7199 | dd->f_sdma_update_tail = qib_sdma_update_7322_tail; | |
7200 | dd->f_sendctrl = sendctrl_7322_mod; | |
7201 | dd->f_set_armlaunch = qib_set_7322_armlaunch; | |
7202 | dd->f_set_cntr_sample = qib_set_cntr_7322_sample; | |
7203 | dd->f_iblink_state = qib_7322_iblink_state; | |
7204 | dd->f_ibphys_portstate = qib_7322_phys_portstate; | |
7205 | dd->f_get_ib_cfg = qib_7322_get_ib_cfg; | |
7206 | dd->f_set_ib_cfg = qib_7322_set_ib_cfg; | |
7207 | dd->f_set_ib_loopback = qib_7322_set_loopback; | |
7208 | dd->f_get_ib_table = qib_7322_get_ib_table; | |
7209 | dd->f_set_ib_table = qib_7322_set_ib_table; | |
7210 | dd->f_set_intr_state = qib_7322_set_intr_state; | |
7211 | dd->f_setextled = qib_setup_7322_setextled; | |
7212 | dd->f_txchk_change = qib_7322_txchk_change; | |
7213 | dd->f_update_usrhead = qib_update_7322_usrhead; | |
7214 | dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr; | |
7215 | dd->f_xgxs_reset = qib_7322_mini_pcs_reset; | |
7216 | dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up; | |
7217 | dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up; | |
7218 | dd->f_sdma_init_early = qib_7322_sdma_init_early; | |
7219 | dd->f_writescratch = writescratch; | |
7220 | dd->f_tempsense_rd = qib_7322_tempsense_rd; | |
8469ba39 MM |
7221 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
7222 | dd->f_notify_dca = qib_7322_notify_dca; | |
7223 | #endif | |
f931551b RC |
7224 | /* |
7225 | * Do remaining PCIe setup and save PCIe values in dd. | |
7226 | * Any error printing is already done by the init code. | |
7227 | * On return, we have the chip mapped, but chip registers | |
7228 | * are not set up until start of qib_init_7322_variables. | |
7229 | */ | |
7230 | ret = qib_pcie_ddinit(dd, pdev, ent); | |
7231 | if (ret < 0) | |
7232 | goto bail_free; | |
7233 | ||
7234 | /* initialize chip-specific variables */ | |
7235 | ret = qib_init_7322_variables(dd); | |
7236 | if (ret) | |
7237 | goto bail_cleanup; | |
7238 | ||
7239 | if (qib_mini_init || !dd->num_pports) | |
7240 | goto bail; | |
7241 | ||
7242 | /* | |
7243 | * Determine number of vectors we want; depends on port count | |
7244 | * and number of configured kernel receive queues actually used. | |
7245 | * Should also depend on whether sdma is enabled or not, but | |
7246 | * that's such a rare testing case it's not worth worrying about. | |
7247 | */ | |
7248 | tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table); | |
7249 | for (i = 0; i < tabsize; i++) | |
7250 | if ((i < ARRAY_SIZE(irq_table) && | |
7251 | irq_table[i].port <= dd->num_pports) || | |
7252 | (i >= ARRAY_SIZE(irq_table) && | |
7253 | dd->rcd[i - ARRAY_SIZE(irq_table)])) | |
7254 | actual_cnt++; | |
e67306a3 MM |
7255 | /* reduce by ctxt's < 2 */ |
7256 | if (qib_krcvq01_no_msi) | |
7257 | actual_cnt -= dd->num_pports; | |
7258 | ||
f931551b | 7259 | tabsize = actual_cnt; |
6396bb22 KC |
7260 | dd->cspec->msix_entries = kcalloc(tabsize, |
7261 | sizeof(struct qib_msix_entry), | |
7262 | GFP_KERNEL); | |
c40a83b9 | 7263 | if (!dd->cspec->msix_entries) |
f931551b | 7264 | tabsize = 0; |
c40a83b9 | 7265 | |
581d01aa | 7266 | if (qib_pcie_params(dd, 8, &tabsize)) |
7fac3301 MM |
7267 | qib_dev_err(dd, |
7268 | "Failed to setup PCIe or interrupts; continuing anyway\n"); | |
f931551b RC |
7269 | /* may be less than we wanted, if not enough available */ |
7270 | dd->cspec->num_msix_entries = tabsize; | |
7271 | ||
7272 | /* setup interrupt handler */ | |
7273 | qib_setup_7322_interrupt(dd, 1); | |
7274 | ||
7275 | /* clear diagctrl register, in case diags were running and crashed */ | |
7276 | qib_write_kreg(dd, kr_hwdiagctrl, 0); | |
8469ba39 MM |
7277 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
7278 | if (!dca_add_requester(&pdev->dev)) { | |
7279 | qib_devinfo(dd->pcidev, "DCA enabled\n"); | |
7280 | dd->flags |= QIB_DCA_ENABLED; | |
7281 | qib_setup_dca(dd); | |
7282 | } | |
7283 | #endif | |
f931551b RC |
7284 | goto bail; |
7285 | ||
7286 | bail_cleanup: | |
7287 | qib_pcie_ddcleanup(dd); | |
7288 | bail_free: | |
7289 | qib_free_devdata(dd); | |
7290 | dd = ERR_PTR(ret); | |
7291 | bail: | |
7292 | return dd; | |
7293 | } | |
7294 | ||
7295 | /* | |
7296 | * Set the table entry at the specified index from the table specifed. | |
7297 | * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first | |
7298 | * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR. | |
7299 | * 'idx' below addresses the correct entry, while its 4 LSBs select the | |
7300 | * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table. | |
7301 | */ | |
7302 | #define DDS_ENT_AMP_LSB 14 | |
7303 | #define DDS_ENT_MAIN_LSB 9 | |
7304 | #define DDS_ENT_POST_LSB 5 | |
7305 | #define DDS_ENT_PRE_XTRA_LSB 3 | |
7306 | #define DDS_ENT_PRE_LSB 0 | |
7307 | ||
7308 | /* | |
7309 | * Set one entry in the TxDDS table for spec'd port | |
7310 | * ridx picks one of the entries, while tp points | |
7311 | * to the appropriate table entry. | |
7312 | */ | |
7313 | static void set_txdds(struct qib_pportdata *ppd, int ridx, | |
7314 | const struct txdds_ent *tp) | |
7315 | { | |
7316 | struct qib_devdata *dd = ppd->dd; | |
7317 | u32 pack_ent; | |
7318 | int regidx; | |
7319 | ||
7320 | /* Get correct offset in chip-space, and in source table */ | |
7321 | regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx; | |
7322 | /* | |
7323 | * We do not use qib_write_kreg_port() because it was intended | |
7324 | * only for registers in the lower "port specific" pages. | |
7325 | * So do index calculation by hand. | |
7326 | */ | |
7327 | if (ppd->hw_pidx) | |
7328 | regidx += (dd->palign / sizeof(u64)); | |
7329 | ||
7330 | pack_ent = tp->amp << DDS_ENT_AMP_LSB; | |
7331 | pack_ent |= tp->main << DDS_ENT_MAIN_LSB; | |
7332 | pack_ent |= tp->pre << DDS_ENT_PRE_LSB; | |
7333 | pack_ent |= tp->post << DDS_ENT_POST_LSB; | |
7334 | qib_write_kreg(dd, regidx, pack_ent); | |
7335 | /* Prevent back-to-back writes by hitting scratch */ | |
7336 | qib_write_kreg(ppd->dd, kr_scratch, 0); | |
7337 | } | |
7338 | ||
7339 | static const struct vendor_txdds_ent vendor_txdds[] = { | |
7340 | { /* Amphenol 1m 30awg NoEq */ | |
7341 | { 0x41, 0x50, 0x48 }, "584470002 ", | |
7342 | { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 }, | |
7343 | }, | |
7344 | { /* Amphenol 3m 28awg NoEq */ | |
7345 | { 0x41, 0x50, 0x48 }, "584470004 ", | |
7346 | { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 }, | |
7347 | }, | |
7348 | { /* Finisar 3m OM2 Optical */ | |
7349 | { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL", | |
7350 | { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 }, | |
7351 | }, | |
7352 | { /* Finisar 30m OM2 Optical */ | |
7353 | { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL", | |
7354 | { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 }, | |
7355 | }, | |
7356 | { /* Finisar Default OM2 Optical */ | |
7357 | { 0x00, 0x90, 0x65 }, NULL, | |
7358 | { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 }, | |
7359 | }, | |
7360 | { /* Gore 1m 30awg NoEq */ | |
7361 | { 0x00, 0x21, 0x77 }, "QSN3300-1 ", | |
7362 | { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 }, | |
7363 | }, | |
7364 | { /* Gore 2m 30awg NoEq */ | |
7365 | { 0x00, 0x21, 0x77 }, "QSN3300-2 ", | |
7366 | { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 }, | |
7367 | }, | |
7368 | { /* Gore 1m 28awg NoEq */ | |
7369 | { 0x00, 0x21, 0x77 }, "QSN3800-1 ", | |
7370 | { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 }, | |
7371 | }, | |
7372 | { /* Gore 3m 28awg NoEq */ | |
7373 | { 0x00, 0x21, 0x77 }, "QSN3800-3 ", | |
7374 | { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 }, | |
7375 | }, | |
7376 | { /* Gore 5m 24awg Eq */ | |
7377 | { 0x00, 0x21, 0x77 }, "QSN7000-5 ", | |
7378 | { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 }, | |
7379 | }, | |
7380 | { /* Gore 7m 24awg Eq */ | |
7381 | { 0x00, 0x21, 0x77 }, "QSN7000-7 ", | |
7382 | { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 }, | |
7383 | }, | |
7384 | { /* Gore 5m 26awg Eq */ | |
7385 | { 0x00, 0x21, 0x77 }, "QSN7600-5 ", | |
7386 | { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 }, | |
7387 | }, | |
7388 | { /* Gore 7m 26awg Eq */ | |
7389 | { 0x00, 0x21, 0x77 }, "QSN7600-7 ", | |
7390 | { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 }, | |
7391 | }, | |
7392 | { /* Intersil 12m 24awg Active */ | |
7393 | { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224", | |
7394 | { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 }, | |
7395 | }, | |
7396 | { /* Intersil 10m 28awg Active */ | |
7397 | { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028", | |
7398 | { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 }, | |
7399 | }, | |
7400 | { /* Intersil 7m 30awg Active */ | |
7401 | { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730", | |
7402 | { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 }, | |
7403 | }, | |
7404 | { /* Intersil 5m 32awg Active */ | |
7405 | { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532", | |
7406 | { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 }, | |
7407 | }, | |
7408 | { /* Intersil Default Active */ | |
7409 | { 0x00, 0x30, 0xB4 }, NULL, | |
7410 | { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 }, | |
7411 | }, | |
7412 | { /* Luxtera 20m Active Optical */ | |
7413 | { 0x00, 0x25, 0x63 }, NULL, | |
7414 | { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 }, | |
7415 | }, | |
7416 | { /* Molex 1M Cu loopback */ | |
7417 | { 0x00, 0x09, 0x3A }, "74763-0025 ", | |
7418 | { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, | |
7419 | }, | |
7420 | { /* Molex 2m 28awg NoEq */ | |
7421 | { 0x00, 0x09, 0x3A }, "74757-2201 ", | |
7422 | { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 }, | |
7423 | }, | |
7424 | }; | |
7425 | ||
7426 | static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = { | |
7427 | /* amp, pre, main, post */ | |
7428 | { 2, 2, 15, 6 }, /* Loopback */ | |
7429 | { 0, 0, 0, 1 }, /* 2 dB */ | |
7430 | { 0, 0, 0, 2 }, /* 3 dB */ | |
7431 | { 0, 0, 0, 3 }, /* 4 dB */ | |
7432 | { 0, 0, 0, 4 }, /* 5 dB */ | |
7433 | { 0, 0, 0, 5 }, /* 6 dB */ | |
7434 | { 0, 0, 0, 6 }, /* 7 dB */ | |
7435 | { 0, 0, 0, 7 }, /* 8 dB */ | |
7436 | { 0, 0, 0, 8 }, /* 9 dB */ | |
7437 | { 0, 0, 0, 9 }, /* 10 dB */ | |
7438 | { 0, 0, 0, 10 }, /* 11 dB */ | |
7439 | { 0, 0, 0, 11 }, /* 12 dB */ | |
7440 | { 0, 0, 0, 12 }, /* 13 dB */ | |
7441 | { 0, 0, 0, 13 }, /* 14 dB */ | |
7442 | { 0, 0, 0, 14 }, /* 15 dB */ | |
7443 | { 0, 0, 0, 15 }, /* 16 dB */ | |
7444 | }; | |
7445 | ||
7446 | static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = { | |
7447 | /* amp, pre, main, post */ | |
7448 | { 2, 2, 15, 6 }, /* Loopback */ | |
7449 | { 0, 0, 0, 8 }, /* 2 dB */ | |
7450 | { 0, 0, 0, 8 }, /* 3 dB */ | |
7451 | { 0, 0, 0, 9 }, /* 4 dB */ | |
7452 | { 0, 0, 0, 9 }, /* 5 dB */ | |
7453 | { 0, 0, 0, 10 }, /* 6 dB */ | |
7454 | { 0, 0, 0, 10 }, /* 7 dB */ | |
7455 | { 0, 0, 0, 11 }, /* 8 dB */ | |
7456 | { 0, 0, 0, 11 }, /* 9 dB */ | |
7457 | { 0, 0, 0, 12 }, /* 10 dB */ | |
7458 | { 0, 0, 0, 12 }, /* 11 dB */ | |
7459 | { 0, 0, 0, 13 }, /* 12 dB */ | |
7460 | { 0, 0, 0, 13 }, /* 13 dB */ | |
7461 | { 0, 0, 0, 14 }, /* 14 dB */ | |
7462 | { 0, 0, 0, 14 }, /* 15 dB */ | |
7463 | { 0, 0, 0, 15 }, /* 16 dB */ | |
7464 | }; | |
7465 | ||
7466 | static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = { | |
7467 | /* amp, pre, main, post */ | |
7468 | { 2, 2, 15, 6 }, /* Loopback */ | |
a77fcf89 RC |
7469 | { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */ |
7470 | { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */ | |
f931551b RC |
7471 | { 0, 1, 0, 11 }, /* 4 dB */ |
7472 | { 0, 1, 0, 13 }, /* 5 dB */ | |
7473 | { 0, 1, 0, 15 }, /* 6 dB */ | |
7474 | { 0, 1, 3, 15 }, /* 7 dB */ | |
7475 | { 0, 1, 7, 15 }, /* 8 dB */ | |
7476 | { 0, 1, 7, 15 }, /* 9 dB */ | |
7477 | { 0, 1, 8, 15 }, /* 10 dB */ | |
7478 | { 0, 1, 9, 15 }, /* 11 dB */ | |
7479 | { 0, 1, 10, 15 }, /* 12 dB */ | |
7480 | { 0, 2, 6, 15 }, /* 13 dB */ | |
7481 | { 0, 2, 7, 15 }, /* 14 dB */ | |
7482 | { 0, 2, 8, 15 }, /* 15 dB */ | |
7483 | { 0, 2, 9, 15 }, /* 16 dB */ | |
7484 | }; | |
7485 | ||
a77fcf89 RC |
7486 | /* |
7487 | * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ. | |
7488 | * These are mostly used for mez cards going through connectors | |
7489 | * and backplane traces, but can be used to add other "unusual" | |
7490 | * table values as well. | |
7491 | */ | |
7492 | static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = { | |
7493 | /* amp, pre, main, post */ | |
7494 | { 0, 0, 0, 1 }, /* QMH7342 backplane settings */ | |
7495 | { 0, 0, 0, 1 }, /* QMH7342 backplane settings */ | |
7496 | { 0, 0, 0, 2 }, /* QMH7342 backplane settings */ | |
7497 | { 0, 0, 0, 2 }, /* QMH7342 backplane settings */ | |
7c7a416e RC |
7498 | { 0, 0, 0, 3 }, /* QMH7342 backplane settings */ |
7499 | { 0, 0, 0, 4 }, /* QMH7342 backplane settings */ | |
22baa407 MH |
7500 | { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */ |
7501 | { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */ | |
7502 | { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */ | |
7503 | { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */ | |
7504 | { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */ | |
7505 | { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */ | |
7506 | { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */ | |
7507 | { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */ | |
7508 | { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */ | |
7509 | { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */ | |
7510 | { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */ | |
7511 | { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */ | |
a77fcf89 RC |
7512 | }; |
7513 | ||
7514 | static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = { | |
7515 | /* amp, pre, main, post */ | |
7516 | { 0, 0, 0, 7 }, /* QMH7342 backplane settings */ | |
7517 | { 0, 0, 0, 7 }, /* QMH7342 backplane settings */ | |
7518 | { 0, 0, 0, 8 }, /* QMH7342 backplane settings */ | |
7519 | { 0, 0, 0, 8 }, /* QMH7342 backplane settings */ | |
7c7a416e RC |
7520 | { 0, 0, 0, 9 }, /* QMH7342 backplane settings */ |
7521 | { 0, 0, 0, 10 }, /* QMH7342 backplane settings */ | |
22baa407 MH |
7522 | { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */ |
7523 | { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */ | |
7524 | { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */ | |
7525 | { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */ | |
7526 | { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */ | |
7527 | { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */ | |
7528 | { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */ | |
7529 | { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */ | |
7530 | { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */ | |
7531 | { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */ | |
7532 | { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */ | |
7533 | { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */ | |
a77fcf89 RC |
7534 | }; |
7535 | ||
7536 | static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = { | |
7537 | /* amp, pre, main, post */ | |
7538 | { 0, 1, 0, 4 }, /* QMH7342 backplane settings */ | |
7539 | { 0, 1, 0, 5 }, /* QMH7342 backplane settings */ | |
7540 | { 0, 1, 0, 6 }, /* QMH7342 backplane settings */ | |
7541 | { 0, 1, 0, 8 }, /* QMH7342 backplane settings */ | |
7c7a416e RC |
7542 | { 0, 1, 0, 10 }, /* QMH7342 backplane settings */ |
7543 | { 0, 1, 0, 12 }, /* QMH7342 backplane settings */ | |
22baa407 MH |
7544 | { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */ |
7545 | { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */ | |
7546 | { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */ | |
7547 | { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */ | |
7548 | { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */ | |
7549 | { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */ | |
7550 | { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */ | |
7551 | { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */ | |
7552 | { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */ | |
7553 | { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */ | |
7554 | { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */ | |
7555 | { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */ | |
a77fcf89 RC |
7556 | }; |
7557 | ||
e706203c MM |
7558 | static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = { |
7559 | /* amp, pre, main, post */ | |
7560 | { 0, 0, 0, 0 }, /* QME7342 mfg settings */ | |
7561 | { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */ | |
7562 | }; | |
7563 | ||
f931551b RC |
7564 | static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds, |
7565 | unsigned atten) | |
7566 | { | |
7567 | /* | |
7568 | * The attenuation table starts at 2dB for entry 1, | |
7569 | * with entry 0 being the loopback entry. | |
7570 | */ | |
7571 | if (atten <= 2) | |
7572 | atten = 1; | |
7573 | else if (atten > TXDDS_TABLE_SZ) | |
7574 | atten = TXDDS_TABLE_SZ - 1; | |
7575 | else | |
7576 | atten--; | |
7577 | return txdds + atten; | |
7578 | } | |
7579 | ||
7580 | /* | |
a77fcf89 | 7581 | * if override is set, the module parameter txselect has a value |
f931551b RC |
7582 | * for this specific port, so use it, rather than our normal mechanism. |
7583 | */ | |
7584 | static void find_best_ent(struct qib_pportdata *ppd, | |
7585 | const struct txdds_ent **sdr_dds, | |
7586 | const struct txdds_ent **ddr_dds, | |
7587 | const struct txdds_ent **qdr_dds, int override) | |
7588 | { | |
7589 | struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache; | |
7590 | int idx; | |
7591 | ||
7592 | /* Search table of known cables */ | |
7593 | for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) { | |
7594 | const struct vendor_txdds_ent *v = vendor_txdds + idx; | |
7595 | ||
7596 | if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) && | |
7597 | (!v->partnum || | |
7598 | !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) { | |
7599 | *sdr_dds = &v->sdr; | |
7600 | *ddr_dds = &v->ddr; | |
7601 | *qdr_dds = &v->qdr; | |
7602 | return; | |
7603 | } | |
7604 | } | |
7605 | ||
dde05cbd MH |
7606 | /* Active cables don't have attenuation so we only set SERDES |
7607 | * settings to account for the attenuation of the board traces. */ | |
f931551b RC |
7608 | if (!override && QSFP_IS_ACTIVE(qd->tech)) { |
7609 | *sdr_dds = txdds_sdr + ppd->dd->board_atten; | |
7610 | *ddr_dds = txdds_ddr + ppd->dd->board_atten; | |
7611 | *qdr_dds = txdds_qdr + ppd->dd->board_atten; | |
7612 | return; | |
7613 | } | |
7614 | ||
7615 | if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] || | |
7616 | qd->atten[1])) { | |
7617 | *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]); | |
7618 | *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]); | |
7619 | *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]); | |
7620 | return; | |
a77fcf89 | 7621 | } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) { |
f931551b RC |
7622 | /* |
7623 | * If we have no (or incomplete) data from the cable | |
a77fcf89 RC |
7624 | * EEPROM, or no QSFP, or override is set, use the |
7625 | * module parameter value to index into the attentuation | |
7626 | * table. | |
f931551b | 7627 | */ |
a77fcf89 RC |
7628 | idx = ppd->cpspec->no_eep; |
7629 | *sdr_dds = &txdds_sdr[idx]; | |
7630 | *ddr_dds = &txdds_ddr[idx]; | |
7631 | *qdr_dds = &txdds_qdr[idx]; | |
7632 | } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) { | |
7633 | /* similar to above, but index into the "extra" table. */ | |
7634 | idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ; | |
7635 | *sdr_dds = &txdds_extra_sdr[idx]; | |
7636 | *ddr_dds = &txdds_extra_ddr[idx]; | |
7637 | *qdr_dds = &txdds_extra_qdr[idx]; | |
e706203c MM |
7638 | } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) && |
7639 | ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + | |
7640 | TXDDS_MFG_SZ)) { | |
7641 | idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ); | |
7fac3301 | 7642 | pr_info("IB%u:%u use idx %u into txdds_mfg\n", |
e706203c MM |
7643 | ppd->dd->unit, ppd->port, idx); |
7644 | *sdr_dds = &txdds_extra_mfg[idx]; | |
7645 | *ddr_dds = &txdds_extra_mfg[idx]; | |
7646 | *qdr_dds = &txdds_extra_mfg[idx]; | |
a77fcf89 RC |
7647 | } else { |
7648 | /* this shouldn't happen, it's range checked */ | |
7649 | *sdr_dds = txdds_sdr + qib_long_atten; | |
7650 | *ddr_dds = txdds_ddr + qib_long_atten; | |
7651 | *qdr_dds = txdds_qdr + qib_long_atten; | |
f931551b RC |
7652 | } |
7653 | } | |
7654 | ||
7655 | static void init_txdds_table(struct qib_pportdata *ppd, int override) | |
7656 | { | |
7657 | const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds; | |
7658 | struct txdds_ent *dds; | |
7659 | int idx; | |
7660 | int single_ent = 0; | |
7661 | ||
a77fcf89 RC |
7662 | find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override); |
7663 | ||
7664 | /* for mez cards or override, use the selected value for all entries */ | |
7665 | if (!(ppd->dd->flags & QIB_HAS_QSFP) || override) | |
f931551b | 7666 | single_ent = 1; |
f931551b RC |
7667 | |
7668 | /* Fill in the first entry with the best entry found. */ | |
7669 | set_txdds(ppd, 0, sdr_dds); | |
7670 | set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds); | |
7671 | set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds); | |
a77fcf89 RC |
7672 | if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | |
7673 | QIBL_LINKACTIVE)) { | |
7674 | dds = (struct txdds_ent *)(ppd->link_speed_active == | |
7675 | QIB_IB_QDR ? qdr_dds : | |
7676 | (ppd->link_speed_active == | |
7677 | QIB_IB_DDR ? ddr_dds : sdr_dds)); | |
7678 | write_tx_serdes_param(ppd, dds); | |
7679 | } | |
f931551b RC |
7680 | |
7681 | /* Fill in the remaining entries with the default table values. */ | |
7682 | for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) { | |
7683 | set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx); | |
7684 | set_txdds(ppd, idx + TXDDS_TABLE_SZ, | |
7685 | single_ent ? ddr_dds : txdds_ddr + idx); | |
7686 | set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ, | |
7687 | single_ent ? qdr_dds : txdds_qdr + idx); | |
7688 | } | |
7689 | } | |
7690 | ||
7691 | #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl) | |
7692 | #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg) | |
7693 | #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy) | |
7694 | #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address) | |
7695 | #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data) | |
7696 | #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read) | |
7697 | #define AHB_TRANS_TRIES 10 | |
7698 | ||
7699 | /* | |
7700 | * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4, | |
7701 | * 5=subsystem which is why most calls have "chan + chan >> 1" | |
7702 | * for the channel argument. | |
7703 | */ | |
7704 | static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr, | |
7705 | u32 data, u32 mask) | |
7706 | { | |
7707 | u32 rd_data, wr_data, sz_mask; | |
7708 | u64 trans, acc, prev_acc; | |
7709 | u32 ret = 0xBAD0BAD; | |
7710 | int tries; | |
7711 | ||
7712 | prev_acc = qib_read_kreg64(dd, KR_AHB_ACC); | |
7713 | /* From this point on, make sure we return access */ | |
7714 | acc = (quad << 1) | 1; | |
7715 | qib_write_kreg(dd, KR_AHB_ACC, acc); | |
7716 | ||
7717 | for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { | |
7718 | trans = qib_read_kreg64(dd, KR_AHB_TRANS); | |
7719 | if (trans & AHB_TRANS_RDY) | |
7720 | break; | |
7721 | } | |
7722 | if (tries >= AHB_TRANS_TRIES) { | |
7723 | qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES); | |
7724 | goto bail; | |
7725 | } | |
7726 | ||
7727 | /* If mask is not all 1s, we need to read, but different SerDes | |
7728 | * entities have different sizes | |
7729 | */ | |
7730 | sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1; | |
7731 | wr_data = data & mask & sz_mask; | |
7732 | if ((~mask & sz_mask) != 0) { | |
7733 | trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1); | |
7734 | qib_write_kreg(dd, KR_AHB_TRANS, trans); | |
7735 | ||
7736 | for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { | |
7737 | trans = qib_read_kreg64(dd, KR_AHB_TRANS); | |
7738 | if (trans & AHB_TRANS_RDY) | |
7739 | break; | |
7740 | } | |
7741 | if (tries >= AHB_TRANS_TRIES) { | |
7742 | qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n", | |
7743 | AHB_TRANS_TRIES); | |
7744 | goto bail; | |
7745 | } | |
7746 | /* Re-read in case host split reads and read data first */ | |
7747 | trans = qib_read_kreg64(dd, KR_AHB_TRANS); | |
7748 | rd_data = (uint32_t)(trans >> AHB_DATA_LSB); | |
7749 | wr_data |= (rd_data & ~mask & sz_mask); | |
7750 | } | |
7751 | ||
7752 | /* If mask is not zero, we need to write. */ | |
7753 | if (mask & sz_mask) { | |
7754 | trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1); | |
7755 | trans |= ((uint64_t)wr_data << AHB_DATA_LSB); | |
7756 | trans |= AHB_WR; | |
7757 | qib_write_kreg(dd, KR_AHB_TRANS, trans); | |
7758 | ||
7759 | for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { | |
7760 | trans = qib_read_kreg64(dd, KR_AHB_TRANS); | |
7761 | if (trans & AHB_TRANS_RDY) | |
7762 | break; | |
7763 | } | |
7764 | if (tries >= AHB_TRANS_TRIES) { | |
7765 | qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n", | |
7766 | AHB_TRANS_TRIES); | |
7767 | goto bail; | |
7768 | } | |
7769 | } | |
7770 | ret = wr_data; | |
7771 | bail: | |
7772 | qib_write_kreg(dd, KR_AHB_ACC, prev_acc); | |
7773 | return ret; | |
7774 | } | |
7775 | ||
7776 | static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data, | |
7777 | unsigned mask) | |
7778 | { | |
7779 | struct qib_devdata *dd = ppd->dd; | |
7780 | int chan; | |
f931551b RC |
7781 | |
7782 | for (chan = 0; chan < SERDES_CHANS; ++chan) { | |
7783 | ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, | |
7784 | data, mask); | |
2055d1f0 BVA |
7785 | ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, |
7786 | 0, 0); | |
f931551b RC |
7787 | } |
7788 | } | |
7789 | ||
a0a234d4 MM |
7790 | static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable) |
7791 | { | |
7792 | u64 data = qib_read_kreg_port(ppd, krp_serdesctrl); | |
31264484 MH |
7793 | u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN); |
7794 | ||
7795 | if (enable && !state) { | |
7fac3301 | 7796 | pr_info("IB%u:%u Turning LOS on\n", |
31264484 | 7797 | ppd->dd->unit, ppd->port); |
a0a234d4 | 7798 | data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN); |
31264484 | 7799 | } else if (!enable && state) { |
7fac3301 | 7800 | pr_info("IB%u:%u Turning LOS off\n", |
31264484 | 7801 | ppd->dd->unit, ppd->port); |
a0a234d4 | 7802 | data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN); |
31264484 | 7803 | } |
a0a234d4 MM |
7804 | qib_write_kreg_port(ppd, krp_serdesctrl, data); |
7805 | } | |
7806 | ||
f931551b RC |
7807 | static int serdes_7322_init(struct qib_pportdata *ppd) |
7808 | { | |
a0a234d4 | 7809 | int ret = 0; |
da12c1f6 | 7810 | |
a0a234d4 MM |
7811 | if (ppd->dd->cspec->r1) |
7812 | ret = serdes_7322_init_old(ppd); | |
7813 | else | |
7814 | ret = serdes_7322_init_new(ppd); | |
7815 | return ret; | |
7816 | } | |
7817 | ||
7818 | static int serdes_7322_init_old(struct qib_pportdata *ppd) | |
7819 | { | |
f931551b RC |
7820 | u32 le_val; |
7821 | ||
7822 | /* | |
7823 | * Initialize the Tx DDS tables. Also done every QSFP event, | |
7824 | * for adapters with QSFP | |
7825 | */ | |
7826 | init_txdds_table(ppd, 0); | |
7827 | ||
a77fcf89 RC |
7828 | /* ensure no tx overrides from earlier driver loads */ |
7829 | qib_write_kreg_port(ppd, krp_tx_deemph_override, | |
7830 | SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
7831 | reset_tx_deemphasis_override)); | |
7832 | ||
f931551b RC |
7833 | /* Patch some SerDes defaults to "Better for IB" */ |
7834 | /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */ | |
7835 | ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9)); | |
7836 | ||
7837 | /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */ | |
7838 | ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11)); | |
7839 | /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */ | |
7840 | ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6)); | |
7841 | ||
7842 | /* May be overridden in qsfp_7322_event */ | |
7843 | le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; | |
7844 | ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7)); | |
7845 | ||
7846 | /* enable LE1 adaptation for all but QME, which is disabled */ | |
7847 | le_val = IS_QME(ppd->dd) ? 0 : 1; | |
7848 | ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5)); | |
7849 | ||
7850 | /* Clear cmode-override, may be set from older driver */ | |
7851 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); | |
7852 | ||
7853 | /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */ | |
7854 | ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8)); | |
7855 | ||
7856 | /* setup LoS params; these are subsystem, so chan == 5 */ | |
7857 | /* LoS filter threshold_count on, ch 0-3, set to 8 */ | |
7858 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); | |
7859 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); | |
7860 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); | |
7861 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); | |
7862 | ||
7863 | /* LoS filter threshold_count off, ch 0-3, set to 4 */ | |
7864 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); | |
7865 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); | |
7866 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); | |
7867 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); | |
7868 | ||
7869 | /* LoS filter select enabled */ | |
7870 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); | |
7871 | ||
7872 | /* LoS target data: SDR=4, DDR=2, QDR=1 */ | |
7873 | ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */ | |
7874 | ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ | |
7875 | ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ | |
7876 | ||
a0a234d4 | 7877 | serdes_7322_los_enable(ppd, 1); |
f931551b RC |
7878 | |
7879 | /* rxbistena; set 0 to avoid effects of it switch later */ | |
7880 | ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15); | |
7881 | ||
7882 | /* Configure 4 DFE taps, and only they adapt */ | |
7883 | ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0)); | |
7884 | ||
7885 | /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */ | |
7886 | le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; | |
7887 | ibsd_wr_allchans(ppd, 21, le_val, 0xfffe); | |
7888 | ||
7889 | /* | |
7890 | * Set receive adaptation mode. SDR and DDR adaptation are | |
7891 | * always on, and QDR is initially enabled; later disabled. | |
7892 | */ | |
7893 | qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL); | |
7894 | qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL); | |
7895 | qib_write_kreg_port(ppd, krp_static_adapt_dis(2), | |
7896 | ppd->dd->cspec->r1 ? | |
7897 | QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN); | |
7898 | ppd->cpspec->qdr_dfe_on = 1; | |
7899 | ||
a77fcf89 | 7900 | /* FLoop LOS gate: PPM filter enabled */ |
f931551b RC |
7901 | ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10); |
7902 | ||
7903 | /* rx offset center enabled */ | |
7904 | ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4); | |
7905 | ||
7906 | if (!ppd->dd->cspec->r1) { | |
7907 | ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12); | |
7908 | ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8); | |
7909 | } | |
7910 | ||
7911 | /* Set the frequency loop bandwidth to 15 */ | |
7912 | ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5)); | |
7913 | ||
7914 | return 0; | |
7915 | } | |
7916 | ||
a0a234d4 MM |
7917 | static int serdes_7322_init_new(struct qib_pportdata *ppd) |
7918 | { | |
8482d5d1 | 7919 | unsigned long tend; |
a0a234d4 MM |
7920 | u32 le_val, rxcaldone; |
7921 | int chan, chan_done = (1 << SERDES_CHANS) - 1; | |
7922 | ||
a0a234d4 MM |
7923 | /* Clear cmode-override, may be set from older driver */ |
7924 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); | |
7925 | ||
7926 | /* ensure no tx overrides from earlier driver loads */ | |
7927 | qib_write_kreg_port(ppd, krp_tx_deemph_override, | |
7928 | SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
7929 | reset_tx_deemphasis_override)); | |
7930 | ||
7931 | /* START OF LSI SUGGESTED SERDES BRINGUP */ | |
7932 | /* Reset - Calibration Setup */ | |
7933 | /* Stop DFE adaptaion */ | |
7934 | ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1)); | |
7935 | /* Disable LE1 */ | |
7936 | ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5)); | |
7937 | /* Disable autoadapt for LE1 */ | |
7938 | ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15)); | |
7939 | /* Disable LE2 */ | |
7940 | ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6)); | |
7941 | /* Disable VGA */ | |
7942 | ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); | |
7943 | /* Disable AFE Offset Cancel */ | |
7944 | ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12)); | |
7945 | /* Disable Timing Loop */ | |
7946 | ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3)); | |
7947 | /* Disable Frequency Loop */ | |
7948 | ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4)); | |
7949 | /* Disable Baseline Wander Correction */ | |
7950 | ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13)); | |
7951 | /* Disable RX Calibration */ | |
7952 | ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); | |
7953 | /* Disable RX Offset Calibration */ | |
7954 | ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4)); | |
7955 | /* Select BB CDR */ | |
7956 | ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15)); | |
7957 | /* CDR Step Size */ | |
7958 | ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8)); | |
7959 | /* Enable phase Calibration */ | |
7960 | ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5)); | |
7961 | /* DFE Bandwidth [2:14-12] */ | |
7962 | ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12)); | |
7963 | /* DFE Config (4 taps only) */ | |
7964 | ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0)); | |
7965 | /* Gain Loop Bandwidth */ | |
7966 | if (!ppd->dd->cspec->r1) { | |
7967 | ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12)); | |
7968 | ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8)); | |
7969 | } else { | |
7970 | ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11)); | |
7971 | } | |
7972 | /* Baseline Wander Correction Gain [13:4-0] (leave as default) */ | |
7973 | /* Baseline Wander Correction Gain [3:7-5] (leave as default) */ | |
7974 | /* Data Rate Select [5:7-6] (leave as default) */ | |
25985edc | 7975 | /* RX Parallel Word Width [3:10-8] (leave as default) */ |
a0a234d4 MM |
7976 | |
7977 | /* RX REST */ | |
7978 | /* Single- or Multi-channel reset */ | |
7979 | /* RX Analog reset */ | |
7980 | /* RX Digital reset */ | |
7981 | ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13)); | |
7982 | msleep(20); | |
7983 | /* RX Analog reset */ | |
7984 | ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14)); | |
7985 | msleep(20); | |
7986 | /* RX Digital reset */ | |
7987 | ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13)); | |
7988 | msleep(20); | |
7989 | ||
7990 | /* setup LoS params; these are subsystem, so chan == 5 */ | |
7991 | /* LoS filter threshold_count on, ch 0-3, set to 8 */ | |
7992 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); | |
7993 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); | |
7994 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); | |
7995 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); | |
7996 | ||
7997 | /* LoS filter threshold_count off, ch 0-3, set to 4 */ | |
7998 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); | |
7999 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); | |
8000 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); | |
8001 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); | |
8002 | ||
8003 | /* LoS filter select enabled */ | |
8004 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); | |
8005 | ||
8006 | /* LoS target data: SDR=4, DDR=2, QDR=1 */ | |
8007 | ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */ | |
8008 | ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ | |
8009 | ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ | |
8010 | ||
8011 | /* Turn on LOS on initial SERDES init */ | |
8012 | serdes_7322_los_enable(ppd, 1); | |
8013 | /* FLoop LOS gate: PPM filter enabled */ | |
8014 | ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10); | |
8015 | ||
8016 | /* RX LATCH CALIBRATION */ | |
8017 | /* Enable Eyefinder Phase Calibration latch */ | |
8018 | ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0)); | |
8019 | /* Enable RX Offset Calibration latch */ | |
8020 | ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4)); | |
8021 | msleep(20); | |
8022 | /* Start Calibration */ | |
8023 | ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10)); | |
8482d5d1 MM |
8024 | tend = jiffies + msecs_to_jiffies(500); |
8025 | while (chan_done && !time_is_before_jiffies(tend)) { | |
a0a234d4 MM |
8026 | msleep(20); |
8027 | for (chan = 0; chan < SERDES_CHANS; ++chan) { | |
8028 | rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), | |
8029 | (chan + (chan >> 1)), | |
8030 | 25, 0, 0); | |
8031 | if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 && | |
8032 | (~chan_done & (1 << chan)) == 0) | |
8033 | chan_done &= ~(1 << chan); | |
8034 | } | |
8035 | } | |
8036 | if (chan_done) { | |
7fac3301 | 8037 | pr_info("Serdes %d calibration not done after .5 sec: 0x%x\n", |
a0a234d4 MM |
8038 | IBSD(ppd->hw_pidx), chan_done); |
8039 | } else { | |
8040 | for (chan = 0; chan < SERDES_CHANS; ++chan) { | |
8041 | rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), | |
8042 | (chan + (chan >> 1)), | |
8043 | 25, 0, 0); | |
8044 | if ((~rxcaldone & (u32)BMASK(10, 10)) == 0) | |
7fac3301 MM |
8045 | pr_info("Serdes %d chan %d calibration failed\n", |
8046 | IBSD(ppd->hw_pidx), chan); | |
a0a234d4 MM |
8047 | } |
8048 | } | |
8049 | ||
8050 | /* Turn off Calibration */ | |
8051 | ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); | |
8052 | msleep(20); | |
8053 | ||
8054 | /* BRING RX UP */ | |
8055 | /* Set LE2 value (May be overridden in qsfp_7322_event) */ | |
8056 | le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; | |
8057 | ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7)); | |
8058 | /* Set LE2 Loop bandwidth */ | |
8059 | ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5)); | |
8060 | /* Enable LE2 */ | |
8061 | ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6)); | |
8062 | msleep(20); | |
8063 | /* Enable H0 only */ | |
8064 | ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1)); | |
8065 | /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */ | |
8066 | le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; | |
8067 | ibsd_wr_allchans(ppd, 21, le_val, 0xfffe); | |
8068 | /* Enable VGA */ | |
8069 | ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); | |
8070 | msleep(20); | |
8071 | /* Set Frequency Loop Bandwidth */ | |
f665acb3 | 8072 | ibsd_wr_allchans(ppd, 2, (15 << 5), BMASK(8, 5)); |
a0a234d4 MM |
8073 | /* Enable Frequency Loop */ |
8074 | ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4)); | |
8075 | /* Set Timing Loop Bandwidth */ | |
8076 | ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9)); | |
8077 | /* Enable Timing Loop */ | |
8078 | ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3)); | |
8079 | msleep(50); | |
8080 | /* Enable DFE | |
8081 | * Set receive adaptation mode. SDR and DDR adaptation are | |
8082 | * always on, and QDR is initially enabled; later disabled. | |
8083 | */ | |
8084 | qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL); | |
8085 | qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL); | |
8086 | qib_write_kreg_port(ppd, krp_static_adapt_dis(2), | |
8087 | ppd->dd->cspec->r1 ? | |
8088 | QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN); | |
8089 | ppd->cpspec->qdr_dfe_on = 1; | |
8090 | /* Disable LE1 */ | |
8091 | ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5)); | |
8092 | /* Disable auto adapt for LE1 */ | |
8093 | ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15)); | |
8094 | msleep(20); | |
8095 | /* Enable AFE Offset Cancel */ | |
8096 | ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12)); | |
8097 | /* Enable Baseline Wander Correction */ | |
8098 | ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13)); | |
8099 | /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */ | |
8100 | ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11)); | |
8101 | /* VGA output common mode */ | |
8102 | ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2)); | |
8103 | ||
dde05cbd MH |
8104 | /* |
8105 | * Initialize the Tx DDS tables. Also done every QSFP event, | |
8106 | * for adapters with QSFP | |
8107 | */ | |
8108 | init_txdds_table(ppd, 0); | |
8109 | ||
a0a234d4 MM |
8110 | return 0; |
8111 | } | |
8112 | ||
f931551b RC |
8113 | /* start adjust QMH serdes parameters */ |
8114 | ||
8115 | static void set_man_code(struct qib_pportdata *ppd, int chan, int code) | |
8116 | { | |
8117 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), | |
8118 | 9, code << 9, 0x3f << 9); | |
8119 | } | |
8120 | ||
8121 | static void set_man_mode_h1(struct qib_pportdata *ppd, int chan, | |
8122 | int enable, u32 tapenable) | |
8123 | { | |
8124 | if (enable) | |
8125 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), | |
8126 | 1, 3 << 10, 0x1f << 10); | |
8127 | else | |
8128 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), | |
8129 | 1, 0, 0x1f << 10); | |
8130 | } | |
8131 | ||
8132 | /* Set clock to 1, 0, 1, 0 */ | |
8133 | static void clock_man(struct qib_pportdata *ppd, int chan) | |
8134 | { | |
8135 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), | |
8136 | 4, 0x4000, 0x4000); | |
8137 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), | |
8138 | 4, 0, 0x4000); | |
8139 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), | |
8140 | 4, 0x4000, 0x4000); | |
8141 | ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), | |
8142 | 4, 0, 0x4000); | |
8143 | } | |
8144 | ||
8145 | /* | |
8146 | * write the current Tx serdes pre,post,main,amp settings into the serdes. | |
8147 | * The caller must pass the settings appropriate for the current speed, | |
8148 | * or not care if they are correct for the current speed. | |
8149 | */ | |
8150 | static void write_tx_serdes_param(struct qib_pportdata *ppd, | |
8151 | struct txdds_ent *txdds) | |
8152 | { | |
8153 | u64 deemph; | |
8154 | ||
8155 | deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override); | |
8156 | /* field names for amp, main, post, pre, respectively */ | |
8157 | deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) | | |
8158 | SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) | | |
8159 | SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) | | |
8160 | SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena)); | |
a77fcf89 RC |
8161 | |
8162 | deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
8163 | tx_override_deemphasis_select); | |
8164 | deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
8165 | txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
8166 | txampcntl_d2a); | |
8167 | deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
8168 | txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
8169 | txc0_ena); | |
8170 | deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
8171 | txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
8172 | txcp1_ena); | |
8173 | deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
8174 | txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, | |
f931551b RC |
8175 | txcn1_ena); |
8176 | qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph); | |
8177 | } | |
8178 | ||
8179 | /* | |
a77fcf89 RC |
8180 | * Set the parameters for mez cards on link bounce, so they are |
8181 | * always exactly what was requested. Similar logic to init_txdds | |
8182 | * but does just the serdes. | |
f931551b RC |
8183 | */ |
8184 | static void adj_tx_serdes(struct qib_pportdata *ppd) | |
8185 | { | |
a77fcf89 RC |
8186 | const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds; |
8187 | struct txdds_ent *dds; | |
f931551b | 8188 | |
a77fcf89 RC |
8189 | find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1); |
8190 | dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ? | |
8191 | qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ? | |
8192 | ddr_dds : sdr_dds)); | |
8193 | write_tx_serdes_param(ppd, dds); | |
f931551b RC |
8194 | } |
8195 | ||
8196 | /* set QDR forced value for H1, if needed */ | |
8197 | static void force_h1(struct qib_pportdata *ppd) | |
8198 | { | |
8199 | int chan; | |
8200 | ||
8201 | ppd->cpspec->qdr_reforce = 0; | |
8202 | if (!ppd->dd->cspec->r1) | |
8203 | return; | |
8204 | ||
8205 | for (chan = 0; chan < SERDES_CHANS; chan++) { | |
8206 | set_man_mode_h1(ppd, chan, 1, 0); | |
8207 | set_man_code(ppd, chan, ppd->cpspec->h1_val); | |
8208 | clock_man(ppd, chan); | |
8209 | set_man_mode_h1(ppd, chan, 0, 0); | |
8210 | } | |
8211 | } | |
8212 | ||
f931551b RC |
8213 | #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN) |
8214 | #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en) | |
8215 | ||
8216 | #define R_OPCODE_LSB 3 | |
8217 | #define R_OP_NOP 0 | |
8218 | #define R_OP_SHIFT 2 | |
8219 | #define R_OP_UPDATE 3 | |
8220 | #define R_TDI_LSB 2 | |
8221 | #define R_TDO_LSB 1 | |
8222 | #define R_RDY 1 | |
8223 | ||
8224 | static int qib_r_grab(struct qib_devdata *dd) | |
8225 | { | |
da12c1f6 MM |
8226 | u64 val = SJA_EN; |
8227 | ||
f931551b RC |
8228 | qib_write_kreg(dd, kr_r_access, val); |
8229 | qib_read_kreg32(dd, kr_scratch); | |
8230 | return 0; | |
8231 | } | |
8232 | ||
8233 | /* qib_r_wait_for_rdy() not only waits for the ready bit, it | |
8234 | * returns the current state of R_TDO | |
8235 | */ | |
8236 | static int qib_r_wait_for_rdy(struct qib_devdata *dd) | |
8237 | { | |
8238 | u64 val; | |
8239 | int timeout; | |
da12c1f6 | 8240 | |
f931551b RC |
8241 | for (timeout = 0; timeout < 100 ; ++timeout) { |
8242 | val = qib_read_kreg32(dd, kr_r_access); | |
8243 | if (val & R_RDY) | |
8244 | return (val >> R_TDO_LSB) & 1; | |
8245 | } | |
8246 | return -1; | |
8247 | } | |
8248 | ||
8249 | static int qib_r_shift(struct qib_devdata *dd, int bisten, | |
8250 | int len, u8 *inp, u8 *outp) | |
8251 | { | |
8252 | u64 valbase, val; | |
8253 | int ret, pos; | |
8254 | ||
8255 | valbase = SJA_EN | (bisten << BISTEN_LSB) | | |
8256 | (R_OP_SHIFT << R_OPCODE_LSB); | |
8257 | ret = qib_r_wait_for_rdy(dd); | |
8258 | if (ret < 0) | |
8259 | goto bail; | |
8260 | for (pos = 0; pos < len; ++pos) { | |
8261 | val = valbase; | |
8262 | if (outp) { | |
8263 | outp[pos >> 3] &= ~(1 << (pos & 7)); | |
8264 | outp[pos >> 3] |= (ret << (pos & 7)); | |
8265 | } | |
8266 | if (inp) { | |
8267 | int tdi = inp[pos >> 3] >> (pos & 7); | |
da12c1f6 | 8268 | |
f931551b RC |
8269 | val |= ((tdi & 1) << R_TDI_LSB); |
8270 | } | |
8271 | qib_write_kreg(dd, kr_r_access, val); | |
8272 | qib_read_kreg32(dd, kr_scratch); | |
8273 | ret = qib_r_wait_for_rdy(dd); | |
8274 | if (ret < 0) | |
8275 | break; | |
8276 | } | |
8277 | /* Restore to NOP between operations. */ | |
8278 | val = SJA_EN | (bisten << BISTEN_LSB); | |
8279 | qib_write_kreg(dd, kr_r_access, val); | |
8280 | qib_read_kreg32(dd, kr_scratch); | |
8281 | ret = qib_r_wait_for_rdy(dd); | |
8282 | ||
8283 | if (ret >= 0) | |
8284 | ret = pos; | |
8285 | bail: | |
8286 | return ret; | |
8287 | } | |
8288 | ||
8289 | static int qib_r_update(struct qib_devdata *dd, int bisten) | |
8290 | { | |
8291 | u64 val; | |
8292 | int ret; | |
8293 | ||
8294 | val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB); | |
8295 | ret = qib_r_wait_for_rdy(dd); | |
8296 | if (ret >= 0) { | |
8297 | qib_write_kreg(dd, kr_r_access, val); | |
8298 | qib_read_kreg32(dd, kr_scratch); | |
8299 | } | |
8300 | return ret; | |
8301 | } | |
8302 | ||
8303 | #define BISTEN_PORT_SEL 15 | |
8304 | #define LEN_PORT_SEL 625 | |
8305 | #define BISTEN_AT 17 | |
8306 | #define LEN_AT 156 | |
8307 | #define BISTEN_ETM 16 | |
8308 | #define LEN_ETM 632 | |
8309 | ||
8310 | #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE) | |
8311 | ||
8312 | /* these are common for all IB port use cases. */ | |
8313 | static u8 reset_at[BIT2BYTE(LEN_AT)] = { | |
8314 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8315 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, | |
8316 | }; | |
8317 | static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = { | |
8318 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8319 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8320 | 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e, | |
8321 | 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7, | |
8322 | 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70, | |
8323 | 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00, | |
8324 | 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8325 | 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, | |
8326 | }; | |
8327 | static u8 at[BIT2BYTE(LEN_AT)] = { | |
8328 | 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, | |
8329 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, | |
8330 | }; | |
8331 | ||
8332 | /* used for IB1 or IB2, only one in use */ | |
8333 | static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = { | |
8334 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8335 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8336 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8337 | 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00, | |
8338 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8339 | 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03, | |
8340 | 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00, | |
8341 | 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00, | |
8342 | }; | |
8343 | ||
8344 | /* used when both IB1 and IB2 are in use */ | |
8345 | static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = { | |
8346 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8347 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, | |
8348 | 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8349 | 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05, | |
8350 | 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, | |
8351 | 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07, | |
8352 | 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00, | |
8353 | 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, | |
8354 | }; | |
8355 | ||
8356 | /* used when only IB1 is in use */ | |
8357 | static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = { | |
8358 | 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13, | |
8359 | 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c, | |
8360 | 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, | |
8361 | 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, | |
8362 | 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32, | |
8363 | 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, | |
8364 | 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, | |
8365 | 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8366 | }; | |
8367 | ||
8368 | /* used when only IB2 is in use */ | |
8369 | static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = { | |
8370 | 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39, | |
8371 | 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32, | |
8372 | 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, | |
8373 | 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, | |
8374 | 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32, | |
8375 | 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, | |
8376 | 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, | |
8377 | 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, | |
8378 | }; | |
8379 | ||
8380 | /* used when both IB1 and IB2 are in use */ | |
8381 | static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = { | |
8382 | 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13, | |
8383 | 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c, | |
8384 | 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, | |
8385 | 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, | |
8386 | 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32, | |
8387 | 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a, | |
8388 | 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, | |
8389 | 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, | |
8390 | }; | |
8391 | ||
8392 | /* | |
8393 | * Do setup to properly handle IB link recovery; if port is zero, we | |
8394 | * are initializing to cover both ports; otherwise we are initializing | |
8395 | * to cover a single port card, or the port has reached INIT and we may | |
8396 | * need to switch coverage types. | |
8397 | */ | |
8398 | static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both) | |
8399 | { | |
8400 | u8 *portsel, *etm; | |
8401 | struct qib_devdata *dd = ppd->dd; | |
8402 | ||
8403 | if (!ppd->dd->cspec->r1) | |
8404 | return; | |
8405 | if (!both) { | |
8406 | dd->cspec->recovery_ports_initted++; | |
8407 | ppd->cpspec->recovery_init = 1; | |
8408 | } | |
8409 | if (!both && dd->cspec->recovery_ports_initted == 1) { | |
8410 | portsel = ppd->port == 1 ? portsel_port1 : portsel_port2; | |
8411 | etm = atetm_1port; | |
8412 | } else { | |
8413 | portsel = portsel_2port; | |
8414 | etm = atetm_2port; | |
8415 | } | |
8416 | ||
8417 | if (qib_r_grab(dd) < 0 || | |
8418 | qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 || | |
8419 | qib_r_update(dd, BISTEN_ETM) < 0 || | |
8420 | qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 || | |
8421 | qib_r_update(dd, BISTEN_AT) < 0 || | |
8422 | qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL, | |
8423 | portsel, NULL) < 0 || | |
8424 | qib_r_update(dd, BISTEN_PORT_SEL) < 0 || | |
8425 | qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 || | |
8426 | qib_r_update(dd, BISTEN_AT) < 0 || | |
8427 | qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 || | |
8428 | qib_r_update(dd, BISTEN_ETM) < 0) | |
8429 | qib_dev_err(dd, "Failed IB link recovery setup\n"); | |
8430 | } | |
8431 | ||
8432 | static void check_7322_rxe_status(struct qib_pportdata *ppd) | |
8433 | { | |
8434 | struct qib_devdata *dd = ppd->dd; | |
8435 | u64 fmask; | |
8436 | ||
8437 | if (dd->cspec->recovery_ports_initted != 1) | |
8438 | return; /* rest doesn't apply to dualport */ | |
8439 | qib_write_kreg(dd, kr_control, dd->control | | |
8440 | SYM_MASK(Control, FreezeMode)); | |
8441 | (void)qib_read_kreg64(dd, kr_scratch); | |
8442 | udelay(3); /* ibcreset asserted 400ns, be sure that's over */ | |
8443 | fmask = qib_read_kreg64(dd, kr_act_fmask); | |
8444 | if (!fmask) { | |
8445 | /* | |
8446 | * require a powercycle before we'll work again, and make | |
8447 | * sure we get no more interrupts, and don't turn off | |
8448 | * freeze. | |
8449 | */ | |
8450 | ppd->dd->cspec->stay_in_freeze = 1; | |
8451 | qib_7322_set_intr_state(ppd->dd, 0); | |
8452 | qib_write_kreg(dd, kr_fmask, 0ULL); | |
8453 | qib_dev_err(dd, "HCA unusable until powercycled\n"); | |
8454 | return; /* eventually reset */ | |
8455 | } | |
8456 | ||
8457 | qib_write_kreg(ppd->dd, kr_hwerrclear, | |
8458 | SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1)); | |
8459 | ||
8460 | /* don't do the full clear_freeze(), not needed for this */ | |
8461 | qib_write_kreg(dd, kr_control, dd->control); | |
8462 | qib_read_kreg32(dd, kr_scratch); | |
8463 | /* take IBC out of reset */ | |
8464 | if (ppd->link_speed_supported) { | |
8465 | ppd->cpspec->ibcctrl_a &= | |
8466 | ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); | |
8467 | qib_write_kreg_port(ppd, krp_ibcctrl_a, | |
8468 | ppd->cpspec->ibcctrl_a); | |
8469 | qib_read_kreg32(dd, kr_scratch); | |
8470 | if (ppd->lflags & QIBL_IB_LINK_DISABLED) | |
8471 | qib_set_ib_7322_lstate(ppd, 0, | |
8472 | QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); | |
8473 | } | |
8474 | } |