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[linux-2.6-block.git] / drivers / infiniband / hw / qedr / main.c
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2e0cbc4d
RA		 1/* QLogic qedr NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <linux/module.h>
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_addr.h>
ac1b36e5 35#include <rdma/ib_user_verbs.h>
e6a38c54
KM		 36#include <rdma/iw_cm.h>
37#include <rdma/ib_mad.h>
2e0cbc4d
RA		 38#include <linux/netdevice.h>
39#include <linux/iommu.h>
461a6946 40#include <linux/pci.h>
2e0cbc4d 41#include <net/addrconf.h>
de0089e6 42#include <linux/idr.h>
b262a06e 43
ec72fce4
RA		 44#include <linux/qed/qed_chain.h>
45#include <linux/qed/qed_if.h>
2e0cbc4d 46#include "qedr.h"
ac1b36e5
RA		 47#include "verbs.h"
48#include <rdma/qedr-abi.h>
de0089e6 49#include "qedr_iw_cm.h"
2e0cbc4d
RA		 50
51MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
52MODULE_AUTHOR("QLogic Corporation");
53MODULE_LICENSE("Dual BSD/GPL");
2e0cbc4d 54
cecbcddf
RA		 55#define QEDR_WQ_MULTIPLIER_DFT (3)
56
0089985e
BVA		 57static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
58 enum ib_event_type type)
2e0cbc4d
RA		 59{
60 struct ib_event ibev;
61
62 ibev.device = &dev->ibdev;
63 ibev.element.port_num = port_num;
64 ibev.event = type;
65
66 ib_dispatch_event(&ibev);
67}
68
69static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
70 u8 port_num)
71{
72 return IB_LINK_LAYER_ETHERNET;
73}
74
9abb0d1b 75static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
ec72fce4
RA		 76{
77 struct qedr_dev *qedr = get_qedr_dev(ibdev);
78 u32 fw_ver = (u32)qedr->attr.fw_ver;
79
9abb0d1b 80 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d. %d. %d. %d",
ec72fce4
RA		 81 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
82 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
83}
84
993d1b52
RA		 85static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num)
86{
87 struct qedr_dev *qdev;
88
89 qdev = get_qedr_dev(dev);
90 dev_hold(qdev->ndev);
91
92 /* The HW vendor's device driver must guarantee
070f2d7e
KT		 93 * that this function returns NULL before the net device has finished
94 * NETDEV_UNREGISTER state.
993d1b52
RA		 95 */
96 return qdev->ndev;
97}
98
0089985e
BVA		 99static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
100 struct ib_port_immutable *immutable)
e6a38c54
KM		 101{
102 struct ib_port_attr attr;
103 int err;
104
105 err = qedr_query_port(ibdev, port_num, &attr);
106 if (err)
107 return err;
108
109 immutable->pkey_tbl_len = attr.pkey_tbl_len;
110 immutable->gid_tbl_len = attr.gid_tbl_len;
111 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
112 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
113 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
114
115 return 0;
116}
117
0089985e
BVA		 118static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
119 struct ib_port_immutable *immutable)
e6a38c54
KM		 120{
121 struct ib_port_attr attr;
122 int err;
123
124 err = qedr_query_port(ibdev, port_num, &attr);
125 if (err)
126 return err;
127
128 immutable->pkey_tbl_len = 1;
129 immutable->gid_tbl_len = 1;
130 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
131 immutable->max_mad_size = 0;
132
133 return 0;
134}
135
0089985e 136static int qedr_iw_register_device(struct qedr_dev *dev)
e6a38c54
KM		 137{
138 dev->ibdev.node_type = RDMA_NODE_RNIC;
139 dev->ibdev.query_gid = qedr_iw_query_gid;
140
141 dev->ibdev.get_port_immutable = qedr_iw_port_immutable;
142
143 dev->ibdev.iwcm = kzalloc(sizeof(*dev->ibdev.iwcm), GFP_KERNEL);
144 if (!dev->ibdev.iwcm)
145 return -ENOMEM;
e411e058
KM		 146
147 dev->ibdev.iwcm->connect = qedr_iw_connect;
148 dev->ibdev.iwcm->accept = qedr_iw_accept;
149 dev->ibdev.iwcm->reject = qedr_iw_reject;
150 dev->ibdev.iwcm->create_listen = qedr_iw_create_listen;
151 dev->ibdev.iwcm->destroy_listen = qedr_iw_destroy_listen;
de0089e6
KM		 152 dev->ibdev.iwcm->add_ref = qedr_iw_qp_add_ref;
153 dev->ibdev.iwcm->rem_ref = qedr_iw_qp_rem_ref;
154 dev->ibdev.iwcm->get_qp = qedr_iw_get_qp;
e6a38c54
KM		 155
156 memcpy(dev->ibdev.iwcm->ifname,
157 dev->ndev->name, sizeof(dev->ibdev.iwcm->ifname));
158
159 return 0;
160}
161
0089985e 162static void qedr_roce_register_device(struct qedr_dev *dev)
e6a38c54
KM		 163{
164 dev->ibdev.node_type = RDMA_NODE_IB_CA;
e6a38c54
KM		 165
166 dev->ibdev.get_port_immutable = qedr_roce_port_immutable;
167}
168
2e0cbc4d
RA		 169static int qedr_register_device(struct qedr_dev *dev)
170{
e6a38c54
KM		 171 int rc;
172
2e0cbc4d
RA		 173 strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
174
993d1b52 175 dev->ibdev.node_guid = dev->attr.node_guid;
2e0cbc4d
RA		 176 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
177 dev->ibdev.owner = THIS_MODULE;
ac1b36e5
RA		 178 dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
179
180 dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
181 QEDR_UVERBS(QUERY_DEVICE) |
a7efd777
RA		 182 QEDR_UVERBS(QUERY_PORT) |
183 QEDR_UVERBS(ALLOC_PD) |
184 QEDR_UVERBS(DEALLOC_PD) |
185 QEDR_UVERBS(CREATE_COMP_CHANNEL) |
186 QEDR_UVERBS(CREATE_CQ) |
187 QEDR_UVERBS(RESIZE_CQ) |
188 QEDR_UVERBS(DESTROY_CQ) |
cecbcddf
RA		 189 QEDR_UVERBS(REQ_NOTIFY_CQ) |
190 QEDR_UVERBS(CREATE_QP) |
191 QEDR_UVERBS(MODIFY_QP) |
192 QEDR_UVERBS(QUERY_QP) |
e0290cce
RA		 193 QEDR_UVERBS(DESTROY_QP) |
194 QEDR_UVERBS(REG_MR) |
afa0e13b
RA		 195 QEDR_UVERBS(DEREG_MR) |
196 QEDR_UVERBS(POLL_CQ) |
197 QEDR_UVERBS(POST_SEND) |
198 QEDR_UVERBS(POST_RECV);
ac1b36e5 199
e6a38c54
KM		 200 if (IS_IWARP(dev)) {
201 rc = qedr_iw_register_device(dev);
202 if (rc)
203 return rc;
204 } else {
205 qedr_roce_register_device(dev);
206 }
207
ac1b36e5
RA		 208 dev->ibdev.phys_port_cnt = 1;
209 dev->ibdev.num_comp_vectors = dev->num_cnq;
ac1b36e5
RA		 210
211 dev->ibdev.query_device = qedr_query_device;
212 dev->ibdev.query_port = qedr_query_port;
213 dev->ibdev.modify_port = qedr_modify_port;
214
ac1b36e5
RA		 215 dev->ibdev.alloc_ucontext = qedr_alloc_ucontext;
216 dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext;
217 dev->ibdev.mmap = qedr_mmap;
218
a7efd777
RA		 219 dev->ibdev.alloc_pd = qedr_alloc_pd;
220 dev->ibdev.dealloc_pd = qedr_dealloc_pd;
221
222 dev->ibdev.create_cq = qedr_create_cq;
223 dev->ibdev.destroy_cq = qedr_destroy_cq;
224 dev->ibdev.resize_cq = qedr_resize_cq;
225 dev->ibdev.req_notify_cq = qedr_arm_cq;
226
cecbcddf
RA		 227 dev->ibdev.create_qp = qedr_create_qp;
228 dev->ibdev.modify_qp = qedr_modify_qp;
229 dev->ibdev.query_qp = qedr_query_qp;
230 dev->ibdev.destroy_qp = qedr_destroy_qp;
231
a7efd777
RA		 232 dev->ibdev.query_pkey = qedr_query_pkey;
233
04886779
RA		 234 dev->ibdev.create_ah = qedr_create_ah;
235 dev->ibdev.destroy_ah = qedr_destroy_ah;
236
e0290cce
RA		 237 dev->ibdev.get_dma_mr = qedr_get_dma_mr;
238 dev->ibdev.dereg_mr = qedr_dereg_mr;
239 dev->ibdev.reg_user_mr = qedr_reg_user_mr;
240 dev->ibdev.alloc_mr = qedr_alloc_mr;
241 dev->ibdev.map_mr_sg = qedr_map_mr_sg;
242
afa0e13b
RA		 243 dev->ibdev.poll_cq = qedr_poll_cq;
244 dev->ibdev.post_send = qedr_post_send;
245 dev->ibdev.post_recv = qedr_post_recv;
246
993d1b52 247 dev->ibdev.process_mad = qedr_process_mad;
e6a38c54 248
993d1b52
RA		 249 dev->ibdev.get_netdev = qedr_get_netdev;
250
69117101 251 dev->ibdev.dev.parent = &dev->pdev->dev;
2e0cbc4d
RA		 252
253 dev->ibdev.get_link_layer = qedr_link_layer;
ec72fce4 254 dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
2e0cbc4d 255
0ede73bc 256 dev->ibdev.driver_id = RDMA_DRIVER_QEDR;
993d1b52 257 return ib_register_device(&dev->ibdev, NULL);
2e0cbc4d
RA		 258}
259
ec72fce4
RA		 260/* This function allocates fast-path status block memory */
261static int qedr_alloc_mem_sb(struct qedr_dev *dev,
262 struct qed_sb_info *sb_info, u16 sb_id)
263{
21dd79e8 264 struct status_block_e4 *sb_virt;
ec72fce4
RA		 265 dma_addr_t sb_phys;
266 int rc;
267
268 sb_virt = dma_alloc_coherent(&dev->pdev->dev,
269 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
270 if (!sb_virt)
271 return -ENOMEM;
272
273 rc = dev->ops->common->sb_init(dev->cdev, sb_info,
274 sb_virt, sb_phys, sb_id,
275 QED_SB_TYPE_CNQ);
276 if (rc) {
277 pr_err("Status block initialization failed\n");
278 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
279 sb_virt, sb_phys);
280 return rc;
281 }
282
283 return 0;
284}
285
286static void qedr_free_mem_sb(struct qedr_dev *dev,
287 struct qed_sb_info *sb_info, int sb_id)
288{
289 if (sb_info->sb_virt) {
290 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
291 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
292 (void *)sb_info->sb_virt, sb_info->sb_phys);
293 }
294}
295
296static void qedr_free_resources(struct qedr_dev *dev)
297{
298 int i;
299
e411e058
KM		 300 if (IS_IWARP(dev))
301 destroy_workqueue(dev->iwarp_wq);
302
ec72fce4
RA		 303 for (i = 0; i < dev->num_cnq; i++) {
304 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
305 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
306 }
307
308 kfree(dev->cnq_array);
309 kfree(dev->sb_array);
310 kfree(dev->sgid_tbl);
311}
312
313static int qedr_alloc_resources(struct qedr_dev *dev)
314{
315 struct qedr_cnq *cnq;
316 __le16 *cons_pi;
317 u16 n_entries;
318 int i, rc;
319
6396bb22
KC		 320 dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid),
321 GFP_KERNEL);
ec72fce4
RA		 322 if (!dev->sgid_tbl)
323 return -ENOMEM;
324
325 spin_lock_init(&dev->sgid_lock);
326
de0089e6
KM		 327 if (IS_IWARP(dev)) {
328 spin_lock_init(&dev->idr_lock);
329 idr_init(&dev->qpidr);
e411e058 330 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
de0089e6
KM		 331 }
332
ec72fce4
RA		 333 /* Allocate Status blocks for CNQ */
334 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
335 GFP_KERNEL);
336 if (!dev->sb_array) {
337 rc = -ENOMEM;
338 goto err1;
339 }
340
341 dev->cnq_array = kcalloc(dev->num_cnq,
342 sizeof(*dev->cnq_array), GFP_KERNEL);
343 if (!dev->cnq_array) {
344 rc = -ENOMEM;
345 goto err2;
346 }
347
348 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
349
350 /* Allocate CNQ PBLs */
351 n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
352 for (i = 0; i < dev->num_cnq; i++) {
353 cnq = &dev->cnq_array[i];
354
355 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
356 dev->sb_start + i);
357 if (rc)
358 goto err3;
359
360 rc = dev->ops->common->chain_alloc(dev->cdev,
361 QED_CHAIN_USE_TO_CONSUME,
362 QED_CHAIN_MODE_PBL,
363 QED_CHAIN_CNT_TYPE_U16,
364 n_entries,
365 sizeof(struct regpair *),
1a4a6975 366 &cnq->pbl, NULL);
ec72fce4
RA		 367 if (rc)
368 goto err4;
369
370 cnq->dev = dev;
371 cnq->sb = &dev->sb_array[i];
372 cons_pi = dev->sb_array[i].sb_virt->pi_array;
373 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
374 cnq->index = i;
375 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
376
377 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
378 i, qed_chain_get_cons_idx(&cnq->pbl));
379 }
380
381 return 0;
382err4:
383 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
384err3:
385 for (--i; i >= 0; i--) {
386 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
387 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
388 }
389 kfree(dev->cnq_array);
390err2:
391 kfree(dev->sb_array);
392err1:
393 kfree(dev->sgid_tbl);
394 return rc;
395}
396
2e0cbc4d
RA		 397/* QEDR sysfs interface */
398static ssize_t show_rev(struct device *device, struct device_attribute *attr,
399 char *buf)
400{
401 struct qedr_dev *dev = dev_get_drvdata(device);
402
403 return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
404}
405
406static ssize_t show_hca_type(struct device *device,
407 struct device_attribute *attr, char *buf)
408{
409 return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
410}
411
412static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
413static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
414
415static struct device_attribute *qedr_attributes[] = {
416 &dev_attr_hw_rev,
417 &dev_attr_hca_type
418};
419
420static void qedr_remove_sysfiles(struct qedr_dev *dev)
421{
422 int i;
423
424 for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
425 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
426}
427
428static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
429{
20c3ff61
FK		 430 int rc = pci_enable_atomic_ops_to_root(pdev,
431 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
f92faaba 432
20c3ff61
FK		 433 if (rc) {
434 dev->atomic_cap = IB_ATOMIC_NONE;
435 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
436 } else {
437 dev->atomic_cap = IB_ATOMIC_GLOB;
438 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
2e0cbc4d 439 }
2e0cbc4d
RA		 440}
441
ec72fce4
RA		 442static const struct qed_rdma_ops *qed_ops;
443
444#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
445
446static irqreturn_t qedr_irq_handler(int irq, void *handle)
447{
448 u16 hw_comp_cons, sw_comp_cons;
449 struct qedr_cnq *cnq = handle;
a7efd777
RA		 450 struct regpair *cq_handle;
451 struct qedr_cq *cq;
ec72fce4
RA		 452
453 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
454
455 qed_sb_update_sb_idx(cnq->sb);
456
457 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
458 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
459
460 /* Align protocol-index and chain reads */
461 rmb();
462
463 while (sw_comp_cons != hw_comp_cons) {
a7efd777
RA		 464 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
465 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
466 cq_handle->lo);
467
468 if (cq == NULL) {
469 DP_ERR(cnq->dev,
470 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
471 cq_handle->hi, cq_handle->lo, sw_comp_cons,
472 hw_comp_cons);
473
474 break;
475 }
476
477 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
478 DP_ERR(cnq->dev,
479 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
480 cq_handle->hi, cq_handle->lo, cq);
481 break;
482 }
483
484 cq->arm_flags = 0;
485
4dd72636 486 if (!cq->destroyed && cq->ibcq.comp_handler)
a7efd777
RA		 487 (*cq->ibcq.comp_handler)
488 (&cq->ibcq, cq->ibcq.cq_context);
489
4dd72636
AR		 490 /* The CQ's CNQ notification counter is checked before
491 * destroying the CQ in a busy-wait loop that waits for all of
492 * the CQ's CNQ interrupts to be processed. It is increased
493 * here, only after the completion handler, to ensure that the
494 * the handler is not running when the CQ is destroyed.
495 */
496 cq->cnq_notif++;
497
ec72fce4 498 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
a7efd777 499
ec72fce4
RA		 500 cnq->n_comp++;
501 }
502
503 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
504 sw_comp_cons);
505
506 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
507
508 return IRQ_HANDLED;
509}
510
511static void qedr_sync_free_irqs(struct qedr_dev *dev)
512{
513 u32 vector;
514 int i;
515
516 for (i = 0; i < dev->int_info.used_cnt; i++) {
517 if (dev->int_info.msix_cnt) {
518 vector = dev->int_info.msix[i * dev->num_hwfns].vector;
519 synchronize_irq(vector);
520 free_irq(vector, &dev->cnq_array[i]);
521 }
522 }
523
524 dev->int_info.used_cnt = 0;
525}
526
527static int qedr_req_msix_irqs(struct qedr_dev *dev)
528{
529 int i, rc = 0;
530
531 if (dev->num_cnq > dev->int_info.msix_cnt) {
532 DP_ERR(dev,
533 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
534 dev->num_cnq, dev->int_info.msix_cnt);
535 return -EINVAL;
536 }
537
538 for (i = 0; i < dev->num_cnq; i++) {
539 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
540 qedr_irq_handler, 0, dev->cnq_array[i].name,
541 &dev->cnq_array[i]);
542 if (rc) {
543 DP_ERR(dev, "Request cnq %d irq failed\n", i);
544 qedr_sync_free_irqs(dev);
545 } else {
546 DP_DEBUG(dev, QEDR_MSG_INIT,
547 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
548 dev->cnq_array[i].name, i,
549 &dev->cnq_array[i]);
550 dev->int_info.used_cnt++;
551 }
552 }
553
554 return rc;
555}
556
557static int qedr_setup_irqs(struct qedr_dev *dev)
558{
559 int rc;
560
561 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
562
563 /* Learn Interrupt configuration */
564 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
565 if (rc < 0)
566 return rc;
567
568 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
569 if (rc) {
570 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
571 return rc;
572 }
573
574 if (dev->int_info.msix_cnt) {
575 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
576 dev->int_info.msix_cnt);
577 rc = qedr_req_msix_irqs(dev);
578 if (rc)
579 return rc;
580 }
581
582 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
583
584 return 0;
585}
586
587static int qedr_set_device_attr(struct qedr_dev *dev)
588{
589 struct qed_rdma_device *qed_attr;
590 struct qedr_device_attr *attr;
591 u32 page_size;
592
593 /* Part 1 - query core capabilities */
594 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
595
596 /* Part 2 - check capabilities */
597 page_size = ~dev->attr.page_size_caps + 1;
598 if (page_size > PAGE_SIZE) {
599 DP_ERR(dev,
600 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
601 PAGE_SIZE, page_size);
602 return -ENODEV;
603 }
604
605 /* Part 3 - copy and update capabilities */
606 attr = &dev->attr;
607 attr->vendor_id = qed_attr->vendor_id;
608 attr->vendor_part_id = qed_attr->vendor_part_id;
609 attr->hw_ver = qed_attr->hw_ver;
610 attr->fw_ver = qed_attr->fw_ver;
611 attr->node_guid = qed_attr->node_guid;
612 attr->sys_image_guid = qed_attr->sys_image_guid;
613 attr->max_cnq = qed_attr->max_cnq;
614 attr->max_sge = qed_attr->max_sge;
615 attr->max_inline = qed_attr->max_inline;
616 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
617 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
618 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
619 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
620 attr->max_dev_resp_rd_atomic_resc =
621 qed_attr->max_dev_resp_rd_atomic_resc;
622 attr->max_cq = qed_attr->max_cq;
623 attr->max_qp = qed_attr->max_qp;
624 attr->max_mr = qed_attr->max_mr;
625 attr->max_mr_size = qed_attr->max_mr_size;
626 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
627 attr->max_mw = qed_attr->max_mw;
628 attr->max_fmr = qed_attr->max_fmr;
629 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
630 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
631 attr->max_pd = qed_attr->max_pd;
632 attr->max_ah = qed_attr->max_ah;
633 attr->max_pkey = qed_attr->max_pkey;
634 attr->max_srq = qed_attr->max_srq;
635 attr->max_srq_wr = qed_attr->max_srq_wr;
636 attr->dev_caps = qed_attr->dev_caps;
637 attr->page_size_caps = qed_attr->page_size_caps;
638 attr->dev_ack_delay = qed_attr->dev_ack_delay;
639 attr->reserved_lkey = qed_attr->reserved_lkey;
640 attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
641 attr->max_stats_queues = qed_attr->max_stats_queues;
642
643 return 0;
644}
645
0089985e 646static void qedr_unaffiliated_event(void *context, u8 event_code)
993d1b52
RA		 647{
648 pr_err("unaffiliated event not implemented yet\n");
649}
650
0089985e 651static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
993d1b52
RA		 652{
653#define EVENT_TYPE_NOT_DEFINED 0
654#define EVENT_TYPE_CQ 1
655#define EVENT_TYPE_QP 2
656 struct qedr_dev *dev = (struct qedr_dev *)context;
be086e7c
MY		 657 struct regpair *async_handle = (struct regpair *)fw_handle;
658 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
993d1b52
RA		 659 u8 event_type = EVENT_TYPE_NOT_DEFINED;
660 struct ib_event event;
661 struct ib_cq *ibcq;
662 struct ib_qp *ibqp;
663 struct qedr_cq *cq;
664 struct qedr_qp *qp;
665
666 switch (e_code) {
667 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
668 event.event = IB_EVENT_CQ_ERR;
669 event_type = EVENT_TYPE_CQ;
670 break;
671 case ROCE_ASYNC_EVENT_SQ_DRAINED:
672 event.event = IB_EVENT_SQ_DRAINED;
673 event_type = EVENT_TYPE_QP;
674 break;
675 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
676 event.event = IB_EVENT_QP_FATAL;
677 event_type = EVENT_TYPE_QP;
678 break;
679 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
680 event.event = IB_EVENT_QP_REQ_ERR;
681 event_type = EVENT_TYPE_QP;
682 break;
683 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
684 event.event = IB_EVENT_QP_ACCESS_ERR;
685 event_type = EVENT_TYPE_QP;
686 break;
687 default:
688 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
689 roce_handle64);
690 }
691
692 switch (event_type) {
693 case EVENT_TYPE_CQ:
694 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
695 if (cq) {
696 ibcq = &cq->ibcq;
697 if (ibcq->event_handler) {
698 event.device = ibcq->device;
699 event.element.cq = ibcq;
700 ibcq->event_handler(&event, ibcq->cq_context);
701 }
702 } else {
703 WARN(1,
704 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
705 roce_handle64);
706 }
a343e3f8 707 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq);
993d1b52
RA		 708 break;
709 case EVENT_TYPE_QP:
710 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
711 if (qp) {
712 ibqp = &qp->ibqp;
713 if (ibqp->event_handler) {
714 event.device = ibqp->device;
715 event.element.qp = ibqp;
716 ibqp->event_handler(&event, ibqp->qp_context);
717 }
718 } else {
719 WARN(1,
720 "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
721 roce_handle64);
722 }
a343e3f8 723 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp);
993d1b52
RA		 724 break;
725 default:
726 break;
727 }
728}
729
ec72fce4
RA		 730static int qedr_init_hw(struct qedr_dev *dev)
731{
732 struct qed_rdma_add_user_out_params out_params;
733 struct qed_rdma_start_in_params *in_params;
734 struct qed_rdma_cnq_params *cur_pbl;
735 struct qed_rdma_events events;
736 dma_addr_t p_phys_table;
737 u32 page_cnt;
738 int rc = 0;
739 int i;
740
741 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
742 if (!in_params) {
743 rc = -ENOMEM;
744 goto out;
745 }
746
747 in_params->desired_cnq = dev->num_cnq;
748 for (i = 0; i < dev->num_cnq; i++) {
749 cur_pbl = &in_params->cnq_pbl_list[i];
750
751 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
752 cur_pbl->num_pbl_pages = page_cnt;
753
754 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
755 cur_pbl->pbl_ptr = (u64)p_phys_table;
756 }
757
993d1b52
RA		 758 events.affiliated_event = qedr_affiliated_event;
759 events.unaffiliated_event = qedr_unaffiliated_event;
ec72fce4
RA		 760 events.context = dev;
761
762 in_params->events = &events;
763 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
764 in_params->max_mtu = dev->ndev->mtu;
e411e058 765 dev->iwarp_max_mtu = dev->ndev->mtu;
ec72fce4
RA		 766 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
767
768 rc = dev->ops->rdma_init(dev->cdev, in_params);
769 if (rc)
770 goto out;
771
772 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
773 if (rc)
774 goto out;
775
99847b5c 776 dev->db_addr = (void __iomem *)(uintptr_t)out_params.dpi_addr;
ec72fce4
RA		 777 dev->db_phys_addr = out_params.dpi_phys_addr;
778 dev->db_size = out_params.dpi_size;
779 dev->dpi = out_params.dpi;
780
781 rc = qedr_set_device_attr(dev);
782out:
783 kfree(in_params);
784 if (rc)
785 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
786
787 return rc;
788}
789
0089985e 790static void qedr_stop_hw(struct qedr_dev *dev)
ec72fce4
RA		 791{
792 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
793 dev->ops->rdma_stop(dev->rdma_ctx);
794}
795
2e0cbc4d
RA		 796static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
797 struct net_device *ndev)
798{
ec72fce4 799 struct qed_dev_rdma_info dev_info;
2e0cbc4d
RA		 800 struct qedr_dev *dev;
801 int rc = 0, i;
802
803 dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
804 if (!dev) {
805 pr_err("Unable to allocate ib device\n");
806 return NULL;
807 }
808
809 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
810
811 dev->pdev = pdev;
812 dev->ndev = ndev;
813 dev->cdev = cdev;
814
ec72fce4
RA		 815 qed_ops = qed_get_rdma_ops();
816 if (!qed_ops) {
817 DP_ERR(dev, "Failed to get qed roce operations\n");
818 goto init_err;
819 }
820
821 dev->ops = qed_ops;
822 rc = qed_ops->fill_dev_info(cdev, &dev_info);
823 if (rc)
824 goto init_err;
825
ad84dad2 826 dev->user_dpm_enabled = dev_info.user_dpm_enabled;
e538e0ac 827 dev->rdma_type = dev_info.rdma_type;
ec72fce4
RA		 828 dev->num_hwfns = dev_info.common.num_hwfns;
829 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
830
831 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
832 if (!dev->num_cnq) {
b15606f4
KM		 833 DP_ERR(dev, "Failed. At least one CNQ is required.\n");
834 rc = -ENOMEM;
ec72fce4
RA		 835 goto init_err;
836 }
837
cecbcddf
RA		 838 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
839
2e0cbc4d
RA		 840 qedr_pci_set_atomic(dev, pdev);
841
ec72fce4
RA		 842 rc = qedr_alloc_resources(dev);
843 if (rc)
844 goto init_err;
845
846 rc = qedr_init_hw(dev);
847 if (rc)
848 goto alloc_err;
849
850 rc = qedr_setup_irqs(dev);
851 if (rc)
852 goto irq_err;
853
2e0cbc4d
RA		 854 rc = qedr_register_device(dev);
855 if (rc) {
856 DP_ERR(dev, "Unable to allocate register device\n");
ec72fce4 857 goto reg_err;
2e0cbc4d
RA		 858 }
859
860 for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
861 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
993d1b52 862 goto sysfs_err;
2e0cbc4d 863
f449c7a2
RA		 864 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
865 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
866
2e0cbc4d
RA		 867 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
868 return dev;
869
993d1b52
RA		 870sysfs_err:
871 ib_unregister_device(&dev->ibdev);
ec72fce4
RA		 872reg_err:
873 qedr_sync_free_irqs(dev);
874irq_err:
875 qedr_stop_hw(dev);
876alloc_err:
877 qedr_free_resources(dev);
2e0cbc4d
RA		 878init_err:
879 ib_dealloc_device(&dev->ibdev);
880 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
881
882 return NULL;
883}
884
885static void qedr_remove(struct qedr_dev *dev)
886{
887 /* First unregister with stack to stop all the active traffic
888 * of the registered clients.
889 */
890 qedr_remove_sysfiles(dev);
993d1b52 891 ib_unregister_device(&dev->ibdev);
2e0cbc4d 892
ec72fce4
RA		 893 qedr_stop_hw(dev);
894 qedr_sync_free_irqs(dev);
895 qedr_free_resources(dev);
2e0cbc4d
RA		 896 ib_dealloc_device(&dev->ibdev);
897}
898
f449c7a2 899static void qedr_close(struct qedr_dev *dev)
2e0cbc4d 900{
f449c7a2
RA		 901 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
902 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
2e0cbc4d
RA		 903}
904
905static void qedr_shutdown(struct qedr_dev *dev)
906{
907 qedr_close(dev);
908 qedr_remove(dev);
909}
910
f449c7a2
RA		 911static void qedr_open(struct qedr_dev *dev)
912{
913 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
914 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
915}
916
1d1424c8
RA		 917static void qedr_mac_address_change(struct qedr_dev *dev)
918{
919 union ib_gid *sgid = &dev->sgid_tbl[0];
920 u8 guid[8], mac_addr[6];
921 int rc;
922
923 /* Update SGID */
924 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
925 guid[0] = mac_addr[0] ^ 2;
926 guid[1] = mac_addr[1];
927 guid[2] = mac_addr[2];
928 guid[3] = 0xff;
929 guid[4] = 0xfe;
930 guid[5] = mac_addr[3];
931 guid[6] = mac_addr[4];
932 guid[7] = mac_addr[5];
933 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
934 memcpy(&sgid->raw[8], guid, sizeof(guid));
935
936 /* Update LL2 */
0518c12f
MK		 937 rc = dev->ops->ll2_set_mac_filter(dev->cdev,
938 dev->gsi_ll2_mac_address,
939 dev->ndev->dev_addr);
1d1424c8
RA		 940
941 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
942
f449c7a2 943 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
1d1424c8
RA		 944
945 if (rc)
946 DP_ERR(dev, "Error updating mac filter\n");
947}
948
2e0cbc4d
RA		 949/* event handling via NIC driver ensures that all the NIC specific
950 * initialization done before RoCE driver notifies
951 * event to stack.
952 */
bbfcd1e8 953static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
2e0cbc4d
RA		 954{
955 switch (event) {
956 case QEDE_UP:
f449c7a2 957 qedr_open(dev);
2e0cbc4d
RA		 958 break;
959 case QEDE_DOWN:
960 qedr_close(dev);
961 break;
962 case QEDE_CLOSE:
963 qedr_shutdown(dev);
964 break;
965 case QEDE_CHANGE_ADDR:
1d1424c8 966 qedr_mac_address_change(dev);
2e0cbc4d
RA		 967 break;
968 default:
969 pr_err("Event not supported\n");
970 }
971}
972
973static struct qedr_driver qedr_drv = {
974 .name = "qedr_driver",
975 .add = qedr_add,
976 .remove = qedr_remove,
977 .notify = qedr_notify,
978};
979
980static int __init qedr_init_module(void)
981{
bbfcd1e8 982 return qede_rdma_register_driver(&qedr_drv);
2e0cbc4d
RA		 983}
984
985static void __exit qedr_exit_module(void)
986{
bbfcd1e8 987 qede_rdma_unregister_driver(&qedr_drv);
2e0cbc4d
RA		 988}
989
990module_init(qedr_init_module);
991module_exit(qedr_exit_module);
Linux 6.x block layer and io_uring tree(s)