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RDMA/ocrdma: Avoid posting DPP requests for RDMA READ
[linux-2.6-block.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
CommitLineData
fe2caefc
PP		 1/*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/log2.h>
31#include <linux/dma-mapping.h>
32
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_user_verbs.h>
fe2caefc
PP		 35
36#include "ocrdma.h"
37#include "ocrdma_hw.h"
38#include "ocrdma_verbs.h"
39#include "ocrdma_ah.h"
40
41enum mbx_status {
42 OCRDMA_MBX_STATUS_FAILED = 1,
43 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
44 OCRDMA_MBX_STATUS_OOR = 100,
45 OCRDMA_MBX_STATUS_INVALID_PD = 101,
46 OCRDMA_MBX_STATUS_PD_INUSE = 102,
47 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
48 OCRDMA_MBX_STATUS_INVALID_QP = 104,
49 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
50 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
51 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
52 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
53 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
54 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
55 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
56 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
57 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
58 OCRDMA_MBX_STATUS_MW_BOUND = 114,
59 OCRDMA_MBX_STATUS_INVALID_VA = 115,
60 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
61 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
62 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
63 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
64 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
65 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
66 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
67 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
68 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
69 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
70 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
71 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
72 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
73 OCRDMA_MBX_STATUS_QP_BOUND = 130,
74 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
75 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
76 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
77 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
78 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
79 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
80};
81
82enum additional_status {
83 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
84};
85
86enum cqe_status {
87 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
88 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
89 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
90 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
91 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
92};
93
94static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
95{
f99b1649 96 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
fe2caefc
PP		 97}
98
99static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
100{
101 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
102}
103
104static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
105{
106 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
f99b1649 107 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
fe2caefc
PP		 108
109 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
110 return NULL;
111 return cqe;
112}
113
114static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
115{
116 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
117}
118
119static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
120{
f99b1649 121 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 122}
123
124static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
125{
126 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
fe2caefc
PP		 127}
128
129static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
130{
f99b1649 131 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 132}
133
134enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
135{
136 switch (qps) {
137 case OCRDMA_QPS_RST:
138 return IB_QPS_RESET;
139 case OCRDMA_QPS_INIT:
140 return IB_QPS_INIT;
141 case OCRDMA_QPS_RTR:
142 return IB_QPS_RTR;
143 case OCRDMA_QPS_RTS:
144 return IB_QPS_RTS;
145 case OCRDMA_QPS_SQD:
146 case OCRDMA_QPS_SQ_DRAINING:
147 return IB_QPS_SQD;
148 case OCRDMA_QPS_SQE:
149 return IB_QPS_SQE;
150 case OCRDMA_QPS_ERR:
151 return IB_QPS_ERR;
2b50176d 152 }
fe2caefc
PP		 153 return IB_QPS_ERR;
154}
155
abe3afac 156static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
fe2caefc
PP		 157{
158 switch (qps) {
159 case IB_QPS_RESET:
160 return OCRDMA_QPS_RST;
161 case IB_QPS_INIT:
162 return OCRDMA_QPS_INIT;
163 case IB_QPS_RTR:
164 return OCRDMA_QPS_RTR;
165 case IB_QPS_RTS:
166 return OCRDMA_QPS_RTS;
167 case IB_QPS_SQD:
168 return OCRDMA_QPS_SQD;
169 case IB_QPS_SQE:
170 return OCRDMA_QPS_SQE;
171 case IB_QPS_ERR:
172 return OCRDMA_QPS_ERR;
2b50176d 173 }
fe2caefc
PP		 174 return OCRDMA_QPS_ERR;
175}
176
177static int ocrdma_get_mbx_errno(u32 status)
178{
f99b1649 179 int err_num;
fe2caefc
PP		 180 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
181 OCRDMA_MBX_RSP_STATUS_SHIFT;
182 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
183 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
184
185 switch (mbox_status) {
186 case OCRDMA_MBX_STATUS_OOR:
187 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
188 err_num = -EAGAIN;
189 break;
190
191 case OCRDMA_MBX_STATUS_INVALID_PD:
192 case OCRDMA_MBX_STATUS_INVALID_CQ:
193 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
194 case OCRDMA_MBX_STATUS_INVALID_QP:
195 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
196 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
197 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
198 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
199 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
200 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
201 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
202 case OCRDMA_MBX_STATUS_INVALID_LKEY:
203 case OCRDMA_MBX_STATUS_INVALID_VA:
204 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
205 case OCRDMA_MBX_STATUS_INVALID_FBO:
206 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
207 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
208 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
209 case OCRDMA_MBX_STATUS_SRQ_ERROR:
210 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
211 err_num = -EINVAL;
212 break;
213
214 case OCRDMA_MBX_STATUS_PD_INUSE:
215 case OCRDMA_MBX_STATUS_QP_BOUND:
216 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
217 case OCRDMA_MBX_STATUS_MW_BOUND:
218 err_num = -EBUSY;
219 break;
220
221 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
222 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
223 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
224 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
225 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
226 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
227 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
228 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
229 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
230 err_num = -ENOBUFS;
231 break;
232
233 case OCRDMA_MBX_STATUS_FAILED:
234 switch (add_status) {
235 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
236 err_num = -EAGAIN;
237 break;
238 }
239 default:
240 err_num = -EFAULT;
241 }
242 return err_num;
243}
244
a51f06e1
SX		 245char *port_speed_string(struct ocrdma_dev *dev)
246{
247 char *str = "";
248 u16 speeds_supported;
249
250 speeds_supported = dev->phy.fixed_speeds_supported |
251 dev->phy.auto_speeds_supported;
252 if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
253 str = "40Gbps ";
254 else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
255 str = "10Gbps ";
256 else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
257 str = "1Gbps ";
258
259 return str;
260}
261
fe2caefc
PP		 262static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
263{
264 int err_num = -EINVAL;
265
266 switch (cqe_status) {
267 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
268 err_num = -EPERM;
269 break;
270 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
271 err_num = -EINVAL;
272 break;
273 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
274 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
f11220ee 275 err_num = -EINVAL;
fe2caefc
PP		 276 break;
277 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
43a6b402 278 default:
f11220ee 279 err_num = -EINVAL;
fe2caefc
PP		 280 break;
281 }
282 return err_num;
283}
284
285void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
286 bool solicited, u16 cqe_popped)
287{
288 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
289
290 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
291 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
292
293 if (armed)
294 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
295 if (solicited)
296 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
297 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
298 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
299}
300
301static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
302{
303 u32 val = 0;
304
305 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
306 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
307 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
308}
309
310static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
311 bool arm, bool clear_int, u16 num_eqe)
312{
313 u32 val = 0;
314
315 val |= eq_id & OCRDMA_EQ_ID_MASK;
316 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
317 if (arm)
318 val |= (1 << OCRDMA_REARM_SHIFT);
319 if (clear_int)
320 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
321 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
322 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
323 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
324}
325
326static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
327 u8 opcode, u8 subsys, u32 cmd_len)
328{
329 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
330 cmd_hdr->timeout = 20; /* seconds */
331 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
332}
333
334static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
335{
336 struct ocrdma_mqe *mqe;
337
338 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
339 if (!mqe)
340 return NULL;
341 mqe->hdr.spcl_sge_cnt_emb |=
342 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
343 OCRDMA_MQE_HDR_EMB_MASK;
344 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
345
346 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
347 mqe->hdr.pyld_len);
348 return mqe;
349}
350
a51f06e1
SX		 351static void *ocrdma_alloc_mqe(void)
352{
353 return kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
354}
355
fe2caefc
PP		 356static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
357{
358 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
359}
360
361static int ocrdma_alloc_q(struct ocrdma_dev *dev,
362 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
363{
364 memset(q, 0, sizeof(*q));
365 q->len = len;
366 q->entry_size = entry_size;
367 q->size = len * entry_size;
368 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
369 &q->dma, GFP_KERNEL);
370 if (!q->va)
371 return -ENOMEM;
372 memset(q->va, 0, q->size);
373 return 0;
374}
375
376static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
377 dma_addr_t host_pa, int hw_page_size)
378{
379 int i;
380
381 for (i = 0; i < cnt; i++) {
382 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
383 q_pa[i].hi = (u32) upper_32_bits(host_pa);
384 host_pa += hw_page_size;
385 }
386}
387
fad51b7d
DS		 388static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
389 struct ocrdma_queue_info *q, int queue_type)
fe2caefc
PP		 390{
391 u8 opcode = 0;
392 int status;
393 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
394
395 switch (queue_type) {
396 case QTYPE_MCCQ:
397 opcode = OCRDMA_CMD_DELETE_MQ;
398 break;
399 case QTYPE_CQ:
400 opcode = OCRDMA_CMD_DELETE_CQ;
401 break;
402 case QTYPE_EQ:
403 opcode = OCRDMA_CMD_DELETE_EQ;
404 break;
405 default:
406 BUG();
407 }
408 memset(cmd, 0, sizeof(*cmd));
409 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
410 cmd->id = q->id;
411
412 status = be_roce_mcc_cmd(dev->nic_info.netdev,
413 cmd, sizeof(*cmd), NULL, NULL);
414 if (!status)
415 q->created = false;
416 return status;
417}
418
419static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
420{
421 int status;
422 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
423 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
424
425 memset(cmd, 0, sizeof(*cmd));
426 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
427 sizeof(*cmd));
fe2caefc 428
c88bd03f 429 cmd->req.rsvd_version = 2;
fe2caefc
PP		 430 cmd->num_pages = 4;
431 cmd->valid = OCRDMA_CREATE_EQ_VALID;
432 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
433
434 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
435 PAGE_SIZE_4K);
436 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
437 NULL);
438 if (!status) {
439 eq->q.id = rsp->vector_eqid & 0xffff;
c88bd03f 440 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
fe2caefc
PP		 441 eq->q.created = true;
442 }
443 return status;
444}
445
446static int ocrdma_create_eq(struct ocrdma_dev *dev,
447 struct ocrdma_eq *eq, u16 q_len)
448{
449 int status;
450
451 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
452 sizeof(struct ocrdma_eqe));
453 if (status)
454 return status;
455
456 status = ocrdma_mbx_create_eq(dev, eq);
457 if (status)
458 goto mbx_err;
459 eq->dev = dev;
460 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
461
462 return 0;
463mbx_err:
464 ocrdma_free_q(dev, &eq->q);
465 return status;
466}
467
ea617626 468int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
fe2caefc
PP		 469{
470 int irq;
471
472 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
473 irq = dev->nic_info.pdev->irq;
474 else
475 irq = dev->nic_info.msix.vector_list[eq->vector];
476 return irq;
477}
478
479static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
480{
481 if (eq->q.created) {
482 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
fe2caefc
PP		 483 ocrdma_free_q(dev, &eq->q);
484 }
485}
486
487static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
488{
489 int irq;
490
491 /* disarm EQ so that interrupts are not generated
492 * during freeing and EQ delete is in progress.
493 */
494 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
495
496 irq = ocrdma_get_irq(dev, eq);
497 free_irq(irq, eq);
498 _ocrdma_destroy_eq(dev, eq);
499}
500
c88bd03f 501static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
fe2caefc
PP		 502{
503 int i;
504
fe2caefc 505 for (i = 0; i < dev->eq_cnt; i++)
c88bd03f 506 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
fe2caefc
PP		 507}
508
abe3afac
RD		 509static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
510 struct ocrdma_queue_info *cq,
511 struct ocrdma_queue_info *eq)
fe2caefc
PP		 512{
513 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
514 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
515 int status;
516
517 memset(cmd, 0, sizeof(*cmd));
518 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
519 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
520
1afc0454
NG		 521 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
522 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
523 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
524 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
525
fe2caefc 526 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1afc0454
NG		 527 cmd->eqn = eq->id;
528 cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe);
fe2caefc 529
1afc0454 530 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
fe2caefc
PP		 531 cq->dma, PAGE_SIZE_4K);
532 status = be_roce_mcc_cmd(dev->nic_info.netdev,
533 cmd, sizeof(*cmd), NULL, NULL);
534 if (!status) {
1afc0454 535 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
fe2caefc
PP		 536 cq->created = true;
537 }
538 return status;
539}
540
541static u32 ocrdma_encoded_q_len(int q_len)
542{
543 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
544
545 if (len_encoded == 16)
546 len_encoded = 0;
547 return len_encoded;
548}
549
550static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
551 struct ocrdma_queue_info *mq,
552 struct ocrdma_queue_info *cq)
553{
554 int num_pages, status;
555 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
556 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
557 struct ocrdma_pa *pa;
558
559 memset(cmd, 0, sizeof(*cmd));
560 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
561
b1d58b99
NG		 562 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
563 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
564 cmd->req.rsvd_version = 1;
565 cmd->cqid_pages = num_pages;
566 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
567 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
84b105db
NG		 568
569 cmd->async_event_bitmap = Bit(OCRDMA_ASYNC_GRP5_EVE_CODE);
570 cmd->async_event_bitmap |= Bit(OCRDMA_ASYNC_RDMA_EVE_CODE);
571
b1d58b99
NG		 572 cmd->async_cqid_ringsize = cq->id;
573 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
574 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
575 cmd->valid = OCRDMA_CREATE_MQ_VALID;
576 pa = &cmd->pa[0];
577
fe2caefc
PP		 578 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
579 status = be_roce_mcc_cmd(dev->nic_info.netdev,
580 cmd, sizeof(*cmd), NULL, NULL);
581 if (!status) {
582 mq->id = rsp->id;
583 mq->created = true;
584 }
585 return status;
586}
587
588static int ocrdma_create_mq(struct ocrdma_dev *dev)
589{
590 int status;
591
592 /* Alloc completion queue for Mailbox queue */
593 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
594 sizeof(struct ocrdma_mcqe));
595 if (status)
596 goto alloc_err;
597
ea617626 598 dev->eq_tbl[0].cq_cnt++;
c88bd03f 599 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
fe2caefc
PP		 600 if (status)
601 goto mbx_cq_free;
602
603 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
604 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
605 mutex_init(&dev->mqe_ctx.lock);
606
607 /* Alloc Mailbox queue */
608 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
609 sizeof(struct ocrdma_mqe));
610 if (status)
611 goto mbx_cq_destroy;
612 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
613 if (status)
614 goto mbx_q_free;
615 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
616 return 0;
617
618mbx_q_free:
619 ocrdma_free_q(dev, &dev->mq.sq);
620mbx_cq_destroy:
621 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
622mbx_cq_free:
623 ocrdma_free_q(dev, &dev->mq.cq);
624alloc_err:
625 return status;
626}
627
628static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
629{
630 struct ocrdma_queue_info *mbxq, *cq;
631
632 /* mqe_ctx lock synchronizes with any other pending cmds. */
633 mutex_lock(&dev->mqe_ctx.lock);
634 mbxq = &dev->mq.sq;
635 if (mbxq->created) {
636 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
637 ocrdma_free_q(dev, mbxq);
638 }
639 mutex_unlock(&dev->mqe_ctx.lock);
640
641 cq = &dev->mq.cq;
642 if (cq->created) {
643 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
644 ocrdma_free_q(dev, cq);
645 }
646}
647
648static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
649 struct ocrdma_qp *qp)
650{
651 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
652 enum ib_qp_state old_ib_qps;
653
654 if (qp == NULL)
655 BUG();
057729cb 656 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
fe2caefc
PP		 657}
658
659static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
660 struct ocrdma_ae_mcqe *cqe)
661{
662 struct ocrdma_qp *qp = NULL;
663 struct ocrdma_cq *cq = NULL;
1228056b 664 struct ib_event ib_evt = { 0 };
fe2caefc
PP		 665 int cq_event = 0;
666 int qp_event = 1;
667 int srq_event = 0;
668 int dev_event = 0;
669 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
670 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
671
672 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
673 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
674 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
675 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
676
e9db2953
RD		 677 ib_evt.device = &dev->ibdev;
678
fe2caefc
PP		 679 switch (type) {
680 case OCRDMA_CQ_ERROR:
681 ib_evt.element.cq = &cq->ibcq;
682 ib_evt.event = IB_EVENT_CQ_ERR;
683 cq_event = 1;
684 qp_event = 0;
685 break;
686 case OCRDMA_CQ_OVERRUN_ERROR:
687 ib_evt.element.cq = &cq->ibcq;
688 ib_evt.event = IB_EVENT_CQ_ERR;
1228056b
SX		 689 cq_event = 1;
690 qp_event = 0;
fe2caefc
PP		 691 break;
692 case OCRDMA_CQ_QPCAT_ERROR:
693 ib_evt.element.qp = &qp->ibqp;
694 ib_evt.event = IB_EVENT_QP_FATAL;
695 ocrdma_process_qpcat_error(dev, qp);
696 break;
697 case OCRDMA_QP_ACCESS_ERROR:
698 ib_evt.element.qp = &qp->ibqp;
699 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
700 break;
701 case OCRDMA_QP_COMM_EST_EVENT:
702 ib_evt.element.qp = &qp->ibqp;
703 ib_evt.event = IB_EVENT_COMM_EST;
704 break;
705 case OCRDMA_SQ_DRAINED_EVENT:
706 ib_evt.element.qp = &qp->ibqp;
707 ib_evt.event = IB_EVENT_SQ_DRAINED;
708 break;
709 case OCRDMA_DEVICE_FATAL_EVENT:
710 ib_evt.element.port_num = 1;
711 ib_evt.event = IB_EVENT_DEVICE_FATAL;
712 qp_event = 0;
713 dev_event = 1;
714 break;
715 case OCRDMA_SRQCAT_ERROR:
716 ib_evt.element.srq = &qp->srq->ibsrq;
717 ib_evt.event = IB_EVENT_SRQ_ERR;
718 srq_event = 1;
719 qp_event = 0;
720 break;
721 case OCRDMA_SRQ_LIMIT_EVENT:
722 ib_evt.element.srq = &qp->srq->ibsrq;
804eaf29 723 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
fe2caefc
PP		 724 srq_event = 1;
725 qp_event = 0;
726 break;
727 case OCRDMA_QP_LAST_WQE_EVENT:
728 ib_evt.element.qp = &qp->ibqp;
729 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
730 break;
731 default:
732 cq_event = 0;
733 qp_event = 0;
734 srq_event = 0;
735 dev_event = 0;
ef99c4c2 736 pr_err("%s() unknown type=0x%x\n", __func__, type);
fe2caefc
PP		 737 break;
738 }
739
740 if (qp_event) {
741 if (qp->ibqp.event_handler)
742 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
743 } else if (cq_event) {
744 if (cq->ibcq.event_handler)
745 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
746 } else if (srq_event) {
747 if (qp->srq->ibsrq.event_handler)
748 qp->srq->ibsrq.event_handler(&ib_evt,
749 qp->srq->ibsrq.
750 srq_context);
f99b1649 751 } else if (dev_event) {
1228056b 752 pr_err("%s: Fatal event received\n", dev->ibdev.name);
fe2caefc 753 ib_dispatch_event(&ib_evt);
f99b1649 754 }
fe2caefc
PP		 755
756}
757
84b105db
NG		 758static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
759 struct ocrdma_ae_mcqe *cqe)
760{
761 struct ocrdma_ae_pvid_mcqe *evt;
762 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
763 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
764
765 switch (type) {
766 case OCRDMA_ASYNC_EVENT_PVID_STATE:
767 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
768 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
769 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
770 dev->pvid = ((evt->tag_enabled &
771 OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
772 OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
773 break;
774 default:
775 /* Not interested evts. */
776 break;
777 }
778}
779
fe2caefc
PP		 780static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
781{
782 /* async CQE processing */
783 struct ocrdma_ae_mcqe *cqe = ae_cqe;
784 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
785 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
786
84b105db 787 if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
fe2caefc 788 ocrdma_dispatch_ibevent(dev, cqe);
84b105db
NG		 789 else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
790 ocrdma_process_grp5_aync(dev, cqe);
fe2caefc 791 else
ef99c4c2
NG		 792 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
793 dev->id, evt_code);
fe2caefc
PP		 794}
795
796static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
797{
798 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
799 dev->mqe_ctx.cqe_status = (cqe->status &
800 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
801 dev->mqe_ctx.ext_status =
802 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
803 >> OCRDMA_MCQE_ESTATUS_SHIFT;
804 dev->mqe_ctx.cmd_done = true;
805 wake_up(&dev->mqe_ctx.cmd_wait);
806 } else
ef99c4c2
NG		 807 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
808 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
fe2caefc
PP		 809}
810
811static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
812{
813 u16 cqe_popped = 0;
814 struct ocrdma_mcqe *cqe;
815
816 while (1) {
817 cqe = ocrdma_get_mcqe(dev);
818 if (cqe == NULL)
819 break;
820 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
821 cqe_popped += 1;
822 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
823 ocrdma_process_acqe(dev, cqe);
824 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
825 ocrdma_process_mcqe(dev, cqe);
fe2caefc
PP		 826 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
827 ocrdma_mcq_inc_tail(dev);
828 }
829 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
830 return 0;
831}
832
833static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
834 struct ocrdma_cq *cq)
835{
836 unsigned long flags;
837 struct ocrdma_qp *qp;
838 bool buddy_cq_found = false;
839 /* Go through list of QPs in error state which are using this CQ
840 * and invoke its callback handler to trigger CQE processing for
841 * error/flushed CQE. It is rare to find more than few entries in
842 * this list as most consumers stops after getting error CQE.
843 * List is traversed only once when a matching buddy cq found for a QP.
844 */
845 spin_lock_irqsave(&dev->flush_q_lock, flags);
846 list_for_each_entry(qp, &cq->sq_head, sq_entry) {
847 if (qp->srq)
848 continue;
849 /* if wq and rq share the same cq, than comp_handler
850 * is already invoked.
851 */
852 if (qp->sq_cq == qp->rq_cq)
853 continue;
854 /* if completion came on sq, rq's cq is buddy cq.
855 * if completion came on rq, sq's cq is buddy cq.
856 */
857 if (qp->sq_cq == cq)
858 cq = qp->rq_cq;
859 else
860 cq = qp->sq_cq;
861 buddy_cq_found = true;
862 break;
863 }
864 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
865 if (buddy_cq_found == false)
866 return;
867 if (cq->ibcq.comp_handler) {
868 spin_lock_irqsave(&cq->comp_handler_lock, flags);
869 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
870 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
871 }
872}
873
874static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
875{
876 unsigned long flags;
877 struct ocrdma_cq *cq;
878
879 if (cq_idx >= OCRDMA_MAX_CQ)
880 BUG();
881
882 cq = dev->cq_tbl[cq_idx];
ea617626 883 if (cq == NULL)
fe2caefc 884 return;
fe2caefc
PP		 885
886 if (cq->ibcq.comp_handler) {
887 spin_lock_irqsave(&cq->comp_handler_lock, flags);
888 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
889 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
890 }
891 ocrdma_qp_buddy_cq_handler(dev, cq);
892}
893
894static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
895{
896 /* process the MQ-CQE. */
897 if (cq_id == dev->mq.cq.id)
898 ocrdma_mq_cq_handler(dev, cq_id);
899 else
900 ocrdma_qp_cq_handler(dev, cq_id);
901}
902
903static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
904{
905 struct ocrdma_eq *eq = handle;
906 struct ocrdma_dev *dev = eq->dev;
907 struct ocrdma_eqe eqe;
908 struct ocrdma_eqe *ptr;
fe2caefc 909 u16 cq_id;
ea617626
DS		 910 int budget = eq->cq_cnt;
911
912 do {
fe2caefc
PP		 913 ptr = ocrdma_get_eqe(eq);
914 eqe = *ptr;
915 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
916 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
917 break;
ea617626 918
fe2caefc 919 ptr->id_valid = 0;
ea617626
DS		 920 /* ring eq doorbell as soon as its consumed. */
921 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
fe2caefc
PP		 922 /* check whether its CQE or not. */
923 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
924 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
925 ocrdma_cq_handler(dev, cq_id);
926 }
927 ocrdma_eq_inc_tail(eq);
ea617626
DS		 928
929 /* There can be a stale EQE after the last bound CQ is
930 * destroyed. EQE valid and budget == 0 implies this.
931 */
932 if (budget)
933 budget--;
934
935 } while (budget);
936
937 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
fe2caefc
PP		 938 return IRQ_HANDLED;
939}
940
941static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
942{
943 struct ocrdma_mqe *mqe;
944
945 dev->mqe_ctx.tag = dev->mq.sq.head;
946 dev->mqe_ctx.cmd_done = false;
947 mqe = ocrdma_get_mqe(dev);
948 cmd->hdr.tag_lo = dev->mq.sq.head;
949 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
950 /* make sure descriptor is written before ringing doorbell */
951 wmb();
952 ocrdma_mq_inc_head(dev);
953 ocrdma_ring_mq_db(dev);
954}
955
956static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
957{
958 long status;
959 /* 30 sec timeout */
960 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
961 (dev->mqe_ctx.cmd_done != false),
962 msecs_to_jiffies(30000));
963 if (status)
964 return 0;
965 else
966 return -1;
967}
968
969/* issue a mailbox command on the MQ */
970static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
971{
972 int status = 0;
973 u16 cqe_status, ext_status;
bbc5ec52
SX		 974 struct ocrdma_mqe *rsp_mqe;
975 struct ocrdma_mbx_rsp *rsp = NULL;
fe2caefc
PP		 976
977 mutex_lock(&dev->mqe_ctx.lock);
978 ocrdma_post_mqe(dev, mqe);
979 status = ocrdma_wait_mqe_cmpl(dev);
980 if (status)
981 goto mbx_err;
982 cqe_status = dev->mqe_ctx.cqe_status;
983 ext_status = dev->mqe_ctx.ext_status;
bbc5ec52
SX		 984 rsp_mqe = ocrdma_get_mqe_rsp(dev);
985 ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
986 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
987 OCRDMA_MQE_HDR_EMB_SHIFT)
988 rsp = &mqe->u.rsp;
989
fe2caefc 990 if (cqe_status || ext_status) {
bbc5ec52
SX		 991 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
992 __func__, cqe_status, ext_status);
993 if (rsp) {
994 /* This is for embedded cmds. */
995 pr_err("opcode=0x%x, subsystem=0x%x\n",
996 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
997 OCRDMA_MBX_RSP_OPCODE_SHIFT,
998 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
999 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1000 }
fe2caefc
PP		 1001 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1002 goto mbx_err;
1003 }
bbc5ec52
SX		 1004 /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1005 if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
fe2caefc
PP		 1006 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1007mbx_err:
1008 mutex_unlock(&dev->mqe_ctx.lock);
1009 return status;
1010}
1011
bbc5ec52
SX		 1012static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1013 void *payload_va)
1014{
1015 int status = 0;
1016 struct ocrdma_mbx_rsp *rsp = payload_va;
1017
1018 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1019 OCRDMA_MQE_HDR_EMB_SHIFT)
1020 BUG();
1021
1022 status = ocrdma_mbx_cmd(dev, mqe);
1023 if (!status)
1024 /* For non embedded, only CQE failures are handled in
1025 * ocrdma_mbx_cmd. We need to check for RSP errors.
1026 */
1027 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1028 status = ocrdma_get_mbx_errno(rsp->status);
1029
1030 if (status)
1031 pr_err("opcode=0x%x, subsystem=0x%x\n",
1032 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1033 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1034 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1035 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1036 return status;
1037}
1038
fe2caefc
PP		 1039static void ocrdma_get_attr(struct ocrdma_dev *dev,
1040 struct ocrdma_dev_attr *attr,
1041 struct ocrdma_mbx_query_config *rsp)
1042{
fe2caefc
PP		 1043 attr->max_pd =
1044 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1045 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1046 attr->max_qp =
1047 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1048 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
fad51b7d
DS		 1049 attr->max_srq =
1050 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1051 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
fe2caefc
PP		 1052 attr->max_send_sge = ((rsp->max_write_send_sge &
1053 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1054 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1055 attr->max_recv_sge = (rsp->max_write_send_sge &
1056 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1057 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
634c5796
MV		 1058 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1059 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1060 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
45e86b33
NG		 1061 attr->max_rdma_sge = (rsp->max_write_send_sge &
1062 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1063 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
fe2caefc
PP		 1064 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1065 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1066 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1067 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1068 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1069 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1070 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1071 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1072 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1073 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1074 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1075 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1076 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1077 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1078 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
ac578aef 1079 attr->max_mw = rsp->max_mw;
fe2caefc
PP		 1080 attr->max_mr = rsp->max_mr;
1081 attr->max_mr_size = ~0ull;
1082 attr->max_fmr = 0;
1083 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1084 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1085 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1086 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
c43e9ab8
NG		 1087 attr->max_cq = (rsp->max_cq_cqes_per_cq &
1088 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1089 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
fe2caefc
PP		 1090 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1091 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1092 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1093 OCRDMA_WQE_STRIDE;
1094 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1095 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1096 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1097 OCRDMA_WQE_STRIDE;
1098 attr->max_inline_data =
1099 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1100 sizeof(struct ocrdma_sge));
21c3391a 1101 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
fe2caefc
PP		 1102 attr->ird = 1;
1103 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1104 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
07bb5424
MV		 1105 }
1106 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1107 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1108 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1109 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
fe2caefc
PP		 1110}
1111
1112static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1113 struct ocrdma_fw_conf_rsp *conf)
1114{
1115 u32 fn_mode;
1116
1117 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1118 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1119 return -EINVAL;
1120 dev->base_eqid = conf->base_eqid;
1121 dev->max_eq = conf->max_eq;
fe2caefc
PP		 1122 return 0;
1123}
1124
1125/* can be issued only during init time. */
1126static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1127{
1128 int status = -ENOMEM;
1129 struct ocrdma_mqe *cmd;
1130 struct ocrdma_fw_ver_rsp *rsp;
1131
1132 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1133 if (!cmd)
1134 return -ENOMEM;
1135 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1136 OCRDMA_CMD_GET_FW_VER,
1137 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1138
1139 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1140 if (status)
1141 goto mbx_err;
1142 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1143 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1144 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1145 sizeof(rsp->running_ver));
1146 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1147mbx_err:
1148 kfree(cmd);
1149 return status;
1150}
1151
1152/* can be issued only during init time. */
1153static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1154{
1155 int status = -ENOMEM;
1156 struct ocrdma_mqe *cmd;
1157 struct ocrdma_fw_conf_rsp *rsp;
1158
1159 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1160 if (!cmd)
1161 return -ENOMEM;
1162 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1163 OCRDMA_CMD_GET_FW_CONFIG,
1164 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1165 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1166 if (status)
1167 goto mbx_err;
1168 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1169 status = ocrdma_check_fw_config(dev, rsp);
1170mbx_err:
1171 kfree(cmd);
1172 return status;
1173}
1174
a51f06e1
SX		 1175int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1176{
1177 struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1178 struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1179 struct ocrdma_rdma_stats_resp *old_stats = NULL;
1180 int status;
1181
1182 old_stats = kzalloc(sizeof(*old_stats), GFP_KERNEL);
1183 if (old_stats == NULL)
1184 return -ENOMEM;
1185
1186 memset(mqe, 0, sizeof(*mqe));
1187 mqe->hdr.pyld_len = dev->stats_mem.size;
1188 mqe->hdr.spcl_sge_cnt_emb |=
1189 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1190 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1191 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1192 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1193 mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1194
1195 /* Cache the old stats */
1196 memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1197 memset(req, 0, dev->stats_mem.size);
1198
1199 ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1200 OCRDMA_CMD_GET_RDMA_STATS,
1201 OCRDMA_SUBSYS_ROCE,
1202 dev->stats_mem.size);
1203 if (reset)
1204 req->reset_stats = reset;
1205
1206 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1207 if (status)
1208 /* Copy from cache, if mbox fails */
1209 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1210 else
1211 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1212
1213 kfree(old_stats);
1214 return status;
1215}
1216
1217static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1218{
1219 int status = -ENOMEM;
1220 struct ocrdma_dma_mem dma;
1221 struct ocrdma_mqe *mqe;
1222 struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1223 struct mgmt_hba_attribs *hba_attribs;
1224
1225 mqe = ocrdma_alloc_mqe();
1226 if (!mqe)
1227 return status;
1228 memset(mqe, 0, sizeof(*mqe));
1229
1230 dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1231 dma.va = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1232 dma.size, &dma.pa, GFP_KERNEL);
1233 if (!dma.va)
1234 goto free_mqe;
1235
1236 mqe->hdr.pyld_len = dma.size;
1237 mqe->hdr.spcl_sge_cnt_emb |=
1238 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1239 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1240 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1241 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1242 mqe->u.nonemb_req.sge[0].len = dma.size;
1243
1244 memset(dma.va, 0, dma.size);
1245 ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1246 OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1247 OCRDMA_SUBSYS_COMMON,
1248 dma.size);
1249
1250 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1251 if (!status) {
1252 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1253 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1254
1255 dev->hba_port_num = hba_attribs->phy_port;
1256 strncpy(dev->model_number,
1257 hba_attribs->controller_model_number, 31);
1258 }
1259 dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1260free_mqe:
1261 kfree(mqe);
1262 return status;
1263}
1264
fe2caefc
PP		 1265static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1266{
1267 int status = -ENOMEM;
1268 struct ocrdma_mbx_query_config *rsp;
1269 struct ocrdma_mqe *cmd;
1270
1271 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1272 if (!cmd)
1273 return status;
1274 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1275 if (status)
1276 goto mbx_err;
1277 rsp = (struct ocrdma_mbx_query_config *)cmd;
1278 ocrdma_get_attr(dev, &dev->attr, rsp);
1279mbx_err:
1280 kfree(cmd);
1281 return status;
1282}
1283
f24ceba6
NG		 1284int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1285{
1286 int status = -ENOMEM;
1287 struct ocrdma_get_link_speed_rsp *rsp;
1288 struct ocrdma_mqe *cmd;
1289
1290 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1291 sizeof(*cmd));
1292 if (!cmd)
1293 return status;
1294 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1295 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1296 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1297
1298 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1299
1300 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1301 if (status)
1302 goto mbx_err;
1303
1304 rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1305 *lnk_speed = rsp->phys_port_speed;
1306
1307mbx_err:
1308 kfree(cmd);
1309 return status;
1310}
1311
a51f06e1
SX		 1312static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1313{
1314 int status = -ENOMEM;
1315 struct ocrdma_mqe *cmd;
1316 struct ocrdma_get_phy_info_rsp *rsp;
1317
1318 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1319 if (!cmd)
1320 return status;
1321
1322 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1323 OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1324 sizeof(*cmd));
1325
1326 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1327 if (status)
1328 goto mbx_err;
1329
1330 rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1331 dev->phy.phy_type = le16_to_cpu(rsp->phy_type);
1332 dev->phy.auto_speeds_supported =
1333 le16_to_cpu(rsp->auto_speeds_supported);
1334 dev->phy.fixed_speeds_supported =
1335 le16_to_cpu(rsp->fixed_speeds_supported);
1336mbx_err:
1337 kfree(cmd);
1338 return status;
1339}
1340
fe2caefc
PP		 1341int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1342{
1343 int status = -ENOMEM;
1344 struct ocrdma_alloc_pd *cmd;
1345 struct ocrdma_alloc_pd_rsp *rsp;
1346
1347 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1348 if (!cmd)
1349 return status;
1350 if (pd->dpp_enabled)
1351 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1352 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1353 if (status)
1354 goto mbx_err;
1355 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1356 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1357 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1358 pd->dpp_enabled = true;
1359 pd->dpp_page = rsp->dpp_page_pdid >>
1360 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1361 } else {
1362 pd->dpp_enabled = false;
1363 pd->num_dpp_qp = 0;
1364 }
1365mbx_err:
1366 kfree(cmd);
1367 return status;
1368}
1369
1370int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1371{
1372 int status = -ENOMEM;
1373 struct ocrdma_dealloc_pd *cmd;
1374
1375 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1376 if (!cmd)
1377 return status;
1378 cmd->id = pd->id;
1379 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1380 kfree(cmd);
1381 return status;
1382}
1383
1384static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1385 int *num_pages, int *page_size)
1386{
1387 int i;
1388 int mem_size;
1389
1390 *num_entries = roundup_pow_of_two(*num_entries);
1391 mem_size = *num_entries * entry_size;
1392 /* find the possible lowest possible multiplier */
1393 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1394 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1395 break;
1396 }
1397 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1398 return -EINVAL;
1399 mem_size = roundup(mem_size,
1400 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1401 *num_pages =
1402 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1403 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1404 *num_entries = mem_size / entry_size;
1405 return 0;
1406}
1407
1408static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1409{
fad51b7d 1410 int i;
fe2caefc
PP		 1411 int status = 0;
1412 int max_ah;
1413 struct ocrdma_create_ah_tbl *cmd;
1414 struct ocrdma_create_ah_tbl_rsp *rsp;
1415 struct pci_dev *pdev = dev->nic_info.pdev;
1416 dma_addr_t pa;
1417 struct ocrdma_pbe *pbes;
1418
1419 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1420 if (!cmd)
1421 return status;
1422
1423 max_ah = OCRDMA_MAX_AH;
1424 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1425
1426 /* number of PBEs in PBL */
1427 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1428 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1429 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1430
1431 /* page size */
1432 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1433 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1434 break;
1435 }
1436 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1437 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1438
1439 /* ah_entry size */
1440 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1441 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1442 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1443
1444 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1445 &dev->av_tbl.pbl.pa,
1446 GFP_KERNEL);
1447 if (dev->av_tbl.pbl.va == NULL)
1448 goto mem_err;
1449
1450 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1451 &pa, GFP_KERNEL);
1452 if (dev->av_tbl.va == NULL)
1453 goto mem_err_ah;
1454 dev->av_tbl.pa = pa;
1455 dev->av_tbl.num_ah = max_ah;
1456 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1457
1458 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1459 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1460 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1461 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1462 pa += PAGE_SIZE;
1463 }
1464 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1465 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1466 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1467 if (status)
1468 goto mbx_err;
1469 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1470 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1471 kfree(cmd);
1472 return 0;
1473
1474mbx_err:
1475 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1476 dev->av_tbl.pa);
1477 dev->av_tbl.va = NULL;
1478mem_err_ah:
1479 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1480 dev->av_tbl.pbl.pa);
1481 dev->av_tbl.pbl.va = NULL;
1482 dev->av_tbl.size = 0;
1483mem_err:
1484 kfree(cmd);
1485 return status;
1486}
1487
1488static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1489{
1490 struct ocrdma_delete_ah_tbl *cmd;
1491 struct pci_dev *pdev = dev->nic_info.pdev;
1492
1493 if (dev->av_tbl.va == NULL)
1494 return;
1495
1496 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1497 if (!cmd)
1498 return;
1499 cmd->ahid = dev->av_tbl.ahid;
1500
1501 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1502 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1503 dev->av_tbl.pa);
1504 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1505 dev->av_tbl.pbl.pa);
1506 kfree(cmd);
1507}
1508
1509/* Multiple CQs uses the EQ. This routine returns least used
1510 * EQ to associate with CQ. This will distributes the interrupt
1511 * processing and CPU load to associated EQ, vector and so to that CPU.
1512 */
1513static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1514{
1515 int i, selected_eq = 0, cq_cnt = 0;
1516 u16 eq_id;
1517
1518 mutex_lock(&dev->dev_lock);
c88bd03f
NG		 1519 cq_cnt = dev->eq_tbl[0].cq_cnt;
1520 eq_id = dev->eq_tbl[0].q.id;
fe2caefc
PP		 1521 /* find the EQ which is has the least number of
1522 * CQs associated with it.
1523 */
1524 for (i = 0; i < dev->eq_cnt; i++) {
c88bd03f
NG		 1525 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1526 cq_cnt = dev->eq_tbl[i].cq_cnt;
1527 eq_id = dev->eq_tbl[i].q.id;
fe2caefc
PP		 1528 selected_eq = i;
1529 }
1530 }
c88bd03f 1531 dev->eq_tbl[selected_eq].cq_cnt += 1;
fe2caefc
PP		 1532 mutex_unlock(&dev->dev_lock);
1533 return eq_id;
1534}
1535
1536static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1537{
1538 int i;
1539
1540 mutex_lock(&dev->dev_lock);
ea617626
DS		 1541 i = ocrdma_get_eq_table_index(dev, eq_id);
1542 if (i == -EINVAL)
1543 BUG();
1544 dev->eq_tbl[i].cq_cnt -= 1;
fe2caefc
PP		 1545 mutex_unlock(&dev->dev_lock);
1546}
1547
1548int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
cffce990 1549 int entries, int dpp_cq, u16 pd_id)
fe2caefc
PP		 1550{
1551 int status = -ENOMEM; int max_hw_cqe;
1552 struct pci_dev *pdev = dev->nic_info.pdev;
1553 struct ocrdma_create_cq *cmd;
1554 struct ocrdma_create_cq_rsp *rsp;
1555 u32 hw_pages, cqe_size, page_size, cqe_count;
1556
fe2caefc 1557 if (entries > dev->attr.max_cqe) {
ef99c4c2
NG		 1558 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1559 __func__, dev->id, dev->attr.max_cqe, entries);
fe2caefc
PP		 1560 return -EINVAL;
1561 }
21c3391a 1562 if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
fe2caefc
PP		 1563 return -EINVAL;
1564
1565 if (dpp_cq) {
1566 cq->max_hw_cqe = 1;
1567 max_hw_cqe = 1;
1568 cqe_size = OCRDMA_DPP_CQE_SIZE;
1569 hw_pages = 1;
1570 } else {
1571 cq->max_hw_cqe = dev->attr.max_cqe;
1572 max_hw_cqe = dev->attr.max_cqe;
1573 cqe_size = sizeof(struct ocrdma_cqe);
1574 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1575 }
1576
1577 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1578
1579 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1580 if (!cmd)
1581 return -ENOMEM;
1582 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1583 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1584 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1585 if (!cq->va) {
1586 status = -ENOMEM;
1587 goto mem_err;
1588 }
1589 memset(cq->va, 0, cq->len);
1590 page_size = cq->len / hw_pages;
1591 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1592 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1593 cmd->cmd.pgsz_pgcnt |= hw_pages;
1594 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1595
fe2caefc 1596 cq->eqn = ocrdma_bind_eq(dev);
cffce990 1597 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
fe2caefc 1598 cqe_count = cq->len / cqe_size;
ea617626 1599 cq->cqe_cnt = cqe_count;
f99b1649 1600 if (cqe_count > 1024) {
fe2caefc
PP		 1601 /* Set cnt to 3 to indicate more than 1024 cq entries */
1602 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
f99b1649 1603 } else {
fe2caefc
PP		 1604 u8 count = 0;
1605 switch (cqe_count) {
1606 case 256:
1607 count = 0;
1608 break;
1609 case 512:
1610 count = 1;
1611 break;
1612 case 1024:
1613 count = 2;
1614 break;
1615 default:
1616 goto mbx_err;
1617 }
1618 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1619 }
1620 /* shared eq between all the consumer cqs. */
1621 cmd->cmd.eqn = cq->eqn;
21c3391a 1622 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
fe2caefc
PP		 1623 if (dpp_cq)
1624 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1625 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1626 cq->phase_change = false;
1627 cmd->cmd.cqe_count = (cq->len / cqe_size);
1628 } else {
1629 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1630 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1631 cq->phase_change = true;
1632 }
1633
cffce990 1634 cmd->cmd.pd_id = pd_id; /* valid only for v3 */
fe2caefc
PP		 1635 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1636 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1637 if (status)
1638 goto mbx_err;
1639
1640 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1641 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1642 kfree(cmd);
1643 return 0;
1644mbx_err:
1645 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc
PP		 1646 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1647mem_err:
1648 kfree(cmd);
1649 return status;
1650}
1651
1652int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1653{
1654 int status = -ENOMEM;
1655 struct ocrdma_destroy_cq *cmd;
1656
1657 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1658 if (!cmd)
1659 return status;
1660 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1661 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1662
1663 cmd->bypass_flush_qid |=
1664 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1665 OCRDMA_DESTROY_CQ_QID_MASK;
1666
fe2caefc 1667 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
ea617626 1668 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc 1669 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
fe2caefc
PP		 1670 kfree(cmd);
1671 return status;
1672}
1673
1674int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1675 u32 pdid, int addr_check)
1676{
1677 int status = -ENOMEM;
1678 struct ocrdma_alloc_lkey *cmd;
1679 struct ocrdma_alloc_lkey_rsp *rsp;
1680
1681 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1682 if (!cmd)
1683 return status;
1684 cmd->pdid = pdid;
1685 cmd->pbl_sz_flags |= addr_check;
1686 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1687 cmd->pbl_sz_flags |=
1688 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1689 cmd->pbl_sz_flags |=
1690 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1691 cmd->pbl_sz_flags |=
1692 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1693 cmd->pbl_sz_flags |=
1694 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1695 cmd->pbl_sz_flags |=
1696 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1697
1698 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1699 if (status)
1700 goto mbx_err;
1701 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1702 hwmr->lkey = rsp->lrkey;
1703mbx_err:
1704 kfree(cmd);
1705 return status;
1706}
1707
1708int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1709{
1710 int status = -ENOMEM;
1711 struct ocrdma_dealloc_lkey *cmd;
1712
1713 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1714 if (!cmd)
1715 return -ENOMEM;
1716 cmd->lkey = lkey;
1717 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1718 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1719 if (status)
1720 goto mbx_err;
1721mbx_err:
1722 kfree(cmd);
1723 return status;
1724}
1725
1726static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1727 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1728{
1729 int status = -ENOMEM;
1730 int i;
1731 struct ocrdma_reg_nsmr *cmd;
1732 struct ocrdma_reg_nsmr_rsp *rsp;
1733
1734 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1735 if (!cmd)
1736 return -ENOMEM;
1737 cmd->num_pbl_pdid =
1738 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
2b51a9b9 1739 cmd->fr_mr = hwmr->fr_mr;
fe2caefc
PP		 1740
1741 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1742 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1743 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1744 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1745 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1746 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1747 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1748 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1749 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1750 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1751 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1752
1753 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1754 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1755 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1756 cmd->totlen_low = hwmr->len;
1757 cmd->totlen_high = upper_32_bits(hwmr->len);
1758 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1759 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1760 cmd->va_loaddr = (u32) hwmr->va;
1761 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1762
1763 for (i = 0; i < pbl_cnt; i++) {
1764 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1765 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1766 }
1767 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1768 if (status)
1769 goto mbx_err;
1770 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1771 hwmr->lkey = rsp->lrkey;
1772mbx_err:
1773 kfree(cmd);
1774 return status;
1775}
1776
1777static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1778 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1779 u32 pbl_offset, u32 last)
1780{
1781 int status = -ENOMEM;
1782 int i;
1783 struct ocrdma_reg_nsmr_cont *cmd;
1784
1785 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1786 if (!cmd)
1787 return -ENOMEM;
1788 cmd->lrkey = hwmr->lkey;
1789 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1790 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1791 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1792
1793 for (i = 0; i < pbl_cnt; i++) {
1794 cmd->pbl[i].lo =
1795 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1796 cmd->pbl[i].hi =
1797 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1798 }
1799 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1800 if (status)
1801 goto mbx_err;
1802mbx_err:
1803 kfree(cmd);
1804 return status;
1805}
1806
1807int ocrdma_reg_mr(struct ocrdma_dev *dev,
1808 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1809{
1810 int status;
1811 u32 last = 0;
1812 u32 cur_pbl_cnt, pbl_offset;
1813 u32 pending_pbl_cnt = hwmr->num_pbls;
1814
1815 pbl_offset = 0;
1816 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1817 if (cur_pbl_cnt == pending_pbl_cnt)
1818 last = 1;
1819
1820 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1821 cur_pbl_cnt, hwmr->pbe_size, last);
1822 if (status) {
ef99c4c2 1823 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 1824 return status;
1825 }
1826 /* if there is no more pbls to register then exit. */
1827 if (last)
1828 return 0;
1829
1830 while (!last) {
1831 pbl_offset += cur_pbl_cnt;
1832 pending_pbl_cnt -= cur_pbl_cnt;
1833 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1834 /* if we reach the end of the pbls, then need to set the last
1835 * bit, indicating no more pbls to register for this memory key.
1836 */
1837 if (cur_pbl_cnt == pending_pbl_cnt)
1838 last = 1;
1839
1840 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1841 pbl_offset, last);
1842 if (status)
1843 break;
1844 }
1845 if (status)
ef99c4c2 1846 pr_err("%s() err. status=%d\n", __func__, status);
fe2caefc
PP		 1847
1848 return status;
1849}
1850
1851bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1852{
1853 struct ocrdma_qp *tmp;
1854 bool found = false;
1855 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1856 if (qp == tmp) {
1857 found = true;
1858 break;
1859 }
1860 }
1861 return found;
1862}
1863
1864bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1865{
1866 struct ocrdma_qp *tmp;
1867 bool found = false;
1868 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1869 if (qp == tmp) {
1870 found = true;
1871 break;
1872 }
1873 }
1874 return found;
1875}
1876
1877void ocrdma_flush_qp(struct ocrdma_qp *qp)
1878{
1879 bool found;
1880 unsigned long flags;
1881
1882 spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1883 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1884 if (!found)
1885 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1886 if (!qp->srq) {
1887 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1888 if (!found)
1889 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1890 }
1891 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1892}
1893
f11220ee
NG		 1894static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
1895{
1896 qp->sq.head = 0;
1897 qp->sq.tail = 0;
1898 qp->rq.head = 0;
1899 qp->rq.tail = 0;
1900}
1901
057729cb
NG		 1902int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1903 enum ib_qp_state *old_ib_state)
fe2caefc
PP		 1904{
1905 unsigned long flags;
1906 int status = 0;
1907 enum ocrdma_qp_state new_state;
1908 new_state = get_ocrdma_qp_state(new_ib_state);
1909
1910 /* sync with wqe and rqe posting */
1911 spin_lock_irqsave(&qp->q_lock, flags);
1912
1913 if (old_ib_state)
1914 *old_ib_state = get_ibqp_state(qp->state);
1915 if (new_state == qp->state) {
1916 spin_unlock_irqrestore(&qp->q_lock, flags);
1917 return 1;
1918 }
1919
057729cb 1920
f11220ee
NG		 1921 if (new_state == OCRDMA_QPS_INIT) {
1922 ocrdma_init_hwq_ptr(qp);
1923 ocrdma_del_flush_qp(qp);
1924 } else if (new_state == OCRDMA_QPS_ERR) {
057729cb 1925 ocrdma_flush_qp(qp);
f11220ee 1926 }
057729cb
NG		 1927
1928 qp->state = new_state;
fe2caefc
PP		 1929
1930 spin_unlock_irqrestore(&qp->q_lock, flags);
1931 return status;
1932}
1933
1934static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1935{
1936 u32 flags = 0;
1937 if (qp->cap_flags & OCRDMA_QP_INB_RD)
1938 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1939 if (qp->cap_flags & OCRDMA_QP_INB_WR)
1940 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1941 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1942 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1943 if (qp->cap_flags & OCRDMA_QP_LKEY0)
1944 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1945 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1946 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1947 return flags;
1948}
1949
1950static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1951 struct ib_qp_init_attr *attrs,
1952 struct ocrdma_qp *qp)
1953{
1954 int status;
1955 u32 len, hw_pages, hw_page_size;
1956 dma_addr_t pa;
1957 struct ocrdma_dev *dev = qp->dev;
1958 struct pci_dev *pdev = dev->nic_info.pdev;
1959 u32 max_wqe_allocated;
1960 u32 max_sges = attrs->cap.max_send_sge;
1961
43a6b402 1962 /* QP1 may exceed 127 */
6ebacdfc 1963 max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
43a6b402 1964 dev->attr.max_wqe);
fe2caefc
PP		 1965
1966 status = ocrdma_build_q_conf(&max_wqe_allocated,
1967 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1968 if (status) {
ef99c4c2
NG		 1969 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1970 max_wqe_allocated);
fe2caefc
PP		 1971 return -EINVAL;
1972 }
1973 qp->sq.max_cnt = max_wqe_allocated;
1974 len = (hw_pages * hw_page_size);
1975
1976 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1977 if (!qp->sq.va)
1978 return -EINVAL;
1979 memset(qp->sq.va, 0, len);
1980 qp->sq.len = len;
1981 qp->sq.pa = pa;
1982 qp->sq.entry_size = dev->attr.wqe_size;
1983 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1984
1985 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1986 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1987 cmd->num_wq_rq_pages |= (hw_pages <<
1988 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1989 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1990 cmd->max_sge_send_write |= (max_sges <<
1991 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1992 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1993 cmd->max_sge_send_write |= (max_sges <<
1994 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1995 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1996 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1997 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1998 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1999 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2000 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2001 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2002 return 0;
2003}
2004
2005static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2006 struct ib_qp_init_attr *attrs,
2007 struct ocrdma_qp *qp)
2008{
2009 int status;
2010 u32 len, hw_pages, hw_page_size;
2011 dma_addr_t pa = 0;
2012 struct ocrdma_dev *dev = qp->dev;
2013 struct pci_dev *pdev = dev->nic_info.pdev;
2014 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2015
2016 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2017 &hw_pages, &hw_page_size);
2018 if (status) {
ef99c4c2
NG		 2019 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2020 attrs->cap.max_recv_wr + 1);
fe2caefc
PP		 2021 return status;
2022 }
2023 qp->rq.max_cnt = max_rqe_allocated;
2024 len = (hw_pages * hw_page_size);
2025
2026 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2027 if (!qp->rq.va)
c94e15c5 2028 return -ENOMEM;
fe2caefc
PP		 2029 memset(qp->rq.va, 0, len);
2030 qp->rq.pa = pa;
2031 qp->rq.len = len;
2032 qp->rq.entry_size = dev->attr.rqe_size;
2033
2034 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2035 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2036 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2037 cmd->num_wq_rq_pages |=
2038 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2039 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2040 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2041 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2042 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2043 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2044 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2045 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2046 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2047 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2048 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2049 return 0;
2050}
2051
2052static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2053 struct ocrdma_pd *pd,
2054 struct ocrdma_qp *qp,
2055 u8 enable_dpp_cq, u16 dpp_cq_id)
2056{
2057 pd->num_dpp_qp--;
2058 qp->dpp_enabled = true;
2059 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2060 if (!enable_dpp_cq)
2061 return;
2062 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2063 cmd->dpp_credits_cqid = dpp_cq_id;
2064 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2065 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2066}
2067
2068static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2069 struct ocrdma_qp *qp)
2070{
2071 struct ocrdma_dev *dev = qp->dev;
2072 struct pci_dev *pdev = dev->nic_info.pdev;
2073 dma_addr_t pa = 0;
2074 int ird_page_size = dev->attr.ird_page_size;
2075 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
43a6b402
NG		 2076 struct ocrdma_hdr_wqe *rqe;
2077 int i = 0;
fe2caefc
PP		 2078
2079 if (dev->attr.ird == 0)
2080 return 0;
2081
2082 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2083 &pa, GFP_KERNEL);
2084 if (!qp->ird_q_va)
2085 return -ENOMEM;
2086 memset(qp->ird_q_va, 0, ird_q_len);
2087 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2088 pa, ird_page_size);
43a6b402
NG		 2089 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2090 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2091 (i * dev->attr.rqe_size));
2092 rqe->cw = 0;
2093 rqe->cw |= 2;
2094 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2095 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2096 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2097 }
fe2caefc
PP		 2098 return 0;
2099}
2100
2101static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2102 struct ocrdma_qp *qp,
2103 struct ib_qp_init_attr *attrs,
2104 u16 *dpp_offset, u16 *dpp_credit_lmt)
2105{
2106 u32 max_wqe_allocated, max_rqe_allocated;
2107 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2108 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2109 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2110 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2111 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2112 qp->dpp_enabled = false;
2113 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2114 qp->dpp_enabled = true;
2115 *dpp_credit_lmt = (rsp->dpp_response &
2116 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2117 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2118 *dpp_offset = (rsp->dpp_response &
2119 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2120 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2121 }
2122 max_wqe_allocated =
2123 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2124 max_wqe_allocated = 1 << max_wqe_allocated;
2125 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2126
fe2caefc
PP		 2127 qp->sq.max_cnt = max_wqe_allocated;
2128 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2129
2130 if (!attrs->srq) {
2131 qp->rq.max_cnt = max_rqe_allocated;
2132 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
fe2caefc
PP		 2133 }
2134}
2135
2136int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2137 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2138 u16 *dpp_credit_lmt)
2139{
2140 int status = -ENOMEM;
2141 u32 flags = 0;
2142 struct ocrdma_dev *dev = qp->dev;
2143 struct ocrdma_pd *pd = qp->pd;
2144 struct pci_dev *pdev = dev->nic_info.pdev;
2145 struct ocrdma_cq *cq;
2146 struct ocrdma_create_qp_req *cmd;
2147 struct ocrdma_create_qp_rsp *rsp;
2148 int qptype;
2149
2150 switch (attrs->qp_type) {
2151 case IB_QPT_GSI:
2152 qptype = OCRDMA_QPT_GSI;
2153 break;
2154 case IB_QPT_RC:
2155 qptype = OCRDMA_QPT_RC;
2156 break;
2157 case IB_QPT_UD:
2158 qptype = OCRDMA_QPT_UD;
2159 break;
2160 default:
2161 return -EINVAL;
2b50176d 2162 }
fe2caefc
PP		 2163
2164 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2165 if (!cmd)
2166 return status;
2167 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2168 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2169 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2170 if (status)
2171 goto sq_err;
2172
2173 if (attrs->srq) {
2174 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2175 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2176 cmd->rq_addr[0].lo = srq->id;
2177 qp->srq = srq;
2178 } else {
2179 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2180 if (status)
2181 goto rq_err;
2182 }
2183
2184 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2185 if (status)
2186 goto mbx_err;
2187
2188 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2189 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2190
2191 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2192
2193 cmd->max_sge_recv_flags |= flags;
2194 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2195 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2196 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2197 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2198 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2199 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2200 cq = get_ocrdma_cq(attrs->send_cq);
2201 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2202 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2203 qp->sq_cq = cq;
2204 cq = get_ocrdma_cq(attrs->recv_cq);
2205 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2206 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2207 qp->rq_cq = cq;
2208
f50f31e4
DS		 2209 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2210 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
fe2caefc
PP		 2211 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2212 dpp_cq_id);
f99b1649 2213 }
fe2caefc
PP		 2214
2215 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2216 if (status)
2217 goto mbx_err;
2218 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2219 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2220 qp->state = OCRDMA_QPS_RST;
2221 kfree(cmd);
2222 return 0;
2223mbx_err:
2224 if (qp->rq.va)
2225 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2226rq_err:
ef99c4c2 2227 pr_err("%s(%d) rq_err\n", __func__, dev->id);
fe2caefc
PP		 2228 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2229sq_err:
ef99c4c2 2230 pr_err("%s(%d) sq_err\n", __func__, dev->id);
fe2caefc
PP		 2231 kfree(cmd);
2232 return status;
2233}
2234
2235int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2236 struct ocrdma_qp_params *param)
2237{
2238 int status = -ENOMEM;
2239 struct ocrdma_query_qp *cmd;
2240 struct ocrdma_query_qp_rsp *rsp;
2241
2242 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2243 if (!cmd)
2244 return status;
2245 cmd->qp_id = qp->id;
2246 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2247 if (status)
2248 goto mbx_err;
2249 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2250 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2251mbx_err:
2252 kfree(cmd);
2253 return status;
2254}
2255
f99b1649 2256static int ocrdma_set_av_params(struct ocrdma_qp *qp,
fe2caefc
PP		 2257 struct ocrdma_modify_qp *cmd,
2258 struct ib_qp_attr *attrs)
2259{
f99b1649 2260 int status;
fe2caefc 2261 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
9c58726b 2262 union ib_gid sgid, zgid;
fe2caefc
PP		 2263 u32 vlan_id;
2264 u8 mac_addr[6];
9c58726b 2265
fe2caefc 2266 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
f99b1649 2267 return -EINVAL;
fe2caefc
PP		 2268 cmd->params.tclass_sq_psn |=
2269 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2270 cmd->params.rnt_rc_sl_fl |=
2271 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2b51a9b9 2272 cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
fe2caefc
PP		 2273 cmd->params.hop_lmt_rq_psn |=
2274 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2275 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2276 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2277 sizeof(cmd->params.dgid));
f99b1649 2278 status = ocrdma_query_gid(&qp->dev->ibdev, 1,
fad51b7d 2279 ah_attr->grh.sgid_index, &sgid);
f99b1649
NG		 2280 if (status)
2281 return status;
9c58726b
NG		 2282
2283 memset(&zgid, 0, sizeof(zgid));
2284 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2285 return -EINVAL;
2286
fe2caefc
PP		 2287 qp->sgid_idx = ah_attr->grh.sgid_index;
2288 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
40aca6ff 2289 ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
fe2caefc
PP		 2290 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2291 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2292 /* convert them to LE format. */
2293 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2294 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2295 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
40aca6ff 2296 vlan_id = ah_attr->vlan_id;
fe2caefc
PP		 2297 if (vlan_id && (vlan_id < 0x1000)) {
2298 cmd->params.vlan_dmac_b4_to_b5 |=
2299 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2300 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2301 }
f99b1649 2302 return 0;
fe2caefc
PP		 2303}
2304
2305static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2306 struct ocrdma_modify_qp *cmd,
bc1b04ab 2307 struct ib_qp_attr *attrs, int attr_mask)
fe2caefc
PP		 2308{
2309 int status = 0;
fe2caefc
PP		 2310
2311 if (attr_mask & IB_QP_PKEY_INDEX) {
2312 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2313 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2314 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2315 }
2316 if (attr_mask & IB_QP_QKEY) {
2317 qp->qkey = attrs->qkey;
2318 cmd->params.qkey = attrs->qkey;
2319 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2320 }
f99b1649
NG		 2321 if (attr_mask & IB_QP_AV) {
2322 status = ocrdma_set_av_params(qp, cmd, attrs);
2323 if (status)
2324 return status;
2325 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
fe2caefc
PP		 2326 /* set the default mac address for UD, GSI QPs */
2327 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2328 (qp->dev->nic_info.mac_addr[1] << 8) |
2329 (qp->dev->nic_info.mac_addr[2] << 16) |
2330 (qp->dev->nic_info.mac_addr[3] << 24);
2331 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2332 (qp->dev->nic_info.mac_addr[5] << 8);
2333 }
2334 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2335 attrs->en_sqd_async_notify) {
2336 cmd->params.max_sge_recv_flags |=
2337 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2338 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2339 }
2340 if (attr_mask & IB_QP_DEST_QPN) {
2341 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2342 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2343 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2344 }
2345 if (attr_mask & IB_QP_PATH_MTU) {
d3cb6c0b
NG		 2346 if (attrs->path_mtu < IB_MTU_256 ||
2347 attrs->path_mtu > IB_MTU_4096) {
fe2caefc
PP		 2348 status = -EINVAL;
2349 goto pmtu_err;
2350 }
2351 cmd->params.path_mtu_pkey_indx |=
2352 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2353 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2354 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2355 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2356 }
2357 if (attr_mask & IB_QP_TIMEOUT) {
2358 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2359 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2360 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2361 }
2362 if (attr_mask & IB_QP_RETRY_CNT) {
2363 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2364 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2365 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2366 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2367 }
2368 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2369 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2370 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2371 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2372 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2373 }
2374 if (attr_mask & IB_QP_RNR_RETRY) {
2375 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2376 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2377 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2378 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2379 }
2380 if (attr_mask & IB_QP_SQ_PSN) {
2381 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2382 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2383 }
2384 if (attr_mask & IB_QP_RQ_PSN) {
2385 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2386 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2387 }
2388 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2389 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2390 status = -EINVAL;
2391 goto pmtu_err;
2392 }
2393 qp->max_ord = attrs->max_rd_atomic;
2394 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2395 }
2396 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2397 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2398 status = -EINVAL;
2399 goto pmtu_err;
2400 }
2401 qp->max_ird = attrs->max_dest_rd_atomic;
2402 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2403 }
2404 cmd->params.max_ord_ird = (qp->max_ord <<
2405 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2406 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2407pmtu_err:
2408 return status;
2409}
2410
2411int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
bc1b04ab 2412 struct ib_qp_attr *attrs, int attr_mask)
fe2caefc
PP		 2413{
2414 int status = -ENOMEM;
2415 struct ocrdma_modify_qp *cmd;
fe2caefc
PP		 2416
2417 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2418 if (!cmd)
2419 return status;
2420
2421 cmd->params.id = qp->id;
2422 cmd->flags = 0;
2423 if (attr_mask & IB_QP_STATE) {
2424 cmd->params.max_sge_recv_flags |=
2425 (get_ocrdma_qp_state(attrs->qp_state) <<
2426 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2427 OCRDMA_QP_PARAMS_STATE_MASK;
2428 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
f99b1649 2429 } else {
fe2caefc
PP		 2430 cmd->params.max_sge_recv_flags |=
2431 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2432 OCRDMA_QP_PARAMS_STATE_MASK;
f99b1649
NG		 2433 }
2434
bc1b04ab 2435 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
fe2caefc
PP		 2436 if (status)
2437 goto mbx_err;
2438 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2439 if (status)
2440 goto mbx_err;
c592c423 2441
fe2caefc
PP		 2442mbx_err:
2443 kfree(cmd);
2444 return status;
2445}
2446
2447int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2448{
2449 int status = -ENOMEM;
2450 struct ocrdma_destroy_qp *cmd;
fe2caefc
PP		 2451 struct pci_dev *pdev = dev->nic_info.pdev;
2452
2453 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2454 if (!cmd)
2455 return status;
2456 cmd->qp_id = qp->id;
2457 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2458 if (status)
2459 goto mbx_err;
c592c423 2460
fe2caefc
PP		 2461mbx_err:
2462 kfree(cmd);
2463 if (qp->sq.va)
2464 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2465 if (!qp->srq && qp->rq.va)
2466 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2467 if (qp->dpp_enabled)
2468 qp->pd->num_dpp_qp++;
2469 return status;
2470}
2471
1afc0454 2472int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
fe2caefc
PP		 2473 struct ib_srq_init_attr *srq_attr,
2474 struct ocrdma_pd *pd)
2475{
2476 int status = -ENOMEM;
2477 int hw_pages, hw_page_size;
2478 int len;
2479 struct ocrdma_create_srq_rsp *rsp;
2480 struct ocrdma_create_srq *cmd;
2481 dma_addr_t pa;
fe2caefc
PP		 2482 struct pci_dev *pdev = dev->nic_info.pdev;
2483 u32 max_rqe_allocated;
2484
2485 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2486 if (!cmd)
2487 return status;
2488
2489 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2490 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2491 status = ocrdma_build_q_conf(&max_rqe_allocated,
2492 dev->attr.rqe_size,
2493 &hw_pages, &hw_page_size);
2494 if (status) {
ef99c4c2
NG		 2495 pr_err("%s() req. max_wr=0x%x\n", __func__,
2496 srq_attr->attr.max_wr);
fe2caefc
PP		 2497 status = -EINVAL;
2498 goto ret;
2499 }
2500 len = hw_pages * hw_page_size;
2501 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2502 if (!srq->rq.va) {
2503 status = -ENOMEM;
2504 goto ret;
2505 }
2506 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2507
2508 srq->rq.entry_size = dev->attr.rqe_size;
2509 srq->rq.pa = pa;
2510 srq->rq.len = len;
2511 srq->rq.max_cnt = max_rqe_allocated;
2512
2513 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2514 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2515 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2516
2517 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2518 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2519 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2520 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2521 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2522 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2523
2524 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2525 if (status)
2526 goto mbx_err;
2527 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2528 srq->id = rsp->id;
2529 srq->rq.dbid = rsp->id;
2530 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2531 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2532 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2533 max_rqe_allocated = (1 << max_rqe_allocated);
2534 srq->rq.max_cnt = max_rqe_allocated;
2535 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2536 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2537 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2538 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2539 goto ret;
2540mbx_err:
2541 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2542ret:
2543 kfree(cmd);
2544 return status;
2545}
2546
2547int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2548{
2549 int status = -ENOMEM;
2550 struct ocrdma_modify_srq *cmd;
f11220ee
NG		 2551 struct ocrdma_pd *pd = srq->pd;
2552 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
1afc0454 2553
d7e19c0a 2554 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
fe2caefc
PP		 2555 if (!cmd)
2556 return status;
2557 cmd->id = srq->id;
2558 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2559 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
1afc0454 2560 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2561 kfree(cmd);
2562 return status;
2563}
2564
2565int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2566{
2567 int status = -ENOMEM;
2568 struct ocrdma_query_srq *cmd;
1afc0454
NG		 2569 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2570
d7e19c0a 2571 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
fe2caefc
PP		 2572 if (!cmd)
2573 return status;
2574 cmd->id = srq->rq.dbid;
1afc0454 2575 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2576 if (status == 0) {
2577 struct ocrdma_query_srq_rsp *rsp =
2578 (struct ocrdma_query_srq_rsp *)cmd;
2579 srq_attr->max_sge =
2580 rsp->srq_lmt_max_sge &
2581 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2582 srq_attr->max_wr =
2583 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2584 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2585 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2586 }
2587 kfree(cmd);
2588 return status;
2589}
2590
2591int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2592{
2593 int status = -ENOMEM;
2594 struct ocrdma_destroy_srq *cmd;
2595 struct pci_dev *pdev = dev->nic_info.pdev;
2596 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2597 if (!cmd)
2598 return status;
2599 cmd->id = srq->id;
1afc0454 2600 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2601 if (srq->rq.va)
2602 dma_free_coherent(&pdev->dev, srq->rq.len,
2603 srq->rq.va, srq->rq.pa);
2604 kfree(cmd);
2605 return status;
2606}
2607
2608int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2609{
2610 int i;
2611 int status = -EINVAL;
2612 struct ocrdma_av *av;
2613 unsigned long flags;
2614
2615 av = dev->av_tbl.va;
2616 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2617 for (i = 0; i < dev->av_tbl.num_ah; i++) {
2618 if (av->valid == 0) {
2619 av->valid = OCRDMA_AV_VALID;
2620 ah->av = av;
2621 ah->id = i;
2622 status = 0;
2623 break;
2624 }
2625 av++;
2626 }
2627 if (i == dev->av_tbl.num_ah)
2628 status = -EAGAIN;
2629 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2630 return status;
2631}
2632
2633int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2634{
2635 unsigned long flags;
2636 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2637 ah->av->valid = 0;
2638 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2639 return 0;
2640}
2641
c88bd03f 2642static int ocrdma_create_eqs(struct ocrdma_dev *dev)
fe2caefc 2643{
da496438 2644 int num_eq, i, status = 0;
fe2caefc
PP		 2645 int irq;
2646 unsigned long flags = 0;
2647
2648 num_eq = dev->nic_info.msix.num_vectors -
2649 dev->nic_info.msix.start_vector;
2650 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2651 num_eq = 1;
2652 flags = IRQF_SHARED;
f99b1649 2653 } else {
fe2caefc 2654 num_eq = min_t(u32, num_eq, num_online_cpus());
f99b1649
NG		 2655 }
2656
c88bd03f
NG		 2657 if (!num_eq)
2658 return -EINVAL;
2659
2660 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2661 if (!dev->eq_tbl)
fe2caefc
PP		 2662 return -ENOMEM;
2663
2664 for (i = 0; i < num_eq; i++) {
c88bd03f 2665 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
fad51b7d 2666 OCRDMA_EQ_LEN);
fe2caefc
PP		 2667 if (status) {
2668 status = -EINVAL;
2669 break;
2670 }
c88bd03f 2671 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
fe2caefc 2672 dev->id, i);
c88bd03f 2673 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
fe2caefc 2674 status = request_irq(irq, ocrdma_irq_handler, flags,
c88bd03f
NG		 2675 dev->eq_tbl[i].irq_name,
2676 &dev->eq_tbl[i]);
2677 if (status)
2678 goto done;
fe2caefc
PP		 2679 dev->eq_cnt += 1;
2680 }
2681 /* one eq is sufficient for data path to work */
c88bd03f
NG		 2682 return 0;
2683done:
2684 ocrdma_destroy_eqs(dev);
fe2caefc
PP		 2685 return status;
2686}
2687
2688int ocrdma_init_hw(struct ocrdma_dev *dev)
2689{
2690 int status;
c88bd03f
NG		 2691
2692 /* create the eqs */
2693 status = ocrdma_create_eqs(dev);
fe2caefc
PP		 2694 if (status)
2695 goto qpeq_err;
2696 status = ocrdma_create_mq(dev);
2697 if (status)
2698 goto mq_err;
2699 status = ocrdma_mbx_query_fw_config(dev);
2700 if (status)
2701 goto conf_err;
2702 status = ocrdma_mbx_query_dev(dev);
2703 if (status)
2704 goto conf_err;
2705 status = ocrdma_mbx_query_fw_ver(dev);
2706 if (status)
2707 goto conf_err;
2708 status = ocrdma_mbx_create_ah_tbl(dev);
2709 if (status)
2710 goto conf_err;
a51f06e1
SX		 2711 status = ocrdma_mbx_get_phy_info(dev);
2712 if (status)
2713 goto conf_err;
2714 status = ocrdma_mbx_get_ctrl_attribs(dev);
2715 if (status)
2716 goto conf_err;
2717
fe2caefc
PP		 2718 return 0;
2719
2720conf_err:
2721 ocrdma_destroy_mq(dev);
2722mq_err:
c88bd03f 2723 ocrdma_destroy_eqs(dev);
fe2caefc 2724qpeq_err:
ef99c4c2 2725 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 2726 return status;
2727}
2728
2729void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2730{
2731 ocrdma_mbx_delete_ah_tbl(dev);
2732
c88bd03f
NG		 2733 /* cleanup the eqs */
2734 ocrdma_destroy_eqs(dev);
fe2caefc
PP		 2735
2736 /* cleanup the control path */
2737 ocrdma_destroy_mq(dev);
fe2caefc 2738}
Linux 6.x block layer and io_uring tree(s)