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[linux-2.6-block.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
CommitLineData
71ee6730
DS		 1/* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
5 * www.emulex.com
6 *
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
fe2caefc
PP		 34 *
35 * Contact Information:
36 * linux-drivers@emulex.com
37 *
38 * Emulex
39 * 3333 Susan Street
40 * Costa Mesa, CA 92626
71ee6730 41 */
fe2caefc
PP		 42
43#include <linux/sched.h>
44#include <linux/interrupt.h>
45#include <linux/log2.h>
46#include <linux/dma-mapping.h>
69ae5439 47#include <linux/if_ether.h>
fe2caefc
PP		 48
49#include <rdma/ib_verbs.h>
50#include <rdma/ib_user_verbs.h>
dbf727de 51#include <rdma/ib_cache.h>
fe2caefc
PP		 52
53#include "ocrdma.h"
54#include "ocrdma_hw.h"
55#include "ocrdma_verbs.h"
56#include "ocrdma_ah.h"
57
58enum mbx_status {
59 OCRDMA_MBX_STATUS_FAILED = 1,
60 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
61 OCRDMA_MBX_STATUS_OOR = 100,
62 OCRDMA_MBX_STATUS_INVALID_PD = 101,
63 OCRDMA_MBX_STATUS_PD_INUSE = 102,
64 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
65 OCRDMA_MBX_STATUS_INVALID_QP = 104,
66 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
67 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
68 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
69 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
70 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
71 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
72 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
73 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
74 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
75 OCRDMA_MBX_STATUS_MW_BOUND = 114,
76 OCRDMA_MBX_STATUS_INVALID_VA = 115,
77 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
78 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
79 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
80 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
81 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
82 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
83 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
84 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
85 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
86 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
87 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
88 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
89 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
90 OCRDMA_MBX_STATUS_QP_BOUND = 130,
91 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
92 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
93 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
94 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
95 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
96 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
97};
98
99enum additional_status {
100 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
101};
102
103enum cqe_status {
104 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
105 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
106 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
107 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
108 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
109};
110
111static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
112{
f99b1649 113 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
fe2caefc
PP		 114}
115
116static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
117{
118 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
119}
120
121static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
122{
123 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
f99b1649 124 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
fe2caefc
PP		 125
126 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
127 return NULL;
128 return cqe;
129}
130
131static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
132{
133 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
134}
135
136static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
137{
f99b1649 138 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 139}
140
141static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
142{
143 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
fe2caefc
PP		 144}
145
146static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
147{
f99b1649 148 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 149}
150
151enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
152{
153 switch (qps) {
154 case OCRDMA_QPS_RST:
155 return IB_QPS_RESET;
156 case OCRDMA_QPS_INIT:
157 return IB_QPS_INIT;
158 case OCRDMA_QPS_RTR:
159 return IB_QPS_RTR;
160 case OCRDMA_QPS_RTS:
161 return IB_QPS_RTS;
162 case OCRDMA_QPS_SQD:
163 case OCRDMA_QPS_SQ_DRAINING:
164 return IB_QPS_SQD;
165 case OCRDMA_QPS_SQE:
166 return IB_QPS_SQE;
167 case OCRDMA_QPS_ERR:
168 return IB_QPS_ERR;
2b50176d 169 }
fe2caefc
PP		 170 return IB_QPS_ERR;
171}
172
abe3afac 173static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
fe2caefc
PP		 174{
175 switch (qps) {
176 case IB_QPS_RESET:
177 return OCRDMA_QPS_RST;
178 case IB_QPS_INIT:
179 return OCRDMA_QPS_INIT;
180 case IB_QPS_RTR:
181 return OCRDMA_QPS_RTR;
182 case IB_QPS_RTS:
183 return OCRDMA_QPS_RTS;
184 case IB_QPS_SQD:
185 return OCRDMA_QPS_SQD;
186 case IB_QPS_SQE:
187 return OCRDMA_QPS_SQE;
188 case IB_QPS_ERR:
189 return OCRDMA_QPS_ERR;
2b50176d 190 }
fe2caefc
PP		 191 return OCRDMA_QPS_ERR;
192}
193
194static int ocrdma_get_mbx_errno(u32 status)
195{
f99b1649 196 int err_num;
fe2caefc
PP		 197 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
198 OCRDMA_MBX_RSP_STATUS_SHIFT;
199 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
200 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
201
202 switch (mbox_status) {
203 case OCRDMA_MBX_STATUS_OOR:
204 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
205 err_num = -EAGAIN;
206 break;
207
208 case OCRDMA_MBX_STATUS_INVALID_PD:
209 case OCRDMA_MBX_STATUS_INVALID_CQ:
210 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
211 case OCRDMA_MBX_STATUS_INVALID_QP:
212 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
213 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
214 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
215 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
216 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
217 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
218 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
219 case OCRDMA_MBX_STATUS_INVALID_LKEY:
220 case OCRDMA_MBX_STATUS_INVALID_VA:
221 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
222 case OCRDMA_MBX_STATUS_INVALID_FBO:
223 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
224 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
225 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
226 case OCRDMA_MBX_STATUS_SRQ_ERROR:
227 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
228 err_num = -EINVAL;
229 break;
230
231 case OCRDMA_MBX_STATUS_PD_INUSE:
232 case OCRDMA_MBX_STATUS_QP_BOUND:
233 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
234 case OCRDMA_MBX_STATUS_MW_BOUND:
235 err_num = -EBUSY;
236 break;
237
238 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
239 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
240 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
241 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
242 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
243 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
244 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
245 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
246 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
247 err_num = -ENOBUFS;
248 break;
249
250 case OCRDMA_MBX_STATUS_FAILED:
251 switch (add_status) {
252 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
253 err_num = -EAGAIN;
254 break;
06564f60
CIK		 255 default:
256 err_num = -EFAULT;
fe2caefc 257 }
06564f60 258 break;
fe2caefc
PP		 259 default:
260 err_num = -EFAULT;
261 }
262 return err_num;
263}
264
a51f06e1
SX		 265char *port_speed_string(struct ocrdma_dev *dev)
266{
267 char *str = "";
268 u16 speeds_supported;
269
270 speeds_supported = dev->phy.fixed_speeds_supported |
271 dev->phy.auto_speeds_supported;
272 if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
273 str = "40Gbps ";
274 else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
275 str = "10Gbps ";
276 else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
277 str = "1Gbps ";
278
279 return str;
280}
281
fe2caefc
PP		 282static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
283{
284 int err_num = -EINVAL;
285
286 switch (cqe_status) {
287 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
288 err_num = -EPERM;
289 break;
290 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
291 err_num = -EINVAL;
292 break;
293 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
294 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
f11220ee 295 err_num = -EINVAL;
fe2caefc
PP		 296 break;
297 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
43a6b402 298 default:
f11220ee 299 err_num = -EINVAL;
fe2caefc
PP		 300 break;
301 }
302 return err_num;
303}
304
305void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
306 bool solicited, u16 cqe_popped)
307{
308 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
309
310 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
311 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
312
313 if (armed)
314 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
315 if (solicited)
316 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
317 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
318 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
319}
320
321static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
322{
323 u32 val = 0;
324
325 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
326 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
327 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
328}
329
330static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
331 bool arm, bool clear_int, u16 num_eqe)
332{
333 u32 val = 0;
334
335 val |= eq_id & OCRDMA_EQ_ID_MASK;
336 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
337 if (arm)
338 val |= (1 << OCRDMA_REARM_SHIFT);
339 if (clear_int)
340 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
341 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
342 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
343 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
344}
345
346static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
347 u8 opcode, u8 subsys, u32 cmd_len)
348{
349 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
350 cmd_hdr->timeout = 20; /* seconds */
351 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
352}
353
354static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
355{
356 struct ocrdma_mqe *mqe;
357
358 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
359 if (!mqe)
360 return NULL;
361 mqe->hdr.spcl_sge_cnt_emb |=
362 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
363 OCRDMA_MQE_HDR_EMB_MASK;
364 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
365
366 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
367 mqe->hdr.pyld_len);
368 return mqe;
369}
370
371static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
372{
373 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
374}
375
376static int ocrdma_alloc_q(struct ocrdma_dev *dev,
377 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
378{
379 memset(q, 0, sizeof(*q));
380 q->len = len;
381 q->entry_size = entry_size;
382 q->size = len * entry_size;
383 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
384 &q->dma, GFP_KERNEL);
385 if (!q->va)
386 return -ENOMEM;
387 memset(q->va, 0, q->size);
388 return 0;
389}
390
391static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
392 dma_addr_t host_pa, int hw_page_size)
393{
394 int i;
395
396 for (i = 0; i < cnt; i++) {
397 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
398 q_pa[i].hi = (u32) upper_32_bits(host_pa);
399 host_pa += hw_page_size;
400 }
401}
402
fad51b7d
DS		 403static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
404 struct ocrdma_queue_info *q, int queue_type)
fe2caefc
PP		 405{
406 u8 opcode = 0;
407 int status;
408 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
409
410 switch (queue_type) {
411 case QTYPE_MCCQ:
412 opcode = OCRDMA_CMD_DELETE_MQ;
413 break;
414 case QTYPE_CQ:
415 opcode = OCRDMA_CMD_DELETE_CQ;
416 break;
417 case QTYPE_EQ:
418 opcode = OCRDMA_CMD_DELETE_EQ;
419 break;
420 default:
421 BUG();
422 }
423 memset(cmd, 0, sizeof(*cmd));
424 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
425 cmd->id = q->id;
426
427 status = be_roce_mcc_cmd(dev->nic_info.netdev,
428 cmd, sizeof(*cmd), NULL, NULL);
429 if (!status)
430 q->created = false;
431 return status;
432}
433
434static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
435{
436 int status;
437 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
438 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
439
440 memset(cmd, 0, sizeof(*cmd));
441 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
442 sizeof(*cmd));
fe2caefc 443
c88bd03f 444 cmd->req.rsvd_version = 2;
fe2caefc
PP		 445 cmd->num_pages = 4;
446 cmd->valid = OCRDMA_CREATE_EQ_VALID;
447 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
448
449 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
450 PAGE_SIZE_4K);
451 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
452 NULL);
453 if (!status) {
454 eq->q.id = rsp->vector_eqid & 0xffff;
c88bd03f 455 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
fe2caefc
PP		 456 eq->q.created = true;
457 }
458 return status;
459}
460
461static int ocrdma_create_eq(struct ocrdma_dev *dev,
462 struct ocrdma_eq *eq, u16 q_len)
463{
464 int status;
465
466 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
467 sizeof(struct ocrdma_eqe));
468 if (status)
469 return status;
470
471 status = ocrdma_mbx_create_eq(dev, eq);
472 if (status)
473 goto mbx_err;
474 eq->dev = dev;
475 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
476
477 return 0;
478mbx_err:
479 ocrdma_free_q(dev, &eq->q);
480 return status;
481}
482
ea617626 483int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
fe2caefc
PP		 484{
485 int irq;
486
487 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
488 irq = dev->nic_info.pdev->irq;
489 else
490 irq = dev->nic_info.msix.vector_list[eq->vector];
491 return irq;
492}
493
494static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
495{
496 if (eq->q.created) {
497 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
fe2caefc
PP		 498 ocrdma_free_q(dev, &eq->q);
499 }
500}
501
502static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
503{
504 int irq;
505
506 /* disarm EQ so that interrupts are not generated
507 * during freeing and EQ delete is in progress.
508 */
509 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
510
511 irq = ocrdma_get_irq(dev, eq);
512 free_irq(irq, eq);
513 _ocrdma_destroy_eq(dev, eq);
514}
515
c88bd03f 516static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
fe2caefc
PP		 517{
518 int i;
519
fe2caefc 520 for (i = 0; i < dev->eq_cnt; i++)
c88bd03f 521 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
fe2caefc
PP		 522}
523
abe3afac
RD		 524static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
525 struct ocrdma_queue_info *cq,
526 struct ocrdma_queue_info *eq)
fe2caefc
PP		 527{
528 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
529 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
530 int status;
531
532 memset(cmd, 0, sizeof(*cmd));
533 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
534 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
535
1afc0454
NG		 536 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
537 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
538 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
539 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
540
fe2caefc 541 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1afc0454 542 cmd->eqn = eq->id;
8ac0c7c7 543 cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
fe2caefc 544
1afc0454 545 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
fe2caefc
PP		 546 cq->dma, PAGE_SIZE_4K);
547 status = be_roce_mcc_cmd(dev->nic_info.netdev,
548 cmd, sizeof(*cmd), NULL, NULL);
549 if (!status) {
1afc0454 550 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
fe2caefc
PP		 551 cq->created = true;
552 }
553 return status;
554}
555
556static u32 ocrdma_encoded_q_len(int q_len)
557{
558 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
559
560 if (len_encoded == 16)
561 len_encoded = 0;
562 return len_encoded;
563}
564
565static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
566 struct ocrdma_queue_info *mq,
567 struct ocrdma_queue_info *cq)
568{
569 int num_pages, status;
570 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
571 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
572 struct ocrdma_pa *pa;
573
574 memset(cmd, 0, sizeof(*cmd));
575 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
576
b1d58b99
NG		 577 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
578 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
579 cmd->req.rsvd_version = 1;
580 cmd->cqid_pages = num_pages;
581 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
582 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
84b105db 583
de123485
JS		 584 cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
585 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
10a214dc
DS		 586 /* Request link events on this MQ. */
587 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_LINK_EVE_CODE);
84b105db 588
b1d58b99
NG		 589 cmd->async_cqid_ringsize = cq->id;
590 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
591 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
592 cmd->valid = OCRDMA_CREATE_MQ_VALID;
593 pa = &cmd->pa[0];
594
fe2caefc
PP		 595 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
596 status = be_roce_mcc_cmd(dev->nic_info.netdev,
597 cmd, sizeof(*cmd), NULL, NULL);
598 if (!status) {
599 mq->id = rsp->id;
600 mq->created = true;
601 }
602 return status;
603}
604
605static int ocrdma_create_mq(struct ocrdma_dev *dev)
606{
607 int status;
608
609 /* Alloc completion queue for Mailbox queue */
610 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
611 sizeof(struct ocrdma_mcqe));
612 if (status)
613 goto alloc_err;
614
ea617626 615 dev->eq_tbl[0].cq_cnt++;
c88bd03f 616 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
fe2caefc
PP		 617 if (status)
618 goto mbx_cq_free;
619
620 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
621 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
622 mutex_init(&dev->mqe_ctx.lock);
623
624 /* Alloc Mailbox queue */
625 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
626 sizeof(struct ocrdma_mqe));
627 if (status)
628 goto mbx_cq_destroy;
629 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
630 if (status)
631 goto mbx_q_free;
632 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
633 return 0;
634
635mbx_q_free:
636 ocrdma_free_q(dev, &dev->mq.sq);
637mbx_cq_destroy:
638 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
639mbx_cq_free:
640 ocrdma_free_q(dev, &dev->mq.cq);
641alloc_err:
642 return status;
643}
644
645static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
646{
647 struct ocrdma_queue_info *mbxq, *cq;
648
649 /* mqe_ctx lock synchronizes with any other pending cmds. */
650 mutex_lock(&dev->mqe_ctx.lock);
651 mbxq = &dev->mq.sq;
652 if (mbxq->created) {
653 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
654 ocrdma_free_q(dev, mbxq);
655 }
656 mutex_unlock(&dev->mqe_ctx.lock);
657
658 cq = &dev->mq.cq;
659 if (cq->created) {
660 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
661 ocrdma_free_q(dev, cq);
662 }
663}
664
665static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
666 struct ocrdma_qp *qp)
667{
668 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
669 enum ib_qp_state old_ib_qps;
670
671 if (qp == NULL)
672 BUG();
057729cb 673 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
fe2caefc
PP		 674}
675
676static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
677 struct ocrdma_ae_mcqe *cqe)
678{
679 struct ocrdma_qp *qp = NULL;
680 struct ocrdma_cq *cq = NULL;
1b09a0c2 681 struct ib_event ib_evt;
fe2caefc
PP		 682 int cq_event = 0;
683 int qp_event = 1;
684 int srq_event = 0;
685 int dev_event = 0;
686 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
687 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
aeb922df
NI		 688 u16 qpid = cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK;
689 u16 cqid = cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK;
fe2caefc 690
aeb922df
NI		 691 /*
692 * Some FW version returns wrong qp or cq ids in CQEs.
693 * Checking whether the IDs are valid
694 */
695
696 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID) {
697 if (qpid < dev->attr.max_qp)
698 qp = dev->qp_tbl[qpid];
699 if (qp == NULL) {
700 pr_err("ocrdma%d:Async event - qpid %u is not valid\n",
701 dev->id, qpid);
702 return;
703 }
704 }
705
706 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID) {
707 if (cqid < dev->attr.max_cq)
708 cq = dev->cq_tbl[cqid];
709 if (cq == NULL) {
710 pr_err("ocrdma%d:Async event - cqid %u is not valid\n",
711 dev->id, cqid);
712 return;
713 }
714 }
fe2caefc 715
1b09a0c2
SX		 716 memset(&ib_evt, 0, sizeof(ib_evt));
717
e9db2953
RD		 718 ib_evt.device = &dev->ibdev;
719
fe2caefc
PP		 720 switch (type) {
721 case OCRDMA_CQ_ERROR:
722 ib_evt.element.cq = &cq->ibcq;
723 ib_evt.event = IB_EVENT_CQ_ERR;
724 cq_event = 1;
725 qp_event = 0;
726 break;
727 case OCRDMA_CQ_OVERRUN_ERROR:
728 ib_evt.element.cq = &cq->ibcq;
729 ib_evt.event = IB_EVENT_CQ_ERR;
1228056b
SX		 730 cq_event = 1;
731 qp_event = 0;
fe2caefc
PP		 732 break;
733 case OCRDMA_CQ_QPCAT_ERROR:
734 ib_evt.element.qp = &qp->ibqp;
735 ib_evt.event = IB_EVENT_QP_FATAL;
736 ocrdma_process_qpcat_error(dev, qp);
737 break;
738 case OCRDMA_QP_ACCESS_ERROR:
739 ib_evt.element.qp = &qp->ibqp;
740 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
741 break;
742 case OCRDMA_QP_COMM_EST_EVENT:
743 ib_evt.element.qp = &qp->ibqp;
744 ib_evt.event = IB_EVENT_COMM_EST;
745 break;
746 case OCRDMA_SQ_DRAINED_EVENT:
747 ib_evt.element.qp = &qp->ibqp;
748 ib_evt.event = IB_EVENT_SQ_DRAINED;
749 break;
750 case OCRDMA_DEVICE_FATAL_EVENT:
751 ib_evt.element.port_num = 1;
752 ib_evt.event = IB_EVENT_DEVICE_FATAL;
753 qp_event = 0;
754 dev_event = 1;
755 break;
756 case OCRDMA_SRQCAT_ERROR:
757 ib_evt.element.srq = &qp->srq->ibsrq;
758 ib_evt.event = IB_EVENT_SRQ_ERR;
759 srq_event = 1;
760 qp_event = 0;
761 break;
762 case OCRDMA_SRQ_LIMIT_EVENT:
763 ib_evt.element.srq = &qp->srq->ibsrq;
804eaf29 764 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
fe2caefc
PP		 765 srq_event = 1;
766 qp_event = 0;
767 break;
768 case OCRDMA_QP_LAST_WQE_EVENT:
769 ib_evt.element.qp = &qp->ibqp;
770 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
771 break;
772 default:
773 cq_event = 0;
774 qp_event = 0;
775 srq_event = 0;
776 dev_event = 0;
ef99c4c2 777 pr_err("%s() unknown type=0x%x\n", __func__, type);
fe2caefc
PP		 778 break;
779 }
780
ad56ebb4
SX		 781 if (type < OCRDMA_MAX_ASYNC_ERRORS)
782 atomic_inc(&dev->async_err_stats[type]);
783
fe2caefc
PP		 784 if (qp_event) {
785 if (qp->ibqp.event_handler)
786 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
787 } else if (cq_event) {
788 if (cq->ibcq.event_handler)
789 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
790 } else if (srq_event) {
791 if (qp->srq->ibsrq.event_handler)
792 qp->srq->ibsrq.event_handler(&ib_evt,
793 qp->srq->ibsrq.
794 srq_context);
f99b1649 795 } else if (dev_event) {
1228056b 796 pr_err("%s: Fatal event received\n", dev->ibdev.name);
fe2caefc 797 ib_dispatch_event(&ib_evt);
f99b1649 798 }
fe2caefc
PP		 799
800}
801
84b105db
NG		 802static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
803 struct ocrdma_ae_mcqe *cqe)
804{
805 struct ocrdma_ae_pvid_mcqe *evt;
806 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
807 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
808
809 switch (type) {
810 case OCRDMA_ASYNC_EVENT_PVID_STATE:
811 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
812 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
813 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
814 dev->pvid = ((evt->tag_enabled &
815 OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
816 OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
817 break;
31dbdd9a
SX		 818
819 case OCRDMA_ASYNC_EVENT_COS_VALUE:
820 atomic_set(&dev->update_sl, 1);
821 break;
84b105db
NG		 822 default:
823 /* Not interested evts. */
824 break;
825 }
826}
827
10a214dc
DS		 828static void ocrdma_process_link_state(struct ocrdma_dev *dev,
829 struct ocrdma_ae_mcqe *cqe)
830{
831 struct ocrdma_ae_lnkst_mcqe *evt;
832 u8 lstate;
833
834 evt = (struct ocrdma_ae_lnkst_mcqe *)cqe;
835 lstate = ocrdma_get_ae_link_state(evt->speed_state_ptn);
836
837 if (!(lstate & OCRDMA_AE_LSC_LLINK_MASK))
838 return;
839
840 if (dev->flags & OCRDMA_FLAGS_LINK_STATUS_INIT)
841 ocrdma_update_link_state(dev, (lstate & OCRDMA_LINK_ST_MASK));
842}
843
fe2caefc
PP		 844static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
845{
846 /* async CQE processing */
847 struct ocrdma_ae_mcqe *cqe = ae_cqe;
848 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
849 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
10a214dc
DS		 850 switch (evt_code) {
851 case OCRDMA_ASYNC_LINK_EVE_CODE:
852 ocrdma_process_link_state(dev, cqe);
853 break;
854 case OCRDMA_ASYNC_RDMA_EVE_CODE:
fe2caefc 855 ocrdma_dispatch_ibevent(dev, cqe);
10a214dc
DS		 856 break;
857 case OCRDMA_ASYNC_GRP5_EVE_CODE:
84b105db 858 ocrdma_process_grp5_aync(dev, cqe);
10a214dc
DS		 859 break;
860 default:
ef99c4c2
NG		 861 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
862 dev->id, evt_code);
10a214dc 863 }
fe2caefc
PP		 864}
865
866static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
867{
868 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
869 dev->mqe_ctx.cqe_status = (cqe->status &
870 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
871 dev->mqe_ctx.ext_status =
872 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
873 >> OCRDMA_MCQE_ESTATUS_SHIFT;
874 dev->mqe_ctx.cmd_done = true;
875 wake_up(&dev->mqe_ctx.cmd_wait);
876 } else
ef99c4c2
NG		 877 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
878 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
fe2caefc
PP		 879}
880
881static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
882{
883 u16 cqe_popped = 0;
884 struct ocrdma_mcqe *cqe;
885
886 while (1) {
887 cqe = ocrdma_get_mcqe(dev);
888 if (cqe == NULL)
889 break;
890 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
891 cqe_popped += 1;
892 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
893 ocrdma_process_acqe(dev, cqe);
894 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
895 ocrdma_process_mcqe(dev, cqe);
fe2caefc
PP		 896 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
897 ocrdma_mcq_inc_tail(dev);
898 }
899 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
900 return 0;
901}
902
043e9dee
SX		 903static struct ocrdma_cq *_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
904 struct ocrdma_cq *cq, bool sq)
fe2caefc 905{
fe2caefc 906 struct ocrdma_qp *qp;
043e9dee
SX		 907 struct list_head *cur;
908 struct ocrdma_cq *bcq = NULL;
909 struct list_head *head = sq?(&cq->sq_head):(&cq->rq_head);
910
911 list_for_each(cur, head) {
912 if (sq)
913 qp = list_entry(cur, struct ocrdma_qp, sq_entry);
914 else
915 qp = list_entry(cur, struct ocrdma_qp, rq_entry);
916
fe2caefc
PP		 917 if (qp->srq)
918 continue;
919 /* if wq and rq share the same cq, than comp_handler
920 * is already invoked.
921 */
922 if (qp->sq_cq == qp->rq_cq)
923 continue;
924 /* if completion came on sq, rq's cq is buddy cq.
925 * if completion came on rq, sq's cq is buddy cq.
926 */
927 if (qp->sq_cq == cq)
043e9dee 928 bcq = qp->rq_cq;
fe2caefc 929 else
043e9dee
SX		 930 bcq = qp->sq_cq;
931 return bcq;
fe2caefc 932 }
043e9dee
SX		 933 return NULL;
934}
935
936static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
937 struct ocrdma_cq *cq)
938{
939 unsigned long flags;
940 struct ocrdma_cq *bcq = NULL;
941
942 /* Go through list of QPs in error state which are using this CQ
943 * and invoke its callback handler to trigger CQE processing for
944 * error/flushed CQE. It is rare to find more than few entries in
945 * this list as most consumers stops after getting error CQE.
946 * List is traversed only once when a matching buddy cq found for a QP.
947 */
948 spin_lock_irqsave(&dev->flush_q_lock, flags);
949 /* Check if buddy CQ is present.
950 * true - Check for SQ CQ
951 * false - Check for RQ CQ
952 */
953 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, true);
954 if (bcq == NULL)
955 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, false);
fe2caefc 956 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
043e9dee
SX		 957
958 /* if there is valid buddy cq, look for its completion handler */
959 if (bcq && bcq->ibcq.comp_handler) {
960 spin_lock_irqsave(&bcq->comp_handler_lock, flags);
961 (*bcq->ibcq.comp_handler) (&bcq->ibcq, bcq->ibcq.cq_context);
962 spin_unlock_irqrestore(&bcq->comp_handler_lock, flags);
fe2caefc
PP		 963 }
964}
965
966static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
967{
968 unsigned long flags;
969 struct ocrdma_cq *cq;
970
971 if (cq_idx >= OCRDMA_MAX_CQ)
972 BUG();
973
974 cq = dev->cq_tbl[cq_idx];
ea617626 975 if (cq == NULL)
fe2caefc 976 return;
fe2caefc
PP		 977
978 if (cq->ibcq.comp_handler) {
979 spin_lock_irqsave(&cq->comp_handler_lock, flags);
980 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
981 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
982 }
983 ocrdma_qp_buddy_cq_handler(dev, cq);
984}
985
986static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
987{
988 /* process the MQ-CQE. */
989 if (cq_id == dev->mq.cq.id)
990 ocrdma_mq_cq_handler(dev, cq_id);
991 else
992 ocrdma_qp_cq_handler(dev, cq_id);
993}
994
995static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
996{
997 struct ocrdma_eq *eq = handle;
998 struct ocrdma_dev *dev = eq->dev;
999 struct ocrdma_eqe eqe;
1000 struct ocrdma_eqe *ptr;
fe2caefc 1001 u16 cq_id;
5e6f9237 1002 u8 mcode;
ea617626
DS		 1003 int budget = eq->cq_cnt;
1004
1005 do {
fe2caefc
PP		 1006 ptr = ocrdma_get_eqe(eq);
1007 eqe = *ptr;
1008 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
5e6f9237
DS		 1009 mcode = (eqe.id_valid & OCRDMA_EQE_MAJOR_CODE_MASK)
1010 >> OCRDMA_EQE_MAJOR_CODE_SHIFT;
1011 if (mcode == OCRDMA_MAJOR_CODE_SENTINAL)
1012 pr_err("EQ full on eqid = 0x%x, eqe = 0x%x\n",
1013 eq->q.id, eqe.id_valid);
fe2caefc
PP		 1014 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
1015 break;
ea617626 1016
fe2caefc 1017 ptr->id_valid = 0;
ea617626
DS		 1018 /* ring eq doorbell as soon as its consumed. */
1019 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
fe2caefc
PP		 1020 /* check whether its CQE or not. */
1021 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
1022 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
1023 ocrdma_cq_handler(dev, cq_id);
1024 }
1025 ocrdma_eq_inc_tail(eq);
ea617626
DS		 1026
1027 /* There can be a stale EQE after the last bound CQ is
1028 * destroyed. EQE valid and budget == 0 implies this.
1029 */
1030 if (budget)
1031 budget--;
1032
1033 } while (budget);
1034
b4dbe8d5 1035 eq->aic_obj.eq_intr_cnt++;
ea617626 1036 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
fe2caefc
PP		 1037 return IRQ_HANDLED;
1038}
1039
1040static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
1041{
1042 struct ocrdma_mqe *mqe;
1043
1044 dev->mqe_ctx.tag = dev->mq.sq.head;
1045 dev->mqe_ctx.cmd_done = false;
1046 mqe = ocrdma_get_mqe(dev);
1047 cmd->hdr.tag_lo = dev->mq.sq.head;
1048 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
1049 /* make sure descriptor is written before ringing doorbell */
1050 wmb();
1051 ocrdma_mq_inc_head(dev);
1052 ocrdma_ring_mq_db(dev);
1053}
1054
1055static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
1056{
1057 long status;
1058 /* 30 sec timeout */
1059 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
1060 (dev->mqe_ctx.cmd_done != false),
1061 msecs_to_jiffies(30000));
1062 if (status)
1063 return 0;
6dab0264
MA		 1064 else {
1065 dev->mqe_ctx.fw_error_state = true;
1066 pr_err("%s(%d) mailbox timeout: fw not responding\n",
1067 __func__, dev->id);
fe2caefc 1068 return -1;
6dab0264 1069 }
fe2caefc
PP		 1070}
1071
1072/* issue a mailbox command on the MQ */
1073static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
1074{
1075 int status = 0;
1076 u16 cqe_status, ext_status;
bbc5ec52
SX		 1077 struct ocrdma_mqe *rsp_mqe;
1078 struct ocrdma_mbx_rsp *rsp = NULL;
fe2caefc
PP		 1079
1080 mutex_lock(&dev->mqe_ctx.lock);
6dab0264
MA		 1081 if (dev->mqe_ctx.fw_error_state)
1082 goto mbx_err;
fe2caefc
PP		 1083 ocrdma_post_mqe(dev, mqe);
1084 status = ocrdma_wait_mqe_cmpl(dev);
1085 if (status)
1086 goto mbx_err;
1087 cqe_status = dev->mqe_ctx.cqe_status;
1088 ext_status = dev->mqe_ctx.ext_status;
bbc5ec52
SX		 1089 rsp_mqe = ocrdma_get_mqe_rsp(dev);
1090 ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
1091 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1092 OCRDMA_MQE_HDR_EMB_SHIFT)
1093 rsp = &mqe->u.rsp;
1094
fe2caefc 1095 if (cqe_status || ext_status) {
bbc5ec52
SX		 1096 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1097 __func__, cqe_status, ext_status);
1098 if (rsp) {
1099 /* This is for embedded cmds. */
1100 pr_err("opcode=0x%x, subsystem=0x%x\n",
1101 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1102 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1103 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1104 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1105 }
fe2caefc
PP		 1106 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1107 goto mbx_err;
1108 }
bbc5ec52
SX		 1109 /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1110 if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
fe2caefc
PP		 1111 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1112mbx_err:
1113 mutex_unlock(&dev->mqe_ctx.lock);
1114 return status;
1115}
1116
bbc5ec52
SX		 1117static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1118 void *payload_va)
1119{
0ca4c39f 1120 int status;
bbc5ec52
SX		 1121 struct ocrdma_mbx_rsp *rsp = payload_va;
1122
1123 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1124 OCRDMA_MQE_HDR_EMB_SHIFT)
1125 BUG();
1126
1127 status = ocrdma_mbx_cmd(dev, mqe);
1128 if (!status)
1129 /* For non embedded, only CQE failures are handled in
1130 * ocrdma_mbx_cmd. We need to check for RSP errors.
1131 */
1132 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1133 status = ocrdma_get_mbx_errno(rsp->status);
1134
1135 if (status)
1136 pr_err("opcode=0x%x, subsystem=0x%x\n",
1137 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1138 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1139 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1140 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1141 return status;
1142}
1143
fe2caefc
PP		 1144static void ocrdma_get_attr(struct ocrdma_dev *dev,
1145 struct ocrdma_dev_attr *attr,
1146 struct ocrdma_mbx_query_config *rsp)
1147{
fe2caefc
PP		 1148 attr->max_pd =
1149 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1150 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
e1614869
SK		 1151 attr->udp_encap = (rsp->max_pd_ca_ack_delay &
1152 OCRDMA_MBX_QUERY_CFG_L3_TYPE_MASK) >>
1153 OCRDMA_MBX_QUERY_CFG_L3_TYPE_SHIFT;
9ba1377d
MA		 1154 attr->max_dpp_pds =
1155 (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >>
1156 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET;
fe2caefc
PP		 1157 attr->max_qp =
1158 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1159 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
fad51b7d
DS		 1160 attr->max_srq =
1161 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1162 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
3c199b45 1163 attr->max_send_sge = ((rsp->max_recv_send_sge &
fe2caefc
PP		 1164 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1165 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
3c199b45
SX		 1166 attr->max_recv_sge = (rsp->max_recv_send_sge &
1167 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_MASK) >>
1168 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT;
634c5796
MV		 1169 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1170 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1171 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
3c199b45
SX		 1172 attr->max_rdma_sge = (rsp->max_wr_rd_sge &
1173 OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_MASK) >>
1174 OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_SHIFT;
fe2caefc
PP		 1175 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1176 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1177 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1178 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1179 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1180 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1181 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1182 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1183 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1184 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1185 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1186 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1187 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1188 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1189 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
ac578aef 1190 attr->max_mw = rsp->max_mw;
fe2caefc 1191 attr->max_mr = rsp->max_mr;
033edd4d
MA		 1192 attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1193 rsp->max_mr_size_lo;
fe2caefc
PP		 1194 attr->max_fmr = 0;
1195 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1196 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1197 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1198 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
c43e9ab8
NG		 1199 attr->max_cq = (rsp->max_cq_cqes_per_cq &
1200 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1201 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
fe2caefc
PP		 1202 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1203 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1204 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1205 OCRDMA_WQE_STRIDE;
1206 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1207 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1208 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1209 OCRDMA_WQE_STRIDE;
1210 attr->max_inline_data =
1211 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1212 sizeof(struct ocrdma_sge));
21c3391a 1213 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
fe2caefc
PP		 1214 attr->ird = 1;
1215 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1216 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
07bb5424
MV		 1217 }
1218 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1219 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1220 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1221 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
fe2caefc
PP		 1222}
1223
1224static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1225 struct ocrdma_fw_conf_rsp *conf)
1226{
1227 u32 fn_mode;
1228
1229 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1230 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1231 return -EINVAL;
1232 dev->base_eqid = conf->base_eqid;
1233 dev->max_eq = conf->max_eq;
fe2caefc
PP		 1234 return 0;
1235}
1236
1237/* can be issued only during init time. */
1238static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1239{
1240 int status = -ENOMEM;
1241 struct ocrdma_mqe *cmd;
1242 struct ocrdma_fw_ver_rsp *rsp;
1243
1244 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1245 if (!cmd)
1246 return -ENOMEM;
1247 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1248 OCRDMA_CMD_GET_FW_VER,
1249 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1250
1251 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1252 if (status)
1253 goto mbx_err;
1254 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1255 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1256 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1257 sizeof(rsp->running_ver));
1258 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1259mbx_err:
1260 kfree(cmd);
1261 return status;
1262}
1263
1264/* can be issued only during init time. */
1265static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1266{
1267 int status = -ENOMEM;
1268 struct ocrdma_mqe *cmd;
1269 struct ocrdma_fw_conf_rsp *rsp;
1270
1271 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1272 if (!cmd)
1273 return -ENOMEM;
1274 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1275 OCRDMA_CMD_GET_FW_CONFIG,
1276 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1277 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1278 if (status)
1279 goto mbx_err;
1280 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1281 status = ocrdma_check_fw_config(dev, rsp);
1282mbx_err:
1283 kfree(cmd);
1284 return status;
1285}
1286
a51f06e1
SX		 1287int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1288{
1289 struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1290 struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
beb9b703 1291 struct ocrdma_rdma_stats_resp *old_stats;
a51f06e1
SX		 1292 int status;
1293
beb9b703 1294 old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
a51f06e1
SX		 1295 if (old_stats == NULL)
1296 return -ENOMEM;
1297
1298 memset(mqe, 0, sizeof(*mqe));
1299 mqe->hdr.pyld_len = dev->stats_mem.size;
1300 mqe->hdr.spcl_sge_cnt_emb |=
1301 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1302 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1303 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1304 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1305 mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1306
1307 /* Cache the old stats */
1308 memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1309 memset(req, 0, dev->stats_mem.size);
1310
1311 ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1312 OCRDMA_CMD_GET_RDMA_STATS,
1313 OCRDMA_SUBSYS_ROCE,
1314 dev->stats_mem.size);
1315 if (reset)
1316 req->reset_stats = reset;
1317
1318 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1319 if (status)
1320 /* Copy from cache, if mbox fails */
1321 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1322 else
1323 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1324
1325 kfree(old_stats);
1326 return status;
1327}
1328
1329static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1330{
1331 int status = -ENOMEM;
1332 struct ocrdma_dma_mem dma;
1333 struct ocrdma_mqe *mqe;
1334 struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1335 struct mgmt_hba_attribs *hba_attribs;
1336
beb9b703 1337 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
a51f06e1
SX		 1338 if (!mqe)
1339 return status;
a51f06e1
SX		 1340
1341 dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1342 dma.va = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1343 dma.size, &dma.pa, GFP_KERNEL);
1344 if (!dma.va)
1345 goto free_mqe;
1346
1347 mqe->hdr.pyld_len = dma.size;
1348 mqe->hdr.spcl_sge_cnt_emb |=
1349 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1350 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1351 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1352 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1353 mqe->u.nonemb_req.sge[0].len = dma.size;
1354
1355 memset(dma.va, 0, dma.size);
1356 ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1357 OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1358 OCRDMA_SUBSYS_COMMON,
1359 dma.size);
1360
1361 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1362 if (!status) {
1363 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1364 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1365
8ac0c7c7
DS		 1366 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1367 OCRDMA_HBA_ATTRB_PTNUM_MASK)
1368 >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
a51f06e1
SX		 1369 strncpy(dev->model_number,
1370 hba_attribs->controller_model_number, 31);
1371 }
1372 dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1373free_mqe:
1374 kfree(mqe);
1375 return status;
1376}
1377
fe2caefc
PP		 1378static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1379{
1380 int status = -ENOMEM;
1381 struct ocrdma_mbx_query_config *rsp;
1382 struct ocrdma_mqe *cmd;
1383
1384 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1385 if (!cmd)
1386 return status;
1387 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1388 if (status)
1389 goto mbx_err;
1390 rsp = (struct ocrdma_mbx_query_config *)cmd;
1391 ocrdma_get_attr(dev, &dev->attr, rsp);
1392mbx_err:
1393 kfree(cmd);
1394 return status;
1395}
1396
10a214dc
DS		 1397int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed,
1398 u8 *lnk_state)
f24ceba6
NG		 1399{
1400 int status = -ENOMEM;
1401 struct ocrdma_get_link_speed_rsp *rsp;
1402 struct ocrdma_mqe *cmd;
1403
1404 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1405 sizeof(*cmd));
1406 if (!cmd)
1407 return status;
1408 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1409 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1410 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1411
1412 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1413
1414 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1415 if (status)
1416 goto mbx_err;
1417
1418 rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
10a214dc
DS		 1419 if (lnk_speed)
1420 *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1421 >> OCRDMA_PHY_PS_SHIFT;
1422 if (lnk_state)
1423 *lnk_state = (rsp->res_lnk_st & OCRDMA_LINK_ST_MASK);
f24ceba6
NG		 1424
1425mbx_err:
1426 kfree(cmd);
1427 return status;
1428}
1429
a51f06e1
SX		 1430static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1431{
1432 int status = -ENOMEM;
1433 struct ocrdma_mqe *cmd;
1434 struct ocrdma_get_phy_info_rsp *rsp;
1435
1436 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1437 if (!cmd)
1438 return status;
1439
1440 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1441 OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1442 sizeof(*cmd));
1443
1444 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1445 if (status)
1446 goto mbx_err;
1447
1448 rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
8ac0c7c7
DS		 1449 dev->phy.phy_type =
1450 (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1451 dev->phy.interface_type =
1452 (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1453 >> OCRDMA_IF_TYPE_SHIFT;
a51f06e1 1454 dev->phy.auto_speeds_supported =
8ac0c7c7 1455 (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
a51f06e1 1456 dev->phy.fixed_speeds_supported =
8ac0c7c7
DS		 1457 (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1458 >> OCRDMA_FSPEED_SUPP_SHIFT;
a51f06e1
SX		 1459mbx_err:
1460 kfree(cmd);
1461 return status;
1462}
1463
fe2caefc
PP		 1464int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1465{
1466 int status = -ENOMEM;
1467 struct ocrdma_alloc_pd *cmd;
1468 struct ocrdma_alloc_pd_rsp *rsp;
1469
1470 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1471 if (!cmd)
1472 return status;
1473 if (pd->dpp_enabled)
1474 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1475 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1476 if (status)
1477 goto mbx_err;
1478 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1479 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1480 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1481 pd->dpp_enabled = true;
1482 pd->dpp_page = rsp->dpp_page_pdid >>
1483 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1484 } else {
1485 pd->dpp_enabled = false;
1486 pd->num_dpp_qp = 0;
1487 }
1488mbx_err:
1489 kfree(cmd);
1490 return status;
1491}
1492
1493int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1494{
1495 int status = -ENOMEM;
1496 struct ocrdma_dealloc_pd *cmd;
1497
1498 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1499 if (!cmd)
1500 return status;
1501 cmd->id = pd->id;
1502 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1503 kfree(cmd);
1504 return status;
1505}
1506
9ba1377d
MA		 1507
1508static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev)
1509{
1510 int status = -ENOMEM;
1511 size_t pd_bitmap_size;
1512 struct ocrdma_alloc_pd_range *cmd;
1513 struct ocrdma_alloc_pd_range_rsp *rsp;
1514
1515 /* Pre allocate the DPP PDs */
59582d86
MA		 1516 if (dev->attr.max_dpp_pds) {
1517 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE,
1518 sizeof(*cmd));
1519 if (!cmd)
1520 return -ENOMEM;
1521 cmd->pd_count = dev->attr.max_dpp_pds;
1522 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1523 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1524 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1525
1526 if (!status && (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) &&
1527 rsp->pd_count) {
1528 dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >>
1529 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1530 dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid &
1531 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1532 dev->pd_mgr->max_dpp_pd = rsp->pd_count;
1533 pd_bitmap_size =
1534 BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1535 dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size,
1536 GFP_KERNEL);
1537 }
1538 kfree(cmd);
9ba1377d 1539 }
9ba1377d
MA		 1540
1541 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1542 if (!cmd)
1543 return -ENOMEM;
1544
1545 cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds;
1546 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
9ba1377d 1547 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
59582d86 1548 if (!status && rsp->pd_count) {
9ba1377d
MA		 1549 dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid &
1550 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1551 dev->pd_mgr->max_normal_pd = rsp->pd_count;
1552 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1553 dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size,
1554 GFP_KERNEL);
1555 }
59582d86 1556 kfree(cmd);
9ba1377d
MA		 1557
1558 if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) {
1559 /* Enable PD resource manager */
1560 dev->pd_mgr->pd_prealloc_valid = true;
59582d86 1561 return 0;
9ba1377d 1562 }
9ba1377d
MA		 1563 return status;
1564}
1565
1566static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev)
1567{
1568 struct ocrdma_dealloc_pd_range *cmd;
1569
1570 /* return normal PDs to firmware */
1571 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd));
1572 if (!cmd)
1573 goto mbx_err;
1574
1575 if (dev->pd_mgr->max_normal_pd) {
1576 cmd->start_pd_id = dev->pd_mgr->pd_norm_start;
1577 cmd->pd_count = dev->pd_mgr->max_normal_pd;
1578 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1579 }
1580
1581 if (dev->pd_mgr->max_dpp_pd) {
1582 kfree(cmd);
1583 /* return DPP PDs to firmware */
1584 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE,
1585 sizeof(*cmd));
1586 if (!cmd)
1587 goto mbx_err;
1588
1589 cmd->start_pd_id = dev->pd_mgr->pd_dpp_start;
1590 cmd->pd_count = dev->pd_mgr->max_dpp_pd;
1591 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1592 }
1593mbx_err:
1594 kfree(cmd);
1595}
1596
1597void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1598{
1599 int status;
1600
1601 dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1602 GFP_KERNEL);
740c330e 1603 if (!dev->pd_mgr)
9ba1377d 1604 return;
740c330e 1605
9ba1377d
MA		 1606 status = ocrdma_mbx_alloc_pd_range(dev);
1607 if (status) {
1608 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1609 __func__, dev->id);
1610 }
1611}
1612
1613static void ocrdma_free_pd_pool(struct ocrdma_dev *dev)
1614{
1615 ocrdma_mbx_dealloc_pd_range(dev);
1616 kfree(dev->pd_mgr->pd_norm_bitmap);
1617 kfree(dev->pd_mgr->pd_dpp_bitmap);
1618 kfree(dev->pd_mgr);
1619}
1620
fe2caefc
PP		 1621static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1622 int *num_pages, int *page_size)
1623{
1624 int i;
1625 int mem_size;
1626
1627 *num_entries = roundup_pow_of_two(*num_entries);
1628 mem_size = *num_entries * entry_size;
1629 /* find the possible lowest possible multiplier */
1630 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1631 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1632 break;
1633 }
1634 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1635 return -EINVAL;
1636 mem_size = roundup(mem_size,
1637 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1638 *num_pages =
1639 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1640 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1641 *num_entries = mem_size / entry_size;
1642 return 0;
1643}
1644
1645static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1646{
fad51b7d 1647 int i;
5b4c9cd7 1648 int status = -ENOMEM;
fe2caefc
PP		 1649 int max_ah;
1650 struct ocrdma_create_ah_tbl *cmd;
1651 struct ocrdma_create_ah_tbl_rsp *rsp;
1652 struct pci_dev *pdev = dev->nic_info.pdev;
1653 dma_addr_t pa;
1654 struct ocrdma_pbe *pbes;
1655
1656 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1657 if (!cmd)
1658 return status;
1659
1660 max_ah = OCRDMA_MAX_AH;
1661 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1662
1663 /* number of PBEs in PBL */
1664 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1665 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1666 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1667
1668 /* page size */
1669 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1670 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1671 break;
1672 }
1673 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1674 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1675
1676 /* ah_entry size */
1677 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1678 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1679 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1680
1681 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1682 &dev->av_tbl.pbl.pa,
1683 GFP_KERNEL);
1684 if (dev->av_tbl.pbl.va == NULL)
1685 goto mem_err;
1686
1687 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1688 &pa, GFP_KERNEL);
1689 if (dev->av_tbl.va == NULL)
1690 goto mem_err_ah;
1691 dev->av_tbl.pa = pa;
1692 dev->av_tbl.num_ah = max_ah;
1693 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1694
1695 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1696 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
8ac0c7c7
DS		 1697 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1698 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
fe2caefc
PP		 1699 pa += PAGE_SIZE;
1700 }
1701 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1702 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1703 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1704 if (status)
1705 goto mbx_err;
1706 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1707 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1708 kfree(cmd);
1709 return 0;
1710
1711mbx_err:
1712 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1713 dev->av_tbl.pa);
1714 dev->av_tbl.va = NULL;
1715mem_err_ah:
1716 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1717 dev->av_tbl.pbl.pa);
1718 dev->av_tbl.pbl.va = NULL;
1719 dev->av_tbl.size = 0;
1720mem_err:
1721 kfree(cmd);
1722 return status;
1723}
1724
1725static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1726{
1727 struct ocrdma_delete_ah_tbl *cmd;
1728 struct pci_dev *pdev = dev->nic_info.pdev;
1729
1730 if (dev->av_tbl.va == NULL)
1731 return;
1732
1733 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1734 if (!cmd)
1735 return;
1736 cmd->ahid = dev->av_tbl.ahid;
1737
1738 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1739 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1740 dev->av_tbl.pa);
daac9681 1741 dev->av_tbl.va = NULL;
fe2caefc
PP		 1742 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1743 dev->av_tbl.pbl.pa);
1744 kfree(cmd);
1745}
1746
1747/* Multiple CQs uses the EQ. This routine returns least used
1748 * EQ to associate with CQ. This will distributes the interrupt
1749 * processing and CPU load to associated EQ, vector and so to that CPU.
1750 */
1751static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1752{
1753 int i, selected_eq = 0, cq_cnt = 0;
1754 u16 eq_id;
1755
1756 mutex_lock(&dev->dev_lock);
c88bd03f
NG		 1757 cq_cnt = dev->eq_tbl[0].cq_cnt;
1758 eq_id = dev->eq_tbl[0].q.id;
fe2caefc
PP		 1759 /* find the EQ which is has the least number of
1760 * CQs associated with it.
1761 */
1762 for (i = 0; i < dev->eq_cnt; i++) {
c88bd03f
NG		 1763 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1764 cq_cnt = dev->eq_tbl[i].cq_cnt;
1765 eq_id = dev->eq_tbl[i].q.id;
fe2caefc
PP		 1766 selected_eq = i;
1767 }
1768 }
c88bd03f 1769 dev->eq_tbl[selected_eq].cq_cnt += 1;
fe2caefc
PP		 1770 mutex_unlock(&dev->dev_lock);
1771 return eq_id;
1772}
1773
1774static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1775{
1776 int i;
1777
1778 mutex_lock(&dev->dev_lock);
ea617626
DS		 1779 i = ocrdma_get_eq_table_index(dev, eq_id);
1780 if (i == -EINVAL)
1781 BUG();
1782 dev->eq_tbl[i].cq_cnt -= 1;
fe2caefc
PP		 1783 mutex_unlock(&dev->dev_lock);
1784}
1785
1786int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
cffce990 1787 int entries, int dpp_cq, u16 pd_id)
fe2caefc
PP		 1788{
1789 int status = -ENOMEM; int max_hw_cqe;
1790 struct pci_dev *pdev = dev->nic_info.pdev;
1791 struct ocrdma_create_cq *cmd;
1792 struct ocrdma_create_cq_rsp *rsp;
1793 u32 hw_pages, cqe_size, page_size, cqe_count;
1794
fe2caefc 1795 if (entries > dev->attr.max_cqe) {
ef99c4c2
NG		 1796 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1797 __func__, dev->id, dev->attr.max_cqe, entries);
fe2caefc
PP		 1798 return -EINVAL;
1799 }
21c3391a 1800 if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
fe2caefc
PP		 1801 return -EINVAL;
1802
1803 if (dpp_cq) {
1804 cq->max_hw_cqe = 1;
1805 max_hw_cqe = 1;
1806 cqe_size = OCRDMA_DPP_CQE_SIZE;
1807 hw_pages = 1;
1808 } else {
1809 cq->max_hw_cqe = dev->attr.max_cqe;
1810 max_hw_cqe = dev->attr.max_cqe;
1811 cqe_size = sizeof(struct ocrdma_cqe);
1812 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1813 }
1814
1815 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1816
1817 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1818 if (!cmd)
1819 return -ENOMEM;
1820 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1821 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1822 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1823 if (!cq->va) {
1824 status = -ENOMEM;
1825 goto mem_err;
1826 }
1827 memset(cq->va, 0, cq->len);
1828 page_size = cq->len / hw_pages;
1829 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1830 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1831 cmd->cmd.pgsz_pgcnt |= hw_pages;
1832 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1833
fe2caefc 1834 cq->eqn = ocrdma_bind_eq(dev);
cffce990 1835 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
fe2caefc 1836 cqe_count = cq->len / cqe_size;
ea617626 1837 cq->cqe_cnt = cqe_count;
f99b1649 1838 if (cqe_count > 1024) {
fe2caefc
PP		 1839 /* Set cnt to 3 to indicate more than 1024 cq entries */
1840 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
f99b1649 1841 } else {
fe2caefc
PP		 1842 u8 count = 0;
1843 switch (cqe_count) {
1844 case 256:
1845 count = 0;
1846 break;
1847 case 512:
1848 count = 1;
1849 break;
1850 case 1024:
1851 count = 2;
1852 break;
1853 default:
1854 goto mbx_err;
1855 }
1856 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1857 }
1858 /* shared eq between all the consumer cqs. */
1859 cmd->cmd.eqn = cq->eqn;
21c3391a 1860 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
fe2caefc
PP		 1861 if (dpp_cq)
1862 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1863 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1864 cq->phase_change = false;
8ac0c7c7 1865 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
fe2caefc 1866 } else {
8ac0c7c7 1867 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
fe2caefc
PP		 1868 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1869 cq->phase_change = true;
1870 }
1871
8ac0c7c7
DS		 1872 /* pd_id valid only for v3 */
1873 cmd->cmd.pdid_cqecnt |= (pd_id <<
1874 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
fe2caefc
PP		 1875 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1876 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1877 if (status)
1878 goto mbx_err;
1879
1880 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1881 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1882 kfree(cmd);
1883 return 0;
1884mbx_err:
1885 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc
PP		 1886 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1887mem_err:
1888 kfree(cmd);
1889 return status;
1890}
1891
1892int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1893{
1894 int status = -ENOMEM;
1895 struct ocrdma_destroy_cq *cmd;
1896
1897 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1898 if (!cmd)
1899 return status;
1900 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1901 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1902
1903 cmd->bypass_flush_qid |=
1904 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1905 OCRDMA_DESTROY_CQ_QID_MASK;
1906
fe2caefc 1907 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
ea617626 1908 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc 1909 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
fe2caefc
PP		 1910 kfree(cmd);
1911 return status;
1912}
1913
1914int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1915 u32 pdid, int addr_check)
1916{
1917 int status = -ENOMEM;
1918 struct ocrdma_alloc_lkey *cmd;
1919 struct ocrdma_alloc_lkey_rsp *rsp;
1920
1921 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1922 if (!cmd)
1923 return status;
1924 cmd->pdid = pdid;
1925 cmd->pbl_sz_flags |= addr_check;
1926 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1927 cmd->pbl_sz_flags |=
1928 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1929 cmd->pbl_sz_flags |=
1930 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1931 cmd->pbl_sz_flags |=
1932 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1933 cmd->pbl_sz_flags |=
1934 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1935 cmd->pbl_sz_flags |=
1936 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1937
1938 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1939 if (status)
1940 goto mbx_err;
1941 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1942 hwmr->lkey = rsp->lrkey;
1943mbx_err:
1944 kfree(cmd);
1945 return status;
1946}
1947
1948int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1949{
1950 int status = -ENOMEM;
1951 struct ocrdma_dealloc_lkey *cmd;
1952
1953 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1954 if (!cmd)
1955 return -ENOMEM;
1956 cmd->lkey = lkey;
1957 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1958 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1959 if (status)
1960 goto mbx_err;
1961mbx_err:
1962 kfree(cmd);
1963 return status;
1964}
1965
1966static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1967 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1968{
1969 int status = -ENOMEM;
1970 int i;
1971 struct ocrdma_reg_nsmr *cmd;
1972 struct ocrdma_reg_nsmr_rsp *rsp;
1973
1974 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1975 if (!cmd)
1976 return -ENOMEM;
1977 cmd->num_pbl_pdid =
1978 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
2b51a9b9 1979 cmd->fr_mr = hwmr->fr_mr;
fe2caefc
PP		 1980
1981 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1982 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1983 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1984 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1985 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1986 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1987 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1988 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1989 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1990 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1991 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1992
1993 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1994 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1995 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1996 cmd->totlen_low = hwmr->len;
1997 cmd->totlen_high = upper_32_bits(hwmr->len);
1998 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1999 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
2000 cmd->va_loaddr = (u32) hwmr->va;
2001 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
2002
2003 for (i = 0; i < pbl_cnt; i++) {
2004 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
2005 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
2006 }
2007 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2008 if (status)
2009 goto mbx_err;
2010 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
2011 hwmr->lkey = rsp->lrkey;
2012mbx_err:
2013 kfree(cmd);
2014 return status;
2015}
2016
2017static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
2018 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
2019 u32 pbl_offset, u32 last)
2020{
2021 int status = -ENOMEM;
2022 int i;
2023 struct ocrdma_reg_nsmr_cont *cmd;
2024
2025 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
2026 if (!cmd)
2027 return -ENOMEM;
2028 cmd->lrkey = hwmr->lkey;
2029 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
2030 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
2031 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
2032
2033 for (i = 0; i < pbl_cnt; i++) {
2034 cmd->pbl[i].lo =
2035 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
2036 cmd->pbl[i].hi =
2037 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
2038 }
2039 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2040 if (status)
2041 goto mbx_err;
2042mbx_err:
2043 kfree(cmd);
2044 return status;
2045}
2046
2047int ocrdma_reg_mr(struct ocrdma_dev *dev,
2048 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
2049{
2050 int status;
2051 u32 last = 0;
2052 u32 cur_pbl_cnt, pbl_offset;
2053 u32 pending_pbl_cnt = hwmr->num_pbls;
2054
2055 pbl_offset = 0;
2056 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2057 if (cur_pbl_cnt == pending_pbl_cnt)
2058 last = 1;
2059
2060 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
2061 cur_pbl_cnt, hwmr->pbe_size, last);
2062 if (status) {
ef99c4c2 2063 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 2064 return status;
2065 }
2066 /* if there is no more pbls to register then exit. */
2067 if (last)
2068 return 0;
2069
2070 while (!last) {
2071 pbl_offset += cur_pbl_cnt;
2072 pending_pbl_cnt -= cur_pbl_cnt;
2073 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2074 /* if we reach the end of the pbls, then need to set the last
2075 * bit, indicating no more pbls to register for this memory key.
2076 */
2077 if (cur_pbl_cnt == pending_pbl_cnt)
2078 last = 1;
2079
2080 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
2081 pbl_offset, last);
2082 if (status)
2083 break;
2084 }
2085 if (status)
ef99c4c2 2086 pr_err("%s() err. status=%d\n", __func__, status);
fe2caefc
PP		 2087
2088 return status;
2089}
2090
2091bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2092{
2093 struct ocrdma_qp *tmp;
2094 bool found = false;
2095 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
2096 if (qp == tmp) {
2097 found = true;
2098 break;
2099 }
2100 }
2101 return found;
2102}
2103
2104bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2105{
2106 struct ocrdma_qp *tmp;
2107 bool found = false;
2108 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
2109 if (qp == tmp) {
2110 found = true;
2111 break;
2112 }
2113 }
2114 return found;
2115}
2116
2117void ocrdma_flush_qp(struct ocrdma_qp *qp)
2118{
2119 bool found;
2120 unsigned long flags;
d2b8f7b1 2121 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
fe2caefc 2122
d2b8f7b1 2123 spin_lock_irqsave(&dev->flush_q_lock, flags);
fe2caefc
PP		 2124 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
2125 if (!found)
2126 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
2127 if (!qp->srq) {
2128 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
2129 if (!found)
2130 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
2131 }
d2b8f7b1 2132 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
fe2caefc
PP		 2133}
2134
f11220ee
NG		 2135static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
2136{
2137 qp->sq.head = 0;
2138 qp->sq.tail = 0;
2139 qp->rq.head = 0;
2140 qp->rq.tail = 0;
2141}
2142
057729cb
NG		 2143int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
2144 enum ib_qp_state *old_ib_state)
fe2caefc
PP		 2145{
2146 unsigned long flags;
fe2caefc
PP		 2147 enum ocrdma_qp_state new_state;
2148 new_state = get_ocrdma_qp_state(new_ib_state);
2149
2150 /* sync with wqe and rqe posting */
2151 spin_lock_irqsave(&qp->q_lock, flags);
2152
2153 if (old_ib_state)
2154 *old_ib_state = get_ibqp_state(qp->state);
2155 if (new_state == qp->state) {
2156 spin_unlock_irqrestore(&qp->q_lock, flags);
2157 return 1;
2158 }
2159
057729cb 2160
f11220ee
NG		 2161 if (new_state == OCRDMA_QPS_INIT) {
2162 ocrdma_init_hwq_ptr(qp);
2163 ocrdma_del_flush_qp(qp);
2164 } else if (new_state == OCRDMA_QPS_ERR) {
057729cb 2165 ocrdma_flush_qp(qp);
f11220ee 2166 }
057729cb
NG		 2167
2168 qp->state = new_state;
fe2caefc
PP		 2169
2170 spin_unlock_irqrestore(&qp->q_lock, flags);
d1c95b0e 2171 return 0;
fe2caefc
PP		 2172}
2173
2174static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
2175{
2176 u32 flags = 0;
2177 if (qp->cap_flags & OCRDMA_QP_INB_RD)
2178 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
2179 if (qp->cap_flags & OCRDMA_QP_INB_WR)
2180 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
2181 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
2182 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
2183 if (qp->cap_flags & OCRDMA_QP_LKEY0)
2184 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
2185 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
2186 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
2187 return flags;
2188}
2189
2190static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
2191 struct ib_qp_init_attr *attrs,
2192 struct ocrdma_qp *qp)
2193{
2194 int status;
2195 u32 len, hw_pages, hw_page_size;
2196 dma_addr_t pa;
d2b8f7b1
MA		 2197 struct ocrdma_pd *pd = qp->pd;
2198 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
fe2caefc
PP		 2199 struct pci_dev *pdev = dev->nic_info.pdev;
2200 u32 max_wqe_allocated;
2201 u32 max_sges = attrs->cap.max_send_sge;
2202
43a6b402 2203 /* QP1 may exceed 127 */
6ebacdfc 2204 max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
43a6b402 2205 dev->attr.max_wqe);
fe2caefc
PP		 2206
2207 status = ocrdma_build_q_conf(&max_wqe_allocated,
2208 dev->attr.wqe_size, &hw_pages, &hw_page_size);
2209 if (status) {
ef99c4c2
NG		 2210 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
2211 max_wqe_allocated);
fe2caefc
PP		 2212 return -EINVAL;
2213 }
2214 qp->sq.max_cnt = max_wqe_allocated;
2215 len = (hw_pages * hw_page_size);
2216
2217 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2218 if (!qp->sq.va)
2219 return -EINVAL;
2220 memset(qp->sq.va, 0, len);
2221 qp->sq.len = len;
2222 qp->sq.pa = pa;
2223 qp->sq.entry_size = dev->attr.wqe_size;
2224 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2225
2226 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2227 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2228 cmd->num_wq_rq_pages |= (hw_pages <<
2229 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2230 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2231 cmd->max_sge_send_write |= (max_sges <<
2232 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2233 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2234 cmd->max_sge_send_write |= (max_sges <<
2235 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2236 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2237 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2238 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2239 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2240 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2241 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2242 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2243 return 0;
2244}
2245
2246static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2247 struct ib_qp_init_attr *attrs,
2248 struct ocrdma_qp *qp)
2249{
2250 int status;
2251 u32 len, hw_pages, hw_page_size;
2252 dma_addr_t pa = 0;
d2b8f7b1
MA		 2253 struct ocrdma_pd *pd = qp->pd;
2254 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
fe2caefc
PP		 2255 struct pci_dev *pdev = dev->nic_info.pdev;
2256 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2257
2258 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2259 &hw_pages, &hw_page_size);
2260 if (status) {
ef99c4c2
NG		 2261 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2262 attrs->cap.max_recv_wr + 1);
fe2caefc
PP		 2263 return status;
2264 }
2265 qp->rq.max_cnt = max_rqe_allocated;
2266 len = (hw_pages * hw_page_size);
2267
2268 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2269 if (!qp->rq.va)
c94e15c5 2270 return -ENOMEM;
fe2caefc
PP		 2271 memset(qp->rq.va, 0, len);
2272 qp->rq.pa = pa;
2273 qp->rq.len = len;
2274 qp->rq.entry_size = dev->attr.rqe_size;
2275
2276 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2277 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2278 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2279 cmd->num_wq_rq_pages |=
2280 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2281 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2282 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2283 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2284 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2285 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2286 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2287 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2288 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2289 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2290 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2291 return 0;
2292}
2293
2294static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2295 struct ocrdma_pd *pd,
2296 struct ocrdma_qp *qp,
2297 u8 enable_dpp_cq, u16 dpp_cq_id)
2298{
2299 pd->num_dpp_qp--;
2300 qp->dpp_enabled = true;
2301 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2302 if (!enable_dpp_cq)
2303 return;
2304 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2305 cmd->dpp_credits_cqid = dpp_cq_id;
2306 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2307 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2308}
2309
2310static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2311 struct ocrdma_qp *qp)
2312{
d2b8f7b1
MA		 2313 struct ocrdma_pd *pd = qp->pd;
2314 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
fe2caefc
PP		 2315 struct pci_dev *pdev = dev->nic_info.pdev;
2316 dma_addr_t pa = 0;
2317 int ird_page_size = dev->attr.ird_page_size;
2318 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
43a6b402
NG		 2319 struct ocrdma_hdr_wqe *rqe;
2320 int i = 0;
fe2caefc
PP		 2321
2322 if (dev->attr.ird == 0)
2323 return 0;
2324
2325 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2326 &pa, GFP_KERNEL);
2327 if (!qp->ird_q_va)
2328 return -ENOMEM;
2329 memset(qp->ird_q_va, 0, ird_q_len);
2330 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2331 pa, ird_page_size);
43a6b402
NG		 2332 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2333 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2334 (i * dev->attr.rqe_size));
2335 rqe->cw = 0;
2336 rqe->cw |= 2;
2337 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2338 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2339 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2340 }
fe2caefc
PP		 2341 return 0;
2342}
2343
2344static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2345 struct ocrdma_qp *qp,
2346 struct ib_qp_init_attr *attrs,
2347 u16 *dpp_offset, u16 *dpp_credit_lmt)
2348{
2349 u32 max_wqe_allocated, max_rqe_allocated;
2350 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2351 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2352 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2353 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2354 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2355 qp->dpp_enabled = false;
2356 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2357 qp->dpp_enabled = true;
2358 *dpp_credit_lmt = (rsp->dpp_response &
2359 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2360 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2361 *dpp_offset = (rsp->dpp_response &
2362 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2363 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2364 }
2365 max_wqe_allocated =
2366 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2367 max_wqe_allocated = 1 << max_wqe_allocated;
2368 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2369
fe2caefc
PP		 2370 qp->sq.max_cnt = max_wqe_allocated;
2371 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2372
2373 if (!attrs->srq) {
2374 qp->rq.max_cnt = max_rqe_allocated;
2375 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
fe2caefc
PP		 2376 }
2377}
2378
2379int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2380 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2381 u16 *dpp_credit_lmt)
2382{
2383 int status = -ENOMEM;
2384 u32 flags = 0;
fe2caefc 2385 struct ocrdma_pd *pd = qp->pd;
d2b8f7b1 2386 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
fe2caefc
PP		 2387 struct pci_dev *pdev = dev->nic_info.pdev;
2388 struct ocrdma_cq *cq;
2389 struct ocrdma_create_qp_req *cmd;
2390 struct ocrdma_create_qp_rsp *rsp;
2391 int qptype;
2392
2393 switch (attrs->qp_type) {
2394 case IB_QPT_GSI:
2395 qptype = OCRDMA_QPT_GSI;
2396 break;
2397 case IB_QPT_RC:
2398 qptype = OCRDMA_QPT_RC;
2399 break;
2400 case IB_QPT_UD:
2401 qptype = OCRDMA_QPT_UD;
2402 break;
2403 default:
2404 return -EINVAL;
2b50176d 2405 }
fe2caefc
PP		 2406
2407 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2408 if (!cmd)
2409 return status;
2410 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2411 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2412 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2413 if (status)
2414 goto sq_err;
2415
2416 if (attrs->srq) {
2417 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2418 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2419 cmd->rq_addr[0].lo = srq->id;
2420 qp->srq = srq;
2421 } else {
2422 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2423 if (status)
2424 goto rq_err;
2425 }
2426
2427 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2428 if (status)
2429 goto mbx_err;
2430
2431 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2432 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2433
2434 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2435
2436 cmd->max_sge_recv_flags |= flags;
2437 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2438 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2439 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2440 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2441 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2442 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2443 cq = get_ocrdma_cq(attrs->send_cq);
2444 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2445 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2446 qp->sq_cq = cq;
2447 cq = get_ocrdma_cq(attrs->recv_cq);
2448 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2449 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2450 qp->rq_cq = cq;
2451
f50f31e4
DS		 2452 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2453 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
fe2caefc
PP		 2454 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2455 dpp_cq_id);
f99b1649 2456 }
fe2caefc
PP		 2457
2458 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2459 if (status)
2460 goto mbx_err;
2461 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2462 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2463 qp->state = OCRDMA_QPS_RST;
2464 kfree(cmd);
2465 return 0;
2466mbx_err:
2467 if (qp->rq.va)
2468 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2469rq_err:
ef99c4c2 2470 pr_err("%s(%d) rq_err\n", __func__, dev->id);
fe2caefc
PP		 2471 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2472sq_err:
ef99c4c2 2473 pr_err("%s(%d) sq_err\n", __func__, dev->id);
fe2caefc
PP		 2474 kfree(cmd);
2475 return status;
2476}
2477
2478int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2479 struct ocrdma_qp_params *param)
2480{
2481 int status = -ENOMEM;
2482 struct ocrdma_query_qp *cmd;
2483 struct ocrdma_query_qp_rsp *rsp;
2484
038ab8b7 2485 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*rsp));
fe2caefc
PP		 2486 if (!cmd)
2487 return status;
2488 cmd->qp_id = qp->id;
2489 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2490 if (status)
2491 goto mbx_err;
2492 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2493 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2494mbx_err:
2495 kfree(cmd);
2496 return status;
2497}
2498
f99b1649 2499static int ocrdma_set_av_params(struct ocrdma_qp *qp,
fe2caefc 2500 struct ocrdma_modify_qp *cmd,
bf67472c
SX		 2501 struct ib_qp_attr *attrs,
2502 int attr_mask)
fe2caefc 2503{
f99b1649 2504 int status;
90898850 2505 struct rdma_ah_attr *ah_attr = &attrs->ah_attr;
9c58726b 2506 union ib_gid sgid, zgid;
dbf727de 2507 struct ib_gid_attr sgid_attr;
6f5deab0 2508 u32 vlan_id = 0xFFFF;
bcf117e2
DS		 2509 u8 mac_addr[6], hdr_type;
2510 union {
2511 struct sockaddr _sockaddr;
2512 struct sockaddr_in _sockaddr_in;
2513 struct sockaddr_in6 _sockaddr_in6;
2514 } sgid_addr, dgid_addr;
d2b8f7b1 2515 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
d8966fcd 2516 const struct ib_global_route *grh;
9c58726b 2517
d8966fcd 2518 if ((rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH) == 0)
f99b1649 2519 return -EINVAL;
d8966fcd 2520 grh = rdma_ah_read_grh(ah_attr);
d2b8f7b1
MA		 2521 if (atomic_cmpxchg(&dev->update_sl, 1, 0))
2522 ocrdma_init_service_level(dev);
fe2caefc 2523 cmd->params.tclass_sq_psn |=
d8966fcd 2524 (grh->traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
fe2caefc 2525 cmd->params.rnt_rc_sl_fl |=
d8966fcd
DC		 2526 (grh->flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2527 cmd->params.rnt_rc_sl_fl |= (rdma_ah_get_sl(ah_attr) <<
2528 OCRDMA_QP_PARAMS_SL_SHIFT);
fe2caefc 2529 cmd->params.hop_lmt_rq_psn |=
d8966fcd 2530 (grh->hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
fe2caefc 2531 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
bcf117e2
DS		 2532
2533 /* GIDs */
d8966fcd 2534 memcpy(&cmd->params.dgid[0], &grh->dgid.raw[0],
fe2caefc 2535 sizeof(cmd->params.dgid));
dbf727de 2536
d8966fcd 2537 status = ib_get_cached_gid(&dev->ibdev, 1, grh->sgid_index,
dbf727de
MB		 2538 &sgid, &sgid_attr);
2539 if (!status && sgid_attr.ndev) {
2540 vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
2541 memcpy(mac_addr, sgid_attr.ndev->dev_addr, ETH_ALEN);
2542 dev_put(sgid_attr.ndev);
2543 }
9c58726b
NG		 2544
2545 memset(&zgid, 0, sizeof(zgid));
2546 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2547 return -EINVAL;
2548
d8966fcd 2549 qp->sgid_idx = grh->sgid_index;
fe2caefc 2550 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
d2b8f7b1 2551 status = ocrdma_resolve_dmac(dev, ah_attr, &mac_addr[0]);
a601dc77
DS		 2552 if (status)
2553 return status;
fe2caefc
PP		 2554 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2555 (mac_addr[2] << 16) | (mac_addr[3] << 24);
bcf117e2
DS		 2556
2557 hdr_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
2558 if (hdr_type == RDMA_NETWORK_IPV4) {
2559 rdma_gid2ip(&sgid_addr._sockaddr, &sgid);
d8966fcd 2560 rdma_gid2ip(&dgid_addr._sockaddr, &grh->dgid);
bcf117e2
DS		 2561 memcpy(&cmd->params.dgid[0],
2562 &dgid_addr._sockaddr_in.sin_addr.s_addr, 4);
2563 memcpy(&cmd->params.sgid[0],
2564 &sgid_addr._sockaddr_in.sin_addr.s_addr, 4);
2565 }
fe2caefc
PP		 2566 /* convert them to LE format. */
2567 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2568 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2569 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
6f5deab0 2570
c6002d56
DS		 2571 if (vlan_id == 0xFFFF)
2572 vlan_id = 0;
2573 if (vlan_id || dev->pfc_state) {
2574 if (!vlan_id) {
dbf727de
MB		 2575 pr_err("ocrdma%d:Using VLAN with PFC is recommended\n",
2576 dev->id);
2577 pr_err("ocrdma%d:Using VLAN 0 for this connection\n",
2578 dev->id);
2579 }
fe2caefc
PP		 2580 cmd->params.vlan_dmac_b4_to_b5 |=
2581 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2582 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
31dbdd9a 2583 cmd->params.rnt_rc_sl_fl |=
d2b8f7b1 2584 (dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
fe2caefc 2585 }
bcf117e2
DS		 2586 cmd->params.max_sge_recv_flags |= ((hdr_type <<
2587 OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_SHIFT) &
2588 OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_MASK);
f99b1649 2589 return 0;
fe2caefc
PP		 2590}
2591
2592static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2593 struct ocrdma_modify_qp *cmd,
bc1b04ab 2594 struct ib_qp_attr *attrs, int attr_mask)
fe2caefc
PP		 2595{
2596 int status = 0;
d2b8f7b1 2597 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
fe2caefc
PP		 2598
2599 if (attr_mask & IB_QP_PKEY_INDEX) {
2600 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2601 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2602 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2603 }
2604 if (attr_mask & IB_QP_QKEY) {
2605 qp->qkey = attrs->qkey;
2606 cmd->params.qkey = attrs->qkey;
2607 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2608 }
f99b1649 2609 if (attr_mask & IB_QP_AV) {
bf67472c 2610 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
f99b1649
NG		 2611 if (status)
2612 return status;
2613 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
fe2caefc 2614 /* set the default mac address for UD, GSI QPs */
d2b8f7b1
MA		 2615 cmd->params.dmac_b0_to_b3 = dev->nic_info.mac_addr[0] |
2616 (dev->nic_info.mac_addr[1] << 8) |
2617 (dev->nic_info.mac_addr[2] << 16) |
2618 (dev->nic_info.mac_addr[3] << 24);
2619 cmd->params.vlan_dmac_b4_to_b5 = dev->nic_info.mac_addr[4] |
2620 (dev->nic_info.mac_addr[5] << 8);
fe2caefc
PP		 2621 }
2622 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2623 attrs->en_sqd_async_notify) {
2624 cmd->params.max_sge_recv_flags |=
2625 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2626 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2627 }
2628 if (attr_mask & IB_QP_DEST_QPN) {
2629 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2630 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2631 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2632 }
2633 if (attr_mask & IB_QP_PATH_MTU) {
72d8a013 2634 if (attrs->path_mtu < IB_MTU_512 ||
d3cb6c0b 2635 attrs->path_mtu > IB_MTU_4096) {
72d8a013
NI		 2636 pr_err("ocrdma%d: IB MTU %d is not supported\n",
2637 dev->id, ib_mtu_enum_to_int(attrs->path_mtu));
fe2caefc
PP		 2638 status = -EINVAL;
2639 goto pmtu_err;
2640 }
2641 cmd->params.path_mtu_pkey_indx |=
2642 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2643 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2644 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2645 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2646 }
2647 if (attr_mask & IB_QP_TIMEOUT) {
2648 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2649 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2650 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2651 }
2652 if (attr_mask & IB_QP_RETRY_CNT) {
2653 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2654 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2655 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2656 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2657 }
2658 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2659 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2660 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2661 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2662 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2663 }
2664 if (attr_mask & IB_QP_RNR_RETRY) {
2665 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2666 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2667 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2668 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2669 }
2670 if (attr_mask & IB_QP_SQ_PSN) {
2671 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2672 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2673 }
2674 if (attr_mask & IB_QP_RQ_PSN) {
2675 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2676 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2677 }
2678 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
d2b8f7b1 2679 if (attrs->max_rd_atomic > dev->attr.max_ord_per_qp) {
fe2caefc
PP		 2680 status = -EINVAL;
2681 goto pmtu_err;
2682 }
2683 qp->max_ord = attrs->max_rd_atomic;
2684 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2685 }
2686 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
d2b8f7b1 2687 if (attrs->max_dest_rd_atomic > dev->attr.max_ird_per_qp) {
fe2caefc
PP		 2688 status = -EINVAL;
2689 goto pmtu_err;
2690 }
2691 qp->max_ird = attrs->max_dest_rd_atomic;
2692 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2693 }
2694 cmd->params.max_ord_ird = (qp->max_ord <<
2695 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2696 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2697pmtu_err:
2698 return status;
2699}
2700
2701int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
bc1b04ab 2702 struct ib_qp_attr *attrs, int attr_mask)
fe2caefc
PP		 2703{
2704 int status = -ENOMEM;
2705 struct ocrdma_modify_qp *cmd;
fe2caefc
PP		 2706
2707 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2708 if (!cmd)
2709 return status;
2710
2711 cmd->params.id = qp->id;
2712 cmd->flags = 0;
2713 if (attr_mask & IB_QP_STATE) {
2714 cmd->params.max_sge_recv_flags |=
2715 (get_ocrdma_qp_state(attrs->qp_state) <<
2716 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2717 OCRDMA_QP_PARAMS_STATE_MASK;
2718 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
f99b1649 2719 } else {
fe2caefc
PP		 2720 cmd->params.max_sge_recv_flags |=
2721 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2722 OCRDMA_QP_PARAMS_STATE_MASK;
f99b1649
NG		 2723 }
2724
bc1b04ab 2725 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
fe2caefc
PP		 2726 if (status)
2727 goto mbx_err;
2728 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2729 if (status)
2730 goto mbx_err;
c592c423 2731
fe2caefc
PP		 2732mbx_err:
2733 kfree(cmd);
2734 return status;
2735}
2736
2737int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2738{
2739 int status = -ENOMEM;
2740 struct ocrdma_destroy_qp *cmd;
fe2caefc
PP		 2741 struct pci_dev *pdev = dev->nic_info.pdev;
2742
2743 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2744 if (!cmd)
2745 return status;
2746 cmd->qp_id = qp->id;
2747 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2748 if (status)
2749 goto mbx_err;
c592c423 2750
fe2caefc
PP		 2751mbx_err:
2752 kfree(cmd);
2753 if (qp->sq.va)
2754 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2755 if (!qp->srq && qp->rq.va)
2756 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2757 if (qp->dpp_enabled)
2758 qp->pd->num_dpp_qp++;
2759 return status;
2760}
2761
1afc0454 2762int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
fe2caefc
PP		 2763 struct ib_srq_init_attr *srq_attr,
2764 struct ocrdma_pd *pd)
2765{
2766 int status = -ENOMEM;
2767 int hw_pages, hw_page_size;
2768 int len;
2769 struct ocrdma_create_srq_rsp *rsp;
2770 struct ocrdma_create_srq *cmd;
2771 dma_addr_t pa;
fe2caefc
PP		 2772 struct pci_dev *pdev = dev->nic_info.pdev;
2773 u32 max_rqe_allocated;
2774
2775 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2776 if (!cmd)
2777 return status;
2778
2779 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2780 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2781 status = ocrdma_build_q_conf(&max_rqe_allocated,
2782 dev->attr.rqe_size,
2783 &hw_pages, &hw_page_size);
2784 if (status) {
ef99c4c2
NG		 2785 pr_err("%s() req. max_wr=0x%x\n", __func__,
2786 srq_attr->attr.max_wr);
fe2caefc
PP		 2787 status = -EINVAL;
2788 goto ret;
2789 }
2790 len = hw_pages * hw_page_size;
2791 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2792 if (!srq->rq.va) {
2793 status = -ENOMEM;
2794 goto ret;
2795 }
2796 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2797
2798 srq->rq.entry_size = dev->attr.rqe_size;
2799 srq->rq.pa = pa;
2800 srq->rq.len = len;
2801 srq->rq.max_cnt = max_rqe_allocated;
2802
2803 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2804 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2805 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2806
2807 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2808 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2809 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2810 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2811 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2812 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2813
2814 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2815 if (status)
2816 goto mbx_err;
2817 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2818 srq->id = rsp->id;
2819 srq->rq.dbid = rsp->id;
2820 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2821 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2822 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2823 max_rqe_allocated = (1 << max_rqe_allocated);
2824 srq->rq.max_cnt = max_rqe_allocated;
2825 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2826 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2827 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2828 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2829 goto ret;
2830mbx_err:
2831 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2832ret:
2833 kfree(cmd);
2834 return status;
2835}
2836
2837int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2838{
2839 int status = -ENOMEM;
2840 struct ocrdma_modify_srq *cmd;
f11220ee
NG		 2841 struct ocrdma_pd *pd = srq->pd;
2842 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
1afc0454 2843
d7e19c0a 2844 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
fe2caefc
PP		 2845 if (!cmd)
2846 return status;
2847 cmd->id = srq->id;
2848 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2849 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
1afc0454 2850 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2851 kfree(cmd);
2852 return status;
2853}
2854
2855int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2856{
2857 int status = -ENOMEM;
2858 struct ocrdma_query_srq *cmd;
1afc0454
NG		 2859 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2860
d7e19c0a 2861 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
fe2caefc
PP		 2862 if (!cmd)
2863 return status;
2864 cmd->id = srq->rq.dbid;
1afc0454 2865 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2866 if (status == 0) {
2867 struct ocrdma_query_srq_rsp *rsp =
2868 (struct ocrdma_query_srq_rsp *)cmd;
2869 srq_attr->max_sge =
2870 rsp->srq_lmt_max_sge &
2871 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2872 srq_attr->max_wr =
2873 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2874 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2875 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2876 }
2877 kfree(cmd);
2878 return status;
2879}
2880
2881int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2882{
2883 int status = -ENOMEM;
2884 struct ocrdma_destroy_srq *cmd;
2885 struct pci_dev *pdev = dev->nic_info.pdev;
2886 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2887 if (!cmd)
2888 return status;
2889 cmd->id = srq->id;
1afc0454 2890 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2891 if (srq->rq.va)
2892 dma_free_coherent(&pdev->dev, srq->rq.len,
2893 srq->rq.va, srq->rq.pa);
2894 kfree(cmd);
2895 return status;
2896}
2897
31dbdd9a
SX		 2898static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2899 struct ocrdma_dcbx_cfg *dcbxcfg)
2900{
0ca4c39f 2901 int status;
31dbdd9a
SX		 2902 dma_addr_t pa;
2903 struct ocrdma_mqe cmd;
2904
2905 struct ocrdma_get_dcbx_cfg_req *req = NULL;
2906 struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2907 struct pci_dev *pdev = dev->nic_info.pdev;
2908 struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2909
2910 memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2911 cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2912 sizeof(struct ocrdma_get_dcbx_cfg_req));
2913 req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2914 if (!req) {
2915 status = -ENOMEM;
2916 goto mem_err;
2917 }
2918
2919 cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2920 OCRDMA_MQE_HDR_SGE_CNT_MASK;
2921 mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2922 mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2923 mqe_sge->len = cmd.hdr.pyld_len;
2924
2925 memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2926 ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2927 OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2928 req->param_type = ptype;
2929
2930 status = ocrdma_mbx_cmd(dev, &cmd);
2931 if (status)
2932 goto mbx_err;
2933
2934 rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2935 ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2936 memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2937
2938mbx_err:
2939 dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2940mem_err:
2941 return status;
2942}
2943
2944#define OCRDMA_MAX_SERVICE_LEVEL_INDEX 0x08
2945#define OCRDMA_DEFAULT_SERVICE_LEVEL 0x05
2946
2947static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2948 struct ocrdma_dcbx_cfg *dcbxcfg,
2949 u8 *srvc_lvl)
2950{
2951 int status = -EINVAL, indx, slindx;
2952 int ventry_cnt;
2953 struct ocrdma_app_parameter *app_param;
2954 u8 valid, proto_sel;
2955 u8 app_prio, pfc_prio;
2956 u16 proto;
2957
2958 if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2959 pr_info("%s ocrdma%d DCBX is disabled\n",
2960 dev_name(&dev->nic_info.pdev->dev), dev->id);
2961 goto out;
2962 }
2963
2964 if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2965 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2966 dev_name(&dev->nic_info.pdev->dev), dev->id,
2967 (ptype > 0 ? "operational" : "admin"),
2968 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2969 "enabled" : "disabled",
2970 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2971 "" : ", not sync'ed");
2972 goto out;
2973 } else {
2974 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2975 dev_name(&dev->nic_info.pdev->dev), dev->id);
2976 }
2977
2978 ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2979 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2980 & OCRDMA_DCBX_STATE_MASK;
2981
2982 for (indx = 0; indx < ventry_cnt; indx++) {
2983 app_param = &dcbxcfg->app_param[indx];
2984 valid = (app_param->valid_proto_app >>
2985 OCRDMA_APP_PARAM_VALID_SHIFT)
2986 & OCRDMA_APP_PARAM_VALID_MASK;
2987 proto_sel = (app_param->valid_proto_app
2988 >> OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2989 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2990 proto = app_param->valid_proto_app &
2991 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2992
2993 if (
69ae5439 2994 valid && proto == ETH_P_IBOE &&
31dbdd9a
SX		 2995 proto_sel == OCRDMA_PROTO_SELECT_L2) {
2996 for (slindx = 0; slindx <
2997 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2998 app_prio = ocrdma_get_app_prio(
2999 (u8 *)app_param->app_prio,
3000 slindx);
3001 pfc_prio = ocrdma_get_pfc_prio(
3002 (u8 *)dcbxcfg->pfc_prio,
3003 slindx);
3004
3005 if (app_prio && pfc_prio) {
3006 *srvc_lvl = slindx;
3007 status = 0;
3008 goto out;
3009 }
3010 }
3011 if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
3012 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
3013 dev_name(&dev->nic_info.pdev->dev),
3014 dev->id, proto);
3015 }
3016 }
3017 }
3018
3019out:
3020 return status;
3021}
3022
3023void ocrdma_init_service_level(struct ocrdma_dev *dev)
3024{
3025 int status = 0, indx;
3026 struct ocrdma_dcbx_cfg dcbxcfg;
3027 u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
3028 int ptype = OCRDMA_PARAMETER_TYPE_OPER;
3029
3030 for (indx = 0; indx < 2; indx++) {
3031 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
3032 if (status) {
3033 pr_err("%s(): status=%d\n", __func__, status);
3034 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
3035 continue;
3036 }
3037
3038 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
3039 &dcbxcfg, &srvc_lvl);
3040 if (status) {
3041 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
3042 continue;
3043 }
3044
3045 break;
3046 }
3047
3048 if (status)
3049 pr_info("%s ocrdma%d service level default\n",
3050 dev_name(&dev->nic_info.pdev->dev), dev->id);
3051 else
3052 pr_info("%s ocrdma%d service level %d\n",
3053 dev_name(&dev->nic_info.pdev->dev), dev->id,
3054 srvc_lvl);
3055
3056 dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
3057 dev->sl = srvc_lvl;
3058}
3059
fe2caefc
PP		 3060int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3061{
3062 int i;
3063 int status = -EINVAL;
3064 struct ocrdma_av *av;
3065 unsigned long flags;
3066
3067 av = dev->av_tbl.va;
3068 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3069 for (i = 0; i < dev->av_tbl.num_ah; i++) {
3070 if (av->valid == 0) {
3071 av->valid = OCRDMA_AV_VALID;
3072 ah->av = av;
3073 ah->id = i;
3074 status = 0;
3075 break;
3076 }
3077 av++;
3078 }
3079 if (i == dev->av_tbl.num_ah)
3080 status = -EAGAIN;
3081 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3082 return status;
3083}
3084
3085int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3086{
3087 unsigned long flags;
3088 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3089 ah->av->valid = 0;
3090 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3091 return 0;
3092}
3093
c88bd03f 3094static int ocrdma_create_eqs(struct ocrdma_dev *dev)
fe2caefc 3095{
da496438 3096 int num_eq, i, status = 0;
fe2caefc
PP		 3097 int irq;
3098 unsigned long flags = 0;
3099
3100 num_eq = dev->nic_info.msix.num_vectors -
3101 dev->nic_info.msix.start_vector;
3102 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
3103 num_eq = 1;
3104 flags = IRQF_SHARED;
f99b1649 3105 } else {
fe2caefc 3106 num_eq = min_t(u32, num_eq, num_online_cpus());
f99b1649
NG		 3107 }
3108
c88bd03f
NG		 3109 if (!num_eq)
3110 return -EINVAL;
3111
3112 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
3113 if (!dev->eq_tbl)
fe2caefc
PP		 3114 return -ENOMEM;
3115
3116 for (i = 0; i < num_eq; i++) {
c88bd03f 3117 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
fad51b7d 3118 OCRDMA_EQ_LEN);
fe2caefc
PP		 3119 if (status) {
3120 status = -EINVAL;
3121 break;
3122 }
c88bd03f 3123 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
fe2caefc 3124 dev->id, i);
c88bd03f 3125 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
fe2caefc 3126 status = request_irq(irq, ocrdma_irq_handler, flags,
c88bd03f
NG		 3127 dev->eq_tbl[i].irq_name,
3128 &dev->eq_tbl[i]);
3129 if (status)
3130 goto done;
fe2caefc
PP		 3131 dev->eq_cnt += 1;
3132 }
3133 /* one eq is sufficient for data path to work */
c88bd03f
NG		 3134 return 0;
3135done:
3136 ocrdma_destroy_eqs(dev);
fe2caefc
PP		 3137 return status;
3138}
3139
b4dbe8d5
MA		 3140static int ocrdma_mbx_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3141 int num)
3142{
3143 int i, status = -ENOMEM;
3144 struct ocrdma_modify_eqd_req *cmd;
3145
3146 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_EQ_DELAY, sizeof(*cmd));
3147 if (!cmd)
3148 return status;
3149
3150 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_MODIFY_EQ_DELAY,
3151 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
3152
3153 cmd->cmd.num_eq = num;
3154 for (i = 0; i < num; i++) {
3155 cmd->cmd.set_eqd[i].eq_id = eq[i].q.id;
3156 cmd->cmd.set_eqd[i].phase = 0;
3157 cmd->cmd.set_eqd[i].delay_multiplier =
3158 (eq[i].aic_obj.prev_eqd * 65)/100;
3159 }
3160 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
3161 if (status)
3162 goto mbx_err;
3163mbx_err:
3164 kfree(cmd);
3165 return status;
3166}
3167
3168static int ocrdma_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3169 int num)
3170{
3171 int num_eqs, i = 0;
3172 if (num > 8) {
3173 while (num) {
3174 num_eqs = min(num, 8);
3175 ocrdma_mbx_modify_eqd(dev, &eq[i], num_eqs);
3176 i += num_eqs;
3177 num -= num_eqs;
3178 }
3179 } else {
3180 ocrdma_mbx_modify_eqd(dev, eq, num);
3181 }
3182 return 0;
3183}
3184
3185void ocrdma_eqd_set_task(struct work_struct *work)
3186{
3187 struct ocrdma_dev *dev =
3188 container_of(work, struct ocrdma_dev, eqd_work.work);
3189 struct ocrdma_eq *eq = 0;
3190 int i, num = 0, status = -EINVAL;
3191 u64 eq_intr;
3192
3193 for (i = 0; i < dev->eq_cnt; i++) {
3194 eq = &dev->eq_tbl[i];
3195 if (eq->aic_obj.eq_intr_cnt > eq->aic_obj.prev_eq_intr_cnt) {
3196 eq_intr = eq->aic_obj.eq_intr_cnt -
3197 eq->aic_obj.prev_eq_intr_cnt;
3198 if ((eq_intr > EQ_INTR_PER_SEC_THRSH_HI) &&
3199 (eq->aic_obj.prev_eqd == EQ_AIC_MIN_EQD)) {
3200 eq->aic_obj.prev_eqd = EQ_AIC_MAX_EQD;
3201 num++;
3202 } else if ((eq_intr < EQ_INTR_PER_SEC_THRSH_LOW) &&
3203 (eq->aic_obj.prev_eqd == EQ_AIC_MAX_EQD)) {
3204 eq->aic_obj.prev_eqd = EQ_AIC_MIN_EQD;
3205 num++;
3206 }
3207 }
3208 eq->aic_obj.prev_eq_intr_cnt = eq->aic_obj.eq_intr_cnt;
3209 }
3210
3211 if (num)
3212 status = ocrdma_modify_eqd(dev, &dev->eq_tbl[0], num);
3213 schedule_delayed_work(&dev->eqd_work, msecs_to_jiffies(1000));
3214}
3215
fe2caefc
PP		 3216int ocrdma_init_hw(struct ocrdma_dev *dev)
3217{
3218 int status;
c88bd03f
NG		 3219
3220 /* create the eqs */
3221 status = ocrdma_create_eqs(dev);
fe2caefc
PP		 3222 if (status)
3223 goto qpeq_err;
3224 status = ocrdma_create_mq(dev);
3225 if (status)
3226 goto mq_err;
3227 status = ocrdma_mbx_query_fw_config(dev);
3228 if (status)
3229 goto conf_err;
3230 status = ocrdma_mbx_query_dev(dev);
3231 if (status)
3232 goto conf_err;
3233 status = ocrdma_mbx_query_fw_ver(dev);
3234 if (status)
3235 goto conf_err;
3236 status = ocrdma_mbx_create_ah_tbl(dev);
3237 if (status)
3238 goto conf_err;
a51f06e1
SX		 3239 status = ocrdma_mbx_get_phy_info(dev);
3240 if (status)
daac9681 3241 goto info_attrb_err;
a51f06e1
SX		 3242 status = ocrdma_mbx_get_ctrl_attribs(dev);
3243 if (status)
daac9681 3244 goto info_attrb_err;
a51f06e1 3245
fe2caefc
PP		 3246 return 0;
3247
daac9681
DS		 3248info_attrb_err:
3249 ocrdma_mbx_delete_ah_tbl(dev);
fe2caefc
PP		 3250conf_err:
3251 ocrdma_destroy_mq(dev);
3252mq_err:
c88bd03f 3253 ocrdma_destroy_eqs(dev);
fe2caefc 3254qpeq_err:
ef99c4c2 3255 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 3256 return status;
3257}
3258
3259void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
3260{
9ba1377d 3261 ocrdma_free_pd_pool(dev);
fe2caefc
PP		 3262 ocrdma_mbx_delete_ah_tbl(dev);
3263
fe2caefc
PP		 3264 /* cleanup the control path */
3265 ocrdma_destroy_mq(dev);
314fdf44
SX		 3266
3267 /* cleanup the eqs */
3268 ocrdma_destroy_eqs(dev);
fe2caefc 3269}
Linux 6.x block layer and io_uring tree(s)