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RDMA/ocrdma: Cache recv DB until QP moved to RTR
[linux-2.6-block.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
CommitLineData
fe2caefc
PP		 1/*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/log2.h>
31#include <linux/dma-mapping.h>
32
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_user_verbs.h>
35#include <rdma/ib_addr.h>
36
37#include "ocrdma.h"
38#include "ocrdma_hw.h"
39#include "ocrdma_verbs.h"
40#include "ocrdma_ah.h"
41
42enum mbx_status {
43 OCRDMA_MBX_STATUS_FAILED = 1,
44 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
45 OCRDMA_MBX_STATUS_OOR = 100,
46 OCRDMA_MBX_STATUS_INVALID_PD = 101,
47 OCRDMA_MBX_STATUS_PD_INUSE = 102,
48 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
49 OCRDMA_MBX_STATUS_INVALID_QP = 104,
50 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
51 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
52 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
53 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
54 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
55 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
56 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
57 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
58 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
59 OCRDMA_MBX_STATUS_MW_BOUND = 114,
60 OCRDMA_MBX_STATUS_INVALID_VA = 115,
61 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
62 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
63 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
64 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
65 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
66 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
67 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
68 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
69 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
70 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
71 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
72 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
73 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
74 OCRDMA_MBX_STATUS_QP_BOUND = 130,
75 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
76 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
77 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
78 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
79 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
80 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
81};
82
83enum additional_status {
84 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
85};
86
87enum cqe_status {
88 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
89 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
90 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
91 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
92 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
93};
94
95static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
96{
f99b1649 97 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
fe2caefc
PP		 98}
99
100static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
101{
102 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
103}
104
105static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
106{
107 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
f99b1649 108 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
fe2caefc
PP		 109
110 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
111 return NULL;
112 return cqe;
113}
114
115static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
116{
117 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
118}
119
120static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
121{
f99b1649 122 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 123}
124
125static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
126{
127 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
fe2caefc
PP		 128}
129
130static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
131{
f99b1649 132 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 133}
134
135enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
136{
137 switch (qps) {
138 case OCRDMA_QPS_RST:
139 return IB_QPS_RESET;
140 case OCRDMA_QPS_INIT:
141 return IB_QPS_INIT;
142 case OCRDMA_QPS_RTR:
143 return IB_QPS_RTR;
144 case OCRDMA_QPS_RTS:
145 return IB_QPS_RTS;
146 case OCRDMA_QPS_SQD:
147 case OCRDMA_QPS_SQ_DRAINING:
148 return IB_QPS_SQD;
149 case OCRDMA_QPS_SQE:
150 return IB_QPS_SQE;
151 case OCRDMA_QPS_ERR:
152 return IB_QPS_ERR;
153 };
154 return IB_QPS_ERR;
155}
156
abe3afac 157static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
fe2caefc
PP		 158{
159 switch (qps) {
160 case IB_QPS_RESET:
161 return OCRDMA_QPS_RST;
162 case IB_QPS_INIT:
163 return OCRDMA_QPS_INIT;
164 case IB_QPS_RTR:
165 return OCRDMA_QPS_RTR;
166 case IB_QPS_RTS:
167 return OCRDMA_QPS_RTS;
168 case IB_QPS_SQD:
169 return OCRDMA_QPS_SQD;
170 case IB_QPS_SQE:
171 return OCRDMA_QPS_SQE;
172 case IB_QPS_ERR:
173 return OCRDMA_QPS_ERR;
174 };
175 return OCRDMA_QPS_ERR;
176}
177
178static int ocrdma_get_mbx_errno(u32 status)
179{
f99b1649 180 int err_num;
fe2caefc
PP		 181 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
182 OCRDMA_MBX_RSP_STATUS_SHIFT;
183 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
184 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
185
186 switch (mbox_status) {
187 case OCRDMA_MBX_STATUS_OOR:
188 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
189 err_num = -EAGAIN;
190 break;
191
192 case OCRDMA_MBX_STATUS_INVALID_PD:
193 case OCRDMA_MBX_STATUS_INVALID_CQ:
194 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
195 case OCRDMA_MBX_STATUS_INVALID_QP:
196 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
197 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
198 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
199 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
200 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
201 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
202 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
203 case OCRDMA_MBX_STATUS_INVALID_LKEY:
204 case OCRDMA_MBX_STATUS_INVALID_VA:
205 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
206 case OCRDMA_MBX_STATUS_INVALID_FBO:
207 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
208 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
209 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
210 case OCRDMA_MBX_STATUS_SRQ_ERROR:
211 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
212 err_num = -EINVAL;
213 break;
214
215 case OCRDMA_MBX_STATUS_PD_INUSE:
216 case OCRDMA_MBX_STATUS_QP_BOUND:
217 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
218 case OCRDMA_MBX_STATUS_MW_BOUND:
219 err_num = -EBUSY;
220 break;
221
222 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
223 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
224 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
225 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
226 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
227 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
228 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
229 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
230 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
231 err_num = -ENOBUFS;
232 break;
233
234 case OCRDMA_MBX_STATUS_FAILED:
235 switch (add_status) {
236 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
237 err_num = -EAGAIN;
238 break;
239 }
240 default:
241 err_num = -EFAULT;
242 }
243 return err_num;
244}
245
246static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
247{
248 int err_num = -EINVAL;
249
250 switch (cqe_status) {
251 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
252 err_num = -EPERM;
253 break;
254 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
255 err_num = -EINVAL;
256 break;
257 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
258 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
259 err_num = -EAGAIN;
260 break;
261 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
262 err_num = -EIO;
263 break;
264 }
265 return err_num;
266}
267
268void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
269 bool solicited, u16 cqe_popped)
270{
271 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
272
273 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
274 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
275
276 if (armed)
277 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
278 if (solicited)
279 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
280 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
281 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
282}
283
284static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
285{
286 u32 val = 0;
287
288 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
289 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
290 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
291}
292
293static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
294 bool arm, bool clear_int, u16 num_eqe)
295{
296 u32 val = 0;
297
298 val |= eq_id & OCRDMA_EQ_ID_MASK;
299 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
300 if (arm)
301 val |= (1 << OCRDMA_REARM_SHIFT);
302 if (clear_int)
303 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
304 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
305 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
306 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
307}
308
309static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
310 u8 opcode, u8 subsys, u32 cmd_len)
311{
312 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
313 cmd_hdr->timeout = 20; /* seconds */
314 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
315}
316
317static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
318{
319 struct ocrdma_mqe *mqe;
320
321 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
322 if (!mqe)
323 return NULL;
324 mqe->hdr.spcl_sge_cnt_emb |=
325 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
326 OCRDMA_MQE_HDR_EMB_MASK;
327 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
328
329 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
330 mqe->hdr.pyld_len);
331 return mqe;
332}
333
334static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
335{
336 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
337}
338
339static int ocrdma_alloc_q(struct ocrdma_dev *dev,
340 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
341{
342 memset(q, 0, sizeof(*q));
343 q->len = len;
344 q->entry_size = entry_size;
345 q->size = len * entry_size;
346 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
347 &q->dma, GFP_KERNEL);
348 if (!q->va)
349 return -ENOMEM;
350 memset(q->va, 0, q->size);
351 return 0;
352}
353
354static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
355 dma_addr_t host_pa, int hw_page_size)
356{
357 int i;
358
359 for (i = 0; i < cnt; i++) {
360 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
361 q_pa[i].hi = (u32) upper_32_bits(host_pa);
362 host_pa += hw_page_size;
363 }
364}
365
366static void ocrdma_assign_eq_vect_gen2(struct ocrdma_dev *dev,
367 struct ocrdma_eq *eq)
368{
369 /* assign vector and update vector id for next EQ */
370 eq->vector = dev->nic_info.msix.start_vector;
371 dev->nic_info.msix.start_vector += 1;
372}
373
374static void ocrdma_free_eq_vect_gen2(struct ocrdma_dev *dev)
375{
376 /* this assumes that EQs are freed in exactly reverse order
377 * as its allocation.
378 */
379 dev->nic_info.msix.start_vector -= 1;
380}
381
abe3afac
RD		 382static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q,
383 int queue_type)
fe2caefc
PP		 384{
385 u8 opcode = 0;
386 int status;
387 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
388
389 switch (queue_type) {
390 case QTYPE_MCCQ:
391 opcode = OCRDMA_CMD_DELETE_MQ;
392 break;
393 case QTYPE_CQ:
394 opcode = OCRDMA_CMD_DELETE_CQ;
395 break;
396 case QTYPE_EQ:
397 opcode = OCRDMA_CMD_DELETE_EQ;
398 break;
399 default:
400 BUG();
401 }
402 memset(cmd, 0, sizeof(*cmd));
403 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
404 cmd->id = q->id;
405
406 status = be_roce_mcc_cmd(dev->nic_info.netdev,
407 cmd, sizeof(*cmd), NULL, NULL);
408 if (!status)
409 q->created = false;
410 return status;
411}
412
413static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
414{
415 int status;
416 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
417 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
418
419 memset(cmd, 0, sizeof(*cmd));
420 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
421 sizeof(*cmd));
422 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
423 cmd->req.rsvd_version = 0;
424 else
425 cmd->req.rsvd_version = 2;
426
427 cmd->num_pages = 4;
428 cmd->valid = OCRDMA_CREATE_EQ_VALID;
429 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
430
431 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
432 PAGE_SIZE_4K);
433 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
434 NULL);
435 if (!status) {
436 eq->q.id = rsp->vector_eqid & 0xffff;
f99b1649 437 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
fe2caefc 438 ocrdma_assign_eq_vect_gen2(dev, eq);
f99b1649 439 } else {
fe2caefc
PP		 440 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
441 dev->nic_info.msix.start_vector += 1;
442 }
443 eq->q.created = true;
444 }
445 return status;
446}
447
448static int ocrdma_create_eq(struct ocrdma_dev *dev,
449 struct ocrdma_eq *eq, u16 q_len)
450{
451 int status;
452
453 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
454 sizeof(struct ocrdma_eqe));
455 if (status)
456 return status;
457
458 status = ocrdma_mbx_create_eq(dev, eq);
459 if (status)
460 goto mbx_err;
461 eq->dev = dev;
462 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
463
464 return 0;
465mbx_err:
466 ocrdma_free_q(dev, &eq->q);
467 return status;
468}
469
470static int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
471{
472 int irq;
473
474 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
475 irq = dev->nic_info.pdev->irq;
476 else
477 irq = dev->nic_info.msix.vector_list[eq->vector];
478 return irq;
479}
480
481static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
482{
483 if (eq->q.created) {
484 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
485 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
486 ocrdma_free_eq_vect_gen2(dev);
487 ocrdma_free_q(dev, &eq->q);
488 }
489}
490
491static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
492{
493 int irq;
494
495 /* disarm EQ so that interrupts are not generated
496 * during freeing and EQ delete is in progress.
497 */
498 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
499
500 irq = ocrdma_get_irq(dev, eq);
501 free_irq(irq, eq);
502 _ocrdma_destroy_eq(dev, eq);
503}
504
505static void ocrdma_destroy_qp_eqs(struct ocrdma_dev *dev)
506{
507 int i;
508
509 /* deallocate the data path eqs */
510 for (i = 0; i < dev->eq_cnt; i++)
511 ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
512}
513
abe3afac
RD		 514static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
515 struct ocrdma_queue_info *cq,
516 struct ocrdma_queue_info *eq)
fe2caefc
PP		 517{
518 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
519 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
520 int status;
521
522 memset(cmd, 0, sizeof(*cmd));
523 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
524 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
525
1afc0454
NG		 526 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
527 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
528 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
529 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
530
fe2caefc 531 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1afc0454
NG		 532 cmd->eqn = eq->id;
533 cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe);
fe2caefc 534
1afc0454 535 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
fe2caefc
PP		 536 cq->dma, PAGE_SIZE_4K);
537 status = be_roce_mcc_cmd(dev->nic_info.netdev,
538 cmd, sizeof(*cmd), NULL, NULL);
539 if (!status) {
1afc0454 540 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
fe2caefc
PP		 541 cq->created = true;
542 }
543 return status;
544}
545
546static u32 ocrdma_encoded_q_len(int q_len)
547{
548 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
549
550 if (len_encoded == 16)
551 len_encoded = 0;
552 return len_encoded;
553}
554
555static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
556 struct ocrdma_queue_info *mq,
557 struct ocrdma_queue_info *cq)
558{
559 int num_pages, status;
560 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
561 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
562 struct ocrdma_pa *pa;
563
564 memset(cmd, 0, sizeof(*cmd));
565 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
566
b1d58b99
NG		 567 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
568 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
569 cmd->req.rsvd_version = 1;
570 cmd->cqid_pages = num_pages;
571 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
572 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
573 cmd->async_event_bitmap = Bit(20);
574 cmd->async_cqid_ringsize = cq->id;
575 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
576 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
577 cmd->valid = OCRDMA_CREATE_MQ_VALID;
578 pa = &cmd->pa[0];
579
fe2caefc
PP		 580 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
581 status = be_roce_mcc_cmd(dev->nic_info.netdev,
582 cmd, sizeof(*cmd), NULL, NULL);
583 if (!status) {
584 mq->id = rsp->id;
585 mq->created = true;
586 }
587 return status;
588}
589
590static int ocrdma_create_mq(struct ocrdma_dev *dev)
591{
592 int status;
593
594 /* Alloc completion queue for Mailbox queue */
595 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
596 sizeof(struct ocrdma_mcqe));
597 if (status)
598 goto alloc_err;
599
600 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->meq.q);
601 if (status)
602 goto mbx_cq_free;
603
604 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
605 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
606 mutex_init(&dev->mqe_ctx.lock);
607
608 /* Alloc Mailbox queue */
609 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
610 sizeof(struct ocrdma_mqe));
611 if (status)
612 goto mbx_cq_destroy;
613 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
614 if (status)
615 goto mbx_q_free;
616 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
617 return 0;
618
619mbx_q_free:
620 ocrdma_free_q(dev, &dev->mq.sq);
621mbx_cq_destroy:
622 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
623mbx_cq_free:
624 ocrdma_free_q(dev, &dev->mq.cq);
625alloc_err:
626 return status;
627}
628
629static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
630{
631 struct ocrdma_queue_info *mbxq, *cq;
632
633 /* mqe_ctx lock synchronizes with any other pending cmds. */
634 mutex_lock(&dev->mqe_ctx.lock);
635 mbxq = &dev->mq.sq;
636 if (mbxq->created) {
637 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
638 ocrdma_free_q(dev, mbxq);
639 }
640 mutex_unlock(&dev->mqe_ctx.lock);
641
642 cq = &dev->mq.cq;
643 if (cq->created) {
644 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
645 ocrdma_free_q(dev, cq);
646 }
647}
648
649static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
650 struct ocrdma_qp *qp)
651{
652 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
653 enum ib_qp_state old_ib_qps;
654
655 if (qp == NULL)
656 BUG();
057729cb 657 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
fe2caefc
PP		 658}
659
660static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
661 struct ocrdma_ae_mcqe *cqe)
662{
663 struct ocrdma_qp *qp = NULL;
664 struct ocrdma_cq *cq = NULL;
e9db2953 665 struct ib_event ib_evt;
fe2caefc
PP		 666 int cq_event = 0;
667 int qp_event = 1;
668 int srq_event = 0;
669 int dev_event = 0;
670 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
671 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
672
673 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
674 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
675 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
676 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
677
e9db2953
RD		 678 ib_evt.device = &dev->ibdev;
679
fe2caefc
PP		 680 switch (type) {
681 case OCRDMA_CQ_ERROR:
682 ib_evt.element.cq = &cq->ibcq;
683 ib_evt.event = IB_EVENT_CQ_ERR;
684 cq_event = 1;
685 qp_event = 0;
686 break;
687 case OCRDMA_CQ_OVERRUN_ERROR:
688 ib_evt.element.cq = &cq->ibcq;
689 ib_evt.event = IB_EVENT_CQ_ERR;
690 break;
691 case OCRDMA_CQ_QPCAT_ERROR:
692 ib_evt.element.qp = &qp->ibqp;
693 ib_evt.event = IB_EVENT_QP_FATAL;
694 ocrdma_process_qpcat_error(dev, qp);
695 break;
696 case OCRDMA_QP_ACCESS_ERROR:
697 ib_evt.element.qp = &qp->ibqp;
698 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
699 break;
700 case OCRDMA_QP_COMM_EST_EVENT:
701 ib_evt.element.qp = &qp->ibqp;
702 ib_evt.event = IB_EVENT_COMM_EST;
703 break;
704 case OCRDMA_SQ_DRAINED_EVENT:
705 ib_evt.element.qp = &qp->ibqp;
706 ib_evt.event = IB_EVENT_SQ_DRAINED;
707 break;
708 case OCRDMA_DEVICE_FATAL_EVENT:
709 ib_evt.element.port_num = 1;
710 ib_evt.event = IB_EVENT_DEVICE_FATAL;
711 qp_event = 0;
712 dev_event = 1;
713 break;
714 case OCRDMA_SRQCAT_ERROR:
715 ib_evt.element.srq = &qp->srq->ibsrq;
716 ib_evt.event = IB_EVENT_SRQ_ERR;
717 srq_event = 1;
718 qp_event = 0;
719 break;
720 case OCRDMA_SRQ_LIMIT_EVENT:
721 ib_evt.element.srq = &qp->srq->ibsrq;
804eaf29 722 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
fe2caefc
PP		 723 srq_event = 1;
724 qp_event = 0;
725 break;
726 case OCRDMA_QP_LAST_WQE_EVENT:
727 ib_evt.element.qp = &qp->ibqp;
728 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
729 break;
730 default:
731 cq_event = 0;
732 qp_event = 0;
733 srq_event = 0;
734 dev_event = 0;
ef99c4c2 735 pr_err("%s() unknown type=0x%x\n", __func__, type);
fe2caefc
PP		 736 break;
737 }
738
739 if (qp_event) {
740 if (qp->ibqp.event_handler)
741 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
742 } else if (cq_event) {
743 if (cq->ibcq.event_handler)
744 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
745 } else if (srq_event) {
746 if (qp->srq->ibsrq.event_handler)
747 qp->srq->ibsrq.event_handler(&ib_evt,
748 qp->srq->ibsrq.
749 srq_context);
f99b1649 750 } else if (dev_event) {
fe2caefc 751 ib_dispatch_event(&ib_evt);
f99b1649 752 }
fe2caefc
PP		 753
754}
755
756static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
757{
758 /* async CQE processing */
759 struct ocrdma_ae_mcqe *cqe = ae_cqe;
760 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
761 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
762
763 if (evt_code == OCRDMA_ASYNC_EVE_CODE)
764 ocrdma_dispatch_ibevent(dev, cqe);
765 else
ef99c4c2
NG		 766 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
767 dev->id, evt_code);
fe2caefc
PP		 768}
769
770static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
771{
772 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
773 dev->mqe_ctx.cqe_status = (cqe->status &
774 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
775 dev->mqe_ctx.ext_status =
776 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
777 >> OCRDMA_MCQE_ESTATUS_SHIFT;
778 dev->mqe_ctx.cmd_done = true;
779 wake_up(&dev->mqe_ctx.cmd_wait);
780 } else
ef99c4c2
NG		 781 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
782 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
fe2caefc
PP		 783}
784
785static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
786{
787 u16 cqe_popped = 0;
788 struct ocrdma_mcqe *cqe;
789
790 while (1) {
791 cqe = ocrdma_get_mcqe(dev);
792 if (cqe == NULL)
793 break;
794 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
795 cqe_popped += 1;
796 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
797 ocrdma_process_acqe(dev, cqe);
798 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
799 ocrdma_process_mcqe(dev, cqe);
800 else
ef99c4c2 801 pr_err("%s() cqe->compl is not set.\n", __func__);
fe2caefc
PP		 802 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
803 ocrdma_mcq_inc_tail(dev);
804 }
805 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
806 return 0;
807}
808
809static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
810 struct ocrdma_cq *cq)
811{
812 unsigned long flags;
813 struct ocrdma_qp *qp;
814 bool buddy_cq_found = false;
815 /* Go through list of QPs in error state which are using this CQ
816 * and invoke its callback handler to trigger CQE processing for
817 * error/flushed CQE. It is rare to find more than few entries in
818 * this list as most consumers stops after getting error CQE.
819 * List is traversed only once when a matching buddy cq found for a QP.
820 */
821 spin_lock_irqsave(&dev->flush_q_lock, flags);
822 list_for_each_entry(qp, &cq->sq_head, sq_entry) {
823 if (qp->srq)
824 continue;
825 /* if wq and rq share the same cq, than comp_handler
826 * is already invoked.
827 */
828 if (qp->sq_cq == qp->rq_cq)
829 continue;
830 /* if completion came on sq, rq's cq is buddy cq.
831 * if completion came on rq, sq's cq is buddy cq.
832 */
833 if (qp->sq_cq == cq)
834 cq = qp->rq_cq;
835 else
836 cq = qp->sq_cq;
837 buddy_cq_found = true;
838 break;
839 }
840 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
841 if (buddy_cq_found == false)
842 return;
843 if (cq->ibcq.comp_handler) {
844 spin_lock_irqsave(&cq->comp_handler_lock, flags);
845 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
846 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
847 }
848}
849
850static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
851{
852 unsigned long flags;
853 struct ocrdma_cq *cq;
854
855 if (cq_idx >= OCRDMA_MAX_CQ)
856 BUG();
857
858 cq = dev->cq_tbl[cq_idx];
859 if (cq == NULL) {
ef99c4c2 860 pr_err("%s%d invalid id=0x%x\n", __func__, dev->id, cq_idx);
fe2caefc
PP		 861 return;
862 }
863 spin_lock_irqsave(&cq->cq_lock, flags);
864 cq->armed = false;
865 cq->solicited = false;
866 spin_unlock_irqrestore(&cq->cq_lock, flags);
867
868 ocrdma_ring_cq_db(dev, cq->id, false, false, 0);
869
870 if (cq->ibcq.comp_handler) {
871 spin_lock_irqsave(&cq->comp_handler_lock, flags);
872 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
873 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
874 }
875 ocrdma_qp_buddy_cq_handler(dev, cq);
876}
877
878static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
879{
880 /* process the MQ-CQE. */
881 if (cq_id == dev->mq.cq.id)
882 ocrdma_mq_cq_handler(dev, cq_id);
883 else
884 ocrdma_qp_cq_handler(dev, cq_id);
885}
886
887static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
888{
889 struct ocrdma_eq *eq = handle;
890 struct ocrdma_dev *dev = eq->dev;
891 struct ocrdma_eqe eqe;
892 struct ocrdma_eqe *ptr;
893 u16 eqe_popped = 0;
894 u16 cq_id;
895 while (1) {
896 ptr = ocrdma_get_eqe(eq);
897 eqe = *ptr;
898 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
899 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
900 break;
901 eqe_popped += 1;
902 ptr->id_valid = 0;
903 /* check whether its CQE or not. */
904 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
905 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
906 ocrdma_cq_handler(dev, cq_id);
907 }
908 ocrdma_eq_inc_tail(eq);
909 }
910 ocrdma_ring_eq_db(dev, eq->q.id, true, true, eqe_popped);
911 /* Ring EQ doorbell with num_popped to 0 to enable interrupts again. */
912 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
913 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
914 return IRQ_HANDLED;
915}
916
917static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
918{
919 struct ocrdma_mqe *mqe;
920
921 dev->mqe_ctx.tag = dev->mq.sq.head;
922 dev->mqe_ctx.cmd_done = false;
923 mqe = ocrdma_get_mqe(dev);
924 cmd->hdr.tag_lo = dev->mq.sq.head;
925 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
926 /* make sure descriptor is written before ringing doorbell */
927 wmb();
928 ocrdma_mq_inc_head(dev);
929 ocrdma_ring_mq_db(dev);
930}
931
932static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
933{
934 long status;
935 /* 30 sec timeout */
936 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
937 (dev->mqe_ctx.cmd_done != false),
938 msecs_to_jiffies(30000));
939 if (status)
940 return 0;
941 else
942 return -1;
943}
944
945/* issue a mailbox command on the MQ */
946static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
947{
948 int status = 0;
949 u16 cqe_status, ext_status;
950 struct ocrdma_mqe *rsp;
951
952 mutex_lock(&dev->mqe_ctx.lock);
953 ocrdma_post_mqe(dev, mqe);
954 status = ocrdma_wait_mqe_cmpl(dev);
955 if (status)
956 goto mbx_err;
957 cqe_status = dev->mqe_ctx.cqe_status;
958 ext_status = dev->mqe_ctx.ext_status;
959 rsp = ocrdma_get_mqe_rsp(dev);
960 ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe)));
961 if (cqe_status || ext_status) {
f99b1649
NG		 962 pr_err("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n",
963 __func__,
fe2caefc
PP		 964 (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
965 OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status);
966 status = ocrdma_get_mbx_cqe_errno(cqe_status);
967 goto mbx_err;
968 }
969 if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)
970 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
971mbx_err:
972 mutex_unlock(&dev->mqe_ctx.lock);
973 return status;
974}
975
976static void ocrdma_get_attr(struct ocrdma_dev *dev,
977 struct ocrdma_dev_attr *attr,
978 struct ocrdma_mbx_query_config *rsp)
979{
fe2caefc
PP		 980 attr->max_pd =
981 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
982 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
983 attr->max_qp =
984 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
985 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
986 attr->max_send_sge = ((rsp->max_write_send_sge &
987 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
988 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
989 attr->max_recv_sge = (rsp->max_write_send_sge &
990 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
991 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
634c5796
MV		 992 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
993 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
994 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
45e86b33
NG		 995 attr->max_rdma_sge = (rsp->max_write_send_sge &
996 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
997 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
fe2caefc
PP		 998 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
999 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1000 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1001 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1002 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1003 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1004 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1005 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1006 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1007 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1008 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1009 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1010 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1011 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1012 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1013 attr->max_mr = rsp->max_mr;
1014 attr->max_mr_size = ~0ull;
1015 attr->max_fmr = 0;
1016 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1017 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1018 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1019 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1020 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1021 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1022 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1023 OCRDMA_WQE_STRIDE;
1024 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1025 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1026 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1027 OCRDMA_WQE_STRIDE;
1028 attr->max_inline_data =
1029 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1030 sizeof(struct ocrdma_sge));
fe2caefc 1031 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
fe2caefc
PP		 1032 attr->ird = 1;
1033 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1034 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
07bb5424
MV		 1035 }
1036 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1037 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1038 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1039 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
fe2caefc
PP		 1040}
1041
1042static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1043 struct ocrdma_fw_conf_rsp *conf)
1044{
1045 u32 fn_mode;
1046
1047 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1048 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1049 return -EINVAL;
1050 dev->base_eqid = conf->base_eqid;
1051 dev->max_eq = conf->max_eq;
1052 dev->attr.max_cq = OCRDMA_MAX_CQ - 1;
1053 return 0;
1054}
1055
1056/* can be issued only during init time. */
1057static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1058{
1059 int status = -ENOMEM;
1060 struct ocrdma_mqe *cmd;
1061 struct ocrdma_fw_ver_rsp *rsp;
1062
1063 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1064 if (!cmd)
1065 return -ENOMEM;
1066 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1067 OCRDMA_CMD_GET_FW_VER,
1068 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1069
1070 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1071 if (status)
1072 goto mbx_err;
1073 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1074 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1075 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1076 sizeof(rsp->running_ver));
1077 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1078mbx_err:
1079 kfree(cmd);
1080 return status;
1081}
1082
1083/* can be issued only during init time. */
1084static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1085{
1086 int status = -ENOMEM;
1087 struct ocrdma_mqe *cmd;
1088 struct ocrdma_fw_conf_rsp *rsp;
1089
1090 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1091 if (!cmd)
1092 return -ENOMEM;
1093 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1094 OCRDMA_CMD_GET_FW_CONFIG,
1095 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1096 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1097 if (status)
1098 goto mbx_err;
1099 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1100 status = ocrdma_check_fw_config(dev, rsp);
1101mbx_err:
1102 kfree(cmd);
1103 return status;
1104}
1105
1106static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1107{
1108 int status = -ENOMEM;
1109 struct ocrdma_mbx_query_config *rsp;
1110 struct ocrdma_mqe *cmd;
1111
1112 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1113 if (!cmd)
1114 return status;
1115 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1116 if (status)
1117 goto mbx_err;
1118 rsp = (struct ocrdma_mbx_query_config *)cmd;
1119 ocrdma_get_attr(dev, &dev->attr, rsp);
1120mbx_err:
1121 kfree(cmd);
1122 return status;
1123}
1124
1125int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1126{
1127 int status = -ENOMEM;
1128 struct ocrdma_alloc_pd *cmd;
1129 struct ocrdma_alloc_pd_rsp *rsp;
1130
1131 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1132 if (!cmd)
1133 return status;
1134 if (pd->dpp_enabled)
1135 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1136 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1137 if (status)
1138 goto mbx_err;
1139 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1140 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1141 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1142 pd->dpp_enabled = true;
1143 pd->dpp_page = rsp->dpp_page_pdid >>
1144 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1145 } else {
1146 pd->dpp_enabled = false;
1147 pd->num_dpp_qp = 0;
1148 }
1149mbx_err:
1150 kfree(cmd);
1151 return status;
1152}
1153
1154int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1155{
1156 int status = -ENOMEM;
1157 struct ocrdma_dealloc_pd *cmd;
1158
1159 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1160 if (!cmd)
1161 return status;
1162 cmd->id = pd->id;
1163 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1164 kfree(cmd);
1165 return status;
1166}
1167
1168static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1169 int *num_pages, int *page_size)
1170{
1171 int i;
1172 int mem_size;
1173
1174 *num_entries = roundup_pow_of_two(*num_entries);
1175 mem_size = *num_entries * entry_size;
1176 /* find the possible lowest possible multiplier */
1177 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1178 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1179 break;
1180 }
1181 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1182 return -EINVAL;
1183 mem_size = roundup(mem_size,
1184 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1185 *num_pages =
1186 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1187 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1188 *num_entries = mem_size / entry_size;
1189 return 0;
1190}
1191
1192static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1193{
1194 int i ;
1195 int status = 0;
1196 int max_ah;
1197 struct ocrdma_create_ah_tbl *cmd;
1198 struct ocrdma_create_ah_tbl_rsp *rsp;
1199 struct pci_dev *pdev = dev->nic_info.pdev;
1200 dma_addr_t pa;
1201 struct ocrdma_pbe *pbes;
1202
1203 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1204 if (!cmd)
1205 return status;
1206
1207 max_ah = OCRDMA_MAX_AH;
1208 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1209
1210 /* number of PBEs in PBL */
1211 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1212 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1213 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1214
1215 /* page size */
1216 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1217 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1218 break;
1219 }
1220 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1221 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1222
1223 /* ah_entry size */
1224 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1225 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1226 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1227
1228 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1229 &dev->av_tbl.pbl.pa,
1230 GFP_KERNEL);
1231 if (dev->av_tbl.pbl.va == NULL)
1232 goto mem_err;
1233
1234 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1235 &pa, GFP_KERNEL);
1236 if (dev->av_tbl.va == NULL)
1237 goto mem_err_ah;
1238 dev->av_tbl.pa = pa;
1239 dev->av_tbl.num_ah = max_ah;
1240 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1241
1242 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1243 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1244 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1245 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1246 pa += PAGE_SIZE;
1247 }
1248 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1249 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1250 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1251 if (status)
1252 goto mbx_err;
1253 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1254 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1255 kfree(cmd);
1256 return 0;
1257
1258mbx_err:
1259 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1260 dev->av_tbl.pa);
1261 dev->av_tbl.va = NULL;
1262mem_err_ah:
1263 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1264 dev->av_tbl.pbl.pa);
1265 dev->av_tbl.pbl.va = NULL;
1266 dev->av_tbl.size = 0;
1267mem_err:
1268 kfree(cmd);
1269 return status;
1270}
1271
1272static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1273{
1274 struct ocrdma_delete_ah_tbl *cmd;
1275 struct pci_dev *pdev = dev->nic_info.pdev;
1276
1277 if (dev->av_tbl.va == NULL)
1278 return;
1279
1280 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1281 if (!cmd)
1282 return;
1283 cmd->ahid = dev->av_tbl.ahid;
1284
1285 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1286 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1287 dev->av_tbl.pa);
1288 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1289 dev->av_tbl.pbl.pa);
1290 kfree(cmd);
1291}
1292
1293/* Multiple CQs uses the EQ. This routine returns least used
1294 * EQ to associate with CQ. This will distributes the interrupt
1295 * processing and CPU load to associated EQ, vector and so to that CPU.
1296 */
1297static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1298{
1299 int i, selected_eq = 0, cq_cnt = 0;
1300 u16 eq_id;
1301
1302 mutex_lock(&dev->dev_lock);
1303 cq_cnt = dev->qp_eq_tbl[0].cq_cnt;
1304 eq_id = dev->qp_eq_tbl[0].q.id;
1305 /* find the EQ which is has the least number of
1306 * CQs associated with it.
1307 */
1308 for (i = 0; i < dev->eq_cnt; i++) {
1309 if (dev->qp_eq_tbl[i].cq_cnt < cq_cnt) {
1310 cq_cnt = dev->qp_eq_tbl[i].cq_cnt;
1311 eq_id = dev->qp_eq_tbl[i].q.id;
1312 selected_eq = i;
1313 }
1314 }
1315 dev->qp_eq_tbl[selected_eq].cq_cnt += 1;
1316 mutex_unlock(&dev->dev_lock);
1317 return eq_id;
1318}
1319
1320static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1321{
1322 int i;
1323
1324 mutex_lock(&dev->dev_lock);
1325 for (i = 0; i < dev->eq_cnt; i++) {
1326 if (dev->qp_eq_tbl[i].q.id != eq_id)
1327 continue;
1328 dev->qp_eq_tbl[i].cq_cnt -= 1;
1329 break;
1330 }
1331 mutex_unlock(&dev->dev_lock);
1332}
1333
1334int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1335 int entries, int dpp_cq)
1336{
1337 int status = -ENOMEM; int max_hw_cqe;
1338 struct pci_dev *pdev = dev->nic_info.pdev;
1339 struct ocrdma_create_cq *cmd;
1340 struct ocrdma_create_cq_rsp *rsp;
1341 u32 hw_pages, cqe_size, page_size, cqe_count;
1342
1343 if (dpp_cq)
1344 return -EINVAL;
1345 if (entries > dev->attr.max_cqe) {
ef99c4c2
NG		 1346 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1347 __func__, dev->id, dev->attr.max_cqe, entries);
fe2caefc
PP		 1348 return -EINVAL;
1349 }
1350 if (dpp_cq && (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY))
1351 return -EINVAL;
1352
1353 if (dpp_cq) {
1354 cq->max_hw_cqe = 1;
1355 max_hw_cqe = 1;
1356 cqe_size = OCRDMA_DPP_CQE_SIZE;
1357 hw_pages = 1;
1358 } else {
1359 cq->max_hw_cqe = dev->attr.max_cqe;
1360 max_hw_cqe = dev->attr.max_cqe;
1361 cqe_size = sizeof(struct ocrdma_cqe);
1362 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1363 }
1364
1365 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1366
1367 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1368 if (!cmd)
1369 return -ENOMEM;
1370 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1371 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1372 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1373 if (!cq->va) {
1374 status = -ENOMEM;
1375 goto mem_err;
1376 }
1377 memset(cq->va, 0, cq->len);
1378 page_size = cq->len / hw_pages;
1379 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1380 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1381 cmd->cmd.pgsz_pgcnt |= hw_pages;
1382 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1383
fe2caefc
PP		 1384 cq->eqn = ocrdma_bind_eq(dev);
1385 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
1386 cqe_count = cq->len / cqe_size;
f99b1649 1387 if (cqe_count > 1024) {
fe2caefc
PP		 1388 /* Set cnt to 3 to indicate more than 1024 cq entries */
1389 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
f99b1649 1390 } else {
fe2caefc
PP		 1391 u8 count = 0;
1392 switch (cqe_count) {
1393 case 256:
1394 count = 0;
1395 break;
1396 case 512:
1397 count = 1;
1398 break;
1399 case 1024:
1400 count = 2;
1401 break;
1402 default:
1403 goto mbx_err;
1404 }
1405 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1406 }
1407 /* shared eq between all the consumer cqs. */
1408 cmd->cmd.eqn = cq->eqn;
1409 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1410 if (dpp_cq)
1411 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1412 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1413 cq->phase_change = false;
1414 cmd->cmd.cqe_count = (cq->len / cqe_size);
1415 } else {
1416 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1417 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1418 cq->phase_change = true;
1419 }
1420
1421 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1422 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1423 if (status)
1424 goto mbx_err;
1425
1426 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1427 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1428 kfree(cmd);
1429 return 0;
1430mbx_err:
1431 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc
PP		 1432 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1433mem_err:
1434 kfree(cmd);
1435 return status;
1436}
1437
1438int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1439{
1440 int status = -ENOMEM;
1441 struct ocrdma_destroy_cq *cmd;
1442
1443 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1444 if (!cmd)
1445 return status;
1446 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1447 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1448
1449 cmd->bypass_flush_qid |=
1450 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1451 OCRDMA_DESTROY_CQ_QID_MASK;
1452
1453 ocrdma_unbind_eq(dev, cq->eqn);
1454 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1455 if (status)
1456 goto mbx_err;
1457 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1458mbx_err:
1459 kfree(cmd);
1460 return status;
1461}
1462
1463int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1464 u32 pdid, int addr_check)
1465{
1466 int status = -ENOMEM;
1467 struct ocrdma_alloc_lkey *cmd;
1468 struct ocrdma_alloc_lkey_rsp *rsp;
1469
1470 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1471 if (!cmd)
1472 return status;
1473 cmd->pdid = pdid;
1474 cmd->pbl_sz_flags |= addr_check;
1475 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1476 cmd->pbl_sz_flags |=
1477 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1478 cmd->pbl_sz_flags |=
1479 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1480 cmd->pbl_sz_flags |=
1481 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1482 cmd->pbl_sz_flags |=
1483 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1484 cmd->pbl_sz_flags |=
1485 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1486
1487 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1488 if (status)
1489 goto mbx_err;
1490 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1491 hwmr->lkey = rsp->lrkey;
1492mbx_err:
1493 kfree(cmd);
1494 return status;
1495}
1496
1497int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1498{
1499 int status = -ENOMEM;
1500 struct ocrdma_dealloc_lkey *cmd;
1501
1502 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1503 if (!cmd)
1504 return -ENOMEM;
1505 cmd->lkey = lkey;
1506 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1507 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1508 if (status)
1509 goto mbx_err;
1510mbx_err:
1511 kfree(cmd);
1512 return status;
1513}
1514
1515static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1516 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1517{
1518 int status = -ENOMEM;
1519 int i;
1520 struct ocrdma_reg_nsmr *cmd;
1521 struct ocrdma_reg_nsmr_rsp *rsp;
1522
1523 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1524 if (!cmd)
1525 return -ENOMEM;
1526 cmd->num_pbl_pdid =
1527 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1528
1529 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1530 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1531 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1532 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1533 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1534 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1535 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1536 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1537 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1538 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1539 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1540
1541 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1542 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1543 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1544 cmd->totlen_low = hwmr->len;
1545 cmd->totlen_high = upper_32_bits(hwmr->len);
1546 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1547 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1548 cmd->va_loaddr = (u32) hwmr->va;
1549 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1550
1551 for (i = 0; i < pbl_cnt; i++) {
1552 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1553 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1554 }
1555 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1556 if (status)
1557 goto mbx_err;
1558 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1559 hwmr->lkey = rsp->lrkey;
1560mbx_err:
1561 kfree(cmd);
1562 return status;
1563}
1564
1565static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1566 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1567 u32 pbl_offset, u32 last)
1568{
1569 int status = -ENOMEM;
1570 int i;
1571 struct ocrdma_reg_nsmr_cont *cmd;
1572
1573 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1574 if (!cmd)
1575 return -ENOMEM;
1576 cmd->lrkey = hwmr->lkey;
1577 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1578 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1579 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1580
1581 for (i = 0; i < pbl_cnt; i++) {
1582 cmd->pbl[i].lo =
1583 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1584 cmd->pbl[i].hi =
1585 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1586 }
1587 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1588 if (status)
1589 goto mbx_err;
1590mbx_err:
1591 kfree(cmd);
1592 return status;
1593}
1594
1595int ocrdma_reg_mr(struct ocrdma_dev *dev,
1596 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1597{
1598 int status;
1599 u32 last = 0;
1600 u32 cur_pbl_cnt, pbl_offset;
1601 u32 pending_pbl_cnt = hwmr->num_pbls;
1602
1603 pbl_offset = 0;
1604 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1605 if (cur_pbl_cnt == pending_pbl_cnt)
1606 last = 1;
1607
1608 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1609 cur_pbl_cnt, hwmr->pbe_size, last);
1610 if (status) {
ef99c4c2 1611 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 1612 return status;
1613 }
1614 /* if there is no more pbls to register then exit. */
1615 if (last)
1616 return 0;
1617
1618 while (!last) {
1619 pbl_offset += cur_pbl_cnt;
1620 pending_pbl_cnt -= cur_pbl_cnt;
1621 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1622 /* if we reach the end of the pbls, then need to set the last
1623 * bit, indicating no more pbls to register for this memory key.
1624 */
1625 if (cur_pbl_cnt == pending_pbl_cnt)
1626 last = 1;
1627
1628 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1629 pbl_offset, last);
1630 if (status)
1631 break;
1632 }
1633 if (status)
ef99c4c2 1634 pr_err("%s() err. status=%d\n", __func__, status);
fe2caefc
PP		 1635
1636 return status;
1637}
1638
1639bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1640{
1641 struct ocrdma_qp *tmp;
1642 bool found = false;
1643 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1644 if (qp == tmp) {
1645 found = true;
1646 break;
1647 }
1648 }
1649 return found;
1650}
1651
1652bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1653{
1654 struct ocrdma_qp *tmp;
1655 bool found = false;
1656 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1657 if (qp == tmp) {
1658 found = true;
1659 break;
1660 }
1661 }
1662 return found;
1663}
1664
1665void ocrdma_flush_qp(struct ocrdma_qp *qp)
1666{
1667 bool found;
1668 unsigned long flags;
1669
1670 spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1671 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1672 if (!found)
1673 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1674 if (!qp->srq) {
1675 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1676 if (!found)
1677 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1678 }
1679 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1680}
1681
057729cb
NG		 1682int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1683 enum ib_qp_state *old_ib_state)
fe2caefc
PP		 1684{
1685 unsigned long flags;
1686 int status = 0;
1687 enum ocrdma_qp_state new_state;
1688 new_state = get_ocrdma_qp_state(new_ib_state);
1689
1690 /* sync with wqe and rqe posting */
1691 spin_lock_irqsave(&qp->q_lock, flags);
1692
1693 if (old_ib_state)
1694 *old_ib_state = get_ibqp_state(qp->state);
1695 if (new_state == qp->state) {
1696 spin_unlock_irqrestore(&qp->q_lock, flags);
1697 return 1;
1698 }
1699
057729cb
NG		 1700
1701 if (new_state == OCRDMA_QPS_ERR)
1702 ocrdma_flush_qp(qp);
1703
1704 qp->state = new_state;
fe2caefc
PP		 1705
1706 spin_unlock_irqrestore(&qp->q_lock, flags);
1707 return status;
1708}
1709
1710static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1711{
1712 u32 flags = 0;
1713 if (qp->cap_flags & OCRDMA_QP_INB_RD)
1714 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1715 if (qp->cap_flags & OCRDMA_QP_INB_WR)
1716 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1717 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1718 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1719 if (qp->cap_flags & OCRDMA_QP_LKEY0)
1720 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1721 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1722 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1723 return flags;
1724}
1725
1726static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1727 struct ib_qp_init_attr *attrs,
1728 struct ocrdma_qp *qp)
1729{
1730 int status;
1731 u32 len, hw_pages, hw_page_size;
1732 dma_addr_t pa;
1733 struct ocrdma_dev *dev = qp->dev;
1734 struct pci_dev *pdev = dev->nic_info.pdev;
1735 u32 max_wqe_allocated;
1736 u32 max_sges = attrs->cap.max_send_sge;
1737
1738 max_wqe_allocated = attrs->cap.max_send_wr;
1739 /* need to allocate one extra to for GEN1 family */
1740 if (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY)
1741 max_wqe_allocated += 1;
1742
1743 status = ocrdma_build_q_conf(&max_wqe_allocated,
1744 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1745 if (status) {
ef99c4c2
NG		 1746 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1747 max_wqe_allocated);
fe2caefc
PP		 1748 return -EINVAL;
1749 }
1750 qp->sq.max_cnt = max_wqe_allocated;
1751 len = (hw_pages * hw_page_size);
1752
1753 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1754 if (!qp->sq.va)
1755 return -EINVAL;
1756 memset(qp->sq.va, 0, len);
1757 qp->sq.len = len;
1758 qp->sq.pa = pa;
1759 qp->sq.entry_size = dev->attr.wqe_size;
1760 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1761
1762 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1763 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1764 cmd->num_wq_rq_pages |= (hw_pages <<
1765 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1766 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1767 cmd->max_sge_send_write |= (max_sges <<
1768 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1769 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1770 cmd->max_sge_send_write |= (max_sges <<
1771 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1772 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1773 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1774 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1775 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1776 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
1777 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
1778 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
1779 return 0;
1780}
1781
1782static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
1783 struct ib_qp_init_attr *attrs,
1784 struct ocrdma_qp *qp)
1785{
1786 int status;
1787 u32 len, hw_pages, hw_page_size;
1788 dma_addr_t pa = 0;
1789 struct ocrdma_dev *dev = qp->dev;
1790 struct pci_dev *pdev = dev->nic_info.pdev;
1791 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
1792
1793 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
1794 &hw_pages, &hw_page_size);
1795 if (status) {
ef99c4c2
NG		 1796 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
1797 attrs->cap.max_recv_wr + 1);
fe2caefc
PP		 1798 return status;
1799 }
1800 qp->rq.max_cnt = max_rqe_allocated;
1801 len = (hw_pages * hw_page_size);
1802
1803 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1804 if (!qp->rq.va)
c94e15c5 1805 return -ENOMEM;
fe2caefc
PP		 1806 memset(qp->rq.va, 0, len);
1807 qp->rq.pa = pa;
1808 qp->rq.len = len;
1809 qp->rq.entry_size = dev->attr.rqe_size;
1810
1811 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
1812 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1813 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
1814 cmd->num_wq_rq_pages |=
1815 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
1816 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
1817 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
1818 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
1819 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
1820 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
1821 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
1822 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
1823 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
1824 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
1825 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
1826 return 0;
1827}
1828
1829static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
1830 struct ocrdma_pd *pd,
1831 struct ocrdma_qp *qp,
1832 u8 enable_dpp_cq, u16 dpp_cq_id)
1833{
1834 pd->num_dpp_qp--;
1835 qp->dpp_enabled = true;
1836 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1837 if (!enable_dpp_cq)
1838 return;
1839 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1840 cmd->dpp_credits_cqid = dpp_cq_id;
1841 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
1842 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
1843}
1844
1845static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
1846 struct ocrdma_qp *qp)
1847{
1848 struct ocrdma_dev *dev = qp->dev;
1849 struct pci_dev *pdev = dev->nic_info.pdev;
1850 dma_addr_t pa = 0;
1851 int ird_page_size = dev->attr.ird_page_size;
1852 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
1853
1854 if (dev->attr.ird == 0)
1855 return 0;
1856
1857 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
1858 &pa, GFP_KERNEL);
1859 if (!qp->ird_q_va)
1860 return -ENOMEM;
1861 memset(qp->ird_q_va, 0, ird_q_len);
1862 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
1863 pa, ird_page_size);
1864 return 0;
1865}
1866
1867static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
1868 struct ocrdma_qp *qp,
1869 struct ib_qp_init_attr *attrs,
1870 u16 *dpp_offset, u16 *dpp_credit_lmt)
1871{
1872 u32 max_wqe_allocated, max_rqe_allocated;
1873 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
1874 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
1875 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
1876 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
1877 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
1878 qp->dpp_enabled = false;
1879 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
1880 qp->dpp_enabled = true;
1881 *dpp_credit_lmt = (rsp->dpp_response &
1882 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
1883 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
1884 *dpp_offset = (rsp->dpp_response &
1885 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
1886 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
1887 }
1888 max_wqe_allocated =
1889 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
1890 max_wqe_allocated = 1 << max_wqe_allocated;
1891 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
1892
fe2caefc
PP		 1893 qp->sq.max_cnt = max_wqe_allocated;
1894 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
1895
1896 if (!attrs->srq) {
1897 qp->rq.max_cnt = max_rqe_allocated;
1898 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
fe2caefc
PP		 1899 }
1900}
1901
1902int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
1903 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
1904 u16 *dpp_credit_lmt)
1905{
1906 int status = -ENOMEM;
1907 u32 flags = 0;
1908 struct ocrdma_dev *dev = qp->dev;
1909 struct ocrdma_pd *pd = qp->pd;
1910 struct pci_dev *pdev = dev->nic_info.pdev;
1911 struct ocrdma_cq *cq;
1912 struct ocrdma_create_qp_req *cmd;
1913 struct ocrdma_create_qp_rsp *rsp;
1914 int qptype;
1915
1916 switch (attrs->qp_type) {
1917 case IB_QPT_GSI:
1918 qptype = OCRDMA_QPT_GSI;
1919 break;
1920 case IB_QPT_RC:
1921 qptype = OCRDMA_QPT_RC;
1922 break;
1923 case IB_QPT_UD:
1924 qptype = OCRDMA_QPT_UD;
1925 break;
1926 default:
1927 return -EINVAL;
1928 };
1929
1930 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
1931 if (!cmd)
1932 return status;
1933 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
1934 OCRDMA_CREATE_QP_REQ_QPT_MASK;
1935 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
1936 if (status)
1937 goto sq_err;
1938
1939 if (attrs->srq) {
1940 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
1941 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
1942 cmd->rq_addr[0].lo = srq->id;
1943 qp->srq = srq;
1944 } else {
1945 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
1946 if (status)
1947 goto rq_err;
1948 }
1949
1950 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
1951 if (status)
1952 goto mbx_err;
1953
1954 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
1955 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
1956
1957 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
1958
1959 cmd->max_sge_recv_flags |= flags;
1960 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
1961 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
1962 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
1963 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
1964 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
1965 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
1966 cq = get_ocrdma_cq(attrs->send_cq);
1967 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
1968 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
1969 qp->sq_cq = cq;
1970 cq = get_ocrdma_cq(attrs->recv_cq);
1971 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
1972 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
1973 qp->rq_cq = cq;
1974
1975 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
f99b1649 1976 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
fe2caefc
PP		 1977 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
1978 dpp_cq_id);
f99b1649 1979 }
fe2caefc
PP		 1980
1981 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1982 if (status)
1983 goto mbx_err;
1984 rsp = (struct ocrdma_create_qp_rsp *)cmd;
1985 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
1986 qp->state = OCRDMA_QPS_RST;
1987 kfree(cmd);
1988 return 0;
1989mbx_err:
1990 if (qp->rq.va)
1991 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
1992rq_err:
ef99c4c2 1993 pr_err("%s(%d) rq_err\n", __func__, dev->id);
fe2caefc
PP		 1994 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
1995sq_err:
ef99c4c2 1996 pr_err("%s(%d) sq_err\n", __func__, dev->id);
fe2caefc
PP		 1997 kfree(cmd);
1998 return status;
1999}
2000
2001int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2002 struct ocrdma_qp_params *param)
2003{
2004 int status = -ENOMEM;
2005 struct ocrdma_query_qp *cmd;
2006 struct ocrdma_query_qp_rsp *rsp;
2007
2008 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2009 if (!cmd)
2010 return status;
2011 cmd->qp_id = qp->id;
2012 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2013 if (status)
2014 goto mbx_err;
2015 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2016 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2017mbx_err:
2018 kfree(cmd);
2019 return status;
2020}
2021
2022int ocrdma_resolve_dgid(struct ocrdma_dev *dev, union ib_gid *dgid,
2023 u8 *mac_addr)
2024{
2025 struct in6_addr in6;
2026
2027 memcpy(&in6, dgid, sizeof in6);
f99b1649 2028 if (rdma_is_multicast_addr(&in6)) {
fe2caefc 2029 rdma_get_mcast_mac(&in6, mac_addr);
f99b1649 2030 } else if (rdma_link_local_addr(&in6)) {
fe2caefc 2031 rdma_get_ll_mac(&in6, mac_addr);
f99b1649 2032 } else {
ef99c4c2 2033 pr_err("%s() fail to resolve mac_addr.\n", __func__);
fe2caefc
PP		 2034 return -EINVAL;
2035 }
2036 return 0;
2037}
2038
f99b1649 2039static int ocrdma_set_av_params(struct ocrdma_qp *qp,
fe2caefc
PP		 2040 struct ocrdma_modify_qp *cmd,
2041 struct ib_qp_attr *attrs)
2042{
f99b1649 2043 int status;
fe2caefc 2044 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
9c58726b 2045 union ib_gid sgid, zgid;
fe2caefc
PP		 2046 u32 vlan_id;
2047 u8 mac_addr[6];
9c58726b 2048
fe2caefc 2049 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
f99b1649 2050 return -EINVAL;
fe2caefc
PP		 2051 cmd->params.tclass_sq_psn |=
2052 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2053 cmd->params.rnt_rc_sl_fl |=
2054 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2055 cmd->params.hop_lmt_rq_psn |=
2056 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2057 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2058 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2059 sizeof(cmd->params.dgid));
f99b1649 2060 status = ocrdma_query_gid(&qp->dev->ibdev, 1,
fe2caefc 2061 ah_attr->grh.sgid_index, &sgid);
f99b1649
NG		 2062 if (status)
2063 return status;
9c58726b
NG		 2064
2065 memset(&zgid, 0, sizeof(zgid));
2066 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2067 return -EINVAL;
2068
fe2caefc
PP		 2069 qp->sgid_idx = ah_attr->grh.sgid_index;
2070 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2071 ocrdma_resolve_dgid(qp->dev, &ah_attr->grh.dgid, &mac_addr[0]);
2072 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2073 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2074 /* convert them to LE format. */
2075 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2076 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2077 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2078 vlan_id = rdma_get_vlan_id(&sgid);
2079 if (vlan_id && (vlan_id < 0x1000)) {
2080 cmd->params.vlan_dmac_b4_to_b5 |=
2081 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2082 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2083 }
f99b1649 2084 return 0;
fe2caefc
PP		 2085}
2086
2087static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2088 struct ocrdma_modify_qp *cmd,
2089 struct ib_qp_attr *attrs, int attr_mask,
2090 enum ib_qp_state old_qps)
2091{
2092 int status = 0;
2093 struct net_device *netdev = qp->dev->nic_info.netdev;
2094 int eth_mtu = iboe_get_mtu(netdev->mtu);
2095
2096 if (attr_mask & IB_QP_PKEY_INDEX) {
2097 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2098 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2099 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2100 }
2101 if (attr_mask & IB_QP_QKEY) {
2102 qp->qkey = attrs->qkey;
2103 cmd->params.qkey = attrs->qkey;
2104 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2105 }
f99b1649
NG		 2106 if (attr_mask & IB_QP_AV) {
2107 status = ocrdma_set_av_params(qp, cmd, attrs);
2108 if (status)
2109 return status;
2110 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
fe2caefc
PP		 2111 /* set the default mac address for UD, GSI QPs */
2112 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2113 (qp->dev->nic_info.mac_addr[1] << 8) |
2114 (qp->dev->nic_info.mac_addr[2] << 16) |
2115 (qp->dev->nic_info.mac_addr[3] << 24);
2116 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2117 (qp->dev->nic_info.mac_addr[5] << 8);
2118 }
2119 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2120 attrs->en_sqd_async_notify) {
2121 cmd->params.max_sge_recv_flags |=
2122 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2123 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2124 }
2125 if (attr_mask & IB_QP_DEST_QPN) {
2126 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2127 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2128 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2129 }
2130 if (attr_mask & IB_QP_PATH_MTU) {
2131 if (ib_mtu_enum_to_int(eth_mtu) <
2132 ib_mtu_enum_to_int(attrs->path_mtu)) {
2133 status = -EINVAL;
2134 goto pmtu_err;
2135 }
2136 cmd->params.path_mtu_pkey_indx |=
2137 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2138 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2139 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2140 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2141 }
2142 if (attr_mask & IB_QP_TIMEOUT) {
2143 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2144 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2145 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2146 }
2147 if (attr_mask & IB_QP_RETRY_CNT) {
2148 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2149 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2150 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2151 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2152 }
2153 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2154 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2155 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2156 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2157 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2158 }
2159 if (attr_mask & IB_QP_RNR_RETRY) {
2160 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2161 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2162 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2163 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2164 }
2165 if (attr_mask & IB_QP_SQ_PSN) {
2166 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2167 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2168 }
2169 if (attr_mask & IB_QP_RQ_PSN) {
2170 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2171 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2172 }
2173 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2174 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2175 status = -EINVAL;
2176 goto pmtu_err;
2177 }
2178 qp->max_ord = attrs->max_rd_atomic;
2179 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2180 }
2181 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2182 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2183 status = -EINVAL;
2184 goto pmtu_err;
2185 }
2186 qp->max_ird = attrs->max_dest_rd_atomic;
2187 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2188 }
2189 cmd->params.max_ord_ird = (qp->max_ord <<
2190 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2191 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2192pmtu_err:
2193 return status;
2194}
2195
2196int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2197 struct ib_qp_attr *attrs, int attr_mask,
2198 enum ib_qp_state old_qps)
2199{
2200 int status = -ENOMEM;
2201 struct ocrdma_modify_qp *cmd;
fe2caefc
PP		 2202
2203 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2204 if (!cmd)
2205 return status;
2206
2207 cmd->params.id = qp->id;
2208 cmd->flags = 0;
2209 if (attr_mask & IB_QP_STATE) {
2210 cmd->params.max_sge_recv_flags |=
2211 (get_ocrdma_qp_state(attrs->qp_state) <<
2212 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2213 OCRDMA_QP_PARAMS_STATE_MASK;
2214 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
f99b1649 2215 } else {
fe2caefc
PP		 2216 cmd->params.max_sge_recv_flags |=
2217 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2218 OCRDMA_QP_PARAMS_STATE_MASK;
f99b1649
NG		 2219 }
2220
fe2caefc
PP		 2221 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask, old_qps);
2222 if (status)
2223 goto mbx_err;
2224 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2225 if (status)
2226 goto mbx_err;
c592c423 2227
fe2caefc
PP		 2228mbx_err:
2229 kfree(cmd);
2230 return status;
2231}
2232
2233int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2234{
2235 int status = -ENOMEM;
2236 struct ocrdma_destroy_qp *cmd;
fe2caefc
PP		 2237 struct pci_dev *pdev = dev->nic_info.pdev;
2238
2239 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2240 if (!cmd)
2241 return status;
2242 cmd->qp_id = qp->id;
2243 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2244 if (status)
2245 goto mbx_err;
c592c423 2246
fe2caefc
PP		 2247mbx_err:
2248 kfree(cmd);
2249 if (qp->sq.va)
2250 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2251 if (!qp->srq && qp->rq.va)
2252 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2253 if (qp->dpp_enabled)
2254 qp->pd->num_dpp_qp++;
2255 return status;
2256}
2257
1afc0454 2258int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
fe2caefc
PP		 2259 struct ib_srq_init_attr *srq_attr,
2260 struct ocrdma_pd *pd)
2261{
2262 int status = -ENOMEM;
2263 int hw_pages, hw_page_size;
2264 int len;
2265 struct ocrdma_create_srq_rsp *rsp;
2266 struct ocrdma_create_srq *cmd;
2267 dma_addr_t pa;
fe2caefc
PP		 2268 struct pci_dev *pdev = dev->nic_info.pdev;
2269 u32 max_rqe_allocated;
2270
2271 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2272 if (!cmd)
2273 return status;
2274
2275 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2276 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2277 status = ocrdma_build_q_conf(&max_rqe_allocated,
2278 dev->attr.rqe_size,
2279 &hw_pages, &hw_page_size);
2280 if (status) {
ef99c4c2
NG		 2281 pr_err("%s() req. max_wr=0x%x\n", __func__,
2282 srq_attr->attr.max_wr);
fe2caefc
PP		 2283 status = -EINVAL;
2284 goto ret;
2285 }
2286 len = hw_pages * hw_page_size;
2287 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2288 if (!srq->rq.va) {
2289 status = -ENOMEM;
2290 goto ret;
2291 }
2292 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2293
2294 srq->rq.entry_size = dev->attr.rqe_size;
2295 srq->rq.pa = pa;
2296 srq->rq.len = len;
2297 srq->rq.max_cnt = max_rqe_allocated;
2298
2299 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2300 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2301 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2302
2303 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2304 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2305 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2306 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2307 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2308 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2309
2310 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2311 if (status)
2312 goto mbx_err;
2313 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2314 srq->id = rsp->id;
2315 srq->rq.dbid = rsp->id;
2316 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2317 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2318 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2319 max_rqe_allocated = (1 << max_rqe_allocated);
2320 srq->rq.max_cnt = max_rqe_allocated;
2321 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2322 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2323 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2324 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2325 goto ret;
2326mbx_err:
2327 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2328ret:
2329 kfree(cmd);
2330 return status;
2331}
2332
2333int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2334{
2335 int status = -ENOMEM;
2336 struct ocrdma_modify_srq *cmd;
1afc0454
NG		 2337 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2338
fe2caefc
PP		 2339 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2340 if (!cmd)
2341 return status;
2342 cmd->id = srq->id;
2343 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2344 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
1afc0454 2345 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2346 kfree(cmd);
2347 return status;
2348}
2349
2350int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2351{
2352 int status = -ENOMEM;
2353 struct ocrdma_query_srq *cmd;
1afc0454
NG		 2354 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2355
fe2caefc
PP		 2356 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2357 if (!cmd)
2358 return status;
2359 cmd->id = srq->rq.dbid;
1afc0454 2360 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2361 if (status == 0) {
2362 struct ocrdma_query_srq_rsp *rsp =
2363 (struct ocrdma_query_srq_rsp *)cmd;
2364 srq_attr->max_sge =
2365 rsp->srq_lmt_max_sge &
2366 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2367 srq_attr->max_wr =
2368 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2369 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2370 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2371 }
2372 kfree(cmd);
2373 return status;
2374}
2375
2376int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2377{
2378 int status = -ENOMEM;
2379 struct ocrdma_destroy_srq *cmd;
2380 struct pci_dev *pdev = dev->nic_info.pdev;
2381 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2382 if (!cmd)
2383 return status;
2384 cmd->id = srq->id;
1afc0454 2385 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2386 if (srq->rq.va)
2387 dma_free_coherent(&pdev->dev, srq->rq.len,
2388 srq->rq.va, srq->rq.pa);
2389 kfree(cmd);
2390 return status;
2391}
2392
2393int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2394{
2395 int i;
2396 int status = -EINVAL;
2397 struct ocrdma_av *av;
2398 unsigned long flags;
2399
2400 av = dev->av_tbl.va;
2401 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2402 for (i = 0; i < dev->av_tbl.num_ah; i++) {
2403 if (av->valid == 0) {
2404 av->valid = OCRDMA_AV_VALID;
2405 ah->av = av;
2406 ah->id = i;
2407 status = 0;
2408 break;
2409 }
2410 av++;
2411 }
2412 if (i == dev->av_tbl.num_ah)
2413 status = -EAGAIN;
2414 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2415 return status;
2416}
2417
2418int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2419{
2420 unsigned long flags;
2421 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2422 ah->av->valid = 0;
2423 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2424 return 0;
2425}
2426
2427static int ocrdma_create_mq_eq(struct ocrdma_dev *dev)
2428{
2429 int status;
2430 int irq;
2431 unsigned long flags = 0;
2432 int num_eq = 0;
2433
f99b1649 2434 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
fe2caefc 2435 flags = IRQF_SHARED;
f99b1649 2436 } else {
fe2caefc
PP		 2437 num_eq = dev->nic_info.msix.num_vectors -
2438 dev->nic_info.msix.start_vector;
2439 /* minimum two vectors/eq are required for rdma to work.
2440 * one for control path and one for data path.
2441 */
2442 if (num_eq < 2)
2443 return -EBUSY;
2444 }
2445
2446 status = ocrdma_create_eq(dev, &dev->meq, OCRDMA_EQ_LEN);
2447 if (status)
2448 return status;
2449 sprintf(dev->meq.irq_name, "ocrdma_mq%d", dev->id);
2450 irq = ocrdma_get_irq(dev, &dev->meq);
2451 status = request_irq(irq, ocrdma_irq_handler, flags, dev->meq.irq_name,
2452 &dev->meq);
2453 if (status)
2454 _ocrdma_destroy_eq(dev, &dev->meq);
2455 return status;
2456}
2457
2458static int ocrdma_create_qp_eqs(struct ocrdma_dev *dev)
2459{
da496438 2460 int num_eq, i, status = 0;
fe2caefc
PP		 2461 int irq;
2462 unsigned long flags = 0;
2463
2464 num_eq = dev->nic_info.msix.num_vectors -
2465 dev->nic_info.msix.start_vector;
2466 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2467 num_eq = 1;
2468 flags = IRQF_SHARED;
f99b1649 2469 } else {
fe2caefc 2470 num_eq = min_t(u32, num_eq, num_online_cpus());
f99b1649
NG		 2471 }
2472
fe2caefc
PP		 2473 dev->qp_eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2474 if (!dev->qp_eq_tbl)
2475 return -ENOMEM;
2476
2477 for (i = 0; i < num_eq; i++) {
2478 status = ocrdma_create_eq(dev, &dev->qp_eq_tbl[i],
2479 OCRDMA_EQ_LEN);
2480 if (status) {
2481 status = -EINVAL;
2482 break;
2483 }
2484 sprintf(dev->qp_eq_tbl[i].irq_name, "ocrdma_qp%d-%d",
2485 dev->id, i);
2486 irq = ocrdma_get_irq(dev, &dev->qp_eq_tbl[i]);
2487 status = request_irq(irq, ocrdma_irq_handler, flags,
2488 dev->qp_eq_tbl[i].irq_name,
2489 &dev->qp_eq_tbl[i]);
2490 if (status) {
2491 _ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
2492 status = -EINVAL;
2493 break;
2494 }
2495 dev->eq_cnt += 1;
2496 }
2497 /* one eq is sufficient for data path to work */
2498 if (dev->eq_cnt >= 1)
2499 return 0;
f99b1649 2500 ocrdma_destroy_qp_eqs(dev);
fe2caefc
PP		 2501 return status;
2502}
2503
2504int ocrdma_init_hw(struct ocrdma_dev *dev)
2505{
2506 int status;
2507 /* set up control path eq */
2508 status = ocrdma_create_mq_eq(dev);
2509 if (status)
2510 return status;
2511 /* set up data path eq */
2512 status = ocrdma_create_qp_eqs(dev);
2513 if (status)
2514 goto qpeq_err;
2515 status = ocrdma_create_mq(dev);
2516 if (status)
2517 goto mq_err;
2518 status = ocrdma_mbx_query_fw_config(dev);
2519 if (status)
2520 goto conf_err;
2521 status = ocrdma_mbx_query_dev(dev);
2522 if (status)
2523 goto conf_err;
2524 status = ocrdma_mbx_query_fw_ver(dev);
2525 if (status)
2526 goto conf_err;
2527 status = ocrdma_mbx_create_ah_tbl(dev);
2528 if (status)
2529 goto conf_err;
2530 return 0;
2531
2532conf_err:
2533 ocrdma_destroy_mq(dev);
2534mq_err:
2535 ocrdma_destroy_qp_eqs(dev);
2536qpeq_err:
2537 ocrdma_destroy_eq(dev, &dev->meq);
ef99c4c2 2538 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 2539 return status;
2540}
2541
2542void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2543{
2544 ocrdma_mbx_delete_ah_tbl(dev);
2545
2546 /* cleanup the data path eqs */
2547 ocrdma_destroy_qp_eqs(dev);
2548
2549 /* cleanup the control path */
2550 ocrdma_destroy_mq(dev);
2551 ocrdma_destroy_eq(dev, &dev->meq);
2552}
Linux 6.x block layer and io_uring tree(s)