[SG] Update drivers to use sg helpers
[linux-2.6-block.git] / drivers / infiniband / hw / mthca / mthca_memfree.c
CommitLineData
1da177e4
LT
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
56483ec1 3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
2a1d9b7f 4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
1da177e4
LT
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 *
34 * $Id$
35 */
36
dbcf31ba 37#include <linux/mm.h>
391e4dea 38#include <linux/scatterlist.h>
e8edc6e0 39#include <linux/sched.h>
391e4dea
MT
40
41#include <asm/page.h>
dbcf31ba 42
1da177e4
LT
43#include "mthca_memfree.h"
44#include "mthca_dev.h"
45#include "mthca_cmd.h"
46
47/*
48 * We allocate in as big chunks as we can, up to a maximum of 256 KB
49 * per chunk.
50 */
51enum {
52 MTHCA_ICM_ALLOC_SIZE = 1 << 18,
53 MTHCA_TABLE_CHUNK_SIZE = 1 << 18
54};
55
56483ec1 56struct mthca_user_db_table {
fd9cfdd1 57 struct mutex mutex;
56483ec1
RD
58 struct {
59 u64 uvirt;
60 struct scatterlist mem;
61 int refcount;
62 } page[0];
63};
64
391e4dea
MT
65static void mthca_free_icm_pages(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
66{
67 int i;
68
69 if (chunk->nsg > 0)
70 pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
71 PCI_DMA_BIDIRECTIONAL);
72
73 for (i = 0; i < chunk->npages; ++i)
45711f1a 74 __free_pages(sg_page(&chunk->mem[i]),
391e4dea
MT
75 get_order(chunk->mem[i].length));
76}
77
78static void mthca_free_icm_coherent(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
1da177e4 79{
1da177e4
LT
80 int i;
81
391e4dea
MT
82 for (i = 0; i < chunk->npages; ++i) {
83 dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
45711f1a 84 lowmem_page_address(sg_page(&chunk->mem[i])),
391e4dea
MT
85 sg_dma_address(&chunk->mem[i]));
86 }
87}
88
89void mthca_free_icm(struct mthca_dev *dev, struct mthca_icm *icm, int coherent)
90{
91 struct mthca_icm_chunk *chunk, *tmp;
92
1da177e4
LT
93 if (!icm)
94 return;
95
96 list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
391e4dea
MT
97 if (coherent)
98 mthca_free_icm_coherent(dev, chunk);
99 else
100 mthca_free_icm_pages(dev, chunk);
1da177e4
LT
101
102 kfree(chunk);
103 }
104
105 kfree(icm);
106}
107
391e4dea
MT
108static int mthca_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask)
109{
45711f1a
JA
110 struct page *page;
111
112 page = alloc_pages(gfp_mask, order);
113 if (!page)
391e4dea
MT
114 return -ENOMEM;
115
45711f1a 116 sg_set_page(mem, page);
391e4dea
MT
117 mem->length = PAGE_SIZE << order;
118 mem->offset = 0;
119 return 0;
120}
121
122static int mthca_alloc_icm_coherent(struct device *dev, struct scatterlist *mem,
123 int order, gfp_t gfp_mask)
124{
125 void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order, &sg_dma_address(mem),
126 gfp_mask);
127 if (!buf)
128 return -ENOMEM;
129
130 sg_set_buf(mem, buf, PAGE_SIZE << order);
131 BUG_ON(mem->offset);
132 sg_dma_len(mem) = PAGE_SIZE << order;
133 return 0;
134}
135
1da177e4 136struct mthca_icm *mthca_alloc_icm(struct mthca_dev *dev, int npages,
391e4dea 137 gfp_t gfp_mask, int coherent)
1da177e4
LT
138{
139 struct mthca_icm *icm;
140 struct mthca_icm_chunk *chunk = NULL;
141 int cur_order;
391e4dea
MT
142 int ret;
143
144 /* We use sg_set_buf for coherent allocs, which assumes low memory */
145 BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));
1da177e4
LT
146
147 icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
148 if (!icm)
149 return icm;
150
151 icm->refcount = 0;
152 INIT_LIST_HEAD(&icm->chunk_list);
153
154 cur_order = get_order(MTHCA_ICM_ALLOC_SIZE);
155
156 while (npages > 0) {
157 if (!chunk) {
158 chunk = kmalloc(sizeof *chunk,
159 gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
160 if (!chunk)
161 goto fail;
162
45711f1a 163 sg_init_table(chunk->mem, MTHCA_ICM_CHUNK_LEN);
1da177e4
LT
164 chunk->npages = 0;
165 chunk->nsg = 0;
166 list_add_tail(&chunk->list, &icm->chunk_list);
167 }
168
169 while (1 << cur_order > npages)
170 --cur_order;
171
391e4dea
MT
172 if (coherent)
173 ret = mthca_alloc_icm_coherent(&dev->pdev->dev,
174 &chunk->mem[chunk->npages],
175 cur_order, gfp_mask);
176 else
177 ret = mthca_alloc_icm_pages(&chunk->mem[chunk->npages],
178 cur_order, gfp_mask);
179
180 if (!ret) {
181 ++chunk->npages;
1da177e4 182
11282b32
RD
183 if (coherent)
184 ++chunk->nsg;
185 else if (chunk->npages == MTHCA_ICM_CHUNK_LEN) {
1da177e4
LT
186 chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
187 chunk->npages,
188 PCI_DMA_BIDIRECTIONAL);
189
190 if (chunk->nsg <= 0)
191 goto fail;
391e4dea 192 }
1da177e4 193
391e4dea 194 if (chunk->npages == MTHCA_ICM_CHUNK_LEN)
1da177e4 195 chunk = NULL;
1da177e4
LT
196
197 npages -= 1 << cur_order;
198 } else {
199 --cur_order;
200 if (cur_order < 0)
201 goto fail;
202 }
203 }
204
391e4dea 205 if (!coherent && chunk) {
1da177e4
LT
206 chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
207 chunk->npages,
208 PCI_DMA_BIDIRECTIONAL);
209
210 if (chunk->nsg <= 0)
211 goto fail;
212 }
213
214 return icm;
215
216fail:
391e4dea 217 mthca_free_icm(dev, icm, coherent);
1da177e4
LT
218 return NULL;
219}
220
221int mthca_table_get(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
222{
223 int i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
224 int ret = 0;
225 u8 status;
226
fd9cfdd1 227 mutex_lock(&table->mutex);
1da177e4
LT
228
229 if (table->icm[i]) {
230 ++table->icm[i]->refcount;
231 goto out;
232 }
233
234 table->icm[i] = mthca_alloc_icm(dev, MTHCA_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
235 (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
391e4dea 236 __GFP_NOWARN, table->coherent);
1da177e4
LT
237 if (!table->icm[i]) {
238 ret = -ENOMEM;
239 goto out;
240 }
241
242 if (mthca_MAP_ICM(dev, table->icm[i], table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
243 &status) || status) {
391e4dea 244 mthca_free_icm(dev, table->icm[i], table->coherent);
1da177e4
LT
245 table->icm[i] = NULL;
246 ret = -ENOMEM;
247 goto out;
248 }
249
250 ++table->icm[i]->refcount;
251
252out:
fd9cfdd1 253 mutex_unlock(&table->mutex);
1da177e4
LT
254 return ret;
255}
256
257void mthca_table_put(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
258{
a03a5a67 259 int i;
1da177e4
LT
260 u8 status;
261
a03a5a67
RD
262 if (!mthca_is_memfree(dev))
263 return;
264
265 i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
266
fd9cfdd1 267 mutex_lock(&table->mutex);
1da177e4
LT
268
269 if (--table->icm[i]->refcount == 0) {
270 mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
8d3ef29d
IR
271 MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
272 &status);
391e4dea 273 mthca_free_icm(dev, table->icm[i], table->coherent);
1da177e4
LT
274 table->icm[i] = NULL;
275 }
276
fd9cfdd1 277 mutex_unlock(&table->mutex);
1da177e4
LT
278}
279
391e4dea 280void *mthca_table_find(struct mthca_icm_table *table, int obj, dma_addr_t *dma_handle)
0fabd9fb 281{
391e4dea 282 int idx, offset, dma_offset, i;
0fabd9fb
MT
283 struct mthca_icm_chunk *chunk;
284 struct mthca_icm *icm;
285 struct page *page = NULL;
286
287 if (!table->lowmem)
288 return NULL;
289
fd9cfdd1 290 mutex_lock(&table->mutex);
0fabd9fb
MT
291
292 idx = (obj & (table->num_obj - 1)) * table->obj_size;
293 icm = table->icm[idx / MTHCA_TABLE_CHUNK_SIZE];
391e4dea 294 dma_offset = offset = idx % MTHCA_TABLE_CHUNK_SIZE;
0fabd9fb
MT
295
296 if (!icm)
297 goto out;
298
299 list_for_each_entry(chunk, &icm->chunk_list, list) {
300 for (i = 0; i < chunk->npages; ++i) {
391e4dea
MT
301 if (dma_handle && dma_offset >= 0) {
302 if (sg_dma_len(&chunk->mem[i]) > dma_offset)
303 *dma_handle = sg_dma_address(&chunk->mem[i]) +
304 dma_offset;
305 dma_offset -= sg_dma_len(&chunk->mem[i]);
306 }
307 /* DMA mapping can merge pages but not split them,
308 * so if we found the page, dma_handle has already
309 * been assigned to. */
46707e96 310 if (chunk->mem[i].length > offset) {
45711f1a 311 page = sg_page(&chunk->mem[i]);
6c7d2a75 312 goto out;
0fabd9fb
MT
313 }
314 offset -= chunk->mem[i].length;
315 }
316 }
317
318out:
fd9cfdd1 319 mutex_unlock(&table->mutex);
0fabd9fb
MT
320 return page ? lowmem_page_address(page) + offset : NULL;
321}
322
86562a13
RD
323int mthca_table_get_range(struct mthca_dev *dev, struct mthca_icm_table *table,
324 int start, int end)
325{
326 int inc = MTHCA_TABLE_CHUNK_SIZE / table->obj_size;
327 int i, err;
328
329 for (i = start; i <= end; i += inc) {
330 err = mthca_table_get(dev, table, i);
331 if (err)
332 goto fail;
333 }
334
335 return 0;
336
337fail:
338 while (i > start) {
339 i -= inc;
340 mthca_table_put(dev, table, i);
341 }
342
343 return err;
344}
345
346void mthca_table_put_range(struct mthca_dev *dev, struct mthca_icm_table *table,
347 int start, int end)
348{
349 int i;
350
a03a5a67
RD
351 if (!mthca_is_memfree(dev))
352 return;
353
86562a13
RD
354 for (i = start; i <= end; i += MTHCA_TABLE_CHUNK_SIZE / table->obj_size)
355 mthca_table_put(dev, table, i);
356}
357
1da177e4
LT
358struct mthca_icm_table *mthca_alloc_icm_table(struct mthca_dev *dev,
359 u64 virt, int obj_size,
360 int nobj, int reserved,
391e4dea 361 int use_lowmem, int use_coherent)
1da177e4
LT
362{
363 struct mthca_icm_table *table;
364 int num_icm;
d20a4019 365 unsigned chunk_size;
1da177e4
LT
366 int i;
367 u8 status;
368
f02b16be 369 num_icm = (obj_size * nobj + MTHCA_TABLE_CHUNK_SIZE - 1) / MTHCA_TABLE_CHUNK_SIZE;
1da177e4
LT
370
371 table = kmalloc(sizeof *table + num_icm * sizeof *table->icm, GFP_KERNEL);
372 if (!table)
373 return NULL;
374
375 table->virt = virt;
376 table->num_icm = num_icm;
377 table->num_obj = nobj;
378 table->obj_size = obj_size;
379 table->lowmem = use_lowmem;
391e4dea 380 table->coherent = use_coherent;
fd9cfdd1 381 mutex_init(&table->mutex);
1da177e4
LT
382
383 for (i = 0; i < num_icm; ++i)
384 table->icm[i] = NULL;
385
386 for (i = 0; i * MTHCA_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
d20a4019
RD
387 chunk_size = MTHCA_TABLE_CHUNK_SIZE;
388 if ((i + 1) * MTHCA_TABLE_CHUNK_SIZE > nobj * obj_size)
389 chunk_size = nobj * obj_size - i * MTHCA_TABLE_CHUNK_SIZE;
390
391 table->icm[i] = mthca_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
1da177e4 392 (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
391e4dea 393 __GFP_NOWARN, use_coherent);
1da177e4
LT
394 if (!table->icm[i])
395 goto err;
396 if (mthca_MAP_ICM(dev, table->icm[i], virt + i * MTHCA_TABLE_CHUNK_SIZE,
397 &status) || status) {
391e4dea 398 mthca_free_icm(dev, table->icm[i], table->coherent);
1da177e4
LT
399 table->icm[i] = NULL;
400 goto err;
401 }
402
403 /*
404 * Add a reference to this ICM chunk so that it never
405 * gets freed (since it contains reserved firmware objects).
406 */
407 ++table->icm[i]->refcount;
408 }
409
410 return table;
411
412err:
413 for (i = 0; i < num_icm; ++i)
414 if (table->icm[i]) {
415 mthca_UNMAP_ICM(dev, virt + i * MTHCA_TABLE_CHUNK_SIZE,
8d3ef29d
IR
416 MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
417 &status);
391e4dea 418 mthca_free_icm(dev, table->icm[i], table->coherent);
1da177e4
LT
419 }
420
421 kfree(table);
422
423 return NULL;
424}
425
426void mthca_free_icm_table(struct mthca_dev *dev, struct mthca_icm_table *table)
427{
428 int i;
429 u8 status;
430
431 for (i = 0; i < table->num_icm; ++i)
432 if (table->icm[i]) {
433 mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
8d3ef29d
IR
434 MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
435 &status);
391e4dea 436 mthca_free_icm(dev, table->icm[i], table->coherent);
1da177e4
LT
437 }
438
439 kfree(table);
440}
441
56483ec1 442static u64 mthca_uarc_virt(struct mthca_dev *dev, struct mthca_uar *uar, int page)
1da177e4
LT
443{
444 return dev->uar_table.uarc_base +
56483ec1 445 uar->index * dev->uar_table.uarc_size +
8d3ef29d 446 page * MTHCA_ICM_PAGE_SIZE;
1da177e4
LT
447}
448
56483ec1
RD
449int mthca_map_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
450 struct mthca_user_db_table *db_tab, int index, u64 uaddr)
451{
45711f1a 452 struct page *pages[1];
56483ec1
RD
453 int ret = 0;
454 u8 status;
455 int i;
456
457 if (!mthca_is_memfree(dev))
458 return 0;
459
460 if (index < 0 || index > dev->uar_table.uarc_size / 8)
461 return -EINVAL;
462
fd9cfdd1 463 mutex_lock(&db_tab->mutex);
56483ec1
RD
464
465 i = index / MTHCA_DB_REC_PER_PAGE;
466
467 if ((db_tab->page[i].refcount >= MTHCA_DB_REC_PER_PAGE) ||
468 (db_tab->page[i].uvirt && db_tab->page[i].uvirt != uaddr) ||
469 (uaddr & 4095)) {
470 ret = -EINVAL;
471 goto out;
472 }
473
474 if (db_tab->page[i].refcount) {
475 ++db_tab->page[i].refcount;
476 goto out;
477 }
478
479 ret = get_user_pages(current, current->mm, uaddr & PAGE_MASK, 1, 1, 0,
45711f1a 480 pages, NULL);
56483ec1
RD
481 if (ret < 0)
482 goto out;
483
45711f1a 484 sg_set_page(&db_tab->page[i].mem, pages[0]);
8d3ef29d 485 db_tab->page[i].mem.length = MTHCA_ICM_PAGE_SIZE;
56483ec1
RD
486 db_tab->page[i].mem.offset = uaddr & ~PAGE_MASK;
487
488 ret = pci_map_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
489 if (ret < 0) {
45711f1a 490 put_page(pages[0]);
56483ec1
RD
491 goto out;
492 }
493
494 ret = mthca_MAP_ICM_page(dev, sg_dma_address(&db_tab->page[i].mem),
495 mthca_uarc_virt(dev, uar, i), &status);
496 if (!ret && status)
497 ret = -EINVAL;
498 if (ret) {
499 pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
45711f1a 500 put_page(sg_page(&db_tab->page[i].mem));
56483ec1
RD
501 goto out;
502 }
503
504 db_tab->page[i].uvirt = uaddr;
505 db_tab->page[i].refcount = 1;
506
507out:
fd9cfdd1 508 mutex_unlock(&db_tab->mutex);
56483ec1
RD
509 return ret;
510}
511
512void mthca_unmap_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
513 struct mthca_user_db_table *db_tab, int index)
514{
515 if (!mthca_is_memfree(dev))
516 return;
517
518 /*
519 * To make our bookkeeping simpler, we don't unmap DB
520 * pages until we clean up the whole db table.
521 */
522
fd9cfdd1 523 mutex_lock(&db_tab->mutex);
56483ec1
RD
524
525 --db_tab->page[index / MTHCA_DB_REC_PER_PAGE].refcount;
526
fd9cfdd1 527 mutex_unlock(&db_tab->mutex);
56483ec1
RD
528}
529
530struct mthca_user_db_table *mthca_init_user_db_tab(struct mthca_dev *dev)
531{
532 struct mthca_user_db_table *db_tab;
533 int npages;
534 int i;
535
536 if (!mthca_is_memfree(dev))
537 return NULL;
538
8d3ef29d 539 npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
56483ec1
RD
540 db_tab = kmalloc(sizeof *db_tab + npages * sizeof *db_tab->page, GFP_KERNEL);
541 if (!db_tab)
542 return ERR_PTR(-ENOMEM);
543
fd9cfdd1 544 mutex_init(&db_tab->mutex);
56483ec1
RD
545 for (i = 0; i < npages; ++i) {
546 db_tab->page[i].refcount = 0;
547 db_tab->page[i].uvirt = 0;
548 }
549
550 return db_tab;
551}
552
553void mthca_cleanup_user_db_tab(struct mthca_dev *dev, struct mthca_uar *uar,
554 struct mthca_user_db_table *db_tab)
555{
556 int i;
557 u8 status;
558
559 if (!mthca_is_memfree(dev))
560 return;
561
8d3ef29d 562 for (i = 0; i < dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE; ++i) {
56483ec1
RD
563 if (db_tab->page[i].uvirt) {
564 mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, uar, i), 1, &status);
565 pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
45711f1a 566 put_page(sg_page(&db_tab->page[i].mem));
56483ec1
RD
567 }
568 }
52d0df15
JM
569
570 kfree(db_tab);
56483ec1
RD
571}
572
c6f5cb7b
RD
573int mthca_alloc_db(struct mthca_dev *dev, enum mthca_db_type type,
574 u32 qn, __be32 **db)
1da177e4
LT
575{
576 int group;
577 int start, end, dir;
578 int i, j;
579 struct mthca_db_page *page;
580 int ret = 0;
581 u8 status;
582
fd9cfdd1 583 mutex_lock(&dev->db_tab->mutex);
1da177e4
LT
584
585 switch (type) {
586 case MTHCA_DB_TYPE_CQ_ARM:
587 case MTHCA_DB_TYPE_SQ:
588 group = 0;
589 start = 0;
590 end = dev->db_tab->max_group1;
591 dir = 1;
592 break;
593
594 case MTHCA_DB_TYPE_CQ_SET_CI:
595 case MTHCA_DB_TYPE_RQ:
596 case MTHCA_DB_TYPE_SRQ:
597 group = 1;
598 start = dev->db_tab->npages - 1;
599 end = dev->db_tab->min_group2;
600 dir = -1;
601 break;
602
603 default:
2714eb5a
RD
604 ret = -EINVAL;
605 goto out;
1da177e4
LT
606 }
607
608 for (i = start; i != end; i += dir)
609 if (dev->db_tab->page[i].db_rec &&
610 !bitmap_full(dev->db_tab->page[i].used,
611 MTHCA_DB_REC_PER_PAGE)) {
612 page = dev->db_tab->page + i;
613 goto found;
614 }
615
018771f4
RD
616 for (i = start; i != end; i += dir)
617 if (!dev->db_tab->page[i].db_rec) {
618 page = dev->db_tab->page + i;
619 goto alloc;
620 }
621
1da177e4
LT
622 if (dev->db_tab->max_group1 >= dev->db_tab->min_group2 - 1) {
623 ret = -ENOMEM;
624 goto out;
625 }
626
018771f4
RD
627 if (group == 0)
628 ++dev->db_tab->max_group1;
629 else
630 --dev->db_tab->min_group2;
631
1da177e4 632 page = dev->db_tab->page + end;
018771f4
RD
633
634alloc:
8d3ef29d 635 page->db_rec = dma_alloc_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
1da177e4
LT
636 &page->mapping, GFP_KERNEL);
637 if (!page->db_rec) {
638 ret = -ENOMEM;
639 goto out;
640 }
8d3ef29d 641 memset(page->db_rec, 0, MTHCA_ICM_PAGE_SIZE);
1da177e4 642
56483ec1
RD
643 ret = mthca_MAP_ICM_page(dev, page->mapping,
644 mthca_uarc_virt(dev, &dev->driver_uar, i), &status);
1da177e4
LT
645 if (!ret && status)
646 ret = -EINVAL;
647 if (ret) {
8d3ef29d 648 dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
1da177e4
LT
649 page->db_rec, page->mapping);
650 goto out;
651 }
652
653 bitmap_zero(page->used, MTHCA_DB_REC_PER_PAGE);
1da177e4
LT
654
655found:
656 j = find_first_zero_bit(page->used, MTHCA_DB_REC_PER_PAGE);
657 set_bit(j, page->used);
658
659 if (group == 1)
660 j = MTHCA_DB_REC_PER_PAGE - 1 - j;
661
662 ret = i * MTHCA_DB_REC_PER_PAGE + j;
663
664 page->db_rec[j] = cpu_to_be64((qn << 8) | (type << 5));
665
97f52eb4 666 *db = (__be32 *) &page->db_rec[j];
1da177e4
LT
667
668out:
fd9cfdd1 669 mutex_unlock(&dev->db_tab->mutex);
1da177e4
LT
670
671 return ret;
672}
673
674void mthca_free_db(struct mthca_dev *dev, int type, int db_index)
675{
676 int i, j;
677 struct mthca_db_page *page;
678 u8 status;
679
680 i = db_index / MTHCA_DB_REC_PER_PAGE;
681 j = db_index % MTHCA_DB_REC_PER_PAGE;
682
683 page = dev->db_tab->page + i;
684
fd9cfdd1 685 mutex_lock(&dev->db_tab->mutex);
1da177e4
LT
686
687 page->db_rec[j] = 0;
688 if (i >= dev->db_tab->min_group2)
689 j = MTHCA_DB_REC_PER_PAGE - 1 - j;
690 clear_bit(j, page->used);
691
692 if (bitmap_empty(page->used, MTHCA_DB_REC_PER_PAGE) &&
693 i >= dev->db_tab->max_group1 - 1) {
56483ec1 694 mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
1da177e4 695
8d3ef29d 696 dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
1da177e4
LT
697 page->db_rec, page->mapping);
698 page->db_rec = NULL;
699
700 if (i == dev->db_tab->max_group1) {
701 --dev->db_tab->max_group1;
702 /* XXX may be able to unmap more pages now */
703 }
704 if (i == dev->db_tab->min_group2)
705 ++dev->db_tab->min_group2;
706 }
707
fd9cfdd1 708 mutex_unlock(&dev->db_tab->mutex);
1da177e4
LT
709}
710
711int mthca_init_db_tab(struct mthca_dev *dev)
712{
713 int i;
714
d10ddbf6 715 if (!mthca_is_memfree(dev))
1da177e4
LT
716 return 0;
717
718 dev->db_tab = kmalloc(sizeof *dev->db_tab, GFP_KERNEL);
719 if (!dev->db_tab)
720 return -ENOMEM;
721
fd9cfdd1 722 mutex_init(&dev->db_tab->mutex);
1da177e4 723
8d3ef29d 724 dev->db_tab->npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
1da177e4
LT
725 dev->db_tab->max_group1 = 0;
726 dev->db_tab->min_group2 = dev->db_tab->npages - 1;
727
728 dev->db_tab->page = kmalloc(dev->db_tab->npages *
729 sizeof *dev->db_tab->page,
730 GFP_KERNEL);
731 if (!dev->db_tab->page) {
732 kfree(dev->db_tab);
733 return -ENOMEM;
734 }
735
736 for (i = 0; i < dev->db_tab->npages; ++i)
737 dev->db_tab->page[i].db_rec = NULL;
738
739 return 0;
740}
741
742void mthca_cleanup_db_tab(struct mthca_dev *dev)
743{
744 int i;
745 u8 status;
746
d10ddbf6 747 if (!mthca_is_memfree(dev))
1da177e4
LT
748 return;
749
750 /*
751 * Because we don't always free our UARC pages when they
752 * become empty to make mthca_free_db() simpler we need to
753 * make a sweep through the doorbell pages and free any
754 * leftover pages now.
755 */
756 for (i = 0; i < dev->db_tab->npages; ++i) {
757 if (!dev->db_tab->page[i].db_rec)
758 continue;
759
760 if (!bitmap_empty(dev->db_tab->page[i].used, MTHCA_DB_REC_PER_PAGE))
761 mthca_warn(dev, "Kernel UARC page %d not empty\n", i);
762
56483ec1 763 mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
1da177e4 764
8d3ef29d 765 dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
1da177e4
LT
766 dev->db_tab->page[i].db_rec,
767 dev->db_tab->page[i].mapping);
768 }
769
770 kfree(dev->db_tab->page);
771 kfree(dev->db_tab);
772}