Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
cd4e8fb4 | 3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. |
2a1d9b7f | 4 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. |
1da177e4 LT |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
1da177e4 LT |
33 | */ |
34 | ||
1da177e4 LT |
35 | #include <linux/module.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/errno.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/interrupt.h> | |
40 | ||
41 | #include "mthca_dev.h" | |
42 | #include "mthca_config_reg.h" | |
43 | #include "mthca_cmd.h" | |
44 | #include "mthca_profile.h" | |
45 | #include "mthca_memfree.h" | |
12103dca | 46 | #include "mthca_wqe.h" |
1da177e4 LT |
47 | |
48 | MODULE_AUTHOR("Roland Dreier"); | |
49 | MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver"); | |
50 | MODULE_LICENSE("Dual BSD/GPL"); | |
51 | MODULE_VERSION(DRV_VERSION); | |
52 | ||
227c939b RD |
53 | #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG |
54 | ||
55 | int mthca_debug_level = 0; | |
56 | module_param_named(debug_level, mthca_debug_level, int, 0644); | |
57 | MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); | |
58 | ||
59 | #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */ | |
60 | ||
1da177e4 LT |
61 | #ifdef CONFIG_PCI_MSI |
62 | ||
017aadc4 | 63 | static int msi_x = 1; |
1da177e4 LT |
64 | module_param(msi_x, int, 0444); |
65 | MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); | |
66 | ||
1da177e4 LT |
67 | #else /* CONFIG_PCI_MSI */ |
68 | ||
69 | #define msi_x (0) | |
1da177e4 LT |
70 | |
71 | #endif /* CONFIG_PCI_MSI */ | |
72 | ||
abf45dbb MT |
73 | static int tune_pci = 0; |
74 | module_param(tune_pci, int, 0444); | |
75 | MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero"); | |
76 | ||
0b0df6f2 | 77 | DEFINE_MUTEX(mthca_device_mutex); |
b3b30f5e | 78 | |
82da703e LA |
79 | #define MTHCA_DEFAULT_NUM_QP (1 << 16) |
80 | #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2) | |
81 | #define MTHCA_DEFAULT_NUM_CQ (1 << 16) | |
82 | #define MTHCA_DEFAULT_NUM_MCG (1 << 13) | |
83 | #define MTHCA_DEFAULT_NUM_MPT (1 << 17) | |
84 | #define MTHCA_DEFAULT_NUM_MTT (1 << 20) | |
85 | #define MTHCA_DEFAULT_NUM_UDAV (1 << 15) | |
86 | #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18) | |
87 | #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18) | |
88 | ||
89 | static struct mthca_profile hca_profile = { | |
90 | .num_qp = MTHCA_DEFAULT_NUM_QP, | |
91 | .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP, | |
92 | .num_cq = MTHCA_DEFAULT_NUM_CQ, | |
93 | .num_mcg = MTHCA_DEFAULT_NUM_MCG, | |
94 | .num_mpt = MTHCA_DEFAULT_NUM_MPT, | |
95 | .num_mtt = MTHCA_DEFAULT_NUM_MTT, | |
96 | .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */ | |
97 | .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */ | |
98 | .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */ | |
99 | }; | |
100 | ||
101 | module_param_named(num_qp, hca_profile.num_qp, int, 0444); | |
102 | MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA"); | |
103 | ||
104 | module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444); | |
105 | MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP"); | |
106 | ||
107 | module_param_named(num_cq, hca_profile.num_cq, int, 0444); | |
108 | MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA"); | |
109 | ||
110 | module_param_named(num_mcg, hca_profile.num_mcg, int, 0444); | |
111 | MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA"); | |
112 | ||
113 | module_param_named(num_mpt, hca_profile.num_mpt, int, 0444); | |
114 | MODULE_PARM_DESC(num_mpt, | |
115 | "maximum number of memory protection table entries per HCA"); | |
116 | ||
117 | module_param_named(num_mtt, hca_profile.num_mtt, int, 0444); | |
118 | MODULE_PARM_DESC(num_mtt, | |
119 | "maximum number of memory translation table segments per HCA"); | |
120 | ||
121 | module_param_named(num_udav, hca_profile.num_udav, int, 0444); | |
122 | MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA"); | |
123 | ||
124 | module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444); | |
125 | MODULE_PARM_DESC(fmr_reserved_mtts, | |
126 | "number of memory translation table segments reserved for FMR"); | |
127 | ||
c1f67a88 EC |
128 | static int log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8); |
129 | module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); | |
130 | MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)"); | |
131 | ||
f33afc26 | 132 | static char mthca_version[] __devinitdata = |
177214af | 133 | DRV_NAME ": Mellanox InfiniBand HCA driver v" |
1da177e4 LT |
134 | DRV_VERSION " (" DRV_RELDATE ")\n"; |
135 | ||
f4f3d0f0 | 136 | static int mthca_tune_pci(struct mthca_dev *mdev) |
1da177e4 | 137 | { |
abf45dbb MT |
138 | if (!tune_pci) |
139 | return 0; | |
140 | ||
1da177e4 | 141 | /* First try to max out Read Byte Count */ |
a855b1a7 PO |
142 | if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) { |
143 | if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) { | |
144 | mthca_err(mdev, "Couldn't set PCI-X max read count, " | |
145 | "aborting.\n"); | |
1da177e4 LT |
146 | return -ENODEV; |
147 | } | |
68a3c212 | 148 | } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE)) |
1da177e4 LT |
149 | mthca_info(mdev, "No PCI-X capability, not setting RBC.\n"); |
150 | ||
a855b1a7 PO |
151 | if (pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP)) { |
152 | if (pcie_set_readrq(mdev->pdev, 4096)) { | |
153 | mthca_err(mdev, "Couldn't write PCI Express read request, " | |
154 | "aborting.\n"); | |
1da177e4 LT |
155 | return -ENODEV; |
156 | } | |
68a3c212 | 157 | } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE) |
1da177e4 LT |
158 | mthca_info(mdev, "No PCI Express capability, " |
159 | "not setting Max Read Request Size.\n"); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
f4f3d0f0 | 164 | static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim) |
1da177e4 LT |
165 | { |
166 | int err; | |
167 | u8 status; | |
168 | ||
c1f67a88 | 169 | mdev->limits.mtt_seg_size = (1 << log_mtts_per_seg) * 8; |
1da177e4 LT |
170 | err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status); |
171 | if (err) { | |
172 | mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n"); | |
173 | return err; | |
174 | } | |
175 | if (status) { | |
176 | mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, " | |
177 | "aborting.\n", status); | |
178 | return -EINVAL; | |
179 | } | |
180 | if (dev_lim->min_page_sz > PAGE_SIZE) { | |
181 | mthca_err(mdev, "HCA minimum page size of %d bigger than " | |
182 | "kernel PAGE_SIZE of %ld, aborting.\n", | |
183 | dev_lim->min_page_sz, PAGE_SIZE); | |
184 | return -ENODEV; | |
185 | } | |
186 | if (dev_lim->num_ports > MTHCA_MAX_PORTS) { | |
187 | mthca_err(mdev, "HCA has %d ports, but we only support %d, " | |
188 | "aborting.\n", | |
189 | dev_lim->num_ports, MTHCA_MAX_PORTS); | |
190 | return -ENODEV; | |
191 | } | |
192 | ||
cbd2981a MT |
193 | if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) { |
194 | mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than " | |
e29419ff GKH |
195 | "PCI resource 2 size of 0x%llx, aborting.\n", |
196 | dev_lim->uar_size, | |
197 | (unsigned long long)pci_resource_len(mdev->pdev, 2)); | |
cbd2981a MT |
198 | return -ENODEV; |
199 | } | |
200 | ||
1da177e4 LT |
201 | mdev->limits.num_ports = dev_lim->num_ports; |
202 | mdev->limits.vl_cap = dev_lim->max_vl; | |
203 | mdev->limits.mtu_cap = dev_lim->max_mtu; | |
204 | mdev->limits.gid_table_len = dev_lim->max_gids; | |
205 | mdev->limits.pkey_table_len = dev_lim->max_pkeys; | |
206 | mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay; | |
12103dca RD |
207 | /* |
208 | * Need to allow for worst case send WQE overhead and check | |
209 | * whether max_desc_sz imposes a lower limit than max_sg; UD | |
210 | * send has the biggest overhead. | |
211 | */ | |
212 | mdev->limits.max_sg = min_t(int, dev_lim->max_sg, | |
213 | (dev_lim->max_desc_sz - | |
214 | sizeof (struct mthca_next_seg) - | |
215 | (mthca_is_memfree(mdev) ? | |
216 | sizeof (struct mthca_arbel_ud_seg) : | |
217 | sizeof (struct mthca_tavor_ud_seg))) / | |
218 | sizeof (struct mthca_data_seg)); | |
efaae8f7 JM |
219 | mdev->limits.max_wqes = dev_lim->max_qp_sz; |
220 | mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp; | |
1da177e4 | 221 | mdev->limits.reserved_qps = dev_lim->reserved_qps; |
efaae8f7 | 222 | mdev->limits.max_srq_wqes = dev_lim->max_srq_sz; |
1da177e4 LT |
223 | mdev->limits.reserved_srqs = dev_lim->reserved_srqs; |
224 | mdev->limits.reserved_eecs = dev_lim->reserved_eecs; | |
77369ed3 | 225 | mdev->limits.max_desc_sz = dev_lim->max_desc_sz; |
59fef3b1 | 226 | mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev); |
efaae8f7 JM |
227 | /* |
228 | * Subtract 1 from the limit because we need to allocate a | |
229 | * spare CQE so the HCA HW can tell the difference between an | |
230 | * empty CQ and a full CQ. | |
231 | */ | |
232 | mdev->limits.max_cqes = dev_lim->max_cq_sz - 1; | |
1da177e4 LT |
233 | mdev->limits.reserved_cqs = dev_lim->reserved_cqs; |
234 | mdev->limits.reserved_eqs = dev_lim->reserved_eqs; | |
235 | mdev->limits.reserved_mtts = dev_lim->reserved_mtts; | |
236 | mdev->limits.reserved_mrws = dev_lim->reserved_mrws; | |
237 | mdev->limits.reserved_uars = dev_lim->reserved_uars; | |
238 | mdev->limits.reserved_pds = dev_lim->reserved_pds; | |
da6561c2 | 239 | mdev->limits.port_width_cap = dev_lim->max_port_width; |
0f69ce1e | 240 | mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1); |
33033b79 | 241 | mdev->limits.flags = dev_lim->flags; |
bf6a9e31 JM |
242 | /* |
243 | * For old FW that doesn't return static rate support, use a | |
244 | * value of 0x3 (only static rate values of 0 or 1 are handled), | |
245 | * except on Sinai, where even old FW can handle static rate | |
246 | * values of 2 and 3. | |
247 | */ | |
248 | if (dev_lim->stat_rate_support) | |
249 | mdev->limits.stat_rate_support = dev_lim->stat_rate_support; | |
250 | else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT) | |
251 | mdev->limits.stat_rate_support = 0xf; | |
252 | else | |
253 | mdev->limits.stat_rate_support = 0x3; | |
1da177e4 LT |
254 | |
255 | /* IB_DEVICE_RESIZE_MAX_WR not supported by driver. | |
256 | May be doable since hardware supports it for SRQ. | |
257 | ||
258 | IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver. | |
259 | ||
260 | IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not | |
261 | supported by driver. */ | |
262 | mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | | |
263 | IB_DEVICE_PORT_ACTIVE_EVENT | | |
264 | IB_DEVICE_SYS_IMAGE_GUID | | |
265 | IB_DEVICE_RC_RNR_NAK_GEN; | |
266 | ||
267 | if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR) | |
268 | mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; | |
269 | ||
270 | if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR) | |
271 | mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; | |
272 | ||
273 | if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI) | |
274 | mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI; | |
275 | ||
276 | if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG) | |
277 | mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; | |
278 | ||
279 | if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE) | |
280 | mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; | |
281 | ||
282 | if (dev_lim->flags & DEV_LIM_FLAG_SRQ) | |
283 | mdev->mthca_flags |= MTHCA_FLAG_SRQ; | |
284 | ||
680b575f EC |
285 | if (mthca_is_memfree(mdev)) |
286 | if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM) | |
287 | mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; | |
288 | ||
1da177e4 LT |
289 | return 0; |
290 | } | |
291 | ||
f4f3d0f0 | 292 | static int mthca_init_tavor(struct mthca_dev *mdev) |
1da177e4 | 293 | { |
19773539 | 294 | s64 size; |
1da177e4 LT |
295 | u8 status; |
296 | int err; | |
297 | struct mthca_dev_lim dev_lim; | |
298 | struct mthca_profile profile; | |
299 | struct mthca_init_hca_param init_hca; | |
1da177e4 LT |
300 | |
301 | err = mthca_SYS_EN(mdev, &status); | |
302 | if (err) { | |
303 | mthca_err(mdev, "SYS_EN command failed, aborting.\n"); | |
304 | return err; | |
305 | } | |
306 | if (status) { | |
307 | mthca_err(mdev, "SYS_EN returned status 0x%02x, " | |
308 | "aborting.\n", status); | |
309 | return -EINVAL; | |
310 | } | |
311 | ||
312 | err = mthca_QUERY_FW(mdev, &status); | |
313 | if (err) { | |
314 | mthca_err(mdev, "QUERY_FW command failed, aborting.\n"); | |
315 | goto err_disable; | |
316 | } | |
317 | if (status) { | |
318 | mthca_err(mdev, "QUERY_FW returned status 0x%02x, " | |
319 | "aborting.\n", status); | |
320 | err = -EINVAL; | |
321 | goto err_disable; | |
322 | } | |
323 | err = mthca_QUERY_DDR(mdev, &status); | |
324 | if (err) { | |
325 | mthca_err(mdev, "QUERY_DDR command failed, aborting.\n"); | |
326 | goto err_disable; | |
327 | } | |
328 | if (status) { | |
329 | mthca_err(mdev, "QUERY_DDR returned status 0x%02x, " | |
330 | "aborting.\n", status); | |
331 | err = -EINVAL; | |
332 | goto err_disable; | |
333 | } | |
334 | ||
335 | err = mthca_dev_lim(mdev, &dev_lim); | |
aa2f9367 JM |
336 | if (err) { |
337 | mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n"); | |
338 | goto err_disable; | |
339 | } | |
1da177e4 | 340 | |
82da703e | 341 | profile = hca_profile; |
1da177e4 LT |
342 | profile.num_uar = dev_lim.uar_size / PAGE_SIZE; |
343 | profile.uarc_size = 0; | |
ec34a922 RD |
344 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) |
345 | profile.num_srq = dev_lim.max_srqs; | |
1da177e4 | 346 | |
19773539 RD |
347 | size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca); |
348 | if (size < 0) { | |
349 | err = size; | |
1da177e4 | 350 | goto err_disable; |
19773539 | 351 | } |
1da177e4 LT |
352 | |
353 | err = mthca_INIT_HCA(mdev, &init_hca, &status); | |
354 | if (err) { | |
355 | mthca_err(mdev, "INIT_HCA command failed, aborting.\n"); | |
356 | goto err_disable; | |
357 | } | |
358 | if (status) { | |
359 | mthca_err(mdev, "INIT_HCA returned status 0x%02x, " | |
360 | "aborting.\n", status); | |
361 | err = -EINVAL; | |
362 | goto err_disable; | |
363 | } | |
364 | ||
1da177e4 LT |
365 | return 0; |
366 | ||
1da177e4 LT |
367 | err_disable: |
368 | mthca_SYS_DIS(mdev, &status); | |
369 | ||
370 | return err; | |
371 | } | |
372 | ||
f4f3d0f0 | 373 | static int mthca_load_fw(struct mthca_dev *mdev) |
1da177e4 LT |
374 | { |
375 | u8 status; | |
376 | int err; | |
377 | ||
378 | /* FIXME: use HCA-attached memory for FW if present */ | |
379 | ||
380 | mdev->fw.arbel.fw_icm = | |
381 | mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages, | |
391e4dea | 382 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
1da177e4 LT |
383 | if (!mdev->fw.arbel.fw_icm) { |
384 | mthca_err(mdev, "Couldn't allocate FW area, aborting.\n"); | |
385 | return -ENOMEM; | |
386 | } | |
387 | ||
388 | err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status); | |
389 | if (err) { | |
390 | mthca_err(mdev, "MAP_FA command failed, aborting.\n"); | |
391 | goto err_free; | |
392 | } | |
393 | if (status) { | |
394 | mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status); | |
395 | err = -EINVAL; | |
396 | goto err_free; | |
397 | } | |
398 | err = mthca_RUN_FW(mdev, &status); | |
399 | if (err) { | |
400 | mthca_err(mdev, "RUN_FW command failed, aborting.\n"); | |
401 | goto err_unmap_fa; | |
402 | } | |
403 | if (status) { | |
404 | mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status); | |
405 | err = -EINVAL; | |
406 | goto err_unmap_fa; | |
407 | } | |
408 | ||
409 | return 0; | |
410 | ||
411 | err_unmap_fa: | |
412 | mthca_UNMAP_FA(mdev, &status); | |
413 | ||
414 | err_free: | |
391e4dea | 415 | mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0); |
1da177e4 LT |
416 | return err; |
417 | } | |
418 | ||
f4f3d0f0 RD |
419 | static int mthca_init_icm(struct mthca_dev *mdev, |
420 | struct mthca_dev_lim *dev_lim, | |
421 | struct mthca_init_hca_param *init_hca, | |
422 | u64 icm_size) | |
1da177e4 LT |
423 | { |
424 | u64 aux_pages; | |
425 | u8 status; | |
426 | int err; | |
427 | ||
428 | err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status); | |
429 | if (err) { | |
430 | mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n"); | |
431 | return err; | |
432 | } | |
433 | if (status) { | |
434 | mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, " | |
435 | "aborting.\n", status); | |
436 | return -EINVAL; | |
437 | } | |
438 | ||
439 | mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n", | |
440 | (unsigned long long) icm_size >> 10, | |
441 | (unsigned long long) aux_pages << 2); | |
442 | ||
443 | mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages, | |
391e4dea | 444 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
1da177e4 LT |
445 | if (!mdev->fw.arbel.aux_icm) { |
446 | mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n"); | |
447 | return -ENOMEM; | |
448 | } | |
449 | ||
450 | err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status); | |
451 | if (err) { | |
452 | mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n"); | |
453 | goto err_free_aux; | |
454 | } | |
455 | if (status) { | |
456 | mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status); | |
457 | err = -EINVAL; | |
458 | goto err_free_aux; | |
459 | } | |
460 | ||
461 | err = mthca_map_eq_icm(mdev, init_hca->eqc_base); | |
462 | if (err) { | |
463 | mthca_err(mdev, "Failed to map EQ context memory, aborting.\n"); | |
464 | goto err_unmap_aux; | |
465 | } | |
466 | ||
1d1f19cf | 467 | /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */ |
c1f67a88 EC |
468 | mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * mdev->limits.mtt_seg_size, |
469 | dma_get_cache_alignment()) / mdev->limits.mtt_seg_size; | |
1d1f19cf | 470 | |
1da177e4 | 471 | mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base, |
c1f67a88 | 472 | mdev->limits.mtt_seg_size, |
1da177e4 | 473 | mdev->limits.num_mtt_segs, |
391e4dea MT |
474 | mdev->limits.reserved_mtts, |
475 | 1, 0); | |
1da177e4 LT |
476 | if (!mdev->mr_table.mtt_table) { |
477 | mthca_err(mdev, "Failed to map MTT context memory, aborting.\n"); | |
478 | err = -ENOMEM; | |
479 | goto err_unmap_eq; | |
480 | } | |
481 | ||
482 | mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base, | |
483 | dev_lim->mpt_entry_sz, | |
484 | mdev->limits.num_mpts, | |
391e4dea MT |
485 | mdev->limits.reserved_mrws, |
486 | 1, 1); | |
1da177e4 LT |
487 | if (!mdev->mr_table.mpt_table) { |
488 | mthca_err(mdev, "Failed to map MPT context memory, aborting.\n"); | |
489 | err = -ENOMEM; | |
490 | goto err_unmap_mtt; | |
491 | } | |
492 | ||
493 | mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base, | |
494 | dev_lim->qpc_entry_sz, | |
495 | mdev->limits.num_qps, | |
391e4dea MT |
496 | mdev->limits.reserved_qps, |
497 | 0, 0); | |
1da177e4 LT |
498 | if (!mdev->qp_table.qp_table) { |
499 | mthca_err(mdev, "Failed to map QP context memory, aborting.\n"); | |
500 | err = -ENOMEM; | |
501 | goto err_unmap_mpt; | |
502 | } | |
503 | ||
504 | mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base, | |
505 | dev_lim->eqpc_entry_sz, | |
506 | mdev->limits.num_qps, | |
391e4dea MT |
507 | mdev->limits.reserved_qps, |
508 | 0, 0); | |
1da177e4 LT |
509 | if (!mdev->qp_table.eqp_table) { |
510 | mthca_err(mdev, "Failed to map EQP context memory, aborting.\n"); | |
511 | err = -ENOMEM; | |
512 | goto err_unmap_qp; | |
513 | } | |
514 | ||
08aeb14e RD |
515 | mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base, |
516 | MTHCA_RDB_ENTRY_SIZE, | |
517 | mdev->limits.num_qps << | |
391e4dea | 518 | mdev->qp_table.rdb_shift, 0, |
08aeb14e RD |
519 | 0, 0); |
520 | if (!mdev->qp_table.rdb_table) { | |
521 | mthca_err(mdev, "Failed to map RDB context memory, aborting\n"); | |
522 | err = -ENOMEM; | |
19272d43 | 523 | goto err_unmap_eqp; |
08aeb14e RD |
524 | } |
525 | ||
526 | mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base, | |
ec34a922 RD |
527 | dev_lim->cqc_entry_sz, |
528 | mdev->limits.num_cqs, | |
391e4dea MT |
529 | mdev->limits.reserved_cqs, |
530 | 0, 0); | |
1da177e4 LT |
531 | if (!mdev->cq_table.table) { |
532 | mthca_err(mdev, "Failed to map CQ context memory, aborting.\n"); | |
533 | err = -ENOMEM; | |
08aeb14e | 534 | goto err_unmap_rdb; |
1da177e4 LT |
535 | } |
536 | ||
ec34a922 RD |
537 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) { |
538 | mdev->srq_table.table = | |
539 | mthca_alloc_icm_table(mdev, init_hca->srqc_base, | |
540 | dev_lim->srq_entry_sz, | |
541 | mdev->limits.num_srqs, | |
391e4dea MT |
542 | mdev->limits.reserved_srqs, |
543 | 0, 0); | |
ec34a922 RD |
544 | if (!mdev->srq_table.table) { |
545 | mthca_err(mdev, "Failed to map SRQ context memory, " | |
546 | "aborting.\n"); | |
547 | err = -ENOMEM; | |
548 | goto err_unmap_cq; | |
549 | } | |
550 | } | |
551 | ||
1da177e4 LT |
552 | /* |
553 | * It's not strictly required, but for simplicity just map the | |
554 | * whole multicast group table now. The table isn't very big | |
555 | * and it's a lot easier than trying to track ref counts. | |
556 | */ | |
557 | mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base, | |
558 | MTHCA_MGM_ENTRY_SIZE, | |
559 | mdev->limits.num_mgms + | |
560 | mdev->limits.num_amgms, | |
561 | mdev->limits.num_mgms + | |
562 | mdev->limits.num_amgms, | |
391e4dea | 563 | 0, 0); |
1da177e4 LT |
564 | if (!mdev->mcg_table.table) { |
565 | mthca_err(mdev, "Failed to map MCG context memory, aborting.\n"); | |
566 | err = -ENOMEM; | |
ec34a922 | 567 | goto err_unmap_srq; |
1da177e4 LT |
568 | } |
569 | ||
570 | return 0; | |
571 | ||
ec34a922 RD |
572 | err_unmap_srq: |
573 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) | |
574 | mthca_free_icm_table(mdev, mdev->srq_table.table); | |
575 | ||
1da177e4 LT |
576 | err_unmap_cq: |
577 | mthca_free_icm_table(mdev, mdev->cq_table.table); | |
578 | ||
08aeb14e RD |
579 | err_unmap_rdb: |
580 | mthca_free_icm_table(mdev, mdev->qp_table.rdb_table); | |
581 | ||
1da177e4 LT |
582 | err_unmap_eqp: |
583 | mthca_free_icm_table(mdev, mdev->qp_table.eqp_table); | |
584 | ||
585 | err_unmap_qp: | |
586 | mthca_free_icm_table(mdev, mdev->qp_table.qp_table); | |
587 | ||
588 | err_unmap_mpt: | |
589 | mthca_free_icm_table(mdev, mdev->mr_table.mpt_table); | |
590 | ||
591 | err_unmap_mtt: | |
592 | mthca_free_icm_table(mdev, mdev->mr_table.mtt_table); | |
593 | ||
594 | err_unmap_eq: | |
595 | mthca_unmap_eq_icm(mdev); | |
596 | ||
597 | err_unmap_aux: | |
598 | mthca_UNMAP_ICM_AUX(mdev, &status); | |
599 | ||
600 | err_free_aux: | |
391e4dea | 601 | mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0); |
1da177e4 LT |
602 | |
603 | return err; | |
604 | } | |
605 | ||
aba7a22f MT |
606 | static void mthca_free_icms(struct mthca_dev *mdev) |
607 | { | |
608 | u8 status; | |
609 | ||
610 | mthca_free_icm_table(mdev, mdev->mcg_table.table); | |
611 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) | |
612 | mthca_free_icm_table(mdev, mdev->srq_table.table); | |
613 | mthca_free_icm_table(mdev, mdev->cq_table.table); | |
614 | mthca_free_icm_table(mdev, mdev->qp_table.rdb_table); | |
615 | mthca_free_icm_table(mdev, mdev->qp_table.eqp_table); | |
616 | mthca_free_icm_table(mdev, mdev->qp_table.qp_table); | |
617 | mthca_free_icm_table(mdev, mdev->mr_table.mpt_table); | |
618 | mthca_free_icm_table(mdev, mdev->mr_table.mtt_table); | |
619 | mthca_unmap_eq_icm(mdev); | |
620 | ||
621 | mthca_UNMAP_ICM_AUX(mdev, &status); | |
391e4dea | 622 | mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0); |
aba7a22f MT |
623 | } |
624 | ||
f4f3d0f0 | 625 | static int mthca_init_arbel(struct mthca_dev *mdev) |
1da177e4 LT |
626 | { |
627 | struct mthca_dev_lim dev_lim; | |
628 | struct mthca_profile profile; | |
629 | struct mthca_init_hca_param init_hca; | |
19773539 | 630 | s64 icm_size; |
1da177e4 LT |
631 | u8 status; |
632 | int err; | |
633 | ||
634 | err = mthca_QUERY_FW(mdev, &status); | |
635 | if (err) { | |
636 | mthca_err(mdev, "QUERY_FW command failed, aborting.\n"); | |
637 | return err; | |
638 | } | |
639 | if (status) { | |
640 | mthca_err(mdev, "QUERY_FW returned status 0x%02x, " | |
641 | "aborting.\n", status); | |
642 | return -EINVAL; | |
643 | } | |
644 | ||
645 | err = mthca_ENABLE_LAM(mdev, &status); | |
646 | if (err) { | |
647 | mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n"); | |
648 | return err; | |
649 | } | |
650 | if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) { | |
651 | mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n"); | |
652 | mdev->mthca_flags |= MTHCA_FLAG_NO_LAM; | |
653 | } else if (status) { | |
654 | mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, " | |
655 | "aborting.\n", status); | |
656 | return -EINVAL; | |
657 | } | |
658 | ||
659 | err = mthca_load_fw(mdev); | |
660 | if (err) { | |
661 | mthca_err(mdev, "Failed to start FW, aborting.\n"); | |
662 | goto err_disable; | |
663 | } | |
664 | ||
665 | err = mthca_dev_lim(mdev, &dev_lim); | |
666 | if (err) { | |
667 | mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n"); | |
668 | goto err_stop_fw; | |
669 | } | |
670 | ||
82da703e | 671 | profile = hca_profile; |
1da177e4 LT |
672 | profile.num_uar = dev_lim.uar_size / PAGE_SIZE; |
673 | profile.num_udav = 0; | |
ec34a922 RD |
674 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) |
675 | profile.num_srq = dev_lim.max_srqs; | |
1da177e4 LT |
676 | |
677 | icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca); | |
19773539 | 678 | if (icm_size < 0) { |
1da177e4 LT |
679 | err = icm_size; |
680 | goto err_stop_fw; | |
681 | } | |
682 | ||
683 | err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size); | |
684 | if (err) | |
685 | goto err_stop_fw; | |
686 | ||
687 | err = mthca_INIT_HCA(mdev, &init_hca, &status); | |
688 | if (err) { | |
689 | mthca_err(mdev, "INIT_HCA command failed, aborting.\n"); | |
690 | goto err_free_icm; | |
691 | } | |
692 | if (status) { | |
693 | mthca_err(mdev, "INIT_HCA returned status 0x%02x, " | |
694 | "aborting.\n", status); | |
695 | err = -EINVAL; | |
696 | goto err_free_icm; | |
697 | } | |
698 | ||
1da177e4 LT |
699 | return 0; |
700 | ||
701 | err_free_icm: | |
aba7a22f | 702 | mthca_free_icms(mdev); |
1da177e4 LT |
703 | |
704 | err_stop_fw: | |
705 | mthca_UNMAP_FA(mdev, &status); | |
391e4dea | 706 | mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0); |
1da177e4 LT |
707 | |
708 | err_disable: | |
709 | if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM)) | |
710 | mthca_DISABLE_LAM(mdev, &status); | |
711 | ||
712 | return err; | |
713 | } | |
714 | ||
2e8b981c MT |
715 | static void mthca_close_hca(struct mthca_dev *mdev) |
716 | { | |
717 | u8 status; | |
718 | ||
719 | mthca_CLOSE_HCA(mdev, 0, &status); | |
720 | ||
721 | if (mthca_is_memfree(mdev)) { | |
aba7a22f | 722 | mthca_free_icms(mdev); |
2e8b981c MT |
723 | |
724 | mthca_UNMAP_FA(mdev, &status); | |
391e4dea | 725 | mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0); |
2e8b981c MT |
726 | |
727 | if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM)) | |
728 | mthca_DISABLE_LAM(mdev, &status); | |
729 | } else | |
730 | mthca_SYS_DIS(mdev, &status); | |
731 | } | |
732 | ||
f4f3d0f0 | 733 | static int mthca_init_hca(struct mthca_dev *mdev) |
1da177e4 | 734 | { |
2e8b981c MT |
735 | u8 status; |
736 | int err; | |
737 | struct mthca_adapter adapter; | |
738 | ||
d10ddbf6 | 739 | if (mthca_is_memfree(mdev)) |
2e8b981c | 740 | err = mthca_init_arbel(mdev); |
1da177e4 | 741 | else |
2e8b981c MT |
742 | err = mthca_init_tavor(mdev); |
743 | ||
744 | if (err) | |
745 | return err; | |
746 | ||
747 | err = mthca_QUERY_ADAPTER(mdev, &adapter, &status); | |
748 | if (err) { | |
749 | mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n"); | |
750 | goto err_close; | |
751 | } | |
752 | if (status) { | |
753 | mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, " | |
754 | "aborting.\n", status); | |
755 | err = -EINVAL; | |
756 | goto err_close; | |
757 | } | |
758 | ||
759 | mdev->eq_table.inta_pin = adapter.inta_pin; | |
6ccef1de JM |
760 | if (!mthca_is_memfree(mdev)) |
761 | mdev->rev_id = adapter.revision_id; | |
2e8b981c MT |
762 | memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id); |
763 | ||
764 | return 0; | |
765 | ||
766 | err_close: | |
767 | mthca_close_hca(mdev); | |
768 | return err; | |
1da177e4 LT |
769 | } |
770 | ||
f4f3d0f0 | 771 | static int mthca_setup_hca(struct mthca_dev *dev) |
1da177e4 LT |
772 | { |
773 | int err; | |
774 | u8 status; | |
775 | ||
776 | MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock); | |
777 | ||
778 | err = mthca_init_uar_table(dev); | |
779 | if (err) { | |
780 | mthca_err(dev, "Failed to initialize " | |
781 | "user access region table, aborting.\n"); | |
782 | return err; | |
783 | } | |
784 | ||
785 | err = mthca_uar_alloc(dev, &dev->driver_uar); | |
786 | if (err) { | |
787 | mthca_err(dev, "Failed to allocate driver access region, " | |
788 | "aborting.\n"); | |
789 | goto err_uar_table_free; | |
790 | } | |
791 | ||
792 | dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); | |
793 | if (!dev->kar) { | |
794 | mthca_err(dev, "Couldn't map kernel access region, " | |
795 | "aborting.\n"); | |
796 | err = -ENOMEM; | |
797 | goto err_uar_free; | |
798 | } | |
799 | ||
800 | err = mthca_init_pd_table(dev); | |
801 | if (err) { | |
802 | mthca_err(dev, "Failed to initialize " | |
803 | "protection domain table, aborting.\n"); | |
804 | goto err_kar_unmap; | |
805 | } | |
806 | ||
807 | err = mthca_init_mr_table(dev); | |
808 | if (err) { | |
809 | mthca_err(dev, "Failed to initialize " | |
810 | "memory region table, aborting.\n"); | |
811 | goto err_pd_table_free; | |
812 | } | |
813 | ||
99264c1e | 814 | err = mthca_pd_alloc(dev, 1, &dev->driver_pd); |
1da177e4 LT |
815 | if (err) { |
816 | mthca_err(dev, "Failed to create driver PD, " | |
817 | "aborting.\n"); | |
818 | goto err_mr_table_free; | |
819 | } | |
820 | ||
821 | err = mthca_init_eq_table(dev); | |
822 | if (err) { | |
823 | mthca_err(dev, "Failed to initialize " | |
824 | "event queue table, aborting.\n"); | |
825 | goto err_pd_free; | |
826 | } | |
827 | ||
828 | err = mthca_cmd_use_events(dev); | |
829 | if (err) { | |
830 | mthca_err(dev, "Failed to switch to event-driven " | |
831 | "firmware commands, aborting.\n"); | |
832 | goto err_eq_table_free; | |
833 | } | |
834 | ||
835 | err = mthca_NOP(dev, &status); | |
836 | if (err || status) { | |
e57895d3 | 837 | if (dev->mthca_flags & MTHCA_FLAG_MSI_X) { |
017aadc4 MT |
838 | mthca_warn(dev, "NOP command failed to generate interrupt " |
839 | "(IRQ %d).\n", | |
e57895d3 AB |
840 | dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector); |
841 | mthca_warn(dev, "Trying again with MSI-X disabled.\n"); | |
017aadc4 MT |
842 | } else { |
843 | mthca_err(dev, "NOP command failed to generate interrupt " | |
844 | "(IRQ %d), aborting.\n", | |
845 | dev->pdev->irq); | |
1da177e4 | 846 | mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n"); |
017aadc4 | 847 | } |
1da177e4 LT |
848 | |
849 | goto err_cmd_poll; | |
850 | } | |
851 | ||
852 | mthca_dbg(dev, "NOP command IRQ test passed\n"); | |
853 | ||
854 | err = mthca_init_cq_table(dev); | |
855 | if (err) { | |
856 | mthca_err(dev, "Failed to initialize " | |
857 | "completion queue table, aborting.\n"); | |
858 | goto err_cmd_poll; | |
859 | } | |
860 | ||
ec34a922 RD |
861 | err = mthca_init_srq_table(dev); |
862 | if (err) { | |
863 | mthca_err(dev, "Failed to initialize " | |
864 | "shared receive queue table, aborting.\n"); | |
865 | goto err_cq_table_free; | |
866 | } | |
867 | ||
1da177e4 LT |
868 | err = mthca_init_qp_table(dev); |
869 | if (err) { | |
870 | mthca_err(dev, "Failed to initialize " | |
871 | "queue pair table, aborting.\n"); | |
ec34a922 | 872 | goto err_srq_table_free; |
1da177e4 LT |
873 | } |
874 | ||
875 | err = mthca_init_av_table(dev); | |
876 | if (err) { | |
877 | mthca_err(dev, "Failed to initialize " | |
878 | "address vector table, aborting.\n"); | |
879 | goto err_qp_table_free; | |
880 | } | |
881 | ||
882 | err = mthca_init_mcg_table(dev); | |
883 | if (err) { | |
884 | mthca_err(dev, "Failed to initialize " | |
885 | "multicast group table, aborting.\n"); | |
886 | goto err_av_table_free; | |
887 | } | |
888 | ||
889 | return 0; | |
890 | ||
891 | err_av_table_free: | |
892 | mthca_cleanup_av_table(dev); | |
893 | ||
894 | err_qp_table_free: | |
895 | mthca_cleanup_qp_table(dev); | |
896 | ||
ec34a922 RD |
897 | err_srq_table_free: |
898 | mthca_cleanup_srq_table(dev); | |
899 | ||
1da177e4 LT |
900 | err_cq_table_free: |
901 | mthca_cleanup_cq_table(dev); | |
902 | ||
903 | err_cmd_poll: | |
904 | mthca_cmd_use_polling(dev); | |
905 | ||
906 | err_eq_table_free: | |
907 | mthca_cleanup_eq_table(dev); | |
908 | ||
909 | err_pd_free: | |
910 | mthca_pd_free(dev, &dev->driver_pd); | |
911 | ||
912 | err_mr_table_free: | |
913 | mthca_cleanup_mr_table(dev); | |
914 | ||
915 | err_pd_table_free: | |
916 | mthca_cleanup_pd_table(dev); | |
917 | ||
918 | err_kar_unmap: | |
919 | iounmap(dev->kar); | |
920 | ||
921 | err_uar_free: | |
922 | mthca_uar_free(dev, &dev->driver_uar); | |
923 | ||
924 | err_uar_table_free: | |
925 | mthca_cleanup_uar_table(dev); | |
926 | return err; | |
927 | } | |
928 | ||
f4f3d0f0 | 929 | static int mthca_enable_msi_x(struct mthca_dev *mdev) |
1da177e4 LT |
930 | { |
931 | struct msix_entry entries[3]; | |
932 | int err; | |
933 | ||
934 | entries[0].entry = 0; | |
935 | entries[1].entry = 1; | |
936 | entries[2].entry = 2; | |
937 | ||
938 | err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries)); | |
939 | if (err) { | |
940 | if (err > 0) | |
941 | mthca_info(mdev, "Only %d MSI-X vectors available, " | |
942 | "not using MSI-X\n", err); | |
943 | return err; | |
944 | } | |
945 | ||
946 | mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector; | |
947 | mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector; | |
948 | mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector; | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
68a3c212 RD |
953 | /* Types of supported HCA */ |
954 | enum { | |
955 | TAVOR, /* MT23108 */ | |
956 | ARBEL_COMPAT, /* MT25208 in Tavor compat mode */ | |
957 | ARBEL_NATIVE, /* MT25208 with extended features */ | |
958 | SINAI /* MT25204 */ | |
959 | }; | |
960 | ||
961 | #define MTHCA_FW_VER(major, minor, subminor) \ | |
962 | (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor)) | |
963 | ||
964 | static struct { | |
965 | u64 latest_fw; | |
651eaac9 | 966 | u32 flags; |
68a3c212 | 967 | } mthca_hca_table[] = { |
3f114853 | 968 | [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0), |
651eaac9 | 969 | .flags = 0 }, |
3f114853 | 970 | [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200), |
651eaac9 | 971 | .flags = MTHCA_FLAG_PCIE }, |
950529e5 | 972 | [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0), |
651eaac9 EC |
973 | .flags = MTHCA_FLAG_MEMFREE | |
974 | MTHCA_FLAG_PCIE }, | |
3f114853 | 975 | [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0), |
651eaac9 EC |
976 | .flags = MTHCA_FLAG_MEMFREE | |
977 | MTHCA_FLAG_PCIE | | |
978 | MTHCA_FLAG_SINAI_OPT } | |
68a3c212 RD |
979 | }; |
980 | ||
b3b30f5e | 981 | static int __mthca_init_one(struct pci_dev *pdev, int hca_type) |
1da177e4 | 982 | { |
1da177e4 LT |
983 | int ddr_hidden = 0; |
984 | int err; | |
985 | struct mthca_dev *mdev; | |
986 | ||
982245f0 AB |
987 | printk(KERN_INFO PFX "Initializing %s\n", |
988 | pci_name(pdev)); | |
1da177e4 LT |
989 | |
990 | err = pci_enable_device(pdev); | |
991 | if (err) { | |
992 | dev_err(&pdev->dev, "Cannot enable PCI device, " | |
993 | "aborting.\n"); | |
994 | return err; | |
995 | } | |
996 | ||
997 | /* | |
998 | * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not | |
999 | * be present) | |
1000 | */ | |
1001 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || | |
1002 | pci_resource_len(pdev, 0) != 1 << 20) { | |
177214af | 1003 | dev_err(&pdev->dev, "Missing DCS, aborting.\n"); |
1da177e4 LT |
1004 | err = -ENODEV; |
1005 | goto err_disable_pdev; | |
1006 | } | |
cbd2981a | 1007 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
177214af | 1008 | dev_err(&pdev->dev, "Missing UAR, aborting.\n"); |
1da177e4 LT |
1009 | err = -ENODEV; |
1010 | goto err_disable_pdev; | |
1011 | } | |
1012 | if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM)) | |
1013 | ddr_hidden = 1; | |
1014 | ||
208dde28 | 1015 | err = pci_request_regions(pdev, DRV_NAME); |
1da177e4 LT |
1016 | if (err) { |
1017 | dev_err(&pdev->dev, "Cannot obtain PCI resources, " | |
1018 | "aborting.\n"); | |
1019 | goto err_disable_pdev; | |
1020 | } | |
1021 | ||
1022 | pci_set_master(pdev); | |
1023 | ||
6a35528a | 1024 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
1da177e4 LT |
1025 | if (err) { |
1026 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); | |
284901a9 | 1027 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 LT |
1028 | if (err) { |
1029 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); | |
1030 | goto err_free_res; | |
1031 | } | |
1032 | } | |
6a35528a | 1033 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
1da177e4 LT |
1034 | if (err) { |
1035 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " | |
1036 | "consistent PCI DMA mask.\n"); | |
284901a9 | 1037 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 LT |
1038 | if (err) { |
1039 | dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " | |
1040 | "aborting.\n"); | |
1041 | goto err_free_res; | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev); | |
1046 | if (!mdev) { | |
1047 | dev_err(&pdev->dev, "Device struct alloc failed, " | |
1048 | "aborting.\n"); | |
1049 | err = -ENOMEM; | |
1050 | goto err_free_res; | |
1051 | } | |
1052 | ||
68a3c212 | 1053 | mdev->pdev = pdev; |
1da177e4 | 1054 | |
b3b30f5e | 1055 | mdev->mthca_flags = mthca_hca_table[hca_type].flags; |
1da177e4 LT |
1056 | if (ddr_hidden) |
1057 | mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN; | |
1058 | ||
1059 | /* | |
1060 | * Now reset the HCA before we touch the PCI capabilities or | |
1061 | * attempt a firmware command, since a boot ROM may have left | |
1062 | * the HCA in an undefined state. | |
1063 | */ | |
1064 | err = mthca_reset(mdev); | |
1065 | if (err) { | |
1066 | mthca_err(mdev, "Failed to reset HCA, aborting.\n"); | |
1067 | goto err_free_dev; | |
1068 | } | |
1069 | ||
80fd8238 RD |
1070 | if (mthca_cmd_init(mdev)) { |
1071 | mthca_err(mdev, "Failed to init command interface, aborting.\n"); | |
1da177e4 LT |
1072 | goto err_free_dev; |
1073 | } | |
1074 | ||
1075 | err = mthca_tune_pci(mdev); | |
1076 | if (err) | |
80fd8238 | 1077 | goto err_cmd; |
1da177e4 LT |
1078 | |
1079 | err = mthca_init_hca(mdev); | |
1080 | if (err) | |
80fd8238 | 1081 | goto err_cmd; |
1da177e4 | 1082 | |
b3b30f5e | 1083 | if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) { |
e4daf738 | 1084 | mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n", |
68a3c212 RD |
1085 | (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff, |
1086 | (int) (mdev->fw_ver & 0xffff), | |
b3b30f5e JM |
1087 | (int) (mthca_hca_table[hca_type].latest_fw >> 32), |
1088 | (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff, | |
1089 | (int) (mthca_hca_table[hca_type].latest_fw & 0xffff)); | |
68a3c212 RD |
1090 | mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n"); |
1091 | } | |
1092 | ||
017aadc4 MT |
1093 | if (msi_x && !mthca_enable_msi_x(mdev)) |
1094 | mdev->mthca_flags |= MTHCA_FLAG_MSI_X; | |
017aadc4 | 1095 | |
1da177e4 | 1096 | err = mthca_setup_hca(mdev); |
e57895d3 | 1097 | if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) { |
017aadc4 MT |
1098 | if (mdev->mthca_flags & MTHCA_FLAG_MSI_X) |
1099 | pci_disable_msix(pdev); | |
e57895d3 | 1100 | mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X; |
017aadc4 MT |
1101 | |
1102 | err = mthca_setup_hca(mdev); | |
1103 | } | |
1104 | ||
1da177e4 LT |
1105 | if (err) |
1106 | goto err_close; | |
1107 | ||
1108 | err = mthca_register_device(mdev); | |
1109 | if (err) | |
1110 | goto err_cleanup; | |
1111 | ||
1112 | err = mthca_create_agents(mdev); | |
1113 | if (err) | |
1114 | goto err_unregister; | |
1115 | ||
1116 | pci_set_drvdata(pdev, mdev); | |
b3b30f5e | 1117 | mdev->hca_type = hca_type; |
1da177e4 | 1118 | |
d8410647 JM |
1119 | mdev->active = true; |
1120 | ||
1da177e4 LT |
1121 | return 0; |
1122 | ||
1123 | err_unregister: | |
1124 | mthca_unregister_device(mdev); | |
1125 | ||
1126 | err_cleanup: | |
1127 | mthca_cleanup_mcg_table(mdev); | |
1128 | mthca_cleanup_av_table(mdev); | |
1129 | mthca_cleanup_qp_table(mdev); | |
ec34a922 | 1130 | mthca_cleanup_srq_table(mdev); |
1da177e4 LT |
1131 | mthca_cleanup_cq_table(mdev); |
1132 | mthca_cmd_use_polling(mdev); | |
1133 | mthca_cleanup_eq_table(mdev); | |
1134 | ||
1135 | mthca_pd_free(mdev, &mdev->driver_pd); | |
1136 | ||
1137 | mthca_cleanup_mr_table(mdev); | |
1138 | mthca_cleanup_pd_table(mdev); | |
1139 | mthca_cleanup_uar_table(mdev); | |
1140 | ||
1141 | err_close: | |
017aadc4 MT |
1142 | if (mdev->mthca_flags & MTHCA_FLAG_MSI_X) |
1143 | pci_disable_msix(pdev); | |
017aadc4 | 1144 | |
1da177e4 LT |
1145 | mthca_close_hca(mdev); |
1146 | ||
80fd8238 RD |
1147 | err_cmd: |
1148 | mthca_cmd_cleanup(mdev); | |
1da177e4 LT |
1149 | |
1150 | err_free_dev: | |
1da177e4 LT |
1151 | ib_dealloc_device(&mdev->ib_dev); |
1152 | ||
1153 | err_free_res: | |
208dde28 | 1154 | pci_release_regions(pdev); |
1da177e4 LT |
1155 | |
1156 | err_disable_pdev: | |
1157 | pci_disable_device(pdev); | |
1158 | pci_set_drvdata(pdev, NULL); | |
1159 | return err; | |
1160 | } | |
1161 | ||
b3b30f5e | 1162 | static void __mthca_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
1163 | { |
1164 | struct mthca_dev *mdev = pci_get_drvdata(pdev); | |
1165 | u8 status; | |
1166 | int p; | |
1167 | ||
1168 | if (mdev) { | |
1169 | mthca_free_agents(mdev); | |
1170 | mthca_unregister_device(mdev); | |
1171 | ||
1172 | for (p = 1; p <= mdev->limits.num_ports; ++p) | |
1173 | mthca_CLOSE_IB(mdev, p, &status); | |
1174 | ||
1175 | mthca_cleanup_mcg_table(mdev); | |
1176 | mthca_cleanup_av_table(mdev); | |
1177 | mthca_cleanup_qp_table(mdev); | |
ec34a922 | 1178 | mthca_cleanup_srq_table(mdev); |
1da177e4 LT |
1179 | mthca_cleanup_cq_table(mdev); |
1180 | mthca_cmd_use_polling(mdev); | |
1181 | mthca_cleanup_eq_table(mdev); | |
1182 | ||
1183 | mthca_pd_free(mdev, &mdev->driver_pd); | |
1184 | ||
1185 | mthca_cleanup_mr_table(mdev); | |
1186 | mthca_cleanup_pd_table(mdev); | |
1187 | ||
1188 | iounmap(mdev->kar); | |
1189 | mthca_uar_free(mdev, &mdev->driver_uar); | |
1190 | mthca_cleanup_uar_table(mdev); | |
1da177e4 | 1191 | mthca_close_hca(mdev); |
80fd8238 | 1192 | mthca_cmd_cleanup(mdev); |
1da177e4 LT |
1193 | |
1194 | if (mdev->mthca_flags & MTHCA_FLAG_MSI_X) | |
1195 | pci_disable_msix(pdev); | |
1da177e4 LT |
1196 | |
1197 | ib_dealloc_device(&mdev->ib_dev); | |
208dde28 | 1198 | pci_release_regions(pdev); |
1da177e4 LT |
1199 | pci_disable_device(pdev); |
1200 | pci_set_drvdata(pdev, NULL); | |
1201 | } | |
1202 | } | |
1203 | ||
b3b30f5e JM |
1204 | int __mthca_restart_one(struct pci_dev *pdev) |
1205 | { | |
1206 | struct mthca_dev *mdev; | |
de57c9f1 | 1207 | int hca_type; |
b3b30f5e JM |
1208 | |
1209 | mdev = pci_get_drvdata(pdev); | |
1210 | if (!mdev) | |
1211 | return -ENODEV; | |
de57c9f1 | 1212 | hca_type = mdev->hca_type; |
b3b30f5e | 1213 | __mthca_remove_one(pdev); |
de57c9f1 | 1214 | return __mthca_init_one(pdev, hca_type); |
b3b30f5e JM |
1215 | } |
1216 | ||
1217 | static int __devinit mthca_init_one(struct pci_dev *pdev, | |
f4f3d0f0 | 1218 | const struct pci_device_id *id) |
b3b30f5e | 1219 | { |
b3b30f5e JM |
1220 | int ret; |
1221 | ||
1222 | mutex_lock(&mthca_device_mutex); | |
1223 | ||
f1aa78b2 | 1224 | printk_once(KERN_INFO "%s", mthca_version); |
b3b30f5e JM |
1225 | |
1226 | if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) { | |
1227 | printk(KERN_ERR PFX "%s has invalid driver data %lx\n", | |
1228 | pci_name(pdev), id->driver_data); | |
1229 | mutex_unlock(&mthca_device_mutex); | |
1230 | return -ENODEV; | |
1231 | } | |
1232 | ||
1233 | ret = __mthca_init_one(pdev, id->driver_data); | |
1234 | ||
1235 | mutex_unlock(&mthca_device_mutex); | |
1236 | ||
1237 | return ret; | |
1238 | } | |
1239 | ||
1240 | static void __devexit mthca_remove_one(struct pci_dev *pdev) | |
1241 | { | |
1242 | mutex_lock(&mthca_device_mutex); | |
1243 | __mthca_remove_one(pdev); | |
1244 | mutex_unlock(&mthca_device_mutex); | |
1245 | } | |
1246 | ||
1da177e4 LT |
1247 | static struct pci_device_id mthca_pci_table[] = { |
1248 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR), | |
1249 | .driver_data = TAVOR }, | |
1250 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR), | |
1251 | .driver_data = TAVOR }, | |
1252 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT), | |
1253 | .driver_data = ARBEL_COMPAT }, | |
1254 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT), | |
1255 | .driver_data = ARBEL_COMPAT }, | |
1256 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL), | |
1257 | .driver_data = ARBEL_NATIVE }, | |
1258 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL), | |
1259 | .driver_data = ARBEL_NATIVE }, | |
68a3c212 RD |
1260 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI), |
1261 | .driver_data = SINAI }, | |
1262 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI), | |
1263 | .driver_data = SINAI }, | |
1264 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD), | |
1265 | .driver_data = SINAI }, | |
1266 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD), | |
1267 | .driver_data = SINAI }, | |
1da177e4 LT |
1268 | { 0, } |
1269 | }; | |
1270 | ||
1271 | MODULE_DEVICE_TABLE(pci, mthca_pci_table); | |
1272 | ||
1273 | static struct pci_driver mthca_driver = { | |
177214af | 1274 | .name = DRV_NAME, |
1da177e4 LT |
1275 | .id_table = mthca_pci_table, |
1276 | .probe = mthca_init_one, | |
1277 | .remove = __devexit_p(mthca_remove_one) | |
1278 | }; | |
1279 | ||
82da703e LA |
1280 | static void __init __mthca_check_profile_val(const char *name, int *pval, |
1281 | int pval_default) | |
1282 | { | |
1283 | /* value must be positive and power of 2 */ | |
1284 | int old_pval = *pval; | |
1285 | ||
1286 | if (old_pval <= 0) | |
1287 | *pval = pval_default; | |
1288 | else | |
1289 | *pval = roundup_pow_of_two(old_pval); | |
1290 | ||
1291 | if (old_pval != *pval) { | |
1292 | printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n", | |
1293 | old_pval, name); | |
1294 | printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval); | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | #define mthca_check_profile_val(name, default) \ | |
1299 | __mthca_check_profile_val(#name, &hca_profile.name, default) | |
1300 | ||
1301 | static void __init mthca_validate_profile(void) | |
1302 | { | |
1303 | mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP); | |
1304 | mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP); | |
1305 | mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ); | |
1306 | mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG); | |
1307 | mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT); | |
1308 | mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT); | |
1309 | mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV); | |
1310 | mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS); | |
1311 | ||
1312 | if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) { | |
1313 | printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n", | |
1314 | hca_profile.fmr_reserved_mtts); | |
1315 | printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n", | |
1316 | hca_profile.num_mtt); | |
1317 | hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2; | |
1318 | printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n", | |
1319 | hca_profile.fmr_reserved_mtts); | |
1320 | } | |
c1f67a88 EC |
1321 | |
1322 | if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) { | |
1323 | printk(KERN_WARNING PFX "bad log_mtts_per_seg (%d). Using default - %d\n", | |
1324 | log_mtts_per_seg, ilog2(MTHCA_MTT_SEG_SIZE / 8)); | |
1325 | log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8); | |
1326 | } | |
82da703e LA |
1327 | } |
1328 | ||
1da177e4 LT |
1329 | static int __init mthca_init(void) |
1330 | { | |
1331 | int ret; | |
1332 | ||
82da703e LA |
1333 | mthca_validate_profile(); |
1334 | ||
b3b30f5e JM |
1335 | ret = mthca_catas_init(); |
1336 | if (ret) | |
1337 | return ret; | |
1338 | ||
1da177e4 | 1339 | ret = pci_register_driver(&mthca_driver); |
b3b30f5e JM |
1340 | if (ret < 0) { |
1341 | mthca_catas_cleanup(); | |
1342 | return ret; | |
1343 | } | |
1344 | ||
1345 | return 0; | |
1da177e4 LT |
1346 | } |
1347 | ||
1348 | static void __exit mthca_cleanup(void) | |
1349 | { | |
1350 | pci_unregister_driver(&mthca_driver); | |
b3b30f5e | 1351 | mthca_catas_cleanup(); |
1da177e4 LT |
1352 | } |
1353 | ||
1354 | module_init(mthca_init); | |
1355 | module_exit(mthca_cleanup); |