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IB/ehca: Remove tgid checking
[linux-block.git] / drivers / infiniband / hw / mthca / mthca_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
2a1d9b7f 4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
1da177e4
LT		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 *
34 * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
35 */
36
1da177e4
LT		 37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/errno.h>
40#include <linux/pci.h>
41#include <linux/interrupt.h>
42
43#include "mthca_dev.h"
44#include "mthca_config_reg.h"
45#include "mthca_cmd.h"
46#include "mthca_profile.h"
47#include "mthca_memfree.h"
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
52MODULE_VERSION(DRV_VERSION);
53
227c939b
RD		 54#ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
55
56int mthca_debug_level = 0;
57module_param_named(debug_level, mthca_debug_level, int, 0644);
58MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
59
60#endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
61
1da177e4
LT		 62#ifdef CONFIG_PCI_MSI
63
017aadc4 64static int msi_x = 1;
1da177e4
LT		 65module_param(msi_x, int, 0444);
66MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
67
1da177e4
LT		 68#else /* CONFIG_PCI_MSI */
69
70#define msi_x (0)
1da177e4
LT		 71
72#endif /* CONFIG_PCI_MSI */
73
abf45dbb
MT		 74static int tune_pci = 0;
75module_param(tune_pci, int, 0444);
76MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
77
0b0df6f2 78DEFINE_MUTEX(mthca_device_mutex);
b3b30f5e 79
82da703e
LA		 80#define MTHCA_DEFAULT_NUM_QP (1 << 16)
81#define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
82#define MTHCA_DEFAULT_NUM_CQ (1 << 16)
83#define MTHCA_DEFAULT_NUM_MCG (1 << 13)
84#define MTHCA_DEFAULT_NUM_MPT (1 << 17)
85#define MTHCA_DEFAULT_NUM_MTT (1 << 20)
86#define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
87#define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
88#define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
89
90static struct mthca_profile hca_profile = {
91 .num_qp = MTHCA_DEFAULT_NUM_QP,
92 .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
93 .num_cq = MTHCA_DEFAULT_NUM_CQ,
94 .num_mcg = MTHCA_DEFAULT_NUM_MCG,
95 .num_mpt = MTHCA_DEFAULT_NUM_MPT,
96 .num_mtt = MTHCA_DEFAULT_NUM_MTT,
97 .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
98 .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
99 .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
100};
101
102module_param_named(num_qp, hca_profile.num_qp, int, 0444);
103MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
104
105module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
106MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
107
108module_param_named(num_cq, hca_profile.num_cq, int, 0444);
109MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
110
111module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
112MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
113
114module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
115MODULE_PARM_DESC(num_mpt,
116 "maximum number of memory protection table entries per HCA");
117
118module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
119MODULE_PARM_DESC(num_mtt,
120 "maximum number of memory translation table segments per HCA");
121
122module_param_named(num_udav, hca_profile.num_udav, int, 0444);
123MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
124
125module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
126MODULE_PARM_DESC(fmr_reserved_mtts,
127 "number of memory translation table segments reserved for FMR");
128
f33afc26 129static char mthca_version[] __devinitdata =
177214af 130 DRV_NAME ": Mellanox InfiniBand HCA driver v"
1da177e4
LT		 131 DRV_VERSION " (" DRV_RELDATE ")\n";
132
f4f3d0f0 133static int mthca_tune_pci(struct mthca_dev *mdev)
1da177e4 134{
abf45dbb
MT		 135 if (!tune_pci)
136 return 0;
137
1da177e4 138 /* First try to max out Read Byte Count */
a855b1a7
PO		 139 if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
140 if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
141 mthca_err(mdev, "Couldn't set PCI-X max read count, "
142 "aborting.\n");
1da177e4
LT		 143 return -ENODEV;
144 }
68a3c212 145 } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
1da177e4
LT		 146 mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
147
a855b1a7
PO		 148 if (pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP)) {
149 if (pcie_set_readrq(mdev->pdev, 4096)) {
150 mthca_err(mdev, "Couldn't write PCI Express read request, "
151 "aborting.\n");
1da177e4
LT		 152 return -ENODEV;
153 }
68a3c212 154 } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
1da177e4
LT		 155 mthca_info(mdev, "No PCI Express capability, "
156 "not setting Max Read Request Size.\n");
157
158 return 0;
159}
160
f4f3d0f0 161static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
1da177e4
LT		 162{
163 int err;
164 u8 status;
165
166 err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
167 if (err) {
168 mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
169 return err;
170 }
171 if (status) {
172 mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
173 "aborting.\n", status);
174 return -EINVAL;
175 }
176 if (dev_lim->min_page_sz > PAGE_SIZE) {
177 mthca_err(mdev, "HCA minimum page size of %d bigger than "
178 "kernel PAGE_SIZE of %ld, aborting.\n",
179 dev_lim->min_page_sz, PAGE_SIZE);
180 return -ENODEV;
181 }
182 if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
183 mthca_err(mdev, "HCA has %d ports, but we only support %d, "
184 "aborting.\n",
185 dev_lim->num_ports, MTHCA_MAX_PORTS);
186 return -ENODEV;
187 }
188
cbd2981a
MT		 189 if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
190 mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
e29419ff
GKH		 191 "PCI resource 2 size of 0x%llx, aborting.\n",
192 dev_lim->uar_size,
193 (unsigned long long)pci_resource_len(mdev->pdev, 2));
cbd2981a
MT		 194 return -ENODEV;
195 }
196
1da177e4
LT		 197 mdev->limits.num_ports = dev_lim->num_ports;
198 mdev->limits.vl_cap = dev_lim->max_vl;
199 mdev->limits.mtu_cap = dev_lim->max_mtu;
200 mdev->limits.gid_table_len = dev_lim->max_gids;
201 mdev->limits.pkey_table_len = dev_lim->max_pkeys;
202 mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
203 mdev->limits.max_sg = dev_lim->max_sg;
efaae8f7
JM		 204 mdev->limits.max_wqes = dev_lim->max_qp_sz;
205 mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
1da177e4 206 mdev->limits.reserved_qps = dev_lim->reserved_qps;
efaae8f7 207 mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
1da177e4
LT		 208 mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
209 mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
77369ed3 210 mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
59fef3b1 211 mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
efaae8f7
JM		 212 /*
213 * Subtract 1 from the limit because we need to allocate a
214 * spare CQE so the HCA HW can tell the difference between an
215 * empty CQ and a full CQ.
216 */
217 mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
1da177e4
LT		 218 mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
219 mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
220 mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
221 mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
222 mdev->limits.reserved_uars = dev_lim->reserved_uars;
223 mdev->limits.reserved_pds = dev_lim->reserved_pds;
da6561c2 224 mdev->limits.port_width_cap = dev_lim->max_port_width;
0f69ce1e 225 mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
33033b79 226 mdev->limits.flags = dev_lim->flags;
bf6a9e31
JM		 227 /*
228 * For old FW that doesn't return static rate support, use a
229 * value of 0x3 (only static rate values of 0 or 1 are handled),
230 * except on Sinai, where even old FW can handle static rate
231 * values of 2 and 3.
232 */
233 if (dev_lim->stat_rate_support)
234 mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
235 else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
236 mdev->limits.stat_rate_support = 0xf;
237 else
238 mdev->limits.stat_rate_support = 0x3;
1da177e4
LT		 239
240 /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
241 May be doable since hardware supports it for SRQ.
242
243 IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
244
245 IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
246 supported by driver. */
247 mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
248 IB_DEVICE_PORT_ACTIVE_EVENT |
249 IB_DEVICE_SYS_IMAGE_GUID |
250 IB_DEVICE_RC_RNR_NAK_GEN;
251
252 if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
253 mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
254
255 if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
256 mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
257
258 if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
259 mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
260
261 if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
262 mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
263
264 if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
265 mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
266
267 if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
268 mdev->mthca_flags |= MTHCA_FLAG_SRQ;
269
680b575f
EC		 270 if (mthca_is_memfree(mdev))
271 if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
272 mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
273
1da177e4
LT		 274 return 0;
275}
276
f4f3d0f0 277static int mthca_init_tavor(struct mthca_dev *mdev)
1da177e4
LT		 278{
279 u8 status;
280 int err;
281 struct mthca_dev_lim dev_lim;
282 struct mthca_profile profile;
283 struct mthca_init_hca_param init_hca;
1da177e4
LT		 284
285 err = mthca_SYS_EN(mdev, &status);
286 if (err) {
287 mthca_err(mdev, "SYS_EN command failed, aborting.\n");
288 return err;
289 }
290 if (status) {
291 mthca_err(mdev, "SYS_EN returned status 0x%02x, "
292 "aborting.\n", status);
293 return -EINVAL;
294 }
295
296 err = mthca_QUERY_FW(mdev, &status);
297 if (err) {
298 mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
299 goto err_disable;
300 }
301 if (status) {
302 mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
303 "aborting.\n", status);
304 err = -EINVAL;
305 goto err_disable;
306 }
307 err = mthca_QUERY_DDR(mdev, &status);
308 if (err) {
309 mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
310 goto err_disable;
311 }
312 if (status) {
313 mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
314 "aborting.\n", status);
315 err = -EINVAL;
316 goto err_disable;
317 }
318
319 err = mthca_dev_lim(mdev, &dev_lim);
aa2f9367
JM		 320 if (err) {
321 mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
322 goto err_disable;
323 }
1da177e4 324
82da703e 325 profile = hca_profile;
1da177e4
LT		 326 profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
327 profile.uarc_size = 0;
ec34a922
RD		 328 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
329 profile.num_srq = dev_lim.max_srqs;
1da177e4
LT		 330
331 err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
332 if (err < 0)
333 goto err_disable;
334
335 err = mthca_INIT_HCA(mdev, &init_hca, &status);
336 if (err) {
337 mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
338 goto err_disable;
339 }
340 if (status) {
341 mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
342 "aborting.\n", status);
343 err = -EINVAL;
344 goto err_disable;
345 }
346
1da177e4
LT		 347 return 0;
348
1da177e4
LT		 349err_disable:
350 mthca_SYS_DIS(mdev, &status);
351
352 return err;
353}
354
f4f3d0f0 355static int mthca_load_fw(struct mthca_dev *mdev)
1da177e4
LT		 356{
357 u8 status;
358 int err;
359
360 /* FIXME: use HCA-attached memory for FW if present */
361
362 mdev->fw.arbel.fw_icm =
363 mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
391e4dea 364 GFP_HIGHUSER | __GFP_NOWARN, 0);
1da177e4
LT		 365 if (!mdev->fw.arbel.fw_icm) {
366 mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
367 return -ENOMEM;
368 }
369
370 err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
371 if (err) {
372 mthca_err(mdev, "MAP_FA command failed, aborting.\n");
373 goto err_free;
374 }
375 if (status) {
376 mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
377 err = -EINVAL;
378 goto err_free;
379 }
380 err = mthca_RUN_FW(mdev, &status);
381 if (err) {
382 mthca_err(mdev, "RUN_FW command failed, aborting.\n");
383 goto err_unmap_fa;
384 }
385 if (status) {
386 mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
387 err = -EINVAL;
388 goto err_unmap_fa;
389 }
390
391 return 0;
392
393err_unmap_fa:
394 mthca_UNMAP_FA(mdev, &status);
395
396err_free:
391e4dea 397 mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
1da177e4
LT		 398 return err;
399}
400
f4f3d0f0
RD		 401static int mthca_init_icm(struct mthca_dev *mdev,
402 struct mthca_dev_lim *dev_lim,
403 struct mthca_init_hca_param *init_hca,
404 u64 icm_size)
1da177e4
LT		 405{
406 u64 aux_pages;
407 u8 status;
408 int err;
409
410 err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
411 if (err) {
412 mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
413 return err;
414 }
415 if (status) {
416 mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
417 "aborting.\n", status);
418 return -EINVAL;
419 }
420
421 mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
422 (unsigned long long) icm_size >> 10,
423 (unsigned long long) aux_pages << 2);
424
425 mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
391e4dea 426 GFP_HIGHUSER | __GFP_NOWARN, 0);
1da177e4
LT		 427 if (!mdev->fw.arbel.aux_icm) {
428 mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
429 return -ENOMEM;
430 }
431
432 err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
433 if (err) {
434 mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
435 goto err_free_aux;
436 }
437 if (status) {
438 mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
439 err = -EINVAL;
440 goto err_free_aux;
441 }
442
443 err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
444 if (err) {
445 mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
446 goto err_unmap_aux;
447 }
448
1d1f19cf
MT		 449 /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
450 mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * MTHCA_MTT_SEG_SIZE,
451 dma_get_cache_alignment()) / MTHCA_MTT_SEG_SIZE;
452
1da177e4 453 mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
44ea6687 454 MTHCA_MTT_SEG_SIZE,
1da177e4 455 mdev->limits.num_mtt_segs,
391e4dea
MT		 456 mdev->limits.reserved_mtts,
457 1, 0);
1da177e4
LT		 458 if (!mdev->mr_table.mtt_table) {
459 mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
460 err = -ENOMEM;
461 goto err_unmap_eq;
462 }
463
464 mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
465 dev_lim->mpt_entry_sz,
466 mdev->limits.num_mpts,
391e4dea
MT		 467 mdev->limits.reserved_mrws,
468 1, 1);
1da177e4
LT		 469 if (!mdev->mr_table.mpt_table) {
470 mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
471 err = -ENOMEM;
472 goto err_unmap_mtt;
473 }
474
475 mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
476 dev_lim->qpc_entry_sz,
477 mdev->limits.num_qps,
391e4dea
MT		 478 mdev->limits.reserved_qps,
479 0, 0);
1da177e4
LT		 480 if (!mdev->qp_table.qp_table) {
481 mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
482 err = -ENOMEM;
483 goto err_unmap_mpt;
484 }
485
486 mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
487 dev_lim->eqpc_entry_sz,
488 mdev->limits.num_qps,
391e4dea
MT		 489 mdev->limits.reserved_qps,
490 0, 0);
1da177e4
LT		 491 if (!mdev->qp_table.eqp_table) {
492 mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
493 err = -ENOMEM;
494 goto err_unmap_qp;
495 }
496
08aeb14e
RD		 497 mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
498 MTHCA_RDB_ENTRY_SIZE,
499 mdev->limits.num_qps <<
391e4dea 500 mdev->qp_table.rdb_shift, 0,
08aeb14e
RD		 501 0, 0);
502 if (!mdev->qp_table.rdb_table) {
503 mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
504 err = -ENOMEM;
19272d43 505 goto err_unmap_eqp;
08aeb14e
RD		 506 }
507
508 mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
ec34a922
RD		 509 dev_lim->cqc_entry_sz,
510 mdev->limits.num_cqs,
391e4dea
MT		 511 mdev->limits.reserved_cqs,
512 0, 0);
1da177e4
LT		 513 if (!mdev->cq_table.table) {
514 mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
515 err = -ENOMEM;
08aeb14e 516 goto err_unmap_rdb;
1da177e4
LT		 517 }
518
ec34a922
RD		 519 if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
520 mdev->srq_table.table =
521 mthca_alloc_icm_table(mdev, init_hca->srqc_base,
522 dev_lim->srq_entry_sz,
523 mdev->limits.num_srqs,
391e4dea
MT		 524 mdev->limits.reserved_srqs,
525 0, 0);
ec34a922
RD		 526 if (!mdev->srq_table.table) {
527 mthca_err(mdev, "Failed to map SRQ context memory, "
528 "aborting.\n");
529 err = -ENOMEM;
530 goto err_unmap_cq;
531 }
532 }
533
1da177e4
LT		 534 /*
535 * It's not strictly required, but for simplicity just map the
536 * whole multicast group table now. The table isn't very big
537 * and it's a lot easier than trying to track ref counts.
538 */
539 mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
540 MTHCA_MGM_ENTRY_SIZE,
541 mdev->limits.num_mgms +
542 mdev->limits.num_amgms,
543 mdev->limits.num_mgms +
544 mdev->limits.num_amgms,
391e4dea 545 0, 0);
1da177e4
LT		 546 if (!mdev->mcg_table.table) {
547 mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
548 err = -ENOMEM;
ec34a922 549 goto err_unmap_srq;
1da177e4
LT		 550 }
551
552 return 0;
553
ec34a922
RD		 554err_unmap_srq:
555 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
556 mthca_free_icm_table(mdev, mdev->srq_table.table);
557
1da177e4
LT		 558err_unmap_cq:
559 mthca_free_icm_table(mdev, mdev->cq_table.table);
560
08aeb14e
RD		 561err_unmap_rdb:
562 mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
563
1da177e4
LT		 564err_unmap_eqp:
565 mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
566
567err_unmap_qp:
568 mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
569
570err_unmap_mpt:
571 mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
572
573err_unmap_mtt:
574 mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
575
576err_unmap_eq:
577 mthca_unmap_eq_icm(mdev);
578
579err_unmap_aux:
580 mthca_UNMAP_ICM_AUX(mdev, &status);
581
582err_free_aux:
391e4dea 583 mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
1da177e4
LT		 584
585 return err;
586}
587
aba7a22f
MT		 588static void mthca_free_icms(struct mthca_dev *mdev)
589{
590 u8 status;
591
592 mthca_free_icm_table(mdev, mdev->mcg_table.table);
593 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
594 mthca_free_icm_table(mdev, mdev->srq_table.table);
595 mthca_free_icm_table(mdev, mdev->cq_table.table);
596 mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
597 mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
598 mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
599 mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
600 mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
601 mthca_unmap_eq_icm(mdev);
602
603 mthca_UNMAP_ICM_AUX(mdev, &status);
391e4dea 604 mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
aba7a22f
MT		 605}
606
f4f3d0f0 607static int mthca_init_arbel(struct mthca_dev *mdev)
1da177e4
LT		 608{
609 struct mthca_dev_lim dev_lim;
610 struct mthca_profile profile;
611 struct mthca_init_hca_param init_hca;
1da177e4
LT		 612 u64 icm_size;
613 u8 status;
614 int err;
615
616 err = mthca_QUERY_FW(mdev, &status);
617 if (err) {
618 mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
619 return err;
620 }
621 if (status) {
622 mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
623 "aborting.\n", status);
624 return -EINVAL;
625 }
626
627 err = mthca_ENABLE_LAM(mdev, &status);
628 if (err) {
629 mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
630 return err;
631 }
632 if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
633 mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
634 mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
635 } else if (status) {
636 mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
637 "aborting.\n", status);
638 return -EINVAL;
639 }
640
641 err = mthca_load_fw(mdev);
642 if (err) {
643 mthca_err(mdev, "Failed to start FW, aborting.\n");
644 goto err_disable;
645 }
646
647 err = mthca_dev_lim(mdev, &dev_lim);
648 if (err) {
649 mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
650 goto err_stop_fw;
651 }
652
82da703e 653 profile = hca_profile;
1da177e4
LT		 654 profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
655 profile.num_udav = 0;
ec34a922
RD		 656 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
657 profile.num_srq = dev_lim.max_srqs;
1da177e4
LT		 658
659 icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
660 if ((int) icm_size < 0) {
661 err = icm_size;
662 goto err_stop_fw;
663 }
664
665 err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
666 if (err)
667 goto err_stop_fw;
668
669 err = mthca_INIT_HCA(mdev, &init_hca, &status);
670 if (err) {
671 mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
672 goto err_free_icm;
673 }
674 if (status) {
675 mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
676 "aborting.\n", status);
677 err = -EINVAL;
678 goto err_free_icm;
679 }
680
1da177e4
LT		 681 return 0;
682
683err_free_icm:
aba7a22f 684 mthca_free_icms(mdev);
1da177e4
LT		 685
686err_stop_fw:
687 mthca_UNMAP_FA(mdev, &status);
391e4dea 688 mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
1da177e4
LT		 689
690err_disable:
691 if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
692 mthca_DISABLE_LAM(mdev, &status);
693
694 return err;
695}
696
2e8b981c
MT		 697static void mthca_close_hca(struct mthca_dev *mdev)
698{
699 u8 status;
700
701 mthca_CLOSE_HCA(mdev, 0, &status);
702
703 if (mthca_is_memfree(mdev)) {
aba7a22f 704 mthca_free_icms(mdev);
2e8b981c
MT		 705
706 mthca_UNMAP_FA(mdev, &status);
391e4dea 707 mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
2e8b981c
MT		 708
709 if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
710 mthca_DISABLE_LAM(mdev, &status);
711 } else
712 mthca_SYS_DIS(mdev, &status);
713}
714
f4f3d0f0 715static int mthca_init_hca(struct mthca_dev *mdev)
1da177e4 716{
2e8b981c
MT		 717 u8 status;
718 int err;
719 struct mthca_adapter adapter;
720
d10ddbf6 721 if (mthca_is_memfree(mdev))
2e8b981c 722 err = mthca_init_arbel(mdev);
1da177e4 723 else
2e8b981c
MT		 724 err = mthca_init_tavor(mdev);
725
726 if (err)
727 return err;
728
729 err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
730 if (err) {
731 mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
732 goto err_close;
733 }
734 if (status) {
735 mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
736 "aborting.\n", status);
737 err = -EINVAL;
738 goto err_close;
739 }
740
741 mdev->eq_table.inta_pin = adapter.inta_pin;
6ccef1de
JM		 742 if (!mthca_is_memfree(mdev))
743 mdev->rev_id = adapter.revision_id;
2e8b981c
MT		 744 memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
745
746 return 0;
747
748err_close:
749 mthca_close_hca(mdev);
750 return err;
1da177e4
LT		 751}
752
f4f3d0f0 753static int mthca_setup_hca(struct mthca_dev *dev)
1da177e4
LT		 754{
755 int err;
756 u8 status;
757
758 MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
759
760 err = mthca_init_uar_table(dev);
761 if (err) {
762 mthca_err(dev, "Failed to initialize "
763 "user access region table, aborting.\n");
764 return err;
765 }
766
767 err = mthca_uar_alloc(dev, &dev->driver_uar);
768 if (err) {
769 mthca_err(dev, "Failed to allocate driver access region, "
770 "aborting.\n");
771 goto err_uar_table_free;
772 }
773
774 dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
775 if (!dev->kar) {
776 mthca_err(dev, "Couldn't map kernel access region, "
777 "aborting.\n");
778 err = -ENOMEM;
779 goto err_uar_free;
780 }
781
782 err = mthca_init_pd_table(dev);
783 if (err) {
784 mthca_err(dev, "Failed to initialize "
785 "protection domain table, aborting.\n");
786 goto err_kar_unmap;
787 }
788
789 err = mthca_init_mr_table(dev);
790 if (err) {
791 mthca_err(dev, "Failed to initialize "
792 "memory region table, aborting.\n");
793 goto err_pd_table_free;
794 }
795
99264c1e 796 err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
1da177e4
LT		 797 if (err) {
798 mthca_err(dev, "Failed to create driver PD, "
799 "aborting.\n");
800 goto err_mr_table_free;
801 }
802
803 err = mthca_init_eq_table(dev);
804 if (err) {
805 mthca_err(dev, "Failed to initialize "
806 "event queue table, aborting.\n");
807 goto err_pd_free;
808 }
809
810 err = mthca_cmd_use_events(dev);
811 if (err) {
812 mthca_err(dev, "Failed to switch to event-driven "
813 "firmware commands, aborting.\n");
814 goto err_eq_table_free;
815 }
816
817 err = mthca_NOP(dev, &status);
818 if (err || status) {
e57895d3 819 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
017aadc4
MT		 820 mthca_warn(dev, "NOP command failed to generate interrupt "
821 "(IRQ %d).\n",
e57895d3
AB		 822 dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
823 mthca_warn(dev, "Trying again with MSI-X disabled.\n");
017aadc4
MT		 824 } else {
825 mthca_err(dev, "NOP command failed to generate interrupt "
826 "(IRQ %d), aborting.\n",
827 dev->pdev->irq);
1da177e4 828 mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
017aadc4 829 }
1da177e4
LT		 830
831 goto err_cmd_poll;
832 }
833
834 mthca_dbg(dev, "NOP command IRQ test passed\n");
835
836 err = mthca_init_cq_table(dev);
837 if (err) {
838 mthca_err(dev, "Failed to initialize "
839 "completion queue table, aborting.\n");
840 goto err_cmd_poll;
841 }
842
ec34a922
RD		 843 err = mthca_init_srq_table(dev);
844 if (err) {
845 mthca_err(dev, "Failed to initialize "
846 "shared receive queue table, aborting.\n");
847 goto err_cq_table_free;
848 }
849
1da177e4
LT		 850 err = mthca_init_qp_table(dev);
851 if (err) {
852 mthca_err(dev, "Failed to initialize "
853 "queue pair table, aborting.\n");
ec34a922 854 goto err_srq_table_free;
1da177e4
LT		 855 }
856
857 err = mthca_init_av_table(dev);
858 if (err) {
859 mthca_err(dev, "Failed to initialize "
860 "address vector table, aborting.\n");
861 goto err_qp_table_free;
862 }
863
864 err = mthca_init_mcg_table(dev);
865 if (err) {
866 mthca_err(dev, "Failed to initialize "
867 "multicast group table, aborting.\n");
868 goto err_av_table_free;
869 }
870
871 return 0;
872
873err_av_table_free:
874 mthca_cleanup_av_table(dev);
875
876err_qp_table_free:
877 mthca_cleanup_qp_table(dev);
878
ec34a922
RD		 879err_srq_table_free:
880 mthca_cleanup_srq_table(dev);
881
1da177e4
LT		 882err_cq_table_free:
883 mthca_cleanup_cq_table(dev);
884
885err_cmd_poll:
886 mthca_cmd_use_polling(dev);
887
888err_eq_table_free:
889 mthca_cleanup_eq_table(dev);
890
891err_pd_free:
892 mthca_pd_free(dev, &dev->driver_pd);
893
894err_mr_table_free:
895 mthca_cleanup_mr_table(dev);
896
897err_pd_table_free:
898 mthca_cleanup_pd_table(dev);
899
900err_kar_unmap:
901 iounmap(dev->kar);
902
903err_uar_free:
904 mthca_uar_free(dev, &dev->driver_uar);
905
906err_uar_table_free:
907 mthca_cleanup_uar_table(dev);
908 return err;
909}
910
f4f3d0f0 911static int mthca_request_regions(struct pci_dev *pdev, int ddr_hidden)
1da177e4
LT		 912{
913 int err;
914
915 /*
916 * We can't just use pci_request_regions() because the MSI-X
917 * table is right in the middle of the first BAR. If we did
918 * pci_request_region and grab all of the first BAR, then
919 * setting up MSI-X would fail, since the PCI core wants to do
920 * request_mem_region on the MSI-X vector table.
921 *
922 * So just request what we need right now, and request any
923 * other regions we need when setting up EQs.
924 */
925 if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
926 MTHCA_HCR_SIZE, DRV_NAME))
927 return -EBUSY;
928
929 err = pci_request_region(pdev, 2, DRV_NAME);
930 if (err)
931 goto err_bar2_failed;
932
933 if (!ddr_hidden) {
934 err = pci_request_region(pdev, 4, DRV_NAME);
935 if (err)
936 goto err_bar4_failed;
937 }
938
939 return 0;
940
941err_bar4_failed:
942 pci_release_region(pdev, 2);
943
944err_bar2_failed:
945 release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
946 MTHCA_HCR_SIZE);
947
948 return err;
949}
950
951static void mthca_release_regions(struct pci_dev *pdev,
952 int ddr_hidden)
953{
954 if (!ddr_hidden)
955 pci_release_region(pdev, 4);
956
957 pci_release_region(pdev, 2);
958
959 release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
960 MTHCA_HCR_SIZE);
961}
962
f4f3d0f0 963static int mthca_enable_msi_x(struct mthca_dev *mdev)
1da177e4
LT		 964{
965 struct msix_entry entries[3];
966 int err;
967
968 entries[0].entry = 0;
969 entries[1].entry = 1;
970 entries[2].entry = 2;
971
972 err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
973 if (err) {
974 if (err > 0)
975 mthca_info(mdev, "Only %d MSI-X vectors available, "
976 "not using MSI-X\n", err);
977 return err;
978 }
979
980 mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
981 mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
982 mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
983
984 return 0;
985}
986
68a3c212
RD		 987/* Types of supported HCA */
988enum {
989 TAVOR, /* MT23108 */
990 ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
991 ARBEL_NATIVE, /* MT25208 with extended features */
992 SINAI /* MT25204 */
993};
994
995#define MTHCA_FW_VER(major, minor, subminor) \
996 (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
997
998static struct {
999 u64 latest_fw;
651eaac9 1000 u32 flags;
68a3c212 1001} mthca_hca_table[] = {
3f114853 1002 [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
651eaac9 1003 .flags = 0 },
3f114853 1004 [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
651eaac9 1005 .flags = MTHCA_FLAG_PCIE },
950529e5 1006 [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
651eaac9
EC		 1007 .flags = MTHCA_FLAG_MEMFREE |
1008 MTHCA_FLAG_PCIE },
3f114853 1009 [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
651eaac9
EC		 1010 .flags = MTHCA_FLAG_MEMFREE |
1011 MTHCA_FLAG_PCIE |
1012 MTHCA_FLAG_SINAI_OPT }
68a3c212
RD		 1013};
1014
b3b30f5e 1015static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
1da177e4 1016{
1da177e4
LT		 1017 int ddr_hidden = 0;
1018 int err;
1019 struct mthca_dev *mdev;
1020
982245f0
AB		 1021 printk(KERN_INFO PFX "Initializing %s\n",
1022 pci_name(pdev));
1da177e4
LT		 1023
1024 err = pci_enable_device(pdev);
1025 if (err) {
1026 dev_err(&pdev->dev, "Cannot enable PCI device, "
1027 "aborting.\n");
1028 return err;
1029 }
1030
1031 /*
1032 * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
1033 * be present)
1034 */
1035 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1036 pci_resource_len(pdev, 0) != 1 << 20) {
177214af 1037 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1da177e4
LT		 1038 err = -ENODEV;
1039 goto err_disable_pdev;
1040 }
cbd2981a 1041 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
177214af 1042 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1da177e4
LT		 1043 err = -ENODEV;
1044 goto err_disable_pdev;
1045 }
1046 if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
1047 ddr_hidden = 1;
1048
1049 err = mthca_request_regions(pdev, ddr_hidden);
1050 if (err) {
1051 dev_err(&pdev->dev, "Cannot obtain PCI resources, "
1052 "aborting.\n");
1053 goto err_disable_pdev;
1054 }
1055
1056 pci_set_master(pdev);
1057
1058 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1059 if (err) {
1060 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1061 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1062 if (err) {
1063 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1064 goto err_free_res;
1065 }
1066 }
1067 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1068 if (err) {
1069 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1070 "consistent PCI DMA mask.\n");
1071 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1072 if (err) {
1073 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1074 "aborting.\n");
1075 goto err_free_res;
1076 }
1077 }
1078
1079 mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
1080 if (!mdev) {
1081 dev_err(&pdev->dev, "Device struct alloc failed, "
1082 "aborting.\n");
1083 err = -ENOMEM;
1084 goto err_free_res;
1085 }
1086
68a3c212 1087 mdev->pdev = pdev;
1da177e4 1088
b3b30f5e 1089 mdev->mthca_flags = mthca_hca_table[hca_type].flags;
1da177e4
LT		 1090 if (ddr_hidden)
1091 mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
1092
1093 /*
1094 * Now reset the HCA before we touch the PCI capabilities or
1095 * attempt a firmware command, since a boot ROM may have left
1096 * the HCA in an undefined state.
1097 */
1098 err = mthca_reset(mdev);
1099 if (err) {
1100 mthca_err(mdev, "Failed to reset HCA, aborting.\n");
1101 goto err_free_dev;
1102 }
1103
80fd8238
RD		 1104 if (mthca_cmd_init(mdev)) {
1105 mthca_err(mdev, "Failed to init command interface, aborting.\n");
1da177e4
LT		 1106 goto err_free_dev;
1107 }
1108
1109 err = mthca_tune_pci(mdev);
1110 if (err)
80fd8238 1111 goto err_cmd;
1da177e4
LT		 1112
1113 err = mthca_init_hca(mdev);
1114 if (err)
80fd8238 1115 goto err_cmd;
1da177e4 1116
b3b30f5e 1117 if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
e4daf738 1118 mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
68a3c212
RD		 1119 (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
1120 (int) (mdev->fw_ver & 0xffff),
b3b30f5e
JM		 1121 (int) (mthca_hca_table[hca_type].latest_fw >> 32),
1122 (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
1123 (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
68a3c212
RD		 1124 mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
1125 }
1126
017aadc4
MT		 1127 if (msi_x && !mthca_enable_msi_x(mdev))
1128 mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
017aadc4 1129
1da177e4 1130 err = mthca_setup_hca(mdev);
e57895d3 1131 if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
017aadc4
MT		 1132 if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
1133 pci_disable_msix(pdev);
e57895d3 1134 mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
017aadc4
MT		 1135
1136 err = mthca_setup_hca(mdev);
1137 }
1138
1da177e4
LT		 1139 if (err)
1140 goto err_close;
1141
1142 err = mthca_register_device(mdev);
1143 if (err)
1144 goto err_cleanup;
1145
1146 err = mthca_create_agents(mdev);
1147 if (err)
1148 goto err_unregister;
1149
1150 pci_set_drvdata(pdev, mdev);
b3b30f5e 1151 mdev->hca_type = hca_type;
1da177e4
LT		 1152
1153 return 0;
1154
1155err_unregister:
1156 mthca_unregister_device(mdev);
1157
1158err_cleanup:
1159 mthca_cleanup_mcg_table(mdev);
1160 mthca_cleanup_av_table(mdev);
1161 mthca_cleanup_qp_table(mdev);
ec34a922 1162 mthca_cleanup_srq_table(mdev);
1da177e4
LT		 1163 mthca_cleanup_cq_table(mdev);
1164 mthca_cmd_use_polling(mdev);
1165 mthca_cleanup_eq_table(mdev);
1166
1167 mthca_pd_free(mdev, &mdev->driver_pd);
1168
1169 mthca_cleanup_mr_table(mdev);
1170 mthca_cleanup_pd_table(mdev);
1171 mthca_cleanup_uar_table(mdev);
1172
1173err_close:
017aadc4
MT		 1174 if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
1175 pci_disable_msix(pdev);
017aadc4 1176
1da177e4
LT		 1177 mthca_close_hca(mdev);
1178
80fd8238
RD		 1179err_cmd:
1180 mthca_cmd_cleanup(mdev);
1da177e4
LT		 1181
1182err_free_dev:
1da177e4
LT		 1183 ib_dealloc_device(&mdev->ib_dev);
1184
1185err_free_res:
1186 mthca_release_regions(pdev, ddr_hidden);
1187
1188err_disable_pdev:
1189 pci_disable_device(pdev);
1190 pci_set_drvdata(pdev, NULL);
1191 return err;
1192}
1193
b3b30f5e 1194static void __mthca_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1195{
1196 struct mthca_dev *mdev = pci_get_drvdata(pdev);
1197 u8 status;
1198 int p;
1199
1200 if (mdev) {
1201 mthca_free_agents(mdev);
1202 mthca_unregister_device(mdev);
1203
1204 for (p = 1; p <= mdev->limits.num_ports; ++p)
1205 mthca_CLOSE_IB(mdev, p, &status);
1206
1207 mthca_cleanup_mcg_table(mdev);
1208 mthca_cleanup_av_table(mdev);
1209 mthca_cleanup_qp_table(mdev);
ec34a922 1210 mthca_cleanup_srq_table(mdev);
1da177e4
LT		 1211 mthca_cleanup_cq_table(mdev);
1212 mthca_cmd_use_polling(mdev);
1213 mthca_cleanup_eq_table(mdev);
1214
1215 mthca_pd_free(mdev, &mdev->driver_pd);
1216
1217 mthca_cleanup_mr_table(mdev);
1218 mthca_cleanup_pd_table(mdev);
1219
1220 iounmap(mdev->kar);
1221 mthca_uar_free(mdev, &mdev->driver_uar);
1222 mthca_cleanup_uar_table(mdev);
1da177e4 1223 mthca_close_hca(mdev);
80fd8238 1224 mthca_cmd_cleanup(mdev);
1da177e4
LT		 1225
1226 if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
1227 pci_disable_msix(pdev);
1da177e4
LT		 1228
1229 ib_dealloc_device(&mdev->ib_dev);
1230 mthca_release_regions(pdev, mdev->mthca_flags &
1231 MTHCA_FLAG_DDR_HIDDEN);
1232 pci_disable_device(pdev);
1233 pci_set_drvdata(pdev, NULL);
1234 }
1235}
1236
b3b30f5e
JM		 1237int __mthca_restart_one(struct pci_dev *pdev)
1238{
1239 struct mthca_dev *mdev;
de57c9f1 1240 int hca_type;
b3b30f5e
JM		 1241
1242 mdev = pci_get_drvdata(pdev);
1243 if (!mdev)
1244 return -ENODEV;
de57c9f1 1245 hca_type = mdev->hca_type;
b3b30f5e 1246 __mthca_remove_one(pdev);
de57c9f1 1247 return __mthca_init_one(pdev, hca_type);
b3b30f5e
JM		 1248}
1249
1250static int __devinit mthca_init_one(struct pci_dev *pdev,
f4f3d0f0 1251 const struct pci_device_id *id)
b3b30f5e
JM		 1252{
1253 static int mthca_version_printed = 0;
1254 int ret;
1255
1256 mutex_lock(&mthca_device_mutex);
1257
1258 if (!mthca_version_printed) {
1259 printk(KERN_INFO "%s", mthca_version);
1260 ++mthca_version_printed;
1261 }
1262
1263 if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
1264 printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
1265 pci_name(pdev), id->driver_data);
1266 mutex_unlock(&mthca_device_mutex);
1267 return -ENODEV;
1268 }
1269
1270 ret = __mthca_init_one(pdev, id->driver_data);
1271
1272 mutex_unlock(&mthca_device_mutex);
1273
1274 return ret;
1275}
1276
1277static void __devexit mthca_remove_one(struct pci_dev *pdev)
1278{
1279 mutex_lock(&mthca_device_mutex);
1280 __mthca_remove_one(pdev);
1281 mutex_unlock(&mthca_device_mutex);
1282}
1283
1da177e4
LT		 1284static struct pci_device_id mthca_pci_table[] = {
1285 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
1286 .driver_data = TAVOR },
1287 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
1288 .driver_data = TAVOR },
1289 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
1290 .driver_data = ARBEL_COMPAT },
1291 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
1292 .driver_data = ARBEL_COMPAT },
1293 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
1294 .driver_data = ARBEL_NATIVE },
1295 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
1296 .driver_data = ARBEL_NATIVE },
68a3c212
RD		 1297 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
1298 .driver_data = SINAI },
1299 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
1300 .driver_data = SINAI },
1301 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
1302 .driver_data = SINAI },
1303 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
1304 .driver_data = SINAI },
1da177e4
LT		 1305 { 0, }
1306};
1307
1308MODULE_DEVICE_TABLE(pci, mthca_pci_table);
1309
1310static struct pci_driver mthca_driver = {
177214af 1311 .name = DRV_NAME,
1da177e4
LT		 1312 .id_table = mthca_pci_table,
1313 .probe = mthca_init_one,
1314 .remove = __devexit_p(mthca_remove_one)
1315};
1316
82da703e
LA		 1317static void __init __mthca_check_profile_val(const char *name, int *pval,
1318 int pval_default)
1319{
1320 /* value must be positive and power of 2 */
1321 int old_pval = *pval;
1322
1323 if (old_pval <= 0)
1324 *pval = pval_default;
1325 else
1326 *pval = roundup_pow_of_two(old_pval);
1327
1328 if (old_pval != *pval) {
1329 printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
1330 old_pval, name);
1331 printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
1332 }
1333}
1334
1335#define mthca_check_profile_val(name, default) \
1336 __mthca_check_profile_val(#name, &hca_profile.name, default)
1337
1338static void __init mthca_validate_profile(void)
1339{
1340 mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
1341 mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
1342 mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
1343 mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
1344 mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
1345 mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
1346 mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
1347 mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
1348
1349 if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
1350 printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
1351 hca_profile.fmr_reserved_mtts);
1352 printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
1353 hca_profile.num_mtt);
1354 hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
1355 printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
1356 hca_profile.fmr_reserved_mtts);
1357 }
1358}
1359
1da177e4
LT		 1360static int __init mthca_init(void)
1361{
1362 int ret;
1363
82da703e
LA		 1364 mthca_validate_profile();
1365
b3b30f5e
JM		 1366 ret = mthca_catas_init();
1367 if (ret)
1368 return ret;
1369
1da177e4 1370 ret = pci_register_driver(&mthca_driver);
b3b30f5e
JM		 1371 if (ret < 0) {
1372 mthca_catas_cleanup();
1373 return ret;
1374 }
1375
1376 return 0;
1da177e4
LT		 1377}
1378
1379static void __exit mthca_cleanup(void)
1380{
1381 pci_unregister_driver(&mthca_driver);
b3b30f5e 1382 mthca_catas_cleanup();
1da177e4
LT		 1383}
1384
1385module_init(mthca_init);
1386module_exit(mthca_cleanup);
Linux 6.x block layer and io_uring tree(s)