RDMA/usnic: Silence uninitialized symbol smatch warnings
[linux-block.git] / drivers / infiniband / hw / mthca / mthca_main.c
CommitLineData
1da177e4
LT
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
2a1d9b7f 4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
1da177e4
LT
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
1da177e4
LT
33 */
34
1da177e4
LT
35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/interrupt.h>
5a0e3ad6 40#include <linux/gfp.h>
1da177e4
LT
41
42#include "mthca_dev.h"
43#include "mthca_config_reg.h"
44#include "mthca_cmd.h"
45#include "mthca_profile.h"
46#include "mthca_memfree.h"
12103dca 47#include "mthca_wqe.h"
1da177e4
LT
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
1da177e4 52
227c939b
RD
53#ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
54
55int mthca_debug_level = 0;
56module_param_named(debug_level, mthca_debug_level, int, 0644);
57MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
58
59#endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
60
1da177e4
LT
61#ifdef CONFIG_PCI_MSI
62
017aadc4 63static int msi_x = 1;
1da177e4
LT
64module_param(msi_x, int, 0444);
65MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
66
1da177e4
LT
67#else /* CONFIG_PCI_MSI */
68
69#define msi_x (0)
1da177e4
LT
70
71#endif /* CONFIG_PCI_MSI */
72
abf45dbb
MT
73static int tune_pci = 0;
74module_param(tune_pci, int, 0444);
75MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
76
0b0df6f2 77DEFINE_MUTEX(mthca_device_mutex);
b3b30f5e 78
82da703e
LA
79#define MTHCA_DEFAULT_NUM_QP (1 << 16)
80#define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
81#define MTHCA_DEFAULT_NUM_CQ (1 << 16)
82#define MTHCA_DEFAULT_NUM_MCG (1 << 13)
83#define MTHCA_DEFAULT_NUM_MPT (1 << 17)
84#define MTHCA_DEFAULT_NUM_MTT (1 << 20)
85#define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
86#define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
87#define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
88
89static struct mthca_profile hca_profile = {
90 .num_qp = MTHCA_DEFAULT_NUM_QP,
91 .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
92 .num_cq = MTHCA_DEFAULT_NUM_CQ,
93 .num_mcg = MTHCA_DEFAULT_NUM_MCG,
94 .num_mpt = MTHCA_DEFAULT_NUM_MPT,
95 .num_mtt = MTHCA_DEFAULT_NUM_MTT,
96 .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
97 .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
98 .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
99};
100
101module_param_named(num_qp, hca_profile.num_qp, int, 0444);
102MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
103
104module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
105MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
106
107module_param_named(num_cq, hca_profile.num_cq, int, 0444);
108MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
109
110module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
111MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
112
113module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
114MODULE_PARM_DESC(num_mpt,
115 "maximum number of memory protection table entries per HCA");
116
117module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
118MODULE_PARM_DESC(num_mtt,
119 "maximum number of memory translation table segments per HCA");
120
121module_param_named(num_udav, hca_profile.num_udav, int, 0444);
122MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
123
124module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
125MODULE_PARM_DESC(fmr_reserved_mtts,
126 "number of memory translation table segments reserved for FMR");
127
c1f67a88
EC
128static int log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
129module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
130MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)");
131
1e6d9abe 132static char mthca_version[] =
177214af 133 DRV_NAME ": Mellanox InfiniBand HCA driver v"
1da177e4
LT
134 DRV_VERSION " (" DRV_RELDATE ")\n";
135
f4f3d0f0 136static int mthca_tune_pci(struct mthca_dev *mdev)
1da177e4 137{
abf45dbb
MT
138 if (!tune_pci)
139 return 0;
140
1da177e4 141 /* First try to max out Read Byte Count */
a855b1a7
PO
142 if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
143 if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
144 mthca_err(mdev, "Couldn't set PCI-X max read count, "
145 "aborting.\n");
1da177e4
LT
146 return -ENODEV;
147 }
68a3c212 148 } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
1da177e4
LT
149 mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
150
9b89925c 151 if (pci_is_pcie(mdev->pdev)) {
a855b1a7
PO
152 if (pcie_set_readrq(mdev->pdev, 4096)) {
153 mthca_err(mdev, "Couldn't write PCI Express read request, "
154 "aborting.\n");
1da177e4
LT
155 return -ENODEV;
156 }
68a3c212 157 } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
1da177e4
LT
158 mthca_info(mdev, "No PCI Express capability, "
159 "not setting Max Read Request Size.\n");
160
161 return 0;
162}
163
f4f3d0f0 164static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
1da177e4
LT
165{
166 int err;
1da177e4 167
c1f67a88 168 mdev->limits.mtt_seg_size = (1 << log_mtts_per_seg) * 8;
cdb73db0 169 err = mthca_QUERY_DEV_LIM(mdev, dev_lim);
1da177e4 170 if (err) {
cdb73db0
GR
171 mthca_err(mdev, "QUERY_DEV_LIM command returned %d"
172 ", aborting.\n", err);
1da177e4
LT
173 return err;
174 }
1da177e4
LT
175 if (dev_lim->min_page_sz > PAGE_SIZE) {
176 mthca_err(mdev, "HCA minimum page size of %d bigger than "
177 "kernel PAGE_SIZE of %ld, aborting.\n",
178 dev_lim->min_page_sz, PAGE_SIZE);
179 return -ENODEV;
180 }
181 if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
182 mthca_err(mdev, "HCA has %d ports, but we only support %d, "
183 "aborting.\n",
184 dev_lim->num_ports, MTHCA_MAX_PORTS);
185 return -ENODEV;
186 }
187
cbd2981a
MT
188 if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
189 mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
e29419ff
GKH
190 "PCI resource 2 size of 0x%llx, aborting.\n",
191 dev_lim->uar_size,
192 (unsigned long long)pci_resource_len(mdev->pdev, 2));
cbd2981a
MT
193 return -ENODEV;
194 }
195
1da177e4
LT
196 mdev->limits.num_ports = dev_lim->num_ports;
197 mdev->limits.vl_cap = dev_lim->max_vl;
198 mdev->limits.mtu_cap = dev_lim->max_mtu;
199 mdev->limits.gid_table_len = dev_lim->max_gids;
200 mdev->limits.pkey_table_len = dev_lim->max_pkeys;
201 mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
12103dca
RD
202 /*
203 * Need to allow for worst case send WQE overhead and check
204 * whether max_desc_sz imposes a lower limit than max_sg; UD
205 * send has the biggest overhead.
206 */
207 mdev->limits.max_sg = min_t(int, dev_lim->max_sg,
208 (dev_lim->max_desc_sz -
209 sizeof (struct mthca_next_seg) -
210 (mthca_is_memfree(mdev) ?
211 sizeof (struct mthca_arbel_ud_seg) :
212 sizeof (struct mthca_tavor_ud_seg))) /
213 sizeof (struct mthca_data_seg));
efaae8f7
JM
214 mdev->limits.max_wqes = dev_lim->max_qp_sz;
215 mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
1da177e4 216 mdev->limits.reserved_qps = dev_lim->reserved_qps;
efaae8f7 217 mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
1da177e4
LT
218 mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
219 mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
77369ed3 220 mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
59fef3b1 221 mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
efaae8f7
JM
222 /*
223 * Subtract 1 from the limit because we need to allocate a
224 * spare CQE so the HCA HW can tell the difference between an
225 * empty CQ and a full CQ.
226 */
227 mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
1da177e4
LT
228 mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
229 mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
230 mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
231 mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
232 mdev->limits.reserved_uars = dev_lim->reserved_uars;
233 mdev->limits.reserved_pds = dev_lim->reserved_pds;
da6561c2 234 mdev->limits.port_width_cap = dev_lim->max_port_width;
0f69ce1e 235 mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
33033b79 236 mdev->limits.flags = dev_lim->flags;
bf6a9e31
JM
237 /*
238 * For old FW that doesn't return static rate support, use a
239 * value of 0x3 (only static rate values of 0 or 1 are handled),
240 * except on Sinai, where even old FW can handle static rate
241 * values of 2 and 3.
242 */
243 if (dev_lim->stat_rate_support)
244 mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
245 else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
246 mdev->limits.stat_rate_support = 0xf;
247 else
248 mdev->limits.stat_rate_support = 0x3;
1da177e4
LT
249
250 /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
251 May be doable since hardware supports it for SRQ.
252
253 IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
254
255 IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
256 supported by driver. */
257 mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
258 IB_DEVICE_PORT_ACTIVE_EVENT |
259 IB_DEVICE_SYS_IMAGE_GUID |
260 IB_DEVICE_RC_RNR_NAK_GEN;
261
262 if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
263 mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
264
265 if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
266 mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
267
268 if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
269 mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
270
271 if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
272 mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
273
274 if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
275 mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
276
277 if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
278 mdev->mthca_flags |= MTHCA_FLAG_SRQ;
279
680b575f
EC
280 if (mthca_is_memfree(mdev))
281 if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
282 mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
283
1da177e4
LT
284 return 0;
285}
286
f4f3d0f0 287static int mthca_init_tavor(struct mthca_dev *mdev)
1da177e4 288{
19773539 289 s64 size;
1da177e4
LT
290 int err;
291 struct mthca_dev_lim dev_lim;
292 struct mthca_profile profile;
293 struct mthca_init_hca_param init_hca;
1da177e4 294
cdb73db0 295 err = mthca_SYS_EN(mdev);
1da177e4 296 if (err) {
cdb73db0 297 mthca_err(mdev, "SYS_EN command returned %d, aborting.\n", err);
1da177e4
LT
298 return err;
299 }
1da177e4 300
cdb73db0 301 err = mthca_QUERY_FW(mdev);
1da177e4 302 if (err) {
cdb73db0
GR
303 mthca_err(mdev, "QUERY_FW command returned %d,"
304 " aborting.\n", err);
1da177e4
LT
305 goto err_disable;
306 }
cdb73db0 307 err = mthca_QUERY_DDR(mdev);
1da177e4 308 if (err) {
cdb73db0 309 mthca_err(mdev, "QUERY_DDR command returned %d, aborting.\n", err);
1da177e4
LT
310 goto err_disable;
311 }
312
313 err = mthca_dev_lim(mdev, &dev_lim);
aa2f9367 314 if (err) {
cdb73db0 315 mthca_err(mdev, "QUERY_DEV_LIM command returned %d, aborting.\n", err);
aa2f9367
JM
316 goto err_disable;
317 }
1da177e4 318
82da703e 319 profile = hca_profile;
1da177e4
LT
320 profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
321 profile.uarc_size = 0;
ec34a922
RD
322 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
323 profile.num_srq = dev_lim.max_srqs;
1da177e4 324
19773539
RD
325 size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
326 if (size < 0) {
327 err = size;
1da177e4 328 goto err_disable;
19773539 329 }
1da177e4 330
cdb73db0 331 err = mthca_INIT_HCA(mdev, &init_hca);
1da177e4 332 if (err) {
cdb73db0 333 mthca_err(mdev, "INIT_HCA command returned %d, aborting.\n", err);
1da177e4
LT
334 goto err_disable;
335 }
336
1da177e4
LT
337 return 0;
338
1da177e4 339err_disable:
cdb73db0 340 mthca_SYS_DIS(mdev);
1da177e4
LT
341
342 return err;
343}
344
f4f3d0f0 345static int mthca_load_fw(struct mthca_dev *mdev)
1da177e4 346{
1da177e4
LT
347 int err;
348
349 /* FIXME: use HCA-attached memory for FW if present */
350
351 mdev->fw.arbel.fw_icm =
352 mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
391e4dea 353 GFP_HIGHUSER | __GFP_NOWARN, 0);
1da177e4
LT
354 if (!mdev->fw.arbel.fw_icm) {
355 mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
356 return -ENOMEM;
357 }
358
cdb73db0 359 err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm);
1da177e4 360 if (err) {
cdb73db0 361 mthca_err(mdev, "MAP_FA command returned %d, aborting.\n", err);
1da177e4
LT
362 goto err_free;
363 }
cdb73db0 364 err = mthca_RUN_FW(mdev);
1da177e4 365 if (err) {
cdb73db0 366 mthca_err(mdev, "RUN_FW command returned %d, aborting.\n", err);
1da177e4
LT
367 goto err_unmap_fa;
368 }
369
370 return 0;
371
372err_unmap_fa:
cdb73db0 373 mthca_UNMAP_FA(mdev);
1da177e4
LT
374
375err_free:
391e4dea 376 mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
1da177e4
LT
377 return err;
378}
379
f4f3d0f0
RD
380static int mthca_init_icm(struct mthca_dev *mdev,
381 struct mthca_dev_lim *dev_lim,
382 struct mthca_init_hca_param *init_hca,
383 u64 icm_size)
1da177e4 384{
b9a85e5e 385 u64 aux_pages = 0;
1da177e4
LT
386 int err;
387
cdb73db0 388 err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages);
1da177e4 389 if (err) {
cdb73db0 390 mthca_err(mdev, "SET_ICM_SIZE command returned %d, aborting.\n", err);
1da177e4
LT
391 return err;
392 }
1da177e4
LT
393
394 mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
395 (unsigned long long) icm_size >> 10,
396 (unsigned long long) aux_pages << 2);
397
398 mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
391e4dea 399 GFP_HIGHUSER | __GFP_NOWARN, 0);
1da177e4
LT
400 if (!mdev->fw.arbel.aux_icm) {
401 mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
402 return -ENOMEM;
403 }
404
cdb73db0 405 err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm);
1da177e4 406 if (err) {
cdb73db0 407 mthca_err(mdev, "MAP_ICM_AUX returned %d, aborting.\n", err);
1da177e4
LT
408 goto err_free_aux;
409 }
410
411 err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
412 if (err) {
413 mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
414 goto err_unmap_aux;
415 }
416
1d1f19cf 417 /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
c1f67a88
EC
418 mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * mdev->limits.mtt_seg_size,
419 dma_get_cache_alignment()) / mdev->limits.mtt_seg_size;
1d1f19cf 420
1da177e4 421 mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
c1f67a88 422 mdev->limits.mtt_seg_size,
1da177e4 423 mdev->limits.num_mtt_segs,
391e4dea
MT
424 mdev->limits.reserved_mtts,
425 1, 0);
1da177e4
LT
426 if (!mdev->mr_table.mtt_table) {
427 mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
428 err = -ENOMEM;
429 goto err_unmap_eq;
430 }
431
432 mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
433 dev_lim->mpt_entry_sz,
434 mdev->limits.num_mpts,
391e4dea
MT
435 mdev->limits.reserved_mrws,
436 1, 1);
1da177e4
LT
437 if (!mdev->mr_table.mpt_table) {
438 mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
439 err = -ENOMEM;
440 goto err_unmap_mtt;
441 }
442
443 mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
444 dev_lim->qpc_entry_sz,
445 mdev->limits.num_qps,
391e4dea
MT
446 mdev->limits.reserved_qps,
447 0, 0);
1da177e4
LT
448 if (!mdev->qp_table.qp_table) {
449 mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
450 err = -ENOMEM;
451 goto err_unmap_mpt;
452 }
453
454 mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
455 dev_lim->eqpc_entry_sz,
456 mdev->limits.num_qps,
391e4dea
MT
457 mdev->limits.reserved_qps,
458 0, 0);
1da177e4
LT
459 if (!mdev->qp_table.eqp_table) {
460 mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
461 err = -ENOMEM;
462 goto err_unmap_qp;
463 }
464
08aeb14e
RD
465 mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
466 MTHCA_RDB_ENTRY_SIZE,
467 mdev->limits.num_qps <<
391e4dea 468 mdev->qp_table.rdb_shift, 0,
08aeb14e
RD
469 0, 0);
470 if (!mdev->qp_table.rdb_table) {
471 mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
472 err = -ENOMEM;
19272d43 473 goto err_unmap_eqp;
08aeb14e
RD
474 }
475
8a53f41b
BVA
476 mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
477 dev_lim->cqc_entry_sz,
478 mdev->limits.num_cqs,
479 mdev->limits.reserved_cqs,
480 0, 0);
1da177e4
LT
481 if (!mdev->cq_table.table) {
482 mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
483 err = -ENOMEM;
08aeb14e 484 goto err_unmap_rdb;
1da177e4
LT
485 }
486
ec34a922
RD
487 if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
488 mdev->srq_table.table =
489 mthca_alloc_icm_table(mdev, init_hca->srqc_base,
490 dev_lim->srq_entry_sz,
491 mdev->limits.num_srqs,
391e4dea
MT
492 mdev->limits.reserved_srqs,
493 0, 0);
ec34a922
RD
494 if (!mdev->srq_table.table) {
495 mthca_err(mdev, "Failed to map SRQ context memory, "
496 "aborting.\n");
497 err = -ENOMEM;
498 goto err_unmap_cq;
499 }
500 }
501
1da177e4
LT
502 /*
503 * It's not strictly required, but for simplicity just map the
504 * whole multicast group table now. The table isn't very big
505 * and it's a lot easier than trying to track ref counts.
506 */
507 mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
508 MTHCA_MGM_ENTRY_SIZE,
509 mdev->limits.num_mgms +
510 mdev->limits.num_amgms,
511 mdev->limits.num_mgms +
512 mdev->limits.num_amgms,
391e4dea 513 0, 0);
1da177e4
LT
514 if (!mdev->mcg_table.table) {
515 mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
516 err = -ENOMEM;
ec34a922 517 goto err_unmap_srq;
1da177e4
LT
518 }
519
520 return 0;
521
ec34a922
RD
522err_unmap_srq:
523 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
524 mthca_free_icm_table(mdev, mdev->srq_table.table);
525
1da177e4
LT
526err_unmap_cq:
527 mthca_free_icm_table(mdev, mdev->cq_table.table);
528
08aeb14e
RD
529err_unmap_rdb:
530 mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
531
1da177e4
LT
532err_unmap_eqp:
533 mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
534
535err_unmap_qp:
536 mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
537
538err_unmap_mpt:
539 mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
540
541err_unmap_mtt:
542 mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
543
544err_unmap_eq:
545 mthca_unmap_eq_icm(mdev);
546
547err_unmap_aux:
cdb73db0 548 mthca_UNMAP_ICM_AUX(mdev);
1da177e4
LT
549
550err_free_aux:
391e4dea 551 mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
1da177e4
LT
552
553 return err;
554}
555
aba7a22f
MT
556static void mthca_free_icms(struct mthca_dev *mdev)
557{
aba7a22f
MT
558
559 mthca_free_icm_table(mdev, mdev->mcg_table.table);
560 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
561 mthca_free_icm_table(mdev, mdev->srq_table.table);
562 mthca_free_icm_table(mdev, mdev->cq_table.table);
563 mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
564 mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
565 mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
566 mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
567 mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
568 mthca_unmap_eq_icm(mdev);
569
cdb73db0 570 mthca_UNMAP_ICM_AUX(mdev);
391e4dea 571 mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
aba7a22f
MT
572}
573
f4f3d0f0 574static int mthca_init_arbel(struct mthca_dev *mdev)
1da177e4
LT
575{
576 struct mthca_dev_lim dev_lim;
577 struct mthca_profile profile;
578 struct mthca_init_hca_param init_hca;
19773539 579 s64 icm_size;
1da177e4
LT
580 int err;
581
cdb73db0 582 err = mthca_QUERY_FW(mdev);
1da177e4 583 if (err) {
cdb73db0 584 mthca_err(mdev, "QUERY_FW command failed %d, aborting.\n", err);
1da177e4
LT
585 return err;
586 }
1da177e4 587
cdb73db0
GR
588 err = mthca_ENABLE_LAM(mdev);
589 if (err == -EAGAIN) {
1da177e4
LT
590 mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
591 mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
cdb73db0
GR
592 } else if (err) {
593 mthca_err(mdev, "ENABLE_LAM returned %d, aborting.\n", err);
594 return err;
1da177e4
LT
595 }
596
597 err = mthca_load_fw(mdev);
598 if (err) {
cdb73db0 599 mthca_err(mdev, "Loading FW returned %d, aborting.\n", err);
1da177e4
LT
600 goto err_disable;
601 }
602
603 err = mthca_dev_lim(mdev, &dev_lim);
604 if (err) {
cdb73db0 605 mthca_err(mdev, "QUERY_DEV_LIM returned %d, aborting.\n", err);
1da177e4
LT
606 goto err_stop_fw;
607 }
608
82da703e 609 profile = hca_profile;
1da177e4
LT
610 profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
611 profile.num_udav = 0;
ec34a922
RD
612 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
613 profile.num_srq = dev_lim.max_srqs;
1da177e4
LT
614
615 icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
19773539 616 if (icm_size < 0) {
1da177e4
LT
617 err = icm_size;
618 goto err_stop_fw;
619 }
620
621 err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
622 if (err)
623 goto err_stop_fw;
624
cdb73db0 625 err = mthca_INIT_HCA(mdev, &init_hca);
1da177e4 626 if (err) {
cdb73db0 627 mthca_err(mdev, "INIT_HCA command returned %d, aborting.\n", err);
1da177e4
LT
628 goto err_free_icm;
629 }
630
1da177e4
LT
631 return 0;
632
633err_free_icm:
aba7a22f 634 mthca_free_icms(mdev);
1da177e4
LT
635
636err_stop_fw:
cdb73db0 637 mthca_UNMAP_FA(mdev);
391e4dea 638 mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
1da177e4
LT
639
640err_disable:
641 if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
cdb73db0 642 mthca_DISABLE_LAM(mdev);
1da177e4
LT
643
644 return err;
645}
646
2e8b981c
MT
647static void mthca_close_hca(struct mthca_dev *mdev)
648{
cdb73db0 649 mthca_CLOSE_HCA(mdev, 0);
2e8b981c
MT
650
651 if (mthca_is_memfree(mdev)) {
aba7a22f 652 mthca_free_icms(mdev);
2e8b981c 653
cdb73db0 654 mthca_UNMAP_FA(mdev);
391e4dea 655 mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
2e8b981c
MT
656
657 if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
cdb73db0 658 mthca_DISABLE_LAM(mdev);
2e8b981c 659 } else
cdb73db0 660 mthca_SYS_DIS(mdev);
2e8b981c
MT
661}
662
f4f3d0f0 663static int mthca_init_hca(struct mthca_dev *mdev)
1da177e4 664{
2e8b981c
MT
665 int err;
666 struct mthca_adapter adapter;
667
d10ddbf6 668 if (mthca_is_memfree(mdev))
2e8b981c 669 err = mthca_init_arbel(mdev);
1da177e4 670 else
2e8b981c
MT
671 err = mthca_init_tavor(mdev);
672
673 if (err)
674 return err;
675
cdb73db0 676 err = mthca_QUERY_ADAPTER(mdev, &adapter);
2e8b981c 677 if (err) {
cdb73db0 678 mthca_err(mdev, "QUERY_ADAPTER command returned %d, aborting.\n", err);
2e8b981c
MT
679 goto err_close;
680 }
681
682 mdev->eq_table.inta_pin = adapter.inta_pin;
6ccef1de
JM
683 if (!mthca_is_memfree(mdev))
684 mdev->rev_id = adapter.revision_id;
2e8b981c
MT
685 memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
686
687 return 0;
688
689err_close:
690 mthca_close_hca(mdev);
691 return err;
1da177e4
LT
692}
693
f4f3d0f0 694static int mthca_setup_hca(struct mthca_dev *dev)
1da177e4
LT
695{
696 int err;
1da177e4
LT
697
698 MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
699
700 err = mthca_init_uar_table(dev);
701 if (err) {
702 mthca_err(dev, "Failed to initialize "
703 "user access region table, aborting.\n");
704 return err;
705 }
706
707 err = mthca_uar_alloc(dev, &dev->driver_uar);
708 if (err) {
709 mthca_err(dev, "Failed to allocate driver access region, "
710 "aborting.\n");
711 goto err_uar_table_free;
712 }
713
eb4a7cbf 714 dev->kar = ioremap((phys_addr_t) dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1da177e4
LT
715 if (!dev->kar) {
716 mthca_err(dev, "Couldn't map kernel access region, "
717 "aborting.\n");
718 err = -ENOMEM;
719 goto err_uar_free;
720 }
721
722 err = mthca_init_pd_table(dev);
723 if (err) {
724 mthca_err(dev, "Failed to initialize "
725 "protection domain table, aborting.\n");
726 goto err_kar_unmap;
727 }
728
729 err = mthca_init_mr_table(dev);
730 if (err) {
731 mthca_err(dev, "Failed to initialize "
732 "memory region table, aborting.\n");
733 goto err_pd_table_free;
734 }
735
99264c1e 736 err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
1da177e4
LT
737 if (err) {
738 mthca_err(dev, "Failed to create driver PD, "
739 "aborting.\n");
740 goto err_mr_table_free;
741 }
742
743 err = mthca_init_eq_table(dev);
744 if (err) {
745 mthca_err(dev, "Failed to initialize "
746 "event queue table, aborting.\n");
747 goto err_pd_free;
748 }
749
750 err = mthca_cmd_use_events(dev);
751 if (err) {
752 mthca_err(dev, "Failed to switch to event-driven "
753 "firmware commands, aborting.\n");
754 goto err_eq_table_free;
755 }
756
cdb73db0
GR
757 err = mthca_NOP(dev);
758 if (err) {
e57895d3 759 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
017aadc4
MT
760 mthca_warn(dev, "NOP command failed to generate interrupt "
761 "(IRQ %d).\n",
e57895d3
AB
762 dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
763 mthca_warn(dev, "Trying again with MSI-X disabled.\n");
017aadc4
MT
764 } else {
765 mthca_err(dev, "NOP command failed to generate interrupt "
766 "(IRQ %d), aborting.\n",
767 dev->pdev->irq);
1da177e4 768 mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
017aadc4 769 }
1da177e4
LT
770
771 goto err_cmd_poll;
772 }
773
774 mthca_dbg(dev, "NOP command IRQ test passed\n");
775
776 err = mthca_init_cq_table(dev);
777 if (err) {
778 mthca_err(dev, "Failed to initialize "
779 "completion queue table, aborting.\n");
780 goto err_cmd_poll;
781 }
782
ec34a922
RD
783 err = mthca_init_srq_table(dev);
784 if (err) {
785 mthca_err(dev, "Failed to initialize "
786 "shared receive queue table, aborting.\n");
787 goto err_cq_table_free;
788 }
789
1da177e4
LT
790 err = mthca_init_qp_table(dev);
791 if (err) {
792 mthca_err(dev, "Failed to initialize "
793 "queue pair table, aborting.\n");
ec34a922 794 goto err_srq_table_free;
1da177e4
LT
795 }
796
797 err = mthca_init_av_table(dev);
798 if (err) {
799 mthca_err(dev, "Failed to initialize "
800 "address vector table, aborting.\n");
801 goto err_qp_table_free;
802 }
803
804 err = mthca_init_mcg_table(dev);
805 if (err) {
806 mthca_err(dev, "Failed to initialize "
807 "multicast group table, aborting.\n");
808 goto err_av_table_free;
809 }
810
811 return 0;
812
813err_av_table_free:
814 mthca_cleanup_av_table(dev);
815
816err_qp_table_free:
817 mthca_cleanup_qp_table(dev);
818
ec34a922
RD
819err_srq_table_free:
820 mthca_cleanup_srq_table(dev);
821
1da177e4
LT
822err_cq_table_free:
823 mthca_cleanup_cq_table(dev);
824
825err_cmd_poll:
826 mthca_cmd_use_polling(dev);
827
828err_eq_table_free:
829 mthca_cleanup_eq_table(dev);
830
831err_pd_free:
832 mthca_pd_free(dev, &dev->driver_pd);
833
834err_mr_table_free:
835 mthca_cleanup_mr_table(dev);
836
837err_pd_table_free:
838 mthca_cleanup_pd_table(dev);
839
840err_kar_unmap:
841 iounmap(dev->kar);
842
843err_uar_free:
844 mthca_uar_free(dev, &dev->driver_uar);
845
846err_uar_table_free:
847 mthca_cleanup_uar_table(dev);
848 return err;
849}
850
f4f3d0f0 851static int mthca_enable_msi_x(struct mthca_dev *mdev)
1da177e4 852{
1da177e4
LT
853 int err;
854
f50cccdd
CH
855 err = pci_alloc_irq_vectors(mdev->pdev, 3, 3, PCI_IRQ_MSIX);
856 if (err < 0)
1da177e4 857 return err;
1da177e4 858
f50cccdd
CH
859 mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector =
860 pci_irq_vector(mdev->pdev, 0);
861 mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector =
862 pci_irq_vector(mdev->pdev, 1);
863 mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector =
864 pci_irq_vector(mdev->pdev, 2);
1da177e4
LT
865
866 return 0;
867}
868
68a3c212
RD
869/* Types of supported HCA */
870enum {
871 TAVOR, /* MT23108 */
872 ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
873 ARBEL_NATIVE, /* MT25208 with extended features */
874 SINAI /* MT25204 */
875};
876
877#define MTHCA_FW_VER(major, minor, subminor) \
878 (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
879
880static struct {
881 u64 latest_fw;
651eaac9 882 u32 flags;
68a3c212 883} mthca_hca_table[] = {
3f114853 884 [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
651eaac9 885 .flags = 0 },
3f114853 886 [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
651eaac9 887 .flags = MTHCA_FLAG_PCIE },
950529e5 888 [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
651eaac9
EC
889 .flags = MTHCA_FLAG_MEMFREE |
890 MTHCA_FLAG_PCIE },
3f114853 891 [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
651eaac9
EC
892 .flags = MTHCA_FLAG_MEMFREE |
893 MTHCA_FLAG_PCIE |
894 MTHCA_FLAG_SINAI_OPT }
68a3c212
RD
895};
896
b3b30f5e 897static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
1da177e4 898{
1da177e4
LT
899 int ddr_hidden = 0;
900 int err;
901 struct mthca_dev *mdev;
902
982245f0
AB
903 printk(KERN_INFO PFX "Initializing %s\n",
904 pci_name(pdev));
1da177e4
LT
905
906 err = pci_enable_device(pdev);
907 if (err) {
908 dev_err(&pdev->dev, "Cannot enable PCI device, "
909 "aborting.\n");
910 return err;
911 }
912
913 /*
914 * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
915 * be present)
916 */
917 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
918 pci_resource_len(pdev, 0) != 1 << 20) {
177214af 919 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1da177e4
LT
920 err = -ENODEV;
921 goto err_disable_pdev;
922 }
cbd2981a 923 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
177214af 924 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1da177e4
LT
925 err = -ENODEV;
926 goto err_disable_pdev;
927 }
928 if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
929 ddr_hidden = 1;
930
208dde28 931 err = pci_request_regions(pdev, DRV_NAME);
1da177e4
LT
932 if (err) {
933 dev_err(&pdev->dev, "Cannot obtain PCI resources, "
934 "aborting.\n");
935 goto err_disable_pdev;
936 }
937
938 pci_set_master(pdev);
939
3f69f4e0 940 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1da177e4 941 if (err) {
667da76b
CJ
942 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
943 goto err_free_res;
1da177e4
LT
944 }
945
7f9e5c48
DD
946 /* We can handle large RDMA requests, so allow larger segments. */
947 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
948
459cc69f 949 mdev = ib_alloc_device(mthca_dev, ib_dev);
1da177e4
LT
950 if (!mdev) {
951 dev_err(&pdev->dev, "Device struct alloc failed, "
952 "aborting.\n");
953 err = -ENOMEM;
954 goto err_free_res;
955 }
956
68a3c212 957 mdev->pdev = pdev;
1da177e4 958
b3b30f5e 959 mdev->mthca_flags = mthca_hca_table[hca_type].flags;
1da177e4
LT
960 if (ddr_hidden)
961 mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
962
963 /*
964 * Now reset the HCA before we touch the PCI capabilities or
965 * attempt a firmware command, since a boot ROM may have left
966 * the HCA in an undefined state.
967 */
968 err = mthca_reset(mdev);
969 if (err) {
970 mthca_err(mdev, "Failed to reset HCA, aborting.\n");
971 goto err_free_dev;
972 }
973
39f24956
WY
974 err = mthca_cmd_init(mdev);
975 if (err) {
80fd8238 976 mthca_err(mdev, "Failed to init command interface, aborting.\n");
1da177e4
LT
977 goto err_free_dev;
978 }
979
980 err = mthca_tune_pci(mdev);
981 if (err)
80fd8238 982 goto err_cmd;
1da177e4
LT
983
984 err = mthca_init_hca(mdev);
985 if (err)
80fd8238 986 goto err_cmd;
1da177e4 987
b3b30f5e 988 if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
e4daf738 989 mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
68a3c212
RD
990 (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
991 (int) (mdev->fw_ver & 0xffff),
b3b30f5e
JM
992 (int) (mthca_hca_table[hca_type].latest_fw >> 32),
993 (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
994 (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
68a3c212
RD
995 mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
996 }
997
017aadc4
MT
998 if (msi_x && !mthca_enable_msi_x(mdev))
999 mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
017aadc4 1000
1da177e4 1001 err = mthca_setup_hca(mdev);
e57895d3 1002 if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
6e68c899 1003 pci_free_irq_vectors(pdev);
e57895d3 1004 mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
017aadc4
MT
1005
1006 err = mthca_setup_hca(mdev);
1007 }
1008
1da177e4
LT
1009 if (err)
1010 goto err_close;
1011
1012 err = mthca_register_device(mdev);
1013 if (err)
1014 goto err_cleanup;
1015
1016 err = mthca_create_agents(mdev);
1017 if (err)
1018 goto err_unregister;
1019
1020 pci_set_drvdata(pdev, mdev);
b3b30f5e 1021 mdev->hca_type = hca_type;
1da177e4 1022
d8410647
JM
1023 mdev->active = true;
1024
1da177e4
LT
1025 return 0;
1026
1027err_unregister:
1028 mthca_unregister_device(mdev);
1029
1030err_cleanup:
1031 mthca_cleanup_mcg_table(mdev);
1032 mthca_cleanup_av_table(mdev);
1033 mthca_cleanup_qp_table(mdev);
ec34a922 1034 mthca_cleanup_srq_table(mdev);
1da177e4
LT
1035 mthca_cleanup_cq_table(mdev);
1036 mthca_cmd_use_polling(mdev);
1037 mthca_cleanup_eq_table(mdev);
1038
1039 mthca_pd_free(mdev, &mdev->driver_pd);
1040
1041 mthca_cleanup_mr_table(mdev);
1042 mthca_cleanup_pd_table(mdev);
1043 mthca_cleanup_uar_table(mdev);
1044
1045err_close:
017aadc4 1046 if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
f50cccdd 1047 pci_free_irq_vectors(pdev);
017aadc4 1048
1da177e4
LT
1049 mthca_close_hca(mdev);
1050
80fd8238
RD
1051err_cmd:
1052 mthca_cmd_cleanup(mdev);
1da177e4
LT
1053
1054err_free_dev:
1da177e4
LT
1055 ib_dealloc_device(&mdev->ib_dev);
1056
1057err_free_res:
208dde28 1058 pci_release_regions(pdev);
1da177e4
LT
1059
1060err_disable_pdev:
1061 pci_disable_device(pdev);
1062 pci_set_drvdata(pdev, NULL);
1063 return err;
1064}
1065
b3b30f5e 1066static void __mthca_remove_one(struct pci_dev *pdev)
1da177e4
LT
1067{
1068 struct mthca_dev *mdev = pci_get_drvdata(pdev);
1da177e4
LT
1069 int p;
1070
1071 if (mdev) {
1072 mthca_free_agents(mdev);
1073 mthca_unregister_device(mdev);
1074
1075 for (p = 1; p <= mdev->limits.num_ports; ++p)
cdb73db0 1076 mthca_CLOSE_IB(mdev, p);
1da177e4
LT
1077
1078 mthca_cleanup_mcg_table(mdev);
1079 mthca_cleanup_av_table(mdev);
1080 mthca_cleanup_qp_table(mdev);
ec34a922 1081 mthca_cleanup_srq_table(mdev);
1da177e4
LT
1082 mthca_cleanup_cq_table(mdev);
1083 mthca_cmd_use_polling(mdev);
1084 mthca_cleanup_eq_table(mdev);
1085
1086 mthca_pd_free(mdev, &mdev->driver_pd);
1087
1088 mthca_cleanup_mr_table(mdev);
1089 mthca_cleanup_pd_table(mdev);
1090
1091 iounmap(mdev->kar);
1092 mthca_uar_free(mdev, &mdev->driver_uar);
1093 mthca_cleanup_uar_table(mdev);
1da177e4 1094 mthca_close_hca(mdev);
80fd8238 1095 mthca_cmd_cleanup(mdev);
1da177e4
LT
1096
1097 if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
f50cccdd 1098 pci_free_irq_vectors(pdev);
1da177e4
LT
1099
1100 ib_dealloc_device(&mdev->ib_dev);
208dde28 1101 pci_release_regions(pdev);
1da177e4
LT
1102 pci_disable_device(pdev);
1103 pci_set_drvdata(pdev, NULL);
1104 }
1105}
1106
b3b30f5e
JM
1107int __mthca_restart_one(struct pci_dev *pdev)
1108{
1109 struct mthca_dev *mdev;
de57c9f1 1110 int hca_type;
b3b30f5e
JM
1111
1112 mdev = pci_get_drvdata(pdev);
1113 if (!mdev)
1114 return -ENODEV;
de57c9f1 1115 hca_type = mdev->hca_type;
b3b30f5e 1116 __mthca_remove_one(pdev);
de57c9f1 1117 return __mthca_init_one(pdev, hca_type);
b3b30f5e
JM
1118}
1119
1e6d9abe 1120static int mthca_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
b3b30f5e 1121{
b3b30f5e
JM
1122 int ret;
1123
1124 mutex_lock(&mthca_device_mutex);
1125
f1aa78b2 1126 printk_once(KERN_INFO "%s", mthca_version);
b3b30f5e
JM
1127
1128 if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
1129 printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
1130 pci_name(pdev), id->driver_data);
1131 mutex_unlock(&mthca_device_mutex);
1132 return -ENODEV;
1133 }
1134
1135 ret = __mthca_init_one(pdev, id->driver_data);
1136
1137 mutex_unlock(&mthca_device_mutex);
1138
1139 return ret;
1140}
1141
1e6d9abe 1142static void mthca_remove_one(struct pci_dev *pdev)
b3b30f5e
JM
1143{
1144 mutex_lock(&mthca_device_mutex);
1145 __mthca_remove_one(pdev);
1146 mutex_unlock(&mthca_device_mutex);
1147}
1148
e0604df1 1149static const struct pci_device_id mthca_pci_table[] = {
1da177e4
LT
1150 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
1151 .driver_data = TAVOR },
1152 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
1153 .driver_data = TAVOR },
1154 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
1155 .driver_data = ARBEL_COMPAT },
1156 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
1157 .driver_data = ARBEL_COMPAT },
1158 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
1159 .driver_data = ARBEL_NATIVE },
1160 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
1161 .driver_data = ARBEL_NATIVE },
68a3c212
RD
1162 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
1163 .driver_data = SINAI },
1164 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
1165 .driver_data = SINAI },
1166 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
1167 .driver_data = SINAI },
1168 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
1169 .driver_data = SINAI },
1da177e4
LT
1170 { 0, }
1171};
1172
1173MODULE_DEVICE_TABLE(pci, mthca_pci_table);
1174
1175static struct pci_driver mthca_driver = {
177214af 1176 .name = DRV_NAME,
1da177e4
LT
1177 .id_table = mthca_pci_table,
1178 .probe = mthca_init_one,
1e6d9abe 1179 .remove = mthca_remove_one,
1da177e4
LT
1180};
1181
82da703e
LA
1182static void __init __mthca_check_profile_val(const char *name, int *pval,
1183 int pval_default)
1184{
1185 /* value must be positive and power of 2 */
1186 int old_pval = *pval;
1187
1188 if (old_pval <= 0)
1189 *pval = pval_default;
1190 else
1191 *pval = roundup_pow_of_two(old_pval);
1192
1193 if (old_pval != *pval) {
1194 printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
1195 old_pval, name);
1196 printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
1197 }
1198}
1199
1200#define mthca_check_profile_val(name, default) \
1201 __mthca_check_profile_val(#name, &hca_profile.name, default)
1202
1203static void __init mthca_validate_profile(void)
1204{
1205 mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
1206 mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
1207 mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
1208 mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
1209 mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
1210 mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
1211 mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
1212 mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
1213
1214 if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
1215 printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
1216 hca_profile.fmr_reserved_mtts);
1217 printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
1218 hca_profile.num_mtt);
1219 hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
1220 printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
1221 hca_profile.fmr_reserved_mtts);
1222 }
c1f67a88
EC
1223
1224 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) {
1225 printk(KERN_WARNING PFX "bad log_mtts_per_seg (%d). Using default - %d\n",
1226 log_mtts_per_seg, ilog2(MTHCA_MTT_SEG_SIZE / 8));
1227 log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
1228 }
82da703e
LA
1229}
1230
1da177e4
LT
1231static int __init mthca_init(void)
1232{
1233 int ret;
1234
82da703e
LA
1235 mthca_validate_profile();
1236
b3b30f5e
JM
1237 ret = mthca_catas_init();
1238 if (ret)
1239 return ret;
1240
1da177e4 1241 ret = pci_register_driver(&mthca_driver);
b3b30f5e
JM
1242 if (ret < 0) {
1243 mthca_catas_cleanup();
1244 return ret;
1245 }
1246
1247 return 0;
1da177e4
LT
1248}
1249
1250static void __exit mthca_cleanup(void)
1251{
1252 pci_unregister_driver(&mthca_driver);
b3b30f5e 1253 mthca_catas_cleanup();
1da177e4
LT
1254}
1255
1256module_init(mthca_init);
1257module_exit(mthca_cleanup);