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Merge branch 'rcu-v28-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-block.git] / drivers / infiniband / hw / mthca / mthca_eq.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
2a1d9b7f 3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
1da177e4
LT		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
1da177e4
LT		 32 */
33
1da177e4
LT		 34#include <linux/errno.h>
35#include <linux/interrupt.h>
36#include <linux/pci.h>
37
38#include "mthca_dev.h"
39#include "mthca_cmd.h"
40#include "mthca_config_reg.h"
41
42enum {
43 MTHCA_NUM_ASYNC_EQE = 0x80,
44 MTHCA_NUM_CMD_EQE = 0x80,
92898522 45 MTHCA_NUM_SPARE_EQE = 0x80,
1da177e4
LT		 46 MTHCA_EQ_ENTRY_SIZE = 0x20
47};
48
49/*
50 * Must be packed because start is 64 bits but only aligned to 32 bits.
51 */
52struct mthca_eq_context {
97f52eb4
SH		 53 __be32 flags;
54 __be64 start;
55 __be32 logsize_usrpage;
56 __be32 tavor_pd; /* reserved for Arbel */
57 u8 reserved1[3];
58 u8 intr;
59 __be32 arbel_pd; /* lost_count for Tavor */
60 __be32 lkey;
61 u32 reserved2[2];
62 __be32 consumer_index;
63 __be32 producer_index;
64 u32 reserved3[4];
1da177e4
LT		 65} __attribute__((packed));
66
67#define MTHCA_EQ_STATUS_OK ( 0 << 28)
68#define MTHCA_EQ_STATUS_OVERFLOW ( 9 << 28)
69#define MTHCA_EQ_STATUS_WRITE_FAIL (10 << 28)
70#define MTHCA_EQ_OWNER_SW ( 0 << 24)
71#define MTHCA_EQ_OWNER_HW ( 1 << 24)
72#define MTHCA_EQ_FLAG_TR ( 1 << 18)
73#define MTHCA_EQ_FLAG_OI ( 1 << 17)
74#define MTHCA_EQ_STATE_ARMED ( 1 << 8)
75#define MTHCA_EQ_STATE_FIRED ( 2 << 8)
76#define MTHCA_EQ_STATE_ALWAYS_ARMED ( 3 << 8)
77#define MTHCA_EQ_STATE_ARBEL ( 8 << 8)
78
79enum {
80 MTHCA_EVENT_TYPE_COMP = 0x00,
81 MTHCA_EVENT_TYPE_PATH_MIG = 0x01,
82 MTHCA_EVENT_TYPE_COMM_EST = 0x02,
83 MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03,
90f104da
RD		 84 MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
85 MTHCA_EVENT_TYPE_SRQ_LIMIT = 0x14,
1da177e4
LT		 86 MTHCA_EVENT_TYPE_CQ_ERROR = 0x04,
87 MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
88 MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
89 MTHCA_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
90 MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
91 MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
92 MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
93 MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
94 MTHCA_EVENT_TYPE_PORT_CHANGE = 0x09,
95 MTHCA_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
96 MTHCA_EVENT_TYPE_ECC_DETECT = 0x0e,
97 MTHCA_EVENT_TYPE_CMD = 0x0a
98};
99
100#define MTHCA_ASYNC_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_PATH_MIG) | \
101 (1ULL << MTHCA_EVENT_TYPE_COMM_EST) | \
102 (1ULL << MTHCA_EVENT_TYPE_SQ_DRAINED) | \
103 (1ULL << MTHCA_EVENT_TYPE_CQ_ERROR) | \
104 (1ULL << MTHCA_EVENT_TYPE_WQ_CATAS_ERROR) | \
105 (1ULL << MTHCA_EVENT_TYPE_EEC_CATAS_ERROR) | \
106 (1ULL << MTHCA_EVENT_TYPE_PATH_MIG_FAILED) | \
107 (1ULL << MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
108 (1ULL << MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR) | \
109 (1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \
110 (1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \
111 (1ULL << MTHCA_EVENT_TYPE_ECC_DETECT))
90f104da
RD		 112#define MTHCA_SRQ_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \
113 (1ULL << MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
114 (1ULL << MTHCA_EVENT_TYPE_SRQ_LIMIT))
1da177e4
LT		 115#define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD)
116
117#define MTHCA_EQ_DB_INC_CI (1 << 24)
118#define MTHCA_EQ_DB_REQ_NOT (2 << 24)
119#define MTHCA_EQ_DB_DISARM_CQ (3 << 24)
120#define MTHCA_EQ_DB_SET_CI (4 << 24)
121#define MTHCA_EQ_DB_ALWAYS_ARM (5 << 24)
122
123struct mthca_eqe {
124 u8 reserved1;
125 u8 type;
126 u8 reserved2;
127 u8 subtype;
128 union {
129 u32 raw[6];
130 struct {
97f52eb4 131 __be32 cqn;
1da177e4
LT		 132 } __attribute__((packed)) comp;
133 struct {
97f52eb4
SH		 134 u16 reserved1;
135 __be16 token;
136 u32 reserved2;
137 u8 reserved3[3];
138 u8 status;
139 __be64 out_param;
1da177e4
LT		 140 } __attribute__((packed)) cmd;
141 struct {
97f52eb4 142 __be32 qpn;
1da177e4 143 } __attribute__((packed)) qp;
90f104da
RD		 144 struct {
145 __be32 srqn;
146 } __attribute__((packed)) srq;
1da177e4 147 struct {
97f52eb4
SH		 148 __be32 cqn;
149 u32 reserved1;
150 u8 reserved2[3];
151 u8 syndrome;
1da177e4
LT		 152 } __attribute__((packed)) cq_err;
153 struct {
97f52eb4
SH		 154 u32 reserved1[2];
155 __be32 port;
1da177e4
LT		 156 } __attribute__((packed)) port_change;
157 } event;
158 u8 reserved3[3];
159 u8 owner;
160} __attribute__((packed));
161
162#define MTHCA_EQ_ENTRY_OWNER_SW (0 << 7)
163#define MTHCA_EQ_ENTRY_OWNER_HW (1 << 7)
164
165static inline u64 async_mask(struct mthca_dev *dev)
166{
167 return dev->mthca_flags & MTHCA_FLAG_SRQ ?
168 MTHCA_ASYNC_EVENT_MASK | MTHCA_SRQ_EVENT_MASK :
169 MTHCA_ASYNC_EVENT_MASK;
170}
171
172static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
173{
1da177e4
LT		 174 /*
175 * This barrier makes sure that all updates to ownership bits
176 * done by set_eqe_hw() hit memory before the consumer index
177 * is updated. set_eq_ci() allows the HCA to possibly write
178 * more EQ entries, and we want to avoid the exceedingly
179 * unlikely possibility of the HCA writing an entry and then
180 * having set_eqe_hw() overwrite the owner field.
181 */
182 wmb();
ab8403c4 183 mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1),
1da177e4
LT		 184 dev->kar + MTHCA_EQ_DOORBELL,
185 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
186}
187
188static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
189{
190 /* See comment in tavor_set_eq_ci() above. */
191 wmb();
97f52eb4
SH		 192 __raw_writel((__force u32) cpu_to_be32(ci),
193 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8);
1da177e4
LT		 194 /* We still want ordering, just not swabbing, so add a barrier */
195 mb();
196}
197
198static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
199{
d10ddbf6 200 if (mthca_is_memfree(dev))
1da177e4
LT		 201 arbel_set_eq_ci(dev, eq, ci);
202 else
203 tavor_set_eq_ci(dev, eq, ci);
204}
205
206static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn)
207{
ab8403c4 208 mthca_write64(MTHCA_EQ_DB_REQ_NOT | eqn, 0,
1da177e4
LT		 209 dev->kar + MTHCA_EQ_DOORBELL,
210 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
211}
212
213static inline void arbel_eq_req_not(struct mthca_dev *dev, u32 eqn_mask)
214{
215 writel(eqn_mask, dev->eq_regs.arbel.eq_arm);
216}
217
218static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn)
219{
d10ddbf6 220 if (!mthca_is_memfree(dev)) {
ab8403c4 221 mthca_write64(MTHCA_EQ_DB_DISARM_CQ | eqn, cqn,
1da177e4
LT		 222 dev->kar + MTHCA_EQ_DOORBELL,
223 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
224 }
225}
226
227static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry)
228{
229 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE;
230 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
231}
232
b3999393 233static inline struct mthca_eqe *next_eqe_sw(struct mthca_eq *eq)
1da177e4 234{
b3999393 235 struct mthca_eqe *eqe;
1da177e4
LT		 236 eqe = get_eqe(eq, eq->cons_index);
237 return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe;
238}
239
240static inline void set_eqe_hw(struct mthca_eqe *eqe)
241{
242 eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW;
243}
244
245static void port_change(struct mthca_dev *dev, int port, int active)
246{
247 struct ib_event record;
248
249 mthca_dbg(dev, "Port change to %s for port %d\n",
250 active ? "active" : "down", port);
251
252 record.device = &dev->ib_dev;
253 record.event = active ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
254 record.element.port_num = port;
255
256 ib_dispatch_event(&record);
257}
258
259static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq)
260{
261 struct mthca_eqe *eqe;
262 int disarm_cqn;
92898522
MT		 263 int eqes_found = 0;
264 int set_ci = 0;
1da177e4
LT		 265
266 while ((eqe = next_eqe_sw(eq))) {
1da177e4
LT		 267 /*
268 * Make sure we read EQ entry contents after we've
269 * checked the ownership bit.
270 */
271 rmb();
272
273 switch (eqe->type) {
274 case MTHCA_EVENT_TYPE_COMP:
275 disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
276 disarm_cq(dev, eq->eqn, disarm_cqn);
affcd505 277 mthca_cq_completion(dev, disarm_cqn);
1da177e4
LT		 278 break;
279
280 case MTHCA_EVENT_TYPE_PATH_MIG:
281 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
282 IB_EVENT_PATH_MIG);
283 break;
284
285 case MTHCA_EVENT_TYPE_COMM_EST:
286 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
287 IB_EVENT_COMM_EST);
288 break;
289
290 case MTHCA_EVENT_TYPE_SQ_DRAINED:
291 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
292 IB_EVENT_SQ_DRAINED);
293 break;
294
90f104da
RD		 295 case MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE:
296 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
297 IB_EVENT_QP_LAST_WQE_REACHED);
298 break;
299
300 case MTHCA_EVENT_TYPE_SRQ_LIMIT:
301 mthca_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
302 IB_EVENT_SRQ_LIMIT_REACHED);
303 break;
304
1da177e4
LT		 305 case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR:
306 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
307 IB_EVENT_QP_FATAL);
308 break;
309
310 case MTHCA_EVENT_TYPE_PATH_MIG_FAILED:
311 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
312 IB_EVENT_PATH_MIG_ERR);
313 break;
314
315 case MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
316 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
317 IB_EVENT_QP_REQ_ERR);
318 break;
319
320 case MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR:
321 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
322 IB_EVENT_QP_ACCESS_ERR);
323 break;
324
325 case MTHCA_EVENT_TYPE_CMD:
326 mthca_cmd_event(dev,
327 be16_to_cpu(eqe->event.cmd.token),
328 eqe->event.cmd.status,
329 be64_to_cpu(eqe->event.cmd.out_param));
1da177e4
LT		 330 break;
331
332 case MTHCA_EVENT_TYPE_PORT_CHANGE:
333 port_change(dev,
334 (be32_to_cpu(eqe->event.port_change.port) >> 28) & 3,
335 eqe->subtype == 0x4);
336 break;
337
338 case MTHCA_EVENT_TYPE_CQ_ERROR:
b87dcfba 339 mthca_warn(dev, "CQ %s on CQN %06x\n",
1da177e4
LT		 340 eqe->event.cq_err.syndrome == 1 ?
341 "overrun" : "access violation",
b87dcfba 342 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
affcd505
MT		 343 mthca_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
344 IB_EVENT_CQ_ERR);
1da177e4
LT		 345 break;
346
347 case MTHCA_EVENT_TYPE_EQ_OVERFLOW:
348 mthca_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
349 break;
350
351 case MTHCA_EVENT_TYPE_EEC_CATAS_ERROR:
352 case MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR:
353 case MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR:
354 case MTHCA_EVENT_TYPE_ECC_DETECT:
355 default:
356 mthca_warn(dev, "Unhandled event %02x(%02x) on EQ %d\n",
357 eqe->type, eqe->subtype, eq->eqn);
358 break;
359 };
360
361 set_eqe_hw(eqe);
362 ++eq->cons_index;
363 eqes_found = 1;
92898522 364 ++set_ci;
1da177e4 365
92898522
MT		 366 /*
367 * The HCA will think the queue has overflowed if we
368 * don't tell it we've been processing events. We
369 * create our EQs with MTHCA_NUM_SPARE_EQE extra
370 * entries, so we must update our consumer index at
371 * least that often.
372 */
373 if (unlikely(set_ci >= MTHCA_NUM_SPARE_EQE)) {
1da177e4
LT		 374 /*
375 * Conditional on hca_type is OK here because
376 * this is a rare case, not the fast path.
377 */
378 set_eq_ci(dev, eq, eq->cons_index);
379 set_ci = 0;
380 }
381 }
382
383 /*
384 * Rely on caller to set consumer index so that we don't have
385 * to test hca_type in our interrupt handling fast path.
386 */
387 return eqes_found;
388}
389
7d12e780 390static irqreturn_t mthca_tavor_interrupt(int irq, void *dev_ptr)
1da177e4
LT		 391{
392 struct mthca_dev *dev = dev_ptr;
393 u32 ecr;
394 int i;
395
396 if (dev->eq_table.clr_mask)
397 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
398
399 ecr = readl(dev->eq_regs.tavor.ecr_base + 4);
c8e0ca68
RD		 400 if (!ecr)
401 return IRQ_NONE;
1da177e4 402
c8e0ca68
RD		 403 writel(ecr, dev->eq_regs.tavor.ecr_base +
404 MTHCA_ECR_CLR_BASE - MTHCA_ECR_BASE + 4);
405
406 for (i = 0; i < MTHCA_NUM_EQ; ++i)
407 if (ecr & dev->eq_table.eq[i].eqn_mask) {
408 if (mthca_eq_int(dev, &dev->eq_table.eq[i]))
1da177e4
LT		 409 tavor_set_eq_ci(dev, &dev->eq_table.eq[i],
410 dev->eq_table.eq[i].cons_index);
c8e0ca68
RD		 411 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
412 }
1da177e4 413
c8e0ca68 414 return IRQ_HANDLED;
1da177e4
LT		 415}
416
7d12e780 417static irqreturn_t mthca_tavor_msi_x_interrupt(int irq, void *eq_ptr)
1da177e4
LT		 418{
419 struct mthca_eq *eq = eq_ptr;
420 struct mthca_dev *dev = eq->dev;
421
422 mthca_eq_int(dev, eq);
423 tavor_set_eq_ci(dev, eq, eq->cons_index);
424 tavor_eq_req_not(dev, eq->eqn);
425
426 /* MSI-X vectors always belong to us */
427 return IRQ_HANDLED;
428}
429
7d12e780 430static irqreturn_t mthca_arbel_interrupt(int irq, void *dev_ptr)
1da177e4
LT		 431{
432 struct mthca_dev *dev = dev_ptr;
433 int work = 0;
434 int i;
435
436 if (dev->eq_table.clr_mask)
437 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
438
439 for (i = 0; i < MTHCA_NUM_EQ; ++i)
440 if (mthca_eq_int(dev, &dev->eq_table.eq[i])) {
441 work = 1;
442 arbel_set_eq_ci(dev, &dev->eq_table.eq[i],
443 dev->eq_table.eq[i].cons_index);
444 }
445
446 arbel_eq_req_not(dev, dev->eq_table.arm_mask);
447
448 return IRQ_RETVAL(work);
449}
450
7d12e780 451static irqreturn_t mthca_arbel_msi_x_interrupt(int irq, void *eq_ptr)
1da177e4
LT		 452{
453 struct mthca_eq *eq = eq_ptr;
454 struct mthca_dev *dev = eq->dev;
455
456 mthca_eq_int(dev, eq);
457 arbel_set_eq_ci(dev, eq, eq->cons_index);
458 arbel_eq_req_not(dev, eq->eqn_mask);
459
460 /* MSI-X vectors always belong to us */
461 return IRQ_HANDLED;
462}
463
f4f3d0f0
RD		 464static int mthca_create_eq(struct mthca_dev *dev,
465 int nent,
466 u8 intr,
467 struct mthca_eq *eq)
1da177e4 468{
46620056 469 int npages;
1da177e4
LT		 470 u64 *dma_list = NULL;
471 dma_addr_t t;
ed878458 472 struct mthca_mailbox *mailbox;
1da177e4
LT		 473 struct mthca_eq_context *eq_context;
474 int err = -ENOMEM;
475 int i;
476 u8 status;
477
c915033f
RD		 478 eq->dev = dev;
479 eq->nent = roundup_pow_of_two(max(nent, 2));
2fa5e2eb 480 npages = ALIGN(eq->nent * MTHCA_EQ_ENTRY_SIZE, PAGE_SIZE) / PAGE_SIZE;
1da177e4
LT		 481
482 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
483 GFP_KERNEL);
484 if (!eq->page_list)
485 goto err_out;
486
487 for (i = 0; i < npages; ++i)
488 eq->page_list[i].buf = NULL;
489
490 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
491 if (!dma_list)
492 goto err_out_free;
493
ed878458
RD		 494 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
495 if (IS_ERR(mailbox))
1da177e4 496 goto err_out_free;
ed878458 497 eq_context = mailbox->buf;
1da177e4
LT		 498
499 for (i = 0; i < npages; ++i) {
64dc81fc
RD		 500 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
501 PAGE_SIZE, &t, GFP_KERNEL);
1da177e4 502 if (!eq->page_list[i].buf)
ed878458 503 goto err_out_free_pages;
1da177e4
LT		 504
505 dma_list[i] = t;
506 pci_unmap_addr_set(&eq->page_list[i], mapping, t);
507
8909c571 508 clear_page(eq->page_list[i].buf);
1da177e4
LT		 509 }
510
c915033f 511 for (i = 0; i < eq->nent; ++i)
1da177e4
LT		 512 set_eqe_hw(get_eqe(eq, i));
513
514 eq->eqn = mthca_alloc(&dev->eq_table.alloc);
515 if (eq->eqn == -1)
ed878458 516 goto err_out_free_pages;
1da177e4
LT		 517
518 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
519 dma_list, PAGE_SHIFT, npages,
520 0, npages * PAGE_SIZE,
521 MTHCA_MPT_FLAG_LOCAL_WRITE |
522 MTHCA_MPT_FLAG_LOCAL_READ,
523 &eq->mr);
524 if (err)
525 goto err_out_free_eq;
526
1da177e4
LT		 527 memset(eq_context, 0, sizeof *eq_context);
528 eq_context->flags = cpu_to_be32(MTHCA_EQ_STATUS_OK |
529 MTHCA_EQ_OWNER_HW |
530 MTHCA_EQ_STATE_ARMED |
531 MTHCA_EQ_FLAG_TR);
d10ddbf6 532 if (mthca_is_memfree(dev))
1da177e4
LT		 533 eq_context->flags |= cpu_to_be32(MTHCA_EQ_STATE_ARBEL);
534
c915033f 535 eq_context->logsize_usrpage = cpu_to_be32((ffs(eq->nent) - 1) << 24);
d10ddbf6 536 if (mthca_is_memfree(dev)) {
1da177e4
LT		 537 eq_context->arbel_pd = cpu_to_be32(dev->driver_pd.pd_num);
538 } else {
539 eq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
540 eq_context->tavor_pd = cpu_to_be32(dev->driver_pd.pd_num);
541 }
542 eq_context->intr = intr;
543 eq_context->lkey = cpu_to_be32(eq->mr.ibmr.lkey);
544
ed878458 545 err = mthca_SW2HW_EQ(dev, mailbox, eq->eqn, &status);
1da177e4
LT		 546 if (err) {
547 mthca_warn(dev, "SW2HW_EQ failed (%d)\n", err);
548 goto err_out_free_mr;
549 }
550 if (status) {
551 mthca_warn(dev, "SW2HW_EQ returned status 0x%02x\n",
552 status);
553 err = -EINVAL;
554 goto err_out_free_mr;
555 }
556
557 kfree(dma_list);
ed878458 558 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 559
560 eq->eqn_mask = swab32(1 << eq->eqn);
561 eq->cons_index = 0;
562
563 dev->eq_table.arm_mask |= eq->eqn_mask;
564
565 mthca_dbg(dev, "Allocated EQ %d with %d entries\n",
c915033f 566 eq->eqn, eq->nent);
1da177e4
LT		 567
568 return err;
569
570 err_out_free_mr:
571 mthca_free_mr(dev, &eq->mr);
572
573 err_out_free_eq:
574 mthca_free(&dev->eq_table.alloc, eq->eqn);
575
ed878458 576 err_out_free_pages:
1da177e4
LT		 577 for (i = 0; i < npages; ++i)
578 if (eq->page_list[i].buf)
64dc81fc
RD		 579 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
580 eq->page_list[i].buf,
581 pci_unmap_addr(&eq->page_list[i],
582 mapping));
1da177e4 583
ed878458
RD		 584 mthca_free_mailbox(dev, mailbox);
585
586 err_out_free:
1da177e4
LT		 587 kfree(eq->page_list);
588 kfree(dma_list);
1da177e4
LT		 589
590 err_out:
591 return err;
592}
593
594static void mthca_free_eq(struct mthca_dev *dev,
595 struct mthca_eq *eq)
596{
ed878458 597 struct mthca_mailbox *mailbox;
1da177e4
LT		 598 int err;
599 u8 status;
600 int npages = (eq->nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
601 PAGE_SIZE;
602 int i;
603
ed878458
RD		 604 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
605 if (IS_ERR(mailbox))
1da177e4
LT		 606 return;
607
ed878458 608 err = mthca_HW2SW_EQ(dev, mailbox, eq->eqn, &status);
1da177e4
LT		 609 if (err)
610 mthca_warn(dev, "HW2SW_EQ failed (%d)\n", err);
611 if (status)
177214af 612 mthca_warn(dev, "HW2SW_EQ returned status 0x%02x\n", status);
1da177e4
LT		 613
614 dev->eq_table.arm_mask &= ~eq->eqn_mask;
615
616 if (0) {
617 mthca_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
618 for (i = 0; i < sizeof (struct mthca_eq_context) / 4; ++i) {
619 if (i % 4 == 0)
620 printk("[%02x] ", i * 4);
ed878458 621 printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
1da177e4
LT		 622 if ((i + 1) % 4 == 0)
623 printk("\n");
624 }
625 }
626
627 mthca_free_mr(dev, &eq->mr);
628 for (i = 0; i < npages; ++i)
629 pci_free_consistent(dev->pdev, PAGE_SIZE,
630 eq->page_list[i].buf,
631 pci_unmap_addr(&eq->page_list[i], mapping));
632
633 kfree(eq->page_list);
ed878458 634 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 635}
636
637static void mthca_free_irqs(struct mthca_dev *dev)
638{
639 int i;
640
641 if (dev->eq_table.have_irq)
642 free_irq(dev->pdev->irq, dev);
643 for (i = 0; i < MTHCA_NUM_EQ; ++i)
644 if (dev->eq_table.eq[i].have_irq)
645 free_irq(dev->eq_table.eq[i].msi_x_vector,
646 dev->eq_table.eq + i);
647}
648
f4f3d0f0
RD		 649static int mthca_map_reg(struct mthca_dev *dev,
650 unsigned long offset, unsigned long size,
651 void __iomem **map)
1da177e4
LT		 652{
653 unsigned long base = pci_resource_start(dev->pdev, 0);
654
1da177e4 655 *map = ioremap(base + offset, size);
208dde28 656 if (!*map)
1da177e4 657 return -ENOMEM;
1da177e4
LT		 658
659 return 0;
660}
661
f4f3d0f0 662static int mthca_map_eq_regs(struct mthca_dev *dev)
1da177e4 663{
d10ddbf6 664 if (mthca_is_memfree(dev)) {
1da177e4
LT		 665 /*
666 * We assume that the EQ arm and EQ set CI registers
667 * fall within the first BAR. We can't trust the
668 * values firmware gives us, since those addresses are
669 * valid on the HCA's side of the PCI bus but not
670 * necessarily the host side.
671 */
672 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
673 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
674 &dev->clr_base)) {
675 mthca_err(dev, "Couldn't map interrupt clear register, "
676 "aborting.\n");
677 return -ENOMEM;
678 }
679
680 /*
681 * Add 4 because we limit ourselves to EQs 0 ... 31,
682 * so we only need the low word of the register.
683 */
684 if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
685 dev->fw.arbel.eq_arm_base) + 4, 4,
686 &dev->eq_regs.arbel.eq_arm)) {
177214af 687 mthca_err(dev, "Couldn't map EQ arm register, aborting.\n");
208dde28 688 iounmap(dev->clr_base);
1da177e4
LT		 689 return -ENOMEM;
690 }
691
692 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
693 dev->fw.arbel.eq_set_ci_base,
694 MTHCA_EQ_SET_CI_SIZE,
695 &dev->eq_regs.arbel.eq_set_ci_base)) {
177214af 696 mthca_err(dev, "Couldn't map EQ CI register, aborting.\n");
208dde28
RD		 697 iounmap(dev->eq_regs.arbel.eq_arm);
698 iounmap(dev->clr_base);
1da177e4
LT		 699 return -ENOMEM;
700 }
701 } else {
702 if (mthca_map_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
703 &dev->clr_base)) {
704 mthca_err(dev, "Couldn't map interrupt clear register, "
705 "aborting.\n");
706 return -ENOMEM;
707 }
708
709 if (mthca_map_reg(dev, MTHCA_ECR_BASE,
710 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
711 &dev->eq_regs.tavor.ecr_base)) {
712 mthca_err(dev, "Couldn't map ecr register, "
713 "aborting.\n");
208dde28 714 iounmap(dev->clr_base);
1da177e4
LT		 715 return -ENOMEM;
716 }
717 }
718
719 return 0;
720
721}
722
e1f7868c 723static void mthca_unmap_eq_regs(struct mthca_dev *dev)
1da177e4 724{
d10ddbf6 725 if (mthca_is_memfree(dev)) {
208dde28
RD		 726 iounmap(dev->eq_regs.arbel.eq_set_ci_base);
727 iounmap(dev->eq_regs.arbel.eq_arm);
728 iounmap(dev->clr_base);
1da177e4 729 } else {
208dde28
RD		 730 iounmap(dev->eq_regs.tavor.ecr_base);
731 iounmap(dev->clr_base);
1da177e4
LT		 732 }
733}
734
f4f3d0f0 735int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt)
1da177e4
LT		 736{
737 int ret;
738 u8 status;
739
740 /*
741 * We assume that mapping one page is enough for the whole EQ
742 * context table. This is fine with all current HCAs, because
743 * we only use 32 EQs and each EQ uses 32 bytes of context
744 * memory, or 1 KB total.
745 */
746 dev->eq_table.icm_virt = icm_virt;
747 dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
748 if (!dev->eq_table.icm_page)
749 return -ENOMEM;
750 dev->eq_table.icm_dma = pci_map_page(dev->pdev, dev->eq_table.icm_page, 0,
751 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
8d8bb39b 752 if (pci_dma_mapping_error(dev->pdev, dev->eq_table.icm_dma)) {
1da177e4
LT		 753 __free_page(dev->eq_table.icm_page);
754 return -ENOMEM;
755 }
756
757 ret = mthca_MAP_ICM_page(dev, dev->eq_table.icm_dma, icm_virt, &status);
758 if (!ret && status)
759 ret = -EINVAL;
760 if (ret) {
761 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
762 PCI_DMA_BIDIRECTIONAL);
763 __free_page(dev->eq_table.icm_page);
764 }
765
766 return ret;
767}
768
e1f7868c 769void mthca_unmap_eq_icm(struct mthca_dev *dev)
1da177e4
LT		 770{
771 u8 status;
772
8d3ef29d 773 mthca_UNMAP_ICM(dev, dev->eq_table.icm_virt, 1, &status);
1da177e4
LT		 774 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
775 PCI_DMA_BIDIRECTIONAL);
776 __free_page(dev->eq_table.icm_page);
777}
778
f4f3d0f0 779int mthca_init_eq_table(struct mthca_dev *dev)
1da177e4
LT		 780{
781 int err;
782 u8 status;
783 u8 intr;
784 int i;
785
786 err = mthca_alloc_init(&dev->eq_table.alloc,
787 dev->limits.num_eqs,
788 dev->limits.num_eqs - 1,
789 dev->limits.reserved_eqs);
790 if (err)
791 return err;
792
793 err = mthca_map_eq_regs(dev);
794 if (err)
795 goto err_out_free;
796
e57895d3 797 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
1da177e4
LT		 798 dev->eq_table.clr_mask = 0;
799 } else {
800 dev->eq_table.clr_mask =
801 swab32(1 << (dev->eq_table.inta_pin & 31));
802 dev->eq_table.clr_int = dev->clr_base +
f7ed3a59 803 (dev->eq_table.inta_pin < 32 ? 4 : 0);
1da177e4
LT		 804 }
805
806 dev->eq_table.arm_mask = 0;
807
e57895d3 808 intr = dev->eq_table.inta_pin;
1da177e4 809
92898522 810 err = mthca_create_eq(dev, dev->limits.num_cqs + MTHCA_NUM_SPARE_EQE,
1da177e4
LT		 811 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr,
812 &dev->eq_table.eq[MTHCA_EQ_COMP]);
813 if (err)
814 goto err_out_unmap;
815
92898522 816 err = mthca_create_eq(dev, MTHCA_NUM_ASYNC_EQE + MTHCA_NUM_SPARE_EQE,
1da177e4
LT		 817 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr,
818 &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
819 if (err)
820 goto err_out_comp;
821
92898522 822 err = mthca_create_eq(dev, MTHCA_NUM_CMD_EQE + MTHCA_NUM_SPARE_EQE,
1da177e4
LT		 823 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr,
824 &dev->eq_table.eq[MTHCA_EQ_CMD]);
825 if (err)
826 goto err_out_async;
827
828 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
829 static const char *eq_name[] = {
830 [MTHCA_EQ_COMP] = DRV_NAME " (comp)",
831 [MTHCA_EQ_ASYNC] = DRV_NAME " (async)",
832 [MTHCA_EQ_CMD] = DRV_NAME " (cmd)"
833 };
834
835 for (i = 0; i < MTHCA_NUM_EQ; ++i) {
836 err = request_irq(dev->eq_table.eq[i].msi_x_vector,
d10ddbf6 837 mthca_is_memfree(dev) ?
1da177e4
LT		 838 mthca_arbel_msi_x_interrupt :
839 mthca_tavor_msi_x_interrupt,
840 0, eq_name[i], dev->eq_table.eq + i);
841 if (err)
842 goto err_out_cmd;
843 dev->eq_table.eq[i].have_irq = 1;
844 }
845 } else {
846 err = request_irq(dev->pdev->irq,
d10ddbf6 847 mthca_is_memfree(dev) ?
1da177e4
LT		 848 mthca_arbel_interrupt :
849 mthca_tavor_interrupt,
dace1453 850 IRQF_SHARED, DRV_NAME, dev);
1da177e4
LT		 851 if (err)
852 goto err_out_cmd;
853 dev->eq_table.have_irq = 1;
854 }
855
856 err = mthca_MAP_EQ(dev, async_mask(dev),
857 0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
858 if (err)
859 mthca_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
860 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, err);
861 if (status)
862 mthca_warn(dev, "MAP_EQ for async EQ %d returned status 0x%02x\n",
863 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, status);
864
865 err = mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
866 0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
867 if (err)
868 mthca_warn(dev, "MAP_EQ for cmd EQ %d failed (%d)\n",
869 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, err);
870 if (status)
871 mthca_warn(dev, "MAP_EQ for cmd EQ %d returned status 0x%02x\n",
872 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, status);
873
6b63e301 874 for (i = 0; i < MTHCA_NUM_EQ; ++i)
d10ddbf6 875 if (mthca_is_memfree(dev))
1da177e4
LT		 876 arbel_eq_req_not(dev, dev->eq_table.eq[i].eqn_mask);
877 else
878 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
879
880 return 0;
881
882err_out_cmd:
883 mthca_free_irqs(dev);
884 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_CMD]);
885
886err_out_async:
887 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
888
889err_out_comp:
890 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_COMP]);
891
892err_out_unmap:
893 mthca_unmap_eq_regs(dev);
894
895err_out_free:
896 mthca_alloc_cleanup(&dev->eq_table.alloc);
897 return err;
898}
899
e1f7868c 900void mthca_cleanup_eq_table(struct mthca_dev *dev)
1da177e4
LT		 901{
902 u8 status;
903 int i;
904
905 mthca_free_irqs(dev);
906
907 mthca_MAP_EQ(dev, async_mask(dev),
908 1, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
909 mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
910 1, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
911
912 for (i = 0; i < MTHCA_NUM_EQ; ++i)
913 mthca_free_eq(dev, &dev->eq_table.eq[i]);
914
915 mthca_unmap_eq_regs(dev);
916
917 mthca_alloc_cleanup(&dev->eq_table.alloc);
918}
Linux 6.x block layer and io_uring tree(s)