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[PATCH] IB: move include files to include/rdma
[linux-2.6-block.git] / drivers / infiniband / hw / mthca / mthca_cmd.h
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
2a1d9b7f 3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
1da177e4
LT		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 * $Id: mthca_cmd.h 1349 2004-12-16 21:09:43Z roland $
34 */
35
36#ifndef MTHCA_CMD_H
37#define MTHCA_CMD_H
38
a4d61e84 39#include <rdma/ib_verbs.h>
1da177e4 40
ed878458 41#define MTHCA_MAILBOX_SIZE 4096
1da177e4
LT		 42
43enum {
44 /* command completed successfully: */
45 MTHCA_CMD_STAT_OK = 0x00,
46 /* Internal error (such as a bus error) occurred while processing command: */
47 MTHCA_CMD_STAT_INTERNAL_ERR = 0x01,
48 /* Operation/command not supported or opcode modifier not supported: */
49 MTHCA_CMD_STAT_BAD_OP = 0x02,
50 /* Parameter not supported or parameter out of range: */
51 MTHCA_CMD_STAT_BAD_PARAM = 0x03,
52 /* System not enabled or bad system state: */
53 MTHCA_CMD_STAT_BAD_SYS_STATE = 0x04,
54 /* Attempt to access reserved or unallocaterd resource: */
55 MTHCA_CMD_STAT_BAD_RESOURCE = 0x05,
56 /* Requested resource is currently executing a command, or is otherwise busy: */
57 MTHCA_CMD_STAT_RESOURCE_BUSY = 0x06,
58 /* memory error: */
59 MTHCA_CMD_STAT_DDR_MEM_ERR = 0x07,
60 /* Required capability exceeds device limits: */
61 MTHCA_CMD_STAT_EXCEED_LIM = 0x08,
62 /* Resource is not in the appropriate state or ownership: */
63 MTHCA_CMD_STAT_BAD_RES_STATE = 0x09,
64 /* Index out of range: */
65 MTHCA_CMD_STAT_BAD_INDEX = 0x0a,
66 /* FW image corrupted: */
67 MTHCA_CMD_STAT_BAD_NVMEM = 0x0b,
68 /* Attempt to modify a QP/EE which is not in the presumed state: */
69 MTHCA_CMD_STAT_BAD_QPEE_STATE = 0x10,
70 /* Bad segment parameters (Address/Size): */
71 MTHCA_CMD_STAT_BAD_SEG_PARAM = 0x20,
72 /* Memory Region has Memory Windows bound to: */
73 MTHCA_CMD_STAT_REG_BOUND = 0x21,
74 /* HCA local attached memory not present: */
75 MTHCA_CMD_STAT_LAM_NOT_PRE = 0x22,
76 /* Bad management packet (silently discarded): */
77 MTHCA_CMD_STAT_BAD_PKT = 0x30,
78 /* More outstanding CQEs in CQ than new CQ size: */
79 MTHCA_CMD_STAT_BAD_SIZE = 0x40
80};
81
82enum {
83 MTHCA_TRANS_INVALID = 0,
84 MTHCA_TRANS_RST2INIT,
85 MTHCA_TRANS_INIT2INIT,
86 MTHCA_TRANS_INIT2RTR,
87 MTHCA_TRANS_RTR2RTS,
88 MTHCA_TRANS_RTS2RTS,
89 MTHCA_TRANS_SQERR2RTS,
90 MTHCA_TRANS_ANY2ERR,
91 MTHCA_TRANS_RTS2SQD,
92 MTHCA_TRANS_SQD2SQD,
93 MTHCA_TRANS_SQD2RTS,
94 MTHCA_TRANS_ANY2RST,
95};
96
97enum {
98 DEV_LIM_FLAG_RC = 1 << 0,
99 DEV_LIM_FLAG_UC = 1 << 1,
100 DEV_LIM_FLAG_UD = 1 << 2,
101 DEV_LIM_FLAG_RD = 1 << 3,
102 DEV_LIM_FLAG_RAW_IPV6 = 1 << 4,
103 DEV_LIM_FLAG_RAW_ETHER = 1 << 5,
104 DEV_LIM_FLAG_SRQ = 1 << 6,
105 DEV_LIM_FLAG_BAD_PKEY_CNTR = 1 << 8,
106 DEV_LIM_FLAG_BAD_QKEY_CNTR = 1 << 9,
107 DEV_LIM_FLAG_MW = 1 << 16,
108 DEV_LIM_FLAG_AUTO_PATH_MIG = 1 << 17,
109 DEV_LIM_FLAG_ATOMIC = 1 << 18,
110 DEV_LIM_FLAG_RAW_MULTI = 1 << 19,
111 DEV_LIM_FLAG_UD_AV_PORT_ENFORCE = 1 << 20,
112 DEV_LIM_FLAG_UD_MULTI = 1 << 21,
113};
114
ed878458
RD		 115struct mthca_mailbox {
116 dma_addr_t dma;
117 void *buf;
118};
119
1da177e4
LT		 120struct mthca_dev_lim {
121 int max_srq_sz;
122 int max_qp_sz;
123 int reserved_qps;
124 int max_qps;
125 int reserved_srqs;
126 int max_srqs;
127 int reserved_eecs;
128 int max_eecs;
129 int max_cq_sz;
130 int reserved_cqs;
131 int max_cqs;
132 int max_mpts;
133 int reserved_eqs;
134 int max_eqs;
135 int reserved_mtts;
136 int max_mrw_sz;
137 int reserved_mrws;
138 int max_mtt_seg;
139 int max_requester_per_qp;
140 int max_responder_per_qp;
141 int max_rdma_global;
142 int local_ca_ack_delay;
143 int max_mtu;
144 int max_port_width;
145 int max_vl;
146 int num_ports;
147 int max_gids;
148 int max_pkeys;
149 u32 flags;
150 int reserved_uars;
151 int uar_size;
152 int min_page_sz;
153 int max_sg;
154 int max_desc_sz;
155 int max_qp_per_mcg;
156 int reserved_mgms;
157 int max_mcgs;
158 int reserved_pds;
159 int max_pds;
160 int reserved_rdds;
161 int max_rdds;
162 int eec_entry_sz;
163 int qpc_entry_sz;
164 int eeec_entry_sz;
165 int eqpc_entry_sz;
166 int eqc_entry_sz;
167 int cqc_entry_sz;
168 int srq_entry_sz;
169 int uar_scratch_entry_sz;
1da177e4
LT		 170 int mpt_entry_sz;
171 union {
172 struct {
173 int max_avs;
174 } tavor;
175 struct {
176 int resize_srq;
177 int max_pbl_sz;
178 u8 bmme_flags;
179 u32 reserved_lkey;
180 int lam_required;
181 u64 max_icm_sz;
182 } arbel;
183 } hca;
184};
185
186struct mthca_adapter {
2e8b981c
MT		 187 u32 vendor_id;
188 u32 device_id;
189 u32 revision_id;
190 char board_id[MTHCA_BOARD_ID_LEN];
191 u8 inta_pin;
1da177e4
LT		 192};
193
194struct mthca_init_hca_param {
195 u64 qpc_base;
196 u64 eec_base;
197 u64 srqc_base;
198 u64 cqc_base;
199 u64 eqpc_base;
200 u64 eeec_base;
201 u64 eqc_base;
202 u64 rdb_base;
203 u64 mc_base;
204 u64 mpt_base;
205 u64 mtt_base;
206 u64 uar_scratch_base;
207 u64 uarc_base;
208 u16 log_mc_entry_sz;
209 u16 mc_hash_sz;
210 u8 log_num_qps;
211 u8 log_num_eecs;
212 u8 log_num_srqs;
213 u8 log_num_cqs;
214 u8 log_num_eqs;
215 u8 log_mc_table_sz;
216 u8 mtt_seg_sz;
217 u8 log_mpt_sz;
218 u8 log_uar_sz;
219 u8 log_uarc_sz;
220};
221
222struct mthca_init_ib_param {
da6561c2 223 int port_width;
1da177e4
LT		 224 int vl_cap;
225 int mtu_cap;
226 u16 gid_cap;
227 u16 pkey_cap;
228 int set_guid0;
229 u64 guid0;
230 int set_node_guid;
231 u64 node_guid;
232 int set_si_guid;
233 u64 si_guid;
234};
235
236struct mthca_set_ib_param {
237 int set_si_guid;
238 int reset_qkey_viol;
239 u64 si_guid;
240 u32 cap_mask;
241};
242
80fd8238
RD		 243int mthca_cmd_init(struct mthca_dev *dev);
244void mthca_cmd_cleanup(struct mthca_dev *dev);
1da177e4
LT		 245int mthca_cmd_use_events(struct mthca_dev *dev);
246void mthca_cmd_use_polling(struct mthca_dev *dev);
247void mthca_cmd_event(struct mthca_dev *dev, u16 token,
248 u8 status, u64 out_param);
249
ed878458
RD		 250struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
251 unsigned int gfp_mask);
252void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox);
253
1da177e4
LT		 254int mthca_SYS_EN(struct mthca_dev *dev, u8 *status);
255int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status);
256int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status);
257int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status);
258int mthca_RUN_FW(struct mthca_dev *dev, u8 *status);
259int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status);
260int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status);
261int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status);
262int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status);
263int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
264 struct mthca_dev_lim *dev_lim, u8 *status);
265int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
266 struct mthca_adapter *adapter, u8 *status);
267int mthca_INIT_HCA(struct mthca_dev *dev,
268 struct mthca_init_hca_param *param,
269 u8 *status);
270int mthca_INIT_IB(struct mthca_dev *dev,
271 struct mthca_init_ib_param *param,
272 int port, u8 *status);
273int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status);
274int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status);
275int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
276 int port, u8 *status);
277int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status);
278int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status);
279int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status);
280int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status);
281int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status);
282int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
283 u8 *status);
ed878458 284int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4 285 int mpt_index, u8 *status);
ed878458 286int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4 287 int mpt_index, u8 *status);
ed878458 288int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4 289 int num_mtt, u8 *status);
b8ca06f6 290int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status);
1da177e4
LT		 291int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
292 int eq_num, u8 *status);
ed878458 293int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4 294 int eq_num, u8 *status);
ed878458 295int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4 296 int eq_num, u8 *status);
ed878458 297int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4 298 int cq_num, u8 *status);
ed878458 299int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4 300 int cq_num, u8 *status);
ec34a922
RD		 301int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
302 int srq_num, u8 *status);
303int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
304 int srq_num, u8 *status);
305int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status);
1da177e4 306int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
ed878458 307 int is_ee, struct mthca_mailbox *mailbox, u32 optmask,
1da177e4
LT		 308 u8 *status);
309int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
ed878458 310 struct mthca_mailbox *mailbox, u8 *status);
1da177e4
LT		 311int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
312 u8 *status);
313int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
ed878458 314 int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1da177e4 315 void *in_mad, void *response_mad, u8 *status);
ed878458
RD		 316int mthca_READ_MGM(struct mthca_dev *dev, int index,
317 struct mthca_mailbox *mailbox, u8 *status);
318int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
319 struct mthca_mailbox *mailbox, u8 *status);
320int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
321 u16 *hash, u8 *status);
1da177e4
LT		 322int mthca_NOP(struct mthca_dev *dev, u8 *status);
323
1da177e4 324#endif /* MTHCA_CMD_H */
Linux 6.x block layer and io_uring tree(s)