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[PATCH] IB: Remove unnecessary includes of <linux/version.h>
[linux-2.6-block.git] / drivers / infiniband / hw / mthca / mthca_cmd.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
2a1d9b7f 3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
1da177e4
LT		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
34 */
35
36#include <linux/sched.h>
37#include <linux/pci.h>
38#include <linux/errno.h>
39#include <asm/io.h>
40#include <ib_mad.h>
41
42#include "mthca_dev.h"
43#include "mthca_config_reg.h"
44#include "mthca_cmd.h"
45#include "mthca_memfree.h"
46
47#define CMD_POLL_TOKEN 0xffff
48
49enum {
50 HCR_IN_PARAM_OFFSET = 0x00,
51 HCR_IN_MODIFIER_OFFSET = 0x08,
52 HCR_OUT_PARAM_OFFSET = 0x0c,
53 HCR_TOKEN_OFFSET = 0x14,
54 HCR_STATUS_OFFSET = 0x18,
55
56 HCR_OPMOD_SHIFT = 12,
57 HCA_E_BIT = 22,
58 HCR_GO_BIT = 23
59};
60
61enum {
62 /* initialization and general commands */
63 CMD_SYS_EN = 0x1,
64 CMD_SYS_DIS = 0x2,
65 CMD_MAP_FA = 0xfff,
66 CMD_UNMAP_FA = 0xffe,
67 CMD_RUN_FW = 0xff6,
68 CMD_MOD_STAT_CFG = 0x34,
69 CMD_QUERY_DEV_LIM = 0x3,
70 CMD_QUERY_FW = 0x4,
71 CMD_ENABLE_LAM = 0xff8,
72 CMD_DISABLE_LAM = 0xff7,
73 CMD_QUERY_DDR = 0x5,
74 CMD_QUERY_ADAPTER = 0x6,
75 CMD_INIT_HCA = 0x7,
76 CMD_CLOSE_HCA = 0x8,
77 CMD_INIT_IB = 0x9,
78 CMD_CLOSE_IB = 0xa,
79 CMD_QUERY_HCA = 0xb,
80 CMD_SET_IB = 0xc,
81 CMD_ACCESS_DDR = 0x2e,
82 CMD_MAP_ICM = 0xffa,
83 CMD_UNMAP_ICM = 0xff9,
84 CMD_MAP_ICM_AUX = 0xffc,
85 CMD_UNMAP_ICM_AUX = 0xffb,
86 CMD_SET_ICM_SIZE = 0xffd,
87
88 /* TPT commands */
89 CMD_SW2HW_MPT = 0xd,
90 CMD_QUERY_MPT = 0xe,
91 CMD_HW2SW_MPT = 0xf,
92 CMD_READ_MTT = 0x10,
93 CMD_WRITE_MTT = 0x11,
94 CMD_SYNC_TPT = 0x2f,
95
96 /* EQ commands */
97 CMD_MAP_EQ = 0x12,
98 CMD_SW2HW_EQ = 0x13,
99 CMD_HW2SW_EQ = 0x14,
100 CMD_QUERY_EQ = 0x15,
101
102 /* CQ commands */
103 CMD_SW2HW_CQ = 0x16,
104 CMD_HW2SW_CQ = 0x17,
105 CMD_QUERY_CQ = 0x18,
106 CMD_RESIZE_CQ = 0x2c,
107
108 /* SRQ commands */
109 CMD_SW2HW_SRQ = 0x35,
110 CMD_HW2SW_SRQ = 0x36,
111 CMD_QUERY_SRQ = 0x37,
112
113 /* QP/EE commands */
114 CMD_RST2INIT_QPEE = 0x19,
115 CMD_INIT2RTR_QPEE = 0x1a,
116 CMD_RTR2RTS_QPEE = 0x1b,
117 CMD_RTS2RTS_QPEE = 0x1c,
118 CMD_SQERR2RTS_QPEE = 0x1d,
119 CMD_2ERR_QPEE = 0x1e,
120 CMD_RTS2SQD_QPEE = 0x1f,
121 CMD_SQD2SQD_QPEE = 0x38,
122 CMD_SQD2RTS_QPEE = 0x20,
123 CMD_ERR2RST_QPEE = 0x21,
124 CMD_QUERY_QPEE = 0x22,
125 CMD_INIT2INIT_QPEE = 0x2d,
126 CMD_SUSPEND_QPEE = 0x32,
127 CMD_UNSUSPEND_QPEE = 0x33,
128 /* special QPs and management commands */
129 CMD_CONF_SPECIAL_QP = 0x23,
130 CMD_MAD_IFC = 0x24,
131
132 /* multicast commands */
133 CMD_READ_MGM = 0x25,
134 CMD_WRITE_MGM = 0x26,
135 CMD_MGID_HASH = 0x27,
136
137 /* miscellaneous commands */
138 CMD_DIAG_RPRT = 0x30,
139 CMD_NOP = 0x31,
140
141 /* debug commands */
142 CMD_QUERY_DEBUG_MSG = 0x2a,
143 CMD_SET_DEBUG_MSG = 0x2b,
144};
145
146/*
147 * According to Mellanox code, FW may be starved and never complete
148 * commands. So we can't use strict timeouts described in PRM -- we
149 * just arbitrarily select 60 seconds for now.
150 */
151#if 0
152/*
153 * Round up and add 1 to make sure we get the full wait time (since we
154 * will be starting in the middle of a jiffy)
155 */
156enum {
157 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
158 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
159 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1
160};
161#else
162enum {
163 CMD_TIME_CLASS_A = 60 * HZ,
164 CMD_TIME_CLASS_B = 60 * HZ,
165 CMD_TIME_CLASS_C = 60 * HZ
166};
167#endif
168
169enum {
170 GO_BIT_TIMEOUT = HZ * 10
171};
172
173struct mthca_cmd_context {
174 struct completion done;
175 struct timer_list timer;
176 int result;
177 int next;
178 u64 out_param;
179 u16 token;
180 u8 status;
181};
182
183static inline int go_bit(struct mthca_dev *dev)
184{
185 return readl(dev->hcr + HCR_STATUS_OFFSET) &
186 swab32(1 << HCR_GO_BIT);
187}
188
189static int mthca_cmd_post(struct mthca_dev *dev,
190 u64 in_param,
191 u64 out_param,
192 u32 in_modifier,
193 u8 op_modifier,
194 u16 op,
195 u16 token,
196 int event)
197{
198 int err = 0;
199
200 if (down_interruptible(&dev->cmd.hcr_sem))
201 return -EINTR;
202
203 if (event) {
204 unsigned long end = jiffies + GO_BIT_TIMEOUT;
205
206 while (go_bit(dev) && time_before(jiffies, end)) {
207 set_current_state(TASK_RUNNING);
208 schedule();
209 }
210 }
211
212 if (go_bit(dev)) {
213 err = -EAGAIN;
214 goto out;
215 }
216
217 /*
218 * We use writel (instead of something like memcpy_toio)
219 * because writes of less than 32 bits to the HCR don't work
220 * (and some architectures such as ia64 implement memcpy_toio
221 * in terms of writeb).
222 */
97f52eb4
SH		 223 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
224 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
225 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
226 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
227 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
228 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
1da177e4
LT		 229
230 /* __raw_writel may not order writes. */
231 wmb();
232
97f52eb4
SH		 233 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
234 (event ? (1 << HCA_E_BIT) : 0) |
235 (op_modifier << HCR_OPMOD_SHIFT) |
236 op), dev->hcr + 6 * 4);
1da177e4
LT		 237
238out:
239 up(&dev->cmd.hcr_sem);
240 return err;
241}
242
243static int mthca_cmd_poll(struct mthca_dev *dev,
244 u64 in_param,
245 u64 *out_param,
246 int out_is_imm,
247 u32 in_modifier,
248 u8 op_modifier,
249 u16 op,
250 unsigned long timeout,
251 u8 *status)
252{
253 int err = 0;
254 unsigned long end;
255
256 if (down_interruptible(&dev->cmd.poll_sem))
257 return -EINTR;
258
259 err = mthca_cmd_post(dev, in_param,
260 out_param ? *out_param : 0,
261 in_modifier, op_modifier,
262 op, CMD_POLL_TOKEN, 0);
263 if (err)
264 goto out;
265
266 end = timeout + jiffies;
267 while (go_bit(dev) && time_before(jiffies, end)) {
268 set_current_state(TASK_RUNNING);
269 schedule();
270 }
271
272 if (go_bit(dev)) {
273 err = -EBUSY;
274 goto out;
275 }
276
97f52eb4
SH		 277 if (out_is_imm)
278 *out_param =
279 (u64) be32_to_cpu((__force __be32)
280 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
281 (u64) be32_to_cpu((__force __be32)
282 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
1da177e4 283
97f52eb4 284 *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
1da177e4
LT		 285
286out:
287 up(&dev->cmd.poll_sem);
288 return err;
289}
290
291void mthca_cmd_event(struct mthca_dev *dev,
292 u16 token,
293 u8 status,
294 u64 out_param)
295{
296 struct mthca_cmd_context *context =
297 &dev->cmd.context[token & dev->cmd.token_mask];
298
299 /* previously timed out command completing at long last */
300 if (token != context->token)
301 return;
302
303 context->result = 0;
304 context->status = status;
305 context->out_param = out_param;
306
307 context->token += dev->cmd.token_mask + 1;
308
309 complete(&context->done);
310}
311
312static void event_timeout(unsigned long context_ptr)
313{
314 struct mthca_cmd_context *context =
315 (struct mthca_cmd_context *) context_ptr;
316
317 context->result = -EBUSY;
318 complete(&context->done);
319}
320
321static int mthca_cmd_wait(struct mthca_dev *dev,
322 u64 in_param,
323 u64 *out_param,
324 int out_is_imm,
325 u32 in_modifier,
326 u8 op_modifier,
327 u16 op,
328 unsigned long timeout,
329 u8 *status)
330{
331 int err = 0;
332 struct mthca_cmd_context *context;
333
334 if (down_interruptible(&dev->cmd.event_sem))
335 return -EINTR;
336
337 spin_lock(&dev->cmd.context_lock);
338 BUG_ON(dev->cmd.free_head < 0);
339 context = &dev->cmd.context[dev->cmd.free_head];
340 dev->cmd.free_head = context->next;
341 spin_unlock(&dev->cmd.context_lock);
342
343 init_completion(&context->done);
344
345 err = mthca_cmd_post(dev, in_param,
346 out_param ? *out_param : 0,
347 in_modifier, op_modifier,
348 op, context->token, 1);
349 if (err)
350 goto out;
351
352 context->timer.expires = jiffies + timeout;
353 add_timer(&context->timer);
354
355 wait_for_completion(&context->done);
356 del_timer_sync(&context->timer);
357
358 err = context->result;
359 if (err)
360 goto out;
361
362 *status = context->status;
363 if (*status)
364 mthca_dbg(dev, "Command %02x completed with status %02x\n",
365 op, *status);
366
367 if (out_is_imm)
368 *out_param = context->out_param;
369
370out:
371 spin_lock(&dev->cmd.context_lock);
372 context->next = dev->cmd.free_head;
373 dev->cmd.free_head = context - dev->cmd.context;
374 spin_unlock(&dev->cmd.context_lock);
375
376 up(&dev->cmd.event_sem);
377 return err;
378}
379
380/* Invoke a command with an output mailbox */
381static int mthca_cmd_box(struct mthca_dev *dev,
382 u64 in_param,
383 u64 out_param,
384 u32 in_modifier,
385 u8 op_modifier,
386 u16 op,
387 unsigned long timeout,
388 u8 *status)
389{
390 if (dev->cmd.use_events)
391 return mthca_cmd_wait(dev, in_param, &out_param, 0,
392 in_modifier, op_modifier, op,
393 timeout, status);
394 else
395 return mthca_cmd_poll(dev, in_param, &out_param, 0,
396 in_modifier, op_modifier, op,
397 timeout, status);
398}
399
400/* Invoke a command with no output parameter */
401static int mthca_cmd(struct mthca_dev *dev,
402 u64 in_param,
403 u32 in_modifier,
404 u8 op_modifier,
405 u16 op,
406 unsigned long timeout,
407 u8 *status)
408{
409 return mthca_cmd_box(dev, in_param, 0, in_modifier,
410 op_modifier, op, timeout, status);
411}
412
413/*
414 * Invoke a command with an immediate output parameter (and copy the
415 * output into the caller's out_param pointer after the command
416 * executes).
417 */
418static int mthca_cmd_imm(struct mthca_dev *dev,
419 u64 in_param,
420 u64 *out_param,
421 u32 in_modifier,
422 u8 op_modifier,
423 u16 op,
424 unsigned long timeout,
425 u8 *status)
426{
427 if (dev->cmd.use_events)
428 return mthca_cmd_wait(dev, in_param, out_param, 1,
429 in_modifier, op_modifier, op,
430 timeout, status);
431 else
432 return mthca_cmd_poll(dev, in_param, out_param, 1,
433 in_modifier, op_modifier, op,
434 timeout, status);
435}
436
80fd8238
RD		 437int mthca_cmd_init(struct mthca_dev *dev)
438{
439 sema_init(&dev->cmd.hcr_sem, 1);
440 sema_init(&dev->cmd.poll_sem, 1);
441 dev->cmd.use_events = 0;
442
443 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
444 MTHCA_HCR_SIZE);
445 if (!dev->hcr) {
446 mthca_err(dev, "Couldn't map command register.");
447 return -ENOMEM;
448 }
449
ed878458
RD		 450 dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
451 MTHCA_MAILBOX_SIZE,
452 MTHCA_MAILBOX_SIZE, 0);
453 if (!dev->cmd.pool) {
454 iounmap(dev->hcr);
455 return -ENOMEM;
456 }
457
80fd8238
RD		 458 return 0;
459}
460
461void mthca_cmd_cleanup(struct mthca_dev *dev)
462{
ed878458 463 pci_pool_destroy(dev->cmd.pool);
80fd8238
RD		 464 iounmap(dev->hcr);
465}
466
1da177e4
LT		 467/*
468 * Switch to using events to issue FW commands (should be called after
469 * event queue to command events has been initialized).
470 */
471int mthca_cmd_use_events(struct mthca_dev *dev)
472{
473 int i;
474
475 dev->cmd.context = kmalloc(dev->cmd.max_cmds *
476 sizeof (struct mthca_cmd_context),
477 GFP_KERNEL);
478 if (!dev->cmd.context)
479 return -ENOMEM;
480
481 for (i = 0; i < dev->cmd.max_cmds; ++i) {
482 dev->cmd.context[i].token = i;
483 dev->cmd.context[i].next = i + 1;
484 init_timer(&dev->cmd.context[i].timer);
485 dev->cmd.context[i].timer.data =
486 (unsigned long) &dev->cmd.context[i];
487 dev->cmd.context[i].timer.function = event_timeout;
488 }
489
490 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
491 dev->cmd.free_head = 0;
492
493 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
494 spin_lock_init(&dev->cmd.context_lock);
495
496 for (dev->cmd.token_mask = 1;
497 dev->cmd.token_mask < dev->cmd.max_cmds;
498 dev->cmd.token_mask <<= 1)
499 ; /* nothing */
500 --dev->cmd.token_mask;
501
502 dev->cmd.use_events = 1;
503 down(&dev->cmd.poll_sem);
504
505 return 0;
506}
507
508/*
509 * Switch back to polling (used when shutting down the device)
510 */
511void mthca_cmd_use_polling(struct mthca_dev *dev)
512{
513 int i;
514
515 dev->cmd.use_events = 0;
516
517 for (i = 0; i < dev->cmd.max_cmds; ++i)
518 down(&dev->cmd.event_sem);
519
520 kfree(dev->cmd.context);
521
522 up(&dev->cmd.poll_sem);
523}
524
ed878458
RD		 525struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
526 unsigned int gfp_mask)
527{
528 struct mthca_mailbox *mailbox;
529
530 mailbox = kmalloc(sizeof *mailbox, gfp_mask);
531 if (!mailbox)
532 return ERR_PTR(-ENOMEM);
533
534 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
535 if (!mailbox->buf) {
536 kfree(mailbox);
537 return ERR_PTR(-ENOMEM);
538 }
539
540 return mailbox;
541}
542
543void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
544{
545 if (!mailbox)
546 return;
547
548 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
549 kfree(mailbox);
550}
551
1da177e4
LT		 552int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
553{
554 u64 out;
555 int ret;
556
557 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
558
559 if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
560 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
561 "sladdr=%d, SPD source=%s\n",
562 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
563 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
564
565 return ret;
566}
567
568int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
569{
570 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
571}
572
573static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
574 u64 virt, u8 *status)
575{
ed878458 576 struct mthca_mailbox *mailbox;
1da177e4 577 struct mthca_icm_iter iter;
ed878458 578 __be64 *pages;
1da177e4
LT		 579 int lg;
580 int nent = 0;
581 int i;
582 int err = 0;
583 int ts = 0, tc = 0;
584
ed878458
RD		 585 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
586 if (IS_ERR(mailbox))
587 return PTR_ERR(mailbox);
588 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
589 pages = mailbox->buf;
1da177e4
LT		 590
591 for (mthca_icm_first(icm, &iter);
592 !mthca_icm_last(&iter);
593 mthca_icm_next(&iter)) {
594 /*
595 * We have to pass pages that are aligned to their
596 * size, so find the least significant 1 in the
597 * address or size and use that as our log2 size.
598 */
599 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
600 if (lg < 12) {
601 mthca_warn(dev, "Got FW area not aligned to 4K (%llx/%lx).\n",
602 (unsigned long long) mthca_icm_addr(&iter),
603 mthca_icm_size(&iter));
604 err = -EINVAL;
605 goto out;
606 }
607 for (i = 0; i < mthca_icm_size(&iter) / (1 << lg); ++i, ++nent) {
608 if (virt != -1) {
ed878458 609 pages[nent * 2] = cpu_to_be64(virt);
1da177e4
LT		 610 virt += 1 << lg;
611 }
612
ed878458
RD		 613 pages[nent * 2 + 1] = cpu_to_be64((mthca_icm_addr(&iter) +
614 (i << lg)) | (lg - 12));
1da177e4
LT		 615 ts += 1 << (lg - 10);
616 ++tc;
617
ed878458
RD		 618 if (nent == MTHCA_MAILBOX_SIZE / 16) {
619 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
1da177e4
LT		 620 CMD_TIME_CLASS_B, status);
621 if (err || *status)
622 goto out;
623 nent = 0;
624 }
625 }
626 }
627
628 if (nent)
ed878458 629 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
1da177e4
LT		 630 CMD_TIME_CLASS_B, status);
631
632 switch (op) {
633 case CMD_MAP_FA:
634 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
635 break;
636 case CMD_MAP_ICM_AUX:
637 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
638 break;
639 case CMD_MAP_ICM:
640 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
641 tc, ts, (unsigned long long) virt - (ts << 10));
642 break;
643 }
644
645out:
ed878458 646 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 647 return err;
648}
649
650int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
651{
652 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
653}
654
655int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
656{
657 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
658}
659
660int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
661{
662 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
663}
664
665int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
666{
ed878458 667 struct mthca_mailbox *mailbox;
1da177e4 668 u32 *outbox;
1da177e4
LT		 669 int err = 0;
670 u8 lg;
671
672#define QUERY_FW_OUT_SIZE 0x100
673#define QUERY_FW_VER_OFFSET 0x00
674#define QUERY_FW_MAX_CMD_OFFSET 0x0f
675#define QUERY_FW_ERR_START_OFFSET 0x30
676#define QUERY_FW_ERR_SIZE_OFFSET 0x38
677
678#define QUERY_FW_START_OFFSET 0x20
679#define QUERY_FW_END_OFFSET 0x28
680
681#define QUERY_FW_SIZE_OFFSET 0x00
682#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
683#define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
684#define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
685
ed878458
RD		 686 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
687 if (IS_ERR(mailbox))
688 return PTR_ERR(mailbox);
689 outbox = mailbox->buf;
1da177e4 690
ed878458 691 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
1da177e4
LT		 692 CMD_TIME_CLASS_A, status);
693
694 if (err)
695 goto out;
696
697 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
698 /*
699 * FW subminor version is at more signifant bits than minor
700 * version, so swap here.
701 */
702 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
703 ((dev->fw_ver & 0xffff0000ull) >> 16) |
704 ((dev->fw_ver & 0x0000ffffull) << 16);
705
706 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
707 dev->cmd.max_cmds = 1 << lg;
708
709 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
710 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
711
d10ddbf6 712 if (mthca_is_memfree(dev)) {
1da177e4
LT		 713 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
714 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
715 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
716 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
717 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
718
719 /*
720 * Arbel page size is always 4 KB; round up number of
721 * system pages needed.
722 */
723 dev->fw.arbel.fw_pages =
724 (dev->fw.arbel.fw_pages + (1 << (PAGE_SHIFT - 12)) - 1) >>
725 (PAGE_SHIFT - 12);
726
727 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
728 (unsigned long long) dev->fw.arbel.clr_int_base,
729 (unsigned long long) dev->fw.arbel.eq_arm_base,
730 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
731 } else {
732 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
733 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
734
735 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
736 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
737 (unsigned long long) dev->fw.tavor.fw_start,
738 (unsigned long long) dev->fw.tavor.fw_end);
739 }
740
741out:
ed878458 742 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 743 return err;
744}
745
746int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
747{
ed878458 748 struct mthca_mailbox *mailbox;
1da177e4
LT		 749 u8 info;
750 u32 *outbox;
1da177e4
LT		 751 int err = 0;
752
753#define ENABLE_LAM_OUT_SIZE 0x100
754#define ENABLE_LAM_START_OFFSET 0x00
755#define ENABLE_LAM_END_OFFSET 0x08
756#define ENABLE_LAM_INFO_OFFSET 0x13
757
758#define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
759#define ENABLE_LAM_INFO_ECC_MASK 0x3
760
ed878458
RD		 761 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
762 if (IS_ERR(mailbox))
763 return PTR_ERR(mailbox);
764 outbox = mailbox->buf;
1da177e4 765
ed878458 766 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
1da177e4
LT		 767 CMD_TIME_CLASS_C, status);
768
769 if (err)
770 goto out;
771
772 if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
773 goto out;
774
775 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
776 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
777 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
778
779 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
780 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
781 mthca_info(dev, "FW reports that HCA-attached memory "
782 "is %s hidden; does not match PCI config\n",
783 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
784 "" : "not");
785 }
786 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
787 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
788
789 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
790 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
791 (unsigned long long) dev->ddr_start,
792 (unsigned long long) dev->ddr_end);
793
794out:
ed878458 795 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 796 return err;
797}
798
799int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
800{
801 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
802}
803
804int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
805{
ed878458 806 struct mthca_mailbox *mailbox;
1da177e4
LT		 807 u8 info;
808 u32 *outbox;
1da177e4
LT		 809 int err = 0;
810
811#define QUERY_DDR_OUT_SIZE 0x100
812#define QUERY_DDR_START_OFFSET 0x00
813#define QUERY_DDR_END_OFFSET 0x08
814#define QUERY_DDR_INFO_OFFSET 0x13
815
816#define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
817#define QUERY_DDR_INFO_ECC_MASK 0x3
818
ed878458
RD		 819 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
820 if (IS_ERR(mailbox))
821 return PTR_ERR(mailbox);
822 outbox = mailbox->buf;
1da177e4 823
ed878458 824 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
1da177e4
LT		 825 CMD_TIME_CLASS_A, status);
826
827 if (err)
828 goto out;
829
830 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
831 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
832 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
833
834 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
835 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
836 mthca_info(dev, "FW reports that HCA-attached memory "
837 "is %s hidden; does not match PCI config\n",
838 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
839 "" : "not");
840 }
841 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
842 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
843
844 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
845 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
846 (unsigned long long) dev->ddr_start,
847 (unsigned long long) dev->ddr_end);
848
849out:
ed878458 850 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 851 return err;
852}
853
854int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
855 struct mthca_dev_lim *dev_lim, u8 *status)
856{
ed878458 857 struct mthca_mailbox *mailbox;
1da177e4 858 u32 *outbox;
1da177e4
LT		 859 u8 field;
860 u16 size;
861 int err;
862
863#define QUERY_DEV_LIM_OUT_SIZE 0x100
864#define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
865#define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
866#define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
867#define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
868#define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
869#define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
870#define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
871#define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
872#define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
873#define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
874#define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
875#define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
876#define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
877#define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
878#define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
879#define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
880#define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
881#define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
882#define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
883#define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
884#define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
885#define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
886#define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
887#define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
888#define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
889#define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
890#define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
891#define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
892#define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
893#define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
894#define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
895#define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
896#define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
897#define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
898#define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
899#define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
900#define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
901#define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
902#define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
903#define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
904#define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
905#define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
906#define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
907#define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
908#define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
909#define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
910#define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
911#define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
912#define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
913#define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
914#define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
915#define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
916#define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
917#define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
918#define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
919#define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
920#define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
921#define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
922
ed878458
RD		 923 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
924 if (IS_ERR(mailbox))
925 return PTR_ERR(mailbox);
926 outbox = mailbox->buf;
1da177e4 927
ed878458 928 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1da177e4
LT		 929 CMD_TIME_CLASS_A, status);
930
931 if (err)
932 goto out;
933
934 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
935 dev_lim->max_srq_sz = 1 << field;
936 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
937 dev_lim->max_qp_sz = 1 << field;
938 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
939 dev_lim->reserved_qps = 1 << (field & 0xf);
940 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
941 dev_lim->max_qps = 1 << (field & 0x1f);
942 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
943 dev_lim->reserved_srqs = 1 << (field >> 4);
944 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
945 dev_lim->max_srqs = 1 << (field & 0x1f);
946 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
947 dev_lim->reserved_eecs = 1 << (field & 0xf);
948 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
949 dev_lim->max_eecs = 1 << (field & 0x1f);
950 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
951 dev_lim->max_cq_sz = 1 << field;
952 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
953 dev_lim->reserved_cqs = 1 << (field & 0xf);
954 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
955 dev_lim->max_cqs = 1 << (field & 0x1f);
956 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
957 dev_lim->max_mpts = 1 << (field & 0x3f);
958 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
959 dev_lim->reserved_eqs = 1 << (field & 0xf);
960 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
961 dev_lim->max_eqs = 1 << (field & 0x7);
962 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
963 dev_lim->reserved_mtts = 1 << (field >> 4);
964 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
965 dev_lim->max_mrw_sz = 1 << field;
966 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
967 dev_lim->reserved_mrws = 1 << (field & 0xf);
968 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
969 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
970 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
971 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
972 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
973 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
974 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
975 dev_lim->max_rdma_global = 1 << (field & 0x3f);
976 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
977 dev_lim->local_ca_ack_delay = field & 0x1f;
978 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
979 dev_lim->max_mtu = field >> 4;
980 dev_lim->max_port_width = field & 0xf;
981 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
982 dev_lim->max_vl = field >> 4;
983 dev_lim->num_ports = field & 0xf;
984 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
985 dev_lim->max_gids = 1 << (field & 0xf);
986 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
987 dev_lim->max_pkeys = 1 << (field & 0xf);
988 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
989 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
990 dev_lim->reserved_uars = field >> 4;
991 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
992 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
993 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
994 dev_lim->min_page_sz = 1 << field;
995 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
996 dev_lim->max_sg = field;
997
998 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
999 dev_lim->max_desc_sz = size;
1000
1001 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1002 dev_lim->max_qp_per_mcg = 1 << field;
1003 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1004 dev_lim->reserved_mgms = field & 0xf;
1005 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1006 dev_lim->max_mcgs = 1 << field;
1007 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1008 dev_lim->reserved_pds = field >> 4;
1009 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1010 dev_lim->max_pds = 1 << (field & 0x3f);
1011 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1012 dev_lim->reserved_rdds = field >> 4;
1013 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1014 dev_lim->max_rdds = 1 << (field & 0x3f);
1015
1016 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1017 dev_lim->eec_entry_sz = size;
1018 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1019 dev_lim->qpc_entry_sz = size;
1020 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1021 dev_lim->eeec_entry_sz = size;
1022 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1023 dev_lim->eqpc_entry_sz = size;
1024 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1025 dev_lim->eqc_entry_sz = size;
1026 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1027 dev_lim->cqc_entry_sz = size;
1028 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1029 dev_lim->srq_entry_sz = size;
1030 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1031 dev_lim->uar_scratch_entry_sz = size;
1032
1033 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1034 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1035 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1036 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1037 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1038 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1039 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1040 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1041 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1042 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1043 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1044 dev_lim->max_pds, dev_lim->reserved_mgms);
1045
1046 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1047
d10ddbf6 1048 if (mthca_is_memfree(dev)) {
1da177e4
LT		 1049 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1050 dev_lim->hca.arbel.resize_srq = field & 1;
8cf2daf3
RD		 1051 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1052 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1da177e4
LT		 1053 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1054 dev_lim->mpt_entry_sz = size;
1055 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1056 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1057 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1058 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1059 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1060 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1061 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1062 dev_lim->hca.arbel.lam_required = field & 1;
1063 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1064 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1065
1066 if (dev_lim->hca.arbel.bmme_flags & 1)
1067 mthca_dbg(dev, "Base MM extensions: yes "
1068 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1069 dev_lim->hca.arbel.bmme_flags,
1070 dev_lim->hca.arbel.max_pbl_sz,
1071 dev_lim->hca.arbel.reserved_lkey);
1072 else
1073 mthca_dbg(dev, "Base MM extensions: no\n");
1074
1075 mthca_dbg(dev, "Max ICM size %lld MB\n",
1076 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1077 } else {
1078 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1079 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1da177e4
LT		 1080 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1081 }
1082
1083out:
ed878458 1084 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1085 return err;
1086}
1087
2e8b981c
MT		 1088static void get_board_id(void *vsd, char *board_id)
1089{
1090 int i;
1091
1092#define VSD_OFFSET_SIG1 0x00
1093#define VSD_OFFSET_SIG2 0xde
1094#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1095#define VSD_OFFSET_TS_BOARD_ID 0x20
1096
1097#define VSD_SIGNATURE_TOPSPIN 0x5ad
1098
1099 memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1100
1101 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1102 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1103 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1104 } else {
1105 /*
1106 * The board ID is a string but the firmware byte
1107 * swaps each 4-byte word before passing it back to
1108 * us. Therefore we need to swab it before printing.
1109 */
1110 for (i = 0; i < 4; ++i)
1111 ((u32 *) board_id)[i] =
1112 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1113 }
1114}
1115
1da177e4
LT		 1116int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1117 struct mthca_adapter *adapter, u8 *status)
1118{
ed878458 1119 struct mthca_mailbox *mailbox;
1da177e4 1120 u32 *outbox;
1da177e4
LT		 1121 int err;
1122
1123#define QUERY_ADAPTER_OUT_SIZE 0x100
1124#define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1125#define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1126#define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1127#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
2e8b981c 1128#define QUERY_ADAPTER_VSD_OFFSET 0x20
1da177e4 1129
ed878458
RD		 1130 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1131 if (IS_ERR(mailbox))
1132 return PTR_ERR(mailbox);
1133 outbox = mailbox->buf;
1da177e4 1134
ed878458 1135 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1da177e4
LT		 1136 CMD_TIME_CLASS_A, status);
1137
1138 if (err)
1139 goto out;
1140
ed878458
RD		 1141 MTHCA_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET);
1142 MTHCA_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET);
1da177e4 1143 MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
ed878458 1144 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1da177e4 1145
2e8b981c
MT		 1146 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1147 adapter->board_id);
1148
1da177e4 1149out:
ed878458 1150 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1151 return err;
1152}
1153
1154int mthca_INIT_HCA(struct mthca_dev *dev,
1155 struct mthca_init_hca_param *param,
1156 u8 *status)
1157{
ed878458 1158 struct mthca_mailbox *mailbox;
97f52eb4 1159 __be32 *inbox;
1da177e4
LT		 1160 int err;
1161
1162#define INIT_HCA_IN_SIZE 0x200
1163#define INIT_HCA_FLAGS_OFFSET 0x014
1164#define INIT_HCA_QPC_OFFSET 0x020
1165#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1166#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1167#define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1168#define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1169#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1170#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1171#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1172#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1173#define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1174#define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1175#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1176#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1177#define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1178#define INIT_HCA_UDAV_OFFSET 0x0b0
1179#define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1180#define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1181#define INIT_HCA_MCAST_OFFSET 0x0c0
1182#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1183#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1184#define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1185#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1186#define INIT_HCA_TPT_OFFSET 0x0f0
1187#define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1188#define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1189#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1190#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1191#define INIT_HCA_UAR_OFFSET 0x120
1192#define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1193#define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1194#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1195#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1196#define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1197#define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1198
ed878458
RD		 1199 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1200 if (IS_ERR(mailbox))
1201 return PTR_ERR(mailbox);
1202 inbox = mailbox->buf;
1da177e4
LT		 1203
1204 memset(inbox, 0, INIT_HCA_IN_SIZE);
1205
1206#if defined(__LITTLE_ENDIAN)
1207 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1208#elif defined(__BIG_ENDIAN)
1209 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1210#else
1211#error Host endianness not defined
1212#endif
1213 /* Check port for UD address vector: */
1214 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1215
1216 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1217
1218 /* QPC/EEC/CQC/EQC/RDB attributes */
1219
1220 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1221 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1222 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1223 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1224 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1225 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1226 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1227 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1228 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1229 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1230 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1231 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1232 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1233
1234 /* UD AV attributes */
1235
1236 /* multicast attributes */
1237
1238 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1239 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1240 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1241 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1242
1243 /* TPT attributes */
1244
1245 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
d10ddbf6 1246 if (!mthca_is_memfree(dev))
1da177e4
LT		 1247 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1248 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1249 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1250
1251 /* UAR attributes */
1252 {
1253 u8 uar_page_sz = PAGE_SHIFT - 12;
1254 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1255 }
1256
1257 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1258
d10ddbf6 1259 if (mthca_is_memfree(dev)) {
1da177e4
LT		 1260 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1261 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1262 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1263 }
1264
ed878458 1265 err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
1da177e4 1266
ed878458 1267 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1268 return err;
1269}
1270
1271int mthca_INIT_IB(struct mthca_dev *dev,
1272 struct mthca_init_ib_param *param,
1273 int port, u8 *status)
1274{
ed878458 1275 struct mthca_mailbox *mailbox;
1da177e4 1276 u32 *inbox;
1da177e4
LT		 1277 int err;
1278 u32 flags;
1279
1280#define INIT_IB_IN_SIZE 56
1281#define INIT_IB_FLAGS_OFFSET 0x00
1282#define INIT_IB_FLAG_SIG (1 << 18)
1283#define INIT_IB_FLAG_NG (1 << 17)
1284#define INIT_IB_FLAG_G0 (1 << 16)
1285#define INIT_IB_FLAG_1X (1 << 8)
1286#define INIT_IB_FLAG_4X (1 << 9)
1287#define INIT_IB_FLAG_12X (1 << 11)
1288#define INIT_IB_VL_SHIFT 4
1289#define INIT_IB_MTU_SHIFT 12
1290#define INIT_IB_MAX_GID_OFFSET 0x06
1291#define INIT_IB_MAX_PKEY_OFFSET 0x0a
1292#define INIT_IB_GUID0_OFFSET 0x10
1293#define INIT_IB_NODE_GUID_OFFSET 0x18
1294#define INIT_IB_SI_GUID_OFFSET 0x20
1295
ed878458
RD		 1296 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1297 if (IS_ERR(mailbox))
1298 return PTR_ERR(mailbox);
1299 inbox = mailbox->buf;
1da177e4
LT		 1300
1301 memset(inbox, 0, INIT_IB_IN_SIZE);
1302
1303 flags = 0;
1304 flags |= param->enable_1x ? INIT_IB_FLAG_1X : 0;
1305 flags |= param->enable_4x ? INIT_IB_FLAG_4X : 0;
1306 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1307 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1308 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1309 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1310 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1311 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1312
1313 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1314 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1315 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1316 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1317 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1318
ed878458 1319 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1da177e4
LT		 1320 CMD_TIME_CLASS_A, status);
1321
ed878458 1322 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1323 return err;
1324}
1325
1326int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1327{
1328 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
1329}
1330
1331int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1332{
1333 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
1334}
1335
1336int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1337 int port, u8 *status)
1338{
ed878458 1339 struct mthca_mailbox *mailbox;
1da177e4 1340 u32 *inbox;
1da177e4
LT		 1341 int err;
1342 u32 flags = 0;
1343
1344#define SET_IB_IN_SIZE 0x40
1345#define SET_IB_FLAGS_OFFSET 0x00
1346#define SET_IB_FLAG_SIG (1 << 18)
1347#define SET_IB_FLAG_RQK (1 << 0)
1348#define SET_IB_CAP_MASK_OFFSET 0x04
1349#define SET_IB_SI_GUID_OFFSET 0x08
1350
ed878458
RD		 1351 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1352 if (IS_ERR(mailbox))
1353 return PTR_ERR(mailbox);
1354 inbox = mailbox->buf;
1da177e4
LT		 1355
1356 memset(inbox, 0, SET_IB_IN_SIZE);
1357
1358 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1359 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1360 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1361
1362 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1363 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1364
ed878458 1365 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1da177e4
LT		 1366 CMD_TIME_CLASS_B, status);
1367
ed878458 1368 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1369 return err;
1370}
1371
1372int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1373{
1374 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1375}
1376
1377int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1378{
ed878458 1379 struct mthca_mailbox *mailbox;
97f52eb4 1380 __be64 *inbox;
1da177e4
LT		 1381 int err;
1382
ed878458
RD		 1383 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1384 if (IS_ERR(mailbox))
1385 return PTR_ERR(mailbox);
1386 inbox = mailbox->buf;
1da177e4
LT		 1387
1388 inbox[0] = cpu_to_be64(virt);
1389 inbox[1] = cpu_to_be64(dma_addr);
1390
ed878458
RD		 1391 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1392 CMD_TIME_CLASS_B, status);
1da177e4 1393
ed878458 1394 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1395
1396 if (!err)
6bd6228e
RD		 1397 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1398 (unsigned long long) dma_addr, (unsigned long long) virt);
1da177e4
LT		 1399
1400 return err;
1401}
1402
1403int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1404{
1405 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1406 page_count, (unsigned long long) virt);
1407
1408 return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1409}
1410
1411int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1412{
1413 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1414}
1415
1416int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1417{
1418 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1419}
1420
1421int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1422 u8 *status)
1423{
1424 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1425 CMD_TIME_CLASS_A, status);
1426
1427 if (ret || status)
1428 return ret;
1429
1430 /*
1431 * Arbel page size is always 4 KB; round up number of system
1432 * pages needed.
1433 */
1434 *aux_pages = (*aux_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> (PAGE_SHIFT - 12);
1435
1436 return 0;
1437}
1438
ed878458 1439int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1440 int mpt_index, u8 *status)
1441{
ed878458
RD		 1442 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1443 CMD_TIME_CLASS_B, status);
1da177e4
LT		 1444}
1445
ed878458 1446int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1447 int mpt_index, u8 *status)
1448{
ed878458
RD		 1449 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1450 !mailbox, CMD_HW2SW_MPT,
1451 CMD_TIME_CLASS_B, status);
1da177e4
LT		 1452}
1453
ed878458 1454int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1455 int num_mtt, u8 *status)
1456{
ed878458
RD		 1457 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1458 CMD_TIME_CLASS_B, status);
1da177e4
LT		 1459}
1460
b8ca06f6
MT		 1461int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1462{
1463 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1464}
1465
1da177e4
LT		 1466int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1467 int eq_num, u8 *status)
1468{
1469 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1470 unmap ? "Clearing" : "Setting",
1471 (unsigned long long) event_mask, eq_num);
1472 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1473 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1474}
1475
ed878458 1476int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1477 int eq_num, u8 *status)
1478{
ed878458
RD		 1479 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1480 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1481}
1482
ed878458 1483int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1484 int eq_num, u8 *status)
1485{
ed878458
RD		 1486 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1487 CMD_HW2SW_EQ,
1488 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1489}
1490
ed878458 1491int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1492 int cq_num, u8 *status)
1493{
ed878458 1494 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1da177e4 1495 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1496}
1497
ed878458 1498int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1499 int cq_num, u8 *status)
1500{
ed878458
RD		 1501 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1502 CMD_HW2SW_CQ,
1503 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1504}
1505
1506int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
ed878458 1507 int is_ee, struct mthca_mailbox *mailbox, u32 optmask,
1da177e4
LT		 1508 u8 *status)
1509{
1510 static const u16 op[] = {
1511 [MTHCA_TRANS_RST2INIT] = CMD_RST2INIT_QPEE,
1512 [MTHCA_TRANS_INIT2INIT] = CMD_INIT2INIT_QPEE,
1513 [MTHCA_TRANS_INIT2RTR] = CMD_INIT2RTR_QPEE,
1514 [MTHCA_TRANS_RTR2RTS] = CMD_RTR2RTS_QPEE,
1515 [MTHCA_TRANS_RTS2RTS] = CMD_RTS2RTS_QPEE,
1516 [MTHCA_TRANS_SQERR2RTS] = CMD_SQERR2RTS_QPEE,
1517 [MTHCA_TRANS_ANY2ERR] = CMD_2ERR_QPEE,
1518 [MTHCA_TRANS_RTS2SQD] = CMD_RTS2SQD_QPEE,
1519 [MTHCA_TRANS_SQD2SQD] = CMD_SQD2SQD_QPEE,
1520 [MTHCA_TRANS_SQD2RTS] = CMD_SQD2RTS_QPEE,
1521 [MTHCA_TRANS_ANY2RST] = CMD_ERR2RST_QPEE
1522 };
1523 u8 op_mod = 0;
ed878458 1524 int my_mailbox = 0;
1da177e4
LT		 1525 int err;
1526
1527 if (trans < 0 || trans >= ARRAY_SIZE(op))
1528 return -EINVAL;
1529
1530 if (trans == MTHCA_TRANS_ANY2RST) {
1da177e4
LT		 1531 op_mod = 3; /* don't write outbox, any->reset */
1532
1533 /* For debugging */
ed878458
RD		 1534 if (!mailbox) {
1535 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1536 if (!IS_ERR(mailbox)) {
1537 my_mailbox = 1;
1538 op_mod = 2; /* write outbox, any->reset */
1539 } else
1540 mailbox = NULL;
1541 }
1da177e4 1542 } else {
1da177e4
LT		 1543 if (0) {
1544 int i;
1545 mthca_dbg(dev, "Dumping QP context:\n");
ed878458 1546 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1da177e4
LT		 1547 for (i = 0; i < 0x100 / 4; ++i) {
1548 if (i % 8 == 0)
1549 printk(" [%02x] ", i * 4);
ed878458 1550 printk(" %08x",
97f52eb4 1551 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1da177e4
LT		 1552 if ((i + 1) % 8 == 0)
1553 printk("\n");
1554 }
1555 }
1556 }
1557
1558 if (trans == MTHCA_TRANS_ANY2RST) {
ed878458
RD		 1559 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1560 (!!is_ee << 24) | num, op_mod,
1561 op[trans], CMD_TIME_CLASS_C, status);
1da177e4 1562
ed878458 1563 if (0 && mailbox) {
1da177e4
LT		 1564 int i;
1565 mthca_dbg(dev, "Dumping QP context:\n");
ed878458 1566 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1da177e4
LT		 1567 for (i = 0; i < 0x100 / 4; ++i) {
1568 if (i % 8 == 0)
1569 printk("[%02x] ", i * 4);
ed878458 1570 printk(" %08x",
97f52eb4 1571 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1da177e4
LT		 1572 if ((i + 1) % 8 == 0)
1573 printk("\n");
1574 }
1575 }
1576
1577 } else
ed878458 1578 err = mthca_cmd(dev, mailbox->dma, (!!is_ee << 24) | num,
1da177e4
LT		 1579 op_mod, op[trans], CMD_TIME_CLASS_C, status);
1580
ed878458
RD		 1581 if (my_mailbox)
1582 mthca_free_mailbox(dev, mailbox);
1583
1da177e4
LT		 1584 return err;
1585}
1586
1587int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
ed878458 1588 struct mthca_mailbox *mailbox, u8 *status)
1da177e4 1589{
ed878458
RD		 1590 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1591 CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1da177e4
LT		 1592}
1593
1594int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1595 u8 *status)
1596{
1597 u8 op_mod;
1598
1599 switch (type) {
1600 case IB_QPT_SMI:
1601 op_mod = 0;
1602 break;
1603 case IB_QPT_GSI:
1604 op_mod = 1;
1605 break;
1606 case IB_QPT_RAW_IPV6:
1607 op_mod = 2;
1608 break;
1609 case IB_QPT_RAW_ETY:
1610 op_mod = 3;
1611 break;
1612 default:
1613 return -EINVAL;
1614 }
1615
1616 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1617 CMD_TIME_CLASS_B, status);
1618}
1619
1620int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
ed878458 1621 int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1da177e4
LT		 1622 void *in_mad, void *response_mad, u8 *status)
1623{
ed878458
RD		 1624 struct mthca_mailbox *inmailbox, *outmailbox;
1625 void *inbox;
1da177e4
LT		 1626 int err;
1627 u32 in_modifier = port;
1628 u8 op_modifier = 0;
1629
1630#define MAD_IFC_BOX_SIZE 0x400
1631#define MAD_IFC_MY_QPN_OFFSET 0x100
1632#define MAD_IFC_RQPN_OFFSET 0x104
1633#define MAD_IFC_SL_OFFSET 0x108
1634#define MAD_IFC_G_PATH_OFFSET 0x109
1635#define MAD_IFC_RLID_OFFSET 0x10a
1636#define MAD_IFC_PKEY_OFFSET 0x10e
1637#define MAD_IFC_GRH_OFFSET 0x140
1638
ed878458
RD		 1639 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1640 if (IS_ERR(inmailbox))
1641 return PTR_ERR(inmailbox);
1642 inbox = inmailbox->buf;
1643
1644 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1645 if (IS_ERR(outmailbox)) {
1646 mthca_free_mailbox(dev, inmailbox);
1647 return PTR_ERR(outmailbox);
1648 }
1da177e4 1649
ed878458 1650 memcpy(inbox, in_mad, 256);
1da177e4
LT		 1651
1652 /*
1653 * Key check traps can't be generated unless we have in_wc to
1654 * tell us where to send the trap.
1655 */
1656 if (ignore_mkey || !in_wc)
1657 op_modifier |= 0x1;
1658 if (ignore_bkey || !in_wc)
1659 op_modifier |= 0x2;
1660
1661 if (in_wc) {
1662 u8 val;
1663
ed878458 1664 memset(inbox + 256, 0, 256);
1da177e4 1665
ed878458
RD		 1666 MTHCA_PUT(inbox, in_wc->qp_num, MAD_IFC_MY_QPN_OFFSET);
1667 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1da177e4
LT		 1668
1669 val = in_wc->sl << 4;
ed878458 1670 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
1da177e4
LT		 1671
1672 val = in_wc->dlid_path_bits |
1673 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
ed878458 1674 MTHCA_PUT(inbox, val, MAD_IFC_GRH_OFFSET);
1da177e4 1675
ed878458
RD		 1676 MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET);
1677 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1da177e4
LT		 1678
1679 if (in_grh)
ed878458 1680 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1da177e4
LT		 1681
1682 op_modifier |= 0x10;
1683
1684 in_modifier |= in_wc->slid << 16;
1685 }
1686
ed878458
RD		 1687 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1688 in_modifier, op_modifier,
1da177e4
LT		 1689 CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1690
1691 if (!err && !*status)
ed878458 1692 memcpy(response_mad, outmailbox->buf, 256);
1da177e4 1693
ed878458
RD		 1694 mthca_free_mailbox(dev, inmailbox);
1695 mthca_free_mailbox(dev, outmailbox);
1da177e4
LT		 1696 return err;
1697}
1698
ed878458
RD		 1699int mthca_READ_MGM(struct mthca_dev *dev, int index,
1700 struct mthca_mailbox *mailbox, u8 *status)
1da177e4 1701{
ed878458
RD		 1702 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1703 CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1da177e4
LT		 1704}
1705
ed878458
RD		 1706int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1707 struct mthca_mailbox *mailbox, u8 *status)
1da177e4 1708{
ed878458
RD		 1709 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1710 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1711}
1712
ed878458
RD		 1713int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1714 u16 *hash, u8 *status)
1da177e4 1715{
1da177e4
LT		 1716 u64 imm;
1717 int err;
1718
ed878458 1719 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1da177e4 1720 CMD_TIME_CLASS_A, status);
1da177e4 1721
ed878458 1722 *hash = imm;
1da177e4
LT		 1723 return err;
1724}
1725
1726int mthca_NOP(struct mthca_dev *dev, u8 *status)
1727{
1728 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1729}
Linux 6.x block layer and io_uring tree(s)