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[linux-2.6-block.git] / drivers / infiniband / hw / mthca / mthca_cmd.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
2a1d9b7f 3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4885bf64 4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
1da177e4
LT		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
1da177e4
LT		 33 */
34
2a214182 35#include <linux/completion.h>
1da177e4
LT		 36#include <linux/pci.h>
37#include <linux/errno.h>
e8edc6e0 38#include <linux/sched.h>
e4dd23d7 39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
1da177e4 41#include <asm/io.h>
a4d61e84 42#include <rdma/ib_mad.h>
1da177e4
LT		 43
44#include "mthca_dev.h"
45#include "mthca_config_reg.h"
46#include "mthca_cmd.h"
47#include "mthca_memfree.h"
48
49#define CMD_POLL_TOKEN 0xffff
50
51enum {
52 HCR_IN_PARAM_OFFSET = 0x00,
53 HCR_IN_MODIFIER_OFFSET = 0x08,
54 HCR_OUT_PARAM_OFFSET = 0x0c,
55 HCR_TOKEN_OFFSET = 0x14,
56 HCR_STATUS_OFFSET = 0x18,
57
58 HCR_OPMOD_SHIFT = 12,
59 HCA_E_BIT = 22,
60 HCR_GO_BIT = 23
61};
62
63enum {
64 /* initialization and general commands */
65 CMD_SYS_EN = 0x1,
66 CMD_SYS_DIS = 0x2,
67 CMD_MAP_FA = 0xfff,
68 CMD_UNMAP_FA = 0xffe,
69 CMD_RUN_FW = 0xff6,
70 CMD_MOD_STAT_CFG = 0x34,
71 CMD_QUERY_DEV_LIM = 0x3,
72 CMD_QUERY_FW = 0x4,
73 CMD_ENABLE_LAM = 0xff8,
74 CMD_DISABLE_LAM = 0xff7,
75 CMD_QUERY_DDR = 0x5,
76 CMD_QUERY_ADAPTER = 0x6,
77 CMD_INIT_HCA = 0x7,
78 CMD_CLOSE_HCA = 0x8,
79 CMD_INIT_IB = 0x9,
80 CMD_CLOSE_IB = 0xa,
81 CMD_QUERY_HCA = 0xb,
82 CMD_SET_IB = 0xc,
83 CMD_ACCESS_DDR = 0x2e,
84 CMD_MAP_ICM = 0xffa,
85 CMD_UNMAP_ICM = 0xff9,
86 CMD_MAP_ICM_AUX = 0xffc,
87 CMD_UNMAP_ICM_AUX = 0xffb,
88 CMD_SET_ICM_SIZE = 0xffd,
89
90 /* TPT commands */
91 CMD_SW2HW_MPT = 0xd,
92 CMD_QUERY_MPT = 0xe,
93 CMD_HW2SW_MPT = 0xf,
94 CMD_READ_MTT = 0x10,
95 CMD_WRITE_MTT = 0x11,
96 CMD_SYNC_TPT = 0x2f,
97
98 /* EQ commands */
99 CMD_MAP_EQ = 0x12,
100 CMD_SW2HW_EQ = 0x13,
101 CMD_HW2SW_EQ = 0x14,
102 CMD_QUERY_EQ = 0x15,
103
104 /* CQ commands */
105 CMD_SW2HW_CQ = 0x16,
106 CMD_HW2SW_CQ = 0x17,
107 CMD_QUERY_CQ = 0x18,
108 CMD_RESIZE_CQ = 0x2c,
109
110 /* SRQ commands */
111 CMD_SW2HW_SRQ = 0x35,
112 CMD_HW2SW_SRQ = 0x36,
113 CMD_QUERY_SRQ = 0x37,
ec34a922 114 CMD_ARM_SRQ = 0x40,
1da177e4
LT		 115
116 /* QP/EE commands */
117 CMD_RST2INIT_QPEE = 0x19,
118 CMD_INIT2RTR_QPEE = 0x1a,
119 CMD_RTR2RTS_QPEE = 0x1b,
120 CMD_RTS2RTS_QPEE = 0x1c,
121 CMD_SQERR2RTS_QPEE = 0x1d,
122 CMD_2ERR_QPEE = 0x1e,
123 CMD_RTS2SQD_QPEE = 0x1f,
124 CMD_SQD2SQD_QPEE = 0x38,
125 CMD_SQD2RTS_QPEE = 0x20,
126 CMD_ERR2RST_QPEE = 0x21,
127 CMD_QUERY_QPEE = 0x22,
128 CMD_INIT2INIT_QPEE = 0x2d,
129 CMD_SUSPEND_QPEE = 0x32,
130 CMD_UNSUSPEND_QPEE = 0x33,
131 /* special QPs and management commands */
132 CMD_CONF_SPECIAL_QP = 0x23,
133 CMD_MAD_IFC = 0x24,
134
135 /* multicast commands */
136 CMD_READ_MGM = 0x25,
137 CMD_WRITE_MGM = 0x26,
138 CMD_MGID_HASH = 0x27,
139
140 /* miscellaneous commands */
141 CMD_DIAG_RPRT = 0x30,
142 CMD_NOP = 0x31,
143
144 /* debug commands */
145 CMD_QUERY_DEBUG_MSG = 0x2a,
146 CMD_SET_DEBUG_MSG = 0x2b,
147};
148
149/*
150 * According to Mellanox code, FW may be starved and never complete
151 * commands. So we can't use strict timeouts described in PRM -- we
152 * just arbitrarily select 60 seconds for now.
153 */
154#if 0
155/*
156 * Round up and add 1 to make sure we get the full wait time (since we
157 * will be starting in the middle of a jiffy)
158 */
159enum {
160 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
161 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
8531f1f1
JM		 162 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1,
163 CMD_TIME_CLASS_D = 60 * HZ
1da177e4
LT		 164};
165#else
166enum {
167 CMD_TIME_CLASS_A = 60 * HZ,
168 CMD_TIME_CLASS_B = 60 * HZ,
8531f1f1
JM		 169 CMD_TIME_CLASS_C = 60 * HZ,
170 CMD_TIME_CLASS_D = 60 * HZ
1da177e4
LT		 171};
172#endif
173
174enum {
175 GO_BIT_TIMEOUT = HZ * 10
176};
177
178struct mthca_cmd_context {
179 struct completion done;
1da177e4
LT		 180 int result;
181 int next;
182 u64 out_param;
183 u16 token;
184 u8 status;
185};
186
1db76c14 187static int fw_cmd_doorbell = 0;
14abdffc
EC		 188module_param(fw_cmd_doorbell, int, 0644);
189MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
190 "(and supported by FW)");
191
1da177e4
LT		 192static inline int go_bit(struct mthca_dev *dev)
193{
194 return readl(dev->hcr + HCR_STATUS_OFFSET) &
195 swab32(1 << HCR_GO_BIT);
196}
197
14abdffc
EC		 198static void mthca_cmd_post_dbell(struct mthca_dev *dev,
199 u64 in_param,
200 u64 out_param,
201 u32 in_modifier,
202 u8 op_modifier,
203 u16 op,
204 u16 token)
1da177e4 205{
14abdffc
EC		 206 void __iomem *ptr = dev->cmd.dbell_map;
207 u16 *offs = dev->cmd.dbell_offsets;
1da177e4 208
14abdffc
EC		 209 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
210 wmb();
211 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
212 wmb();
213 __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
214 wmb();
215 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
216 wmb();
217 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
218 wmb();
219 __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
220 wmb();
221 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
222 (1 << HCA_E_BIT) |
223 (op_modifier << HCR_OPMOD_SHIFT) |
b3999393 224 op), ptr + offs[6]);
14abdffc
EC		 225 wmb();
226 __raw_writel((__force u32) 0, ptr + offs[7]);
227 wmb();
228}
1da177e4 229
14abdffc
EC		 230static int mthca_cmd_post_hcr(struct mthca_dev *dev,
231 u64 in_param,
232 u64 out_param,
233 u32 in_modifier,
234 u8 op_modifier,
235 u16 op,
236 u16 token,
237 int event)
238{
1da177e4
LT		 239 if (event) {
240 unsigned long end = jiffies + GO_BIT_TIMEOUT;
241
242 while (go_bit(dev) && time_before(jiffies, end)) {
243 set_current_state(TASK_RUNNING);
244 schedule();
245 }
246 }
247
14abdffc
EC		 248 if (go_bit(dev))
249 return -EAGAIN;
1da177e4
LT		 250
251 /*
252 * We use writel (instead of something like memcpy_toio)
253 * because writes of less than 32 bits to the HCR don't work
254 * (and some architectures such as ia64 implement memcpy_toio
255 * in terms of writeb).
256 */
97f52eb4
SH		 257 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
258 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
259 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
260 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
261 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
262 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
1da177e4
LT		 263
264 /* __raw_writel may not order writes. */
265 wmb();
266
97f52eb4
SH		 267 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
268 (event ? (1 << HCA_E_BIT) : 0) |
269 (op_modifier << HCR_OPMOD_SHIFT) |
270 op), dev->hcr + 6 * 4);
1da177e4 271
14abdffc
EC		 272 return 0;
273}
274
275static int mthca_cmd_post(struct mthca_dev *dev,
276 u64 in_param,
277 u64 out_param,
278 u32 in_modifier,
279 u8 op_modifier,
280 u16 op,
281 u16 token,
282 int event)
283{
284 int err = 0;
285
286 mutex_lock(&dev->cmd.hcr_mutex);
287
288 if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
289 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
290 op_modifier, op, token);
291 else
292 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
293 op_modifier, op, token, event);
294
76d7cc03
RD		 295 /*
296 * Make sure that our HCR writes don't get mixed in with
297 * writes from another CPU starting a FW command.
298 */
299 mmiowb();
300
fd9cfdd1 301 mutex_unlock(&dev->cmd.hcr_mutex);
1da177e4
LT		 302 return err;
303}
304
cdb73db0
GR		 305
306static int mthca_status_to_errno(u8 status)
307{
308 static const int trans_table[] = {
309 [MTHCA_CMD_STAT_INTERNAL_ERR] = -EIO,
310 [MTHCA_CMD_STAT_BAD_OP] = -EPERM,
311 [MTHCA_CMD_STAT_BAD_PARAM] = -EINVAL,
312 [MTHCA_CMD_STAT_BAD_SYS_STATE] = -ENXIO,
313 [MTHCA_CMD_STAT_BAD_RESOURCE] = -EBADF,
314 [MTHCA_CMD_STAT_RESOURCE_BUSY] = -EBUSY,
315 [MTHCA_CMD_STAT_DDR_MEM_ERR] = -ENOMEM,
316 [MTHCA_CMD_STAT_EXCEED_LIM] = -ENOMEM,
317 [MTHCA_CMD_STAT_BAD_RES_STATE] = -EBADF,
318 [MTHCA_CMD_STAT_BAD_INDEX] = -EBADF,
319 [MTHCA_CMD_STAT_BAD_NVMEM] = -EFAULT,
320 [MTHCA_CMD_STAT_BAD_QPEE_STATE] = -EINVAL,
321 [MTHCA_CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
322 [MTHCA_CMD_STAT_REG_BOUND] = -EBUSY,
323 [MTHCA_CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
324 [MTHCA_CMD_STAT_BAD_PKT] = -EBADMSG,
325 [MTHCA_CMD_STAT_BAD_SIZE] = -ENOMEM,
326 };
327
328 if (status >= ARRAY_SIZE(trans_table) ||
329 (status != MTHCA_CMD_STAT_OK
330 && trans_table[status] == 0))
331 return -EINVAL;
332
333 return trans_table[status];
334}
335
336
1da177e4
LT		 337static int mthca_cmd_poll(struct mthca_dev *dev,
338 u64 in_param,
339 u64 *out_param,
340 int out_is_imm,
341 u32 in_modifier,
342 u8 op_modifier,
343 u16 op,
cdb73db0 344 unsigned long timeout)
1da177e4
LT		 345{
346 int err = 0;
347 unsigned long end;
cdb73db0 348 u8 status;
1da177e4 349
e3aa31c5 350 down(&dev->cmd.poll_sem);
1da177e4
LT		 351
352 err = mthca_cmd_post(dev, in_param,
353 out_param ? *out_param : 0,
354 in_modifier, op_modifier,
355 op, CMD_POLL_TOKEN, 0);
356 if (err)
357 goto out;
358
359 end = timeout + jiffies;
360 while (go_bit(dev) && time_before(jiffies, end)) {
361 set_current_state(TASK_RUNNING);
362 schedule();
363 }
364
365 if (go_bit(dev)) {
366 err = -EBUSY;
367 goto out;
368 }
369
a43402af 370 if (out_is_imm && out_param) {
2fa5e2eb 371 *out_param =
97f52eb4
SH		 372 (u64) be32_to_cpu((__force __be32)
373 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
374 (u64) be32_to_cpu((__force __be32)
375 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
a43402af
LR		 376 } else if (out_is_imm) {
377 err = -EINVAL;
378 goto out;
379 }
1da177e4 380
cdb73db0
GR		 381 status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
382 if (status) {
383 mthca_dbg(dev, "Command %02x completed with status %02x\n",
384 op, status);
385 err = mthca_status_to_errno(status);
386 }
1da177e4
LT		 387
388out:
389 up(&dev->cmd.poll_sem);
390 return err;
391}
392
393void mthca_cmd_event(struct mthca_dev *dev,
394 u16 token,
395 u8 status,
396 u64 out_param)
397{
398 struct mthca_cmd_context *context =
399 &dev->cmd.context[token & dev->cmd.token_mask];
400
401 /* previously timed out command completing at long last */
402 if (token != context->token)
403 return;
404
405 context->result = 0;
406 context->status = status;
407 context->out_param = out_param;
408
1da177e4
LT		 409 complete(&context->done);
410}
411
1da177e4
LT		 412static int mthca_cmd_wait(struct mthca_dev *dev,
413 u64 in_param,
414 u64 *out_param,
415 int out_is_imm,
416 u32 in_modifier,
417 u8 op_modifier,
418 u16 op,
cdb73db0 419 unsigned long timeout)
1da177e4
LT		 420{
421 int err = 0;
422 struct mthca_cmd_context *context;
423
e3aa31c5 424 down(&dev->cmd.event_sem);
1da177e4
LT		 425
426 spin_lock(&dev->cmd.context_lock);
427 BUG_ON(dev->cmd.free_head < 0);
428 context = &dev->cmd.context[dev->cmd.free_head];
c1f74958 429 context->token += dev->cmd.token_mask + 1;
1da177e4
LT		 430 dev->cmd.free_head = context->next;
431 spin_unlock(&dev->cmd.context_lock);
432
433 init_completion(&context->done);
434
435 err = mthca_cmd_post(dev, in_param,
436 out_param ? *out_param : 0,
437 in_modifier, op_modifier,
438 op, context->token, 1);
439 if (err)
440 goto out;
441
e9cd5941
RD		 442 if (!wait_for_completion_timeout(&context->done, timeout)) {
443 err = -EBUSY;
444 goto out;
445 }
1da177e4
LT		 446
447 err = context->result;
448 if (err)
449 goto out;
450
cdb73db0 451 if (context->status) {
1da177e4 452 mthca_dbg(dev, "Command %02x completed with status %02x\n",
cdb73db0
GR		 453 op, context->status);
454 err = mthca_status_to_errno(context->status);
455 }
1da177e4 456
a43402af 457 if (out_is_imm && out_param) {
1da177e4 458 *out_param = context->out_param;
a43402af
LR		 459 } else if (out_is_imm) {
460 err = -EINVAL;
461 goto out;
462 }
1da177e4
LT		 463
464out:
465 spin_lock(&dev->cmd.context_lock);
466 context->next = dev->cmd.free_head;
467 dev->cmd.free_head = context - dev->cmd.context;
468 spin_unlock(&dev->cmd.context_lock);
469
470 up(&dev->cmd.event_sem);
471 return err;
472}
473
474/* Invoke a command with an output mailbox */
475static int mthca_cmd_box(struct mthca_dev *dev,
476 u64 in_param,
477 u64 out_param,
478 u32 in_modifier,
479 u8 op_modifier,
480 u16 op,
cdb73db0 481 unsigned long timeout)
1da177e4 482{
14abdffc 483 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
1da177e4
LT		 484 return mthca_cmd_wait(dev, in_param, &out_param, 0,
485 in_modifier, op_modifier, op,
cdb73db0 486 timeout);
1da177e4
LT		 487 else
488 return mthca_cmd_poll(dev, in_param, &out_param, 0,
489 in_modifier, op_modifier, op,
cdb73db0 490 timeout);
1da177e4
LT		 491}
492
493/* Invoke a command with no output parameter */
494static int mthca_cmd(struct mthca_dev *dev,
495 u64 in_param,
496 u32 in_modifier,
497 u8 op_modifier,
498 u16 op,
cdb73db0 499 unsigned long timeout)
1da177e4
LT		 500{
501 return mthca_cmd_box(dev, in_param, 0, in_modifier,
cdb73db0 502 op_modifier, op, timeout);
1da177e4
LT		 503}
504
505/*
506 * Invoke a command with an immediate output parameter (and copy the
507 * output into the caller's out_param pointer after the command
508 * executes).
509 */
510static int mthca_cmd_imm(struct mthca_dev *dev,
511 u64 in_param,
512 u64 *out_param,
513 u32 in_modifier,
514 u8 op_modifier,
515 u16 op,
cdb73db0 516 unsigned long timeout)
1da177e4 517{
14abdffc 518 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
1da177e4
LT		 519 return mthca_cmd_wait(dev, in_param, out_param, 1,
520 in_modifier, op_modifier, op,
cdb73db0 521 timeout);
1da177e4
LT		 522 else
523 return mthca_cmd_poll(dev, in_param, out_param, 1,
524 in_modifier, op_modifier, op,
cdb73db0 525 timeout);
1da177e4
LT		 526}
527
80fd8238
RD		 528int mthca_cmd_init(struct mthca_dev *dev)
529{
fd9cfdd1 530 mutex_init(&dev->cmd.hcr_mutex);
80fd8238 531 sema_init(&dev->cmd.poll_sem, 1);
14abdffc 532 dev->cmd.flags = 0;
80fd8238
RD		 533
534 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
535 MTHCA_HCR_SIZE);
536 if (!dev->hcr) {
537 mthca_err(dev, "Couldn't map command register.");
538 return -ENOMEM;
539 }
540
11880a55 541 dev->cmd.pool = dma_pool_create("mthca_cmd", &dev->pdev->dev,
ed878458
RD		 542 MTHCA_MAILBOX_SIZE,
543 MTHCA_MAILBOX_SIZE, 0);
544 if (!dev->cmd.pool) {
545 iounmap(dev->hcr);
546 return -ENOMEM;
547 }
548
80fd8238
RD		 549 return 0;
550}
551
552void mthca_cmd_cleanup(struct mthca_dev *dev)
553{
11880a55 554 dma_pool_destroy(dev->cmd.pool);
80fd8238 555 iounmap(dev->hcr);
14abdffc
EC		 556 if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
557 iounmap(dev->cmd.dbell_map);
80fd8238
RD		 558}
559
1da177e4
LT		 560/*
561 * Switch to using events to issue FW commands (should be called after
562 * event queue to command events has been initialized).
563 */
564int mthca_cmd_use_events(struct mthca_dev *dev)
565{
566 int i;
567
6da2ec56
KC		 568 dev->cmd.context = kmalloc_array(dev->cmd.max_cmds,
569 sizeof(struct mthca_cmd_context),
570 GFP_KERNEL);
1da177e4
LT		 571 if (!dev->cmd.context)
572 return -ENOMEM;
573
574 for (i = 0; i < dev->cmd.max_cmds; ++i) {
575 dev->cmd.context[i].token = i;
576 dev->cmd.context[i].next = i + 1;
1da177e4
LT		 577 }
578
579 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
580 dev->cmd.free_head = 0;
581
582 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
583 spin_lock_init(&dev->cmd.context_lock);
584
585 for (dev->cmd.token_mask = 1;
586 dev->cmd.token_mask < dev->cmd.max_cmds;
587 dev->cmd.token_mask <<= 1)
588 ; /* nothing */
589 --dev->cmd.token_mask;
590
14abdffc
EC		 591 dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
592
1da177e4
LT		 593 down(&dev->cmd.poll_sem);
594
595 return 0;
596}
597
598/*
599 * Switch back to polling (used when shutting down the device)
600 */
601void mthca_cmd_use_polling(struct mthca_dev *dev)
602{
603 int i;
604
14abdffc 605 dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
1da177e4
LT		 606
607 for (i = 0; i < dev->cmd.max_cmds; ++i)
608 down(&dev->cmd.event_sem);
609
610 kfree(dev->cmd.context);
611
612 up(&dev->cmd.poll_sem);
613}
614
ed878458 615struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
87b750dc 616 gfp_t gfp_mask)
ed878458
RD		 617{
618 struct mthca_mailbox *mailbox;
619
620 mailbox = kmalloc(sizeof *mailbox, gfp_mask);
621 if (!mailbox)
622 return ERR_PTR(-ENOMEM);
623
11880a55 624 mailbox->buf = dma_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
ed878458
RD		 625 if (!mailbox->buf) {
626 kfree(mailbox);
627 return ERR_PTR(-ENOMEM);
628 }
629
630 return mailbox;
631}
632
633void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
634{
635 if (!mailbox)
636 return;
637
11880a55 638 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
ed878458
RD		 639 kfree(mailbox);
640}
641
cdb73db0 642int mthca_SYS_EN(struct mthca_dev *dev)
1da177e4
LT		 643{
644 u64 out;
645 int ret;
646
cdb73db0 647 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D);
1da177e4 648
cdb73db0 649 if (ret == -ENOMEM)
1da177e4
LT		 650 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
651 "sladdr=%d, SPD source=%s\n",
652 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
653 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
654
655 return ret;
656}
657
cdb73db0 658int mthca_SYS_DIS(struct mthca_dev *dev)
1da177e4 659{
cdb73db0 660 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
1da177e4
LT		 661}
662
663static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
cdb73db0 664 u64 virt)
1da177e4 665{
ed878458 666 struct mthca_mailbox *mailbox;
1da177e4 667 struct mthca_icm_iter iter;
ed878458 668 __be64 *pages;
1da177e4
LT		 669 int lg;
670 int nent = 0;
671 int i;
672 int err = 0;
673 int ts = 0, tc = 0;
674
ed878458
RD		 675 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
676 if (IS_ERR(mailbox))
677 return PTR_ERR(mailbox);
678 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
679 pages = mailbox->buf;
1da177e4
LT		 680
681 for (mthca_icm_first(icm, &iter);
682 !mthca_icm_last(&iter);
683 mthca_icm_next(&iter)) {
684 /*
685 * We have to pass pages that are aligned to their
686 * size, so find the least significant 1 in the
687 * address or size and use that as our log2 size.
688 */
689 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
8d3ef29d
IR		 690 if (lg < MTHCA_ICM_PAGE_SHIFT) {
691 mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
692 MTHCA_ICM_PAGE_SIZE,
1da177e4
LT		 693 (unsigned long long) mthca_icm_addr(&iter),
694 mthca_icm_size(&iter));
695 err = -EINVAL;
696 goto out;
697 }
59f174fa 698 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
1da177e4 699 if (virt != -1) {
ed878458 700 pages[nent * 2] = cpu_to_be64(virt);
62324895 701 virt += 1ULL << lg;
1da177e4
LT		 702 }
703
8d3ef29d
IR		 704 pages[nent * 2 + 1] =
705 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
706 (lg - MTHCA_ICM_PAGE_SHIFT));
1da177e4
LT		 707 ts += 1 << (lg - 10);
708 ++tc;
709
44dd823b 710 if (++nent == MTHCA_MAILBOX_SIZE / 16) {
ed878458 711 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
cdb73db0
GR		 712 CMD_TIME_CLASS_B);
713 if (err)
1da177e4
LT		 714 goto out;
715 nent = 0;
716 }
717 }
718 }
719
720 if (nent)
ed878458 721 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
cdb73db0 722 CMD_TIME_CLASS_B);
1da177e4
LT		 723
724 switch (op) {
725 case CMD_MAP_FA:
726 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
727 break;
728 case CMD_MAP_ICM_AUX:
729 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
730 break;
731 case CMD_MAP_ICM:
732 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
733 tc, ts, (unsigned long long) virt - (ts << 10));
734 break;
735 }
736
737out:
ed878458 738 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 739 return err;
740}
741
cdb73db0 742int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm)
1da177e4 743{
cdb73db0 744 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1);
1da177e4
LT		 745}
746
cdb73db0 747int mthca_UNMAP_FA(struct mthca_dev *dev)
1da177e4 748{
cdb73db0 749 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B);
1da177e4
LT		 750}
751
cdb73db0 752int mthca_RUN_FW(struct mthca_dev *dev)
1da177e4 753{
cdb73db0 754 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A);
1da177e4
LT		 755}
756
14abdffc
EC		 757static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
758{
eb4a7cbf 759 phys_addr_t addr;
14abdffc
EC		 760 u16 max_off = 0;
761 int i;
762
763 for (i = 0; i < 8; ++i)
764 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
765
766 if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
767 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
768 "length 0x%x crosses a page boundary\n",
769 (unsigned long long) base, max_off);
770 return;
771 }
772
773 addr = pci_resource_start(dev->pdev, 2) +
774 ((pci_resource_len(dev->pdev, 2) - 1) & base);
775 dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
776 if (!dev->cmd.dbell_map)
777 return;
778
779 dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
780 mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
781}
782
cdb73db0 783int mthca_QUERY_FW(struct mthca_dev *dev)
1da177e4 784{
ed878458 785 struct mthca_mailbox *mailbox;
1da177e4 786 u32 *outbox;
14abdffc
EC		 787 u64 base;
788 u32 tmp;
1da177e4
LT		 789 int err = 0;
790 u8 lg;
14abdffc 791 int i;
1da177e4
LT		 792
793#define QUERY_FW_OUT_SIZE 0x100
794#define QUERY_FW_VER_OFFSET 0x00
795#define QUERY_FW_MAX_CMD_OFFSET 0x0f
796#define QUERY_FW_ERR_START_OFFSET 0x30
797#define QUERY_FW_ERR_SIZE_OFFSET 0x38
798
14abdffc
EC		 799#define QUERY_FW_CMD_DB_EN_OFFSET 0x10
800#define QUERY_FW_CMD_DB_OFFSET 0x50
801#define QUERY_FW_CMD_DB_BASE 0x60
802
1da177e4
LT		 803#define QUERY_FW_START_OFFSET 0x20
804#define QUERY_FW_END_OFFSET 0x28
805
806#define QUERY_FW_SIZE_OFFSET 0x00
807#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
808#define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
809#define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
810
ed878458
RD		 811 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
812 if (IS_ERR(mailbox))
813 return PTR_ERR(mailbox);
814 outbox = mailbox->buf;
1da177e4 815
ed878458 816 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
cdb73db0 817 CMD_TIME_CLASS_A);
1da177e4
LT		 818
819 if (err)
820 goto out;
821
822 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
823 /*
3e1db334 824 * FW subminor version is at more significant bits than minor
1da177e4
LT		 825 * version, so swap here.
826 */
827 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
828 ((dev->fw_ver & 0xffff0000ull) >> 16) |
829 ((dev->fw_ver & 0x0000ffffull) << 16);
830
8fdf679f
RD		 831 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
832 dev->cmd.max_cmds = 1 << lg;
833
14abdffc
EC		 834 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
835 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
836
3d155f8c
RD		 837 MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
838 MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1da177e4 839
3d155f8c
RD		 840 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
841 (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
1da177e4 842
14abdffc
EC		 843 MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
844 if (tmp & 0x1) {
845 mthca_dbg(dev, "FW supports commands through doorbells\n");
846
847 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
848 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
849 MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
850 QUERY_FW_CMD_DB_OFFSET + (i << 1));
851
852 mthca_setup_cmd_doorbells(dev, base);
853 }
854
d10ddbf6 855 if (mthca_is_memfree(dev)) {
1da177e4
LT		 856 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
857 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
858 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
859 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
860 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
861
862 /*
8d3ef29d
IR		 863 * Round up number of system pages needed in case
864 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1da177e4
LT		 865 */
866 dev->fw.arbel.fw_pages =
8d3ef29d
IR		 867 ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
868 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1da177e4
LT		 869
870 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
871 (unsigned long long) dev->fw.arbel.clr_int_base,
872 (unsigned long long) dev->fw.arbel.eq_arm_base,
873 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
874 } else {
875 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
876 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
877
878 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
879 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
880 (unsigned long long) dev->fw.tavor.fw_start,
881 (unsigned long long) dev->fw.tavor.fw_end);
882 }
883
884out:
ed878458 885 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 886 return err;
887}
888
cdb73db0 889int mthca_ENABLE_LAM(struct mthca_dev *dev)
1da177e4 890{
ed878458 891 struct mthca_mailbox *mailbox;
1da177e4
LT		 892 u8 info;
893 u32 *outbox;
1da177e4
LT		 894 int err = 0;
895
896#define ENABLE_LAM_OUT_SIZE 0x100
897#define ENABLE_LAM_START_OFFSET 0x00
898#define ENABLE_LAM_END_OFFSET 0x08
899#define ENABLE_LAM_INFO_OFFSET 0x13
900
901#define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
902#define ENABLE_LAM_INFO_ECC_MASK 0x3
903
ed878458
RD		 904 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
905 if (IS_ERR(mailbox))
906 return PTR_ERR(mailbox);
907 outbox = mailbox->buf;
1da177e4 908
ed878458 909 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
cdb73db0 910 CMD_TIME_CLASS_C);
1da177e4
LT		 911
912 if (err)
913 goto out;
914
1da177e4
LT		 915 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
916 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
917 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
918
919 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
920 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
921 mthca_info(dev, "FW reports that HCA-attached memory "
922 "is %s hidden; does not match PCI config\n",
923 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
924 "" : "not");
925 }
926 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
927 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
928
929 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
930 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
931 (unsigned long long) dev->ddr_start,
932 (unsigned long long) dev->ddr_end);
933
934out:
ed878458 935 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 936 return err;
937}
938
cdb73db0 939int mthca_DISABLE_LAM(struct mthca_dev *dev)
1da177e4 940{
cdb73db0 941 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
1da177e4
LT		 942}
943
cdb73db0 944int mthca_QUERY_DDR(struct mthca_dev *dev)
1da177e4 945{
ed878458 946 struct mthca_mailbox *mailbox;
1da177e4
LT		 947 u8 info;
948 u32 *outbox;
1da177e4
LT		 949 int err = 0;
950
951#define QUERY_DDR_OUT_SIZE 0x100
952#define QUERY_DDR_START_OFFSET 0x00
953#define QUERY_DDR_END_OFFSET 0x08
954#define QUERY_DDR_INFO_OFFSET 0x13
955
956#define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
957#define QUERY_DDR_INFO_ECC_MASK 0x3
958
ed878458
RD		 959 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
960 if (IS_ERR(mailbox))
961 return PTR_ERR(mailbox);
962 outbox = mailbox->buf;
1da177e4 963
ed878458 964 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
cdb73db0 965 CMD_TIME_CLASS_A);
1da177e4
LT		 966
967 if (err)
968 goto out;
969
970 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
971 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
972 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
973
974 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
975 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
976 mthca_info(dev, "FW reports that HCA-attached memory "
977 "is %s hidden; does not match PCI config\n",
978 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
979 "" : "not");
980 }
981 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
982 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
983
984 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
985 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
986 (unsigned long long) dev->ddr_start,
987 (unsigned long long) dev->ddr_end);
988
989out:
ed878458 990 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 991 return err;
992}
993
994int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
cdb73db0 995 struct mthca_dev_lim *dev_lim)
1da177e4 996{
ed878458 997 struct mthca_mailbox *mailbox;
1da177e4 998 u32 *outbox;
1da177e4
LT		 999 u8 field;
1000 u16 size;
bf6a9e31 1001 u16 stat_rate;
1da177e4
LT		 1002 int err;
1003
1004#define QUERY_DEV_LIM_OUT_SIZE 0x100
1005#define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
1006#define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
1007#define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
1008#define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
1009#define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
1010#define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
1011#define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
1012#define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
1013#define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
1014#define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
1015#define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
1016#define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
1017#define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
1018#define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
1019#define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
1020#define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
1021#define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
1022#define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
1023#define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
1024#define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
1025#define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
1026#define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
1027#define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
1028#define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
1029#define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
1030#define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
1031#define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
bf6a9e31 1032#define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
1da177e4
LT		 1033#define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
1034#define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
1035#define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
1036#define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
1037#define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
1038#define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
1039#define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
1040#define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
1041#define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
1042#define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
1043#define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
1044#define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
1045#define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
1046#define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
1047#define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
1048#define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
1049#define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
1050#define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
1051#define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
1052#define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1053#define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1054#define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1055#define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1056#define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1057#define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1058#define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1059#define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1060#define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1061#define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1062#define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1063#define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1064
ed878458
RD		 1065 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1066 if (IS_ERR(mailbox))
1067 return PTR_ERR(mailbox);
1068 outbox = mailbox->buf;
1da177e4 1069
ed878458 1070 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
cdb73db0 1071 CMD_TIME_CLASS_A);
1da177e4
LT		 1072
1073 if (err)
1074 goto out;
1075
1da177e4
LT		 1076 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1077 dev_lim->reserved_qps = 1 << (field & 0xf);
1078 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1079 dev_lim->max_qps = 1 << (field & 0x1f);
1080 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1081 dev_lim->reserved_srqs = 1 << (field >> 4);
1082 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1083 dev_lim->max_srqs = 1 << (field & 0x1f);
1084 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1085 dev_lim->reserved_eecs = 1 << (field & 0xf);
1086 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1087 dev_lim->max_eecs = 1 << (field & 0x1f);
1088 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1089 dev_lim->max_cq_sz = 1 << field;
1090 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1091 dev_lim->reserved_cqs = 1 << (field & 0xf);
1092 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1093 dev_lim->max_cqs = 1 << (field & 0x1f);
1094 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1095 dev_lim->max_mpts = 1 << (field & 0x3f);
1096 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1097 dev_lim->reserved_eqs = 1 << (field & 0xf);
1098 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1099 dev_lim->max_eqs = 1 << (field & 0x7);
1100 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
c7d204e8
MT		 1101 if (mthca_is_memfree(dev))
1102 dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64),
c1f67a88 1103 dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size;
c7d204e8
MT		 1104 else
1105 dev_lim->reserved_mtts = 1 << (field >> 4);
1da177e4
LT		 1106 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1107 dev_lim->max_mrw_sz = 1 << field;
1108 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1109 dev_lim->reserved_mrws = 1 << (field & 0xf);
1110 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1111 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1112 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1113 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1114 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1115 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1116 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1117 dev_lim->max_rdma_global = 1 << (field & 0x3f);
1118 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1119 dev_lim->local_ca_ack_delay = field & 0x1f;
1120 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1121 dev_lim->max_mtu = field >> 4;
1122 dev_lim->max_port_width = field & 0xf;
1123 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1124 dev_lim->max_vl = field >> 4;
1125 dev_lim->num_ports = field & 0xf;
1126 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1127 dev_lim->max_gids = 1 << (field & 0xf);
bf6a9e31
JM		 1128 MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1129 dev_lim->stat_rate_support = stat_rate;
1da177e4
LT		 1130 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1131 dev_lim->max_pkeys = 1 << (field & 0xf);
1132 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1133 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1134 dev_lim->reserved_uars = field >> 4;
1135 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1136 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1137 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1138 dev_lim->min_page_sz = 1 << field;
1139 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1140 dev_lim->max_sg = field;
1141
1142 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1143 dev_lim->max_desc_sz = size;
1144
1145 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1146 dev_lim->max_qp_per_mcg = 1 << field;
1147 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1148 dev_lim->reserved_mgms = field & 0xf;
1149 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1150 dev_lim->max_mcgs = 1 << field;
1151 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1152 dev_lim->reserved_pds = field >> 4;
1153 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1154 dev_lim->max_pds = 1 << (field & 0x3f);
1155 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1156 dev_lim->reserved_rdds = field >> 4;
1157 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1158 dev_lim->max_rdds = 1 << (field & 0x3f);
1159
1160 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1161 dev_lim->eec_entry_sz = size;
1162 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1163 dev_lim->qpc_entry_sz = size;
1164 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1165 dev_lim->eeec_entry_sz = size;
1166 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1167 dev_lim->eqpc_entry_sz = size;
1168 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1169 dev_lim->eqc_entry_sz = size;
1170 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1171 dev_lim->cqc_entry_sz = size;
1172 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1173 dev_lim->srq_entry_sz = size;
1174 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1175 dev_lim->uar_scratch_entry_sz = size;
1176
d10ddbf6 1177 if (mthca_is_memfree(dev)) {
a3c8ab4f
JM		 1178 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1179 dev_lim->max_srq_sz = 1 << field;
1180 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1181 dev_lim->max_qp_sz = 1 << field;
1da177e4
LT		 1182 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1183 dev_lim->hca.arbel.resize_srq = field & 1;
8cf2daf3
RD		 1184 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1185 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
77369ed3
JM		 1186 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1187 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1da177e4
LT		 1188 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1189 dev_lim->mpt_entry_sz = size;
1190 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1191 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1192 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1193 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1194 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1195 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1196 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1197 dev_lim->hca.arbel.lam_required = field & 1;
1198 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1199 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1200
1201 if (dev_lim->hca.arbel.bmme_flags & 1)
1202 mthca_dbg(dev, "Base MM extensions: yes "
1203 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1204 dev_lim->hca.arbel.bmme_flags,
1205 dev_lim->hca.arbel.max_pbl_sz,
1206 dev_lim->hca.arbel.reserved_lkey);
1207 else
1208 mthca_dbg(dev, "Base MM extensions: no\n");
1209
1210 mthca_dbg(dev, "Max ICM size %lld MB\n",
1211 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1212 } else {
a3c8ab4f
JM		 1213 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1214 dev_lim->max_srq_sz = (1 << field) - 1;
1215 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1216 dev_lim->max_qp_sz = (1 << field) - 1;
1da177e4
LT		 1217 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1218 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1da177e4
LT		 1219 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1220 }
1221
f295c79b
RD		 1222 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1223 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1224 mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1225 dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1226 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1227 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1228 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1229 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1230 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1231 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1232 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1233 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1234 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1235 dev_lim->max_pds, dev_lim->reserved_mgms);
1236 mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1237 dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1238
1239 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1240
1da177e4 1241out:
ed878458 1242 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1243 return err;
1244}
1245
2e8b981c
MT		 1246static void get_board_id(void *vsd, char *board_id)
1247{
1248 int i;
1249
1250#define VSD_OFFSET_SIG1 0x00
1251#define VSD_OFFSET_SIG2 0xde
1252#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1253#define VSD_OFFSET_TS_BOARD_ID 0x20
1254
1255#define VSD_SIGNATURE_TOPSPIN 0x5ad
1256
1257 memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1258
1259 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1260 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1261 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1262 } else {
1263 /*
1264 * The board ID is a string but the firmware byte
1265 * swaps each 4-byte word before passing it back to
1266 * us. Therefore we need to swab it before printing.
1267 */
1268 for (i = 0; i < 4; ++i)
1269 ((u32 *) board_id)[i] =
1270 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1271 }
1272}
1273
1da177e4 1274int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
cdb73db0 1275 struct mthca_adapter *adapter)
1da177e4 1276{
ed878458 1277 struct mthca_mailbox *mailbox;
1da177e4 1278 u32 *outbox;
1da177e4
LT		 1279 int err;
1280
1281#define QUERY_ADAPTER_OUT_SIZE 0x100
1282#define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1283#define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1284#define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1285#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
2e8b981c 1286#define QUERY_ADAPTER_VSD_OFFSET 0x20
1da177e4 1287
ed878458
RD		 1288 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1289 if (IS_ERR(mailbox))
1290 return PTR_ERR(mailbox);
1291 outbox = mailbox->buf;
1da177e4 1292
ed878458 1293 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
cdb73db0 1294 CMD_TIME_CLASS_A);
1da177e4
LT		 1295
1296 if (err)
1297 goto out;
1298
6ccef1de
JM		 1299 if (!mthca_is_memfree(dev)) {
1300 MTHCA_GET(adapter->vendor_id, outbox,
1301 QUERY_ADAPTER_VENDOR_ID_OFFSET);
1302 MTHCA_GET(adapter->device_id, outbox,
1303 QUERY_ADAPTER_DEVICE_ID_OFFSET);
1304 MTHCA_GET(adapter->revision_id, outbox,
1305 QUERY_ADAPTER_REVISION_ID_OFFSET);
1306 }
ed878458 1307 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1da177e4 1308
2e8b981c
MT		 1309 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1310 adapter->board_id);
1311
1da177e4 1312out:
ed878458 1313 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1314 return err;
1315}
1316
1317int mthca_INIT_HCA(struct mthca_dev *dev,
cdb73db0 1318 struct mthca_init_hca_param *param)
1da177e4 1319{
ed878458 1320 struct mthca_mailbox *mailbox;
97f52eb4 1321 __be32 *inbox;
1da177e4
LT		 1322 int err;
1323
1324#define INIT_HCA_IN_SIZE 0x200
651eaac9
EC		 1325#define INIT_HCA_FLAGS1_OFFSET 0x00c
1326#define INIT_HCA_FLAGS2_OFFSET 0x014
1da177e4
LT		 1327#define INIT_HCA_QPC_OFFSET 0x020
1328#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1329#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1330#define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1331#define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1332#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1333#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1334#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1335#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1336#define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1337#define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1338#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1339#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1340#define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1341#define INIT_HCA_UDAV_OFFSET 0x0b0
1342#define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1343#define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1344#define INIT_HCA_MCAST_OFFSET 0x0c0
1345#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1346#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1347#define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1348#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1349#define INIT_HCA_TPT_OFFSET 0x0f0
1350#define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1351#define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1352#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1353#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1354#define INIT_HCA_UAR_OFFSET 0x120
1355#define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1356#define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1357#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1358#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1359#define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1360#define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1361
ed878458
RD		 1362 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1363 if (IS_ERR(mailbox))
1364 return PTR_ERR(mailbox);
1365 inbox = mailbox->buf;
1da177e4
LT		 1366
1367 memset(inbox, 0, INIT_HCA_IN_SIZE);
1368
651eaac9
EC		 1369 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1370 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1371
1da177e4 1372#if defined(__LITTLE_ENDIAN)
651eaac9 1373 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1da177e4 1374#elif defined(__BIG_ENDIAN)
651eaac9 1375 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1da177e4
LT		 1376#else
1377#error Host endianness not defined
1378#endif
1379 /* Check port for UD address vector: */
651eaac9 1380 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1da177e4 1381
680b575f
EC		 1382 /* Enable IPoIB checksumming if we can: */
1383 if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM)
1384 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3);
1385
1da177e4
LT		 1386 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1387
1388 /* QPC/EEC/CQC/EQC/RDB attributes */
1389
1390 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1391 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1392 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1393 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1394 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1395 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1396 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1397 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1398 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1399 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1400 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1401 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1402 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1403
1404 /* UD AV attributes */
1405
1406 /* multicast attributes */
1407
1408 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1409 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1410 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1411 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1412
1413 /* TPT attributes */
1414
1415 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
d10ddbf6 1416 if (!mthca_is_memfree(dev))
1da177e4
LT		 1417 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1418 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1419 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1420
1421 /* UAR attributes */
1422 {
1423 u8 uar_page_sz = PAGE_SHIFT - 12;
1424 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1425 }
1426
1427 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1428
d10ddbf6 1429 if (mthca_is_memfree(dev)) {
1da177e4
LT		 1430 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1431 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1432 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1433 }
1434
cdb73db0
GR		 1435 err = mthca_cmd(dev, mailbox->dma, 0, 0,
1436 CMD_INIT_HCA, CMD_TIME_CLASS_D);
1da177e4 1437
ed878458 1438 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1439 return err;
1440}
1441
1442int mthca_INIT_IB(struct mthca_dev *dev,
1443 struct mthca_init_ib_param *param,
cdb73db0 1444 int port)
1da177e4 1445{
ed878458 1446 struct mthca_mailbox *mailbox;
1da177e4 1447 u32 *inbox;
1da177e4
LT		 1448 int err;
1449 u32 flags;
1450
1451#define INIT_IB_IN_SIZE 56
1452#define INIT_IB_FLAGS_OFFSET 0x00
1453#define INIT_IB_FLAG_SIG (1 << 18)
1454#define INIT_IB_FLAG_NG (1 << 17)
1455#define INIT_IB_FLAG_G0 (1 << 16)
1da177e4 1456#define INIT_IB_VL_SHIFT 4
da6561c2 1457#define INIT_IB_PORT_WIDTH_SHIFT 8
1da177e4
LT		 1458#define INIT_IB_MTU_SHIFT 12
1459#define INIT_IB_MAX_GID_OFFSET 0x06
1460#define INIT_IB_MAX_PKEY_OFFSET 0x0a
1461#define INIT_IB_GUID0_OFFSET 0x10
1462#define INIT_IB_NODE_GUID_OFFSET 0x18
1463#define INIT_IB_SI_GUID_OFFSET 0x20
1464
ed878458
RD		 1465 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1466 if (IS_ERR(mailbox))
1467 return PTR_ERR(mailbox);
1468 inbox = mailbox->buf;
1da177e4
LT		 1469
1470 memset(inbox, 0, INIT_IB_IN_SIZE);
1471
1472 flags = 0;
1da177e4
LT		 1473 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1474 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1475 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1476 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
da6561c2 1477 flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1da177e4
LT		 1478 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1479 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1480
1481 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1482 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1483 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1484 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1485 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1486
ed878458 1487 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
cdb73db0 1488 CMD_TIME_CLASS_A);
1da177e4 1489
ed878458 1490 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1491 return err;
1492}
1493
cdb73db0 1494int mthca_CLOSE_IB(struct mthca_dev *dev, int port)
1da177e4 1495{
cdb73db0 1496 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A);
1da177e4
LT		 1497}
1498
cdb73db0 1499int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic)
1da177e4 1500{
cdb73db0 1501 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C);
1da177e4
LT		 1502}
1503
1504int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
cdb73db0 1505 int port)
1da177e4 1506{
ed878458 1507 struct mthca_mailbox *mailbox;
1da177e4 1508 u32 *inbox;
1da177e4
LT		 1509 int err;
1510 u32 flags = 0;
1511
1512#define SET_IB_IN_SIZE 0x40
1513#define SET_IB_FLAGS_OFFSET 0x00
1514#define SET_IB_FLAG_SIG (1 << 18)
1515#define SET_IB_FLAG_RQK (1 << 0)
1516#define SET_IB_CAP_MASK_OFFSET 0x04
1517#define SET_IB_SI_GUID_OFFSET 0x08
1518
ed878458
RD		 1519 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1520 if (IS_ERR(mailbox))
1521 return PTR_ERR(mailbox);
1522 inbox = mailbox->buf;
1da177e4
LT		 1523
1524 memset(inbox, 0, SET_IB_IN_SIZE);
1525
1526 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1527 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1528 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1529
1530 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1531 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1532
ed878458 1533 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
cdb73db0 1534 CMD_TIME_CLASS_B);
1da177e4 1535
ed878458 1536 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1537 return err;
1538}
1539
cdb73db0 1540int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt)
1da177e4 1541{
cdb73db0 1542 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt);
1da177e4
LT		 1543}
1544
cdb73db0 1545int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt)
1da177e4 1546{
ed878458 1547 struct mthca_mailbox *mailbox;
97f52eb4 1548 __be64 *inbox;
1da177e4
LT		 1549 int err;
1550
ed878458
RD		 1551 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1552 if (IS_ERR(mailbox))
1553 return PTR_ERR(mailbox);
1554 inbox = mailbox->buf;
1da177e4
LT		 1555
1556 inbox[0] = cpu_to_be64(virt);
1557 inbox[1] = cpu_to_be64(dma_addr);
1558
ed878458 1559 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
cdb73db0 1560 CMD_TIME_CLASS_B);
1da177e4 1561
ed878458 1562 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1563
1564 if (!err)
6bd6228e
RD		 1565 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1566 (unsigned long long) dma_addr, (unsigned long long) virt);
1da177e4
LT		 1567
1568 return err;
1569}
1570
cdb73db0 1571int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count)
1da177e4
LT		 1572{
1573 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1574 page_count, (unsigned long long) virt);
1575
cdb73db0
GR		 1576 return mthca_cmd(dev, virt, page_count, 0,
1577 CMD_UNMAP_ICM, CMD_TIME_CLASS_B);
1da177e4
LT		 1578}
1579
cdb73db0 1580int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm)
1da177e4 1581{
cdb73db0 1582 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1);
1da177e4
LT		 1583}
1584
cdb73db0 1585int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev)
1da177e4 1586{
cdb73db0 1587 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B);
1da177e4
LT		 1588}
1589
cdb73db0 1590int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages)
1da177e4 1591{
cdb73db0
GR		 1592 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0,
1593 0, CMD_SET_ICM_SIZE, CMD_TIME_CLASS_A);
1da177e4 1594
cdb73db0 1595 if (ret)
1da177e4
LT		 1596 return ret;
1597
1598 /*
8d3ef29d
IR		 1599 * Round up number of system pages needed in case
1600 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1da177e4 1601 */
8d3ef29d
IR		 1602 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1603 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1da177e4
LT		 1604
1605 return 0;
1606}
1607
ed878458 1608int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1609 int mpt_index)
1da177e4 1610{
ed878458 1611 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
cdb73db0 1612 CMD_TIME_CLASS_B);
1da177e4
LT		 1613}
1614
ed878458 1615int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1616 int mpt_index)
1da177e4 1617{
ed878458
RD		 1618 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1619 !mailbox, CMD_HW2SW_MPT,
cdb73db0 1620 CMD_TIME_CLASS_B);
1da177e4
LT		 1621}
1622
ed878458 1623int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1624 int num_mtt)
1da177e4 1625{
ed878458 1626 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
cdb73db0 1627 CMD_TIME_CLASS_B);
1da177e4
LT		 1628}
1629
cdb73db0 1630int mthca_SYNC_TPT(struct mthca_dev *dev)
b8ca06f6 1631{
cdb73db0 1632 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B);
b8ca06f6
MT		 1633}
1634
1da177e4 1635int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
cdb73db0 1636 int eq_num)
1da177e4
LT		 1637{
1638 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1639 unmap ? "Clearing" : "Setting",
1640 (unsigned long long) event_mask, eq_num);
1641 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
cdb73db0 1642 0, CMD_MAP_EQ, CMD_TIME_CLASS_B);
1da177e4
LT		 1643}
1644
ed878458 1645int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1646 int eq_num)
1da177e4 1647{
ed878458 1648 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
cdb73db0 1649 CMD_TIME_CLASS_A);
1da177e4
LT		 1650}
1651
ed878458 1652int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1653 int eq_num)
1da177e4 1654{
ed878458
RD		 1655 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1656 CMD_HW2SW_EQ,
cdb73db0 1657 CMD_TIME_CLASS_A);
1da177e4
LT		 1658}
1659
ed878458 1660int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1661 int cq_num)
1da177e4 1662{
ed878458 1663 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
cdb73db0 1664 CMD_TIME_CLASS_A);
1da177e4
LT		 1665}
1666
ed878458 1667int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1668 int cq_num)
1da177e4 1669{
ed878458
RD		 1670 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1671 CMD_HW2SW_CQ,
cdb73db0 1672 CMD_TIME_CLASS_A);
1da177e4
LT		 1673}
1674
cdb73db0 1675int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size)
4885bf64
RD		 1676{
1677 struct mthca_mailbox *mailbox;
1678 __be32 *inbox;
1679 int err;
1680
1681#define RESIZE_CQ_IN_SIZE 0x40
1682#define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1683#define RESIZE_CQ_LKEY_OFFSET 0x1c
1684
1685 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1686 if (IS_ERR(mailbox))
1687 return PTR_ERR(mailbox);
1688 inbox = mailbox->buf;
1689
1690 memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1691 /*
1692 * Leave start address fields zeroed out -- mthca assumes that
1693 * MRs for CQs always start at virtual address 0.
1694 */
1695 MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1696 MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET);
1697
1698 err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
cdb73db0 1699 CMD_TIME_CLASS_B);
4885bf64
RD		 1700
1701 mthca_free_mailbox(dev, mailbox);
1702 return err;
1703}
1704
ec34a922 1705int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1706 int srq_num)
ec34a922
RD		 1707{
1708 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
cdb73db0 1709 CMD_TIME_CLASS_A);
ec34a922
RD		 1710}
1711
1712int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1713 int srq_num)
ec34a922
RD		 1714{
1715 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1716 CMD_HW2SW_SRQ,
cdb73db0 1717 CMD_TIME_CLASS_A);
ec34a922
RD		 1718}
1719
8ebe5077 1720int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
cdb73db0 1721 struct mthca_mailbox *mailbox)
8ebe5077
EC		 1722{
1723 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
cdb73db0 1724 CMD_QUERY_SRQ, CMD_TIME_CLASS_A);
8ebe5077
EC		 1725}
1726
cdb73db0 1727int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit)
ec34a922
RD		 1728{
1729 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
cdb73db0 1730 CMD_TIME_CLASS_B);
ec34a922
RD		 1731}
1732
d844183d
RD		 1733int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1734 enum ib_qp_state next, u32 num, int is_ee,
cdb73db0 1735 struct mthca_mailbox *mailbox, u32 optmask)
1da177e4 1736{
d844183d
RD		 1737 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1738 [IB_QPS_RESET] = {
1739 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1740 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1741 [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
1742 },
1743 [IB_QPS_INIT] = {
1744 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1745 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1746 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
1747 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
1748 },
1749 [IB_QPS_RTR] = {
1750 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1751 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1752 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
1753 },
1754 [IB_QPS_RTS] = {
1755 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1756 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1757 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
1758 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
1759 },
1760 [IB_QPS_SQD] = {
1761 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1762 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1763 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
1764 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
1765 },
1766 [IB_QPS_SQE] = {
1767 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1768 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1769 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
1770 },
1771 [IB_QPS_ERR] = {
1772 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1773 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1774 }
1da177e4 1775 };
d844183d 1776
1da177e4 1777 u8 op_mod = 0;
ed878458 1778 int my_mailbox = 0;
1da177e4
LT		 1779 int err;
1780
d844183d 1781 if (op[cur][next] == CMD_ERR2RST_QPEE) {
1da177e4
LT		 1782 op_mod = 3; /* don't write outbox, any->reset */
1783
1784 /* For debugging */
ed878458
RD		 1785 if (!mailbox) {
1786 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1787 if (!IS_ERR(mailbox)) {
1788 my_mailbox = 1;
1789 op_mod = 2; /* write outbox, any->reset */
1790 } else
1791 mailbox = NULL;
1792 }
d844183d
RD		 1793
1794 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1795 (!!is_ee << 24) | num, op_mod,
cdb73db0 1796 op[cur][next], CMD_TIME_CLASS_C);
d844183d
RD		 1797
1798 if (0 && mailbox) {
1da177e4
LT		 1799 int i;
1800 mthca_dbg(dev, "Dumping QP context:\n");
d844183d 1801 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1da177e4
LT		 1802 for (i = 0; i < 0x100 / 4; ++i) {
1803 if (i % 8 == 0)
d844183d 1804 printk("[%02x] ", i * 4);
ed878458 1805 printk(" %08x",
97f52eb4 1806 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1da177e4
LT		 1807 if ((i + 1) % 8 == 0)
1808 printk("\n");
1809 }
1810 }
1da177e4 1811
d844183d
RD		 1812 if (my_mailbox)
1813 mthca_free_mailbox(dev, mailbox);
1814 } else {
1815 if (0) {
1da177e4
LT		 1816 int i;
1817 mthca_dbg(dev, "Dumping QP context:\n");
d844183d 1818 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1da177e4
LT		 1819 for (i = 0; i < 0x100 / 4; ++i) {
1820 if (i % 8 == 0)
d844183d 1821 printk(" [%02x] ", i * 4);
ed878458 1822 printk(" %08x",
97f52eb4 1823 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1da177e4
LT		 1824 if ((i + 1) % 8 == 0)
1825 printk("\n");
1826 }
1827 }
1828
d844183d 1829 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
cdb73db0 1830 op_mod, op[cur][next], CMD_TIME_CLASS_C);
d844183d 1831 }
ed878458 1832
1da177e4
LT		 1833 return err;
1834}
1835
1836int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
cdb73db0 1837 struct mthca_mailbox *mailbox)
1da177e4 1838{
ed878458 1839 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
cdb73db0 1840 CMD_QUERY_QPEE, CMD_TIME_CLASS_A);
1da177e4
LT		 1841}
1842
cdb73db0 1843int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn)
1da177e4
LT		 1844{
1845 u8 op_mod;
1846
1847 switch (type) {
1848 case IB_QPT_SMI:
1849 op_mod = 0;
1850 break;
1851 case IB_QPT_GSI:
1852 op_mod = 1;
1853 break;
1854 case IB_QPT_RAW_IPV6:
1855 op_mod = 2;
1856 break;
a2ebf07a 1857 case IB_QPT_RAW_ETHERTYPE:
1da177e4
LT		 1858 op_mod = 3;
1859 break;
1860 default:
1861 return -EINVAL;
1862 }
1863
1864 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
cdb73db0 1865 CMD_TIME_CLASS_B);
1da177e4
LT		 1866}
1867
1868int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
a97e2d86
IW		 1869 int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1870 const void *in_mad, void *response_mad)
1da177e4 1871{
ed878458
RD		 1872 struct mthca_mailbox *inmailbox, *outmailbox;
1873 void *inbox;
1da177e4
LT		 1874 int err;
1875 u32 in_modifier = port;
1876 u8 op_modifier = 0;
1877
1878#define MAD_IFC_BOX_SIZE 0x400
1879#define MAD_IFC_MY_QPN_OFFSET 0x100
68586b67
MT		 1880#define MAD_IFC_RQPN_OFFSET 0x108
1881#define MAD_IFC_SL_OFFSET 0x10c
1882#define MAD_IFC_G_PATH_OFFSET 0x10d
1883#define MAD_IFC_RLID_OFFSET 0x10e
1884#define MAD_IFC_PKEY_OFFSET 0x112
1da177e4
LT		 1885#define MAD_IFC_GRH_OFFSET 0x140
1886
ed878458
RD		 1887 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1888 if (IS_ERR(inmailbox))
1889 return PTR_ERR(inmailbox);
1890 inbox = inmailbox->buf;
1891
1892 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1893 if (IS_ERR(outmailbox)) {
1894 mthca_free_mailbox(dev, inmailbox);
1895 return PTR_ERR(outmailbox);
1896 }
1da177e4 1897
ed878458 1898 memcpy(inbox, in_mad, 256);
1da177e4
LT		 1899
1900 /*
1901 * Key check traps can't be generated unless we have in_wc to
1902 * tell us where to send the trap.
1903 */
1904 if (ignore_mkey || !in_wc)
1905 op_modifier |= 0x1;
1906 if (ignore_bkey || !in_wc)
1907 op_modifier |= 0x2;
1908
1909 if (in_wc) {
1910 u8 val;
1911
ed878458 1912 memset(inbox + 256, 0, 256);
1da177e4 1913
062dbb69 1914 MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET);
ed878458 1915 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1da177e4
LT		 1916
1917 val = in_wc->sl << 4;
ed878458 1918 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
1da177e4
LT		 1919
1920 val = in_wc->dlid_path_bits |
1921 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
68586b67 1922 MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET);
1da177e4 1923
62ede777 1924 MTHCA_PUT(inbox, ib_lid_cpu16(in_wc->slid), MAD_IFC_RLID_OFFSET);
ed878458 1925 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1da177e4
LT		 1926
1927 if (in_grh)
ed878458 1928 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1da177e4 1929
68586b67 1930 op_modifier |= 0x4;
1da177e4 1931
62ede777 1932 in_modifier |= ib_lid_cpu16(in_wc->slid) << 16;
1da177e4
LT		 1933 }
1934
ed878458
RD		 1935 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1936 in_modifier, op_modifier,
cdb73db0 1937 CMD_MAD_IFC, CMD_TIME_CLASS_C);
1da177e4 1938
cdb73db0 1939 if (!err)
ed878458 1940 memcpy(response_mad, outmailbox->buf, 256);
1da177e4 1941
ed878458
RD		 1942 mthca_free_mailbox(dev, inmailbox);
1943 mthca_free_mailbox(dev, outmailbox);
1da177e4
LT		 1944 return err;
1945}
1946
ed878458 1947int mthca_READ_MGM(struct mthca_dev *dev, int index,
cdb73db0 1948 struct mthca_mailbox *mailbox)
1da177e4 1949{
ed878458 1950 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
cdb73db0 1951 CMD_READ_MGM, CMD_TIME_CLASS_A);
1da177e4
LT		 1952}
1953
ed878458 1954int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
cdb73db0 1955 struct mthca_mailbox *mailbox)
1da177e4 1956{
ed878458 1957 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
cdb73db0 1958 CMD_TIME_CLASS_A);
1da177e4
LT		 1959}
1960
ed878458 1961int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
cdb73db0 1962 u16 *hash)
1da177e4 1963{
1da177e4
LT		 1964 u64 imm;
1965 int err;
1966
ed878458 1967 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
cdb73db0 1968 CMD_TIME_CLASS_A);
1da177e4 1969
ed878458 1970 *hash = imm;
1da177e4
LT		 1971 return err;
1972}
1973
cdb73db0 1974int mthca_NOP(struct mthca_dev *dev)
1da177e4 1975{
cdb73db0 1976 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100));
1da177e4 1977}
Linux 6.x block layer and io_uring tree(s)