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3d155f8c RD |
1 | /* |
2 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
3d155f8c RD |
31 | */ |
32 | ||
8c65b4a6 | 33 | #include <linux/jiffies.h> |
e4dd23d7 | 34 | #include <linux/module.h> |
8c65b4a6 | 35 | #include <linux/timer.h> |
b3b30f5e | 36 | #include <linux/workqueue.h> |
8c65b4a6 | 37 | |
3d155f8c RD |
38 | #include "mthca_dev.h" |
39 | ||
40 | enum { | |
41 | MTHCA_CATAS_POLL_INTERVAL = 5 * HZ, | |
42 | ||
43 | MTHCA_CATAS_TYPE_INTERNAL = 0, | |
44 | MTHCA_CATAS_TYPE_UPLINK = 3, | |
45 | MTHCA_CATAS_TYPE_DDR = 4, | |
46 | MTHCA_CATAS_TYPE_PARITY = 5, | |
47 | }; | |
48 | ||
49 | static DEFINE_SPINLOCK(catas_lock); | |
50 | ||
b3b30f5e JM |
51 | static LIST_HEAD(catas_list); |
52 | static struct workqueue_struct *catas_wq; | |
53 | static struct work_struct catas_work; | |
54 | ||
55 | static int catas_reset_disable; | |
56 | module_param_named(catas_reset_disable, catas_reset_disable, int, 0644); | |
57 | MODULE_PARM_DESC(catas_reset_disable, "disable reset on catastrophic event if nonzero"); | |
58 | ||
c4028958 | 59 | static void catas_reset(struct work_struct *work) |
b3b30f5e JM |
60 | { |
61 | struct mthca_dev *dev, *tmpdev; | |
62 | LIST_HEAD(tlist); | |
63 | int ret; | |
64 | ||
65 | mutex_lock(&mthca_device_mutex); | |
66 | ||
67 | spin_lock_irq(&catas_lock); | |
68 | list_splice_init(&catas_list, &tlist); | |
69 | spin_unlock_irq(&catas_lock); | |
70 | ||
71 | list_for_each_entry_safe(dev, tmpdev, &tlist, catas_err.list) { | |
d686159e | 72 | struct pci_dev *pdev = dev->pdev; |
b3b30f5e | 73 | ret = __mthca_restart_one(dev->pdev); |
d686159e | 74 | /* 'dev' now is not valid */ |
b3b30f5e | 75 | if (ret) |
d686159e JM |
76 | printk(KERN_ERR "mthca %s: Reset failed (%d)\n", |
77 | pci_name(pdev), ret); | |
78 | else { | |
79 | struct mthca_dev *d = pci_get_drvdata(pdev); | |
80 | mthca_dbg(d, "Reset succeeded\n"); | |
81 | } | |
b3b30f5e JM |
82 | } |
83 | ||
84 | mutex_unlock(&mthca_device_mutex); | |
85 | } | |
86 | ||
3d155f8c RD |
87 | static void handle_catas(struct mthca_dev *dev) |
88 | { | |
89 | struct ib_event event; | |
b3b30f5e | 90 | unsigned long flags; |
3d155f8c RD |
91 | const char *type; |
92 | int i; | |
93 | ||
94 | event.device = &dev->ib_dev; | |
95 | event.event = IB_EVENT_DEVICE_FATAL; | |
96 | event.element.port_num = 0; | |
d8410647 | 97 | dev->active = false; |
3d155f8c RD |
98 | |
99 | ib_dispatch_event(&event); | |
100 | ||
101 | switch (swab32(readl(dev->catas_err.map)) >> 24) { | |
102 | case MTHCA_CATAS_TYPE_INTERNAL: | |
103 | type = "internal error"; | |
104 | break; | |
105 | case MTHCA_CATAS_TYPE_UPLINK: | |
106 | type = "uplink bus error"; | |
107 | break; | |
108 | case MTHCA_CATAS_TYPE_DDR: | |
109 | type = "DDR data error"; | |
110 | break; | |
111 | case MTHCA_CATAS_TYPE_PARITY: | |
112 | type = "internal parity error"; | |
113 | break; | |
114 | default: | |
115 | type = "unknown error"; | |
116 | break; | |
117 | } | |
118 | ||
119 | mthca_err(dev, "Catastrophic error detected: %s\n", type); | |
120 | for (i = 0; i < dev->catas_err.size; ++i) | |
121 | mthca_err(dev, " buf[%02x]: %08x\n", | |
122 | i, swab32(readl(dev->catas_err.map + i))); | |
b3b30f5e JM |
123 | |
124 | if (catas_reset_disable) | |
125 | return; | |
126 | ||
127 | spin_lock_irqsave(&catas_lock, flags); | |
128 | list_add(&dev->catas_err.list, &catas_list); | |
129 | queue_work(catas_wq, &catas_work); | |
130 | spin_unlock_irqrestore(&catas_lock, flags); | |
3d155f8c RD |
131 | } |
132 | ||
133 | static void poll_catas(unsigned long dev_ptr) | |
134 | { | |
135 | struct mthca_dev *dev = (struct mthca_dev *) dev_ptr; | |
3d155f8c RD |
136 | int i; |
137 | ||
138 | for (i = 0; i < dev->catas_err.size; ++i) | |
139 | if (readl(dev->catas_err.map + i)) { | |
140 | handle_catas(dev); | |
141 | return; | |
142 | } | |
143 | ||
4522e08c | 144 | mod_timer(&dev->catas_err.timer, |
c036925a | 145 | round_jiffies(jiffies + MTHCA_CATAS_POLL_INTERVAL)); |
3d155f8c RD |
146 | } |
147 | ||
148 | void mthca_start_catas_poll(struct mthca_dev *dev) | |
149 | { | |
eb4a7cbf | 150 | phys_addr_t addr; |
3d155f8c RD |
151 | |
152 | init_timer(&dev->catas_err.timer); | |
3d155f8c RD |
153 | dev->catas_err.map = NULL; |
154 | ||
155 | addr = pci_resource_start(dev->pdev, 0) + | |
156 | ((pci_resource_len(dev->pdev, 0) - 1) & | |
157 | dev->catas_err.addr); | |
158 | ||
3d155f8c RD |
159 | dev->catas_err.map = ioremap(addr, dev->catas_err.size * 4); |
160 | if (!dev->catas_err.map) { | |
161 | mthca_warn(dev, "couldn't map catastrophic error region " | |
eb4a7cbf JB |
162 | "at 0x%llx/0x%x\n", (unsigned long long) addr, |
163 | dev->catas_err.size * 4); | |
3d155f8c RD |
164 | return; |
165 | } | |
166 | ||
167 | dev->catas_err.timer.data = (unsigned long) dev; | |
168 | dev->catas_err.timer.function = poll_catas; | |
169 | dev->catas_err.timer.expires = jiffies + MTHCA_CATAS_POLL_INTERVAL; | |
b3b30f5e | 170 | INIT_LIST_HEAD(&dev->catas_err.list); |
3d155f8c RD |
171 | add_timer(&dev->catas_err.timer); |
172 | } | |
173 | ||
174 | void mthca_stop_catas_poll(struct mthca_dev *dev) | |
175 | { | |
3d155f8c RD |
176 | del_timer_sync(&dev->catas_err.timer); |
177 | ||
208dde28 | 178 | if (dev->catas_err.map) |
3d155f8c | 179 | iounmap(dev->catas_err.map); |
b3b30f5e JM |
180 | |
181 | spin_lock_irq(&catas_lock); | |
182 | list_del(&dev->catas_err.list); | |
183 | spin_unlock_irq(&catas_lock); | |
184 | } | |
185 | ||
186 | int __init mthca_catas_init(void) | |
187 | { | |
c4028958 | 188 | INIT_WORK(&catas_work, catas_reset); |
b3b30f5e JM |
189 | |
190 | catas_wq = create_singlethread_workqueue("mthca_catas"); | |
191 | if (!catas_wq) | |
192 | return -ENOMEM; | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | void mthca_catas_cleanup(void) | |
198 | { | |
199 | destroy_workqueue(catas_wq); | |
3d155f8c | 200 | } |