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net/mlx5: Unify and improve command interface
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97
EC		 37#include "mlx5_ib.h"
38#include "user.h"
39
40/* not supported currently */
41static int wq_signature;
42
43enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52};
53
54enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 MLX5_IB_CACHE_LINE_SIZE = 64,
57};
58
59static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 61 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
74};
75
f0313965
ES		 76struct mlx5_wqe_eth_pad {
77 u8 rsvd0[16];
78};
e126ba97 79
89ea94a7
MG		 80static void get_cqs(enum ib_qp_type qp_type,
81 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
82 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
83
e126ba97
EC		 84static int is_qp0(enum ib_qp_type qp_type)
85{
86 return qp_type == IB_QPT_SMI;
87}
88
e126ba97
EC		 89static int is_sqp(enum ib_qp_type qp_type)
90{
91 return is_qp0(qp_type) || is_qp1(qp_type);
92}
93
94static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
95{
96 return mlx5_buf_offset(&qp->buf, offset);
97}
98
99static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
100{
101 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
102}
103
104void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
105{
106 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
107}
108
c1395a2a
HE		 109/**
110 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
111 *
112 * @qp: QP to copy from.
113 * @send: copy from the send queue when non-zero, use the receive queue
114 * otherwise.
115 * @wqe_index: index to start copying from. For send work queues, the
116 * wqe_index is in units of MLX5_SEND_WQE_BB.
117 * For receive work queue, it is the number of work queue
118 * element in the queue.
119 * @buffer: destination buffer.
120 * @length: maximum number of bytes to copy.
121 *
122 * Copies at least a single WQE, but may copy more data.
123 *
124 * Return: the number of bytes copied, or an error code.
125 */
126int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 127 void *buffer, u32 length,
128 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 129{
130 struct ib_device *ibdev = qp->ibqp.device;
131 struct mlx5_ib_dev *dev = to_mdev(ibdev);
132 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
133 size_t offset;
134 size_t wq_end;
19098df2 135 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 136 u32 first_copy_length;
137 int wqe_length;
138 int ret;
139
140 if (wq->wqe_cnt == 0) {
141 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
142 qp->ibqp.qp_type);
143 return -EINVAL;
144 }
145
146 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
147 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
148
149 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
150 return -EINVAL;
151
152 if (offset > umem->length ||
153 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
154 return -EINVAL;
155
156 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
157 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
158 if (ret)
159 return ret;
160
161 if (send) {
162 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
163 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
164
165 wqe_length = ds * MLX5_WQE_DS_UNITS;
166 } else {
167 wqe_length = 1 << wq->wqe_shift;
168 }
169
170 if (wqe_length <= first_copy_length)
171 return first_copy_length;
172
173 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
174 wqe_length - first_copy_length);
175 if (ret)
176 return ret;
177
178 return wqe_length;
179}
180
e126ba97
EC		 181static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
182{
183 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
184 struct ib_event event;
185
19098df2 186 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
187 /* This event is only valid for trans_qps */
188 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
189 }
e126ba97
EC		 190
191 if (ibqp->event_handler) {
192 event.device = ibqp->device;
193 event.element.qp = ibqp;
194 switch (type) {
195 case MLX5_EVENT_TYPE_PATH_MIG:
196 event.event = IB_EVENT_PATH_MIG;
197 break;
198 case MLX5_EVENT_TYPE_COMM_EST:
199 event.event = IB_EVENT_COMM_EST;
200 break;
201 case MLX5_EVENT_TYPE_SQ_DRAINED:
202 event.event = IB_EVENT_SQ_DRAINED;
203 break;
204 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
205 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
206 break;
207 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
208 event.event = IB_EVENT_QP_FATAL;
209 break;
210 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
211 event.event = IB_EVENT_PATH_MIG_ERR;
212 break;
213 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
214 event.event = IB_EVENT_QP_REQ_ERR;
215 break;
216 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
217 event.event = IB_EVENT_QP_ACCESS_ERR;
218 break;
219 default:
220 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
221 return;
222 }
223
224 ibqp->event_handler(&event, ibqp->qp_context);
225 }
226}
227
228static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
229 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
230{
231 int wqe_size;
232 int wq_size;
233
234 /* Sanity check RQ size before proceeding */
938fe83c 235 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 236 return -EINVAL;
237
238 if (!has_rq) {
239 qp->rq.max_gs = 0;
240 qp->rq.wqe_cnt = 0;
241 qp->rq.wqe_shift = 0;
0540d814
NO		 242 cap->max_recv_wr = 0;
243 cap->max_recv_sge = 0;
e126ba97
EC		 244 } else {
245 if (ucmd) {
246 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
247 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
248 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
249 qp->rq.max_post = qp->rq.wqe_cnt;
250 } else {
251 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
252 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
253 wqe_size = roundup_pow_of_two(wqe_size);
254 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
255 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
256 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 257 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 258 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
259 wqe_size,
938fe83c
SM		 260 MLX5_CAP_GEN(dev->mdev,
261 max_wqe_sz_rq));
e126ba97
EC		 262 return -EINVAL;
263 }
264 qp->rq.wqe_shift = ilog2(wqe_size);
265 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
266 qp->rq.max_post = qp->rq.wqe_cnt;
267 }
268 }
269
270 return 0;
271}
272
f0313965 273static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 274{
618af384 275 int size = 0;
e126ba97 276
f0313965 277 switch (attr->qp_type) {
e126ba97 278 case IB_QPT_XRC_INI:
b125a54b 279 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 280 /* fall through */
281 case IB_QPT_RC:
282 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 283 max(sizeof(struct mlx5_wqe_atomic_seg) +
284 sizeof(struct mlx5_wqe_raddr_seg),
285 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
286 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 287 break;
288
b125a54b
EC		 289 case IB_QPT_XRC_TGT:
290 return 0;
291
e126ba97 292 case IB_QPT_UC:
b125a54b 293 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 294 max(sizeof(struct mlx5_wqe_raddr_seg),
295 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
296 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 297 break;
298
299 case IB_QPT_UD:
f0313965
ES		 300 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
301 size += sizeof(struct mlx5_wqe_eth_pad) +
302 sizeof(struct mlx5_wqe_eth_seg);
303 /* fall through */
e126ba97 304 case IB_QPT_SMI:
d16e91da 305 case MLX5_IB_QPT_HW_GSI:
b125a54b 306 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 307 sizeof(struct mlx5_wqe_datagram_seg);
308 break;
309
310 case MLX5_IB_QPT_REG_UMR:
b125a54b 311 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 312 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
313 sizeof(struct mlx5_mkey_seg);
314 break;
315
316 default:
317 return -EINVAL;
318 }
319
320 return size;
321}
322
323static int calc_send_wqe(struct ib_qp_init_attr *attr)
324{
325 int inl_size = 0;
326 int size;
327
f0313965 328 size = sq_overhead(attr);
e126ba97
EC		 329 if (size < 0)
330 return size;
331
332 if (attr->cap.max_inline_data) {
333 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
334 attr->cap.max_inline_data;
335 }
336
337 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 338 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
339 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
340 return MLX5_SIG_WQE_SIZE;
341 else
342 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 343}
344
345static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
346 struct mlx5_ib_qp *qp)
347{
348 int wqe_size;
349 int wq_size;
350
351 if (!attr->cap.max_send_wr)
352 return 0;
353
354 wqe_size = calc_send_wqe(attr);
355 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
356 if (wqe_size < 0)
357 return wqe_size;
358
938fe83c 359 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 360 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 361 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 362 return -EINVAL;
363 }
364
f0313965
ES		 365 qp->max_inline_data = wqe_size - sq_overhead(attr) -
366 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 367 attr->cap.max_inline_data = qp->max_inline_data;
368
e1e66cc2
SG		 369 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
370 qp->signature_en = true;
371
e126ba97
EC		 372 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
373 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 374 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
b125a54b 375 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
938fe83c
SM		 376 qp->sq.wqe_cnt,
377 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 378 return -ENOMEM;
379 }
e126ba97
EC		 380 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
381 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 382 qp->sq.max_post = wq_size / wqe_size;
383 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 384
385 return wq_size;
386}
387
388static int set_user_buf_size(struct mlx5_ib_dev *dev,
389 struct mlx5_ib_qp *qp,
19098df2 390 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 391 struct mlx5_ib_qp_base *base,
392 struct ib_qp_init_attr *attr)
e126ba97
EC		 393{
394 int desc_sz = 1 << qp->sq.wqe_shift;
395
938fe83c 396 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 397 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 398 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 399 return -EINVAL;
400 }
401
402 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
403 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
404 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
405 return -EINVAL;
406 }
407
408 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
409
938fe83c 410 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 411 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 412 qp->sq.wqe_cnt,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 414 return -EINVAL;
415 }
416
0fb2ed66 417 if (attr->qp_type == IB_QPT_RAW_PACKET) {
418 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
419 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
420 } else {
421 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
422 (qp->sq.wqe_cnt << 6);
423 }
e126ba97
EC		 424
425 return 0;
426}
427
428static int qp_has_rq(struct ib_qp_init_attr *attr)
429{
430 if (attr->qp_type == IB_QPT_XRC_INI ||
431 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
432 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
433 !attr->cap.max_recv_wr)
434 return 0;
435
436 return 1;
437}
438
c1be5232
EC		 439static int first_med_uuar(void)
440{
441 return 1;
442}
443
444static int next_uuar(int n)
445{
446 n++;
447
448 while (((n % 4) & 2))
449 n++;
450
451 return n;
452}
453
454static int num_med_uuar(struct mlx5_uuar_info *uuari)
455{
456 int n;
457
458 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
459 uuari->num_low_latency_uuars - 1;
460
461 return n >= 0 ? n : 0;
462}
463
464static int max_uuari(struct mlx5_uuar_info *uuari)
465{
466 return uuari->num_uars * 4;
467}
468
469static int first_hi_uuar(struct mlx5_uuar_info *uuari)
470{
471 int med;
472 int i;
473 int t;
474
475 med = num_med_uuar(uuari);
476 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
477 t++;
478 if (t == med)
479 return next_uuar(i);
480 }
481
482 return 0;
483}
484
e126ba97
EC		 485static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
486{
e126ba97
EC		 487 int i;
488
c1be5232 489 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 490 if (!test_bit(i, uuari->bitmap)) {
491 set_bit(i, uuari->bitmap);
492 uuari->count[i]++;
493 return i;
494 }
495 }
496
497 return -ENOMEM;
498}
499
500static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
501{
c1be5232 502 int minidx = first_med_uuar();
e126ba97
EC		 503 int i;
504
c1be5232 505 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 506 if (uuari->count[i] < uuari->count[minidx])
507 minidx = i;
508 }
509
510 uuari->count[minidx]++;
511 return minidx;
512}
513
514static int alloc_uuar(struct mlx5_uuar_info *uuari,
515 enum mlx5_ib_latency_class lat)
516{
517 int uuarn = -EINVAL;
518
519 mutex_lock(&uuari->lock);
520 switch (lat) {
521 case MLX5_IB_LATENCY_CLASS_LOW:
522 uuarn = 0;
523 uuari->count[uuarn]++;
524 break;
525
526 case MLX5_IB_LATENCY_CLASS_MEDIUM:
78c0f98c
EC		 527 if (uuari->ver < 2)
528 uuarn = -ENOMEM;
529 else
530 uuarn = alloc_med_class_uuar(uuari);
e126ba97
EC		 531 break;
532
533 case MLX5_IB_LATENCY_CLASS_HIGH:
78c0f98c
EC		 534 if (uuari->ver < 2)
535 uuarn = -ENOMEM;
536 else
537 uuarn = alloc_high_class_uuar(uuari);
e126ba97
EC		 538 break;
539
540 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
541 uuarn = 2;
542 break;
543 }
544 mutex_unlock(&uuari->lock);
545
546 return uuarn;
547}
548
549static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
550{
551 clear_bit(uuarn, uuari->bitmap);
552 --uuari->count[uuarn];
553}
554
555static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
556{
557 clear_bit(uuarn, uuari->bitmap);
558 --uuari->count[uuarn];
559}
560
561static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
562{
563 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
564 int high_uuar = nuuars - uuari->num_low_latency_uuars;
565
566 mutex_lock(&uuari->lock);
567 if (uuarn == 0) {
568 --uuari->count[uuarn];
569 goto out;
570 }
571
572 if (uuarn < high_uuar) {
573 free_med_class_uuar(uuari, uuarn);
574 goto out;
575 }
576
577 free_high_class_uuar(uuari, uuarn);
578
579out:
580 mutex_unlock(&uuari->lock);
581}
582
583static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
584{
585 switch (state) {
586 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
587 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
588 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
589 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
590 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
591 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
592 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
593 default: return -1;
594 }
595}
596
597static int to_mlx5_st(enum ib_qp_type type)
598{
599 switch (type) {
600 case IB_QPT_RC: return MLX5_QP_ST_RC;
601 case IB_QPT_UC: return MLX5_QP_ST_UC;
602 case IB_QPT_UD: return MLX5_QP_ST_UD;
603 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
604 case IB_QPT_XRC_INI:
605 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
606 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 607 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 608 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 609 case IB_QPT_RAW_PACKET:
0fb2ed66 610 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 611 case IB_QPT_MAX:
612 default: return -EINVAL;
613 }
614}
615
89ea94a7
MG		 616static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
617 struct mlx5_ib_cq *recv_cq);
618static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
619 struct mlx5_ib_cq *recv_cq);
620
e126ba97
EC		 621static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
622{
623 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
624}
625
19098df2 626static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
627 struct ib_pd *pd,
628 unsigned long addr, size_t size,
629 struct ib_umem **umem,
630 int *npages, int *page_shift, int *ncont,
631 u32 *offset)
632{
633 int err;
634
635 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
636 if (IS_ERR(*umem)) {
637 mlx5_ib_dbg(dev, "umem_get failed\n");
638 return PTR_ERR(*umem);
639 }
640
641 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
642
643 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
644 if (err) {
645 mlx5_ib_warn(dev, "bad offset\n");
646 goto err_umem;
647 }
648
649 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
650 addr, size, *npages, *page_shift, *ncont, *offset);
651
652 return 0;
653
654err_umem:
655 ib_umem_release(*umem);
656 *umem = NULL;
657
658 return err;
659}
660
79b20a6c
YH		 661static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
662{
663 struct mlx5_ib_ucontext *context;
664
665 context = to_mucontext(pd->uobject->context);
666 mlx5_ib_db_unmap_user(context, &rwq->db);
667 if (rwq->umem)
668 ib_umem_release(rwq->umem);
669}
670
671static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
672 struct mlx5_ib_rwq *rwq,
673 struct mlx5_ib_create_wq *ucmd)
674{
675 struct mlx5_ib_ucontext *context;
676 int page_shift = 0;
677 int npages;
678 u32 offset = 0;
679 int ncont = 0;
680 int err;
681
682 if (!ucmd->buf_addr)
683 return -EINVAL;
684
685 context = to_mucontext(pd->uobject->context);
686 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
687 rwq->buf_size, 0, 0);
688 if (IS_ERR(rwq->umem)) {
689 mlx5_ib_dbg(dev, "umem_get failed\n");
690 err = PTR_ERR(rwq->umem);
691 return err;
692 }
693
694 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
695 &ncont, NULL);
696 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
697 &rwq->rq_page_offset);
698 if (err) {
699 mlx5_ib_warn(dev, "bad offset\n");
700 goto err_umem;
701 }
702
703 rwq->rq_num_pas = ncont;
704 rwq->page_shift = page_shift;
705 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
706 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
707
708 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
709 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
710 npages, page_shift, ncont, offset);
711
712 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
713 if (err) {
714 mlx5_ib_dbg(dev, "map failed\n");
715 goto err_umem;
716 }
717
718 rwq->create_type = MLX5_WQ_USER;
719 return 0;
720
721err_umem:
722 ib_umem_release(rwq->umem);
723 return err;
724}
725
e126ba97
EC		 726static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
727 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 728 struct ib_qp_init_attr *attr,
09a7d9ec 729 u32 **in,
19098df2 730 struct mlx5_ib_create_qp_resp *resp, int *inlen,
731 struct mlx5_ib_qp_base *base)
e126ba97
EC		 732{
733 struct mlx5_ib_ucontext *context;
734 struct mlx5_ib_create_qp ucmd;
19098df2 735 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 736 int page_shift = 0;
e126ba97
EC		 737 int uar_index;
738 int npages;
9e9c47d0 739 u32 offset = 0;
e126ba97 740 int uuarn;
9e9c47d0 741 int ncont = 0;
09a7d9ec
SM		 742 __be64 *pas;
743 void *qpc;
e126ba97
EC		 744 int err;
745
746 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
747 if (err) {
748 mlx5_ib_dbg(dev, "copy failed\n");
749 return err;
750 }
751
752 context = to_mucontext(pd->uobject->context);
753 /*
754 * TBD: should come from the verbs when we have the API
755 */
051f2630
LR		 756 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
757 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
758 uuarn = MLX5_CROSS_CHANNEL_UUAR;
759 else {
760 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
e126ba97 761 if (uuarn < 0) {
051f2630
LR		 762 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
763 mlx5_ib_dbg(dev, "reverting to medium latency\n");
764 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
c1be5232 765 if (uuarn < 0) {
051f2630
LR		 766 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
767 mlx5_ib_dbg(dev, "reverting to high latency\n");
768 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
769 if (uuarn < 0) {
770 mlx5_ib_warn(dev, "uuar allocation failed\n");
771 return uuarn;
772 }
c1be5232 773 }
e126ba97
EC		 774 }
775 }
776
777 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
778 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
779
48fea837
HE		 780 qp->rq.offset = 0;
781 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
782 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
783
0fb2ed66 784 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97
EC		 785 if (err)
786 goto err_uuar;
787
19098df2 788 if (ucmd.buf_addr && ubuffer->buf_size) {
789 ubuffer->buf_addr = ucmd.buf_addr;
790 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
791 ubuffer->buf_size,
792 &ubuffer->umem, &npages, &page_shift,
793 &ncont, &offset);
794 if (err)
9e9c47d0 795 goto err_uuar;
9e9c47d0 796 } else {
19098df2 797 ubuffer->umem = NULL;
e126ba97 798 }
e126ba97 799
09a7d9ec
SM		 800 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
801 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
e126ba97
EC		 802 *in = mlx5_vzalloc(*inlen);
803 if (!*in) {
804 err = -ENOMEM;
805 goto err_umem;
806 }
09a7d9ec
SM		 807
808 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 809 if (ubuffer->umem)
09a7d9ec
SM		 810 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
811
812 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
813
814 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
815 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 816
09a7d9ec 817 MLX5_SET(qpc, qpc, uar_page, uar_index);
e126ba97
EC		 818 resp->uuar_index = uuarn;
819 qp->uuarn = uuarn;
820
821 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
822 if (err) {
823 mlx5_ib_dbg(dev, "map failed\n");
824 goto err_free;
825 }
826
827 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
828 if (err) {
829 mlx5_ib_dbg(dev, "copy failed\n");
830 goto err_unmap;
831 }
832 qp->create_type = MLX5_QP_USER;
833
834 return 0;
835
836err_unmap:
837 mlx5_ib_db_unmap_user(context, &qp->db);
838
839err_free:
479163f4 840 kvfree(*in);
e126ba97
EC		 841
842err_umem:
19098df2 843 if (ubuffer->umem)
844 ib_umem_release(ubuffer->umem);
e126ba97
EC		 845
846err_uuar:
847 free_uuar(&context->uuari, uuarn);
848 return err;
849}
850
19098df2 851static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
852 struct mlx5_ib_qp_base *base)
e126ba97
EC		 853{
854 struct mlx5_ib_ucontext *context;
855
856 context = to_mucontext(pd->uobject->context);
857 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 858 if (base->ubuffer.umem)
859 ib_umem_release(base->ubuffer.umem);
e126ba97
EC		 860 free_uuar(&context->uuari, qp->uuarn);
861}
862
863static int create_kernel_qp(struct mlx5_ib_dev *dev,
864 struct ib_qp_init_attr *init_attr,
865 struct mlx5_ib_qp *qp,
09a7d9ec 866 u32 **in, int *inlen,
19098df2 867 struct mlx5_ib_qp_base *base)
e126ba97
EC		 868{
869 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
870 struct mlx5_uuar_info *uuari;
871 int uar_index;
09a7d9ec 872 void *qpc;
e126ba97
EC		 873 int uuarn;
874 int err;
875
9603b61d 876 uuari = &dev->mdev->priv.uuari;
f0313965
ES		 877 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
878 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c
HE		 879 IB_QP_CREATE_IPOIB_UD_LSO |
880 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 881 return -EINVAL;
e126ba97
EC		 882
883 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
884 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
885
886 uuarn = alloc_uuar(uuari, lc);
887 if (uuarn < 0) {
888 mlx5_ib_dbg(dev, "\n");
889 return -ENOMEM;
890 }
891
892 qp->bf = &uuari->bfs[uuarn];
893 uar_index = qp->bf->uar->index;
894
895 err = calc_sq_size(dev, init_attr, qp);
896 if (err < 0) {
897 mlx5_ib_dbg(dev, "err %d\n", err);
898 goto err_uuar;
899 }
900
901 qp->rq.offset = 0;
902 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 903 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 904
19098df2 905 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 906 if (err) {
907 mlx5_ib_dbg(dev, "err %d\n", err);
908 goto err_uuar;
909 }
910
911 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 912 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
913 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
e126ba97
EC		 914 *in = mlx5_vzalloc(*inlen);
915 if (!*in) {
916 err = -ENOMEM;
917 goto err_buf;
918 }
09a7d9ec
SM		 919
920 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
921 MLX5_SET(qpc, qpc, uar_page, uar_index);
922 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
923
e126ba97 924 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 925 MLX5_SET(qpc, qpc, fre, 1);
926 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 927
b11a4f9c 928 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 929 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 930 qp->flags |= MLX5_IB_QP_SQPN_QP1;
931 }
932
09a7d9ec
SM		 933 mlx5_fill_page_array(&qp->buf,
934 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 935
9603b61d 936 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 937 if (err) {
938 mlx5_ib_dbg(dev, "err %d\n", err);
939 goto err_free;
940 }
941
e126ba97
EC		 942 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
943 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
944 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
945 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
946 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
947
948 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
949 !qp->sq.w_list || !qp->sq.wqe_head) {
950 err = -ENOMEM;
951 goto err_wrid;
952 }
953 qp->create_type = MLX5_QP_KERNEL;
954
955 return 0;
956
957err_wrid:
9603b61d 958 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 959 kfree(qp->sq.wqe_head);
960 kfree(qp->sq.w_list);
961 kfree(qp->sq.wrid);
962 kfree(qp->sq.wr_data);
963 kfree(qp->rq.wrid);
964
965err_free:
479163f4 966 kvfree(*in);
e126ba97
EC		 967
968err_buf:
9603b61d 969 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 970
971err_uuar:
9603b61d 972 free_uuar(&dev->mdev->priv.uuari, uuarn);
e126ba97
EC		 973 return err;
974}
975
976static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
977{
9603b61d 978 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 979 kfree(qp->sq.wqe_head);
980 kfree(qp->sq.w_list);
981 kfree(qp->sq.wrid);
982 kfree(qp->sq.wr_data);
983 kfree(qp->rq.wrid);
9603b61d
JM		 984 mlx5_buf_free(dev->mdev, &qp->buf);
985 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
e126ba97
EC		 986}
987
09a7d9ec 988static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 989{
990 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
991 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 992 return MLX5_SRQ_RQ;
e126ba97 993 else if (!qp->has_rq)
09a7d9ec 994 return MLX5_ZERO_LEN_RQ;
e126ba97 995 else
09a7d9ec 996 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 997}
998
999static int is_connected(enum ib_qp_type qp_type)
1000{
1001 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1002 return 1;
1003
1004 return 0;
1005}
1006
0fb2ed66 1007static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1008 struct mlx5_ib_sq *sq, u32 tdn)
1009{
c4f287c4 1010 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1011 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1012
0fb2ed66 1013 MLX5_SET(tisc, tisc, transport_domain, tdn);
0fb2ed66 1014 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1015}
1016
1017static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1018 struct mlx5_ib_sq *sq)
1019{
1020 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1021}
1022
1023static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1024 struct mlx5_ib_sq *sq, void *qpin,
1025 struct ib_pd *pd)
1026{
1027 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1028 __be64 *pas;
1029 void *in;
1030 void *sqc;
1031 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1032 void *wq;
1033 int inlen;
1034 int err;
1035 int page_shift = 0;
1036 int npages;
1037 int ncont = 0;
1038 u32 offset = 0;
1039
1040 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1041 &sq->ubuffer.umem, &npages, &page_shift,
1042 &ncont, &offset);
1043 if (err)
1044 return err;
1045
1046 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1047 in = mlx5_vzalloc(inlen);
1048 if (!in) {
1049 err = -ENOMEM;
1050 goto err_umem;
1051 }
1052
1053 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1054 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1055 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1056 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1057 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1058 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1059 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1060
1061 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1062 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1063 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1064 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1065 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1066 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1067 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1068 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1069 MLX5_SET(wq, wq, page_offset, offset);
1070
1071 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1072 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1073
1074 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1075
1076 kvfree(in);
1077
1078 if (err)
1079 goto err_umem;
1080
1081 return 0;
1082
1083err_umem:
1084 ib_umem_release(sq->ubuffer.umem);
1085 sq->ubuffer.umem = NULL;
1086
1087 return err;
1088}
1089
1090static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1091 struct mlx5_ib_sq *sq)
1092{
1093 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1094 ib_umem_release(sq->ubuffer.umem);
1095}
1096
1097static int get_rq_pas_size(void *qpc)
1098{
1099 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1100 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1101 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1102 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1103 u32 po_quanta = 1 << (log_page_size - 6);
1104 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1105 u32 page_size = 1 << log_page_size;
1106 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1107 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1108
1109 return rq_num_pas * sizeof(u64);
1110}
1111
1112static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1113 struct mlx5_ib_rq *rq, void *qpin)
1114{
358e42ea 1115 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1116 __be64 *pas;
1117 __be64 *qp_pas;
1118 void *in;
1119 void *rqc;
1120 void *wq;
1121 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1122 int inlen;
1123 int err;
1124 u32 rq_pas_size = get_rq_pas_size(qpc);
1125
1126 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1127 in = mlx5_vzalloc(inlen);
1128 if (!in)
1129 return -ENOMEM;
1130
1131 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1132 MLX5_SET(rqc, rqc, vsd, 1);
1133 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1134 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1135 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1136 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1137 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1138
358e42ea
MD		 1139 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1140 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1141
0fb2ed66 1142 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1143 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1144 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1145 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1146 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1147 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1148 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1149 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1150 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1151 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1152
1153 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1154 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1155 memcpy(pas, qp_pas, rq_pas_size);
1156
1157 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1158
1159 kvfree(in);
1160
1161 return err;
1162}
1163
1164static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1165 struct mlx5_ib_rq *rq)
1166{
1167 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1168}
1169
1170static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1171 struct mlx5_ib_rq *rq, u32 tdn)
1172{
1173 u32 *in;
1174 void *tirc;
1175 int inlen;
1176 int err;
1177
1178 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1179 in = mlx5_vzalloc(inlen);
1180 if (!in)
1181 return -ENOMEM;
1182
1183 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1184 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1185 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1186 MLX5_SET(tirc, tirc, transport_domain, tdn);
1187
1188 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1189
1190 kvfree(in);
1191
1192 return err;
1193}
1194
1195static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1196 struct mlx5_ib_rq *rq)
1197{
1198 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1199}
1200
1201static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1202 u32 *in,
0fb2ed66 1203 struct ib_pd *pd)
1204{
1205 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1206 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1207 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1208 struct ib_uobject *uobj = pd->uobject;
1209 struct ib_ucontext *ucontext = uobj->context;
1210 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1211 int err;
1212 u32 tdn = mucontext->tdn;
1213
1214 if (qp->sq.wqe_cnt) {
1215 err = create_raw_packet_qp_tis(dev, sq, tdn);
1216 if (err)
1217 return err;
1218
1219 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1220 if (err)
1221 goto err_destroy_tis;
1222
1223 sq->base.container_mibqp = qp;
1224 }
1225
1226 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1227 rq->base.container_mibqp = qp;
1228
0fb2ed66 1229 err = create_raw_packet_qp_rq(dev, rq, in);
1230 if (err)
1231 goto err_destroy_sq;
1232
0fb2ed66 1233
1234 err = create_raw_packet_qp_tir(dev, rq, tdn);
1235 if (err)
1236 goto err_destroy_rq;
1237 }
1238
1239 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1240 rq->base.mqp.qpn;
1241
1242 return 0;
1243
1244err_destroy_rq:
1245 destroy_raw_packet_qp_rq(dev, rq);
1246err_destroy_sq:
1247 if (!qp->sq.wqe_cnt)
1248 return err;
1249 destroy_raw_packet_qp_sq(dev, sq);
1250err_destroy_tis:
1251 destroy_raw_packet_qp_tis(dev, sq);
1252
1253 return err;
1254}
1255
1256static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1257 struct mlx5_ib_qp *qp)
1258{
1259 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1260 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1261 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1262
1263 if (qp->rq.wqe_cnt) {
1264 destroy_raw_packet_qp_tir(dev, rq);
1265 destroy_raw_packet_qp_rq(dev, rq);
1266 }
1267
1268 if (qp->sq.wqe_cnt) {
1269 destroy_raw_packet_qp_sq(dev, sq);
1270 destroy_raw_packet_qp_tis(dev, sq);
1271 }
1272}
1273
1274static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1275 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1276{
1277 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1278 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1279
1280 sq->sq = &qp->sq;
1281 rq->rq = &qp->rq;
1282 sq->doorbell = &qp->db;
1283 rq->doorbell = &qp->db;
1284}
1285
28d61370
YH		 1286static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1287{
1288 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1289}
1290
1291static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1292 struct ib_pd *pd,
1293 struct ib_qp_init_attr *init_attr,
1294 struct ib_udata *udata)
1295{
1296 struct ib_uobject *uobj = pd->uobject;
1297 struct ib_ucontext *ucontext = uobj->context;
1298 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1299 struct mlx5_ib_create_qp_resp resp = {};
1300 int inlen;
1301 int err;
1302 u32 *in;
1303 void *tirc;
1304 void *hfso;
1305 u32 selected_fields = 0;
1306 size_t min_resp_len;
1307 u32 tdn = mucontext->tdn;
1308 struct mlx5_ib_create_qp_rss ucmd = {};
1309 size_t required_cmd_sz;
1310
1311 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1312 return -EOPNOTSUPP;
1313
1314 if (init_attr->create_flags || init_attr->send_cq)
1315 return -EINVAL;
1316
1317 min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1318 if (udata->outlen < min_resp_len)
1319 return -EINVAL;
1320
1321 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1322 if (udata->inlen < required_cmd_sz) {
1323 mlx5_ib_dbg(dev, "invalid inlen\n");
1324 return -EINVAL;
1325 }
1326
1327 if (udata->inlen > sizeof(ucmd) &&
1328 !ib_is_udata_cleared(udata, sizeof(ucmd),
1329 udata->inlen - sizeof(ucmd))) {
1330 mlx5_ib_dbg(dev, "inlen is not supported\n");
1331 return -EOPNOTSUPP;
1332 }
1333
1334 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1335 mlx5_ib_dbg(dev, "copy failed\n");
1336 return -EFAULT;
1337 }
1338
1339 if (ucmd.comp_mask) {
1340 mlx5_ib_dbg(dev, "invalid comp mask\n");
1341 return -EOPNOTSUPP;
1342 }
1343
1344 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1345 mlx5_ib_dbg(dev, "invalid reserved\n");
1346 return -EOPNOTSUPP;
1347 }
1348
1349 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1350 if (err) {
1351 mlx5_ib_dbg(dev, "copy failed\n");
1352 return -EINVAL;
1353 }
1354
1355 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1356 in = mlx5_vzalloc(inlen);
1357 if (!in)
1358 return -ENOMEM;
1359
1360 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1361 MLX5_SET(tirc, tirc, disp_type,
1362 MLX5_TIRC_DISP_TYPE_INDIRECT);
1363 MLX5_SET(tirc, tirc, indirect_table,
1364 init_attr->rwq_ind_tbl->ind_tbl_num);
1365 MLX5_SET(tirc, tirc, transport_domain, tdn);
1366
1367 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1368 switch (ucmd.rx_hash_function) {
1369 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1370 {
1371 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1372 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1373
1374 if (len != ucmd.rx_key_len) {
1375 err = -EINVAL;
1376 goto err;
1377 }
1378
1379 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1380 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1381 memcpy(rss_key, ucmd.rx_hash_key, len);
1382 break;
1383 }
1384 default:
1385 err = -EOPNOTSUPP;
1386 goto err;
1387 }
1388
1389 if (!ucmd.rx_hash_fields_mask) {
1390 /* special case when this TIR serves as steering entry without hashing */
1391 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1392 goto create_tir;
1393 err = -EINVAL;
1394 goto err;
1395 }
1396
1397 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1398 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1399 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1400 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1401 err = -EINVAL;
1402 goto err;
1403 }
1404
1405 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1406 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1407 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1408 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1409 MLX5_L3_PROT_TYPE_IPV4);
1410 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1411 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1412 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1413 MLX5_L3_PROT_TYPE_IPV6);
1414
1415 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1416 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1417 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1418 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1419 err = -EINVAL;
1420 goto err;
1421 }
1422
1423 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1424 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1425 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1426 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1427 MLX5_L4_PROT_TYPE_TCP);
1428 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1429 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1430 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1431 MLX5_L4_PROT_TYPE_UDP);
1432
1433 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1434 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1435 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1436
1437 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1439 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1440
1441 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1442 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1443 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1444
1445 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1446 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1447 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1448
1449 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1450
1451create_tir:
1452 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1453
1454 if (err)
1455 goto err;
1456
1457 kvfree(in);
1458 /* qpn is reserved for that QP */
1459 qp->trans_qp.base.mqp.qpn = 0;
1460 return 0;
1461
1462err:
1463 kvfree(in);
1464 return err;
1465}
1466
e126ba97
EC		 1467static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1468 struct ib_qp_init_attr *init_attr,
1469 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1470{
1471 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1472 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1473 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1474 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1475 struct mlx5_ib_cq *send_cq;
1476 struct mlx5_ib_cq *recv_cq;
1477 unsigned long flags;
cfb5e088 1478 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1479 struct mlx5_ib_create_qp ucmd;
1480 struct mlx5_ib_qp_base *base;
cfb5e088 1481 void *qpc;
09a7d9ec
SM		 1482 u32 *in;
1483 int err;
e126ba97 1484
0fb2ed66 1485 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1486 &qp->raw_packet_qp.rq.base :
1487 &qp->trans_qp.base;
1488
1489 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1490 mlx5_ib_odp_create_qp(qp);
6aec21f6 1491
e126ba97
EC		 1492 mutex_init(&qp->mutex);
1493 spin_lock_init(&qp->sq.lock);
1494 spin_lock_init(&qp->rq.lock);
1495
28d61370
YH		 1496 if (init_attr->rwq_ind_tbl) {
1497 if (!udata)
1498 return -ENOSYS;
1499
1500 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1501 return err;
1502 }
1503
f360d88a 1504 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1505 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1506 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1507 return -EINVAL;
1508 } else {
1509 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1510 }
1511 }
1512
051f2630
LR		 1513 if (init_attr->create_flags &
1514 (IB_QP_CREATE_CROSS_CHANNEL |
1515 IB_QP_CREATE_MANAGED_SEND |
1516 IB_QP_CREATE_MANAGED_RECV)) {
1517 if (!MLX5_CAP_GEN(mdev, cd)) {
1518 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1519 return -EINVAL;
1520 }
1521 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1522 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1523 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1524 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1525 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1526 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1527 }
f0313965
ES		 1528
1529 if (init_attr->qp_type == IB_QPT_UD &&
1530 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1531 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1532 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1533 return -EOPNOTSUPP;
1534 }
1535
358e42ea
MD		 1536 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1537 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1538 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1539 return -EOPNOTSUPP;
1540 }
1541 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1542 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1543 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1544 return -EOPNOTSUPP;
1545 }
1546 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1547 }
1548
e126ba97
EC		 1549 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1550 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1551
1552 if (pd && pd->uobject) {
1553 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1554 mlx5_ib_dbg(dev, "copy failed\n");
1555 return -EFAULT;
1556 }
1557
cfb5e088
HA		 1558 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1559 &ucmd, udata->inlen, &uidx);
1560 if (err)
1561 return err;
1562
e126ba97
EC		 1563 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1564 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1565 } else {
1566 qp->wq_sig = !!wq_signature;
1567 }
1568
1569 qp->has_rq = qp_has_rq(init_attr);
1570 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1571 qp, (pd && pd->uobject) ? &ucmd : NULL);
1572 if (err) {
1573 mlx5_ib_dbg(dev, "err %d\n", err);
1574 return err;
1575 }
1576
1577 if (pd) {
1578 if (pd->uobject) {
938fe83c
SM		 1579 __u32 max_wqes =
1580 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1581 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1582 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1583 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1584 mlx5_ib_dbg(dev, "invalid rq params\n");
1585 return -EINVAL;
1586 }
938fe83c 1587 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1588 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1589 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1590 return -EINVAL;
1591 }
b11a4f9c
HE		 1592 if (init_attr->create_flags &
1593 mlx5_ib_create_qp_sqpn_qp1()) {
1594 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1595 return -EINVAL;
1596 }
0fb2ed66 1597 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1598 &resp, &inlen, base);
e126ba97
EC		 1599 if (err)
1600 mlx5_ib_dbg(dev, "err %d\n", err);
1601 } else {
19098df2 1602 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1603 base);
e126ba97
EC		 1604 if (err)
1605 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1606 }
1607
1608 if (err)
1609 return err;
1610 } else {
09a7d9ec 1611 in = mlx5_vzalloc(inlen);
e126ba97
EC		 1612 if (!in)
1613 return -ENOMEM;
1614
1615 qp->create_type = MLX5_QP_EMPTY;
1616 }
1617
1618 if (is_sqp(init_attr->qp_type))
1619 qp->port = init_attr->port_num;
1620
09a7d9ec
SM		 1621 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1622
1623 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1624 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1625
1626 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1627 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1628 else
09a7d9ec
SM		 1629 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1630
e126ba97
EC		 1631
1632 if (qp->wq_sig)
09a7d9ec 1633 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1634
f360d88a 1635 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1636 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1637
051f2630 1638 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1639 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1640 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1641 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1642 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1643 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1644
e126ba97
EC		 1645 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1646 int rcqe_sz;
1647 int scqe_sz;
1648
1649 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1650 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1651
1652 if (rcqe_sz == 128)
09a7d9ec 1653 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1654 else
09a7d9ec 1655 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1656
1657 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1658 if (scqe_sz == 128)
09a7d9ec 1659 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1660 else
09a7d9ec 1661 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1662 }
1663 }
1664
1665 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1666 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1667 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1668 }
1669
09a7d9ec 1670 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97
EC		 1671
1672 if (qp->sq.wqe_cnt)
09a7d9ec 1673 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
e126ba97 1674 else
09a7d9ec 1675 MLX5_SET(qpc, qpc, no_sq, 1);
e126ba97
EC		 1676
1677 /* Set default resources */
1678 switch (init_attr->qp_type) {
1679 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1680 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1681 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1682 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1683 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1684 break;
1685 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1686 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1687 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1688 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1689 break;
1690 default:
1691 if (init_attr->srq) {
09a7d9ec
SM		 1692 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1693 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1694 } else {
09a7d9ec
SM		 1695 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1696 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1697 }
1698 }
1699
1700 if (init_attr->send_cq)
09a7d9ec 1701 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1702
1703 if (init_attr->recv_cq)
09a7d9ec 1704 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1705
09a7d9ec 1706 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1707
09a7d9ec
SM		 1708 /* 0xffffff means we ask to work with cqe version 0 */
1709 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1710 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1711
f0313965
ES		 1712 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1713 if (init_attr->qp_type == IB_QPT_UD &&
1714 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1715 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1716 qp->flags |= MLX5_IB_QP_LSO;
1717 }
cfb5e088 1718
0fb2ed66 1719 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1720 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1721 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1722 err = create_raw_packet_qp(dev, qp, in, pd);
1723 } else {
1724 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1725 }
1726
e126ba97
EC		 1727 if (err) {
1728 mlx5_ib_dbg(dev, "create qp failed\n");
1729 goto err_create;
1730 }
1731
479163f4 1732 kvfree(in);
e126ba97 1733
19098df2 1734 base->container_mibqp = qp;
1735 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1736
89ea94a7
MG		 1737 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1738 &send_cq, &recv_cq);
1739 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1740 mlx5_ib_lock_cqs(send_cq, recv_cq);
1741 /* Maintain device to QPs access, needed for further handling via reset
1742 * flow
1743 */
1744 list_add_tail(&qp->qps_list, &dev->qp_list);
1745 /* Maintain CQ to QPs access, needed for further handling via reset flow
1746 */
1747 if (send_cq)
1748 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1749 if (recv_cq)
1750 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1751 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1752 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1753
e126ba97
EC		 1754 return 0;
1755
1756err_create:
1757 if (qp->create_type == MLX5_QP_USER)
19098df2 1758 destroy_qp_user(pd, qp, base);
e126ba97
EC		 1759 else if (qp->create_type == MLX5_QP_KERNEL)
1760 destroy_qp_kernel(dev, qp);
1761
479163f4 1762 kvfree(in);
e126ba97
EC		 1763 return err;
1764}
1765
1766static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1767 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1768{
1769 if (send_cq) {
1770 if (recv_cq) {
1771 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1772 spin_lock(&send_cq->lock);
e126ba97
EC		 1773 spin_lock_nested(&recv_cq->lock,
1774 SINGLE_DEPTH_NESTING);
1775 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1776 spin_lock(&send_cq->lock);
e126ba97
EC		 1777 __acquire(&recv_cq->lock);
1778 } else {
89ea94a7 1779 spin_lock(&recv_cq->lock);
e126ba97
EC		 1780 spin_lock_nested(&send_cq->lock,
1781 SINGLE_DEPTH_NESTING);
1782 }
1783 } else {
89ea94a7 1784 spin_lock(&send_cq->lock);
6a4f139a 1785 __acquire(&recv_cq->lock);
e126ba97
EC		 1786 }
1787 } else if (recv_cq) {
89ea94a7 1788 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1789 __acquire(&send_cq->lock);
1790 } else {
1791 __acquire(&send_cq->lock);
1792 __acquire(&recv_cq->lock);
e126ba97
EC		 1793 }
1794}
1795
1796static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1797 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1798{
1799 if (send_cq) {
1800 if (recv_cq) {
1801 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1802 spin_unlock(&recv_cq->lock);
89ea94a7 1803 spin_unlock(&send_cq->lock);
e126ba97
EC		 1804 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1805 __release(&recv_cq->lock);
89ea94a7 1806 spin_unlock(&send_cq->lock);
e126ba97
EC		 1807 } else {
1808 spin_unlock(&send_cq->lock);
89ea94a7 1809 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1810 }
1811 } else {
6a4f139a 1812 __release(&recv_cq->lock);
89ea94a7 1813 spin_unlock(&send_cq->lock);
e126ba97
EC		 1814 }
1815 } else if (recv_cq) {
6a4f139a 1816 __release(&send_cq->lock);
89ea94a7 1817 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1818 } else {
1819 __release(&recv_cq->lock);
1820 __release(&send_cq->lock);
e126ba97
EC		 1821 }
1822}
1823
1824static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1825{
1826 return to_mpd(qp->ibqp.pd);
1827}
1828
89ea94a7
MG		 1829static void get_cqs(enum ib_qp_type qp_type,
1830 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1831 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1832{
89ea94a7 1833 switch (qp_type) {
e126ba97
EC		 1834 case IB_QPT_XRC_TGT:
1835 *send_cq = NULL;
1836 *recv_cq = NULL;
1837 break;
1838 case MLX5_IB_QPT_REG_UMR:
1839 case IB_QPT_XRC_INI:
89ea94a7 1840 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1841 *recv_cq = NULL;
1842 break;
1843
1844 case IB_QPT_SMI:
d16e91da 1845 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1846 case IB_QPT_RC:
1847 case IB_QPT_UC:
1848 case IB_QPT_UD:
1849 case IB_QPT_RAW_IPV6:
1850 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1851 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 1852 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1853 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 1854 break;
1855
e126ba97
EC		 1856 case IB_QPT_MAX:
1857 default:
1858 *send_cq = NULL;
1859 *recv_cq = NULL;
1860 break;
1861 }
1862}
1863
ad5f8e96 1864static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1865 u16 operation);
1866
e126ba97
EC		 1867static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1868{
1869 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1870 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
89ea94a7 1871 unsigned long flags;
e126ba97
EC		 1872 int err;
1873
28d61370
YH		 1874 if (qp->ibqp.rwq_ind_tbl) {
1875 destroy_rss_raw_qp_tir(dev, qp);
1876 return;
1877 }
1878
0fb2ed66 1879 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1880 &qp->raw_packet_qp.rq.base :
1881 &qp->trans_qp.base;
1882
6aec21f6 1883 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1884 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1885 mlx5_ib_qp_disable_pagefaults(qp);
1886 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 1887 MLX5_CMD_OP_2RST_QP, 0,
1888 NULL, &base->mqp);
ad5f8e96 1889 } else {
1890 err = modify_raw_packet_qp(dev, qp,
1891 MLX5_CMD_OP_2RST_QP);
1892 }
1893 if (err)
427c1e7b 1894 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1895 base->mqp.qpn);
6aec21f6 1896 }
e126ba97 1897
89ea94a7
MG		 1898 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1899 &send_cq, &recv_cq);
1900
1901 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1902 mlx5_ib_lock_cqs(send_cq, recv_cq);
1903 /* del from lists under both locks above to protect reset flow paths */
1904 list_del(&qp->qps_list);
1905 if (send_cq)
1906 list_del(&qp->cq_send_list);
1907
1908 if (recv_cq)
1909 list_del(&qp->cq_recv_list);
e126ba97
EC		 1910
1911 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 1912 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1913 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1914 if (send_cq != recv_cq)
19098df2 1915 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1916 NULL);
e126ba97 1917 }
89ea94a7
MG		 1918 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1919 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 1920
0fb2ed66 1921 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1922 destroy_raw_packet_qp(dev, qp);
1923 } else {
1924 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1925 if (err)
1926 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1927 base->mqp.qpn);
1928 }
e126ba97 1929
e126ba97
EC		 1930 if (qp->create_type == MLX5_QP_KERNEL)
1931 destroy_qp_kernel(dev, qp);
1932 else if (qp->create_type == MLX5_QP_USER)
19098df2 1933 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1934}
1935
1936static const char *ib_qp_type_str(enum ib_qp_type type)
1937{
1938 switch (type) {
1939 case IB_QPT_SMI:
1940 return "IB_QPT_SMI";
1941 case IB_QPT_GSI:
1942 return "IB_QPT_GSI";
1943 case IB_QPT_RC:
1944 return "IB_QPT_RC";
1945 case IB_QPT_UC:
1946 return "IB_QPT_UC";
1947 case IB_QPT_UD:
1948 return "IB_QPT_UD";
1949 case IB_QPT_RAW_IPV6:
1950 return "IB_QPT_RAW_IPV6";
1951 case IB_QPT_RAW_ETHERTYPE:
1952 return "IB_QPT_RAW_ETHERTYPE";
1953 case IB_QPT_XRC_INI:
1954 return "IB_QPT_XRC_INI";
1955 case IB_QPT_XRC_TGT:
1956 return "IB_QPT_XRC_TGT";
1957 case IB_QPT_RAW_PACKET:
1958 return "IB_QPT_RAW_PACKET";
1959 case MLX5_IB_QPT_REG_UMR:
1960 return "MLX5_IB_QPT_REG_UMR";
1961 case IB_QPT_MAX:
1962 default:
1963 return "Invalid QP type";
1964 }
1965}
1966
1967struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1968 struct ib_qp_init_attr *init_attr,
1969 struct ib_udata *udata)
1970{
1971 struct mlx5_ib_dev *dev;
1972 struct mlx5_ib_qp *qp;
1973 u16 xrcdn = 0;
1974 int err;
1975
1976 if (pd) {
1977 dev = to_mdev(pd->device);
0fb2ed66 1978
1979 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1980 if (!pd->uobject) {
1981 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1982 return ERR_PTR(-EINVAL);
1983 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1984 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1985 return ERR_PTR(-EINVAL);
1986 }
1987 }
09f16cf5
MD		 1988 } else {
1989 /* being cautious here */
1990 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1991 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1992 pr_warn("%s: no PD for transport %s\n", __func__,
1993 ib_qp_type_str(init_attr->qp_type));
1994 return ERR_PTR(-EINVAL);
1995 }
1996 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 1997 }
1998
1999 switch (init_attr->qp_type) {
2000 case IB_QPT_XRC_TGT:
2001 case IB_QPT_XRC_INI:
938fe83c 2002 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2003 mlx5_ib_dbg(dev, "XRC not supported\n");
2004 return ERR_PTR(-ENOSYS);
2005 }
2006 init_attr->recv_cq = NULL;
2007 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2008 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2009 init_attr->send_cq = NULL;
2010 }
2011
2012 /* fall through */
0fb2ed66 2013 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2014 case IB_QPT_RC:
2015 case IB_QPT_UC:
2016 case IB_QPT_UD:
2017 case IB_QPT_SMI:
d16e91da 2018 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2019 case MLX5_IB_QPT_REG_UMR:
2020 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2021 if (!qp)
2022 return ERR_PTR(-ENOMEM);
2023
2024 err = create_qp_common(dev, pd, init_attr, udata, qp);
2025 if (err) {
2026 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2027 kfree(qp);
2028 return ERR_PTR(err);
2029 }
2030
2031 if (is_qp0(init_attr->qp_type))
2032 qp->ibqp.qp_num = 0;
2033 else if (is_qp1(init_attr->qp_type))
2034 qp->ibqp.qp_num = 1;
2035 else
19098df2 2036 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2037
2038 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2039 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2040 to_mcq(init_attr->recv_cq)->mcq.cqn,
e126ba97
EC		 2041 to_mcq(init_attr->send_cq)->mcq.cqn);
2042
19098df2 2043 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2044
2045 break;
2046
d16e91da
HE		 2047 case IB_QPT_GSI:
2048 return mlx5_ib_gsi_create_qp(pd, init_attr);
2049
e126ba97
EC		 2050 case IB_QPT_RAW_IPV6:
2051 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2052 case IB_QPT_MAX:
2053 default:
2054 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2055 init_attr->qp_type);
2056 /* Don't support raw QPs */
2057 return ERR_PTR(-EINVAL);
2058 }
2059
2060 return &qp->ibqp;
2061}
2062
2063int mlx5_ib_destroy_qp(struct ib_qp *qp)
2064{
2065 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2066 struct mlx5_ib_qp *mqp = to_mqp(qp);
2067
d16e91da
HE		 2068 if (unlikely(qp->qp_type == IB_QPT_GSI))
2069 return mlx5_ib_gsi_destroy_qp(qp);
2070
e126ba97
EC		 2071 destroy_qp_common(dev, mqp);
2072
2073 kfree(mqp);
2074
2075 return 0;
2076}
2077
2078static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2079 int attr_mask)
2080{
2081 u32 hw_access_flags = 0;
2082 u8 dest_rd_atomic;
2083 u32 access_flags;
2084
2085 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2086 dest_rd_atomic = attr->max_dest_rd_atomic;
2087 else
19098df2 2088 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2089
2090 if (attr_mask & IB_QP_ACCESS_FLAGS)
2091 access_flags = attr->qp_access_flags;
2092 else
19098df2 2093 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2094
2095 if (!dest_rd_atomic)
2096 access_flags &= IB_ACCESS_REMOTE_WRITE;
2097
2098 if (access_flags & IB_ACCESS_REMOTE_READ)
2099 hw_access_flags |= MLX5_QP_BIT_RRE;
2100 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2101 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2102 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2103 hw_access_flags |= MLX5_QP_BIT_RWE;
2104
2105 return cpu_to_be32(hw_access_flags);
2106}
2107
2108enum {
2109 MLX5_PATH_FLAG_FL = 1 << 0,
2110 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2111 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2112};
2113
2114static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2115{
2116 if (rate == IB_RATE_PORT_CURRENT) {
2117 return 0;
2118 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2119 return -EINVAL;
2120 } else {
2121 while (rate != IB_RATE_2_5_GBPS &&
2122 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2123 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2124 --rate;
2125 }
2126
2127 return rate + MLX5_STAT_RATE_OFFSET;
2128}
2129
75850d0b 2130static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2131 struct mlx5_ib_sq *sq, u8 sl)
2132{
2133 void *in;
2134 void *tisc;
2135 int inlen;
2136 int err;
2137
2138 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2139 in = mlx5_vzalloc(inlen);
2140 if (!in)
2141 return -ENOMEM;
2142
2143 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2144
2145 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2146 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2147
2148 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2149
2150 kvfree(in);
2151
2152 return err;
2153}
2154
2155static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2156 const struct ib_ah_attr *ah,
e126ba97 2157 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2158 u32 path_flags, const struct ib_qp_attr *attr,
2159 bool alt)
e126ba97 2160{
2811ba51 2161 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97
EC		 2162 int err;
2163
e126ba97 2164 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2165 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2166 attr->pkey_index);
e126ba97 2167
e126ba97 2168 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 2169 if (ah->grh.sgid_index >=
2170 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2171 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 2172 ah->grh.sgid_index,
2173 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2174 return -EINVAL;
2175 }
2811ba51
AS		 2176 }
2177
2178 if (ll == IB_LINK_LAYER_ETHERNET) {
2179 if (!(ah->ah_flags & IB_AH_GRH))
2180 return -EINVAL;
2181 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2182 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2183 ah->grh.sgid_index);
2184 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2185 } else {
d3ae2bde
NO		 2186 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2187 path->fl_free_ar |=
2188 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2811ba51
AS		 2189 path->rlid = cpu_to_be16(ah->dlid);
2190 path->grh_mlid = ah->src_path_bits & 0x7f;
2191 if (ah->ah_flags & IB_AH_GRH)
2192 path->grh_mlid |= 1 << 7;
2193 path->dci_cfi_prio_sl = ah->sl & 0xf;
2194 }
2195
2196 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 2197 path->mgid_index = ah->grh.sgid_index;
2198 path->hop_limit = ah->grh.hop_limit;
2199 path->tclass_flowlabel =
2200 cpu_to_be32((ah->grh.traffic_class << 20) |
2201 (ah->grh.flow_label));
2202 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2203 }
2204
2205 err = ib_rate_to_mlx5(dev, ah->static_rate);
2206 if (err < 0)
2207 return err;
2208 path->static_rate = err;
2209 path->port = port;
2210
e126ba97 2211 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2212 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2213
75850d0b 2214 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2215 return modify_raw_packet_eth_prio(dev->mdev,
2216 &qp->raw_packet_qp.sq,
2217 ah->sl & 0xf);
2218
e126ba97
EC		 2219 return 0;
2220}
2221
2222static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2223 [MLX5_QP_STATE_INIT] = {
2224 [MLX5_QP_STATE_INIT] = {
2225 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2226 MLX5_QP_OPTPAR_RAE |
2227 MLX5_QP_OPTPAR_RWE |
2228 MLX5_QP_OPTPAR_PKEY_INDEX |
2229 MLX5_QP_OPTPAR_PRI_PORT,
2230 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2231 MLX5_QP_OPTPAR_PKEY_INDEX |
2232 MLX5_QP_OPTPAR_PRI_PORT,
2233 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2234 MLX5_QP_OPTPAR_Q_KEY |
2235 MLX5_QP_OPTPAR_PRI_PORT,
2236 },
2237 [MLX5_QP_STATE_RTR] = {
2238 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2239 MLX5_QP_OPTPAR_RRE |
2240 MLX5_QP_OPTPAR_RAE |
2241 MLX5_QP_OPTPAR_RWE |
2242 MLX5_QP_OPTPAR_PKEY_INDEX,
2243 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2244 MLX5_QP_OPTPAR_RWE |
2245 MLX5_QP_OPTPAR_PKEY_INDEX,
2246 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2247 MLX5_QP_OPTPAR_Q_KEY,
2248 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2249 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2250 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2251 MLX5_QP_OPTPAR_RRE |
2252 MLX5_QP_OPTPAR_RAE |
2253 MLX5_QP_OPTPAR_RWE |
2254 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2255 },
2256 },
2257 [MLX5_QP_STATE_RTR] = {
2258 [MLX5_QP_STATE_RTS] = {
2259 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2260 MLX5_QP_OPTPAR_RRE |
2261 MLX5_QP_OPTPAR_RAE |
2262 MLX5_QP_OPTPAR_RWE |
2263 MLX5_QP_OPTPAR_PM_STATE |
2264 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2265 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2266 MLX5_QP_OPTPAR_RWE |
2267 MLX5_QP_OPTPAR_PM_STATE,
2268 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2269 },
2270 },
2271 [MLX5_QP_STATE_RTS] = {
2272 [MLX5_QP_STATE_RTS] = {
2273 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2274 MLX5_QP_OPTPAR_RAE |
2275 MLX5_QP_OPTPAR_RWE |
2276 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2277 MLX5_QP_OPTPAR_PM_STATE |
2278 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2279 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2280 MLX5_QP_OPTPAR_PM_STATE |
2281 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2282 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2283 MLX5_QP_OPTPAR_SRQN |
2284 MLX5_QP_OPTPAR_CQN_RCV,
2285 },
2286 },
2287 [MLX5_QP_STATE_SQER] = {
2288 [MLX5_QP_STATE_RTS] = {
2289 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2290 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2291 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2292 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2293 MLX5_QP_OPTPAR_RWE |
2294 MLX5_QP_OPTPAR_RAE |
2295 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2296 },
2297 },
2298};
2299
2300static int ib_nr_to_mlx5_nr(int ib_mask)
2301{
2302 switch (ib_mask) {
2303 case IB_QP_STATE:
2304 return 0;
2305 case IB_QP_CUR_STATE:
2306 return 0;
2307 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2308 return 0;
2309 case IB_QP_ACCESS_FLAGS:
2310 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2311 MLX5_QP_OPTPAR_RAE;
2312 case IB_QP_PKEY_INDEX:
2313 return MLX5_QP_OPTPAR_PKEY_INDEX;
2314 case IB_QP_PORT:
2315 return MLX5_QP_OPTPAR_PRI_PORT;
2316 case IB_QP_QKEY:
2317 return MLX5_QP_OPTPAR_Q_KEY;
2318 case IB_QP_AV:
2319 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2320 MLX5_QP_OPTPAR_PRI_PORT;
2321 case IB_QP_PATH_MTU:
2322 return 0;
2323 case IB_QP_TIMEOUT:
2324 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2325 case IB_QP_RETRY_CNT:
2326 return MLX5_QP_OPTPAR_RETRY_COUNT;
2327 case IB_QP_RNR_RETRY:
2328 return MLX5_QP_OPTPAR_RNR_RETRY;
2329 case IB_QP_RQ_PSN:
2330 return 0;
2331 case IB_QP_MAX_QP_RD_ATOMIC:
2332 return MLX5_QP_OPTPAR_SRA_MAX;
2333 case IB_QP_ALT_PATH:
2334 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2335 case IB_QP_MIN_RNR_TIMER:
2336 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2337 case IB_QP_SQ_PSN:
2338 return 0;
2339 case IB_QP_MAX_DEST_RD_ATOMIC:
2340 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2341 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2342 case IB_QP_PATH_MIG_STATE:
2343 return MLX5_QP_OPTPAR_PM_STATE;
2344 case IB_QP_CAP:
2345 return 0;
2346 case IB_QP_DEST_QPN:
2347 return 0;
2348 }
2349 return 0;
2350}
2351
2352static int ib_mask_to_mlx5_opt(int ib_mask)
2353{
2354 int result = 0;
2355 int i;
2356
2357 for (i = 0; i < 8 * sizeof(int); i++) {
2358 if ((1 << i) & ib_mask)
2359 result |= ib_nr_to_mlx5_nr(1 << i);
2360 }
2361
2362 return result;
2363}
2364
ad5f8e96 2365static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2366 struct mlx5_ib_rq *rq, int new_state)
2367{
2368 void *in;
2369 void *rqc;
2370 int inlen;
2371 int err;
2372
2373 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2374 in = mlx5_vzalloc(inlen);
2375 if (!in)
2376 return -ENOMEM;
2377
2378 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2379
2380 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2381 MLX5_SET(rqc, rqc, state, new_state);
2382
2383 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2384 if (err)
2385 goto out;
2386
2387 rq->state = new_state;
2388
2389out:
2390 kvfree(in);
2391 return err;
2392}
2393
2394static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2395 struct mlx5_ib_sq *sq, int new_state)
2396{
2397 void *in;
2398 void *sqc;
2399 int inlen;
2400 int err;
2401
2402 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2403 in = mlx5_vzalloc(inlen);
2404 if (!in)
2405 return -ENOMEM;
2406
2407 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2408
2409 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2410 MLX5_SET(sqc, sqc, state, new_state);
2411
2412 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2413 if (err)
2414 goto out;
2415
2416 sq->state = new_state;
2417
2418out:
2419 kvfree(in);
2420 return err;
2421}
2422
2423static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2424 u16 operation)
2425{
2426 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2427 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2428 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2429 int rq_state;
2430 int sq_state;
2431 int err;
2432
2433 switch (operation) {
2434 case MLX5_CMD_OP_RST2INIT_QP:
2435 rq_state = MLX5_RQC_STATE_RDY;
2436 sq_state = MLX5_SQC_STATE_RDY;
2437 break;
2438 case MLX5_CMD_OP_2ERR_QP:
2439 rq_state = MLX5_RQC_STATE_ERR;
2440 sq_state = MLX5_SQC_STATE_ERR;
2441 break;
2442 case MLX5_CMD_OP_2RST_QP:
2443 rq_state = MLX5_RQC_STATE_RST;
2444 sq_state = MLX5_SQC_STATE_RST;
2445 break;
2446 case MLX5_CMD_OP_INIT2INIT_QP:
2447 case MLX5_CMD_OP_INIT2RTR_QP:
2448 case MLX5_CMD_OP_RTR2RTS_QP:
2449 case MLX5_CMD_OP_RTS2RTS_QP:
2450 /* Nothing to do here... */
2451 return 0;
2452 default:
2453 WARN_ON(1);
2454 return -EINVAL;
2455 }
2456
2457 if (qp->rq.wqe_cnt) {
2458 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2459 if (err)
2460 return err;
2461 }
2462
2463 if (qp->sq.wqe_cnt)
2464 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2465
2466 return 0;
2467}
2468
e126ba97
EC		 2469static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2470 const struct ib_qp_attr *attr, int attr_mask,
2471 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2472{
427c1e7b 2473 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2474 [MLX5_QP_STATE_RST] = {
2475 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2476 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2477 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2478 },
2479 [MLX5_QP_STATE_INIT] = {
2480 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2481 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2482 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2483 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2484 },
2485 [MLX5_QP_STATE_RTR] = {
2486 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2487 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2488 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2489 },
2490 [MLX5_QP_STATE_RTS] = {
2491 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2492 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2493 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2494 },
2495 [MLX5_QP_STATE_SQD] = {
2496 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2497 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2498 },
2499 [MLX5_QP_STATE_SQER] = {
2500 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2501 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2502 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2503 },
2504 [MLX5_QP_STATE_ERR] = {
2505 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2506 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2507 }
2508 };
2509
e126ba97
EC		 2510 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2511 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2512 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2513 struct mlx5_ib_cq *send_cq, *recv_cq;
2514 struct mlx5_qp_context *context;
e126ba97
EC		 2515 struct mlx5_ib_pd *pd;
2516 enum mlx5_qp_state mlx5_cur, mlx5_new;
2517 enum mlx5_qp_optpar optpar;
2518 int sqd_event;
2519 int mlx5_st;
2520 int err;
427c1e7b 2521 u16 op;
e126ba97 2522
1a412fb1
SM		 2523 context = kzalloc(sizeof(*context), GFP_KERNEL);
2524 if (!context)
e126ba97
EC		 2525 return -ENOMEM;
2526
e126ba97 2527 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2528 if (err < 0) {
2529 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2530 goto out;
158abf86 2531 }
e126ba97
EC		 2532
2533 context->flags = cpu_to_be32(err << 16);
2534
2535 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2536 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2537 } else {
2538 switch (attr->path_mig_state) {
2539 case IB_MIG_MIGRATED:
2540 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2541 break;
2542 case IB_MIG_REARM:
2543 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2544 break;
2545 case IB_MIG_ARMED:
2546 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2547 break;
2548 }
2549 }
2550
d16e91da 2551 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2552 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2553 } else if (ibqp->qp_type == IB_QPT_UD ||
2554 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2555 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2556 } else if (attr_mask & IB_QP_PATH_MTU) {
2557 if (attr->path_mtu < IB_MTU_256 ||
2558 attr->path_mtu > IB_MTU_4096) {
2559 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2560 err = -EINVAL;
2561 goto out;
2562 }
938fe83c
SM		 2563 context->mtu_msgmax = (attr->path_mtu << 5) |
2564 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2565 }
2566
2567 if (attr_mask & IB_QP_DEST_QPN)
2568 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2569
2570 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2571 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2572
2573 /* todo implement counter_index functionality */
2574
2575 if (is_sqp(ibqp->qp_type))
2576 context->pri_path.port = qp->port;
2577
2578 if (attr_mask & IB_QP_PORT)
2579 context->pri_path.port = attr->port_num;
2580
2581 if (attr_mask & IB_QP_AV) {
75850d0b 2582 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2583 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2584 attr_mask, 0, attr, false);
e126ba97
EC		 2585 if (err)
2586 goto out;
2587 }
2588
2589 if (attr_mask & IB_QP_TIMEOUT)
2590 context->pri_path.ackto_lt |= attr->timeout << 3;
2591
2592 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2593 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2594 &context->alt_path,
f879ee8d
AS		 2595 attr->alt_port_num,
2596 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2597 0, attr, true);
e126ba97
EC		 2598 if (err)
2599 goto out;
2600 }
2601
2602 pd = get_pd(qp);
89ea94a7
MG		 2603 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2604 &send_cq, &recv_cq);
e126ba97
EC		 2605
2606 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2607 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2608 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2609 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2610
2611 if (attr_mask & IB_QP_RNR_RETRY)
2612 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2613
2614 if (attr_mask & IB_QP_RETRY_CNT)
2615 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2616
2617 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2618 if (attr->max_rd_atomic)
2619 context->params1 |=
2620 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2621 }
2622
2623 if (attr_mask & IB_QP_SQ_PSN)
2624 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2625
2626 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2627 if (attr->max_dest_rd_atomic)
2628 context->params2 |=
2629 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2630 }
2631
2632 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2633 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2634
2635 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2636 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2637
2638 if (attr_mask & IB_QP_RQ_PSN)
2639 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2640
2641 if (attr_mask & IB_QP_QKEY)
2642 context->qkey = cpu_to_be32(attr->qkey);
2643
2644 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2645 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2646
2647 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2648 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2649 sqd_event = 1;
2650 else
2651 sqd_event = 0;
2652
0837e86a
MB		 2653 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2654 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2655 qp->port) - 1;
2656 struct mlx5_ib_port *mibport = &dev->port[port_num];
2657
2658 context->qp_counter_set_usr_page |=
321a9e3e 2659 cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
0837e86a
MB		 2660 }
2661
e126ba97
EC		 2662 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2663 context->sq_crq_size |= cpu_to_be16(1 << 4);
2664
b11a4f9c
HE		 2665 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2666 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2667
2668 mlx5_cur = to_mlx5_state(cur_state);
2669 mlx5_new = to_mlx5_state(new_state);
2670 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2671 if (mlx5_st < 0)
e126ba97
EC		 2672 goto out;
2673
6aec21f6
HE		 2674 /* If moving to a reset or error state, we must disable page faults on
2675 * this QP and flush all current page faults. Otherwise a stale page
2676 * fault may attempt to work on this QP after it is reset and moved
2677 * again to RTS, and may cause the driver and the device to get out of
2678 * sync. */
2679 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
ad5f8e96 2680 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2681 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2682 mlx5_ib_qp_disable_pagefaults(qp);
2683
427c1e7b 2684 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2685 !optab[mlx5_cur][mlx5_new])
2686 goto out;
2687
2688 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2689 optpar = ib_mask_to_mlx5_opt(attr_mask);
2690 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 2691
2692 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2693 err = modify_raw_packet_qp(dev, qp, op);
2694 else
1a412fb1 2695 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 2696 &base->mqp);
e126ba97
EC		 2697 if (err)
2698 goto out;
2699
ad5f8e96 2700 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2701 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2702 mlx5_ib_qp_enable_pagefaults(qp);
2703
e126ba97
EC		 2704 qp->state = new_state;
2705
2706 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2707 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2708 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2709 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2710 if (attr_mask & IB_QP_PORT)
2711 qp->port = attr->port_num;
2712 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2713 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2714
2715 /*
2716 * If we moved a kernel QP to RESET, clean up all old CQ
2717 * entries and reinitialize the QP.
2718 */
2719 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2720 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2721 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2722 if (send_cq != recv_cq)
19098df2 2723 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2724
2725 qp->rq.head = 0;
2726 qp->rq.tail = 0;
2727 qp->sq.head = 0;
2728 qp->sq.tail = 0;
2729 qp->sq.cur_post = 0;
2730 qp->sq.last_poll = 0;
2731 qp->db.db[MLX5_RCV_DBR] = 0;
2732 qp->db.db[MLX5_SND_DBR] = 0;
2733 }
2734
2735out:
1a412fb1 2736 kfree(context);
e126ba97
EC		 2737 return err;
2738}
2739
2740int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2741 int attr_mask, struct ib_udata *udata)
2742{
2743 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2744 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2745 enum ib_qp_type qp_type;
e126ba97
EC		 2746 enum ib_qp_state cur_state, new_state;
2747 int err = -EINVAL;
2748 int port;
2811ba51 2749 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2750
28d61370
YH		 2751 if (ibqp->rwq_ind_tbl)
2752 return -ENOSYS;
2753
d16e91da
HE		 2754 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2755 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2756
2757 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2758 IB_QPT_GSI : ibqp->qp_type;
2759
e126ba97
EC		 2760 mutex_lock(&qp->mutex);
2761
2762 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2763 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2764
2811ba51
AS		 2765 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2766 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2767 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2768 }
2769
d16e91da
HE		 2770 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2771 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2772 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2773 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2774 goto out;
158abf86 2775 }
e126ba97
EC		 2776
2777 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2778 (attr->port_num == 0 ||
158abf86
HE		 2779 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2780 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2781 attr->port_num, dev->num_ports);
e126ba97 2782 goto out;
158abf86 2783 }
e126ba97
EC		 2784
2785 if (attr_mask & IB_QP_PKEY_INDEX) {
2786 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2787 if (attr->pkey_index >=
158abf86
HE		 2788 dev->mdev->port_caps[port - 1].pkey_table_len) {
2789 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2790 attr->pkey_index);
e126ba97 2791 goto out;
158abf86 2792 }
e126ba97
EC		 2793 }
2794
2795 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2796 attr->max_rd_atomic >
158abf86
HE		 2797 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2798 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2799 attr->max_rd_atomic);
e126ba97 2800 goto out;
158abf86 2801 }
e126ba97
EC		 2802
2803 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2804 attr->max_dest_rd_atomic >
158abf86
HE		 2805 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2806 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2807 attr->max_dest_rd_atomic);
e126ba97 2808 goto out;
158abf86 2809 }
e126ba97
EC		 2810
2811 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2812 err = 0;
2813 goto out;
2814 }
2815
2816 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2817
2818out:
2819 mutex_unlock(&qp->mutex);
2820 return err;
2821}
2822
2823static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2824{
2825 struct mlx5_ib_cq *cq;
2826 unsigned cur;
2827
2828 cur = wq->head - wq->tail;
2829 if (likely(cur + nreq < wq->max_post))
2830 return 0;
2831
2832 cq = to_mcq(ib_cq);
2833 spin_lock(&cq->lock);
2834 cur = wq->head - wq->tail;
2835 spin_unlock(&cq->lock);
2836
2837 return cur + nreq >= wq->max_post;
2838}
2839
2840static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2841 u64 remote_addr, u32 rkey)
2842{
2843 rseg->raddr = cpu_to_be64(remote_addr);
2844 rseg->rkey = cpu_to_be32(rkey);
2845 rseg->reserved = 0;
2846}
2847
f0313965
ES		 2848static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2849 struct ib_send_wr *wr, void *qend,
2850 struct mlx5_ib_qp *qp, int *size)
2851{
2852 void *seg = eseg;
2853
2854 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2855
2856 if (wr->send_flags & IB_SEND_IP_CSUM)
2857 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2858 MLX5_ETH_WQE_L4_CSUM;
2859
2860 seg += sizeof(struct mlx5_wqe_eth_seg);
2861 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2862
2863 if (wr->opcode == IB_WR_LSO) {
2864 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2865 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2866 u64 left, leftlen, copysz;
2867 void *pdata = ud_wr->header;
2868
2869 left = ud_wr->hlen;
2870 eseg->mss = cpu_to_be16(ud_wr->mss);
2871 eseg->inline_hdr_sz = cpu_to_be16(left);
2872
2873 /*
2874 * check if there is space till the end of queue, if yes,
2875 * copy all in one shot, otherwise copy till the end of queue,
2876 * rollback and than the copy the left
2877 */
2878 leftlen = qend - (void *)eseg->inline_hdr_start;
2879 copysz = min_t(u64, leftlen, left);
2880
2881 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2882
2883 if (likely(copysz > size_of_inl_hdr_start)) {
2884 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2885 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2886 }
2887
2888 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2889 seg = mlx5_get_send_wqe(qp, 0);
2890 left -= copysz;
2891 pdata += copysz;
2892 memcpy(seg, pdata, left);
2893 seg += ALIGN(left, 16);
2894 *size += ALIGN(left, 16) / 16;
2895 }
2896 }
2897
2898 return seg;
2899}
2900
e126ba97
EC		 2901static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2902 struct ib_send_wr *wr)
2903{
e622f2f4
CH		 2904 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2905 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2906 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 2907}
2908
2909static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2910{
2911 dseg->byte_count = cpu_to_be32(sg->length);
2912 dseg->lkey = cpu_to_be32(sg->lkey);
2913 dseg->addr = cpu_to_be64(sg->addr);
2914}
2915
2916static __be16 get_klm_octo(int npages)
2917{
2918 return cpu_to_be16(ALIGN(npages, 8) / 2);
2919}
2920
2921static __be64 frwr_mkey_mask(void)
2922{
2923 u64 result;
2924
2925 result = MLX5_MKEY_MASK_LEN |
2926 MLX5_MKEY_MASK_PAGE_SIZE |
2927 MLX5_MKEY_MASK_START_ADDR |
2928 MLX5_MKEY_MASK_EN_RINVAL |
2929 MLX5_MKEY_MASK_KEY |
2930 MLX5_MKEY_MASK_LR |
2931 MLX5_MKEY_MASK_LW |
2932 MLX5_MKEY_MASK_RR |
2933 MLX5_MKEY_MASK_RW |
2934 MLX5_MKEY_MASK_A |
2935 MLX5_MKEY_MASK_SMALL_FENCE |
2936 MLX5_MKEY_MASK_FREE;
2937
2938 return cpu_to_be64(result);
2939}
2940
e6631814
SG		 2941static __be64 sig_mkey_mask(void)
2942{
2943 u64 result;
2944
2945 result = MLX5_MKEY_MASK_LEN |
2946 MLX5_MKEY_MASK_PAGE_SIZE |
2947 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 2948 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 2949 MLX5_MKEY_MASK_EN_RINVAL |
2950 MLX5_MKEY_MASK_KEY |
2951 MLX5_MKEY_MASK_LR |
2952 MLX5_MKEY_MASK_LW |
2953 MLX5_MKEY_MASK_RR |
2954 MLX5_MKEY_MASK_RW |
2955 MLX5_MKEY_MASK_SMALL_FENCE |
2956 MLX5_MKEY_MASK_FREE |
2957 MLX5_MKEY_MASK_BSF_EN;
2958
2959 return cpu_to_be64(result);
2960}
2961
8a187ee5
SG		 2962static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2963 struct mlx5_ib_mr *mr)
2964{
2965 int ndescs = mr->ndescs;
2966
2967 memset(umr, 0, sizeof(*umr));
b005d316 2968
ec22eb53 2969 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 2970 /* KLMs take twice the size of MTTs */
2971 ndescs *= 2;
2972
8a187ee5
SG		 2973 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2974 umr->klm_octowords = get_klm_octo(ndescs);
2975 umr->mkey_mask = frwr_mkey_mask();
2976}
2977
dd01e66a 2978static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 2979{
2980 memset(umr, 0, sizeof(*umr));
dd01e66a
SG		 2981 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2982 umr->flags = 1 << 7;
e126ba97
EC		 2983}
2984
968e78dd
HE		 2985static __be64 get_umr_reg_mr_mask(void)
2986{
2987 u64 result;
2988
2989 result = MLX5_MKEY_MASK_LEN |
2990 MLX5_MKEY_MASK_PAGE_SIZE |
2991 MLX5_MKEY_MASK_START_ADDR |
2992 MLX5_MKEY_MASK_PD |
2993 MLX5_MKEY_MASK_LR |
2994 MLX5_MKEY_MASK_LW |
2995 MLX5_MKEY_MASK_KEY |
2996 MLX5_MKEY_MASK_RR |
2997 MLX5_MKEY_MASK_RW |
2998 MLX5_MKEY_MASK_A |
2999 MLX5_MKEY_MASK_FREE;
3000
3001 return cpu_to_be64(result);
3002}
3003
3004static __be64 get_umr_unreg_mr_mask(void)
3005{
3006 u64 result;
3007
3008 result = MLX5_MKEY_MASK_FREE;
3009
3010 return cpu_to_be64(result);
3011}
3012
3013static __be64 get_umr_update_mtt_mask(void)
3014{
3015 u64 result;
3016
3017 result = MLX5_MKEY_MASK_FREE;
3018
3019 return cpu_to_be64(result);
3020}
3021
56e11d62
NO		 3022static __be64 get_umr_update_translation_mask(void)
3023{
3024 u64 result;
3025
3026 result = MLX5_MKEY_MASK_LEN |
3027 MLX5_MKEY_MASK_PAGE_SIZE |
3028 MLX5_MKEY_MASK_START_ADDR |
3029 MLX5_MKEY_MASK_KEY |
3030 MLX5_MKEY_MASK_FREE;
3031
3032 return cpu_to_be64(result);
3033}
3034
3035static __be64 get_umr_update_access_mask(void)
3036{
3037 u64 result;
3038
3039 result = MLX5_MKEY_MASK_LW |
3040 MLX5_MKEY_MASK_RR |
3041 MLX5_MKEY_MASK_RW |
3042 MLX5_MKEY_MASK_A |
3043 MLX5_MKEY_MASK_KEY |
3044 MLX5_MKEY_MASK_FREE;
3045
3046 return cpu_to_be64(result);
3047}
3048
3049static __be64 get_umr_update_pd_mask(void)
3050{
3051 u64 result;
3052
3053 result = MLX5_MKEY_MASK_PD |
3054 MLX5_MKEY_MASK_KEY |
3055 MLX5_MKEY_MASK_FREE;
3056
3057 return cpu_to_be64(result);
3058}
3059
e126ba97
EC		 3060static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3061 struct ib_send_wr *wr)
3062{
e622f2f4 3063 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3064
3065 memset(umr, 0, sizeof(*umr));
3066
968e78dd
HE		 3067 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3068 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3069 else
3070 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3071
e126ba97 3072 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
e126ba97 3073 umr->klm_octowords = get_klm_octo(umrwr->npages);
968e78dd
HE		 3074 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3075 umr->mkey_mask = get_umr_update_mtt_mask();
3076 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3077 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
968e78dd 3078 }
56e11d62
NO		 3079 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3080 umr->mkey_mask |= get_umr_update_translation_mask();
3081 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3082 umr->mkey_mask |= get_umr_update_access_mask();
3083 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3084 umr->mkey_mask |= get_umr_update_pd_mask();
3085 if (!umr->mkey_mask)
3086 umr->mkey_mask = get_umr_reg_mr_mask();
e126ba97 3087 } else {
968e78dd 3088 umr->mkey_mask = get_umr_unreg_mr_mask();
e126ba97
EC		 3089 }
3090
3091 if (!wr->num_sge)
968e78dd 3092 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3093}
3094
3095static u8 get_umr_flags(int acc)
3096{
3097 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3098 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3099 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3100 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3101 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3102}
3103
8a187ee5
SG		 3104static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3105 struct mlx5_ib_mr *mr,
3106 u32 key, int access)
3107{
3108 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3109
3110 memset(seg, 0, sizeof(*seg));
b005d316 3111
ec22eb53 3112 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3113 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3114 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3115 /* KLMs take twice the size of MTTs */
3116 ndescs *= 2;
3117
3118 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3119 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3120 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3121 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3122 seg->len = cpu_to_be64(mr->ibmr.length);
3123 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3124}
3125
dd01e66a 3126static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3127{
3128 memset(seg, 0, sizeof(*seg));
dd01e66a 3129 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3130}
3131
3132static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3133{
e622f2f4 3134 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3135
e126ba97
EC		 3136 memset(seg, 0, sizeof(*seg));
3137 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
968e78dd 3138 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3139 return;
3140 }
3141
968e78dd
HE		 3142 seg->flags = convert_access(umrwr->access_flags);
3143 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
56e11d62
NO		 3144 if (umrwr->pd)
3145 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
968e78dd
HE		 3146 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3147 }
3148 seg->len = cpu_to_be64(umrwr->length);
3149 seg->log2_page_size = umrwr->page_shift;
746b5583 3150 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3151 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3152}
3153
8a187ee5
SG		 3154static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3155 struct mlx5_ib_mr *mr,
3156 struct mlx5_ib_pd *pd)
3157{
3158 int bcount = mr->desc_size * mr->ndescs;
3159
3160 dseg->addr = cpu_to_be64(mr->desc_map);
3161 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3162 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3163}
3164
e126ba97
EC		 3165static __be32 send_ieth(struct ib_send_wr *wr)
3166{
3167 switch (wr->opcode) {
3168 case IB_WR_SEND_WITH_IMM:
3169 case IB_WR_RDMA_WRITE_WITH_IMM:
3170 return wr->ex.imm_data;
3171
3172 case IB_WR_SEND_WITH_INV:
3173 return cpu_to_be32(wr->ex.invalidate_rkey);
3174
3175 default:
3176 return 0;
3177 }
3178}
3179
3180static u8 calc_sig(void *wqe, int size)
3181{
3182 u8 *p = wqe;
3183 u8 res = 0;
3184 int i;
3185
3186 for (i = 0; i < size; i++)
3187 res ^= p[i];
3188
3189 return ~res;
3190}
3191
3192static u8 wq_sig(void *wqe)
3193{
3194 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3195}
3196
3197static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3198 void *wqe, int *sz)
3199{
3200 struct mlx5_wqe_inline_seg *seg;
3201 void *qend = qp->sq.qend;
3202 void *addr;
3203 int inl = 0;
3204 int copy;
3205 int len;
3206 int i;
3207
3208 seg = wqe;
3209 wqe += sizeof(*seg);
3210 for (i = 0; i < wr->num_sge; i++) {
3211 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3212 len = wr->sg_list[i].length;
3213 inl += len;
3214
3215 if (unlikely(inl > qp->max_inline_data))
3216 return -ENOMEM;
3217
3218 if (unlikely(wqe + len > qend)) {
3219 copy = qend - wqe;
3220 memcpy(wqe, addr, copy);
3221 addr += copy;
3222 len -= copy;
3223 wqe = mlx5_get_send_wqe(qp, 0);
3224 }
3225 memcpy(wqe, addr, len);
3226 wqe += len;
3227 }
3228
3229 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3230
3231 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3232
3233 return 0;
3234}
3235
e6631814
SG		 3236static u16 prot_field_size(enum ib_signature_type type)
3237{
3238 switch (type) {
3239 case IB_SIG_TYPE_T10_DIF:
3240 return MLX5_DIF_SIZE;
3241 default:
3242 return 0;
3243 }
3244}
3245
3246static u8 bs_selector(int block_size)
3247{
3248 switch (block_size) {
3249 case 512: return 0x1;
3250 case 520: return 0x2;
3251 case 4096: return 0x3;
3252 case 4160: return 0x4;
3253 case 1073741824: return 0x5;
3254 default: return 0;
3255 }
3256}
3257
78eda2bb
SG		 3258static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3259 struct mlx5_bsf_inl *inl)
e6631814 3260{
142537f4
SG		 3261 /* Valid inline section and allow BSF refresh */
3262 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3263 MLX5_BSF_REFRESH_DIF);
3264 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3265 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3266 /* repeating block */
3267 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3268 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3269 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3270
78eda2bb
SG		 3271 if (domain->sig.dif.ref_remap)
3272 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3273
78eda2bb
SG		 3274 if (domain->sig.dif.app_escape) {
3275 if (domain->sig.dif.ref_escape)
3276 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3277 else
3278 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3279 }
3280
78eda2bb
SG		 3281 inl->dif_app_bitmask_check =
3282 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3283}
3284
3285static int mlx5_set_bsf(struct ib_mr *sig_mr,
3286 struct ib_sig_attrs *sig_attrs,
3287 struct mlx5_bsf *bsf, u32 data_size)
3288{
3289 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3290 struct mlx5_bsf_basic *basic = &bsf->basic;
3291 struct ib_sig_domain *mem = &sig_attrs->mem;
3292 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3293
c7f44fbd 3294 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3295
3296 /* Basic + Extended + Inline */
3297 basic->bsf_size_sbs = 1 << 7;
3298 /* Input domain check byte mask */
3299 basic->check_byte_mask = sig_attrs->check_mask;
3300 basic->raw_data_size = cpu_to_be32(data_size);
3301
3302 /* Memory domain */
e6631814 3303 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3304 case IB_SIG_TYPE_NONE:
3305 break;
e6631814 3306 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3307 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3308 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3309 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3310 break;
3311 default:
3312 return -EINVAL;
3313 }
e6631814 3314
78eda2bb
SG		 3315 /* Wire domain */
3316 switch (sig_attrs->wire.sig_type) {
3317 case IB_SIG_TYPE_NONE:
3318 break;
3319 case IB_SIG_TYPE_T10_DIF:
e6631814 3320 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3321 mem->sig_type == wire->sig_type) {
e6631814 3322 /* Same block structure */
142537f4 3323 basic->bsf_size_sbs |= 1 << 4;
e6631814 3324 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3325 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3326 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3327 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3328 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3329 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3330 } else
3331 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3332
142537f4 3333 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3334 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3335 break;
e6631814
SG		 3336 default:
3337 return -EINVAL;
3338 }
3339
3340 return 0;
3341}
3342
e622f2f4
CH		 3343static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3344 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3345{
e622f2f4
CH		 3346 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3347 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3348 struct mlx5_bsf *bsf;
e622f2f4
CH		 3349 u32 data_len = wr->wr.sg_list->length;
3350 u32 data_key = wr->wr.sg_list->lkey;
3351 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3352 int ret;
3353 int wqe_size;
3354
e622f2f4
CH		 3355 if (!wr->prot ||
3356 (data_key == wr->prot->lkey &&
3357 data_va == wr->prot->addr &&
3358 data_len == wr->prot->length)) {
e6631814
SG		 3359 /**
3360 * Source domain doesn't contain signature information
5c273b16 3361 * or data and protection are interleaved in memory.
e6631814
SG		 3362 * So need construct:
3363 * ------------------
3364 * | data_klm |
3365 * ------------------
3366 * | BSF |
3367 * ------------------
3368 **/
3369 struct mlx5_klm *data_klm = *seg;
3370
3371 data_klm->bcount = cpu_to_be32(data_len);
3372 data_klm->key = cpu_to_be32(data_key);
3373 data_klm->va = cpu_to_be64(data_va);
3374 wqe_size = ALIGN(sizeof(*data_klm), 64);
3375 } else {
3376 /**
3377 * Source domain contains signature information
3378 * So need construct a strided block format:
3379 * ---------------------------
3380 * | stride_block_ctrl |
3381 * ---------------------------
3382 * | data_klm |
3383 * ---------------------------
3384 * | prot_klm |
3385 * ---------------------------
3386 * | BSF |
3387 * ---------------------------
3388 **/
3389 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3390 struct mlx5_stride_block_entry *data_sentry;
3391 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3392 u32 prot_key = wr->prot->lkey;
3393 u64 prot_va = wr->prot->addr;
e6631814
SG		 3394 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3395 int prot_size;
3396
3397 sblock_ctrl = *seg;
3398 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3399 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3400
3401 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3402 if (!prot_size) {
3403 pr_err("Bad block size given: %u\n", block_size);
3404 return -EINVAL;
3405 }
3406 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3407 prot_size);
3408 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3409 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3410 sblock_ctrl->num_entries = cpu_to_be16(2);
3411
3412 data_sentry->bcount = cpu_to_be16(block_size);
3413 data_sentry->key = cpu_to_be32(data_key);
3414 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3415 data_sentry->stride = cpu_to_be16(block_size);
3416
e6631814
SG		 3417 prot_sentry->bcount = cpu_to_be16(prot_size);
3418 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3419 prot_sentry->va = cpu_to_be64(prot_va);
3420 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3421
e6631814
SG		 3422 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3423 sizeof(*prot_sentry), 64);
3424 }
3425
3426 *seg += wqe_size;
3427 *size += wqe_size / 16;
3428 if (unlikely((*seg == qp->sq.qend)))
3429 *seg = mlx5_get_send_wqe(qp, 0);
3430
3431 bsf = *seg;
3432 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3433 if (ret)
3434 return -EINVAL;
3435
3436 *seg += sizeof(*bsf);
3437 *size += sizeof(*bsf) / 16;
3438 if (unlikely((*seg == qp->sq.qend)))
3439 *seg = mlx5_get_send_wqe(qp, 0);
3440
3441 return 0;
3442}
3443
3444static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
e622f2f4 3445 struct ib_sig_handover_wr *wr, u32 nelements,
e6631814
SG		 3446 u32 length, u32 pdn)
3447{
e622f2f4 3448 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3449 u32 sig_key = sig_mr->rkey;
d5436ba0 3450 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3451
3452 memset(seg, 0, sizeof(*seg));
3453
e622f2f4 3454 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 3455 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 3456 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3457 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3458 MLX5_MKEY_BSF_EN | pdn);
3459 seg->len = cpu_to_be64(length);
3460 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3461 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3462}
3463
3464static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
e622f2f4 3465 u32 nelements)
e6631814
SG		 3466{
3467 memset(umr, 0, sizeof(*umr));
3468
3469 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3470 umr->klm_octowords = get_klm_octo(nelements);
3471 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3472 umr->mkey_mask = sig_mkey_mask();
3473}
3474
3475
e622f2f4 3476static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3477 void **seg, int *size)
3478{
e622f2f4
CH		 3479 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3480 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814
SG		 3481 u32 pdn = get_pd(qp)->pdn;
3482 u32 klm_oct_size;
3483 int region_len, ret;
3484
e622f2f4
CH		 3485 if (unlikely(wr->wr.num_sge != 1) ||
3486 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3487 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3488 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3489 return -EINVAL;
3490
3491 /* length of the protected region, data + protection */
e622f2f4
CH		 3492 region_len = wr->wr.sg_list->length;
3493 if (wr->prot &&
3494 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3495 wr->prot->addr != wr->wr.sg_list->addr ||
3496 wr->prot->length != wr->wr.sg_list->length))
3497 region_len += wr->prot->length;
e6631814
SG		 3498
3499 /**
3500 * KLM octoword size - if protection was provided
3501 * then we use strided block format (3 octowords),
3502 * else we use single KLM (1 octoword)
3503 **/
e622f2f4 3504 klm_oct_size = wr->prot ? 3 : 1;
e6631814 3505
e622f2f4 3506 set_sig_umr_segment(*seg, klm_oct_size);
e6631814
SG		 3507 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3508 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3509 if (unlikely((*seg == qp->sq.qend)))
3510 *seg = mlx5_get_send_wqe(qp, 0);
3511
3512 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3513 *seg += sizeof(struct mlx5_mkey_seg);
3514 *size += sizeof(struct mlx5_mkey_seg) / 16;
3515 if (unlikely((*seg == qp->sq.qend)))
3516 *seg = mlx5_get_send_wqe(qp, 0);
3517
3518 ret = set_sig_data_segment(wr, qp, seg, size);
3519 if (ret)
3520 return ret;
3521
d5436ba0 3522 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3523 return 0;
3524}
3525
3526static int set_psv_wr(struct ib_sig_domain *domain,
3527 u32 psv_idx, void **seg, int *size)
3528{
3529 struct mlx5_seg_set_psv *psv_seg = *seg;
3530
3531 memset(psv_seg, 0, sizeof(*psv_seg));
3532 psv_seg->psv_num = cpu_to_be32(psv_idx);
3533 switch (domain->sig_type) {
78eda2bb
SG		 3534 case IB_SIG_TYPE_NONE:
3535 break;
e6631814
SG		 3536 case IB_SIG_TYPE_T10_DIF:
3537 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3538 domain->sig.dif.app_tag);
3539 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3540 break;
e6631814
SG		 3541 default:
3542 pr_err("Bad signature type given.\n");
3543 return 1;
3544 }
3545
78eda2bb
SG		 3546 *seg += sizeof(*psv_seg);
3547 *size += sizeof(*psv_seg) / 16;
3548
e6631814
SG		 3549 return 0;
3550}
3551
8a187ee5
SG		 3552static int set_reg_wr(struct mlx5_ib_qp *qp,
3553 struct ib_reg_wr *wr,
3554 void **seg, int *size)
3555{
3556 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3557 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3558
3559 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3560 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3561 "Invalid IB_SEND_INLINE send flag\n");
3562 return -EINVAL;
3563 }
3564
3565 set_reg_umr_seg(*seg, mr);
3566 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3567 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3568 if (unlikely((*seg == qp->sq.qend)))
3569 *seg = mlx5_get_send_wqe(qp, 0);
3570
3571 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3572 *seg += sizeof(struct mlx5_mkey_seg);
3573 *size += sizeof(struct mlx5_mkey_seg) / 16;
3574 if (unlikely((*seg == qp->sq.qend)))
3575 *seg = mlx5_get_send_wqe(qp, 0);
3576
3577 set_reg_data_seg(*seg, mr, pd);
3578 *seg += sizeof(struct mlx5_wqe_data_seg);
3579 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3580
3581 return 0;
3582}
3583
dd01e66a 3584static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3585{
dd01e66a 3586 set_linv_umr_seg(*seg);
e126ba97
EC		 3587 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3588 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3589 if (unlikely((*seg == qp->sq.qend)))
3590 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3591 set_linv_mkey_seg(*seg);
e126ba97
EC		 3592 *seg += sizeof(struct mlx5_mkey_seg);
3593 *size += sizeof(struct mlx5_mkey_seg) / 16;
3594 if (unlikely((*seg == qp->sq.qend)))
3595 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3596}
3597
3598static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3599{
3600 __be32 *p = NULL;
3601 int tidx = idx;
3602 int i, j;
3603
3604 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3605 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3606 if ((i & 0xf) == 0) {
3607 void *buf = mlx5_get_send_wqe(qp, tidx);
3608 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3609 p = buf;
3610 j = 0;
3611 }
3612 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3613 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3614 be32_to_cpu(p[j + 3]));
3615 }
3616}
3617
3618static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3619 unsigned bytecnt, struct mlx5_ib_qp *qp)
3620{
3621 while (bytecnt > 0) {
3622 __iowrite64_copy(dst++, src++, 8);
3623 __iowrite64_copy(dst++, src++, 8);
3624 __iowrite64_copy(dst++, src++, 8);
3625 __iowrite64_copy(dst++, src++, 8);
3626 __iowrite64_copy(dst++, src++, 8);
3627 __iowrite64_copy(dst++, src++, 8);
3628 __iowrite64_copy(dst++, src++, 8);
3629 __iowrite64_copy(dst++, src++, 8);
3630 bytecnt -= 64;
3631 if (unlikely(src == qp->sq.qend))
3632 src = mlx5_get_send_wqe(qp, 0);
3633 }
3634}
3635
3636static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3637{
3638 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3639 wr->send_flags & IB_SEND_FENCE))
3640 return MLX5_FENCE_MODE_STRONG_ORDERING;
3641
3642 if (unlikely(fence)) {
3643 if (wr->send_flags & IB_SEND_FENCE)
3644 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3645 else
3646 return fence;
c9b25495
EC		 3647 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3648 return MLX5_FENCE_MODE_FENCE;
e126ba97 3649 }
c9b25495
EC		 3650
3651 return 0;
e126ba97
EC		 3652}
3653
6e5eadac
SG		 3654static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3655 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3656 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3657 int *size, int nreq)
3658{
3659 int err = 0;
3660
3661 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3662 err = -ENOMEM;
3663 return err;
3664 }
3665
3666 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3667 *seg = mlx5_get_send_wqe(qp, *idx);
3668 *ctrl = *seg;
3669 *(uint32_t *)(*seg + 8) = 0;
3670 (*ctrl)->imm = send_ieth(wr);
3671 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3672 (wr->send_flags & IB_SEND_SIGNALED ?
3673 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3674 (wr->send_flags & IB_SEND_SOLICITED ?
3675 MLX5_WQE_CTRL_SOLICITED : 0);
3676
3677 *seg += sizeof(**ctrl);
3678 *size = sizeof(**ctrl) / 16;
3679
3680 return err;
3681}
3682
3683static void finish_wqe(struct mlx5_ib_qp *qp,
3684 struct mlx5_wqe_ctrl_seg *ctrl,
3685 u8 size, unsigned idx, u64 wr_id,
3686 int nreq, u8 fence, u8 next_fence,
3687 u32 mlx5_opcode)
3688{
3689 u8 opmod = 0;
3690
3691 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3692 mlx5_opcode | ((u32)opmod << 24));
19098df2 3693 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3694 ctrl->fm_ce_se |= fence;
3695 qp->fm_cache = next_fence;
3696 if (unlikely(qp->wq_sig))
3697 ctrl->signature = wq_sig(ctrl);
3698
3699 qp->sq.wrid[idx] = wr_id;
3700 qp->sq.w_list[idx].opcode = mlx5_opcode;
3701 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3702 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3703 qp->sq.w_list[idx].next = qp->sq.cur_post;
3704}
3705
3706
e126ba97
EC		 3707int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3708 struct ib_send_wr **bad_wr)
3709{
3710 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3711 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 3712 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 3713 struct mlx5_ib_qp *qp;
e6631814 3714 struct mlx5_ib_mr *mr;
e126ba97
EC		 3715 struct mlx5_wqe_data_seg *dpseg;
3716 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3717 struct mlx5_bf *bf;
e126ba97 3718 int uninitialized_var(size);
d16e91da 3719 void *qend;
e126ba97 3720 unsigned long flags;
e126ba97
EC		 3721 unsigned idx;
3722 int err = 0;
3723 int inl = 0;
3724 int num_sge;
3725 void *seg;
3726 int nreq;
3727 int i;
3728 u8 next_fence = 0;
e126ba97
EC		 3729 u8 fence;
3730
d16e91da
HE		 3731 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3732 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3733
3734 qp = to_mqp(ibqp);
3735 bf = qp->bf;
3736 qend = qp->sq.qend;
3737
e126ba97
EC		 3738 spin_lock_irqsave(&qp->sq.lock, flags);
3739
89ea94a7
MG		 3740 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3741 err = -EIO;
3742 *bad_wr = wr;
3743 nreq = 0;
3744 goto out;
3745 }
3746
e126ba97 3747 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3748 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3749 mlx5_ib_warn(dev, "\n");
3750 err = -EINVAL;
3751 *bad_wr = wr;
3752 goto out;
3753 }
3754
6e5eadac
SG		 3755 fence = qp->fm_cache;
3756 num_sge = wr->num_sge;
3757 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97
EC		 3758 mlx5_ib_warn(dev, "\n");
3759 err = -ENOMEM;
3760 *bad_wr = wr;
3761 goto out;
3762 }
3763
6e5eadac
SG		 3764 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3765 if (err) {
e126ba97
EC		 3766 mlx5_ib_warn(dev, "\n");
3767 err = -ENOMEM;
3768 *bad_wr = wr;
3769 goto out;
3770 }
3771
e126ba97
EC		 3772 switch (ibqp->qp_type) {
3773 case IB_QPT_XRC_INI:
3774 xrc = seg;
e126ba97
EC		 3775 seg += sizeof(*xrc);
3776 size += sizeof(*xrc) / 16;
3777 /* fall through */
3778 case IB_QPT_RC:
3779 switch (wr->opcode) {
3780 case IB_WR_RDMA_READ:
3781 case IB_WR_RDMA_WRITE:
3782 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3783 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3784 rdma_wr(wr)->rkey);
f241e749 3785 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3786 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3787 break;
3788
3789 case IB_WR_ATOMIC_CMP_AND_SWP:
3790 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3791 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3792 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3793 err = -ENOSYS;
3794 *bad_wr = wr;
3795 goto out;
e126ba97
EC		 3796
3797 case IB_WR_LOCAL_INV:
3798 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3799 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3800 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3801 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3802 num_sge = 0;
3803 break;
3804
8a187ee5
SG		 3805 case IB_WR_REG_MR:
3806 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3807 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3808 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3809 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3810 if (err) {
3811 *bad_wr = wr;
3812 goto out;
3813 }
3814 num_sge = 0;
3815 break;
3816
e6631814
SG		 3817 case IB_WR_REG_SIG_MR:
3818 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3819 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3820
3821 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3822 err = set_sig_umr_wr(wr, qp, &seg, &size);
3823 if (err) {
3824 mlx5_ib_warn(dev, "\n");
3825 *bad_wr = wr;
3826 goto out;
3827 }
3828
3829 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3830 nreq, get_fence(fence, wr),
3831 next_fence, MLX5_OPCODE_UMR);
3832 /*
3833 * SET_PSV WQEs are not signaled and solicited
3834 * on error
3835 */
3836 wr->send_flags &= ~IB_SEND_SIGNALED;
3837 wr->send_flags |= IB_SEND_SOLICITED;
3838 err = begin_wqe(qp, &seg, &ctrl, wr,
3839 &idx, &size, nreq);
3840 if (err) {
3841 mlx5_ib_warn(dev, "\n");
3842 err = -ENOMEM;
3843 *bad_wr = wr;
3844 goto out;
3845 }
3846
e622f2f4 3847 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3848 mr->sig->psv_memory.psv_idx, &seg,
3849 &size);
3850 if (err) {
3851 mlx5_ib_warn(dev, "\n");
3852 *bad_wr = wr;
3853 goto out;
3854 }
3855
3856 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3857 nreq, get_fence(fence, wr),
3858 next_fence, MLX5_OPCODE_SET_PSV);
3859 err = begin_wqe(qp, &seg, &ctrl, wr,
3860 &idx, &size, nreq);
3861 if (err) {
3862 mlx5_ib_warn(dev, "\n");
3863 err = -ENOMEM;
3864 *bad_wr = wr;
3865 goto out;
3866 }
3867
3868 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3869 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3870 mr->sig->psv_wire.psv_idx, &seg,
3871 &size);
3872 if (err) {
3873 mlx5_ib_warn(dev, "\n");
3874 *bad_wr = wr;
3875 goto out;
3876 }
3877
3878 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3879 nreq, get_fence(fence, wr),
3880 next_fence, MLX5_OPCODE_SET_PSV);
3881 num_sge = 0;
3882 goto skip_psv;
3883
e126ba97
EC		 3884 default:
3885 break;
3886 }
3887 break;
3888
3889 case IB_QPT_UC:
3890 switch (wr->opcode) {
3891 case IB_WR_RDMA_WRITE:
3892 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3893 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3894 rdma_wr(wr)->rkey);
e126ba97
EC		 3895 seg += sizeof(struct mlx5_wqe_raddr_seg);
3896 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3897 break;
3898
3899 default:
3900 break;
3901 }
3902 break;
3903
e126ba97 3904 case IB_QPT_SMI:
d16e91da 3905 case MLX5_IB_QPT_HW_GSI:
e126ba97 3906 set_datagram_seg(seg, wr);
f241e749 3907 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 3908 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3909 if (unlikely((seg == qend)))
3910 seg = mlx5_get_send_wqe(qp, 0);
3911 break;
f0313965
ES		 3912 case IB_QPT_UD:
3913 set_datagram_seg(seg, wr);
3914 seg += sizeof(struct mlx5_wqe_datagram_seg);
3915 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3916
3917 if (unlikely((seg == qend)))
3918 seg = mlx5_get_send_wqe(qp, 0);
3919
3920 /* handle qp that supports ud offload */
3921 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3922 struct mlx5_wqe_eth_pad *pad;
e126ba97 3923
f0313965
ES		 3924 pad = seg;
3925 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3926 seg += sizeof(struct mlx5_wqe_eth_pad);
3927 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3928
3929 seg = set_eth_seg(seg, wr, qend, qp, &size);
3930
3931 if (unlikely((seg == qend)))
3932 seg = mlx5_get_send_wqe(qp, 0);
3933 }
3934 break;
e126ba97
EC		 3935 case MLX5_IB_QPT_REG_UMR:
3936 if (wr->opcode != MLX5_IB_WR_UMR) {
3937 err = -EINVAL;
3938 mlx5_ib_warn(dev, "bad opcode\n");
3939 goto out;
3940 }
3941 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 3942 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
e126ba97
EC		 3943 set_reg_umr_segment(seg, wr);
3944 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3945 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3946 if (unlikely((seg == qend)))
3947 seg = mlx5_get_send_wqe(qp, 0);
3948 set_reg_mkey_segment(seg, wr);
3949 seg += sizeof(struct mlx5_mkey_seg);
3950 size += sizeof(struct mlx5_mkey_seg) / 16;
3951 if (unlikely((seg == qend)))
3952 seg = mlx5_get_send_wqe(qp, 0);
3953 break;
3954
3955 default:
3956 break;
3957 }
3958
3959 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3960 int uninitialized_var(sz);
3961
3962 err = set_data_inl_seg(qp, wr, seg, &sz);
3963 if (unlikely(err)) {
3964 mlx5_ib_warn(dev, "\n");
3965 *bad_wr = wr;
3966 goto out;
3967 }
3968 inl = 1;
3969 size += sz;
3970 } else {
3971 dpseg = seg;
3972 for (i = 0; i < num_sge; i++) {
3973 if (unlikely(dpseg == qend)) {
3974 seg = mlx5_get_send_wqe(qp, 0);
3975 dpseg = seg;
3976 }
3977 if (likely(wr->sg_list[i].length)) {
3978 set_data_ptr_seg(dpseg, wr->sg_list + i);
3979 size += sizeof(struct mlx5_wqe_data_seg) / 16;
3980 dpseg++;
3981 }
3982 }
3983 }
3984
6e5eadac
SG		 3985 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3986 get_fence(fence, wr), next_fence,
3987 mlx5_ib_opcode[wr->opcode]);
e6631814 3988skip_psv:
e126ba97
EC		 3989 if (0)
3990 dump_wqe(qp, idx, size);
3991 }
3992
3993out:
3994 if (likely(nreq)) {
3995 qp->sq.head += nreq;
3996
3997 /* Make sure that descriptors are written before
3998 * updating doorbell record and ringing the doorbell
3999 */
4000 wmb();
4001
4002 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4003
ada388f7
EC		 4004 /* Make sure doorbell record is visible to the HCA before
4005 * we hit doorbell */
4006 wmb();
4007
e126ba97
EC		 4008 if (bf->need_lock)
4009 spin_lock(&bf->lock);
6a4f139a
EC		 4010 else
4011 __acquire(&bf->lock);
e126ba97
EC		 4012
4013 /* TBD enable WC */
4014 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4015 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4016 /* wc_wmb(); */
4017 } else {
4018 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4019 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4020 /* Make sure doorbells don't leak out of SQ spinlock
4021 * and reach the HCA out of order.
4022 */
4023 mmiowb();
4024 }
4025 bf->offset ^= bf->buf_size;
4026 if (bf->need_lock)
4027 spin_unlock(&bf->lock);
6a4f139a
EC		 4028 else
4029 __release(&bf->lock);
e126ba97
EC		 4030 }
4031
4032 spin_unlock_irqrestore(&qp->sq.lock, flags);
4033
4034 return err;
4035}
4036
4037static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4038{
4039 sig->signature = calc_sig(sig, size);
4040}
4041
4042int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4043 struct ib_recv_wr **bad_wr)
4044{
4045 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4046 struct mlx5_wqe_data_seg *scat;
4047 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4048 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4049 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4050 unsigned long flags;
4051 int err = 0;
4052 int nreq;
4053 int ind;
4054 int i;
4055
d16e91da
HE		 4056 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4057 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4058
e126ba97
EC		 4059 spin_lock_irqsave(&qp->rq.lock, flags);
4060
89ea94a7
MG		 4061 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4062 err = -EIO;
4063 *bad_wr = wr;
4064 nreq = 0;
4065 goto out;
4066 }
4067
e126ba97
EC		 4068 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4069
4070 for (nreq = 0; wr; nreq++, wr = wr->next) {
4071 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4072 err = -ENOMEM;
4073 *bad_wr = wr;
4074 goto out;
4075 }
4076
4077 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4078 err = -EINVAL;
4079 *bad_wr = wr;
4080 goto out;
4081 }
4082
4083 scat = get_recv_wqe(qp, ind);
4084 if (qp->wq_sig)
4085 scat++;
4086
4087 for (i = 0; i < wr->num_sge; i++)
4088 set_data_ptr_seg(scat + i, wr->sg_list + i);
4089
4090 if (i < qp->rq.max_gs) {
4091 scat[i].byte_count = 0;
4092 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4093 scat[i].addr = 0;
4094 }
4095
4096 if (qp->wq_sig) {
4097 sig = (struct mlx5_rwqe_sig *)scat;
4098 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4099 }
4100
4101 qp->rq.wrid[ind] = wr->wr_id;
4102
4103 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4104 }
4105
4106out:
4107 if (likely(nreq)) {
4108 qp->rq.head += nreq;
4109
4110 /* Make sure that descriptors are written before
4111 * doorbell record.
4112 */
4113 wmb();
4114
4115 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4116 }
4117
4118 spin_unlock_irqrestore(&qp->rq.lock, flags);
4119
4120 return err;
4121}
4122
4123static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4124{
4125 switch (mlx5_state) {
4126 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4127 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4128 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4129 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4130 case MLX5_QP_STATE_SQ_DRAINING:
4131 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4132 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4133 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4134 default: return -1;
4135 }
4136}
4137
4138static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4139{
4140 switch (mlx5_mig_state) {
4141 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4142 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4143 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4144 default: return -1;
4145 }
4146}
4147
4148static int to_ib_qp_access_flags(int mlx5_flags)
4149{
4150 int ib_flags = 0;
4151
4152 if (mlx5_flags & MLX5_QP_BIT_RRE)
4153 ib_flags |= IB_ACCESS_REMOTE_READ;
4154 if (mlx5_flags & MLX5_QP_BIT_RWE)
4155 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4156 if (mlx5_flags & MLX5_QP_BIT_RAE)
4157 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4158
4159 return ib_flags;
4160}
4161
4162static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4163 struct mlx5_qp_path *path)
4164{
9603b61d 4165 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 4166
4167 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4168 ib_ah_attr->port_num = path->port;
4169
c7a08ac7 4170 if (ib_ah_attr->port_num == 0 ||
938fe83c 4171 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4172 return;
4173
2811ba51 4174 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 4175
4176 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
4177 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4178 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
4179 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4180 if (ib_ah_attr->ah_flags) {
4181 ib_ah_attr->grh.sgid_index = path->mgid_index;
4182 ib_ah_attr->grh.hop_limit = path->hop_limit;
4183 ib_ah_attr->grh.traffic_class =
4184 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4185 ib_ah_attr->grh.flow_label =
4186 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4187 memcpy(ib_ah_attr->grh.dgid.raw,
4188 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4189 }
4190}
4191
6d2f89df 4192static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4193 struct mlx5_ib_sq *sq,
4194 u8 *sq_state)
4195{
4196 void *out;
4197 void *sqc;
4198 int inlen;
4199 int err;
4200
4201 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4202 out = mlx5_vzalloc(inlen);
4203 if (!out)
4204 return -ENOMEM;
4205
4206 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4207 if (err)
4208 goto out;
4209
4210 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4211 *sq_state = MLX5_GET(sqc, sqc, state);
4212 sq->state = *sq_state;
4213
4214out:
4215 kvfree(out);
4216 return err;
4217}
4218
4219static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4220 struct mlx5_ib_rq *rq,
4221 u8 *rq_state)
4222{
4223 void *out;
4224 void *rqc;
4225 int inlen;
4226 int err;
4227
4228 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4229 out = mlx5_vzalloc(inlen);
4230 if (!out)
4231 return -ENOMEM;
4232
4233 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4234 if (err)
4235 goto out;
4236
4237 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4238 *rq_state = MLX5_GET(rqc, rqc, state);
4239 rq->state = *rq_state;
4240
4241out:
4242 kvfree(out);
4243 return err;
4244}
4245
4246static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4247 struct mlx5_ib_qp *qp, u8 *qp_state)
4248{
4249 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4250 [MLX5_RQC_STATE_RST] = {
4251 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4252 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4253 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4254 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4255 },
4256 [MLX5_RQC_STATE_RDY] = {
4257 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4258 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4259 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4260 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4261 },
4262 [MLX5_RQC_STATE_ERR] = {
4263 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4264 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4265 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4266 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4267 },
4268 [MLX5_RQ_STATE_NA] = {
4269 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4270 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4271 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4272 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4273 },
4274 };
4275
4276 *qp_state = sqrq_trans[rq_state][sq_state];
4277
4278 if (*qp_state == MLX5_QP_STATE_BAD) {
4279 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4280 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4281 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4282 return -EINVAL;
4283 }
4284
4285 if (*qp_state == MLX5_QP_STATE)
4286 *qp_state = qp->state;
4287
4288 return 0;
4289}
4290
4291static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4292 struct mlx5_ib_qp *qp,
4293 u8 *raw_packet_qp_state)
4294{
4295 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4296 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4297 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4298 int err;
4299 u8 sq_state = MLX5_SQ_STATE_NA;
4300 u8 rq_state = MLX5_RQ_STATE_NA;
4301
4302 if (qp->sq.wqe_cnt) {
4303 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4304 if (err)
4305 return err;
4306 }
4307
4308 if (qp->rq.wqe_cnt) {
4309 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4310 if (err)
4311 return err;
4312 }
4313
4314 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4315 raw_packet_qp_state);
4316}
4317
4318static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4319 struct ib_qp_attr *qp_attr)
e126ba97 4320{
09a7d9ec 4321 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4322 struct mlx5_qp_context *context;
4323 int mlx5_state;
09a7d9ec 4324 u32 *outb;
e126ba97
EC		 4325 int err = 0;
4326
09a7d9ec 4327 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4328 if (!outb)
4329 return -ENOMEM;
4330
19098df2 4331 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4332 outlen);
e126ba97 4333 if (err)
6d2f89df 4334 goto out;
e126ba97 4335
09a7d9ec
SM		 4336 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4337 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4338
e126ba97
EC		 4339 mlx5_state = be32_to_cpu(context->flags) >> 28;
4340
4341 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4342 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4343 qp_attr->path_mig_state =
4344 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4345 qp_attr->qkey = be32_to_cpu(context->qkey);
4346 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4347 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4348 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4349 qp_attr->qp_access_flags =
4350 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4351
4352 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4353 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4354 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4355 qp_attr->alt_pkey_index =
4356 be16_to_cpu(context->alt_path.pkey_index);
e126ba97
EC		 4357 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4358 }
4359
d3ae2bde 4360 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4361 qp_attr->port_num = context->pri_path.port;
4362
4363 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4364 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4365
4366 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4367
4368 qp_attr->max_dest_rd_atomic =
4369 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4370 qp_attr->min_rnr_timer =
4371 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4372 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4373 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4374 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4375 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4376
4377out:
4378 kfree(outb);
4379 return err;
4380}
4381
4382int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4383 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4384{
4385 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4386 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4387 int err = 0;
4388 u8 raw_packet_qp_state;
4389
28d61370
YH		 4390 if (ibqp->rwq_ind_tbl)
4391 return -ENOSYS;
4392
d16e91da
HE		 4393 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4394 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4395 qp_init_attr);
4396
6d2f89df 4397#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4398 /*
4399 * Wait for any outstanding page faults, in case the user frees memory
4400 * based upon this query's result.
4401 */
4402 flush_workqueue(mlx5_ib_page_fault_wq);
4403#endif
4404
4405 mutex_lock(&qp->mutex);
4406
4407 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4408 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4409 if (err)
4410 goto out;
4411 qp->state = raw_packet_qp_state;
4412 qp_attr->port_num = 1;
4413 } else {
4414 err = query_qp_attr(dev, qp, qp_attr);
4415 if (err)
4416 goto out;
4417 }
4418
4419 qp_attr->qp_state = qp->state;
e126ba97
EC		 4420 qp_attr->cur_qp_state = qp_attr->qp_state;
4421 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4422 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4423
4424 if (!ibqp->uobject) {
0540d814 4425 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4426 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4427 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4428 } else {
4429 qp_attr->cap.max_send_wr = 0;
4430 qp_attr->cap.max_send_sge = 0;
4431 }
4432
0540d814
NO		 4433 qp_init_attr->qp_type = ibqp->qp_type;
4434 qp_init_attr->recv_cq = ibqp->recv_cq;
4435 qp_init_attr->send_cq = ibqp->send_cq;
4436 qp_init_attr->srq = ibqp->srq;
4437 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4438
4439 qp_init_attr->cap = qp_attr->cap;
4440
4441 qp_init_attr->create_flags = 0;
4442 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4443 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4444
051f2630
LR		 4445 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4446 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4447 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4448 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4449 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4450 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4451 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4452 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4453
e126ba97
EC		 4454 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4455 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4456
e126ba97
EC		 4457out:
4458 mutex_unlock(&qp->mutex);
4459 return err;
4460}
4461
4462struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4463 struct ib_ucontext *context,
4464 struct ib_udata *udata)
4465{
4466 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4467 struct mlx5_ib_xrcd *xrcd;
4468 int err;
4469
938fe83c 4470 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4471 return ERR_PTR(-ENOSYS);
4472
4473 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4474 if (!xrcd)
4475 return ERR_PTR(-ENOMEM);
4476
9603b61d 4477 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4478 if (err) {
4479 kfree(xrcd);
4480 return ERR_PTR(-ENOMEM);
4481 }
4482
4483 return &xrcd->ibxrcd;
4484}
4485
4486int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4487{
4488 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4489 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4490 int err;
4491
9603b61d 4492 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4493 if (err) {
4494 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4495 return err;
4496 }
4497
4498 kfree(xrcd);
4499
4500 return 0;
4501}
79b20a6c
YH		 4502
4503static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4504 struct ib_wq_init_attr *init_attr)
4505{
4506 struct mlx5_ib_dev *dev;
4507 __be64 *rq_pas0;
4508 void *in;
4509 void *rqc;
4510 void *wq;
4511 int inlen;
4512 int err;
4513
4514 dev = to_mdev(pd->device);
4515
4516 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4517 in = mlx5_vzalloc(inlen);
4518 if (!in)
4519 return -ENOMEM;
4520
4521 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4522 MLX5_SET(rqc, rqc, mem_rq_type,
4523 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4524 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4525 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4526 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4527 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4528 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4529 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4530 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4531 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4532 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4533 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4534 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4535 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4536 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4537 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4538 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4539 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4540 err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn);
4541 kvfree(in);
4542 return err;
4543}
4544
4545static int set_user_rq_size(struct mlx5_ib_dev *dev,
4546 struct ib_wq_init_attr *wq_init_attr,
4547 struct mlx5_ib_create_wq *ucmd,
4548 struct mlx5_ib_rwq *rwq)
4549{
4550 /* Sanity check RQ size before proceeding */
4551 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4552 return -EINVAL;
4553
4554 if (!ucmd->rq_wqe_count)
4555 return -EINVAL;
4556
4557 rwq->wqe_count = ucmd->rq_wqe_count;
4558 rwq->wqe_shift = ucmd->rq_wqe_shift;
4559 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4560 rwq->log_rq_stride = rwq->wqe_shift;
4561 rwq->log_rq_size = ilog2(rwq->wqe_count);
4562 return 0;
4563}
4564
4565static int prepare_user_rq(struct ib_pd *pd,
4566 struct ib_wq_init_attr *init_attr,
4567 struct ib_udata *udata,
4568 struct mlx5_ib_rwq *rwq)
4569{
4570 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4571 struct mlx5_ib_create_wq ucmd = {};
4572 int err;
4573 size_t required_cmd_sz;
4574
4575 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4576 if (udata->inlen < required_cmd_sz) {
4577 mlx5_ib_dbg(dev, "invalid inlen\n");
4578 return -EINVAL;
4579 }
4580
4581 if (udata->inlen > sizeof(ucmd) &&
4582 !ib_is_udata_cleared(udata, sizeof(ucmd),
4583 udata->inlen - sizeof(ucmd))) {
4584 mlx5_ib_dbg(dev, "inlen is not supported\n");
4585 return -EOPNOTSUPP;
4586 }
4587
4588 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4589 mlx5_ib_dbg(dev, "copy failed\n");
4590 return -EFAULT;
4591 }
4592
4593 if (ucmd.comp_mask) {
4594 mlx5_ib_dbg(dev, "invalid comp mask\n");
4595 return -EOPNOTSUPP;
4596 }
4597
4598 if (ucmd.reserved) {
4599 mlx5_ib_dbg(dev, "invalid reserved\n");
4600 return -EOPNOTSUPP;
4601 }
4602
4603 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4604 if (err) {
4605 mlx5_ib_dbg(dev, "err %d\n", err);
4606 return err;
4607 }
4608
4609 err = create_user_rq(dev, pd, rwq, &ucmd);
4610 if (err) {
4611 mlx5_ib_dbg(dev, "err %d\n", err);
4612 if (err)
4613 return err;
4614 }
4615
4616 rwq->user_index = ucmd.user_index;
4617 return 0;
4618}
4619
4620struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4621 struct ib_wq_init_attr *init_attr,
4622 struct ib_udata *udata)
4623{
4624 struct mlx5_ib_dev *dev;
4625 struct mlx5_ib_rwq *rwq;
4626 struct mlx5_ib_create_wq_resp resp = {};
4627 size_t min_resp_len;
4628 int err;
4629
4630 if (!udata)
4631 return ERR_PTR(-ENOSYS);
4632
4633 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4634 if (udata->outlen && udata->outlen < min_resp_len)
4635 return ERR_PTR(-EINVAL);
4636
4637 dev = to_mdev(pd->device);
4638 switch (init_attr->wq_type) {
4639 case IB_WQT_RQ:
4640 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4641 if (!rwq)
4642 return ERR_PTR(-ENOMEM);
4643 err = prepare_user_rq(pd, init_attr, udata, rwq);
4644 if (err)
4645 goto err;
4646 err = create_rq(rwq, pd, init_attr);
4647 if (err)
4648 goto err_user_rq;
4649 break;
4650 default:
4651 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4652 init_attr->wq_type);
4653 return ERR_PTR(-EINVAL);
4654 }
4655
4656 rwq->ibwq.wq_num = rwq->rqn;
4657 rwq->ibwq.state = IB_WQS_RESET;
4658 if (udata->outlen) {
4659 resp.response_length = offsetof(typeof(resp), response_length) +
4660 sizeof(resp.response_length);
4661 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4662 if (err)
4663 goto err_copy;
4664 }
4665
4666 return &rwq->ibwq;
4667
4668err_copy:
4669 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4670err_user_rq:
4671 destroy_user_rq(pd, rwq);
4672err:
4673 kfree(rwq);
4674 return ERR_PTR(err);
4675}
4676
4677int mlx5_ib_destroy_wq(struct ib_wq *wq)
4678{
4679 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4680 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4681
4682 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4683 destroy_user_rq(wq->pd, rwq);
4684 kfree(rwq);
4685
4686 return 0;
4687}
4688
c5f90929
YH		 4689struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4690 struct ib_rwq_ind_table_init_attr *init_attr,
4691 struct ib_udata *udata)
4692{
4693 struct mlx5_ib_dev *dev = to_mdev(device);
4694 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4695 int sz = 1 << init_attr->log_ind_tbl_size;
4696 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4697 size_t min_resp_len;
4698 int inlen;
4699 int err;
4700 int i;
4701 u32 *in;
4702 void *rqtc;
4703
4704 if (udata->inlen > 0 &&
4705 !ib_is_udata_cleared(udata, 0,
4706 udata->inlen))
4707 return ERR_PTR(-EOPNOTSUPP);
4708
4709 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4710 if (udata->outlen && udata->outlen < min_resp_len)
4711 return ERR_PTR(-EINVAL);
4712
4713 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4714 if (!rwq_ind_tbl)
4715 return ERR_PTR(-ENOMEM);
4716
4717 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4718 in = mlx5_vzalloc(inlen);
4719 if (!in) {
4720 err = -ENOMEM;
4721 goto err;
4722 }
4723
4724 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4725
4726 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4727 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4728
4729 for (i = 0; i < sz; i++)
4730 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4731
4732 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4733 kvfree(in);
4734
4735 if (err)
4736 goto err;
4737
4738 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4739 if (udata->outlen) {
4740 resp.response_length = offsetof(typeof(resp), response_length) +
4741 sizeof(resp.response_length);
4742 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4743 if (err)
4744 goto err_copy;
4745 }
4746
4747 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4748
4749err_copy:
4750 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4751err:
4752 kfree(rwq_ind_tbl);
4753 return ERR_PTR(err);
4754}
4755
4756int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4757{
4758 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4759 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4760
4761 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4762
4763 kfree(rwq_ind_tbl);
4764 return 0;
4765}
4766
79b20a6c
YH		 4767int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4768 u32 wq_attr_mask, struct ib_udata *udata)
4769{
4770 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4771 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4772 struct mlx5_ib_modify_wq ucmd = {};
4773 size_t required_cmd_sz;
4774 int curr_wq_state;
4775 int wq_state;
4776 int inlen;
4777 int err;
4778 void *rqc;
4779 void *in;
4780
4781 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4782 if (udata->inlen < required_cmd_sz)
4783 return -EINVAL;
4784
4785 if (udata->inlen > sizeof(ucmd) &&
4786 !ib_is_udata_cleared(udata, sizeof(ucmd),
4787 udata->inlen - sizeof(ucmd)))
4788 return -EOPNOTSUPP;
4789
4790 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4791 return -EFAULT;
4792
4793 if (ucmd.comp_mask || ucmd.reserved)
4794 return -EOPNOTSUPP;
4795
4796 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4797 in = mlx5_vzalloc(inlen);
4798 if (!in)
4799 return -ENOMEM;
4800
4801 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4802
4803 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4804 wq_attr->curr_wq_state : wq->state;
4805 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4806 wq_attr->wq_state : curr_wq_state;
4807 if (curr_wq_state == IB_WQS_ERR)
4808 curr_wq_state = MLX5_RQC_STATE_ERR;
4809 if (wq_state == IB_WQS_ERR)
4810 wq_state = MLX5_RQC_STATE_ERR;
4811 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4812 MLX5_SET(rqc, rqc, state, wq_state);
4813
4814 err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen);
4815 kvfree(in);
4816 if (!err)
4817 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4818
4819 return err;
4820}
Linux 6.x block layer and io_uring tree(s)