Commit | Line | Data |
---|---|---|
e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | ||
34 | #include <linux/kref.h> | |
35 | #include <linux/random.h> | |
36 | #include <linux/debugfs.h> | |
37 | #include <linux/export.h> | |
746b5583 | 38 | #include <linux/delay.h> |
e126ba97 | 39 | #include <rdma/ib_umem.h> |
b4cfe447 | 40 | #include <rdma/ib_umem_odp.h> |
968e78dd | 41 | #include <rdma/ib_verbs.h> |
e126ba97 EC |
42 | #include "mlx5_ib.h" |
43 | ||
44 | enum { | |
746b5583 | 45 | MAX_PENDING_REG_MR = 8, |
e126ba97 EC |
46 | }; |
47 | ||
832a6b06 | 48 | #define MLX5_UMR_ALIGN 2048 |
fe45f827 | 49 | |
eeea6953 LR |
50 | static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); |
51 | static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); | |
8b7ff7f3 | 52 | static int mr_cache_max_order(struct mlx5_ib_dev *dev); |
49780d42 | 53 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); |
c8d75a98 MD |
54 | static bool umr_can_modify_entity_size(struct mlx5_ib_dev *dev) |
55 | { | |
56 | return !MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled); | |
57 | } | |
58 | ||
59 | static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev *dev) | |
60 | { | |
61 | return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled); | |
62 | } | |
63 | ||
64 | static bool use_umr(struct mlx5_ib_dev *dev, int order) | |
65 | { | |
66 | return order <= mr_cache_max_order(dev) && | |
67 | umr_can_modify_entity_size(dev); | |
68 | } | |
6aec21f6 | 69 | |
b4cfe447 HE |
70 | static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
71 | { | |
a606b0f6 | 72 | int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); |
b4cfe447 HE |
73 | |
74 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
75 | /* Wait until all page fault handlers using the mr complete. */ | |
76 | synchronize_srcu(&dev->mr_srcu); | |
77 | #endif | |
78 | ||
79 | return err; | |
80 | } | |
81 | ||
e126ba97 EC |
82 | static int order2idx(struct mlx5_ib_dev *dev, int order) |
83 | { | |
84 | struct mlx5_mr_cache *cache = &dev->cache; | |
85 | ||
86 | if (order < cache->ent[0].order) | |
87 | return 0; | |
88 | else | |
89 | return order - cache->ent[0].order; | |
90 | } | |
91 | ||
56e11d62 NO |
92 | static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length) |
93 | { | |
94 | return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >= | |
95 | length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1)); | |
96 | } | |
97 | ||
395a8e4c NO |
98 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
99 | static void update_odp_mr(struct mlx5_ib_mr *mr) | |
100 | { | |
101 | if (mr->umem->odp_data) { | |
102 | /* | |
103 | * This barrier prevents the compiler from moving the | |
104 | * setting of umem->odp_data->private to point to our | |
105 | * MR, before reg_umr finished, to ensure that the MR | |
106 | * initialization have finished before starting to | |
107 | * handle invalidations. | |
108 | */ | |
109 | smp_wmb(); | |
110 | mr->umem->odp_data->private = mr; | |
111 | /* | |
112 | * Make sure we will see the new | |
113 | * umem->odp_data->private value in the invalidation | |
114 | * routines, before we can get page faults on the | |
115 | * MR. Page faults can happen once we put the MR in | |
116 | * the tree, below this line. Without the barrier, | |
117 | * there can be a fault handling and an invalidation | |
118 | * before umem->odp_data->private == mr is visible to | |
119 | * the invalidation handler. | |
120 | */ | |
121 | smp_wmb(); | |
122 | } | |
123 | } | |
124 | #endif | |
125 | ||
746b5583 EC |
126 | static void reg_mr_callback(int status, void *context) |
127 | { | |
128 | struct mlx5_ib_mr *mr = context; | |
129 | struct mlx5_ib_dev *dev = mr->dev; | |
130 | struct mlx5_mr_cache *cache = &dev->cache; | |
131 | int c = order2idx(dev, mr->order); | |
132 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
133 | u8 key; | |
746b5583 | 134 | unsigned long flags; |
a606b0f6 | 135 | struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table; |
8605933a | 136 | int err; |
746b5583 | 137 | |
746b5583 EC |
138 | spin_lock_irqsave(&ent->lock, flags); |
139 | ent->pending--; | |
140 | spin_unlock_irqrestore(&ent->lock, flags); | |
141 | if (status) { | |
142 | mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status); | |
143 | kfree(mr); | |
144 | dev->fill_delay = 1; | |
145 | mod_timer(&dev->delay_timer, jiffies + HZ); | |
146 | return; | |
147 | } | |
148 | ||
aa8e08d2 | 149 | mr->mmkey.type = MLX5_MKEY_MR; |
9603b61d JM |
150 | spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags); |
151 | key = dev->mdev->priv.mkey_key++; | |
152 | spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags); | |
ec22eb53 | 153 | mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key; |
746b5583 EC |
154 | |
155 | cache->last_add = jiffies; | |
156 | ||
157 | spin_lock_irqsave(&ent->lock, flags); | |
158 | list_add_tail(&mr->list, &ent->head); | |
159 | ent->cur++; | |
160 | ent->size++; | |
161 | spin_unlock_irqrestore(&ent->lock, flags); | |
8605933a HE |
162 | |
163 | write_lock_irqsave(&table->lock, flags); | |
a606b0f6 MB |
164 | err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key), |
165 | &mr->mmkey); | |
8605933a | 166 | if (err) |
a606b0f6 | 167 | pr_err("Error inserting to mkey tree. 0x%x\n", -err); |
8605933a | 168 | write_unlock_irqrestore(&table->lock, flags); |
49780d42 AK |
169 | |
170 | if (!completion_done(&ent->compl)) | |
171 | complete(&ent->compl); | |
746b5583 EC |
172 | } |
173 | ||
e126ba97 EC |
174 | static int add_keys(struct mlx5_ib_dev *dev, int c, int num) |
175 | { | |
e126ba97 EC |
176 | struct mlx5_mr_cache *cache = &dev->cache; |
177 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
ec22eb53 | 178 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
e126ba97 | 179 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
180 | void *mkc; |
181 | u32 *in; | |
e126ba97 EC |
182 | int err = 0; |
183 | int i; | |
184 | ||
ec22eb53 | 185 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
186 | if (!in) |
187 | return -ENOMEM; | |
188 | ||
ec22eb53 | 189 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
e126ba97 | 190 | for (i = 0; i < num; i++) { |
746b5583 EC |
191 | if (ent->pending >= MAX_PENDING_REG_MR) { |
192 | err = -EAGAIN; | |
193 | break; | |
194 | } | |
195 | ||
e126ba97 EC |
196 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
197 | if (!mr) { | |
198 | err = -ENOMEM; | |
746b5583 | 199 | break; |
e126ba97 EC |
200 | } |
201 | mr->order = ent->order; | |
8b7ff7f3 | 202 | mr->allocated_from_cache = 1; |
746b5583 | 203 | mr->dev = dev; |
ec22eb53 SM |
204 | |
205 | MLX5_SET(mkc, mkc, free, 1); | |
206 | MLX5_SET(mkc, mkc, umr_en, 1); | |
cdbd0d2b AL |
207 | MLX5_SET(mkc, mkc, access_mode_1_0, ent->access_mode & 0x3); |
208 | MLX5_SET(mkc, mkc, access_mode_4_2, | |
209 | (ent->access_mode >> 2) & 0x7); | |
ec22eb53 SM |
210 | |
211 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
49780d42 AK |
212 | MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt); |
213 | MLX5_SET(mkc, mkc, log_page_size, ent->page); | |
e126ba97 | 214 | |
746b5583 EC |
215 | spin_lock_irq(&ent->lock); |
216 | ent->pending++; | |
217 | spin_unlock_irq(&ent->lock); | |
ec22eb53 SM |
218 | err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey, |
219 | in, inlen, | |
220 | mr->out, sizeof(mr->out), | |
221 | reg_mr_callback, mr); | |
e126ba97 | 222 | if (err) { |
d14e7110 EC |
223 | spin_lock_irq(&ent->lock); |
224 | ent->pending--; | |
225 | spin_unlock_irq(&ent->lock); | |
e126ba97 | 226 | mlx5_ib_warn(dev, "create mkey failed %d\n", err); |
e126ba97 | 227 | kfree(mr); |
746b5583 | 228 | break; |
e126ba97 | 229 | } |
e126ba97 EC |
230 | } |
231 | ||
e126ba97 EC |
232 | kfree(in); |
233 | return err; | |
234 | } | |
235 | ||
236 | static void remove_keys(struct mlx5_ib_dev *dev, int c, int num) | |
237 | { | |
e126ba97 EC |
238 | struct mlx5_mr_cache *cache = &dev->cache; |
239 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
65edd0e7 | 240 | struct mlx5_ib_mr *tmp_mr; |
e126ba97 | 241 | struct mlx5_ib_mr *mr; |
65edd0e7 | 242 | LIST_HEAD(del_list); |
e126ba97 EC |
243 | int i; |
244 | ||
245 | for (i = 0; i < num; i++) { | |
746b5583 | 246 | spin_lock_irq(&ent->lock); |
e126ba97 | 247 | if (list_empty(&ent->head)) { |
746b5583 | 248 | spin_unlock_irq(&ent->lock); |
65edd0e7 | 249 | break; |
e126ba97 EC |
250 | } |
251 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
65edd0e7 | 252 | list_move(&mr->list, &del_list); |
e126ba97 EC |
253 | ent->cur--; |
254 | ent->size--; | |
746b5583 | 255 | spin_unlock_irq(&ent->lock); |
65edd0e7 DJ |
256 | mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); |
257 | } | |
258 | ||
259 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
260 | synchronize_srcu(&dev->mr_srcu); | |
261 | #endif | |
262 | ||
263 | list_for_each_entry_safe(mr, tmp_mr, &del_list, list) { | |
264 | list_del(&mr->list); | |
265 | kfree(mr); | |
e126ba97 EC |
266 | } |
267 | } | |
268 | ||
269 | static ssize_t size_write(struct file *filp, const char __user *buf, | |
270 | size_t count, loff_t *pos) | |
271 | { | |
272 | struct mlx5_cache_ent *ent = filp->private_data; | |
273 | struct mlx5_ib_dev *dev = ent->dev; | |
60e6627f | 274 | char lbuf[20] = {0}; |
e126ba97 EC |
275 | u32 var; |
276 | int err; | |
277 | int c; | |
278 | ||
60e6627f JH |
279 | count = min(count, sizeof(lbuf) - 1); |
280 | if (copy_from_user(lbuf, buf, count)) | |
5e631a03 | 281 | return -EFAULT; |
e126ba97 EC |
282 | |
283 | c = order2idx(dev, ent->order); | |
e126ba97 EC |
284 | |
285 | if (sscanf(lbuf, "%u", &var) != 1) | |
286 | return -EINVAL; | |
287 | ||
288 | if (var < ent->limit) | |
289 | return -EINVAL; | |
290 | ||
291 | if (var > ent->size) { | |
746b5583 EC |
292 | do { |
293 | err = add_keys(dev, c, var - ent->size); | |
294 | if (err && err != -EAGAIN) | |
295 | return err; | |
296 | ||
297 | usleep_range(3000, 5000); | |
298 | } while (err); | |
e126ba97 EC |
299 | } else if (var < ent->size) { |
300 | remove_keys(dev, c, ent->size - var); | |
301 | } | |
302 | ||
303 | return count; | |
304 | } | |
305 | ||
306 | static ssize_t size_read(struct file *filp, char __user *buf, size_t count, | |
307 | loff_t *pos) | |
308 | { | |
309 | struct mlx5_cache_ent *ent = filp->private_data; | |
310 | char lbuf[20]; | |
311 | int err; | |
312 | ||
e126ba97 EC |
313 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size); |
314 | if (err < 0) | |
315 | return err; | |
316 | ||
60e6627f | 317 | return simple_read_from_buffer(buf, count, pos, lbuf, err); |
e126ba97 EC |
318 | } |
319 | ||
320 | static const struct file_operations size_fops = { | |
321 | .owner = THIS_MODULE, | |
322 | .open = simple_open, | |
323 | .write = size_write, | |
324 | .read = size_read, | |
325 | }; | |
326 | ||
327 | static ssize_t limit_write(struct file *filp, const char __user *buf, | |
328 | size_t count, loff_t *pos) | |
329 | { | |
330 | struct mlx5_cache_ent *ent = filp->private_data; | |
331 | struct mlx5_ib_dev *dev = ent->dev; | |
60e6627f | 332 | char lbuf[20] = {0}; |
e126ba97 EC |
333 | u32 var; |
334 | int err; | |
335 | int c; | |
336 | ||
60e6627f JH |
337 | count = min(count, sizeof(lbuf) - 1); |
338 | if (copy_from_user(lbuf, buf, count)) | |
5e631a03 | 339 | return -EFAULT; |
e126ba97 EC |
340 | |
341 | c = order2idx(dev, ent->order); | |
e126ba97 EC |
342 | |
343 | if (sscanf(lbuf, "%u", &var) != 1) | |
344 | return -EINVAL; | |
345 | ||
346 | if (var > ent->size) | |
347 | return -EINVAL; | |
348 | ||
349 | ent->limit = var; | |
350 | ||
351 | if (ent->cur < ent->limit) { | |
352 | err = add_keys(dev, c, 2 * ent->limit - ent->cur); | |
353 | if (err) | |
354 | return err; | |
355 | } | |
356 | ||
357 | return count; | |
358 | } | |
359 | ||
360 | static ssize_t limit_read(struct file *filp, char __user *buf, size_t count, | |
361 | loff_t *pos) | |
362 | { | |
363 | struct mlx5_cache_ent *ent = filp->private_data; | |
364 | char lbuf[20]; | |
365 | int err; | |
366 | ||
e126ba97 EC |
367 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit); |
368 | if (err < 0) | |
369 | return err; | |
370 | ||
60e6627f | 371 | return simple_read_from_buffer(buf, count, pos, lbuf, err); |
e126ba97 EC |
372 | } |
373 | ||
374 | static const struct file_operations limit_fops = { | |
375 | .owner = THIS_MODULE, | |
376 | .open = simple_open, | |
377 | .write = limit_write, | |
378 | .read = limit_read, | |
379 | }; | |
380 | ||
381 | static int someone_adding(struct mlx5_mr_cache *cache) | |
382 | { | |
383 | int i; | |
384 | ||
385 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
386 | if (cache->ent[i].cur < cache->ent[i].limit) | |
387 | return 1; | |
388 | } | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | static void __cache_work_func(struct mlx5_cache_ent *ent) | |
394 | { | |
395 | struct mlx5_ib_dev *dev = ent->dev; | |
396 | struct mlx5_mr_cache *cache = &dev->cache; | |
397 | int i = order2idx(dev, ent->order); | |
746b5583 | 398 | int err; |
e126ba97 EC |
399 | |
400 | if (cache->stopped) | |
401 | return; | |
402 | ||
403 | ent = &dev->cache.ent[i]; | |
746b5583 EC |
404 | if (ent->cur < 2 * ent->limit && !dev->fill_delay) { |
405 | err = add_keys(dev, i, 1); | |
406 | if (ent->cur < 2 * ent->limit) { | |
407 | if (err == -EAGAIN) { | |
408 | mlx5_ib_dbg(dev, "returned eagain, order %d\n", | |
409 | i + 2); | |
410 | queue_delayed_work(cache->wq, &ent->dwork, | |
411 | msecs_to_jiffies(3)); | |
412 | } else if (err) { | |
413 | mlx5_ib_warn(dev, "command failed order %d, err %d\n", | |
414 | i + 2, err); | |
415 | queue_delayed_work(cache->wq, &ent->dwork, | |
416 | msecs_to_jiffies(1000)); | |
417 | } else { | |
418 | queue_work(cache->wq, &ent->work); | |
419 | } | |
420 | } | |
e126ba97 | 421 | } else if (ent->cur > 2 * ent->limit) { |
ab5cdc31 LR |
422 | /* |
423 | * The remove_keys() logic is performed as garbage collection | |
424 | * task. Such task is intended to be run when no other active | |
425 | * processes are running. | |
426 | * | |
427 | * The need_resched() will return TRUE if there are user tasks | |
428 | * to be activated in near future. | |
429 | * | |
430 | * In such case, we don't execute remove_keys() and postpone | |
431 | * the garbage collection work to try to run in next cycle, | |
432 | * in order to free CPU resources to other tasks. | |
433 | */ | |
434 | if (!need_resched() && !someone_adding(cache) && | |
746b5583 | 435 | time_after(jiffies, cache->last_add + 300 * HZ)) { |
e126ba97 EC |
436 | remove_keys(dev, i, 1); |
437 | if (ent->cur > ent->limit) | |
438 | queue_work(cache->wq, &ent->work); | |
439 | } else { | |
746b5583 | 440 | queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ); |
e126ba97 EC |
441 | } |
442 | } | |
443 | } | |
444 | ||
445 | static void delayed_cache_work_func(struct work_struct *work) | |
446 | { | |
447 | struct mlx5_cache_ent *ent; | |
448 | ||
449 | ent = container_of(work, struct mlx5_cache_ent, dwork.work); | |
450 | __cache_work_func(ent); | |
451 | } | |
452 | ||
453 | static void cache_work_func(struct work_struct *work) | |
454 | { | |
455 | struct mlx5_cache_ent *ent; | |
456 | ||
457 | ent = container_of(work, struct mlx5_cache_ent, work); | |
458 | __cache_work_func(ent); | |
459 | } | |
460 | ||
49780d42 AK |
461 | struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry) |
462 | { | |
463 | struct mlx5_mr_cache *cache = &dev->cache; | |
464 | struct mlx5_cache_ent *ent; | |
465 | struct mlx5_ib_mr *mr; | |
466 | int err; | |
467 | ||
468 | if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) { | |
469 | mlx5_ib_err(dev, "cache entry %d is out of range\n", entry); | |
470 | return NULL; | |
471 | } | |
472 | ||
473 | ent = &cache->ent[entry]; | |
474 | while (1) { | |
475 | spin_lock_irq(&ent->lock); | |
476 | if (list_empty(&ent->head)) { | |
477 | spin_unlock_irq(&ent->lock); | |
478 | ||
479 | err = add_keys(dev, entry, 1); | |
81713d37 | 480 | if (err && err != -EAGAIN) |
49780d42 AK |
481 | return ERR_PTR(err); |
482 | ||
483 | wait_for_completion(&ent->compl); | |
484 | } else { | |
485 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
486 | list); | |
487 | list_del(&mr->list); | |
488 | ent->cur--; | |
489 | spin_unlock_irq(&ent->lock); | |
490 | if (ent->cur < ent->limit) | |
491 | queue_work(cache->wq, &ent->work); | |
492 | return mr; | |
493 | } | |
494 | } | |
495 | } | |
496 | ||
e126ba97 EC |
497 | static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order) |
498 | { | |
499 | struct mlx5_mr_cache *cache = &dev->cache; | |
500 | struct mlx5_ib_mr *mr = NULL; | |
501 | struct mlx5_cache_ent *ent; | |
4c25b7a3 | 502 | int last_umr_cache_entry; |
e126ba97 EC |
503 | int c; |
504 | int i; | |
505 | ||
506 | c = order2idx(dev, order); | |
8b7ff7f3 | 507 | last_umr_cache_entry = order2idx(dev, mr_cache_max_order(dev)); |
4c25b7a3 | 508 | if (c < 0 || c > last_umr_cache_entry) { |
e126ba97 EC |
509 | mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c); |
510 | return NULL; | |
511 | } | |
512 | ||
4c25b7a3 | 513 | for (i = c; i <= last_umr_cache_entry; i++) { |
e126ba97 EC |
514 | ent = &cache->ent[i]; |
515 | ||
516 | mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i); | |
517 | ||
746b5583 | 518 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
519 | if (!list_empty(&ent->head)) { |
520 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
521 | list); | |
522 | list_del(&mr->list); | |
523 | ent->cur--; | |
746b5583 | 524 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
525 | if (ent->cur < ent->limit) |
526 | queue_work(cache->wq, &ent->work); | |
527 | break; | |
528 | } | |
746b5583 | 529 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
530 | |
531 | queue_work(cache->wq, &ent->work); | |
e126ba97 EC |
532 | } |
533 | ||
534 | if (!mr) | |
535 | cache->ent[c].miss++; | |
536 | ||
537 | return mr; | |
538 | } | |
539 | ||
49780d42 | 540 | void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
e126ba97 EC |
541 | { |
542 | struct mlx5_mr_cache *cache = &dev->cache; | |
543 | struct mlx5_cache_ent *ent; | |
544 | int shrink = 0; | |
545 | int c; | |
546 | ||
dd9a4034 VF |
547 | if (!mr->allocated_from_cache) |
548 | return; | |
549 | ||
e126ba97 EC |
550 | c = order2idx(dev, mr->order); |
551 | if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { | |
552 | mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c); | |
553 | return; | |
554 | } | |
49780d42 AK |
555 | |
556 | if (unreg_umr(dev, mr)) | |
557 | return; | |
558 | ||
e126ba97 | 559 | ent = &cache->ent[c]; |
746b5583 | 560 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
561 | list_add_tail(&mr->list, &ent->head); |
562 | ent->cur++; | |
563 | if (ent->cur > 2 * ent->limit) | |
564 | shrink = 1; | |
746b5583 | 565 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
566 | |
567 | if (shrink) | |
568 | queue_work(cache->wq, &ent->work); | |
569 | } | |
570 | ||
571 | static void clean_keys(struct mlx5_ib_dev *dev, int c) | |
572 | { | |
e126ba97 EC |
573 | struct mlx5_mr_cache *cache = &dev->cache; |
574 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
65edd0e7 | 575 | struct mlx5_ib_mr *tmp_mr; |
e126ba97 | 576 | struct mlx5_ib_mr *mr; |
65edd0e7 | 577 | LIST_HEAD(del_list); |
e126ba97 | 578 | |
3c461911 | 579 | cancel_delayed_work(&ent->dwork); |
e126ba97 | 580 | while (1) { |
746b5583 | 581 | spin_lock_irq(&ent->lock); |
e126ba97 | 582 | if (list_empty(&ent->head)) { |
746b5583 | 583 | spin_unlock_irq(&ent->lock); |
65edd0e7 | 584 | break; |
e126ba97 EC |
585 | } |
586 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
65edd0e7 | 587 | list_move(&mr->list, &del_list); |
e126ba97 EC |
588 | ent->cur--; |
589 | ent->size--; | |
746b5583 | 590 | spin_unlock_irq(&ent->lock); |
65edd0e7 DJ |
591 | mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); |
592 | } | |
593 | ||
594 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
595 | synchronize_srcu(&dev->mr_srcu); | |
596 | #endif | |
597 | ||
598 | list_for_each_entry_safe(mr, tmp_mr, &del_list, list) { | |
599 | list_del(&mr->list); | |
600 | kfree(mr); | |
e126ba97 EC |
601 | } |
602 | } | |
603 | ||
12cc1a02 LR |
604 | static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) |
605 | { | |
72afcf82 | 606 | if (!mlx5_debugfs_root || dev->rep) |
12cc1a02 LR |
607 | return; |
608 | ||
609 | debugfs_remove_recursive(dev->cache.root); | |
610 | dev->cache.root = NULL; | |
611 | } | |
612 | ||
e126ba97 EC |
613 | static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev) |
614 | { | |
615 | struct mlx5_mr_cache *cache = &dev->cache; | |
616 | struct mlx5_cache_ent *ent; | |
617 | int i; | |
618 | ||
72afcf82 | 619 | if (!mlx5_debugfs_root || dev->rep) |
e126ba97 EC |
620 | return 0; |
621 | ||
9603b61d | 622 | cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root); |
e126ba97 EC |
623 | if (!cache->root) |
624 | return -ENOMEM; | |
625 | ||
626 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
627 | ent = &cache->ent[i]; | |
628 | sprintf(ent->name, "%d", ent->order); | |
629 | ent->dir = debugfs_create_dir(ent->name, cache->root); | |
630 | if (!ent->dir) | |
12cc1a02 | 631 | goto err; |
e126ba97 EC |
632 | |
633 | ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent, | |
634 | &size_fops); | |
635 | if (!ent->fsize) | |
12cc1a02 | 636 | goto err; |
e126ba97 EC |
637 | |
638 | ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent, | |
639 | &limit_fops); | |
640 | if (!ent->flimit) | |
12cc1a02 | 641 | goto err; |
e126ba97 EC |
642 | |
643 | ent->fcur = debugfs_create_u32("cur", 0400, ent->dir, | |
644 | &ent->cur); | |
645 | if (!ent->fcur) | |
12cc1a02 | 646 | goto err; |
e126ba97 EC |
647 | |
648 | ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir, | |
649 | &ent->miss); | |
650 | if (!ent->fmiss) | |
12cc1a02 | 651 | goto err; |
e126ba97 EC |
652 | } |
653 | ||
654 | return 0; | |
12cc1a02 LR |
655 | err: |
656 | mlx5_mr_cache_debugfs_cleanup(dev); | |
e126ba97 | 657 | |
12cc1a02 | 658 | return -ENOMEM; |
e126ba97 EC |
659 | } |
660 | ||
e99e88a9 | 661 | static void delay_time_func(struct timer_list *t) |
746b5583 | 662 | { |
e99e88a9 | 663 | struct mlx5_ib_dev *dev = from_timer(dev, t, delay_timer); |
746b5583 EC |
664 | |
665 | dev->fill_delay = 0; | |
666 | } | |
667 | ||
e126ba97 EC |
668 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) |
669 | { | |
670 | struct mlx5_mr_cache *cache = &dev->cache; | |
671 | struct mlx5_cache_ent *ent; | |
e126ba97 EC |
672 | int err; |
673 | int i; | |
674 | ||
6bc1a656 | 675 | mutex_init(&dev->slow_path_mutex); |
3c856c82 | 676 | cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM); |
e126ba97 EC |
677 | if (!cache->wq) { |
678 | mlx5_ib_warn(dev, "failed to create work queue\n"); | |
679 | return -ENOMEM; | |
680 | } | |
681 | ||
e99e88a9 | 682 | timer_setup(&dev->delay_timer, delay_time_func, 0); |
e126ba97 | 683 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { |
e126ba97 EC |
684 | ent = &cache->ent[i]; |
685 | INIT_LIST_HEAD(&ent->head); | |
686 | spin_lock_init(&ent->lock); | |
687 | ent->order = i + 2; | |
688 | ent->dev = dev; | |
49780d42 | 689 | ent->limit = 0; |
e126ba97 | 690 | |
49780d42 | 691 | init_completion(&ent->compl); |
e126ba97 EC |
692 | INIT_WORK(&ent->work, cache_work_func); |
693 | INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); | |
e126ba97 | 694 | queue_work(cache->wq, &ent->work); |
49780d42 | 695 | |
8b7ff7f3 | 696 | if (i > MR_CACHE_LAST_STD_ENTRY) { |
81713d37 | 697 | mlx5_odp_init_mr_cache_entry(ent); |
49780d42 | 698 | continue; |
81713d37 | 699 | } |
49780d42 | 700 | |
8b7ff7f3 | 701 | if (ent->order > mr_cache_max_order(dev)) |
49780d42 AK |
702 | continue; |
703 | ||
704 | ent->page = PAGE_SHIFT; | |
705 | ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) / | |
706 | MLX5_IB_UMR_OCTOWORD; | |
707 | ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; | |
708 | if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) && | |
72afcf82 | 709 | !dev->rep && |
49780d42 AK |
710 | mlx5_core_is_pf(dev->mdev)) |
711 | ent->limit = dev->mdev->profile->mr_cache[i].limit; | |
712 | else | |
713 | ent->limit = 0; | |
e126ba97 EC |
714 | } |
715 | ||
716 | err = mlx5_mr_cache_debugfs_init(dev); | |
717 | if (err) | |
718 | mlx5_ib_warn(dev, "cache debugfs failure\n"); | |
719 | ||
12cc1a02 LR |
720 | /* |
721 | * We don't want to fail driver if debugfs failed to initialize, | |
722 | * so we are not forwarding error to the user. | |
723 | */ | |
724 | ||
e126ba97 EC |
725 | return 0; |
726 | } | |
727 | ||
acbda523 EC |
728 | static void wait_for_async_commands(struct mlx5_ib_dev *dev) |
729 | { | |
730 | struct mlx5_mr_cache *cache = &dev->cache; | |
731 | struct mlx5_cache_ent *ent; | |
732 | int total = 0; | |
733 | int i; | |
734 | int j; | |
735 | ||
736 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
737 | ent = &cache->ent[i]; | |
738 | for (j = 0 ; j < 1000; j++) { | |
739 | if (!ent->pending) | |
740 | break; | |
741 | msleep(50); | |
742 | } | |
743 | } | |
744 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
745 | ent = &cache->ent[i]; | |
746 | total += ent->pending; | |
747 | } | |
748 | ||
749 | if (total) | |
750 | mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total); | |
751 | else | |
752 | mlx5_ib_warn(dev, "done with all pending requests\n"); | |
753 | } | |
754 | ||
e126ba97 EC |
755 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) |
756 | { | |
757 | int i; | |
758 | ||
32927e28 MB |
759 | if (!dev->cache.wq) |
760 | return 0; | |
761 | ||
e126ba97 | 762 | dev->cache.stopped = 1; |
3c461911 | 763 | flush_workqueue(dev->cache.wq); |
e126ba97 EC |
764 | |
765 | mlx5_mr_cache_debugfs_cleanup(dev); | |
766 | ||
767 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) | |
768 | clean_keys(dev, i); | |
769 | ||
3c461911 | 770 | destroy_workqueue(dev->cache.wq); |
acbda523 | 771 | wait_for_async_commands(dev); |
746b5583 | 772 | del_timer_sync(&dev->delay_timer); |
3c461911 | 773 | |
e126ba97 EC |
774 | return 0; |
775 | } | |
776 | ||
777 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) | |
778 | { | |
779 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 780 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
9603b61d | 781 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 | 782 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
783 | void *mkc; |
784 | u32 *in; | |
e126ba97 EC |
785 | int err; |
786 | ||
787 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
788 | if (!mr) | |
789 | return ERR_PTR(-ENOMEM); | |
790 | ||
ec22eb53 | 791 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
792 | if (!in) { |
793 | err = -ENOMEM; | |
794 | goto err_free; | |
795 | } | |
796 | ||
ec22eb53 SM |
797 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
798 | ||
cdbd0d2b | 799 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); |
ec22eb53 SM |
800 | MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); |
801 | MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); | |
802 | MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); | |
803 | MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); | |
804 | MLX5_SET(mkc, mkc, lr, 1); | |
e126ba97 | 805 | |
ec22eb53 SM |
806 | MLX5_SET(mkc, mkc, length64, 1); |
807 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
808 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
809 | MLX5_SET64(mkc, mkc, start_addr, 0); | |
810 | ||
811 | err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
812 | if (err) |
813 | goto err_in; | |
814 | ||
815 | kfree(in); | |
aa8e08d2 | 816 | mr->mmkey.type = MLX5_MKEY_MR; |
a606b0f6 MB |
817 | mr->ibmr.lkey = mr->mmkey.key; |
818 | mr->ibmr.rkey = mr->mmkey.key; | |
e126ba97 EC |
819 | mr->umem = NULL; |
820 | ||
821 | return &mr->ibmr; | |
822 | ||
823 | err_in: | |
824 | kfree(in); | |
825 | ||
826 | err_free: | |
827 | kfree(mr); | |
828 | ||
829 | return ERR_PTR(err); | |
830 | } | |
831 | ||
7b4cdaae | 832 | static int get_octo_len(u64 addr, u64 len, int page_shift) |
e126ba97 | 833 | { |
7b4cdaae | 834 | u64 page_size = 1ULL << page_shift; |
e126ba97 EC |
835 | u64 offset; |
836 | int npages; | |
837 | ||
838 | offset = addr & (page_size - 1); | |
7b4cdaae | 839 | npages = ALIGN(len + offset, page_size) >> page_shift; |
e126ba97 EC |
840 | return (npages + 1) / 2; |
841 | } | |
842 | ||
8b7ff7f3 | 843 | static int mr_cache_max_order(struct mlx5_ib_dev *dev) |
e126ba97 | 844 | { |
7d0cc6ed | 845 | if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) |
8b7ff7f3 | 846 | return MR_CACHE_LAST_STD_ENTRY + 2; |
4c25b7a3 MD |
847 | return MLX5_MAX_UMR_SHIFT; |
848 | } | |
849 | ||
14ab8896 AB |
850 | static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length, |
851 | int access_flags, struct ib_umem **umem, | |
852 | int *npages, int *page_shift, int *ncont, | |
853 | int *order) | |
395a8e4c NO |
854 | { |
855 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
b4bd701a | 856 | struct ib_umem *u; |
14ab8896 AB |
857 | int err; |
858 | ||
b4bd701a LR |
859 | *umem = NULL; |
860 | ||
861 | u = ib_umem_get(pd->uobject->context, start, length, access_flags, 0); | |
862 | err = PTR_ERR_OR_ZERO(u); | |
f3f134f5 | 863 | if (err) { |
b4bd701a | 864 | mlx5_ib_dbg(dev, "umem get failed (%d)\n", err); |
14ab8896 | 865 | return err; |
395a8e4c NO |
866 | } |
867 | ||
b4bd701a | 868 | mlx5_ib_cont_pages(u, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages, |
762f899a | 869 | page_shift, ncont, order); |
395a8e4c NO |
870 | if (!*npages) { |
871 | mlx5_ib_warn(dev, "avoid zero region\n"); | |
b4bd701a | 872 | ib_umem_release(u); |
14ab8896 | 873 | return -EINVAL; |
395a8e4c NO |
874 | } |
875 | ||
b4bd701a LR |
876 | *umem = u; |
877 | ||
395a8e4c NO |
878 | mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", |
879 | *npages, *ncont, *order, *page_shift); | |
880 | ||
14ab8896 | 881 | return 0; |
395a8e4c NO |
882 | } |
883 | ||
add08d76 | 884 | static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc) |
e126ba97 | 885 | { |
add08d76 CH |
886 | struct mlx5_ib_umr_context *context = |
887 | container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe); | |
e126ba97 | 888 | |
add08d76 CH |
889 | context->status = wc->status; |
890 | complete(&context->done); | |
891 | } | |
e126ba97 | 892 | |
add08d76 CH |
893 | static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) |
894 | { | |
895 | context->cqe.done = mlx5_ib_umr_done; | |
896 | context->status = -1; | |
897 | init_completion(&context->done); | |
e126ba97 EC |
898 | } |
899 | ||
d5ea2df9 BJ |
900 | static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev, |
901 | struct mlx5_umr_wr *umrwr) | |
902 | { | |
903 | struct umr_common *umrc = &dev->umrc; | |
d34ac5cd | 904 | const struct ib_send_wr *bad; |
d5ea2df9 BJ |
905 | int err; |
906 | struct mlx5_ib_umr_context umr_context; | |
907 | ||
908 | mlx5_ib_init_umr_context(&umr_context); | |
909 | umrwr->wr.wr_cqe = &umr_context.cqe; | |
910 | ||
911 | down(&umrc->sem); | |
912 | err = ib_post_send(umrc->qp, &umrwr->wr, &bad); | |
913 | if (err) { | |
914 | mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err); | |
915 | } else { | |
916 | wait_for_completion(&umr_context.done); | |
917 | if (umr_context.status != IB_WC_SUCCESS) { | |
918 | mlx5_ib_warn(dev, "reg umr failed (%u)\n", | |
919 | umr_context.status); | |
920 | err = -EFAULT; | |
921 | } | |
922 | } | |
923 | up(&umrc->sem); | |
924 | return err; | |
925 | } | |
926 | ||
ff740aef IL |
927 | static struct mlx5_ib_mr *alloc_mr_from_cache( |
928 | struct ib_pd *pd, struct ib_umem *umem, | |
e126ba97 EC |
929 | u64 virt_addr, u64 len, int npages, |
930 | int page_shift, int order, int access_flags) | |
931 | { | |
932 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 933 | struct mlx5_ib_mr *mr; |
096f7e72 | 934 | int err = 0; |
e126ba97 EC |
935 | int i; |
936 | ||
746b5583 | 937 | for (i = 0; i < 1; i++) { |
e126ba97 EC |
938 | mr = alloc_cached_mr(dev, order); |
939 | if (mr) | |
940 | break; | |
941 | ||
942 | err = add_keys(dev, order2idx(dev, order), 1); | |
746b5583 EC |
943 | if (err && err != -EAGAIN) { |
944 | mlx5_ib_warn(dev, "add_keys failed, err %d\n", err); | |
e126ba97 EC |
945 | break; |
946 | } | |
947 | } | |
948 | ||
949 | if (!mr) | |
950 | return ERR_PTR(-EAGAIN); | |
951 | ||
7d0cc6ed AK |
952 | mr->ibmr.pd = pd; |
953 | mr->umem = umem; | |
954 | mr->access_flags = access_flags; | |
955 | mr->desc_size = sizeof(struct mlx5_mtt); | |
a606b0f6 MB |
956 | mr->mmkey.iova = virt_addr; |
957 | mr->mmkey.size = len; | |
958 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
b475598a | 959 | |
e126ba97 | 960 | return mr; |
e126ba97 EC |
961 | } |
962 | ||
7d0cc6ed AK |
963 | static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages, |
964 | void *xlt, int page_shift, size_t size, | |
965 | int flags) | |
832a6b06 HE |
966 | { |
967 | struct mlx5_ib_dev *dev = mr->dev; | |
832a6b06 | 968 | struct ib_umem *umem = mr->umem; |
c8d75a98 | 969 | |
81713d37 | 970 | if (flags & MLX5_IB_UPD_XLT_INDIRECT) { |
c8d75a98 MD |
971 | if (!umr_can_use_indirect_mkey(dev)) |
972 | return -EPERM; | |
81713d37 AK |
973 | mlx5_odp_populate_klm(xlt, idx, npages, mr, flags); |
974 | return npages; | |
975 | } | |
7d0cc6ed AK |
976 | |
977 | npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx); | |
978 | ||
979 | if (!(flags & MLX5_IB_UPD_XLT_ZAP)) { | |
980 | __mlx5_ib_populate_pas(dev, umem, page_shift, | |
981 | idx, npages, xlt, | |
982 | MLX5_IB_MTT_PRESENT); | |
983 | /* Clear padding after the pages | |
984 | * brought from the umem. | |
985 | */ | |
986 | memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0, | |
987 | size - npages * sizeof(struct mlx5_mtt)); | |
988 | } | |
989 | ||
990 | return npages; | |
991 | } | |
992 | ||
993 | #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \ | |
994 | MLX5_UMR_MTT_ALIGNMENT) | |
995 | #define MLX5_SPARE_UMR_CHUNK 0x10000 | |
996 | ||
997 | int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, | |
998 | int page_shift, int flags) | |
999 | { | |
1000 | struct mlx5_ib_dev *dev = mr->dev; | |
9b0c289e | 1001 | struct device *ddev = dev->ib_dev.dev.parent; |
832a6b06 | 1002 | int size; |
7d0cc6ed | 1003 | void *xlt; |
832a6b06 | 1004 | dma_addr_t dma; |
e622f2f4 | 1005 | struct mlx5_umr_wr wr; |
832a6b06 HE |
1006 | struct ib_sge sg; |
1007 | int err = 0; | |
81713d37 AK |
1008 | int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT) |
1009 | ? sizeof(struct mlx5_klm) | |
1010 | : sizeof(struct mlx5_mtt); | |
7d0cc6ed AK |
1011 | const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size; |
1012 | const int page_mask = page_align - 1; | |
832a6b06 HE |
1013 | size_t pages_mapped = 0; |
1014 | size_t pages_to_map = 0; | |
1015 | size_t pages_iter = 0; | |
7d0cc6ed | 1016 | gfp_t gfp; |
c44ef998 | 1017 | bool use_emergency_page = false; |
832a6b06 | 1018 | |
c8d75a98 MD |
1019 | if ((flags & MLX5_IB_UPD_XLT_INDIRECT) && |
1020 | !umr_can_use_indirect_mkey(dev)) | |
1021 | return -EPERM; | |
832a6b06 HE |
1022 | |
1023 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, | |
7d0cc6ed AK |
1024 | * so we need to align the offset and length accordingly |
1025 | */ | |
1026 | if (idx & page_mask) { | |
1027 | npages += idx & page_mask; | |
1028 | idx &= ~page_mask; | |
832a6b06 HE |
1029 | } |
1030 | ||
7d0cc6ed AK |
1031 | gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL; |
1032 | gfp |= __GFP_ZERO | __GFP_NOWARN; | |
832a6b06 | 1033 | |
7d0cc6ed AK |
1034 | pages_to_map = ALIGN(npages, page_align); |
1035 | size = desc_size * pages_to_map; | |
1036 | size = min_t(int, size, MLX5_MAX_UMR_CHUNK); | |
832a6b06 | 1037 | |
7d0cc6ed AK |
1038 | xlt = (void *)__get_free_pages(gfp, get_order(size)); |
1039 | if (!xlt && size > MLX5_SPARE_UMR_CHUNK) { | |
1040 | mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n", | |
1041 | size, get_order(size), MLX5_SPARE_UMR_CHUNK); | |
1042 | ||
1043 | size = MLX5_SPARE_UMR_CHUNK; | |
1044 | xlt = (void *)__get_free_pages(gfp, get_order(size)); | |
832a6b06 | 1045 | } |
7d0cc6ed AK |
1046 | |
1047 | if (!xlt) { | |
7d0cc6ed | 1048 | mlx5_ib_warn(dev, "Using XLT emergency buffer\n"); |
c44ef998 | 1049 | xlt = (void *)mlx5_ib_get_xlt_emergency_page(); |
7d0cc6ed | 1050 | size = PAGE_SIZE; |
7d0cc6ed | 1051 | memset(xlt, 0, size); |
c44ef998 | 1052 | use_emergency_page = true; |
7d0cc6ed AK |
1053 | } |
1054 | pages_iter = size / desc_size; | |
1055 | dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE); | |
832a6b06 | 1056 | if (dma_mapping_error(ddev, dma)) { |
7d0cc6ed | 1057 | mlx5_ib_err(dev, "unable to map DMA during XLT update.\n"); |
832a6b06 | 1058 | err = -ENOMEM; |
7d0cc6ed | 1059 | goto free_xlt; |
832a6b06 HE |
1060 | } |
1061 | ||
7d0cc6ed AK |
1062 | sg.addr = dma; |
1063 | sg.lkey = dev->umrc.pd->local_dma_lkey; | |
1064 | ||
1065 | memset(&wr, 0, sizeof(wr)); | |
1066 | wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT; | |
1067 | if (!(flags & MLX5_IB_UPD_XLT_ENABLE)) | |
1068 | wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
1069 | wr.wr.sg_list = &sg; | |
1070 | wr.wr.num_sge = 1; | |
1071 | wr.wr.opcode = MLX5_IB_WR_UMR; | |
1072 | ||
1073 | wr.pd = mr->ibmr.pd; | |
1074 | wr.mkey = mr->mmkey.key; | |
1075 | wr.length = mr->mmkey.size; | |
1076 | wr.virt_addr = mr->mmkey.iova; | |
1077 | wr.access_flags = mr->access_flags; | |
1078 | wr.page_shift = page_shift; | |
1079 | ||
832a6b06 HE |
1080 | for (pages_mapped = 0; |
1081 | pages_mapped < pages_to_map && !err; | |
7d0cc6ed | 1082 | pages_mapped += pages_iter, idx += pages_iter) { |
438b228e | 1083 | npages = min_t(int, pages_iter, pages_to_map - pages_mapped); |
832a6b06 | 1084 | dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE); |
438b228e | 1085 | npages = populate_xlt(mr, idx, npages, xlt, |
7d0cc6ed | 1086 | page_shift, size, flags); |
832a6b06 HE |
1087 | |
1088 | dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE); | |
1089 | ||
7d0cc6ed AK |
1090 | sg.length = ALIGN(npages * desc_size, |
1091 | MLX5_UMR_MTT_ALIGNMENT); | |
1092 | ||
1093 | if (pages_mapped + pages_iter >= pages_to_map) { | |
1094 | if (flags & MLX5_IB_UPD_XLT_ENABLE) | |
1095 | wr.wr.send_flags |= | |
1096 | MLX5_IB_SEND_UMR_ENABLE_MR | | |
1097 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS | | |
1098 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1099 | if (flags & MLX5_IB_UPD_XLT_PD || | |
1100 | flags & MLX5_IB_UPD_XLT_ACCESS) | |
1101 | wr.wr.send_flags |= | |
1102 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; | |
1103 | if (flags & MLX5_IB_UPD_XLT_ADDR) | |
1104 | wr.wr.send_flags |= | |
1105 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1106 | } | |
832a6b06 | 1107 | |
7d0cc6ed | 1108 | wr.offset = idx * desc_size; |
31616255 | 1109 | wr.xlt_size = sg.length; |
832a6b06 | 1110 | |
d5ea2df9 | 1111 | err = mlx5_ib_post_send_wait(dev, &wr); |
832a6b06 HE |
1112 | } |
1113 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); | |
1114 | ||
7d0cc6ed | 1115 | free_xlt: |
c44ef998 IL |
1116 | if (use_emergency_page) |
1117 | mlx5_ib_put_xlt_emergency_page(); | |
832a6b06 | 1118 | else |
7d0cc6ed | 1119 | free_pages((unsigned long)xlt, get_order(size)); |
832a6b06 HE |
1120 | |
1121 | return err; | |
1122 | } | |
832a6b06 | 1123 | |
395a8e4c NO |
1124 | /* |
1125 | * If ibmr is NULL it will be allocated by reg_create. | |
1126 | * Else, the given ibmr will be used. | |
1127 | */ | |
1128 | static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd, | |
1129 | u64 virt_addr, u64 length, | |
1130 | struct ib_umem *umem, int npages, | |
ff740aef IL |
1131 | int page_shift, int access_flags, |
1132 | bool populate) | |
e126ba97 EC |
1133 | { |
1134 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 1135 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
1136 | __be64 *pas; |
1137 | void *mkc; | |
e126ba97 | 1138 | int inlen; |
ec22eb53 | 1139 | u32 *in; |
e126ba97 | 1140 | int err; |
938fe83c | 1141 | bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)); |
e126ba97 | 1142 | |
395a8e4c | 1143 | mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL); |
e126ba97 EC |
1144 | if (!mr) |
1145 | return ERR_PTR(-ENOMEM); | |
1146 | ||
ff740aef IL |
1147 | mr->ibmr.pd = pd; |
1148 | mr->access_flags = access_flags; | |
1149 | ||
1150 | inlen = MLX5_ST_SZ_BYTES(create_mkey_in); | |
1151 | if (populate) | |
1152 | inlen += sizeof(*pas) * roundup(npages, 2); | |
1b9a07ee | 1153 | in = kvzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
1154 | if (!in) { |
1155 | err = -ENOMEM; | |
1156 | goto err_1; | |
1157 | } | |
ec22eb53 | 1158 | pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); |
ff740aef | 1159 | if (populate && !(access_flags & IB_ACCESS_ON_DEMAND)) |
c438fde1 AK |
1160 | mlx5_ib_populate_pas(dev, umem, page_shift, pas, |
1161 | pg_cap ? MLX5_IB_MTT_PRESENT : 0); | |
e126ba97 | 1162 | |
ec22eb53 | 1163 | /* The pg_access bit allows setting the access flags |
cc149f75 | 1164 | * in the page list submitted with the command. */ |
ec22eb53 SM |
1165 | MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap)); |
1166 | ||
1167 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
ff740aef | 1168 | MLX5_SET(mkc, mkc, free, !populate); |
cdbd0d2b | 1169 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); |
ec22eb53 SM |
1170 | MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); |
1171 | MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); | |
1172 | MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); | |
1173 | MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); | |
1174 | MLX5_SET(mkc, mkc, lr, 1); | |
8b7ff7f3 | 1175 | MLX5_SET(mkc, mkc, umr_en, 1); |
ec22eb53 SM |
1176 | |
1177 | MLX5_SET64(mkc, mkc, start_addr, virt_addr); | |
1178 | MLX5_SET64(mkc, mkc, len, length); | |
1179 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1180 | MLX5_SET(mkc, mkc, bsf_octword_size, 0); | |
1181 | MLX5_SET(mkc, mkc, translations_octword_size, | |
7b4cdaae | 1182 | get_octo_len(virt_addr, length, page_shift)); |
ec22eb53 SM |
1183 | MLX5_SET(mkc, mkc, log_page_size, page_shift); |
1184 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
ff740aef IL |
1185 | if (populate) { |
1186 | MLX5_SET(create_mkey_in, in, translations_octword_actual_size, | |
7b4cdaae | 1187 | get_octo_len(virt_addr, length, page_shift)); |
ff740aef | 1188 | } |
ec22eb53 SM |
1189 | |
1190 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
1191 | if (err) { |
1192 | mlx5_ib_warn(dev, "create mkey failed\n"); | |
1193 | goto err_2; | |
1194 | } | |
aa8e08d2 | 1195 | mr->mmkey.type = MLX5_MKEY_MR; |
49780d42 | 1196 | mr->desc_size = sizeof(struct mlx5_mtt); |
7eae20db | 1197 | mr->dev = dev; |
479163f4 | 1198 | kvfree(in); |
e126ba97 | 1199 | |
a606b0f6 | 1200 | mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1201 | |
1202 | return mr; | |
1203 | ||
1204 | err_2: | |
479163f4 | 1205 | kvfree(in); |
e126ba97 EC |
1206 | |
1207 | err_1: | |
395a8e4c NO |
1208 | if (!ibmr) |
1209 | kfree(mr); | |
e126ba97 EC |
1210 | |
1211 | return ERR_PTR(err); | |
1212 | } | |
1213 | ||
395a8e4c NO |
1214 | static void set_mr_fileds(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr, |
1215 | int npages, u64 length, int access_flags) | |
1216 | { | |
1217 | mr->npages = npages; | |
1218 | atomic_add(npages, &dev->mdev->priv.reg_pages); | |
a606b0f6 MB |
1219 | mr->ibmr.lkey = mr->mmkey.key; |
1220 | mr->ibmr.rkey = mr->mmkey.key; | |
395a8e4c | 1221 | mr->ibmr.length = length; |
56e11d62 | 1222 | mr->access_flags = access_flags; |
395a8e4c NO |
1223 | } |
1224 | ||
6c29f57e AL |
1225 | static struct ib_mr *mlx5_ib_get_memic_mr(struct ib_pd *pd, u64 memic_addr, |
1226 | u64 length, int acc) | |
1227 | { | |
1228 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1229 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); | |
1230 | struct mlx5_core_dev *mdev = dev->mdev; | |
1231 | struct mlx5_ib_mr *mr; | |
1232 | void *mkc; | |
1233 | u32 *in; | |
1234 | int err; | |
1235 | ||
1236 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1237 | if (!mr) | |
1238 | return ERR_PTR(-ENOMEM); | |
1239 | ||
1240 | in = kzalloc(inlen, GFP_KERNEL); | |
1241 | if (!in) { | |
1242 | err = -ENOMEM; | |
1243 | goto err_free; | |
1244 | } | |
1245 | ||
1246 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
1247 | ||
1248 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MEMIC & 0x3); | |
1249 | MLX5_SET(mkc, mkc, access_mode_4_2, | |
1250 | (MLX5_MKC_ACCESS_MODE_MEMIC >> 2) & 0x7); | |
1251 | MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); | |
1252 | MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); | |
1253 | MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); | |
1254 | MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); | |
1255 | MLX5_SET(mkc, mkc, lr, 1); | |
1256 | ||
1257 | MLX5_SET64(mkc, mkc, len, length); | |
1258 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1259 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1260 | MLX5_SET64(mkc, mkc, start_addr, | |
1261 | memic_addr - pci_resource_start(dev->mdev->pdev, 0)); | |
1262 | ||
1263 | err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen); | |
1264 | if (err) | |
1265 | goto err_in; | |
1266 | ||
1267 | kfree(in); | |
1268 | ||
1269 | mr->umem = NULL; | |
1270 | set_mr_fileds(dev, mr, 0, length, acc); | |
1271 | ||
1272 | return &mr->ibmr; | |
1273 | ||
1274 | err_in: | |
1275 | kfree(in); | |
1276 | ||
1277 | err_free: | |
1278 | kfree(mr); | |
1279 | ||
1280 | return ERR_PTR(err); | |
1281 | } | |
1282 | ||
1283 | struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, | |
1284 | struct ib_dm_mr_attr *attr, | |
1285 | struct uverbs_attr_bundle *attrs) | |
1286 | { | |
1287 | struct mlx5_ib_dm *mdm = to_mdm(dm); | |
1288 | u64 memic_addr; | |
1289 | ||
1290 | if (attr->access_flags & ~MLX5_IB_DM_ALLOWED_ACCESS) | |
1291 | return ERR_PTR(-EINVAL); | |
1292 | ||
1293 | memic_addr = mdm->dev_addr + attr->offset; | |
1294 | ||
1295 | return mlx5_ib_get_memic_mr(pd, memic_addr, attr->length, | |
1296 | attr->access_flags); | |
1297 | } | |
1298 | ||
e126ba97 EC |
1299 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, |
1300 | u64 virt_addr, int access_flags, | |
1301 | struct ib_udata *udata) | |
1302 | { | |
1303 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1304 | struct mlx5_ib_mr *mr = NULL; | |
c8d75a98 | 1305 | bool populate_mtts = false; |
e126ba97 EC |
1306 | struct ib_umem *umem; |
1307 | int page_shift; | |
1308 | int npages; | |
1309 | int ncont; | |
1310 | int order; | |
1311 | int err; | |
1312 | ||
1b19b951 | 1313 | if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM)) |
ea30f013 | 1314 | return ERR_PTR(-EOPNOTSUPP); |
1b19b951 | 1315 | |
900a6d79 EC |
1316 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", |
1317 | start, virt_addr, length, access_flags); | |
81713d37 AK |
1318 | |
1319 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1320 | if (!start && length == U64_MAX) { | |
1321 | if (!(access_flags & IB_ACCESS_ON_DEMAND) || | |
1322 | !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) | |
1323 | return ERR_PTR(-EINVAL); | |
1324 | ||
1325 | mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags); | |
4289861d LR |
1326 | if (IS_ERR(mr)) |
1327 | return ERR_CAST(mr); | |
81713d37 AK |
1328 | return &mr->ibmr; |
1329 | } | |
1330 | #endif | |
1331 | ||
14ab8896 | 1332 | err = mr_umem_get(pd, start, length, access_flags, &umem, &npages, |
395a8e4c | 1333 | &page_shift, &ncont, &order); |
e126ba97 | 1334 | |
ff740aef | 1335 | if (err < 0) |
14ab8896 | 1336 | return ERR_PTR(err); |
e126ba97 | 1337 | |
c8d75a98 | 1338 | if (use_umr(dev, order)) { |
ff740aef IL |
1339 | mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont, |
1340 | page_shift, order, access_flags); | |
e126ba97 | 1341 | if (PTR_ERR(mr) == -EAGAIN) { |
d23a8baf | 1342 | mlx5_ib_dbg(dev, "cache empty for order %d\n", order); |
e126ba97 EC |
1343 | mr = NULL; |
1344 | } | |
c8d75a98 | 1345 | populate_mtts = false; |
ff740aef IL |
1346 | } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) { |
1347 | if (access_flags & IB_ACCESS_ON_DEMAND) { | |
1348 | err = -EINVAL; | |
d23a8baf | 1349 | pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n"); |
ff740aef IL |
1350 | goto error; |
1351 | } | |
c8d75a98 | 1352 | populate_mtts = true; |
e126ba97 EC |
1353 | } |
1354 | ||
6bc1a656 | 1355 | if (!mr) { |
c8d75a98 MD |
1356 | if (!umr_can_modify_entity_size(dev)) |
1357 | populate_mtts = true; | |
6bc1a656 | 1358 | mutex_lock(&dev->slow_path_mutex); |
395a8e4c | 1359 | mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, |
c8d75a98 | 1360 | page_shift, access_flags, populate_mtts); |
6bc1a656 ML |
1361 | mutex_unlock(&dev->slow_path_mutex); |
1362 | } | |
e126ba97 EC |
1363 | |
1364 | if (IS_ERR(mr)) { | |
1365 | err = PTR_ERR(mr); | |
1366 | goto error; | |
1367 | } | |
1368 | ||
a606b0f6 | 1369 | mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1370 | |
1371 | mr->umem = umem; | |
395a8e4c | 1372 | set_mr_fileds(dev, mr, npages, length, access_flags); |
e126ba97 | 1373 | |
b4cfe447 | 1374 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
395a8e4c | 1375 | update_odp_mr(mr); |
b4cfe447 HE |
1376 | #endif |
1377 | ||
c8d75a98 | 1378 | if (!populate_mtts) { |
ff740aef IL |
1379 | int update_xlt_flags = MLX5_IB_UPD_XLT_ENABLE; |
1380 | ||
1381 | if (access_flags & IB_ACCESS_ON_DEMAND) | |
1382 | update_xlt_flags |= MLX5_IB_UPD_XLT_ZAP; | |
e126ba97 | 1383 | |
ff740aef IL |
1384 | err = mlx5_ib_update_xlt(mr, 0, ncont, page_shift, |
1385 | update_xlt_flags); | |
fbcd4983 | 1386 | |
ff740aef | 1387 | if (err) { |
fbcd4983 | 1388 | dereg_mr(dev, mr); |
ff740aef IL |
1389 | return ERR_PTR(err); |
1390 | } | |
1391 | } | |
1392 | ||
c985bd0e | 1393 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
ff740aef | 1394 | mr->live = 1; |
c985bd0e | 1395 | #endif |
ff740aef | 1396 | return &mr->ibmr; |
e126ba97 EC |
1397 | error: |
1398 | ib_umem_release(umem); | |
1399 | return ERR_PTR(err); | |
1400 | } | |
1401 | ||
1402 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) | |
1403 | { | |
89ea94a7 | 1404 | struct mlx5_core_dev *mdev = dev->mdev; |
0025b0bd | 1405 | struct mlx5_umr_wr umrwr = {}; |
e126ba97 | 1406 | |
89ea94a7 MG |
1407 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) |
1408 | return 0; | |
1409 | ||
7d0cc6ed AK |
1410 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR | |
1411 | MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
1412 | umrwr.wr.opcode = MLX5_IB_WR_UMR; | |
1413 | umrwr.mkey = mr->mmkey.key; | |
e126ba97 | 1414 | |
d5ea2df9 | 1415 | return mlx5_ib_post_send_wait(dev, &umrwr); |
e126ba97 EC |
1416 | } |
1417 | ||
7d0cc6ed | 1418 | static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, |
56e11d62 NO |
1419 | int access_flags, int flags) |
1420 | { | |
1421 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
56e11d62 | 1422 | struct mlx5_umr_wr umrwr = {}; |
56e11d62 NO |
1423 | int err; |
1424 | ||
56e11d62 NO |
1425 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE; |
1426 | ||
7d0cc6ed AK |
1427 | umrwr.wr.opcode = MLX5_IB_WR_UMR; |
1428 | umrwr.mkey = mr->mmkey.key; | |
56e11d62 | 1429 | |
31616255 | 1430 | if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) { |
56e11d62 | 1431 | umrwr.pd = pd; |
56e11d62 | 1432 | umrwr.access_flags = access_flags; |
31616255 | 1433 | umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; |
56e11d62 NO |
1434 | } |
1435 | ||
d5ea2df9 | 1436 | err = mlx5_ib_post_send_wait(dev, &umrwr); |
56e11d62 | 1437 | |
56e11d62 NO |
1438 | return err; |
1439 | } | |
1440 | ||
1441 | int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, | |
1442 | u64 length, u64 virt_addr, int new_access_flags, | |
1443 | struct ib_pd *new_pd, struct ib_udata *udata) | |
1444 | { | |
1445 | struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); | |
1446 | struct mlx5_ib_mr *mr = to_mmr(ib_mr); | |
1447 | struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd; | |
1448 | int access_flags = flags & IB_MR_REREG_ACCESS ? | |
1449 | new_access_flags : | |
1450 | mr->access_flags; | |
56e11d62 | 1451 | int page_shift = 0; |
7d0cc6ed | 1452 | int upd_flags = 0; |
56e11d62 NO |
1453 | int npages = 0; |
1454 | int ncont = 0; | |
1455 | int order = 0; | |
b4bd701a | 1456 | u64 addr, len; |
56e11d62 NO |
1457 | int err; |
1458 | ||
1459 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", | |
1460 | start, virt_addr, length, access_flags); | |
1461 | ||
7d0cc6ed AK |
1462 | atomic_sub(mr->npages, &dev->mdev->priv.reg_pages); |
1463 | ||
b4bd701a LR |
1464 | if (!mr->umem) |
1465 | return -EINVAL; | |
1466 | ||
1467 | if (flags & IB_MR_REREG_TRANS) { | |
1468 | addr = virt_addr; | |
1469 | len = length; | |
1470 | } else { | |
1471 | addr = mr->umem->address; | |
1472 | len = mr->umem->length; | |
1473 | } | |
1474 | ||
56e11d62 NO |
1475 | if (flags != IB_MR_REREG_PD) { |
1476 | /* | |
1477 | * Replace umem. This needs to be done whether or not UMR is | |
1478 | * used. | |
1479 | */ | |
1480 | flags |= IB_MR_REREG_TRANS; | |
1481 | ib_umem_release(mr->umem); | |
b4bd701a | 1482 | mr->umem = NULL; |
14ab8896 AB |
1483 | err = mr_umem_get(pd, addr, len, access_flags, &mr->umem, |
1484 | &npages, &page_shift, &ncont, &order); | |
4638a3b2 LR |
1485 | if (err) |
1486 | goto err; | |
56e11d62 NO |
1487 | } |
1488 | ||
1489 | if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) { | |
1490 | /* | |
1491 | * UMR can't be used - MKey needs to be replaced. | |
1492 | */ | |
eeea6953 | 1493 | if (mr->allocated_from_cache) |
56e11d62 | 1494 | err = unreg_umr(dev, mr); |
eeea6953 | 1495 | else |
56e11d62 | 1496 | err = destroy_mkey(dev, mr); |
56e11d62 | 1497 | if (err) |
4638a3b2 | 1498 | goto err; |
56e11d62 NO |
1499 | |
1500 | mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont, | |
ff740aef | 1501 | page_shift, access_flags, true); |
56e11d62 | 1502 | |
4638a3b2 LR |
1503 | if (IS_ERR(mr)) { |
1504 | err = PTR_ERR(mr); | |
1505 | mr = to_mmr(ib_mr); | |
1506 | goto err; | |
1507 | } | |
56e11d62 | 1508 | |
8b7ff7f3 | 1509 | mr->allocated_from_cache = 0; |
c985bd0e | 1510 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
ff740aef | 1511 | mr->live = 1; |
c985bd0e | 1512 | #endif |
56e11d62 NO |
1513 | } else { |
1514 | /* | |
1515 | * Send a UMR WQE | |
1516 | */ | |
7d0cc6ed AK |
1517 | mr->ibmr.pd = pd; |
1518 | mr->access_flags = access_flags; | |
1519 | mr->mmkey.iova = addr; | |
1520 | mr->mmkey.size = len; | |
1521 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
1522 | ||
1523 | if (flags & IB_MR_REREG_TRANS) { | |
1524 | upd_flags = MLX5_IB_UPD_XLT_ADDR; | |
1525 | if (flags & IB_MR_REREG_PD) | |
1526 | upd_flags |= MLX5_IB_UPD_XLT_PD; | |
1527 | if (flags & IB_MR_REREG_ACCESS) | |
1528 | upd_flags |= MLX5_IB_UPD_XLT_ACCESS; | |
1529 | err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, | |
1530 | upd_flags); | |
1531 | } else { | |
1532 | err = rereg_umr(pd, mr, access_flags, flags); | |
1533 | } | |
1534 | ||
4638a3b2 LR |
1535 | if (err) |
1536 | goto err; | |
56e11d62 NO |
1537 | } |
1538 | ||
7d0cc6ed | 1539 | set_mr_fileds(dev, mr, npages, len, access_flags); |
56e11d62 | 1540 | |
56e11d62 NO |
1541 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1542 | update_odp_mr(mr); | |
1543 | #endif | |
56e11d62 | 1544 | return 0; |
4638a3b2 LR |
1545 | |
1546 | err: | |
1547 | if (mr->umem) { | |
1548 | ib_umem_release(mr->umem); | |
1549 | mr->umem = NULL; | |
1550 | } | |
1551 | clean_mr(dev, mr); | |
1552 | return err; | |
56e11d62 NO |
1553 | } |
1554 | ||
8a187ee5 SG |
1555 | static int |
1556 | mlx5_alloc_priv_descs(struct ib_device *device, | |
1557 | struct mlx5_ib_mr *mr, | |
1558 | int ndescs, | |
1559 | int desc_size) | |
1560 | { | |
1561 | int size = ndescs * desc_size; | |
1562 | int add_size; | |
1563 | int ret; | |
1564 | ||
1565 | add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0); | |
1566 | ||
1567 | mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL); | |
1568 | if (!mr->descs_alloc) | |
1569 | return -ENOMEM; | |
1570 | ||
1571 | mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN); | |
1572 | ||
9b0c289e | 1573 | mr->desc_map = dma_map_single(device->dev.parent, mr->descs, |
8a187ee5 | 1574 | size, DMA_TO_DEVICE); |
9b0c289e | 1575 | if (dma_mapping_error(device->dev.parent, mr->desc_map)) { |
8a187ee5 SG |
1576 | ret = -ENOMEM; |
1577 | goto err; | |
1578 | } | |
1579 | ||
1580 | return 0; | |
1581 | err: | |
1582 | kfree(mr->descs_alloc); | |
1583 | ||
1584 | return ret; | |
1585 | } | |
1586 | ||
1587 | static void | |
1588 | mlx5_free_priv_descs(struct mlx5_ib_mr *mr) | |
1589 | { | |
1590 | if (mr->descs) { | |
1591 | struct ib_device *device = mr->ibmr.device; | |
1592 | int size = mr->max_descs * mr->desc_size; | |
1593 | ||
9b0c289e | 1594 | dma_unmap_single(device->dev.parent, mr->desc_map, |
8a187ee5 SG |
1595 | size, DMA_TO_DEVICE); |
1596 | kfree(mr->descs_alloc); | |
1597 | mr->descs = NULL; | |
1598 | } | |
1599 | } | |
1600 | ||
eeea6953 | 1601 | static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
e126ba97 | 1602 | { |
8b7ff7f3 | 1603 | int allocated_from_cache = mr->allocated_from_cache; |
e126ba97 | 1604 | |
8b91ffc1 SG |
1605 | if (mr->sig) { |
1606 | if (mlx5_core_destroy_psv(dev->mdev, | |
1607 | mr->sig->psv_memory.psv_idx)) | |
1608 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1609 | mr->sig->psv_memory.psv_idx); | |
1610 | if (mlx5_core_destroy_psv(dev->mdev, | |
1611 | mr->sig->psv_wire.psv_idx)) | |
1612 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1613 | mr->sig->psv_wire.psv_idx); | |
1614 | kfree(mr->sig); | |
1615 | mr->sig = NULL; | |
1616 | } | |
1617 | ||
8a187ee5 SG |
1618 | mlx5_free_priv_descs(mr); |
1619 | ||
eeea6953 LR |
1620 | if (!allocated_from_cache) |
1621 | destroy_mkey(dev, mr); | |
6aec21f6 HE |
1622 | } |
1623 | ||
eeea6953 | 1624 | static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
6aec21f6 | 1625 | { |
6aec21f6 HE |
1626 | int npages = mr->npages; |
1627 | struct ib_umem *umem = mr->umem; | |
1628 | ||
1629 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
b4cfe447 HE |
1630 | if (umem && umem->odp_data) { |
1631 | /* Prevent new page faults from succeeding */ | |
1632 | mr->live = 0; | |
6aec21f6 HE |
1633 | /* Wait for all running page-fault handlers to finish. */ |
1634 | synchronize_srcu(&dev->mr_srcu); | |
b4cfe447 | 1635 | /* Destroy all page mappings */ |
81713d37 AK |
1636 | if (umem->odp_data->page_list) |
1637 | mlx5_ib_invalidate_range(umem, ib_umem_start(umem), | |
1638 | ib_umem_end(umem)); | |
1639 | else | |
1640 | mlx5_ib_free_implicit_mr(mr); | |
b4cfe447 HE |
1641 | /* |
1642 | * We kill the umem before the MR for ODP, | |
1643 | * so that there will not be any invalidations in | |
1644 | * flight, looking at the *mr struct. | |
1645 | */ | |
1646 | ib_umem_release(umem); | |
1647 | atomic_sub(npages, &dev->mdev->priv.reg_pages); | |
1648 | ||
1649 | /* Avoid double-freeing the umem. */ | |
1650 | umem = NULL; | |
1651 | } | |
6aec21f6 | 1652 | #endif |
fbcd4983 | 1653 | clean_mr(dev, mr); |
6aec21f6 | 1654 | |
dd9a4034 VF |
1655 | /* |
1656 | * We should unregister the DMA address from the HCA before | |
1657 | * remove the DMA mapping. | |
1658 | */ | |
1659 | mlx5_mr_cache_free(dev, mr); | |
e126ba97 EC |
1660 | if (umem) { |
1661 | ib_umem_release(umem); | |
6aec21f6 | 1662 | atomic_sub(npages, &dev->mdev->priv.reg_pages); |
e126ba97 | 1663 | } |
f3f134f5 LR |
1664 | if (!mr->allocated_from_cache) |
1665 | kfree(mr); | |
e126ba97 EC |
1666 | } |
1667 | ||
fbcd4983 IL |
1668 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr) |
1669 | { | |
eeea6953 LR |
1670 | dereg_mr(to_mdev(ibmr->device), to_mmr(ibmr)); |
1671 | return 0; | |
fbcd4983 IL |
1672 | } |
1673 | ||
9bee178b SG |
1674 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, |
1675 | enum ib_mr_type mr_type, | |
1676 | u32 max_num_sg) | |
3121e3c4 SG |
1677 | { |
1678 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1679 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
b005d316 | 1680 | int ndescs = ALIGN(max_num_sg, 4); |
ec22eb53 SM |
1681 | struct mlx5_ib_mr *mr; |
1682 | void *mkc; | |
1683 | u32 *in; | |
b005d316 | 1684 | int err; |
3121e3c4 SG |
1685 | |
1686 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1687 | if (!mr) | |
1688 | return ERR_PTR(-ENOMEM); | |
1689 | ||
ec22eb53 | 1690 | in = kzalloc(inlen, GFP_KERNEL); |
3121e3c4 SG |
1691 | if (!in) { |
1692 | err = -ENOMEM; | |
1693 | goto err_free; | |
1694 | } | |
1695 | ||
ec22eb53 SM |
1696 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1697 | MLX5_SET(mkc, mkc, free, 1); | |
1698 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1699 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1700 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
3121e3c4 | 1701 | |
9bee178b | 1702 | if (mr_type == IB_MR_TYPE_MEM_REG) { |
ec22eb53 SM |
1703 | mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT; |
1704 | MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); | |
8a187ee5 | 1705 | err = mlx5_alloc_priv_descs(pd->device, mr, |
31616255 | 1706 | ndescs, sizeof(struct mlx5_mtt)); |
8a187ee5 SG |
1707 | if (err) |
1708 | goto err_free_in; | |
1709 | ||
31616255 | 1710 | mr->desc_size = sizeof(struct mlx5_mtt); |
8a187ee5 | 1711 | mr->max_descs = ndescs; |
b005d316 | 1712 | } else if (mr_type == IB_MR_TYPE_SG_GAPS) { |
ec22eb53 | 1713 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
b005d316 SG |
1714 | |
1715 | err = mlx5_alloc_priv_descs(pd->device, mr, | |
1716 | ndescs, sizeof(struct mlx5_klm)); | |
1717 | if (err) | |
1718 | goto err_free_in; | |
1719 | mr->desc_size = sizeof(struct mlx5_klm); | |
1720 | mr->max_descs = ndescs; | |
9bee178b | 1721 | } else if (mr_type == IB_MR_TYPE_SIGNATURE) { |
3121e3c4 SG |
1722 | u32 psv_index[2]; |
1723 | ||
ec22eb53 SM |
1724 | MLX5_SET(mkc, mkc, bsf_en, 1); |
1725 | MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE); | |
3121e3c4 SG |
1726 | mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL); |
1727 | if (!mr->sig) { | |
1728 | err = -ENOMEM; | |
1729 | goto err_free_in; | |
1730 | } | |
1731 | ||
1732 | /* create mem & wire PSVs */ | |
9603b61d | 1733 | err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, |
3121e3c4 SG |
1734 | 2, psv_index); |
1735 | if (err) | |
1736 | goto err_free_sig; | |
1737 | ||
ec22eb53 | 1738 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
3121e3c4 SG |
1739 | mr->sig->psv_memory.psv_idx = psv_index[0]; |
1740 | mr->sig->psv_wire.psv_idx = psv_index[1]; | |
d5436ba0 SG |
1741 | |
1742 | mr->sig->sig_status_checked = true; | |
1743 | mr->sig->sig_err_exists = false; | |
1744 | /* Next UMR, Arm SIGERR */ | |
1745 | ++mr->sig->sigerr_count; | |
9bee178b SG |
1746 | } else { |
1747 | mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type); | |
1748 | err = -EINVAL; | |
1749 | goto err_free_in; | |
3121e3c4 SG |
1750 | } |
1751 | ||
cdbd0d2b AL |
1752 | MLX5_SET(mkc, mkc, access_mode_1_0, mr->access_mode & 0x3); |
1753 | MLX5_SET(mkc, mkc, access_mode_4_2, (mr->access_mode >> 2) & 0x7); | |
ec22eb53 SM |
1754 | MLX5_SET(mkc, mkc, umr_en, 1); |
1755 | ||
45e6ae7e | 1756 | mr->ibmr.device = pd->device; |
ec22eb53 | 1757 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); |
3121e3c4 SG |
1758 | if (err) |
1759 | goto err_destroy_psv; | |
1760 | ||
aa8e08d2 | 1761 | mr->mmkey.type = MLX5_MKEY_MR; |
a606b0f6 MB |
1762 | mr->ibmr.lkey = mr->mmkey.key; |
1763 | mr->ibmr.rkey = mr->mmkey.key; | |
3121e3c4 SG |
1764 | mr->umem = NULL; |
1765 | kfree(in); | |
1766 | ||
1767 | return &mr->ibmr; | |
1768 | ||
1769 | err_destroy_psv: | |
1770 | if (mr->sig) { | |
9603b61d | 1771 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1772 | mr->sig->psv_memory.psv_idx)) |
1773 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1774 | mr->sig->psv_memory.psv_idx); | |
9603b61d | 1775 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1776 | mr->sig->psv_wire.psv_idx)) |
1777 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1778 | mr->sig->psv_wire.psv_idx); | |
1779 | } | |
8a187ee5 | 1780 | mlx5_free_priv_descs(mr); |
3121e3c4 SG |
1781 | err_free_sig: |
1782 | kfree(mr->sig); | |
1783 | err_free_in: | |
1784 | kfree(in); | |
1785 | err_free: | |
1786 | kfree(mr); | |
1787 | return ERR_PTR(err); | |
1788 | } | |
1789 | ||
d2370e0a MB |
1790 | struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
1791 | struct ib_udata *udata) | |
1792 | { | |
1793 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1794 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
d2370e0a | 1795 | struct mlx5_ib_mw *mw = NULL; |
ec22eb53 SM |
1796 | u32 *in = NULL; |
1797 | void *mkc; | |
d2370e0a MB |
1798 | int ndescs; |
1799 | int err; | |
1800 | struct mlx5_ib_alloc_mw req = {}; | |
1801 | struct { | |
1802 | __u32 comp_mask; | |
1803 | __u32 response_length; | |
1804 | } resp = {}; | |
1805 | ||
1806 | err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); | |
1807 | if (err) | |
1808 | return ERR_PTR(err); | |
1809 | ||
1810 | if (req.comp_mask || req.reserved1 || req.reserved2) | |
1811 | return ERR_PTR(-EOPNOTSUPP); | |
1812 | ||
1813 | if (udata->inlen > sizeof(req) && | |
1814 | !ib_is_udata_cleared(udata, sizeof(req), | |
1815 | udata->inlen - sizeof(req))) | |
1816 | return ERR_PTR(-EOPNOTSUPP); | |
1817 | ||
1818 | ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4); | |
1819 | ||
1820 | mw = kzalloc(sizeof(*mw), GFP_KERNEL); | |
ec22eb53 | 1821 | in = kzalloc(inlen, GFP_KERNEL); |
d2370e0a MB |
1822 | if (!mw || !in) { |
1823 | err = -ENOMEM; | |
1824 | goto free; | |
1825 | } | |
1826 | ||
ec22eb53 SM |
1827 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1828 | ||
1829 | MLX5_SET(mkc, mkc, free, 1); | |
1830 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1831 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1832 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1833 | MLX5_SET(mkc, mkc, lr, 1); | |
cdbd0d2b | 1834 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS); |
ec22eb53 SM |
1835 | MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2))); |
1836 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1837 | ||
1838 | err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen); | |
d2370e0a MB |
1839 | if (err) |
1840 | goto free; | |
1841 | ||
aa8e08d2 | 1842 | mw->mmkey.type = MLX5_MKEY_MW; |
d2370e0a | 1843 | mw->ibmw.rkey = mw->mmkey.key; |
db570d7d | 1844 | mw->ndescs = ndescs; |
d2370e0a MB |
1845 | |
1846 | resp.response_length = min(offsetof(typeof(resp), response_length) + | |
1847 | sizeof(resp.response_length), udata->outlen); | |
1848 | if (resp.response_length) { | |
1849 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
1850 | if (err) { | |
1851 | mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey); | |
1852 | goto free; | |
1853 | } | |
1854 | } | |
1855 | ||
1856 | kfree(in); | |
1857 | return &mw->ibmw; | |
1858 | ||
1859 | free: | |
1860 | kfree(mw); | |
1861 | kfree(in); | |
1862 | return ERR_PTR(err); | |
1863 | } | |
1864 | ||
1865 | int mlx5_ib_dealloc_mw(struct ib_mw *mw) | |
1866 | { | |
1867 | struct mlx5_ib_mw *mmw = to_mmw(mw); | |
1868 | int err; | |
1869 | ||
1870 | err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev, | |
1871 | &mmw->mmkey); | |
1872 | if (!err) | |
1873 | kfree(mmw); | |
1874 | return err; | |
1875 | } | |
1876 | ||
d5436ba0 SG |
1877 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
1878 | struct ib_mr_status *mr_status) | |
1879 | { | |
1880 | struct mlx5_ib_mr *mmr = to_mmr(ibmr); | |
1881 | int ret = 0; | |
1882 | ||
1883 | if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { | |
1884 | pr_err("Invalid status check mask\n"); | |
1885 | ret = -EINVAL; | |
1886 | goto done; | |
1887 | } | |
1888 | ||
1889 | mr_status->fail_status = 0; | |
1890 | if (check_mask & IB_MR_CHECK_SIG_STATUS) { | |
1891 | if (!mmr->sig) { | |
1892 | ret = -EINVAL; | |
1893 | pr_err("signature status check requested on a non-signature enabled MR\n"); | |
1894 | goto done; | |
1895 | } | |
1896 | ||
1897 | mmr->sig->sig_status_checked = true; | |
1898 | if (!mmr->sig->sig_err_exists) | |
1899 | goto done; | |
1900 | ||
1901 | if (ibmr->lkey == mmr->sig->err_item.key) | |
1902 | memcpy(&mr_status->sig_err, &mmr->sig->err_item, | |
1903 | sizeof(mr_status->sig_err)); | |
1904 | else { | |
1905 | mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; | |
1906 | mr_status->sig_err.sig_err_offset = 0; | |
1907 | mr_status->sig_err.key = mmr->sig->err_item.key; | |
1908 | } | |
1909 | ||
1910 | mmr->sig->sig_err_exists = false; | |
1911 | mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; | |
1912 | } | |
1913 | ||
1914 | done: | |
1915 | return ret; | |
1916 | } | |
8a187ee5 | 1917 | |
b005d316 SG |
1918 | static int |
1919 | mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr, | |
1920 | struct scatterlist *sgl, | |
ff2ba993 | 1921 | unsigned short sg_nents, |
9aa8b321 | 1922 | unsigned int *sg_offset_p) |
b005d316 SG |
1923 | { |
1924 | struct scatterlist *sg = sgl; | |
1925 | struct mlx5_klm *klms = mr->descs; | |
9aa8b321 | 1926 | unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; |
b005d316 SG |
1927 | u32 lkey = mr->ibmr.pd->local_dma_lkey; |
1928 | int i; | |
1929 | ||
ff2ba993 | 1930 | mr->ibmr.iova = sg_dma_address(sg) + sg_offset; |
b005d316 | 1931 | mr->ibmr.length = 0; |
b005d316 SG |
1932 | |
1933 | for_each_sg(sgl, sg, sg_nents, i) { | |
99975cd4 | 1934 | if (unlikely(i >= mr->max_descs)) |
b005d316 | 1935 | break; |
ff2ba993 CH |
1936 | klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset); |
1937 | klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset); | |
b005d316 | 1938 | klms[i].key = cpu_to_be32(lkey); |
0a49f2c3 | 1939 | mr->ibmr.length += sg_dma_len(sg) - sg_offset; |
ff2ba993 CH |
1940 | |
1941 | sg_offset = 0; | |
b005d316 | 1942 | } |
da343b6d | 1943 | mr->ndescs = i; |
b005d316 | 1944 | |
9aa8b321 BVA |
1945 | if (sg_offset_p) |
1946 | *sg_offset_p = sg_offset; | |
1947 | ||
b005d316 SG |
1948 | return i; |
1949 | } | |
1950 | ||
8a187ee5 SG |
1951 | static int mlx5_set_page(struct ib_mr *ibmr, u64 addr) |
1952 | { | |
1953 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1954 | __be64 *descs; | |
1955 | ||
1956 | if (unlikely(mr->ndescs == mr->max_descs)) | |
1957 | return -ENOMEM; | |
1958 | ||
1959 | descs = mr->descs; | |
1960 | descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); | |
1961 | ||
1962 | return 0; | |
1963 | } | |
1964 | ||
ff2ba993 | 1965 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 1966 | unsigned int *sg_offset) |
8a187ee5 SG |
1967 | { |
1968 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1969 | int n; | |
1970 | ||
1971 | mr->ndescs = 0; | |
1972 | ||
1973 | ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map, | |
1974 | mr->desc_size * mr->max_descs, | |
1975 | DMA_TO_DEVICE); | |
1976 | ||
ec22eb53 | 1977 | if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) |
ff2ba993 | 1978 | n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset); |
b005d316 | 1979 | else |
ff2ba993 CH |
1980 | n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, |
1981 | mlx5_set_page); | |
8a187ee5 SG |
1982 | |
1983 | ib_dma_sync_single_for_device(ibmr->device, mr->desc_map, | |
1984 | mr->desc_size * mr->max_descs, | |
1985 | DMA_TO_DEVICE); | |
1986 | ||
1987 | return n; | |
1988 | } |