Commit | Line | Data |
---|---|---|
e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | ||
34 | #include <linux/kref.h> | |
35 | #include <linux/random.h> | |
36 | #include <linux/debugfs.h> | |
37 | #include <linux/export.h> | |
746b5583 | 38 | #include <linux/delay.h> |
e126ba97 | 39 | #include <rdma/ib_umem.h> |
b4cfe447 | 40 | #include <rdma/ib_umem_odp.h> |
968e78dd | 41 | #include <rdma/ib_verbs.h> |
e126ba97 EC |
42 | #include "mlx5_ib.h" |
43 | ||
44 | enum { | |
746b5583 | 45 | MAX_PENDING_REG_MR = 8, |
e126ba97 EC |
46 | }; |
47 | ||
832a6b06 HE |
48 | #define MLX5_UMR_ALIGN 2048 |
49 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
50 | static __be64 mlx5_ib_update_mtt_emergency_buffer[ | |
51 | MLX5_UMR_MTT_MIN_CHUNK_SIZE/sizeof(__be64)] | |
52 | __aligned(MLX5_UMR_ALIGN); | |
53 | static DEFINE_MUTEX(mlx5_ib_update_mtt_emergency_buffer_mutex); | |
54 | #endif | |
fe45f827 | 55 | |
6aec21f6 HE |
56 | static int clean_mr(struct mlx5_ib_mr *mr); |
57 | ||
b4cfe447 HE |
58 | static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
59 | { | |
60 | int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmr); | |
61 | ||
62 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
63 | /* Wait until all page fault handlers using the mr complete. */ | |
64 | synchronize_srcu(&dev->mr_srcu); | |
65 | #endif | |
66 | ||
67 | return err; | |
68 | } | |
69 | ||
e126ba97 EC |
70 | static int order2idx(struct mlx5_ib_dev *dev, int order) |
71 | { | |
72 | struct mlx5_mr_cache *cache = &dev->cache; | |
73 | ||
74 | if (order < cache->ent[0].order) | |
75 | return 0; | |
76 | else | |
77 | return order - cache->ent[0].order; | |
78 | } | |
79 | ||
746b5583 EC |
80 | static void reg_mr_callback(int status, void *context) |
81 | { | |
82 | struct mlx5_ib_mr *mr = context; | |
83 | struct mlx5_ib_dev *dev = mr->dev; | |
84 | struct mlx5_mr_cache *cache = &dev->cache; | |
85 | int c = order2idx(dev, mr->order); | |
86 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
87 | u8 key; | |
746b5583 | 88 | unsigned long flags; |
9603b61d | 89 | struct mlx5_mr_table *table = &dev->mdev->priv.mr_table; |
8605933a | 90 | int err; |
746b5583 | 91 | |
746b5583 EC |
92 | spin_lock_irqsave(&ent->lock, flags); |
93 | ent->pending--; | |
94 | spin_unlock_irqrestore(&ent->lock, flags); | |
95 | if (status) { | |
96 | mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status); | |
97 | kfree(mr); | |
98 | dev->fill_delay = 1; | |
99 | mod_timer(&dev->delay_timer, jiffies + HZ); | |
100 | return; | |
101 | } | |
102 | ||
103 | if (mr->out.hdr.status) { | |
104 | mlx5_ib_warn(dev, "failed - status %d, syndorme 0x%x\n", | |
105 | mr->out.hdr.status, | |
106 | be32_to_cpu(mr->out.hdr.syndrome)); | |
107 | kfree(mr); | |
108 | dev->fill_delay = 1; | |
109 | mod_timer(&dev->delay_timer, jiffies + HZ); | |
110 | return; | |
111 | } | |
112 | ||
9603b61d JM |
113 | spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags); |
114 | key = dev->mdev->priv.mkey_key++; | |
115 | spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags); | |
746b5583 EC |
116 | mr->mmr.key = mlx5_idx_to_mkey(be32_to_cpu(mr->out.mkey) & 0xffffff) | key; |
117 | ||
118 | cache->last_add = jiffies; | |
119 | ||
120 | spin_lock_irqsave(&ent->lock, flags); | |
121 | list_add_tail(&mr->list, &ent->head); | |
122 | ent->cur++; | |
123 | ent->size++; | |
124 | spin_unlock_irqrestore(&ent->lock, flags); | |
8605933a HE |
125 | |
126 | write_lock_irqsave(&table->lock, flags); | |
127 | err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmr.key), | |
128 | &mr->mmr); | |
129 | if (err) | |
130 | pr_err("Error inserting to mr tree. 0x%x\n", -err); | |
131 | write_unlock_irqrestore(&table->lock, flags); | |
746b5583 EC |
132 | } |
133 | ||
e126ba97 EC |
134 | static int add_keys(struct mlx5_ib_dev *dev, int c, int num) |
135 | { | |
e126ba97 EC |
136 | struct mlx5_mr_cache *cache = &dev->cache; |
137 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
138 | struct mlx5_create_mkey_mbox_in *in; | |
139 | struct mlx5_ib_mr *mr; | |
140 | int npages = 1 << ent->order; | |
e126ba97 EC |
141 | int err = 0; |
142 | int i; | |
143 | ||
144 | in = kzalloc(sizeof(*in), GFP_KERNEL); | |
145 | if (!in) | |
146 | return -ENOMEM; | |
147 | ||
148 | for (i = 0; i < num; i++) { | |
746b5583 EC |
149 | if (ent->pending >= MAX_PENDING_REG_MR) { |
150 | err = -EAGAIN; | |
151 | break; | |
152 | } | |
153 | ||
e126ba97 EC |
154 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
155 | if (!mr) { | |
156 | err = -ENOMEM; | |
746b5583 | 157 | break; |
e126ba97 EC |
158 | } |
159 | mr->order = ent->order; | |
160 | mr->umred = 1; | |
746b5583 | 161 | mr->dev = dev; |
968e78dd | 162 | in->seg.status = MLX5_MKEY_STATUS_FREE; |
e126ba97 EC |
163 | in->seg.xlt_oct_size = cpu_to_be32((npages + 1) / 2); |
164 | in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
165 | in->seg.flags = MLX5_ACCESS_MODE_MTT | MLX5_PERM_UMR_EN; | |
166 | in->seg.log2_page_size = 12; | |
167 | ||
746b5583 EC |
168 | spin_lock_irq(&ent->lock); |
169 | ent->pending++; | |
170 | spin_unlock_irq(&ent->lock); | |
9603b61d | 171 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmr, in, |
746b5583 EC |
172 | sizeof(*in), reg_mr_callback, |
173 | mr, &mr->out); | |
e126ba97 | 174 | if (err) { |
d14e7110 EC |
175 | spin_lock_irq(&ent->lock); |
176 | ent->pending--; | |
177 | spin_unlock_irq(&ent->lock); | |
e126ba97 | 178 | mlx5_ib_warn(dev, "create mkey failed %d\n", err); |
e126ba97 | 179 | kfree(mr); |
746b5583 | 180 | break; |
e126ba97 | 181 | } |
e126ba97 EC |
182 | } |
183 | ||
e126ba97 EC |
184 | kfree(in); |
185 | return err; | |
186 | } | |
187 | ||
188 | static void remove_keys(struct mlx5_ib_dev *dev, int c, int num) | |
189 | { | |
e126ba97 EC |
190 | struct mlx5_mr_cache *cache = &dev->cache; |
191 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
192 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
193 | int err; |
194 | int i; | |
195 | ||
196 | for (i = 0; i < num; i++) { | |
746b5583 | 197 | spin_lock_irq(&ent->lock); |
e126ba97 | 198 | if (list_empty(&ent->head)) { |
746b5583 | 199 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
200 | return; |
201 | } | |
202 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
203 | list_del(&mr->list); | |
204 | ent->cur--; | |
205 | ent->size--; | |
746b5583 | 206 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 207 | err = destroy_mkey(dev, mr); |
203099fd | 208 | if (err) |
e126ba97 | 209 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 210 | else |
e126ba97 | 211 | kfree(mr); |
e126ba97 EC |
212 | } |
213 | } | |
214 | ||
215 | static ssize_t size_write(struct file *filp, const char __user *buf, | |
216 | size_t count, loff_t *pos) | |
217 | { | |
218 | struct mlx5_cache_ent *ent = filp->private_data; | |
219 | struct mlx5_ib_dev *dev = ent->dev; | |
220 | char lbuf[20]; | |
221 | u32 var; | |
222 | int err; | |
223 | int c; | |
224 | ||
225 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 226 | return -EFAULT; |
e126ba97 EC |
227 | |
228 | c = order2idx(dev, ent->order); | |
229 | lbuf[sizeof(lbuf) - 1] = 0; | |
230 | ||
231 | if (sscanf(lbuf, "%u", &var) != 1) | |
232 | return -EINVAL; | |
233 | ||
234 | if (var < ent->limit) | |
235 | return -EINVAL; | |
236 | ||
237 | if (var > ent->size) { | |
746b5583 EC |
238 | do { |
239 | err = add_keys(dev, c, var - ent->size); | |
240 | if (err && err != -EAGAIN) | |
241 | return err; | |
242 | ||
243 | usleep_range(3000, 5000); | |
244 | } while (err); | |
e126ba97 EC |
245 | } else if (var < ent->size) { |
246 | remove_keys(dev, c, ent->size - var); | |
247 | } | |
248 | ||
249 | return count; | |
250 | } | |
251 | ||
252 | static ssize_t size_read(struct file *filp, char __user *buf, size_t count, | |
253 | loff_t *pos) | |
254 | { | |
255 | struct mlx5_cache_ent *ent = filp->private_data; | |
256 | char lbuf[20]; | |
257 | int err; | |
258 | ||
259 | if (*pos) | |
260 | return 0; | |
261 | ||
262 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size); | |
263 | if (err < 0) | |
264 | return err; | |
265 | ||
266 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 267 | return -EFAULT; |
e126ba97 EC |
268 | |
269 | *pos += err; | |
270 | ||
271 | return err; | |
272 | } | |
273 | ||
274 | static const struct file_operations size_fops = { | |
275 | .owner = THIS_MODULE, | |
276 | .open = simple_open, | |
277 | .write = size_write, | |
278 | .read = size_read, | |
279 | }; | |
280 | ||
281 | static ssize_t limit_write(struct file *filp, const char __user *buf, | |
282 | size_t count, loff_t *pos) | |
283 | { | |
284 | struct mlx5_cache_ent *ent = filp->private_data; | |
285 | struct mlx5_ib_dev *dev = ent->dev; | |
286 | char lbuf[20]; | |
287 | u32 var; | |
288 | int err; | |
289 | int c; | |
290 | ||
291 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 292 | return -EFAULT; |
e126ba97 EC |
293 | |
294 | c = order2idx(dev, ent->order); | |
295 | lbuf[sizeof(lbuf) - 1] = 0; | |
296 | ||
297 | if (sscanf(lbuf, "%u", &var) != 1) | |
298 | return -EINVAL; | |
299 | ||
300 | if (var > ent->size) | |
301 | return -EINVAL; | |
302 | ||
303 | ent->limit = var; | |
304 | ||
305 | if (ent->cur < ent->limit) { | |
306 | err = add_keys(dev, c, 2 * ent->limit - ent->cur); | |
307 | if (err) | |
308 | return err; | |
309 | } | |
310 | ||
311 | return count; | |
312 | } | |
313 | ||
314 | static ssize_t limit_read(struct file *filp, char __user *buf, size_t count, | |
315 | loff_t *pos) | |
316 | { | |
317 | struct mlx5_cache_ent *ent = filp->private_data; | |
318 | char lbuf[20]; | |
319 | int err; | |
320 | ||
321 | if (*pos) | |
322 | return 0; | |
323 | ||
324 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit); | |
325 | if (err < 0) | |
326 | return err; | |
327 | ||
328 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 329 | return -EFAULT; |
e126ba97 EC |
330 | |
331 | *pos += err; | |
332 | ||
333 | return err; | |
334 | } | |
335 | ||
336 | static const struct file_operations limit_fops = { | |
337 | .owner = THIS_MODULE, | |
338 | .open = simple_open, | |
339 | .write = limit_write, | |
340 | .read = limit_read, | |
341 | }; | |
342 | ||
343 | static int someone_adding(struct mlx5_mr_cache *cache) | |
344 | { | |
345 | int i; | |
346 | ||
347 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
348 | if (cache->ent[i].cur < cache->ent[i].limit) | |
349 | return 1; | |
350 | } | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | static void __cache_work_func(struct mlx5_cache_ent *ent) | |
356 | { | |
357 | struct mlx5_ib_dev *dev = ent->dev; | |
358 | struct mlx5_mr_cache *cache = &dev->cache; | |
359 | int i = order2idx(dev, ent->order); | |
746b5583 | 360 | int err; |
e126ba97 EC |
361 | |
362 | if (cache->stopped) | |
363 | return; | |
364 | ||
365 | ent = &dev->cache.ent[i]; | |
746b5583 EC |
366 | if (ent->cur < 2 * ent->limit && !dev->fill_delay) { |
367 | err = add_keys(dev, i, 1); | |
368 | if (ent->cur < 2 * ent->limit) { | |
369 | if (err == -EAGAIN) { | |
370 | mlx5_ib_dbg(dev, "returned eagain, order %d\n", | |
371 | i + 2); | |
372 | queue_delayed_work(cache->wq, &ent->dwork, | |
373 | msecs_to_jiffies(3)); | |
374 | } else if (err) { | |
375 | mlx5_ib_warn(dev, "command failed order %d, err %d\n", | |
376 | i + 2, err); | |
377 | queue_delayed_work(cache->wq, &ent->dwork, | |
378 | msecs_to_jiffies(1000)); | |
379 | } else { | |
380 | queue_work(cache->wq, &ent->work); | |
381 | } | |
382 | } | |
e126ba97 EC |
383 | } else if (ent->cur > 2 * ent->limit) { |
384 | if (!someone_adding(cache) && | |
746b5583 | 385 | time_after(jiffies, cache->last_add + 300 * HZ)) { |
e126ba97 EC |
386 | remove_keys(dev, i, 1); |
387 | if (ent->cur > ent->limit) | |
388 | queue_work(cache->wq, &ent->work); | |
389 | } else { | |
746b5583 | 390 | queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ); |
e126ba97 EC |
391 | } |
392 | } | |
393 | } | |
394 | ||
395 | static void delayed_cache_work_func(struct work_struct *work) | |
396 | { | |
397 | struct mlx5_cache_ent *ent; | |
398 | ||
399 | ent = container_of(work, struct mlx5_cache_ent, dwork.work); | |
400 | __cache_work_func(ent); | |
401 | } | |
402 | ||
403 | static void cache_work_func(struct work_struct *work) | |
404 | { | |
405 | struct mlx5_cache_ent *ent; | |
406 | ||
407 | ent = container_of(work, struct mlx5_cache_ent, work); | |
408 | __cache_work_func(ent); | |
409 | } | |
410 | ||
411 | static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order) | |
412 | { | |
413 | struct mlx5_mr_cache *cache = &dev->cache; | |
414 | struct mlx5_ib_mr *mr = NULL; | |
415 | struct mlx5_cache_ent *ent; | |
416 | int c; | |
417 | int i; | |
418 | ||
419 | c = order2idx(dev, order); | |
420 | if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { | |
421 | mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c); | |
422 | return NULL; | |
423 | } | |
424 | ||
425 | for (i = c; i < MAX_MR_CACHE_ENTRIES; i++) { | |
426 | ent = &cache->ent[i]; | |
427 | ||
428 | mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i); | |
429 | ||
746b5583 | 430 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
431 | if (!list_empty(&ent->head)) { |
432 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
433 | list); | |
434 | list_del(&mr->list); | |
435 | ent->cur--; | |
746b5583 | 436 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
437 | if (ent->cur < ent->limit) |
438 | queue_work(cache->wq, &ent->work); | |
439 | break; | |
440 | } | |
746b5583 | 441 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
442 | |
443 | queue_work(cache->wq, &ent->work); | |
e126ba97 EC |
444 | } |
445 | ||
446 | if (!mr) | |
447 | cache->ent[c].miss++; | |
448 | ||
449 | return mr; | |
450 | } | |
451 | ||
452 | static void free_cached_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) | |
453 | { | |
454 | struct mlx5_mr_cache *cache = &dev->cache; | |
455 | struct mlx5_cache_ent *ent; | |
456 | int shrink = 0; | |
457 | int c; | |
458 | ||
459 | c = order2idx(dev, mr->order); | |
460 | if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { | |
461 | mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c); | |
462 | return; | |
463 | } | |
464 | ent = &cache->ent[c]; | |
746b5583 | 465 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
466 | list_add_tail(&mr->list, &ent->head); |
467 | ent->cur++; | |
468 | if (ent->cur > 2 * ent->limit) | |
469 | shrink = 1; | |
746b5583 | 470 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
471 | |
472 | if (shrink) | |
473 | queue_work(cache->wq, &ent->work); | |
474 | } | |
475 | ||
476 | static void clean_keys(struct mlx5_ib_dev *dev, int c) | |
477 | { | |
e126ba97 EC |
478 | struct mlx5_mr_cache *cache = &dev->cache; |
479 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
480 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
481 | int err; |
482 | ||
3c461911 | 483 | cancel_delayed_work(&ent->dwork); |
e126ba97 | 484 | while (1) { |
746b5583 | 485 | spin_lock_irq(&ent->lock); |
e126ba97 | 486 | if (list_empty(&ent->head)) { |
746b5583 | 487 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
488 | return; |
489 | } | |
490 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
491 | list_del(&mr->list); | |
492 | ent->cur--; | |
493 | ent->size--; | |
746b5583 | 494 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 495 | err = destroy_mkey(dev, mr); |
203099fd | 496 | if (err) |
e126ba97 | 497 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 498 | else |
e126ba97 | 499 | kfree(mr); |
e126ba97 EC |
500 | } |
501 | } | |
502 | ||
503 | static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev) | |
504 | { | |
505 | struct mlx5_mr_cache *cache = &dev->cache; | |
506 | struct mlx5_cache_ent *ent; | |
507 | int i; | |
508 | ||
509 | if (!mlx5_debugfs_root) | |
510 | return 0; | |
511 | ||
9603b61d | 512 | cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root); |
e126ba97 EC |
513 | if (!cache->root) |
514 | return -ENOMEM; | |
515 | ||
516 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
517 | ent = &cache->ent[i]; | |
518 | sprintf(ent->name, "%d", ent->order); | |
519 | ent->dir = debugfs_create_dir(ent->name, cache->root); | |
520 | if (!ent->dir) | |
521 | return -ENOMEM; | |
522 | ||
523 | ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent, | |
524 | &size_fops); | |
525 | if (!ent->fsize) | |
526 | return -ENOMEM; | |
527 | ||
528 | ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent, | |
529 | &limit_fops); | |
530 | if (!ent->flimit) | |
531 | return -ENOMEM; | |
532 | ||
533 | ent->fcur = debugfs_create_u32("cur", 0400, ent->dir, | |
534 | &ent->cur); | |
535 | if (!ent->fcur) | |
536 | return -ENOMEM; | |
537 | ||
538 | ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir, | |
539 | &ent->miss); | |
540 | if (!ent->fmiss) | |
541 | return -ENOMEM; | |
542 | } | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) | |
548 | { | |
549 | if (!mlx5_debugfs_root) | |
550 | return; | |
551 | ||
552 | debugfs_remove_recursive(dev->cache.root); | |
553 | } | |
554 | ||
746b5583 EC |
555 | static void delay_time_func(unsigned long ctx) |
556 | { | |
557 | struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx; | |
558 | ||
559 | dev->fill_delay = 0; | |
560 | } | |
561 | ||
e126ba97 EC |
562 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) |
563 | { | |
564 | struct mlx5_mr_cache *cache = &dev->cache; | |
565 | struct mlx5_cache_ent *ent; | |
566 | int limit; | |
e126ba97 EC |
567 | int err; |
568 | int i; | |
569 | ||
570 | cache->wq = create_singlethread_workqueue("mkey_cache"); | |
571 | if (!cache->wq) { | |
572 | mlx5_ib_warn(dev, "failed to create work queue\n"); | |
573 | return -ENOMEM; | |
574 | } | |
575 | ||
746b5583 | 576 | setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev); |
e126ba97 EC |
577 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { |
578 | INIT_LIST_HEAD(&cache->ent[i].head); | |
579 | spin_lock_init(&cache->ent[i].lock); | |
580 | ||
581 | ent = &cache->ent[i]; | |
582 | INIT_LIST_HEAD(&ent->head); | |
583 | spin_lock_init(&ent->lock); | |
584 | ent->order = i + 2; | |
585 | ent->dev = dev; | |
586 | ||
9603b61d JM |
587 | if (dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) |
588 | limit = dev->mdev->profile->mr_cache[i].limit; | |
2d036fad | 589 | else |
e126ba97 | 590 | limit = 0; |
2d036fad | 591 | |
e126ba97 EC |
592 | INIT_WORK(&ent->work, cache_work_func); |
593 | INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); | |
594 | ent->limit = limit; | |
595 | queue_work(cache->wq, &ent->work); | |
596 | } | |
597 | ||
598 | err = mlx5_mr_cache_debugfs_init(dev); | |
599 | if (err) | |
600 | mlx5_ib_warn(dev, "cache debugfs failure\n"); | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) | |
606 | { | |
607 | int i; | |
608 | ||
609 | dev->cache.stopped = 1; | |
3c461911 | 610 | flush_workqueue(dev->cache.wq); |
e126ba97 EC |
611 | |
612 | mlx5_mr_cache_debugfs_cleanup(dev); | |
613 | ||
614 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) | |
615 | clean_keys(dev, i); | |
616 | ||
3c461911 | 617 | destroy_workqueue(dev->cache.wq); |
746b5583 | 618 | del_timer_sync(&dev->delay_timer); |
3c461911 | 619 | |
e126ba97 EC |
620 | return 0; |
621 | } | |
622 | ||
623 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) | |
624 | { | |
625 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
9603b61d | 626 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 EC |
627 | struct mlx5_create_mkey_mbox_in *in; |
628 | struct mlx5_mkey_seg *seg; | |
629 | struct mlx5_ib_mr *mr; | |
630 | int err; | |
631 | ||
632 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
633 | if (!mr) | |
634 | return ERR_PTR(-ENOMEM); | |
635 | ||
636 | in = kzalloc(sizeof(*in), GFP_KERNEL); | |
637 | if (!in) { | |
638 | err = -ENOMEM; | |
639 | goto err_free; | |
640 | } | |
641 | ||
642 | seg = &in->seg; | |
643 | seg->flags = convert_access(acc) | MLX5_ACCESS_MODE_PA; | |
644 | seg->flags_pd = cpu_to_be32(to_mpd(pd)->pdn | MLX5_MKEY_LEN64); | |
645 | seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
646 | seg->start_addr = 0; | |
647 | ||
746b5583 EC |
648 | err = mlx5_core_create_mkey(mdev, &mr->mmr, in, sizeof(*in), NULL, NULL, |
649 | NULL); | |
e126ba97 EC |
650 | if (err) |
651 | goto err_in; | |
652 | ||
653 | kfree(in); | |
654 | mr->ibmr.lkey = mr->mmr.key; | |
655 | mr->ibmr.rkey = mr->mmr.key; | |
656 | mr->umem = NULL; | |
657 | ||
658 | return &mr->ibmr; | |
659 | ||
660 | err_in: | |
661 | kfree(in); | |
662 | ||
663 | err_free: | |
664 | kfree(mr); | |
665 | ||
666 | return ERR_PTR(err); | |
667 | } | |
668 | ||
669 | static int get_octo_len(u64 addr, u64 len, int page_size) | |
670 | { | |
671 | u64 offset; | |
672 | int npages; | |
673 | ||
674 | offset = addr & (page_size - 1); | |
675 | npages = ALIGN(len + offset, page_size) >> ilog2(page_size); | |
676 | return (npages + 1) / 2; | |
677 | } | |
678 | ||
679 | static int use_umr(int order) | |
680 | { | |
cc149f75 | 681 | return order <= MLX5_MAX_UMR_SHIFT; |
e126ba97 EC |
682 | } |
683 | ||
684 | static void prep_umr_reg_wqe(struct ib_pd *pd, struct ib_send_wr *wr, | |
685 | struct ib_sge *sg, u64 dma, int n, u32 key, | |
686 | int page_shift, u64 virt_addr, u64 len, | |
687 | int access_flags) | |
688 | { | |
689 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
690 | struct ib_mr *mr = dev->umrc.mr; | |
968e78dd | 691 | struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr->wr.fast_reg; |
e126ba97 EC |
692 | |
693 | sg->addr = dma; | |
694 | sg->length = ALIGN(sizeof(u64) * n, 64); | |
695 | sg->lkey = mr->lkey; | |
696 | ||
697 | wr->next = NULL; | |
698 | wr->send_flags = 0; | |
699 | wr->sg_list = sg; | |
700 | if (n) | |
701 | wr->num_sge = 1; | |
702 | else | |
703 | wr->num_sge = 0; | |
704 | ||
705 | wr->opcode = MLX5_IB_WR_UMR; | |
968e78dd HE |
706 | |
707 | umrwr->npages = n; | |
708 | umrwr->page_shift = page_shift; | |
709 | umrwr->mkey = key; | |
710 | umrwr->target.virt_addr = virt_addr; | |
711 | umrwr->length = len; | |
712 | umrwr->access_flags = access_flags; | |
713 | umrwr->pd = pd; | |
e126ba97 EC |
714 | } |
715 | ||
716 | static void prep_umr_unreg_wqe(struct mlx5_ib_dev *dev, | |
717 | struct ib_send_wr *wr, u32 key) | |
718 | { | |
968e78dd HE |
719 | struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr->wr.fast_reg; |
720 | ||
721 | wr->send_flags = MLX5_IB_SEND_UMR_UNREG | MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
e126ba97 | 722 | wr->opcode = MLX5_IB_WR_UMR; |
968e78dd | 723 | umrwr->mkey = key; |
e126ba97 EC |
724 | } |
725 | ||
726 | void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context) | |
727 | { | |
a74d2416 | 728 | struct mlx5_ib_umr_context *context; |
e126ba97 EC |
729 | struct ib_wc wc; |
730 | int err; | |
731 | ||
732 | while (1) { | |
733 | err = ib_poll_cq(cq, 1, &wc); | |
734 | if (err < 0) { | |
735 | pr_warn("poll cq error %d\n", err); | |
736 | return; | |
737 | } | |
738 | if (err == 0) | |
739 | break; | |
740 | ||
6c9b5d9b | 741 | context = (struct mlx5_ib_umr_context *) (unsigned long) wc.wr_id; |
a74d2416 SR |
742 | context->status = wc.status; |
743 | complete(&context->done); | |
e126ba97 EC |
744 | } |
745 | ib_req_notify_cq(cq, IB_CQ_NEXT_COMP); | |
746 | } | |
747 | ||
748 | static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem, | |
749 | u64 virt_addr, u64 len, int npages, | |
750 | int page_shift, int order, int access_flags) | |
751 | { | |
752 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
203099fd | 753 | struct device *ddev = dev->ib_dev.dma_device; |
e126ba97 | 754 | struct umr_common *umrc = &dev->umrc; |
a74d2416 | 755 | struct mlx5_ib_umr_context umr_context; |
e126ba97 EC |
756 | struct ib_send_wr wr, *bad; |
757 | struct mlx5_ib_mr *mr; | |
758 | struct ib_sge sg; | |
cc149f75 | 759 | int size; |
21af2c3e | 760 | __be64 *mr_pas; |
cc149f75 | 761 | __be64 *pas; |
21af2c3e | 762 | dma_addr_t dma; |
096f7e72 | 763 | int err = 0; |
e126ba97 EC |
764 | int i; |
765 | ||
746b5583 | 766 | for (i = 0; i < 1; i++) { |
e126ba97 EC |
767 | mr = alloc_cached_mr(dev, order); |
768 | if (mr) | |
769 | break; | |
770 | ||
771 | err = add_keys(dev, order2idx(dev, order), 1); | |
746b5583 EC |
772 | if (err && err != -EAGAIN) { |
773 | mlx5_ib_warn(dev, "add_keys failed, err %d\n", err); | |
e126ba97 EC |
774 | break; |
775 | } | |
776 | } | |
777 | ||
778 | if (!mr) | |
779 | return ERR_PTR(-EAGAIN); | |
780 | ||
cc149f75 HE |
781 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes. |
782 | * To avoid copying garbage after the pas array, we allocate | |
783 | * a little more. */ | |
784 | size = ALIGN(sizeof(u64) * npages, MLX5_UMR_MTT_ALIGNMENT); | |
21af2c3e HE |
785 | mr_pas = kmalloc(size + MLX5_UMR_ALIGN - 1, GFP_KERNEL); |
786 | if (!mr_pas) { | |
203099fd | 787 | err = -ENOMEM; |
096f7e72 | 788 | goto free_mr; |
203099fd | 789 | } |
54313907 | 790 | |
cc149f75 HE |
791 | pas = PTR_ALIGN(mr_pas, MLX5_UMR_ALIGN); |
792 | mlx5_ib_populate_pas(dev, umem, page_shift, pas, MLX5_IB_MTT_PRESENT); | |
793 | /* Clear padding after the actual pages. */ | |
794 | memset(pas + npages, 0, size - npages * sizeof(u64)); | |
54313907 | 795 | |
cc149f75 | 796 | dma = dma_map_single(ddev, pas, size, DMA_TO_DEVICE); |
21af2c3e | 797 | if (dma_mapping_error(ddev, dma)) { |
203099fd | 798 | err = -ENOMEM; |
096f7e72 | 799 | goto free_pas; |
203099fd EC |
800 | } |
801 | ||
e126ba97 | 802 | memset(&wr, 0, sizeof(wr)); |
a74d2416 | 803 | wr.wr_id = (u64)(unsigned long)&umr_context; |
21af2c3e HE |
804 | prep_umr_reg_wqe(pd, &wr, &sg, dma, npages, mr->mmr.key, page_shift, |
805 | virt_addr, len, access_flags); | |
e126ba97 | 806 | |
a74d2416 | 807 | mlx5_ib_init_umr_context(&umr_context); |
e126ba97 | 808 | down(&umrc->sem); |
e126ba97 EC |
809 | err = ib_post_send(umrc->qp, &wr, &bad); |
810 | if (err) { | |
811 | mlx5_ib_warn(dev, "post send failed, err %d\n", err); | |
096f7e72 | 812 | goto unmap_dma; |
a74d2416 SR |
813 | } else { |
814 | wait_for_completion(&umr_context.done); | |
815 | if (umr_context.status != IB_WC_SUCCESS) { | |
816 | mlx5_ib_warn(dev, "reg umr failed\n"); | |
817 | err = -EFAULT; | |
818 | } | |
096f7e72 | 819 | } |
e126ba97 | 820 | |
b475598a HE |
821 | mr->mmr.iova = virt_addr; |
822 | mr->mmr.size = len; | |
823 | mr->mmr.pd = to_mpd(pd)->pdn; | |
824 | ||
b4cfe447 HE |
825 | mr->live = 1; |
826 | ||
096f7e72 HE |
827 | unmap_dma: |
828 | up(&umrc->sem); | |
21af2c3e | 829 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); |
096f7e72 HE |
830 | |
831 | free_pas: | |
21af2c3e | 832 | kfree(mr_pas); |
203099fd | 833 | |
096f7e72 HE |
834 | free_mr: |
835 | if (err) { | |
836 | free_cached_mr(dev, mr); | |
837 | return ERR_PTR(err); | |
e126ba97 EC |
838 | } |
839 | ||
840 | return mr; | |
e126ba97 EC |
841 | } |
842 | ||
832a6b06 HE |
843 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
844 | int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, int npages, | |
845 | int zap) | |
846 | { | |
847 | struct mlx5_ib_dev *dev = mr->dev; | |
848 | struct device *ddev = dev->ib_dev.dma_device; | |
849 | struct umr_common *umrc = &dev->umrc; | |
850 | struct mlx5_ib_umr_context umr_context; | |
851 | struct ib_umem *umem = mr->umem; | |
852 | int size; | |
853 | __be64 *pas; | |
854 | dma_addr_t dma; | |
855 | struct ib_send_wr wr, *bad; | |
856 | struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr.wr.fast_reg; | |
857 | struct ib_sge sg; | |
858 | int err = 0; | |
859 | const int page_index_alignment = MLX5_UMR_MTT_ALIGNMENT / sizeof(u64); | |
860 | const int page_index_mask = page_index_alignment - 1; | |
861 | size_t pages_mapped = 0; | |
862 | size_t pages_to_map = 0; | |
863 | size_t pages_iter = 0; | |
864 | int use_emergency_buf = 0; | |
865 | ||
866 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, | |
867 | * so we need to align the offset and length accordingly */ | |
868 | if (start_page_index & page_index_mask) { | |
869 | npages += start_page_index & page_index_mask; | |
870 | start_page_index &= ~page_index_mask; | |
871 | } | |
872 | ||
873 | pages_to_map = ALIGN(npages, page_index_alignment); | |
874 | ||
875 | if (start_page_index + pages_to_map > MLX5_MAX_UMR_PAGES) | |
876 | return -EINVAL; | |
877 | ||
878 | size = sizeof(u64) * pages_to_map; | |
879 | size = min_t(int, PAGE_SIZE, size); | |
880 | /* We allocate with GFP_ATOMIC to avoid recursion into page-reclaim | |
881 | * code, when we are called from an invalidation. The pas buffer must | |
882 | * be 2k-aligned for Connect-IB. */ | |
883 | pas = (__be64 *)get_zeroed_page(GFP_ATOMIC); | |
884 | if (!pas) { | |
885 | mlx5_ib_warn(dev, "unable to allocate memory during MTT update, falling back to slower chunked mechanism.\n"); | |
886 | pas = mlx5_ib_update_mtt_emergency_buffer; | |
887 | size = MLX5_UMR_MTT_MIN_CHUNK_SIZE; | |
888 | use_emergency_buf = 1; | |
889 | mutex_lock(&mlx5_ib_update_mtt_emergency_buffer_mutex); | |
890 | memset(pas, 0, size); | |
891 | } | |
892 | pages_iter = size / sizeof(u64); | |
893 | dma = dma_map_single(ddev, pas, size, DMA_TO_DEVICE); | |
894 | if (dma_mapping_error(ddev, dma)) { | |
895 | mlx5_ib_err(dev, "unable to map DMA during MTT update.\n"); | |
896 | err = -ENOMEM; | |
897 | goto free_pas; | |
898 | } | |
899 | ||
900 | for (pages_mapped = 0; | |
901 | pages_mapped < pages_to_map && !err; | |
902 | pages_mapped += pages_iter, start_page_index += pages_iter) { | |
903 | dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE); | |
904 | ||
905 | npages = min_t(size_t, | |
906 | pages_iter, | |
907 | ib_umem_num_pages(umem) - start_page_index); | |
908 | ||
909 | if (!zap) { | |
910 | __mlx5_ib_populate_pas(dev, umem, PAGE_SHIFT, | |
911 | start_page_index, npages, pas, | |
912 | MLX5_IB_MTT_PRESENT); | |
913 | /* Clear padding after the pages brought from the | |
914 | * umem. */ | |
915 | memset(pas + npages, 0, size - npages * sizeof(u64)); | |
916 | } | |
917 | ||
918 | dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE); | |
919 | ||
920 | memset(&wr, 0, sizeof(wr)); | |
921 | wr.wr_id = (u64)(unsigned long)&umr_context; | |
922 | ||
923 | sg.addr = dma; | |
924 | sg.length = ALIGN(npages * sizeof(u64), | |
925 | MLX5_UMR_MTT_ALIGNMENT); | |
926 | sg.lkey = dev->umrc.mr->lkey; | |
927 | ||
928 | wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE | | |
929 | MLX5_IB_SEND_UMR_UPDATE_MTT; | |
930 | wr.sg_list = &sg; | |
931 | wr.num_sge = 1; | |
932 | wr.opcode = MLX5_IB_WR_UMR; | |
933 | umrwr->npages = sg.length / sizeof(u64); | |
934 | umrwr->page_shift = PAGE_SHIFT; | |
935 | umrwr->mkey = mr->mmr.key; | |
936 | umrwr->target.offset = start_page_index; | |
937 | ||
938 | mlx5_ib_init_umr_context(&umr_context); | |
939 | down(&umrc->sem); | |
940 | err = ib_post_send(umrc->qp, &wr, &bad); | |
941 | if (err) { | |
942 | mlx5_ib_err(dev, "UMR post send failed, err %d\n", err); | |
943 | } else { | |
944 | wait_for_completion(&umr_context.done); | |
945 | if (umr_context.status != IB_WC_SUCCESS) { | |
946 | mlx5_ib_err(dev, "UMR completion failed, code %d\n", | |
947 | umr_context.status); | |
948 | err = -EFAULT; | |
949 | } | |
950 | } | |
951 | up(&umrc->sem); | |
952 | } | |
953 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); | |
954 | ||
955 | free_pas: | |
956 | if (!use_emergency_buf) | |
957 | free_page((unsigned long)pas); | |
958 | else | |
959 | mutex_unlock(&mlx5_ib_update_mtt_emergency_buffer_mutex); | |
960 | ||
961 | return err; | |
962 | } | |
963 | #endif | |
964 | ||
e126ba97 EC |
965 | static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, u64 virt_addr, |
966 | u64 length, struct ib_umem *umem, | |
967 | int npages, int page_shift, | |
968 | int access_flags) | |
969 | { | |
970 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
971 | struct mlx5_create_mkey_mbox_in *in; | |
972 | struct mlx5_ib_mr *mr; | |
973 | int inlen; | |
974 | int err; | |
938fe83c | 975 | bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)); |
e126ba97 EC |
976 | |
977 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
978 | if (!mr) | |
979 | return ERR_PTR(-ENOMEM); | |
980 | ||
981 | inlen = sizeof(*in) + sizeof(*in->pas) * ((npages + 1) / 2) * 2; | |
982 | in = mlx5_vzalloc(inlen); | |
983 | if (!in) { | |
984 | err = -ENOMEM; | |
985 | goto err_1; | |
986 | } | |
cc149f75 HE |
987 | mlx5_ib_populate_pas(dev, umem, page_shift, in->pas, |
988 | pg_cap ? MLX5_IB_MTT_PRESENT : 0); | |
e126ba97 | 989 | |
cc149f75 HE |
990 | /* The MLX5_MKEY_INBOX_PG_ACCESS bit allows setting the access flags |
991 | * in the page list submitted with the command. */ | |
992 | in->flags = pg_cap ? cpu_to_be32(MLX5_MKEY_INBOX_PG_ACCESS) : 0; | |
e126ba97 EC |
993 | in->seg.flags = convert_access(access_flags) | |
994 | MLX5_ACCESS_MODE_MTT; | |
995 | in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn); | |
996 | in->seg.start_addr = cpu_to_be64(virt_addr); | |
997 | in->seg.len = cpu_to_be64(length); | |
998 | in->seg.bsfs_octo_size = 0; | |
999 | in->seg.xlt_oct_size = cpu_to_be32(get_octo_len(virt_addr, length, 1 << page_shift)); | |
1000 | in->seg.log2_page_size = page_shift; | |
1001 | in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
746b5583 EC |
1002 | in->xlat_oct_act_size = cpu_to_be32(get_octo_len(virt_addr, length, |
1003 | 1 << page_shift)); | |
9603b61d | 1004 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmr, in, inlen, NULL, |
746b5583 | 1005 | NULL, NULL); |
e126ba97 EC |
1006 | if (err) { |
1007 | mlx5_ib_warn(dev, "create mkey failed\n"); | |
1008 | goto err_2; | |
1009 | } | |
1010 | mr->umem = umem; | |
7eae20db | 1011 | mr->dev = dev; |
b4cfe447 | 1012 | mr->live = 1; |
479163f4 | 1013 | kvfree(in); |
e126ba97 EC |
1014 | |
1015 | mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmr.key); | |
1016 | ||
1017 | return mr; | |
1018 | ||
1019 | err_2: | |
479163f4 | 1020 | kvfree(in); |
e126ba97 EC |
1021 | |
1022 | err_1: | |
1023 | kfree(mr); | |
1024 | ||
1025 | return ERR_PTR(err); | |
1026 | } | |
1027 | ||
1028 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
1029 | u64 virt_addr, int access_flags, | |
1030 | struct ib_udata *udata) | |
1031 | { | |
1032 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1033 | struct mlx5_ib_mr *mr = NULL; | |
1034 | struct ib_umem *umem; | |
1035 | int page_shift; | |
1036 | int npages; | |
1037 | int ncont; | |
1038 | int order; | |
1039 | int err; | |
1040 | ||
900a6d79 EC |
1041 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", |
1042 | start, virt_addr, length, access_flags); | |
e126ba97 EC |
1043 | umem = ib_umem_get(pd->uobject->context, start, length, access_flags, |
1044 | 0); | |
1045 | if (IS_ERR(umem)) { | |
900a6d79 | 1046 | mlx5_ib_dbg(dev, "umem get failed (%ld)\n", PTR_ERR(umem)); |
e126ba97 EC |
1047 | return (void *)umem; |
1048 | } | |
1049 | ||
1050 | mlx5_ib_cont_pages(umem, start, &npages, &page_shift, &ncont, &order); | |
1051 | if (!npages) { | |
1052 | mlx5_ib_warn(dev, "avoid zero region\n"); | |
1053 | err = -EINVAL; | |
1054 | goto error; | |
1055 | } | |
1056 | ||
1057 | mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", | |
1058 | npages, ncont, order, page_shift); | |
1059 | ||
1060 | if (use_umr(order)) { | |
1061 | mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift, | |
1062 | order, access_flags); | |
1063 | if (PTR_ERR(mr) == -EAGAIN) { | |
1064 | mlx5_ib_dbg(dev, "cache empty for order %d", order); | |
1065 | mr = NULL; | |
1066 | } | |
6aec21f6 HE |
1067 | } else if (access_flags & IB_ACCESS_ON_DEMAND) { |
1068 | err = -EINVAL; | |
1069 | pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB"); | |
1070 | goto error; | |
e126ba97 EC |
1071 | } |
1072 | ||
1073 | if (!mr) | |
1074 | mr = reg_create(pd, virt_addr, length, umem, ncont, page_shift, | |
1075 | access_flags); | |
1076 | ||
1077 | if (IS_ERR(mr)) { | |
1078 | err = PTR_ERR(mr); | |
1079 | goto error; | |
1080 | } | |
1081 | ||
1082 | mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmr.key); | |
1083 | ||
1084 | mr->umem = umem; | |
1085 | mr->npages = npages; | |
6aec21f6 | 1086 | atomic_add(npages, &dev->mdev->priv.reg_pages); |
e126ba97 EC |
1087 | mr->ibmr.lkey = mr->mmr.key; |
1088 | mr->ibmr.rkey = mr->mmr.key; | |
1089 | ||
b4cfe447 HE |
1090 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1091 | if (umem->odp_data) { | |
1092 | /* | |
1093 | * This barrier prevents the compiler from moving the | |
1094 | * setting of umem->odp_data->private to point to our | |
1095 | * MR, before reg_umr finished, to ensure that the MR | |
1096 | * initialization have finished before starting to | |
1097 | * handle invalidations. | |
1098 | */ | |
1099 | smp_wmb(); | |
1100 | mr->umem->odp_data->private = mr; | |
1101 | /* | |
1102 | * Make sure we will see the new | |
1103 | * umem->odp_data->private value in the invalidation | |
1104 | * routines, before we can get page faults on the | |
1105 | * MR. Page faults can happen once we put the MR in | |
1106 | * the tree, below this line. Without the barrier, | |
1107 | * there can be a fault handling and an invalidation | |
1108 | * before umem->odp_data->private == mr is visible to | |
1109 | * the invalidation handler. | |
1110 | */ | |
1111 | smp_wmb(); | |
1112 | } | |
1113 | #endif | |
1114 | ||
e126ba97 EC |
1115 | return &mr->ibmr; |
1116 | ||
1117 | error: | |
b4cfe447 HE |
1118 | /* |
1119 | * Destroy the umem *before* destroying the MR, to ensure we | |
1120 | * will not have any in-flight notifiers when destroying the | |
1121 | * MR. | |
1122 | * | |
1123 | * As the MR is completely invalid to begin with, and this | |
1124 | * error path is only taken if we can't push the mr entry into | |
1125 | * the pagefault tree, this is safe. | |
1126 | */ | |
1127 | ||
e126ba97 | 1128 | ib_umem_release(umem); |
b4cfe447 HE |
1129 | /* Kill the MR, and return an error code. */ |
1130 | clean_mr(mr); | |
e126ba97 EC |
1131 | return ERR_PTR(err); |
1132 | } | |
1133 | ||
1134 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) | |
1135 | { | |
1136 | struct umr_common *umrc = &dev->umrc; | |
a74d2416 | 1137 | struct mlx5_ib_umr_context umr_context; |
e126ba97 EC |
1138 | struct ib_send_wr wr, *bad; |
1139 | int err; | |
1140 | ||
1141 | memset(&wr, 0, sizeof(wr)); | |
a74d2416 | 1142 | wr.wr_id = (u64)(unsigned long)&umr_context; |
e126ba97 EC |
1143 | prep_umr_unreg_wqe(dev, &wr, mr->mmr.key); |
1144 | ||
a74d2416 | 1145 | mlx5_ib_init_umr_context(&umr_context); |
e126ba97 | 1146 | down(&umrc->sem); |
e126ba97 EC |
1147 | err = ib_post_send(umrc->qp, &wr, &bad); |
1148 | if (err) { | |
1149 | up(&umrc->sem); | |
1150 | mlx5_ib_dbg(dev, "err %d\n", err); | |
1151 | goto error; | |
a74d2416 SR |
1152 | } else { |
1153 | wait_for_completion(&umr_context.done); | |
1154 | up(&umrc->sem); | |
e126ba97 | 1155 | } |
a74d2416 | 1156 | if (umr_context.status != IB_WC_SUCCESS) { |
e126ba97 EC |
1157 | mlx5_ib_warn(dev, "unreg umr failed\n"); |
1158 | err = -EFAULT; | |
1159 | goto error; | |
1160 | } | |
1161 | return 0; | |
1162 | ||
1163 | error: | |
1164 | return err; | |
1165 | } | |
1166 | ||
6aec21f6 | 1167 | static int clean_mr(struct mlx5_ib_mr *mr) |
e126ba97 | 1168 | { |
6aec21f6 | 1169 | struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); |
e126ba97 EC |
1170 | int umred = mr->umred; |
1171 | int err; | |
1172 | ||
1173 | if (!umred) { | |
b4cfe447 | 1174 | err = destroy_mkey(dev, mr); |
e126ba97 EC |
1175 | if (err) { |
1176 | mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n", | |
1177 | mr->mmr.key, err); | |
1178 | return err; | |
1179 | } | |
1180 | } else { | |
1181 | err = unreg_umr(dev, mr); | |
1182 | if (err) { | |
1183 | mlx5_ib_warn(dev, "failed unregister\n"); | |
1184 | return err; | |
1185 | } | |
1186 | free_cached_mr(dev, mr); | |
1187 | } | |
1188 | ||
6aec21f6 HE |
1189 | if (!umred) |
1190 | kfree(mr); | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr) | |
1196 | { | |
1197 | struct mlx5_ib_dev *dev = to_mdev(ibmr->device); | |
1198 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1199 | int npages = mr->npages; | |
1200 | struct ib_umem *umem = mr->umem; | |
1201 | ||
1202 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
b4cfe447 HE |
1203 | if (umem && umem->odp_data) { |
1204 | /* Prevent new page faults from succeeding */ | |
1205 | mr->live = 0; | |
6aec21f6 HE |
1206 | /* Wait for all running page-fault handlers to finish. */ |
1207 | synchronize_srcu(&dev->mr_srcu); | |
b4cfe447 HE |
1208 | /* Destroy all page mappings */ |
1209 | mlx5_ib_invalidate_range(umem, ib_umem_start(umem), | |
1210 | ib_umem_end(umem)); | |
1211 | /* | |
1212 | * We kill the umem before the MR for ODP, | |
1213 | * so that there will not be any invalidations in | |
1214 | * flight, looking at the *mr struct. | |
1215 | */ | |
1216 | ib_umem_release(umem); | |
1217 | atomic_sub(npages, &dev->mdev->priv.reg_pages); | |
1218 | ||
1219 | /* Avoid double-freeing the umem. */ | |
1220 | umem = NULL; | |
1221 | } | |
6aec21f6 HE |
1222 | #endif |
1223 | ||
1224 | clean_mr(mr); | |
1225 | ||
e126ba97 EC |
1226 | if (umem) { |
1227 | ib_umem_release(umem); | |
6aec21f6 | 1228 | atomic_sub(npages, &dev->mdev->priv.reg_pages); |
e126ba97 EC |
1229 | } |
1230 | ||
e126ba97 EC |
1231 | return 0; |
1232 | } | |
1233 | ||
3121e3c4 SG |
1234 | struct ib_mr *mlx5_ib_create_mr(struct ib_pd *pd, |
1235 | struct ib_mr_init_attr *mr_init_attr) | |
1236 | { | |
1237 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1238 | struct mlx5_create_mkey_mbox_in *in; | |
1239 | struct mlx5_ib_mr *mr; | |
1240 | int access_mode, err; | |
1241 | int ndescs = roundup(mr_init_attr->max_reg_descriptors, 4); | |
1242 | ||
1243 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1244 | if (!mr) | |
1245 | return ERR_PTR(-ENOMEM); | |
1246 | ||
1247 | in = kzalloc(sizeof(*in), GFP_KERNEL); | |
1248 | if (!in) { | |
1249 | err = -ENOMEM; | |
1250 | goto err_free; | |
1251 | } | |
1252 | ||
968e78dd | 1253 | in->seg.status = MLX5_MKEY_STATUS_FREE; |
3121e3c4 SG |
1254 | in->seg.xlt_oct_size = cpu_to_be32(ndescs); |
1255 | in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
1256 | in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn); | |
1257 | access_mode = MLX5_ACCESS_MODE_MTT; | |
1258 | ||
1259 | if (mr_init_attr->flags & IB_MR_SIGNATURE_EN) { | |
1260 | u32 psv_index[2]; | |
1261 | ||
1262 | in->seg.flags_pd = cpu_to_be32(be32_to_cpu(in->seg.flags_pd) | | |
1263 | MLX5_MKEY_BSF_EN); | |
1264 | in->seg.bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); | |
1265 | mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL); | |
1266 | if (!mr->sig) { | |
1267 | err = -ENOMEM; | |
1268 | goto err_free_in; | |
1269 | } | |
1270 | ||
1271 | /* create mem & wire PSVs */ | |
9603b61d | 1272 | err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, |
3121e3c4 SG |
1273 | 2, psv_index); |
1274 | if (err) | |
1275 | goto err_free_sig; | |
1276 | ||
1277 | access_mode = MLX5_ACCESS_MODE_KLM; | |
1278 | mr->sig->psv_memory.psv_idx = psv_index[0]; | |
1279 | mr->sig->psv_wire.psv_idx = psv_index[1]; | |
d5436ba0 SG |
1280 | |
1281 | mr->sig->sig_status_checked = true; | |
1282 | mr->sig->sig_err_exists = false; | |
1283 | /* Next UMR, Arm SIGERR */ | |
1284 | ++mr->sig->sigerr_count; | |
3121e3c4 SG |
1285 | } |
1286 | ||
1287 | in->seg.flags = MLX5_PERM_UMR_EN | access_mode; | |
9603b61d | 1288 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmr, in, sizeof(*in), |
3121e3c4 SG |
1289 | NULL, NULL, NULL); |
1290 | if (err) | |
1291 | goto err_destroy_psv; | |
1292 | ||
1293 | mr->ibmr.lkey = mr->mmr.key; | |
1294 | mr->ibmr.rkey = mr->mmr.key; | |
1295 | mr->umem = NULL; | |
1296 | kfree(in); | |
1297 | ||
1298 | return &mr->ibmr; | |
1299 | ||
1300 | err_destroy_psv: | |
1301 | if (mr->sig) { | |
9603b61d | 1302 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1303 | mr->sig->psv_memory.psv_idx)) |
1304 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1305 | mr->sig->psv_memory.psv_idx); | |
9603b61d | 1306 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1307 | mr->sig->psv_wire.psv_idx)) |
1308 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1309 | mr->sig->psv_wire.psv_idx); | |
1310 | } | |
1311 | err_free_sig: | |
1312 | kfree(mr->sig); | |
1313 | err_free_in: | |
1314 | kfree(in); | |
1315 | err_free: | |
1316 | kfree(mr); | |
1317 | return ERR_PTR(err); | |
1318 | } | |
1319 | ||
1320 | int mlx5_ib_destroy_mr(struct ib_mr *ibmr) | |
1321 | { | |
1322 | struct mlx5_ib_dev *dev = to_mdev(ibmr->device); | |
1323 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1324 | int err; | |
1325 | ||
1326 | if (mr->sig) { | |
9603b61d | 1327 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1328 | mr->sig->psv_memory.psv_idx)) |
1329 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1330 | mr->sig->psv_memory.psv_idx); | |
9603b61d | 1331 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1332 | mr->sig->psv_wire.psv_idx)) |
1333 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1334 | mr->sig->psv_wire.psv_idx); | |
1335 | kfree(mr->sig); | |
1336 | } | |
1337 | ||
b4cfe447 | 1338 | err = destroy_mkey(dev, mr); |
3121e3c4 SG |
1339 | if (err) { |
1340 | mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n", | |
1341 | mr->mmr.key, err); | |
1342 | return err; | |
1343 | } | |
1344 | ||
1345 | kfree(mr); | |
1346 | ||
1347 | return err; | |
1348 | } | |
1349 | ||
e126ba97 EC |
1350 | struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd, |
1351 | int max_page_list_len) | |
1352 | { | |
1353 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1354 | struct mlx5_create_mkey_mbox_in *in; | |
1355 | struct mlx5_ib_mr *mr; | |
1356 | int err; | |
1357 | ||
1358 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1359 | if (!mr) | |
1360 | return ERR_PTR(-ENOMEM); | |
1361 | ||
1362 | in = kzalloc(sizeof(*in), GFP_KERNEL); | |
1363 | if (!in) { | |
1364 | err = -ENOMEM; | |
1365 | goto err_free; | |
1366 | } | |
1367 | ||
968e78dd | 1368 | in->seg.status = MLX5_MKEY_STATUS_FREE; |
e126ba97 EC |
1369 | in->seg.xlt_oct_size = cpu_to_be32((max_page_list_len + 1) / 2); |
1370 | in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
1371 | in->seg.flags = MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT; | |
1372 | in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn); | |
1373 | /* | |
1374 | * TBD not needed - issue 197292 */ | |
1375 | in->seg.log2_page_size = PAGE_SHIFT; | |
1376 | ||
9603b61d | 1377 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmr, in, sizeof(*in), NULL, |
746b5583 | 1378 | NULL, NULL); |
e126ba97 EC |
1379 | kfree(in); |
1380 | if (err) | |
1381 | goto err_free; | |
1382 | ||
1383 | mr->ibmr.lkey = mr->mmr.key; | |
1384 | mr->ibmr.rkey = mr->mmr.key; | |
1385 | mr->umem = NULL; | |
1386 | ||
1387 | return &mr->ibmr; | |
1388 | ||
1389 | err_free: | |
1390 | kfree(mr); | |
1391 | return ERR_PTR(err); | |
1392 | } | |
1393 | ||
1394 | struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev, | |
1395 | int page_list_len) | |
1396 | { | |
1397 | struct mlx5_ib_fast_reg_page_list *mfrpl; | |
1398 | int size = page_list_len * sizeof(u64); | |
1399 | ||
1400 | mfrpl = kmalloc(sizeof(*mfrpl), GFP_KERNEL); | |
1401 | if (!mfrpl) | |
1402 | return ERR_PTR(-ENOMEM); | |
1403 | ||
1404 | mfrpl->ibfrpl.page_list = kmalloc(size, GFP_KERNEL); | |
1405 | if (!mfrpl->ibfrpl.page_list) | |
1406 | goto err_free; | |
1407 | ||
1408 | mfrpl->mapped_page_list = dma_alloc_coherent(ibdev->dma_device, | |
1409 | size, &mfrpl->map, | |
1410 | GFP_KERNEL); | |
1411 | if (!mfrpl->mapped_page_list) | |
1412 | goto err_free; | |
1413 | ||
1414 | WARN_ON(mfrpl->map & 0x3f); | |
1415 | ||
1416 | return &mfrpl->ibfrpl; | |
1417 | ||
1418 | err_free: | |
1419 | kfree(mfrpl->ibfrpl.page_list); | |
1420 | kfree(mfrpl); | |
1421 | return ERR_PTR(-ENOMEM); | |
1422 | } | |
1423 | ||
1424 | void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list) | |
1425 | { | |
1426 | struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(page_list); | |
1427 | struct mlx5_ib_dev *dev = to_mdev(page_list->device); | |
1428 | int size = page_list->max_page_list_len * sizeof(u64); | |
1429 | ||
9603b61d | 1430 | dma_free_coherent(&dev->mdev->pdev->dev, size, mfrpl->mapped_page_list, |
e126ba97 EC |
1431 | mfrpl->map); |
1432 | kfree(mfrpl->ibfrpl.page_list); | |
1433 | kfree(mfrpl); | |
1434 | } | |
d5436ba0 SG |
1435 | |
1436 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, | |
1437 | struct ib_mr_status *mr_status) | |
1438 | { | |
1439 | struct mlx5_ib_mr *mmr = to_mmr(ibmr); | |
1440 | int ret = 0; | |
1441 | ||
1442 | if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { | |
1443 | pr_err("Invalid status check mask\n"); | |
1444 | ret = -EINVAL; | |
1445 | goto done; | |
1446 | } | |
1447 | ||
1448 | mr_status->fail_status = 0; | |
1449 | if (check_mask & IB_MR_CHECK_SIG_STATUS) { | |
1450 | if (!mmr->sig) { | |
1451 | ret = -EINVAL; | |
1452 | pr_err("signature status check requested on a non-signature enabled MR\n"); | |
1453 | goto done; | |
1454 | } | |
1455 | ||
1456 | mmr->sig->sig_status_checked = true; | |
1457 | if (!mmr->sig->sig_err_exists) | |
1458 | goto done; | |
1459 | ||
1460 | if (ibmr->lkey == mmr->sig->err_item.key) | |
1461 | memcpy(&mr_status->sig_err, &mmr->sig->err_item, | |
1462 | sizeof(mr_status->sig_err)); | |
1463 | else { | |
1464 | mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; | |
1465 | mr_status->sig_err.sig_err_offset = 0; | |
1466 | mr_status->sig_err.key = mmr->sig->err_item.key; | |
1467 | } | |
1468 | ||
1469 | mmr->sig->sig_err_exists = false; | |
1470 | mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; | |
1471 | } | |
1472 | ||
1473 | done: | |
1474 | return ret; | |
1475 | } |