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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | ||
34 | #include <linux/kref.h> | |
35 | #include <linux/random.h> | |
36 | #include <linux/debugfs.h> | |
37 | #include <linux/export.h> | |
746b5583 | 38 | #include <linux/delay.h> |
e126ba97 | 39 | #include <rdma/ib_umem.h> |
b4cfe447 | 40 | #include <rdma/ib_umem_odp.h> |
968e78dd | 41 | #include <rdma/ib_verbs.h> |
e126ba97 EC |
42 | #include "mlx5_ib.h" |
43 | ||
44 | enum { | |
746b5583 | 45 | MAX_PENDING_REG_MR = 8, |
e126ba97 EC |
46 | }; |
47 | ||
832a6b06 | 48 | #define MLX5_UMR_ALIGN 2048 |
fe45f827 | 49 | |
fc6a9f86 SM |
50 | static void |
51 | create_mkey_callback(int status, struct mlx5_async_work *context); | |
52 | ||
53 | static void | |
54 | assign_mkey_variant(struct mlx5_ib_dev *dev, struct mlx5_core_mkey *mkey, | |
55 | u32 *in) | |
56 | { | |
f743ff3b | 57 | u8 key = atomic_inc_return(&dev->mkey_var); |
fc6a9f86 | 58 | void *mkc; |
fc6a9f86 SM |
59 | |
60 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
61 | MLX5_SET(mkc, mkc, mkey_7_0, key); | |
62 | mkey->key = key; | |
63 | } | |
64 | ||
65 | static int | |
66 | mlx5_ib_create_mkey(struct mlx5_ib_dev *dev, struct mlx5_core_mkey *mkey, | |
67 | u32 *in, int inlen) | |
68 | { | |
69 | assign_mkey_variant(dev, mkey, in); | |
70 | return mlx5_core_create_mkey(dev->mdev, mkey, in, inlen); | |
71 | } | |
72 | ||
73 | static int | |
74 | mlx5_ib_create_mkey_cb(struct mlx5_ib_dev *dev, | |
75 | struct mlx5_core_mkey *mkey, | |
76 | struct mlx5_async_ctx *async_ctx, | |
77 | u32 *in, int inlen, u32 *out, int outlen, | |
78 | struct mlx5_async_work *context) | |
79 | { | |
a3cfdd39 | 80 | MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); |
fc6a9f86 | 81 | assign_mkey_variant(dev, mkey, in); |
a3cfdd39 MG |
82 | return mlx5_cmd_exec_cb(async_ctx, in, inlen, out, outlen, |
83 | create_mkey_callback, context); | |
fc6a9f86 SM |
84 | } |
85 | ||
eeea6953 LR |
86 | static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); |
87 | static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); | |
8b7ff7f3 | 88 | static int mr_cache_max_order(struct mlx5_ib_dev *dev); |
c8d75a98 MD |
89 | |
90 | static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev *dev) | |
91 | { | |
92 | return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled); | |
93 | } | |
94 | ||
b4cfe447 HE |
95 | static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
96 | { | |
806b101b | 97 | WARN_ON(xa_load(&dev->odp_mkeys, mlx5_base_mkey(mr->mmkey.key))); |
b4cfe447 | 98 | |
806b101b | 99 | return mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); |
b4cfe447 HE |
100 | } |
101 | ||
56e11d62 NO |
102 | static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length) |
103 | { | |
104 | return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >= | |
105 | length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1)); | |
106 | } | |
107 | ||
fc6a9f86 | 108 | static void create_mkey_callback(int status, struct mlx5_async_work *context) |
746b5583 | 109 | { |
e355477e JG |
110 | struct mlx5_ib_mr *mr = |
111 | container_of(context, struct mlx5_ib_mr, cb_work); | |
746b5583 | 112 | struct mlx5_ib_dev *dev = mr->dev; |
b91e1751 | 113 | struct mlx5_cache_ent *ent = mr->cache_ent; |
746b5583 EC |
114 | unsigned long flags; |
115 | ||
746b5583 EC |
116 | spin_lock_irqsave(&ent->lock, flags); |
117 | ent->pending--; | |
118 | spin_unlock_irqrestore(&ent->lock, flags); | |
119 | if (status) { | |
120 | mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status); | |
121 | kfree(mr); | |
122 | dev->fill_delay = 1; | |
123 | mod_timer(&dev->delay_timer, jiffies + HZ); | |
124 | return; | |
125 | } | |
126 | ||
aa8e08d2 | 127 | mr->mmkey.type = MLX5_MKEY_MR; |
54c62e13 SM |
128 | mr->mmkey.key |= mlx5_idx_to_mkey( |
129 | MLX5_GET(create_mkey_out, mr->out, mkey_index)); | |
746b5583 | 130 | |
b91e1751 | 131 | dev->cache.last_add = jiffies; |
746b5583 EC |
132 | |
133 | spin_lock_irqsave(&ent->lock, flags); | |
134 | list_add_tail(&mr->list, &ent->head); | |
7c8691a3 JG |
135 | ent->available_mrs++; |
136 | ent->total_mrs++; | |
ad2d3ef4 JG |
137 | /* |
138 | * Creating is always done in response to some demand, so do not call | |
139 | * queue_adjust_cache_locked(). | |
140 | */ | |
746b5583 | 141 | spin_unlock_irqrestore(&ent->lock, flags); |
8605933a | 142 | |
49780d42 AK |
143 | if (!completion_done(&ent->compl)) |
144 | complete(&ent->compl); | |
746b5583 EC |
145 | } |
146 | ||
a1d8854a | 147 | static int add_keys(struct mlx5_cache_ent *ent, unsigned int num) |
e126ba97 | 148 | { |
ec22eb53 | 149 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
e126ba97 | 150 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
151 | void *mkc; |
152 | u32 *in; | |
e126ba97 EC |
153 | int err = 0; |
154 | int i; | |
155 | ||
ec22eb53 | 156 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
157 | if (!in) |
158 | return -ENOMEM; | |
159 | ||
ec22eb53 | 160 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
e126ba97 | 161 | for (i = 0; i < num; i++) { |
746b5583 EC |
162 | if (ent->pending >= MAX_PENDING_REG_MR) { |
163 | err = -EAGAIN; | |
164 | break; | |
165 | } | |
166 | ||
e126ba97 EC |
167 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
168 | if (!mr) { | |
169 | err = -ENOMEM; | |
746b5583 | 170 | break; |
e126ba97 EC |
171 | } |
172 | mr->order = ent->order; | |
b91e1751 JG |
173 | mr->cache_ent = ent; |
174 | mr->dev = ent->dev; | |
ec22eb53 SM |
175 | |
176 | MLX5_SET(mkc, mkc, free, 1); | |
177 | MLX5_SET(mkc, mkc, umr_en, 1); | |
cdbd0d2b AL |
178 | MLX5_SET(mkc, mkc, access_mode_1_0, ent->access_mode & 0x3); |
179 | MLX5_SET(mkc, mkc, access_mode_4_2, | |
180 | (ent->access_mode >> 2) & 0x7); | |
ec22eb53 SM |
181 | |
182 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
49780d42 AK |
183 | MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt); |
184 | MLX5_SET(mkc, mkc, log_page_size, ent->page); | |
e126ba97 | 185 | |
746b5583 EC |
186 | spin_lock_irq(&ent->lock); |
187 | ent->pending++; | |
188 | spin_unlock_irq(&ent->lock); | |
b91e1751 JG |
189 | err = mlx5_ib_create_mkey_cb(ent->dev, &mr->mmkey, |
190 | &ent->dev->async_ctx, in, inlen, | |
191 | mr->out, sizeof(mr->out), | |
192 | &mr->cb_work); | |
e126ba97 | 193 | if (err) { |
d14e7110 EC |
194 | spin_lock_irq(&ent->lock); |
195 | ent->pending--; | |
196 | spin_unlock_irq(&ent->lock); | |
b91e1751 | 197 | mlx5_ib_warn(ent->dev, "create mkey failed %d\n", err); |
e126ba97 | 198 | kfree(mr); |
746b5583 | 199 | break; |
e126ba97 | 200 | } |
e126ba97 EC |
201 | } |
202 | ||
e126ba97 EC |
203 | kfree(in); |
204 | return err; | |
205 | } | |
206 | ||
a1d8854a | 207 | static void remove_cache_mr(struct mlx5_cache_ent *ent) |
e126ba97 | 208 | { |
e126ba97 | 209 | struct mlx5_ib_mr *mr; |
e126ba97 | 210 | |
a1d8854a JG |
211 | spin_lock_irq(&ent->lock); |
212 | if (list_empty(&ent->head)) { | |
746b5583 | 213 | spin_unlock_irq(&ent->lock); |
a1d8854a | 214 | return; |
65edd0e7 | 215 | } |
a1d8854a JG |
216 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); |
217 | list_del(&mr->list); | |
218 | ent->available_mrs--; | |
219 | ent->total_mrs--; | |
220 | spin_unlock_irq(&ent->lock); | |
221 | mlx5_core_destroy_mkey(ent->dev->mdev, &mr->mmkey); | |
222 | kfree(mr); | |
223 | } | |
65edd0e7 | 224 | |
a1d8854a JG |
225 | static int resize_available_mrs(struct mlx5_cache_ent *ent, unsigned int target, |
226 | bool limit_fill) | |
227 | { | |
228 | int err; | |
229 | ||
230 | lockdep_assert_held(&ent->lock); | |
231 | ||
232 | while (true) { | |
233 | if (limit_fill) | |
234 | target = ent->limit * 2; | |
235 | if (target == ent->available_mrs + ent->pending) | |
236 | return 0; | |
237 | if (target > ent->available_mrs + ent->pending) { | |
238 | u32 todo = target - (ent->available_mrs + ent->pending); | |
239 | ||
240 | spin_unlock_irq(&ent->lock); | |
241 | err = add_keys(ent, todo); | |
242 | if (err == -EAGAIN) | |
243 | usleep_range(3000, 5000); | |
244 | spin_lock_irq(&ent->lock); | |
245 | if (err) { | |
246 | if (err != -EAGAIN) | |
247 | return err; | |
248 | } else | |
249 | return 0; | |
250 | } else { | |
251 | spin_unlock_irq(&ent->lock); | |
252 | remove_cache_mr(ent); | |
253 | spin_lock_irq(&ent->lock); | |
254 | } | |
e126ba97 EC |
255 | } |
256 | } | |
257 | ||
258 | static ssize_t size_write(struct file *filp, const char __user *buf, | |
259 | size_t count, loff_t *pos) | |
260 | { | |
261 | struct mlx5_cache_ent *ent = filp->private_data; | |
a1d8854a | 262 | u32 target; |
e126ba97 | 263 | int err; |
e126ba97 | 264 | |
a1d8854a JG |
265 | err = kstrtou32_from_user(buf, count, 0, &target); |
266 | if (err) | |
267 | return err; | |
746b5583 | 268 | |
a1d8854a JG |
269 | /* |
270 | * Target is the new value of total_mrs the user requests, however we | |
271 | * cannot free MRs that are in use. Compute the target value for | |
272 | * available_mrs. | |
273 | */ | |
274 | spin_lock_irq(&ent->lock); | |
275 | if (target < ent->total_mrs - ent->available_mrs) { | |
276 | err = -EINVAL; | |
277 | goto err_unlock; | |
e126ba97 | 278 | } |
a1d8854a JG |
279 | target = target - (ent->total_mrs - ent->available_mrs); |
280 | if (target < ent->limit || target > ent->limit*2) { | |
281 | err = -EINVAL; | |
282 | goto err_unlock; | |
283 | } | |
284 | err = resize_available_mrs(ent, target, false); | |
285 | if (err) | |
286 | goto err_unlock; | |
287 | spin_unlock_irq(&ent->lock); | |
e126ba97 EC |
288 | |
289 | return count; | |
a1d8854a JG |
290 | |
291 | err_unlock: | |
292 | spin_unlock_irq(&ent->lock); | |
293 | return err; | |
e126ba97 EC |
294 | } |
295 | ||
296 | static ssize_t size_read(struct file *filp, char __user *buf, size_t count, | |
297 | loff_t *pos) | |
298 | { | |
299 | struct mlx5_cache_ent *ent = filp->private_data; | |
300 | char lbuf[20]; | |
301 | int err; | |
302 | ||
7c8691a3 | 303 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->total_mrs); |
e126ba97 EC |
304 | if (err < 0) |
305 | return err; | |
306 | ||
60e6627f | 307 | return simple_read_from_buffer(buf, count, pos, lbuf, err); |
e126ba97 EC |
308 | } |
309 | ||
310 | static const struct file_operations size_fops = { | |
311 | .owner = THIS_MODULE, | |
312 | .open = simple_open, | |
313 | .write = size_write, | |
314 | .read = size_read, | |
315 | }; | |
316 | ||
317 | static ssize_t limit_write(struct file *filp, const char __user *buf, | |
318 | size_t count, loff_t *pos) | |
319 | { | |
320 | struct mlx5_cache_ent *ent = filp->private_data; | |
e126ba97 EC |
321 | u32 var; |
322 | int err; | |
e126ba97 | 323 | |
a1d8854a JG |
324 | err = kstrtou32_from_user(buf, count, 0, &var); |
325 | if (err) | |
326 | return err; | |
e126ba97 | 327 | |
a1d8854a JG |
328 | /* |
329 | * Upon set we immediately fill the cache to high water mark implied by | |
330 | * the limit. | |
331 | */ | |
332 | spin_lock_irq(&ent->lock); | |
e126ba97 | 333 | ent->limit = var; |
a1d8854a JG |
334 | err = resize_available_mrs(ent, 0, true); |
335 | spin_unlock_irq(&ent->lock); | |
336 | if (err) | |
337 | return err; | |
e126ba97 EC |
338 | return count; |
339 | } | |
340 | ||
341 | static ssize_t limit_read(struct file *filp, char __user *buf, size_t count, | |
342 | loff_t *pos) | |
343 | { | |
344 | struct mlx5_cache_ent *ent = filp->private_data; | |
345 | char lbuf[20]; | |
346 | int err; | |
347 | ||
e126ba97 EC |
348 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit); |
349 | if (err < 0) | |
350 | return err; | |
351 | ||
60e6627f | 352 | return simple_read_from_buffer(buf, count, pos, lbuf, err); |
e126ba97 EC |
353 | } |
354 | ||
355 | static const struct file_operations limit_fops = { | |
356 | .owner = THIS_MODULE, | |
357 | .open = simple_open, | |
358 | .write = limit_write, | |
359 | .read = limit_read, | |
360 | }; | |
361 | ||
362 | static int someone_adding(struct mlx5_mr_cache *cache) | |
363 | { | |
364 | int i; | |
365 | ||
366 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
7c8691a3 | 367 | if (cache->ent[i].available_mrs < cache->ent[i].limit) |
e126ba97 EC |
368 | return 1; |
369 | } | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
ad2d3ef4 JG |
374 | /* |
375 | * Check if the bucket is outside the high/low water mark and schedule an async | |
376 | * update. The cache refill has hysteresis, once the low water mark is hit it is | |
377 | * refilled up to the high mark. | |
378 | */ | |
379 | static void queue_adjust_cache_locked(struct mlx5_cache_ent *ent) | |
380 | { | |
381 | lockdep_assert_held(&ent->lock); | |
382 | ||
383 | if (ent->available_mrs < ent->limit || | |
384 | ent->available_mrs > 2 * ent->limit) | |
385 | queue_work(ent->dev->cache.wq, &ent->work); | |
386 | } | |
387 | ||
e126ba97 EC |
388 | static void __cache_work_func(struct mlx5_cache_ent *ent) |
389 | { | |
390 | struct mlx5_ib_dev *dev = ent->dev; | |
391 | struct mlx5_mr_cache *cache = &dev->cache; | |
746b5583 | 392 | int err; |
e126ba97 EC |
393 | |
394 | if (cache->stopped) | |
395 | return; | |
396 | ||
7c8691a3 | 397 | if (ent->available_mrs < 2 * ent->limit && !dev->fill_delay) { |
b91e1751 | 398 | err = add_keys(ent, 1); |
7c8691a3 | 399 | if (ent->available_mrs < 2 * ent->limit) { |
746b5583 EC |
400 | if (err == -EAGAIN) { |
401 | mlx5_ib_dbg(dev, "returned eagain, order %d\n", | |
b91e1751 | 402 | ent->order); |
746b5583 EC |
403 | queue_delayed_work(cache->wq, &ent->dwork, |
404 | msecs_to_jiffies(3)); | |
405 | } else if (err) { | |
406 | mlx5_ib_warn(dev, "command failed order %d, err %d\n", | |
b91e1751 | 407 | ent->order, err); |
746b5583 EC |
408 | queue_delayed_work(cache->wq, &ent->dwork, |
409 | msecs_to_jiffies(1000)); | |
410 | } else { | |
411 | queue_work(cache->wq, &ent->work); | |
412 | } | |
413 | } | |
7c8691a3 | 414 | } else if (ent->available_mrs > 2 * ent->limit) { |
ab5cdc31 | 415 | /* |
a1d8854a JG |
416 | * The remove_cache_mr() logic is performed as garbage |
417 | * collection task. Such task is intended to be run when no | |
418 | * other active processes are running. | |
ab5cdc31 LR |
419 | * |
420 | * The need_resched() will return TRUE if there are user tasks | |
421 | * to be activated in near future. | |
422 | * | |
a1d8854a JG |
423 | * In such case, we don't execute remove_cache_mr() and postpone |
424 | * the garbage collection work to try to run in next cycle, in | |
425 | * order to free CPU resources to other tasks. | |
ab5cdc31 LR |
426 | */ |
427 | if (!need_resched() && !someone_adding(cache) && | |
746b5583 | 428 | time_after(jiffies, cache->last_add + 300 * HZ)) { |
a1d8854a | 429 | remove_cache_mr(ent); |
7c8691a3 | 430 | if (ent->available_mrs > ent->limit) |
e126ba97 EC |
431 | queue_work(cache->wq, &ent->work); |
432 | } else { | |
746b5583 | 433 | queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ); |
e126ba97 EC |
434 | } |
435 | } | |
436 | } | |
437 | ||
438 | static void delayed_cache_work_func(struct work_struct *work) | |
439 | { | |
440 | struct mlx5_cache_ent *ent; | |
441 | ||
442 | ent = container_of(work, struct mlx5_cache_ent, dwork.work); | |
443 | __cache_work_func(ent); | |
444 | } | |
445 | ||
446 | static void cache_work_func(struct work_struct *work) | |
447 | { | |
448 | struct mlx5_cache_ent *ent; | |
449 | ||
450 | ent = container_of(work, struct mlx5_cache_ent, work); | |
451 | __cache_work_func(ent); | |
452 | } | |
453 | ||
b91e1751 JG |
454 | /* Allocate a special entry from the cache */ |
455 | struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, | |
456 | unsigned int entry) | |
49780d42 AK |
457 | { |
458 | struct mlx5_mr_cache *cache = &dev->cache; | |
459 | struct mlx5_cache_ent *ent; | |
460 | struct mlx5_ib_mr *mr; | |
461 | int err; | |
462 | ||
b91e1751 JG |
463 | if (WARN_ON(entry <= MR_CACHE_LAST_STD_ENTRY || |
464 | entry >= ARRAY_SIZE(cache->ent))) | |
546d3009 | 465 | return ERR_PTR(-EINVAL); |
49780d42 AK |
466 | |
467 | ent = &cache->ent[entry]; | |
468 | while (1) { | |
469 | spin_lock_irq(&ent->lock); | |
470 | if (list_empty(&ent->head)) { | |
471 | spin_unlock_irq(&ent->lock); | |
472 | ||
b91e1751 | 473 | err = add_keys(ent, 1); |
81713d37 | 474 | if (err && err != -EAGAIN) |
49780d42 AK |
475 | return ERR_PTR(err); |
476 | ||
477 | wait_for_completion(&ent->compl); | |
478 | } else { | |
479 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
480 | list); | |
481 | list_del(&mr->list); | |
7c8691a3 | 482 | ent->available_mrs--; |
ad2d3ef4 | 483 | queue_adjust_cache_locked(ent); |
49780d42 | 484 | spin_unlock_irq(&ent->lock); |
49780d42 AK |
485 | return mr; |
486 | } | |
487 | } | |
488 | } | |
489 | ||
b91e1751 | 490 | static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_cache_ent *req_ent) |
e126ba97 | 491 | { |
b91e1751 | 492 | struct mlx5_ib_dev *dev = req_ent->dev; |
e126ba97 | 493 | struct mlx5_ib_mr *mr = NULL; |
b91e1751 | 494 | struct mlx5_cache_ent *ent = req_ent; |
e126ba97 | 495 | |
b91e1751 JG |
496 | /* Try larger MR pools from the cache to satisfy the allocation */ |
497 | for (; ent != &dev->cache.ent[MR_CACHE_LAST_STD_ENTRY + 1]; ent++) { | |
498 | mlx5_ib_dbg(dev, "order %u, cache index %zu\n", ent->order, | |
499 | ent - dev->cache.ent); | |
e126ba97 | 500 | |
746b5583 | 501 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
502 | if (!list_empty(&ent->head)) { |
503 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
504 | list); | |
505 | list_del(&mr->list); | |
7c8691a3 | 506 | ent->available_mrs--; |
ad2d3ef4 | 507 | queue_adjust_cache_locked(ent); |
746b5583 | 508 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
509 | break; |
510 | } | |
ad2d3ef4 | 511 | queue_adjust_cache_locked(ent); |
746b5583 | 512 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
513 | } |
514 | ||
515 | if (!mr) | |
b91e1751 | 516 | req_ent->miss++; |
e126ba97 EC |
517 | |
518 | return mr; | |
519 | } | |
520 | ||
1769c4c5 JG |
521 | static void detach_mr_from_cache(struct mlx5_ib_mr *mr) |
522 | { | |
523 | struct mlx5_cache_ent *ent = mr->cache_ent; | |
524 | ||
525 | mr->cache_ent = NULL; | |
526 | spin_lock_irq(&ent->lock); | |
527 | ent->total_mrs--; | |
528 | spin_unlock_irq(&ent->lock); | |
529 | } | |
530 | ||
49780d42 | 531 | void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
e126ba97 | 532 | { |
b91e1751 | 533 | struct mlx5_cache_ent *ent = mr->cache_ent; |
e126ba97 | 534 | |
b91e1751 | 535 | if (!ent) |
dd9a4034 VF |
536 | return; |
537 | ||
09689703 | 538 | if (mlx5_mr_cache_invalidate(mr)) { |
1769c4c5 | 539 | detach_mr_from_cache(mr); |
afd14174 | 540 | destroy_mkey(dev, mr); |
e126ba97 EC |
541 | return; |
542 | } | |
49780d42 | 543 | |
746b5583 | 544 | spin_lock_irq(&ent->lock); |
e126ba97 | 545 | list_add_tail(&mr->list, &ent->head); |
7c8691a3 | 546 | ent->available_mrs++; |
ad2d3ef4 | 547 | queue_adjust_cache_locked(ent); |
746b5583 | 548 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
549 | } |
550 | ||
551 | static void clean_keys(struct mlx5_ib_dev *dev, int c) | |
552 | { | |
e126ba97 EC |
553 | struct mlx5_mr_cache *cache = &dev->cache; |
554 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
65edd0e7 | 555 | struct mlx5_ib_mr *tmp_mr; |
e126ba97 | 556 | struct mlx5_ib_mr *mr; |
65edd0e7 | 557 | LIST_HEAD(del_list); |
e126ba97 | 558 | |
3c461911 | 559 | cancel_delayed_work(&ent->dwork); |
e126ba97 | 560 | while (1) { |
746b5583 | 561 | spin_lock_irq(&ent->lock); |
e126ba97 | 562 | if (list_empty(&ent->head)) { |
746b5583 | 563 | spin_unlock_irq(&ent->lock); |
65edd0e7 | 564 | break; |
e126ba97 EC |
565 | } |
566 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
65edd0e7 | 567 | list_move(&mr->list, &del_list); |
7c8691a3 JG |
568 | ent->available_mrs--; |
569 | ent->total_mrs--; | |
746b5583 | 570 | spin_unlock_irq(&ent->lock); |
65edd0e7 DJ |
571 | mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); |
572 | } | |
573 | ||
65edd0e7 DJ |
574 | list_for_each_entry_safe(mr, tmp_mr, &del_list, list) { |
575 | list_del(&mr->list); | |
576 | kfree(mr); | |
e126ba97 EC |
577 | } |
578 | } | |
579 | ||
12cc1a02 LR |
580 | static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) |
581 | { | |
6a4d00be | 582 | if (!mlx5_debugfs_root || dev->is_rep) |
12cc1a02 LR |
583 | return; |
584 | ||
585 | debugfs_remove_recursive(dev->cache.root); | |
586 | dev->cache.root = NULL; | |
587 | } | |
588 | ||
73eb8f03 | 589 | static void mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev) |
e126ba97 EC |
590 | { |
591 | struct mlx5_mr_cache *cache = &dev->cache; | |
592 | struct mlx5_cache_ent *ent; | |
73eb8f03 | 593 | struct dentry *dir; |
e126ba97 EC |
594 | int i; |
595 | ||
6a4d00be | 596 | if (!mlx5_debugfs_root || dev->is_rep) |
73eb8f03 | 597 | return; |
e126ba97 | 598 | |
9603b61d | 599 | cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root); |
e126ba97 EC |
600 | |
601 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
602 | ent = &cache->ent[i]; | |
603 | sprintf(ent->name, "%d", ent->order); | |
73eb8f03 GKH |
604 | dir = debugfs_create_dir(ent->name, cache->root); |
605 | debugfs_create_file("size", 0600, dir, ent, &size_fops); | |
606 | debugfs_create_file("limit", 0600, dir, ent, &limit_fops); | |
7c8691a3 | 607 | debugfs_create_u32("cur", 0400, dir, &ent->available_mrs); |
73eb8f03 | 608 | debugfs_create_u32("miss", 0600, dir, &ent->miss); |
e126ba97 | 609 | } |
e126ba97 EC |
610 | } |
611 | ||
e99e88a9 | 612 | static void delay_time_func(struct timer_list *t) |
746b5583 | 613 | { |
e99e88a9 | 614 | struct mlx5_ib_dev *dev = from_timer(dev, t, delay_timer); |
746b5583 EC |
615 | |
616 | dev->fill_delay = 0; | |
617 | } | |
618 | ||
e126ba97 EC |
619 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) |
620 | { | |
621 | struct mlx5_mr_cache *cache = &dev->cache; | |
622 | struct mlx5_cache_ent *ent; | |
e126ba97 EC |
623 | int i; |
624 | ||
6bc1a656 | 625 | mutex_init(&dev->slow_path_mutex); |
3c856c82 | 626 | cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM); |
e126ba97 EC |
627 | if (!cache->wq) { |
628 | mlx5_ib_warn(dev, "failed to create work queue\n"); | |
629 | return -ENOMEM; | |
630 | } | |
631 | ||
e355477e | 632 | mlx5_cmd_init_async_ctx(dev->mdev, &dev->async_ctx); |
e99e88a9 | 633 | timer_setup(&dev->delay_timer, delay_time_func, 0); |
e126ba97 | 634 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { |
e126ba97 EC |
635 | ent = &cache->ent[i]; |
636 | INIT_LIST_HEAD(&ent->head); | |
637 | spin_lock_init(&ent->lock); | |
638 | ent->order = i + 2; | |
639 | ent->dev = dev; | |
49780d42 | 640 | ent->limit = 0; |
e126ba97 | 641 | |
49780d42 | 642 | init_completion(&ent->compl); |
e126ba97 EC |
643 | INIT_WORK(&ent->work, cache_work_func); |
644 | INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); | |
49780d42 | 645 | |
8b7ff7f3 | 646 | if (i > MR_CACHE_LAST_STD_ENTRY) { |
81713d37 | 647 | mlx5_odp_init_mr_cache_entry(ent); |
49780d42 | 648 | continue; |
81713d37 | 649 | } |
49780d42 | 650 | |
8b7ff7f3 | 651 | if (ent->order > mr_cache_max_order(dev)) |
49780d42 AK |
652 | continue; |
653 | ||
654 | ent->page = PAGE_SHIFT; | |
655 | ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) / | |
656 | MLX5_IB_UMR_OCTOWORD; | |
657 | ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; | |
658 | if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) && | |
6a4d00be | 659 | !dev->is_rep && |
49780d42 AK |
660 | mlx5_core_is_pf(dev->mdev)) |
661 | ent->limit = dev->mdev->profile->mr_cache[i].limit; | |
662 | else | |
663 | ent->limit = 0; | |
ad2d3ef4 JG |
664 | spin_lock_irq(&ent->lock); |
665 | queue_adjust_cache_locked(ent); | |
666 | spin_unlock_irq(&ent->lock); | |
e126ba97 EC |
667 | } |
668 | ||
73eb8f03 | 669 | mlx5_mr_cache_debugfs_init(dev); |
12cc1a02 | 670 | |
e126ba97 EC |
671 | return 0; |
672 | } | |
673 | ||
674 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) | |
675 | { | |
676 | int i; | |
677 | ||
32927e28 MB |
678 | if (!dev->cache.wq) |
679 | return 0; | |
680 | ||
e126ba97 | 681 | dev->cache.stopped = 1; |
3c461911 | 682 | flush_workqueue(dev->cache.wq); |
e126ba97 EC |
683 | |
684 | mlx5_mr_cache_debugfs_cleanup(dev); | |
e355477e | 685 | mlx5_cmd_cleanup_async_ctx(&dev->async_ctx); |
e126ba97 EC |
686 | |
687 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) | |
688 | clean_keys(dev, i); | |
689 | ||
3c461911 | 690 | destroy_workqueue(dev->cache.wq); |
746b5583 | 691 | del_timer_sync(&dev->delay_timer); |
3c461911 | 692 | |
e126ba97 EC |
693 | return 0; |
694 | } | |
695 | ||
03232cc4 PP |
696 | static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr, |
697 | struct ib_pd *pd) | |
698 | { | |
d6de0bb1 MG |
699 | struct mlx5_ib_dev *dev = to_mdev(pd->device); |
700 | ||
03232cc4 PP |
701 | MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); |
702 | MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); | |
703 | MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); | |
704 | MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); | |
705 | MLX5_SET(mkc, mkc, lr, 1); | |
706 | ||
d6de0bb1 MG |
707 | if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) |
708 | MLX5_SET(mkc, mkc, relaxed_ordering_write, | |
709 | !!(acc & IB_ACCESS_RELAXED_ORDERING)); | |
710 | if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)) | |
711 | MLX5_SET(mkc, mkc, relaxed_ordering_read, | |
712 | !!(acc & IB_ACCESS_RELAXED_ORDERING)); | |
713 | ||
03232cc4 PP |
714 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); |
715 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
716 | MLX5_SET64(mkc, mkc, start_addr, start_addr); | |
717 | } | |
718 | ||
e126ba97 EC |
719 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) |
720 | { | |
721 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 722 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
e126ba97 | 723 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
724 | void *mkc; |
725 | u32 *in; | |
e126ba97 EC |
726 | int err; |
727 | ||
728 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
729 | if (!mr) | |
730 | return ERR_PTR(-ENOMEM); | |
731 | ||
ec22eb53 | 732 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
733 | if (!in) { |
734 | err = -ENOMEM; | |
735 | goto err_free; | |
736 | } | |
737 | ||
ec22eb53 SM |
738 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
739 | ||
cdbd0d2b | 740 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); |
ec22eb53 | 741 | MLX5_SET(mkc, mkc, length64, 1); |
03232cc4 | 742 | set_mkc_access_pd_addr_fields(mkc, acc, 0, pd); |
ec22eb53 | 743 | |
fc6a9f86 | 744 | err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen); |
e126ba97 EC |
745 | if (err) |
746 | goto err_in; | |
747 | ||
748 | kfree(in); | |
aa8e08d2 | 749 | mr->mmkey.type = MLX5_MKEY_MR; |
a606b0f6 MB |
750 | mr->ibmr.lkey = mr->mmkey.key; |
751 | mr->ibmr.rkey = mr->mmkey.key; | |
e126ba97 EC |
752 | mr->umem = NULL; |
753 | ||
754 | return &mr->ibmr; | |
755 | ||
756 | err_in: | |
757 | kfree(in); | |
758 | ||
759 | err_free: | |
760 | kfree(mr); | |
761 | ||
762 | return ERR_PTR(err); | |
763 | } | |
764 | ||
7b4cdaae | 765 | static int get_octo_len(u64 addr, u64 len, int page_shift) |
e126ba97 | 766 | { |
7b4cdaae | 767 | u64 page_size = 1ULL << page_shift; |
e126ba97 EC |
768 | u64 offset; |
769 | int npages; | |
770 | ||
771 | offset = addr & (page_size - 1); | |
7b4cdaae | 772 | npages = ALIGN(len + offset, page_size) >> page_shift; |
e126ba97 EC |
773 | return (npages + 1) / 2; |
774 | } | |
775 | ||
8b7ff7f3 | 776 | static int mr_cache_max_order(struct mlx5_ib_dev *dev) |
e126ba97 | 777 | { |
7d0cc6ed | 778 | if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) |
8b7ff7f3 | 779 | return MR_CACHE_LAST_STD_ENTRY + 2; |
4c25b7a3 MD |
780 | return MLX5_MAX_UMR_SHIFT; |
781 | } | |
782 | ||
c320e527 MS |
783 | static int mr_umem_get(struct mlx5_ib_dev *dev, u64 start, u64 length, |
784 | int access_flags, struct ib_umem **umem, int *npages, | |
785 | int *page_shift, int *ncont, int *order) | |
395a8e4c | 786 | { |
b4bd701a | 787 | struct ib_umem *u; |
14ab8896 | 788 | |
b4bd701a LR |
789 | *umem = NULL; |
790 | ||
261dc53f JG |
791 | if (access_flags & IB_ACCESS_ON_DEMAND) { |
792 | struct ib_umem_odp *odp; | |
793 | ||
c320e527 | 794 | odp = ib_umem_odp_get(&dev->ib_dev, start, length, access_flags, |
f25a546e | 795 | &mlx5_mn_ops); |
261dc53f JG |
796 | if (IS_ERR(odp)) { |
797 | mlx5_ib_dbg(dev, "umem get failed (%ld)\n", | |
798 | PTR_ERR(odp)); | |
799 | return PTR_ERR(odp); | |
800 | } | |
801 | ||
802 | u = &odp->umem; | |
803 | ||
804 | *page_shift = odp->page_shift; | |
805 | *ncont = ib_umem_odp_num_pages(odp); | |
806 | *npages = *ncont << (*page_shift - PAGE_SHIFT); | |
807 | if (order) | |
808 | *order = ilog2(roundup_pow_of_two(*ncont)); | |
809 | } else { | |
c320e527 | 810 | u = ib_umem_get(&dev->ib_dev, start, length, access_flags); |
261dc53f JG |
811 | if (IS_ERR(u)) { |
812 | mlx5_ib_dbg(dev, "umem get failed (%ld)\n", PTR_ERR(u)); | |
813 | return PTR_ERR(u); | |
814 | } | |
815 | ||
816 | mlx5_ib_cont_pages(u, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages, | |
817 | page_shift, ncont, order); | |
395a8e4c NO |
818 | } |
819 | ||
395a8e4c NO |
820 | if (!*npages) { |
821 | mlx5_ib_warn(dev, "avoid zero region\n"); | |
b4bd701a | 822 | ib_umem_release(u); |
14ab8896 | 823 | return -EINVAL; |
395a8e4c NO |
824 | } |
825 | ||
b4bd701a LR |
826 | *umem = u; |
827 | ||
395a8e4c NO |
828 | mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", |
829 | *npages, *ncont, *order, *page_shift); | |
830 | ||
14ab8896 | 831 | return 0; |
395a8e4c NO |
832 | } |
833 | ||
add08d76 | 834 | static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc) |
e126ba97 | 835 | { |
add08d76 CH |
836 | struct mlx5_ib_umr_context *context = |
837 | container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe); | |
e126ba97 | 838 | |
add08d76 CH |
839 | context->status = wc->status; |
840 | complete(&context->done); | |
841 | } | |
e126ba97 | 842 | |
add08d76 CH |
843 | static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) |
844 | { | |
845 | context->cqe.done = mlx5_ib_umr_done; | |
846 | context->status = -1; | |
847 | init_completion(&context->done); | |
e126ba97 EC |
848 | } |
849 | ||
d5ea2df9 BJ |
850 | static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev, |
851 | struct mlx5_umr_wr *umrwr) | |
852 | { | |
853 | struct umr_common *umrc = &dev->umrc; | |
d34ac5cd | 854 | const struct ib_send_wr *bad; |
d5ea2df9 BJ |
855 | int err; |
856 | struct mlx5_ib_umr_context umr_context; | |
857 | ||
858 | mlx5_ib_init_umr_context(&umr_context); | |
859 | umrwr->wr.wr_cqe = &umr_context.cqe; | |
860 | ||
861 | down(&umrc->sem); | |
862 | err = ib_post_send(umrc->qp, &umrwr->wr, &bad); | |
863 | if (err) { | |
864 | mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err); | |
865 | } else { | |
866 | wait_for_completion(&umr_context.done); | |
867 | if (umr_context.status != IB_WC_SUCCESS) { | |
868 | mlx5_ib_warn(dev, "reg umr failed (%u)\n", | |
869 | umr_context.status); | |
870 | err = -EFAULT; | |
871 | } | |
872 | } | |
873 | up(&umrc->sem); | |
874 | return err; | |
875 | } | |
876 | ||
b91e1751 JG |
877 | static struct mlx5_cache_ent *mr_cache_ent_from_order(struct mlx5_ib_dev *dev, |
878 | unsigned int order) | |
879 | { | |
880 | struct mlx5_mr_cache *cache = &dev->cache; | |
881 | ||
882 | if (order < cache->ent[0].order) | |
883 | return &cache->ent[0]; | |
884 | order = order - cache->ent[0].order; | |
885 | if (order > MR_CACHE_LAST_STD_ENTRY) | |
886 | return NULL; | |
887 | return &cache->ent[order]; | |
888 | } | |
889 | ||
890 | static struct mlx5_ib_mr * | |
891 | alloc_mr_from_cache(struct ib_pd *pd, struct ib_umem *umem, u64 virt_addr, | |
892 | u64 len, int npages, int page_shift, unsigned int order, | |
893 | int access_flags) | |
e126ba97 EC |
894 | { |
895 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
b91e1751 | 896 | struct mlx5_cache_ent *ent = mr_cache_ent_from_order(dev, order); |
e126ba97 | 897 | struct mlx5_ib_mr *mr; |
096f7e72 | 898 | int err = 0; |
e126ba97 EC |
899 | int i; |
900 | ||
b91e1751 JG |
901 | if (!ent) |
902 | return ERR_PTR(-E2BIG); | |
746b5583 | 903 | for (i = 0; i < 1; i++) { |
b91e1751 | 904 | mr = alloc_cached_mr(ent); |
e126ba97 EC |
905 | if (mr) |
906 | break; | |
907 | ||
b91e1751 | 908 | err = add_keys(ent, 1); |
746b5583 EC |
909 | if (err && err != -EAGAIN) { |
910 | mlx5_ib_warn(dev, "add_keys failed, err %d\n", err); | |
e126ba97 EC |
911 | break; |
912 | } | |
913 | } | |
914 | ||
915 | if (!mr) | |
916 | return ERR_PTR(-EAGAIN); | |
917 | ||
7d0cc6ed AK |
918 | mr->ibmr.pd = pd; |
919 | mr->umem = umem; | |
920 | mr->access_flags = access_flags; | |
921 | mr->desc_size = sizeof(struct mlx5_mtt); | |
a606b0f6 MB |
922 | mr->mmkey.iova = virt_addr; |
923 | mr->mmkey.size = len; | |
924 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
b475598a | 925 | |
e126ba97 | 926 | return mr; |
e126ba97 EC |
927 | } |
928 | ||
7d0cc6ed AK |
929 | #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \ |
930 | MLX5_UMR_MTT_ALIGNMENT) | |
931 | #define MLX5_SPARE_UMR_CHUNK 0x10000 | |
932 | ||
933 | int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, | |
934 | int page_shift, int flags) | |
935 | { | |
936 | struct mlx5_ib_dev *dev = mr->dev; | |
9b0c289e | 937 | struct device *ddev = dev->ib_dev.dev.parent; |
832a6b06 | 938 | int size; |
7d0cc6ed | 939 | void *xlt; |
832a6b06 | 940 | dma_addr_t dma; |
e622f2f4 | 941 | struct mlx5_umr_wr wr; |
832a6b06 HE |
942 | struct ib_sge sg; |
943 | int err = 0; | |
81713d37 AK |
944 | int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT) |
945 | ? sizeof(struct mlx5_klm) | |
946 | : sizeof(struct mlx5_mtt); | |
7d0cc6ed AK |
947 | const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size; |
948 | const int page_mask = page_align - 1; | |
832a6b06 HE |
949 | size_t pages_mapped = 0; |
950 | size_t pages_to_map = 0; | |
951 | size_t pages_iter = 0; | |
cbe4b8f0 | 952 | size_t size_to_map = 0; |
7d0cc6ed | 953 | gfp_t gfp; |
c44ef998 | 954 | bool use_emergency_page = false; |
832a6b06 | 955 | |
c8d75a98 MD |
956 | if ((flags & MLX5_IB_UPD_XLT_INDIRECT) && |
957 | !umr_can_use_indirect_mkey(dev)) | |
958 | return -EPERM; | |
832a6b06 HE |
959 | |
960 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, | |
7d0cc6ed AK |
961 | * so we need to align the offset and length accordingly |
962 | */ | |
963 | if (idx & page_mask) { | |
964 | npages += idx & page_mask; | |
965 | idx &= ~page_mask; | |
832a6b06 HE |
966 | } |
967 | ||
7d0cc6ed AK |
968 | gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL; |
969 | gfp |= __GFP_ZERO | __GFP_NOWARN; | |
832a6b06 | 970 | |
7d0cc6ed AK |
971 | pages_to_map = ALIGN(npages, page_align); |
972 | size = desc_size * pages_to_map; | |
973 | size = min_t(int, size, MLX5_MAX_UMR_CHUNK); | |
832a6b06 | 974 | |
7d0cc6ed AK |
975 | xlt = (void *)__get_free_pages(gfp, get_order(size)); |
976 | if (!xlt && size > MLX5_SPARE_UMR_CHUNK) { | |
977 | mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n", | |
978 | size, get_order(size), MLX5_SPARE_UMR_CHUNK); | |
979 | ||
980 | size = MLX5_SPARE_UMR_CHUNK; | |
981 | xlt = (void *)__get_free_pages(gfp, get_order(size)); | |
832a6b06 | 982 | } |
7d0cc6ed AK |
983 | |
984 | if (!xlt) { | |
7d0cc6ed | 985 | mlx5_ib_warn(dev, "Using XLT emergency buffer\n"); |
c44ef998 | 986 | xlt = (void *)mlx5_ib_get_xlt_emergency_page(); |
7d0cc6ed | 987 | size = PAGE_SIZE; |
7d0cc6ed | 988 | memset(xlt, 0, size); |
c44ef998 | 989 | use_emergency_page = true; |
7d0cc6ed AK |
990 | } |
991 | pages_iter = size / desc_size; | |
992 | dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE); | |
832a6b06 | 993 | if (dma_mapping_error(ddev, dma)) { |
7d0cc6ed | 994 | mlx5_ib_err(dev, "unable to map DMA during XLT update.\n"); |
832a6b06 | 995 | err = -ENOMEM; |
7d0cc6ed | 996 | goto free_xlt; |
832a6b06 HE |
997 | } |
998 | ||
cbe4b8f0 AK |
999 | if (mr->umem->is_odp) { |
1000 | if (!(flags & MLX5_IB_UPD_XLT_INDIRECT)) { | |
1001 | struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); | |
1002 | size_t max_pages = ib_umem_odp_num_pages(odp) - idx; | |
1003 | ||
1004 | pages_to_map = min_t(size_t, pages_to_map, max_pages); | |
1005 | } | |
1006 | } | |
1007 | ||
7d0cc6ed AK |
1008 | sg.addr = dma; |
1009 | sg.lkey = dev->umrc.pd->local_dma_lkey; | |
1010 | ||
1011 | memset(&wr, 0, sizeof(wr)); | |
1012 | wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT; | |
1013 | if (!(flags & MLX5_IB_UPD_XLT_ENABLE)) | |
1014 | wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
1015 | wr.wr.sg_list = &sg; | |
1016 | wr.wr.num_sge = 1; | |
1017 | wr.wr.opcode = MLX5_IB_WR_UMR; | |
1018 | ||
1019 | wr.pd = mr->ibmr.pd; | |
1020 | wr.mkey = mr->mmkey.key; | |
1021 | wr.length = mr->mmkey.size; | |
1022 | wr.virt_addr = mr->mmkey.iova; | |
1023 | wr.access_flags = mr->access_flags; | |
1024 | wr.page_shift = page_shift; | |
1025 | ||
832a6b06 HE |
1026 | for (pages_mapped = 0; |
1027 | pages_mapped < pages_to_map && !err; | |
7d0cc6ed | 1028 | pages_mapped += pages_iter, idx += pages_iter) { |
438b228e | 1029 | npages = min_t(int, pages_iter, pages_to_map - pages_mapped); |
cbe4b8f0 | 1030 | size_to_map = npages * desc_size; |
832a6b06 | 1031 | dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE); |
cbe4b8f0 AK |
1032 | if (mr->umem->is_odp) { |
1033 | mlx5_odp_populate_xlt(xlt, idx, npages, mr, flags); | |
1034 | } else { | |
1035 | __mlx5_ib_populate_pas(dev, mr->umem, page_shift, idx, | |
1036 | npages, xlt, | |
1037 | MLX5_IB_MTT_PRESENT); | |
1038 | /* Clear padding after the pages | |
1039 | * brought from the umem. | |
1040 | */ | |
1041 | memset(xlt + size_to_map, 0, size - size_to_map); | |
1042 | } | |
832a6b06 HE |
1043 | dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE); |
1044 | ||
cbe4b8f0 | 1045 | sg.length = ALIGN(size_to_map, MLX5_UMR_MTT_ALIGNMENT); |
7d0cc6ed AK |
1046 | |
1047 | if (pages_mapped + pages_iter >= pages_to_map) { | |
1048 | if (flags & MLX5_IB_UPD_XLT_ENABLE) | |
1049 | wr.wr.send_flags |= | |
1050 | MLX5_IB_SEND_UMR_ENABLE_MR | | |
1051 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS | | |
1052 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1053 | if (flags & MLX5_IB_UPD_XLT_PD || | |
1054 | flags & MLX5_IB_UPD_XLT_ACCESS) | |
1055 | wr.wr.send_flags |= | |
1056 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; | |
1057 | if (flags & MLX5_IB_UPD_XLT_ADDR) | |
1058 | wr.wr.send_flags |= | |
1059 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1060 | } | |
832a6b06 | 1061 | |
7d0cc6ed | 1062 | wr.offset = idx * desc_size; |
31616255 | 1063 | wr.xlt_size = sg.length; |
832a6b06 | 1064 | |
d5ea2df9 | 1065 | err = mlx5_ib_post_send_wait(dev, &wr); |
832a6b06 HE |
1066 | } |
1067 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); | |
1068 | ||
7d0cc6ed | 1069 | free_xlt: |
c44ef998 IL |
1070 | if (use_emergency_page) |
1071 | mlx5_ib_put_xlt_emergency_page(); | |
832a6b06 | 1072 | else |
7d0cc6ed | 1073 | free_pages((unsigned long)xlt, get_order(size)); |
832a6b06 HE |
1074 | |
1075 | return err; | |
1076 | } | |
832a6b06 | 1077 | |
395a8e4c NO |
1078 | /* |
1079 | * If ibmr is NULL it will be allocated by reg_create. | |
1080 | * Else, the given ibmr will be used. | |
1081 | */ | |
1082 | static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd, | |
1083 | u64 virt_addr, u64 length, | |
1084 | struct ib_umem *umem, int npages, | |
ff740aef IL |
1085 | int page_shift, int access_flags, |
1086 | bool populate) | |
e126ba97 EC |
1087 | { |
1088 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 1089 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
1090 | __be64 *pas; |
1091 | void *mkc; | |
e126ba97 | 1092 | int inlen; |
ec22eb53 | 1093 | u32 *in; |
e126ba97 | 1094 | int err; |
938fe83c | 1095 | bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)); |
e126ba97 | 1096 | |
395a8e4c | 1097 | mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL); |
e126ba97 EC |
1098 | if (!mr) |
1099 | return ERR_PTR(-ENOMEM); | |
1100 | ||
ff740aef IL |
1101 | mr->ibmr.pd = pd; |
1102 | mr->access_flags = access_flags; | |
1103 | ||
1104 | inlen = MLX5_ST_SZ_BYTES(create_mkey_in); | |
1105 | if (populate) | |
1106 | inlen += sizeof(*pas) * roundup(npages, 2); | |
1b9a07ee | 1107 | in = kvzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
1108 | if (!in) { |
1109 | err = -ENOMEM; | |
1110 | goto err_1; | |
1111 | } | |
ec22eb53 | 1112 | pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); |
ff740aef | 1113 | if (populate && !(access_flags & IB_ACCESS_ON_DEMAND)) |
c438fde1 AK |
1114 | mlx5_ib_populate_pas(dev, umem, page_shift, pas, |
1115 | pg_cap ? MLX5_IB_MTT_PRESENT : 0); | |
e126ba97 | 1116 | |
ec22eb53 | 1117 | /* The pg_access bit allows setting the access flags |
cc149f75 | 1118 | * in the page list submitted with the command. */ |
ec22eb53 SM |
1119 | MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap)); |
1120 | ||
1121 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
ff740aef | 1122 | MLX5_SET(mkc, mkc, free, !populate); |
cdbd0d2b | 1123 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); |
d6de0bb1 MG |
1124 | if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) |
1125 | MLX5_SET(mkc, mkc, relaxed_ordering_write, | |
1126 | !!(access_flags & IB_ACCESS_RELAXED_ORDERING)); | |
1127 | if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)) | |
1128 | MLX5_SET(mkc, mkc, relaxed_ordering_read, | |
1129 | !!(access_flags & IB_ACCESS_RELAXED_ORDERING)); | |
ec22eb53 SM |
1130 | MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); |
1131 | MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); | |
1132 | MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); | |
1133 | MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); | |
1134 | MLX5_SET(mkc, mkc, lr, 1); | |
8b7ff7f3 | 1135 | MLX5_SET(mkc, mkc, umr_en, 1); |
ec22eb53 SM |
1136 | |
1137 | MLX5_SET64(mkc, mkc, start_addr, virt_addr); | |
1138 | MLX5_SET64(mkc, mkc, len, length); | |
1139 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1140 | MLX5_SET(mkc, mkc, bsf_octword_size, 0); | |
1141 | MLX5_SET(mkc, mkc, translations_octword_size, | |
7b4cdaae | 1142 | get_octo_len(virt_addr, length, page_shift)); |
ec22eb53 SM |
1143 | MLX5_SET(mkc, mkc, log_page_size, page_shift); |
1144 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
ff740aef IL |
1145 | if (populate) { |
1146 | MLX5_SET(create_mkey_in, in, translations_octword_actual_size, | |
7b4cdaae | 1147 | get_octo_len(virt_addr, length, page_shift)); |
ff740aef | 1148 | } |
ec22eb53 | 1149 | |
fc6a9f86 | 1150 | err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen); |
e126ba97 EC |
1151 | if (err) { |
1152 | mlx5_ib_warn(dev, "create mkey failed\n"); | |
1153 | goto err_2; | |
1154 | } | |
aa8e08d2 | 1155 | mr->mmkey.type = MLX5_MKEY_MR; |
49780d42 | 1156 | mr->desc_size = sizeof(struct mlx5_mtt); |
7eae20db | 1157 | mr->dev = dev; |
479163f4 | 1158 | kvfree(in); |
e126ba97 | 1159 | |
a606b0f6 | 1160 | mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1161 | |
1162 | return mr; | |
1163 | ||
1164 | err_2: | |
479163f4 | 1165 | kvfree(in); |
e126ba97 EC |
1166 | |
1167 | err_1: | |
395a8e4c NO |
1168 | if (!ibmr) |
1169 | kfree(mr); | |
e126ba97 EC |
1170 | |
1171 | return ERR_PTR(err); | |
1172 | } | |
1173 | ||
ac2f7e62 | 1174 | static void set_mr_fields(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr, |
395a8e4c NO |
1175 | int npages, u64 length, int access_flags) |
1176 | { | |
1177 | mr->npages = npages; | |
1178 | atomic_add(npages, &dev->mdev->priv.reg_pages); | |
a606b0f6 MB |
1179 | mr->ibmr.lkey = mr->mmkey.key; |
1180 | mr->ibmr.rkey = mr->mmkey.key; | |
395a8e4c | 1181 | mr->ibmr.length = length; |
56e11d62 | 1182 | mr->access_flags = access_flags; |
395a8e4c NO |
1183 | } |
1184 | ||
3b113a1e AL |
1185 | static struct ib_mr *mlx5_ib_get_dm_mr(struct ib_pd *pd, u64 start_addr, |
1186 | u64 length, int acc, int mode) | |
6c29f57e AL |
1187 | { |
1188 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1189 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); | |
6c29f57e AL |
1190 | struct mlx5_ib_mr *mr; |
1191 | void *mkc; | |
1192 | u32 *in; | |
1193 | int err; | |
1194 | ||
1195 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1196 | if (!mr) | |
1197 | return ERR_PTR(-ENOMEM); | |
1198 | ||
1199 | in = kzalloc(inlen, GFP_KERNEL); | |
1200 | if (!in) { | |
1201 | err = -ENOMEM; | |
1202 | goto err_free; | |
1203 | } | |
1204 | ||
1205 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
1206 | ||
3b113a1e AL |
1207 | MLX5_SET(mkc, mkc, access_mode_1_0, mode & 0x3); |
1208 | MLX5_SET(mkc, mkc, access_mode_4_2, (mode >> 2) & 0x7); | |
6c29f57e | 1209 | MLX5_SET64(mkc, mkc, len, length); |
03232cc4 | 1210 | set_mkc_access_pd_addr_fields(mkc, acc, start_addr, pd); |
6c29f57e | 1211 | |
fc6a9f86 | 1212 | err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen); |
6c29f57e AL |
1213 | if (err) |
1214 | goto err_in; | |
1215 | ||
1216 | kfree(in); | |
1217 | ||
1218 | mr->umem = NULL; | |
ac2f7e62 | 1219 | set_mr_fields(dev, mr, 0, length, acc); |
6c29f57e AL |
1220 | |
1221 | return &mr->ibmr; | |
1222 | ||
1223 | err_in: | |
1224 | kfree(in); | |
1225 | ||
1226 | err_free: | |
1227 | kfree(mr); | |
1228 | ||
1229 | return ERR_PTR(err); | |
1230 | } | |
1231 | ||
813e90b1 MS |
1232 | int mlx5_ib_advise_mr(struct ib_pd *pd, |
1233 | enum ib_uverbs_advise_mr_advice advice, | |
1234 | u32 flags, | |
1235 | struct ib_sge *sg_list, | |
1236 | u32 num_sge, | |
1237 | struct uverbs_attr_bundle *attrs) | |
1238 | { | |
1239 | if (advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH && | |
1240 | advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE) | |
1241 | return -EOPNOTSUPP; | |
1242 | ||
1243 | return mlx5_ib_advise_mr_prefetch(pd, advice, flags, | |
1244 | sg_list, num_sge); | |
1245 | } | |
1246 | ||
6c29f57e AL |
1247 | struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, |
1248 | struct ib_dm_mr_attr *attr, | |
1249 | struct uverbs_attr_bundle *attrs) | |
1250 | { | |
1251 | struct mlx5_ib_dm *mdm = to_mdm(dm); | |
3b113a1e AL |
1252 | struct mlx5_core_dev *dev = to_mdev(dm->device)->mdev; |
1253 | u64 start_addr = mdm->dev_addr + attr->offset; | |
1254 | int mode; | |
1255 | ||
1256 | switch (mdm->type) { | |
1257 | case MLX5_IB_UAPI_DM_TYPE_MEMIC: | |
1258 | if (attr->access_flags & ~MLX5_IB_DM_MEMIC_ALLOWED_ACCESS) | |
1259 | return ERR_PTR(-EINVAL); | |
1260 | ||
1261 | mode = MLX5_MKC_ACCESS_MODE_MEMIC; | |
1262 | start_addr -= pci_resource_start(dev->pdev, 0); | |
1263 | break; | |
25c13324 AL |
1264 | case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: |
1265 | case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: | |
1266 | if (attr->access_flags & ~MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS) | |
1267 | return ERR_PTR(-EINVAL); | |
1268 | ||
1269 | mode = MLX5_MKC_ACCESS_MODE_SW_ICM; | |
1270 | break; | |
3b113a1e | 1271 | default: |
6c29f57e | 1272 | return ERR_PTR(-EINVAL); |
3b113a1e | 1273 | } |
6c29f57e | 1274 | |
3b113a1e AL |
1275 | return mlx5_ib_get_dm_mr(pd, start_addr, attr->length, |
1276 | attr->access_flags, mode); | |
6c29f57e AL |
1277 | } |
1278 | ||
e126ba97 EC |
1279 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, |
1280 | u64 virt_addr, int access_flags, | |
1281 | struct ib_udata *udata) | |
1282 | { | |
1283 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1284 | struct mlx5_ib_mr *mr = NULL; | |
e5366d30 | 1285 | bool use_umr; |
e126ba97 EC |
1286 | struct ib_umem *umem; |
1287 | int page_shift; | |
1288 | int npages; | |
1289 | int ncont; | |
1290 | int order; | |
1291 | int err; | |
1292 | ||
1b19b951 | 1293 | if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM)) |
ea30f013 | 1294 | return ERR_PTR(-EOPNOTSUPP); |
1b19b951 | 1295 | |
900a6d79 EC |
1296 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", |
1297 | start, virt_addr, length, access_flags); | |
81713d37 | 1298 | |
13859d5d LR |
1299 | if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && !start && |
1300 | length == U64_MAX) { | |
8ffc3248 JG |
1301 | if (virt_addr != start) |
1302 | return ERR_PTR(-EINVAL); | |
81713d37 AK |
1303 | if (!(access_flags & IB_ACCESS_ON_DEMAND) || |
1304 | !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) | |
1305 | return ERR_PTR(-EINVAL); | |
1306 | ||
b0ea0fa5 | 1307 | mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), udata, access_flags); |
4289861d LR |
1308 | if (IS_ERR(mr)) |
1309 | return ERR_CAST(mr); | |
81713d37 AK |
1310 | return &mr->ibmr; |
1311 | } | |
81713d37 | 1312 | |
c320e527 | 1313 | err = mr_umem_get(dev, start, length, access_flags, &umem, |
b0ea0fa5 | 1314 | &npages, &page_shift, &ncont, &order); |
e126ba97 | 1315 | |
ff740aef | 1316 | if (err < 0) |
14ab8896 | 1317 | return ERR_PTR(err); |
e126ba97 | 1318 | |
d6de0bb1 | 1319 | use_umr = mlx5_ib_can_use_umr(dev, true, access_flags); |
e5366d30 GL |
1320 | |
1321 | if (order <= mr_cache_max_order(dev) && use_umr) { | |
ff740aef IL |
1322 | mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont, |
1323 | page_shift, order, access_flags); | |
e126ba97 | 1324 | if (PTR_ERR(mr) == -EAGAIN) { |
d23a8baf | 1325 | mlx5_ib_dbg(dev, "cache empty for order %d\n", order); |
e126ba97 EC |
1326 | mr = NULL; |
1327 | } | |
ff740aef IL |
1328 | } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) { |
1329 | if (access_flags & IB_ACCESS_ON_DEMAND) { | |
1330 | err = -EINVAL; | |
d23a8baf | 1331 | pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n"); |
ff740aef IL |
1332 | goto error; |
1333 | } | |
e5366d30 | 1334 | use_umr = false; |
e126ba97 EC |
1335 | } |
1336 | ||
6bc1a656 ML |
1337 | if (!mr) { |
1338 | mutex_lock(&dev->slow_path_mutex); | |
395a8e4c | 1339 | mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, |
e5366d30 | 1340 | page_shift, access_flags, !use_umr); |
6bc1a656 ML |
1341 | mutex_unlock(&dev->slow_path_mutex); |
1342 | } | |
e126ba97 EC |
1343 | |
1344 | if (IS_ERR(mr)) { | |
1345 | err = PTR_ERR(mr); | |
1346 | goto error; | |
1347 | } | |
1348 | ||
a606b0f6 | 1349 | mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1350 | |
1351 | mr->umem = umem; | |
ac2f7e62 | 1352 | set_mr_fields(dev, mr, npages, length, access_flags); |
e126ba97 | 1353 | |
e5366d30 | 1354 | if (use_umr) { |
ff740aef IL |
1355 | int update_xlt_flags = MLX5_IB_UPD_XLT_ENABLE; |
1356 | ||
1357 | if (access_flags & IB_ACCESS_ON_DEMAND) | |
1358 | update_xlt_flags |= MLX5_IB_UPD_XLT_ZAP; | |
e126ba97 | 1359 | |
ff740aef IL |
1360 | err = mlx5_ib_update_xlt(mr, 0, ncont, page_shift, |
1361 | update_xlt_flags); | |
fbcd4983 | 1362 | |
ff740aef | 1363 | if (err) { |
fbcd4983 | 1364 | dereg_mr(dev, mr); |
ff740aef IL |
1365 | return ERR_PTR(err); |
1366 | } | |
1367 | } | |
1368 | ||
aa603815 JG |
1369 | if (is_odp_mr(mr)) { |
1370 | to_ib_umem_odp(mr->umem)->private = mr; | |
5256edcb | 1371 | atomic_set(&mr->num_deferred_work, 0); |
806b101b JG |
1372 | err = xa_err(xa_store(&dev->odp_mkeys, |
1373 | mlx5_base_mkey(mr->mmkey.key), &mr->mmkey, | |
1374 | GFP_KERNEL)); | |
1375 | if (err) { | |
1376 | dereg_mr(dev, mr); | |
1377 | return ERR_PTR(err); | |
1378 | } | |
a6bc3875 | 1379 | } |
13859d5d | 1380 | |
ff740aef | 1381 | return &mr->ibmr; |
e126ba97 EC |
1382 | error: |
1383 | ib_umem_release(umem); | |
1384 | return ERR_PTR(err); | |
1385 | } | |
1386 | ||
09689703 JG |
1387 | /** |
1388 | * mlx5_mr_cache_invalidate - Fence all DMA on the MR | |
1389 | * @mr: The MR to fence | |
1390 | * | |
1391 | * Upon return the NIC will not be doing any DMA to the pages under the MR, | |
1392 | * and any DMA inprogress will be completed. Failure of this function | |
1393 | * indicates the HW has failed catastrophically. | |
1394 | */ | |
1395 | int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr) | |
e126ba97 | 1396 | { |
0025b0bd | 1397 | struct mlx5_umr_wr umrwr = {}; |
e126ba97 | 1398 | |
09689703 | 1399 | if (mr->dev->mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) |
89ea94a7 MG |
1400 | return 0; |
1401 | ||
9ec4483a YH |
1402 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR | |
1403 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; | |
7d0cc6ed | 1404 | umrwr.wr.opcode = MLX5_IB_WR_UMR; |
09689703 | 1405 | umrwr.pd = mr->dev->umrc.pd; |
7d0cc6ed | 1406 | umrwr.mkey = mr->mmkey.key; |
6a053953 | 1407 | umrwr.ignore_free_state = 1; |
e126ba97 | 1408 | |
09689703 | 1409 | return mlx5_ib_post_send_wait(mr->dev, &umrwr); |
e126ba97 EC |
1410 | } |
1411 | ||
7d0cc6ed | 1412 | static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, |
56e11d62 NO |
1413 | int access_flags, int flags) |
1414 | { | |
1415 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
56e11d62 | 1416 | struct mlx5_umr_wr umrwr = {}; |
56e11d62 NO |
1417 | int err; |
1418 | ||
56e11d62 NO |
1419 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE; |
1420 | ||
7d0cc6ed AK |
1421 | umrwr.wr.opcode = MLX5_IB_WR_UMR; |
1422 | umrwr.mkey = mr->mmkey.key; | |
56e11d62 | 1423 | |
31616255 | 1424 | if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) { |
56e11d62 | 1425 | umrwr.pd = pd; |
56e11d62 | 1426 | umrwr.access_flags = access_flags; |
31616255 | 1427 | umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; |
56e11d62 NO |
1428 | } |
1429 | ||
d5ea2df9 | 1430 | err = mlx5_ib_post_send_wait(dev, &umrwr); |
56e11d62 | 1431 | |
56e11d62 NO |
1432 | return err; |
1433 | } | |
1434 | ||
1435 | int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, | |
1436 | u64 length, u64 virt_addr, int new_access_flags, | |
1437 | struct ib_pd *new_pd, struct ib_udata *udata) | |
1438 | { | |
1439 | struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); | |
1440 | struct mlx5_ib_mr *mr = to_mmr(ib_mr); | |
1441 | struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd; | |
1442 | int access_flags = flags & IB_MR_REREG_ACCESS ? | |
1443 | new_access_flags : | |
1444 | mr->access_flags; | |
56e11d62 | 1445 | int page_shift = 0; |
7d0cc6ed | 1446 | int upd_flags = 0; |
56e11d62 NO |
1447 | int npages = 0; |
1448 | int ncont = 0; | |
1449 | int order = 0; | |
b4bd701a | 1450 | u64 addr, len; |
56e11d62 NO |
1451 | int err; |
1452 | ||
1453 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", | |
1454 | start, virt_addr, length, access_flags); | |
1455 | ||
7d0cc6ed AK |
1456 | atomic_sub(mr->npages, &dev->mdev->priv.reg_pages); |
1457 | ||
b4bd701a LR |
1458 | if (!mr->umem) |
1459 | return -EINVAL; | |
1460 | ||
880505cf JG |
1461 | if (is_odp_mr(mr)) |
1462 | return -EOPNOTSUPP; | |
1463 | ||
b4bd701a LR |
1464 | if (flags & IB_MR_REREG_TRANS) { |
1465 | addr = virt_addr; | |
1466 | len = length; | |
1467 | } else { | |
1468 | addr = mr->umem->address; | |
1469 | len = mr->umem->length; | |
1470 | } | |
1471 | ||
56e11d62 NO |
1472 | if (flags != IB_MR_REREG_PD) { |
1473 | /* | |
1474 | * Replace umem. This needs to be done whether or not UMR is | |
1475 | * used. | |
1476 | */ | |
1477 | flags |= IB_MR_REREG_TRANS; | |
1478 | ib_umem_release(mr->umem); | |
b4bd701a | 1479 | mr->umem = NULL; |
c320e527 MS |
1480 | err = mr_umem_get(dev, addr, len, access_flags, &mr->umem, |
1481 | &npages, &page_shift, &ncont, &order); | |
4638a3b2 LR |
1482 | if (err) |
1483 | goto err; | |
56e11d62 NO |
1484 | } |
1485 | ||
d6de0bb1 | 1486 | if (!mlx5_ib_can_use_umr(dev, true, access_flags) || |
25a45172 | 1487 | (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len))) { |
56e11d62 NO |
1488 | /* |
1489 | * UMR can't be used - MKey needs to be replaced. | |
1490 | */ | |
b91e1751 | 1491 | if (mr->cache_ent) |
1769c4c5 JG |
1492 | detach_mr_from_cache(mr); |
1493 | err = destroy_mkey(dev, mr); | |
56e11d62 | 1494 | if (err) |
4638a3b2 | 1495 | goto err; |
56e11d62 NO |
1496 | |
1497 | mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont, | |
ff740aef | 1498 | page_shift, access_flags, true); |
56e11d62 | 1499 | |
4638a3b2 LR |
1500 | if (IS_ERR(mr)) { |
1501 | err = PTR_ERR(mr); | |
1502 | mr = to_mmr(ib_mr); | |
1503 | goto err; | |
1504 | } | |
56e11d62 NO |
1505 | } else { |
1506 | /* | |
1507 | * Send a UMR WQE | |
1508 | */ | |
7d0cc6ed AK |
1509 | mr->ibmr.pd = pd; |
1510 | mr->access_flags = access_flags; | |
1511 | mr->mmkey.iova = addr; | |
1512 | mr->mmkey.size = len; | |
1513 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
1514 | ||
1515 | if (flags & IB_MR_REREG_TRANS) { | |
1516 | upd_flags = MLX5_IB_UPD_XLT_ADDR; | |
1517 | if (flags & IB_MR_REREG_PD) | |
1518 | upd_flags |= MLX5_IB_UPD_XLT_PD; | |
1519 | if (flags & IB_MR_REREG_ACCESS) | |
1520 | upd_flags |= MLX5_IB_UPD_XLT_ACCESS; | |
1521 | err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, | |
1522 | upd_flags); | |
1523 | } else { | |
1524 | err = rereg_umr(pd, mr, access_flags, flags); | |
1525 | } | |
1526 | ||
4638a3b2 LR |
1527 | if (err) |
1528 | goto err; | |
56e11d62 NO |
1529 | } |
1530 | ||
ac2f7e62 | 1531 | set_mr_fields(dev, mr, npages, len, access_flags); |
56e11d62 | 1532 | |
56e11d62 | 1533 | return 0; |
4638a3b2 LR |
1534 | |
1535 | err: | |
836a0fbb LR |
1536 | ib_umem_release(mr->umem); |
1537 | mr->umem = NULL; | |
1538 | ||
4638a3b2 LR |
1539 | clean_mr(dev, mr); |
1540 | return err; | |
56e11d62 NO |
1541 | } |
1542 | ||
8a187ee5 SG |
1543 | static int |
1544 | mlx5_alloc_priv_descs(struct ib_device *device, | |
1545 | struct mlx5_ib_mr *mr, | |
1546 | int ndescs, | |
1547 | int desc_size) | |
1548 | { | |
1549 | int size = ndescs * desc_size; | |
1550 | int add_size; | |
1551 | int ret; | |
1552 | ||
1553 | add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0); | |
1554 | ||
1555 | mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL); | |
1556 | if (!mr->descs_alloc) | |
1557 | return -ENOMEM; | |
1558 | ||
1559 | mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN); | |
1560 | ||
9b0c289e | 1561 | mr->desc_map = dma_map_single(device->dev.parent, mr->descs, |
8a187ee5 | 1562 | size, DMA_TO_DEVICE); |
9b0c289e | 1563 | if (dma_mapping_error(device->dev.parent, mr->desc_map)) { |
8a187ee5 SG |
1564 | ret = -ENOMEM; |
1565 | goto err; | |
1566 | } | |
1567 | ||
1568 | return 0; | |
1569 | err: | |
1570 | kfree(mr->descs_alloc); | |
1571 | ||
1572 | return ret; | |
1573 | } | |
1574 | ||
1575 | static void | |
1576 | mlx5_free_priv_descs(struct mlx5_ib_mr *mr) | |
1577 | { | |
1578 | if (mr->descs) { | |
1579 | struct ib_device *device = mr->ibmr.device; | |
1580 | int size = mr->max_descs * mr->desc_size; | |
1581 | ||
9b0c289e | 1582 | dma_unmap_single(device->dev.parent, mr->desc_map, |
8a187ee5 SG |
1583 | size, DMA_TO_DEVICE); |
1584 | kfree(mr->descs_alloc); | |
1585 | mr->descs = NULL; | |
1586 | } | |
1587 | } | |
1588 | ||
eeea6953 | 1589 | static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
e126ba97 | 1590 | { |
8b91ffc1 SG |
1591 | if (mr->sig) { |
1592 | if (mlx5_core_destroy_psv(dev->mdev, | |
1593 | mr->sig->psv_memory.psv_idx)) | |
1594 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1595 | mr->sig->psv_memory.psv_idx); | |
1596 | if (mlx5_core_destroy_psv(dev->mdev, | |
1597 | mr->sig->psv_wire.psv_idx)) | |
1598 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1599 | mr->sig->psv_wire.psv_idx); | |
50211ec9 | 1600 | xa_erase(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key)); |
8b91ffc1 SG |
1601 | kfree(mr->sig); |
1602 | mr->sig = NULL; | |
1603 | } | |
1604 | ||
b91e1751 | 1605 | if (!mr->cache_ent) { |
eeea6953 | 1606 | destroy_mkey(dev, mr); |
b9332dad YH |
1607 | mlx5_free_priv_descs(mr); |
1608 | } | |
6aec21f6 HE |
1609 | } |
1610 | ||
eeea6953 | 1611 | static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
6aec21f6 | 1612 | { |
6aec21f6 HE |
1613 | int npages = mr->npages; |
1614 | struct ib_umem *umem = mr->umem; | |
1615 | ||
09689703 JG |
1616 | /* Stop all DMA */ |
1617 | if (is_odp_mr(mr)) | |
1618 | mlx5_ib_fence_odp_mr(mr); | |
1619 | else | |
1620 | clean_mr(dev, mr); | |
8b4d5bc5 | 1621 | |
b91e1751 | 1622 | if (mr->cache_ent) |
09689703 JG |
1623 | mlx5_mr_cache_free(dev, mr); |
1624 | else | |
1625 | kfree(mr); | |
6aec21f6 | 1626 | |
836a0fbb | 1627 | ib_umem_release(umem); |
09689703 | 1628 | atomic_sub(npages, &dev->mdev->priv.reg_pages); |
836a0fbb | 1629 | |
e126ba97 EC |
1630 | } |
1631 | ||
c4367a26 | 1632 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata) |
fbcd4983 | 1633 | { |
6c984472 MG |
1634 | struct mlx5_ib_mr *mmr = to_mmr(ibmr); |
1635 | ||
de0ae958 IR |
1636 | if (ibmr->type == IB_MR_TYPE_INTEGRITY) { |
1637 | dereg_mr(to_mdev(mmr->mtt_mr->ibmr.device), mmr->mtt_mr); | |
1638 | dereg_mr(to_mdev(mmr->klm_mr->ibmr.device), mmr->klm_mr); | |
1639 | } | |
6c984472 | 1640 | |
5256edcb JG |
1641 | if (is_odp_mr(mmr) && to_ib_umem_odp(mmr->umem)->is_implicit_odp) { |
1642 | mlx5_ib_free_implicit_mr(mmr); | |
1643 | return 0; | |
1644 | } | |
1645 | ||
6c984472 MG |
1646 | dereg_mr(to_mdev(ibmr->device), mmr); |
1647 | ||
eeea6953 | 1648 | return 0; |
fbcd4983 IL |
1649 | } |
1650 | ||
7796d2a3 MG |
1651 | static void mlx5_set_umr_free_mkey(struct ib_pd *pd, u32 *in, int ndescs, |
1652 | int access_mode, int page_shift) | |
1653 | { | |
1654 | void *mkc; | |
1655 | ||
1656 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
1657 | ||
1658 | MLX5_SET(mkc, mkc, free, 1); | |
1659 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1660 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1661 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1662 | MLX5_SET(mkc, mkc, access_mode_1_0, access_mode & 0x3); | |
1663 | MLX5_SET(mkc, mkc, access_mode_4_2, (access_mode >> 2) & 0x7); | |
1664 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1665 | MLX5_SET(mkc, mkc, log_page_size, page_shift); | |
1666 | } | |
1667 | ||
1668 | static int _mlx5_alloc_mkey_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr, | |
1669 | int ndescs, int desc_size, int page_shift, | |
1670 | int access_mode, u32 *in, int inlen) | |
1671 | { | |
1672 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1673 | int err; | |
1674 | ||
1675 | mr->access_mode = access_mode; | |
1676 | mr->desc_size = desc_size; | |
1677 | mr->max_descs = ndescs; | |
1678 | ||
1679 | err = mlx5_alloc_priv_descs(pd->device, mr, ndescs, desc_size); | |
1680 | if (err) | |
1681 | return err; | |
1682 | ||
1683 | mlx5_set_umr_free_mkey(pd, in, ndescs, access_mode, page_shift); | |
1684 | ||
fc6a9f86 | 1685 | err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen); |
7796d2a3 MG |
1686 | if (err) |
1687 | goto err_free_descs; | |
1688 | ||
1689 | mr->mmkey.type = MLX5_MKEY_MR; | |
1690 | mr->ibmr.lkey = mr->mmkey.key; | |
1691 | mr->ibmr.rkey = mr->mmkey.key; | |
1692 | ||
1693 | return 0; | |
1694 | ||
1695 | err_free_descs: | |
1696 | mlx5_free_priv_descs(mr); | |
1697 | return err; | |
1698 | } | |
1699 | ||
6c984472 | 1700 | static struct mlx5_ib_mr *mlx5_ib_alloc_pi_mr(struct ib_pd *pd, |
de0ae958 IR |
1701 | u32 max_num_sg, u32 max_num_meta_sg, |
1702 | int desc_size, int access_mode) | |
3121e3c4 | 1703 | { |
ec22eb53 | 1704 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
6c984472 | 1705 | int ndescs = ALIGN(max_num_sg + max_num_meta_sg, 4); |
7796d2a3 | 1706 | int page_shift = 0; |
ec22eb53 | 1707 | struct mlx5_ib_mr *mr; |
ec22eb53 | 1708 | u32 *in; |
b005d316 | 1709 | int err; |
3121e3c4 SG |
1710 | |
1711 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1712 | if (!mr) | |
1713 | return ERR_PTR(-ENOMEM); | |
1714 | ||
7796d2a3 MG |
1715 | mr->ibmr.pd = pd; |
1716 | mr->ibmr.device = pd->device; | |
1717 | ||
ec22eb53 | 1718 | in = kzalloc(inlen, GFP_KERNEL); |
3121e3c4 SG |
1719 | if (!in) { |
1720 | err = -ENOMEM; | |
1721 | goto err_free; | |
1722 | } | |
1723 | ||
de0ae958 | 1724 | if (access_mode == MLX5_MKC_ACCESS_MODE_MTT) |
7796d2a3 | 1725 | page_shift = PAGE_SHIFT; |
3121e3c4 | 1726 | |
7796d2a3 MG |
1727 | err = _mlx5_alloc_mkey_descs(pd, mr, ndescs, desc_size, page_shift, |
1728 | access_mode, in, inlen); | |
6c984472 MG |
1729 | if (err) |
1730 | goto err_free_in; | |
6c984472 | 1731 | |
6c984472 MG |
1732 | mr->umem = NULL; |
1733 | kfree(in); | |
1734 | ||
1735 | return mr; | |
1736 | ||
6c984472 MG |
1737 | err_free_in: |
1738 | kfree(in); | |
1739 | err_free: | |
1740 | kfree(mr); | |
1741 | return ERR_PTR(err); | |
1742 | } | |
1743 | ||
7796d2a3 MG |
1744 | static int mlx5_alloc_mem_reg_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr, |
1745 | int ndescs, u32 *in, int inlen) | |
1746 | { | |
1747 | return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_mtt), | |
1748 | PAGE_SHIFT, MLX5_MKC_ACCESS_MODE_MTT, in, | |
1749 | inlen); | |
1750 | } | |
1751 | ||
1752 | static int mlx5_alloc_sg_gaps_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr, | |
1753 | int ndescs, u32 *in, int inlen) | |
1754 | { | |
1755 | return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_klm), | |
1756 | 0, MLX5_MKC_ACCESS_MODE_KLMS, in, inlen); | |
1757 | } | |
1758 | ||
1759 | static int mlx5_alloc_integrity_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr, | |
1760 | int max_num_sg, int max_num_meta_sg, | |
1761 | u32 *in, int inlen) | |
1762 | { | |
1763 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1764 | u32 psv_index[2]; | |
1765 | void *mkc; | |
1766 | int err; | |
1767 | ||
1768 | mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL); | |
1769 | if (!mr->sig) | |
1770 | return -ENOMEM; | |
1771 | ||
1772 | /* create mem & wire PSVs */ | |
1773 | err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, 2, psv_index); | |
1774 | if (err) | |
1775 | goto err_free_sig; | |
1776 | ||
1777 | mr->sig->psv_memory.psv_idx = psv_index[0]; | |
1778 | mr->sig->psv_wire.psv_idx = psv_index[1]; | |
1779 | ||
1780 | mr->sig->sig_status_checked = true; | |
1781 | mr->sig->sig_err_exists = false; | |
1782 | /* Next UMR, Arm SIGERR */ | |
1783 | ++mr->sig->sigerr_count; | |
1784 | mr->klm_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg, | |
1785 | sizeof(struct mlx5_klm), | |
1786 | MLX5_MKC_ACCESS_MODE_KLMS); | |
1787 | if (IS_ERR(mr->klm_mr)) { | |
1788 | err = PTR_ERR(mr->klm_mr); | |
1789 | goto err_destroy_psv; | |
1790 | } | |
1791 | mr->mtt_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg, | |
1792 | sizeof(struct mlx5_mtt), | |
1793 | MLX5_MKC_ACCESS_MODE_MTT); | |
1794 | if (IS_ERR(mr->mtt_mr)) { | |
1795 | err = PTR_ERR(mr->mtt_mr); | |
1796 | goto err_free_klm_mr; | |
1797 | } | |
1798 | ||
1799 | /* Set bsf descriptors for mkey */ | |
1800 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
1801 | MLX5_SET(mkc, mkc, bsf_en, 1); | |
1802 | MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE); | |
1803 | ||
1804 | err = _mlx5_alloc_mkey_descs(pd, mr, 4, sizeof(struct mlx5_klm), 0, | |
1805 | MLX5_MKC_ACCESS_MODE_KLMS, in, inlen); | |
1806 | if (err) | |
1807 | goto err_free_mtt_mr; | |
1808 | ||
50211ec9 JG |
1809 | err = xa_err(xa_store(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key), |
1810 | mr->sig, GFP_KERNEL)); | |
1811 | if (err) | |
1812 | goto err_free_descs; | |
7796d2a3 MG |
1813 | return 0; |
1814 | ||
50211ec9 JG |
1815 | err_free_descs: |
1816 | destroy_mkey(dev, mr); | |
1817 | mlx5_free_priv_descs(mr); | |
7796d2a3 MG |
1818 | err_free_mtt_mr: |
1819 | dereg_mr(to_mdev(mr->mtt_mr->ibmr.device), mr->mtt_mr); | |
1820 | mr->mtt_mr = NULL; | |
1821 | err_free_klm_mr: | |
1822 | dereg_mr(to_mdev(mr->klm_mr->ibmr.device), mr->klm_mr); | |
1823 | mr->klm_mr = NULL; | |
1824 | err_destroy_psv: | |
1825 | if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_memory.psv_idx)) | |
1826 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1827 | mr->sig->psv_memory.psv_idx); | |
1828 | if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_wire.psv_idx)) | |
1829 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1830 | mr->sig->psv_wire.psv_idx); | |
1831 | err_free_sig: | |
1832 | kfree(mr->sig); | |
1833 | ||
1834 | return err; | |
1835 | } | |
1836 | ||
6c984472 MG |
1837 | static struct ib_mr *__mlx5_ib_alloc_mr(struct ib_pd *pd, |
1838 | enum ib_mr_type mr_type, u32 max_num_sg, | |
1839 | u32 max_num_meta_sg) | |
1840 | { | |
1841 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1842 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); | |
1843 | int ndescs = ALIGN(max_num_sg, 4); | |
1844 | struct mlx5_ib_mr *mr; | |
6c984472 MG |
1845 | u32 *in; |
1846 | int err; | |
1847 | ||
1848 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1849 | if (!mr) | |
1850 | return ERR_PTR(-ENOMEM); | |
1851 | ||
1852 | in = kzalloc(inlen, GFP_KERNEL); | |
1853 | if (!in) { | |
1854 | err = -ENOMEM; | |
1855 | goto err_free; | |
1856 | } | |
1857 | ||
7796d2a3 MG |
1858 | mr->ibmr.device = pd->device; |
1859 | mr->umem = NULL; | |
3121e3c4 | 1860 | |
7796d2a3 MG |
1861 | switch (mr_type) { |
1862 | case IB_MR_TYPE_MEM_REG: | |
1863 | err = mlx5_alloc_mem_reg_descs(pd, mr, ndescs, in, inlen); | |
1864 | break; | |
1865 | case IB_MR_TYPE_SG_GAPS: | |
1866 | err = mlx5_alloc_sg_gaps_descs(pd, mr, ndescs, in, inlen); | |
1867 | break; | |
1868 | case IB_MR_TYPE_INTEGRITY: | |
1869 | err = mlx5_alloc_integrity_descs(pd, mr, max_num_sg, | |
1870 | max_num_meta_sg, in, inlen); | |
1871 | break; | |
1872 | default: | |
9bee178b SG |
1873 | mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type); |
1874 | err = -EINVAL; | |
3121e3c4 SG |
1875 | } |
1876 | ||
3121e3c4 | 1877 | if (err) |
7796d2a3 | 1878 | goto err_free_in; |
3121e3c4 | 1879 | |
3121e3c4 SG |
1880 | kfree(in); |
1881 | ||
1882 | return &mr->ibmr; | |
1883 | ||
3121e3c4 SG |
1884 | err_free_in: |
1885 | kfree(in); | |
1886 | err_free: | |
1887 | kfree(mr); | |
1888 | return ERR_PTR(err); | |
1889 | } | |
1890 | ||
6c984472 MG |
1891 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, |
1892 | u32 max_num_sg, struct ib_udata *udata) | |
1893 | { | |
1894 | return __mlx5_ib_alloc_mr(pd, mr_type, max_num_sg, 0); | |
1895 | } | |
1896 | ||
1897 | struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, | |
1898 | u32 max_num_sg, u32 max_num_meta_sg) | |
1899 | { | |
1900 | return __mlx5_ib_alloc_mr(pd, IB_MR_TYPE_INTEGRITY, max_num_sg, | |
1901 | max_num_meta_sg); | |
1902 | } | |
1903 | ||
d2370e0a MB |
1904 | struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
1905 | struct ib_udata *udata) | |
1906 | { | |
1907 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1908 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
d2370e0a | 1909 | struct mlx5_ib_mw *mw = NULL; |
ec22eb53 SM |
1910 | u32 *in = NULL; |
1911 | void *mkc; | |
d2370e0a MB |
1912 | int ndescs; |
1913 | int err; | |
1914 | struct mlx5_ib_alloc_mw req = {}; | |
1915 | struct { | |
1916 | __u32 comp_mask; | |
1917 | __u32 response_length; | |
1918 | } resp = {}; | |
1919 | ||
1920 | err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); | |
1921 | if (err) | |
1922 | return ERR_PTR(err); | |
1923 | ||
1924 | if (req.comp_mask || req.reserved1 || req.reserved2) | |
1925 | return ERR_PTR(-EOPNOTSUPP); | |
1926 | ||
1927 | if (udata->inlen > sizeof(req) && | |
1928 | !ib_is_udata_cleared(udata, sizeof(req), | |
1929 | udata->inlen - sizeof(req))) | |
1930 | return ERR_PTR(-EOPNOTSUPP); | |
1931 | ||
1932 | ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4); | |
1933 | ||
1934 | mw = kzalloc(sizeof(*mw), GFP_KERNEL); | |
ec22eb53 | 1935 | in = kzalloc(inlen, GFP_KERNEL); |
d2370e0a MB |
1936 | if (!mw || !in) { |
1937 | err = -ENOMEM; | |
1938 | goto free; | |
1939 | } | |
1940 | ||
ec22eb53 SM |
1941 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1942 | ||
1943 | MLX5_SET(mkc, mkc, free, 1); | |
1944 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1945 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1946 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1947 | MLX5_SET(mkc, mkc, lr, 1); | |
cdbd0d2b | 1948 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS); |
ec22eb53 SM |
1949 | MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2))); |
1950 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1951 | ||
fc6a9f86 | 1952 | err = mlx5_ib_create_mkey(dev, &mw->mmkey, in, inlen); |
d2370e0a MB |
1953 | if (err) |
1954 | goto free; | |
1955 | ||
aa8e08d2 | 1956 | mw->mmkey.type = MLX5_MKEY_MW; |
d2370e0a | 1957 | mw->ibmw.rkey = mw->mmkey.key; |
db570d7d | 1958 | mw->ndescs = ndescs; |
d2370e0a MB |
1959 | |
1960 | resp.response_length = min(offsetof(typeof(resp), response_length) + | |
1961 | sizeof(resp.response_length), udata->outlen); | |
1962 | if (resp.response_length) { | |
1963 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
1964 | if (err) { | |
1965 | mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey); | |
1966 | goto free; | |
1967 | } | |
1968 | } | |
1969 | ||
806b101b JG |
1970 | if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { |
1971 | err = xa_err(xa_store(&dev->odp_mkeys, | |
1972 | mlx5_base_mkey(mw->mmkey.key), &mw->mmkey, | |
1973 | GFP_KERNEL)); | |
1974 | if (err) | |
1975 | goto free_mkey; | |
1976 | } | |
1977 | ||
d2370e0a MB |
1978 | kfree(in); |
1979 | return &mw->ibmw; | |
1980 | ||
806b101b JG |
1981 | free_mkey: |
1982 | mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey); | |
d2370e0a MB |
1983 | free: |
1984 | kfree(mw); | |
1985 | kfree(in); | |
1986 | return ERR_PTR(err); | |
1987 | } | |
1988 | ||
1989 | int mlx5_ib_dealloc_mw(struct ib_mw *mw) | |
1990 | { | |
04177915 | 1991 | struct mlx5_ib_dev *dev = to_mdev(mw->device); |
d2370e0a MB |
1992 | struct mlx5_ib_mw *mmw = to_mmw(mw); |
1993 | int err; | |
1994 | ||
04177915 | 1995 | if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { |
806b101b | 1996 | xa_erase(&dev->odp_mkeys, mlx5_base_mkey(mmw->mmkey.key)); |
04177915 JG |
1997 | /* |
1998 | * pagefault_single_data_segment() may be accessing mmw under | |
1999 | * SRCU if the user bound an ODP MR to this MW. | |
2000 | */ | |
806b101b | 2001 | synchronize_srcu(&dev->odp_srcu); |
04177915 JG |
2002 | } |
2003 | ||
2004 | err = mlx5_core_destroy_mkey(dev->mdev, &mmw->mmkey); | |
2005 | if (err) | |
2006 | return err; | |
2007 | kfree(mmw); | |
2008 | return 0; | |
d2370e0a MB |
2009 | } |
2010 | ||
d5436ba0 SG |
2011 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
2012 | struct ib_mr_status *mr_status) | |
2013 | { | |
2014 | struct mlx5_ib_mr *mmr = to_mmr(ibmr); | |
2015 | int ret = 0; | |
2016 | ||
2017 | if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { | |
2018 | pr_err("Invalid status check mask\n"); | |
2019 | ret = -EINVAL; | |
2020 | goto done; | |
2021 | } | |
2022 | ||
2023 | mr_status->fail_status = 0; | |
2024 | if (check_mask & IB_MR_CHECK_SIG_STATUS) { | |
2025 | if (!mmr->sig) { | |
2026 | ret = -EINVAL; | |
2027 | pr_err("signature status check requested on a non-signature enabled MR\n"); | |
2028 | goto done; | |
2029 | } | |
2030 | ||
2031 | mmr->sig->sig_status_checked = true; | |
2032 | if (!mmr->sig->sig_err_exists) | |
2033 | goto done; | |
2034 | ||
2035 | if (ibmr->lkey == mmr->sig->err_item.key) | |
2036 | memcpy(&mr_status->sig_err, &mmr->sig->err_item, | |
2037 | sizeof(mr_status->sig_err)); | |
2038 | else { | |
2039 | mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; | |
2040 | mr_status->sig_err.sig_err_offset = 0; | |
2041 | mr_status->sig_err.key = mmr->sig->err_item.key; | |
2042 | } | |
2043 | ||
2044 | mmr->sig->sig_err_exists = false; | |
2045 | mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; | |
2046 | } | |
2047 | ||
2048 | done: | |
2049 | return ret; | |
2050 | } | |
8a187ee5 | 2051 | |
2563e2f3 MG |
2052 | static int |
2053 | mlx5_ib_map_pa_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, | |
2054 | int data_sg_nents, unsigned int *data_sg_offset, | |
2055 | struct scatterlist *meta_sg, int meta_sg_nents, | |
2056 | unsigned int *meta_sg_offset) | |
2057 | { | |
2058 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
2059 | unsigned int sg_offset = 0; | |
2060 | int n = 0; | |
2061 | ||
2062 | mr->meta_length = 0; | |
2063 | if (data_sg_nents == 1) { | |
2064 | n++; | |
2065 | mr->ndescs = 1; | |
2066 | if (data_sg_offset) | |
2067 | sg_offset = *data_sg_offset; | |
2068 | mr->data_length = sg_dma_len(data_sg) - sg_offset; | |
2069 | mr->data_iova = sg_dma_address(data_sg) + sg_offset; | |
2070 | if (meta_sg_nents == 1) { | |
2071 | n++; | |
2072 | mr->meta_ndescs = 1; | |
2073 | if (meta_sg_offset) | |
2074 | sg_offset = *meta_sg_offset; | |
2075 | else | |
2076 | sg_offset = 0; | |
2077 | mr->meta_length = sg_dma_len(meta_sg) - sg_offset; | |
2078 | mr->pi_iova = sg_dma_address(meta_sg) + sg_offset; | |
2079 | } | |
2080 | ibmr->length = mr->data_length + mr->meta_length; | |
2081 | } | |
2082 | ||
2083 | return n; | |
2084 | } | |
2085 | ||
b005d316 SG |
2086 | static int |
2087 | mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr, | |
2088 | struct scatterlist *sgl, | |
ff2ba993 | 2089 | unsigned short sg_nents, |
6c984472 MG |
2090 | unsigned int *sg_offset_p, |
2091 | struct scatterlist *meta_sgl, | |
2092 | unsigned short meta_sg_nents, | |
2093 | unsigned int *meta_sg_offset_p) | |
b005d316 SG |
2094 | { |
2095 | struct scatterlist *sg = sgl; | |
2096 | struct mlx5_klm *klms = mr->descs; | |
9aa8b321 | 2097 | unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; |
b005d316 | 2098 | u32 lkey = mr->ibmr.pd->local_dma_lkey; |
6c984472 | 2099 | int i, j = 0; |
b005d316 | 2100 | |
ff2ba993 | 2101 | mr->ibmr.iova = sg_dma_address(sg) + sg_offset; |
b005d316 | 2102 | mr->ibmr.length = 0; |
b005d316 SG |
2103 | |
2104 | for_each_sg(sgl, sg, sg_nents, i) { | |
99975cd4 | 2105 | if (unlikely(i >= mr->max_descs)) |
b005d316 | 2106 | break; |
ff2ba993 CH |
2107 | klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset); |
2108 | klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset); | |
b005d316 | 2109 | klms[i].key = cpu_to_be32(lkey); |
0a49f2c3 | 2110 | mr->ibmr.length += sg_dma_len(sg) - sg_offset; |
ff2ba993 CH |
2111 | |
2112 | sg_offset = 0; | |
b005d316 SG |
2113 | } |
2114 | ||
9aa8b321 BVA |
2115 | if (sg_offset_p) |
2116 | *sg_offset_p = sg_offset; | |
2117 | ||
6c984472 MG |
2118 | mr->ndescs = i; |
2119 | mr->data_length = mr->ibmr.length; | |
2120 | ||
2121 | if (meta_sg_nents) { | |
2122 | sg = meta_sgl; | |
2123 | sg_offset = meta_sg_offset_p ? *meta_sg_offset_p : 0; | |
2124 | for_each_sg(meta_sgl, sg, meta_sg_nents, j) { | |
2125 | if (unlikely(i + j >= mr->max_descs)) | |
2126 | break; | |
2127 | klms[i + j].va = cpu_to_be64(sg_dma_address(sg) + | |
2128 | sg_offset); | |
2129 | klms[i + j].bcount = cpu_to_be32(sg_dma_len(sg) - | |
2130 | sg_offset); | |
2131 | klms[i + j].key = cpu_to_be32(lkey); | |
2132 | mr->ibmr.length += sg_dma_len(sg) - sg_offset; | |
2133 | ||
2134 | sg_offset = 0; | |
2135 | } | |
2136 | if (meta_sg_offset_p) | |
2137 | *meta_sg_offset_p = sg_offset; | |
2138 | ||
2139 | mr->meta_ndescs = j; | |
2140 | mr->meta_length = mr->ibmr.length - mr->data_length; | |
2141 | } | |
2142 | ||
2143 | return i + j; | |
b005d316 SG |
2144 | } |
2145 | ||
8a187ee5 SG |
2146 | static int mlx5_set_page(struct ib_mr *ibmr, u64 addr) |
2147 | { | |
2148 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
2149 | __be64 *descs; | |
2150 | ||
2151 | if (unlikely(mr->ndescs == mr->max_descs)) | |
2152 | return -ENOMEM; | |
2153 | ||
2154 | descs = mr->descs; | |
2155 | descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); | |
2156 | ||
2157 | return 0; | |
2158 | } | |
2159 | ||
de0ae958 IR |
2160 | static int mlx5_set_page_pi(struct ib_mr *ibmr, u64 addr) |
2161 | { | |
2162 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
2163 | __be64 *descs; | |
2164 | ||
2165 | if (unlikely(mr->ndescs + mr->meta_ndescs == mr->max_descs)) | |
2166 | return -ENOMEM; | |
2167 | ||
2168 | descs = mr->descs; | |
2169 | descs[mr->ndescs + mr->meta_ndescs++] = | |
2170 | cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); | |
2171 | ||
2172 | return 0; | |
2173 | } | |
2174 | ||
2175 | static int | |
2176 | mlx5_ib_map_mtt_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, | |
6c984472 MG |
2177 | int data_sg_nents, unsigned int *data_sg_offset, |
2178 | struct scatterlist *meta_sg, int meta_sg_nents, | |
2179 | unsigned int *meta_sg_offset) | |
2180 | { | |
2181 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
de0ae958 | 2182 | struct mlx5_ib_mr *pi_mr = mr->mtt_mr; |
6c984472 MG |
2183 | int n; |
2184 | ||
de0ae958 IR |
2185 | pi_mr->ndescs = 0; |
2186 | pi_mr->meta_ndescs = 0; | |
2187 | pi_mr->meta_length = 0; | |
2188 | ||
2189 | ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map, | |
2190 | pi_mr->desc_size * pi_mr->max_descs, | |
2191 | DMA_TO_DEVICE); | |
2192 | ||
2193 | pi_mr->ibmr.page_size = ibmr->page_size; | |
2194 | n = ib_sg_to_pages(&pi_mr->ibmr, data_sg, data_sg_nents, data_sg_offset, | |
2195 | mlx5_set_page); | |
2196 | if (n != data_sg_nents) | |
2197 | return n; | |
2198 | ||
2563e2f3 | 2199 | pi_mr->data_iova = pi_mr->ibmr.iova; |
de0ae958 IR |
2200 | pi_mr->data_length = pi_mr->ibmr.length; |
2201 | pi_mr->ibmr.length = pi_mr->data_length; | |
2202 | ibmr->length = pi_mr->data_length; | |
2203 | ||
2204 | if (meta_sg_nents) { | |
2205 | u64 page_mask = ~((u64)ibmr->page_size - 1); | |
2563e2f3 | 2206 | u64 iova = pi_mr->data_iova; |
de0ae958 IR |
2207 | |
2208 | n += ib_sg_to_pages(&pi_mr->ibmr, meta_sg, meta_sg_nents, | |
2209 | meta_sg_offset, mlx5_set_page_pi); | |
2210 | ||
2211 | pi_mr->meta_length = pi_mr->ibmr.length; | |
2212 | /* | |
2213 | * PI address for the HW is the offset of the metadata address | |
2214 | * relative to the first data page address. | |
2215 | * It equals to first data page address + size of data pages + | |
2216 | * metadata offset at the first metadata page | |
2217 | */ | |
2218 | pi_mr->pi_iova = (iova & page_mask) + | |
2219 | pi_mr->ndescs * ibmr->page_size + | |
2220 | (pi_mr->ibmr.iova & ~page_mask); | |
2221 | /* | |
2222 | * In order to use one MTT MR for data and metadata, we register | |
2223 | * also the gaps between the end of the data and the start of | |
2224 | * the metadata (the sig MR will verify that the HW will access | |
2225 | * to right addresses). This mapping is safe because we use | |
2226 | * internal mkey for the registration. | |
2227 | */ | |
2228 | pi_mr->ibmr.length = pi_mr->pi_iova + pi_mr->meta_length - iova; | |
2229 | pi_mr->ibmr.iova = iova; | |
2230 | ibmr->length += pi_mr->meta_length; | |
2231 | } | |
2232 | ||
2233 | ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map, | |
2234 | pi_mr->desc_size * pi_mr->max_descs, | |
2235 | DMA_TO_DEVICE); | |
2236 | ||
2237 | return n; | |
2238 | } | |
2239 | ||
2240 | static int | |
2241 | mlx5_ib_map_klm_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, | |
2242 | int data_sg_nents, unsigned int *data_sg_offset, | |
2243 | struct scatterlist *meta_sg, int meta_sg_nents, | |
2244 | unsigned int *meta_sg_offset) | |
2245 | { | |
2246 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
2247 | struct mlx5_ib_mr *pi_mr = mr->klm_mr; | |
2248 | int n; | |
6c984472 MG |
2249 | |
2250 | pi_mr->ndescs = 0; | |
2251 | pi_mr->meta_ndescs = 0; | |
2252 | pi_mr->meta_length = 0; | |
2253 | ||
2254 | ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map, | |
2255 | pi_mr->desc_size * pi_mr->max_descs, | |
2256 | DMA_TO_DEVICE); | |
2257 | ||
2258 | n = mlx5_ib_sg_to_klms(pi_mr, data_sg, data_sg_nents, data_sg_offset, | |
2259 | meta_sg, meta_sg_nents, meta_sg_offset); | |
2260 | ||
de0ae958 IR |
2261 | ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map, |
2262 | pi_mr->desc_size * pi_mr->max_descs, | |
2263 | DMA_TO_DEVICE); | |
2264 | ||
6c984472 | 2265 | /* This is zero-based memory region */ |
2563e2f3 | 2266 | pi_mr->data_iova = 0; |
6c984472 | 2267 | pi_mr->ibmr.iova = 0; |
de0ae958 | 2268 | pi_mr->pi_iova = pi_mr->data_length; |
6c984472 | 2269 | ibmr->length = pi_mr->ibmr.length; |
6c984472 | 2270 | |
de0ae958 IR |
2271 | return n; |
2272 | } | |
6c984472 | 2273 | |
de0ae958 IR |
2274 | int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, |
2275 | int data_sg_nents, unsigned int *data_sg_offset, | |
2276 | struct scatterlist *meta_sg, int meta_sg_nents, | |
2277 | unsigned int *meta_sg_offset) | |
2278 | { | |
2279 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
2563e2f3 | 2280 | struct mlx5_ib_mr *pi_mr = NULL; |
de0ae958 IR |
2281 | int n; |
2282 | ||
2283 | WARN_ON(ibmr->type != IB_MR_TYPE_INTEGRITY); | |
2284 | ||
2563e2f3 MG |
2285 | mr->ndescs = 0; |
2286 | mr->data_length = 0; | |
2287 | mr->data_iova = 0; | |
2288 | mr->meta_ndescs = 0; | |
2289 | mr->pi_iova = 0; | |
2290 | /* | |
2291 | * As a performance optimization, if possible, there is no need to | |
2292 | * perform UMR operation to register the data/metadata buffers. | |
2293 | * First try to map the sg lists to PA descriptors with local_dma_lkey. | |
2294 | * Fallback to UMR only in case of a failure. | |
2295 | */ | |
2296 | n = mlx5_ib_map_pa_mr_sg_pi(ibmr, data_sg, data_sg_nents, | |
2297 | data_sg_offset, meta_sg, meta_sg_nents, | |
2298 | meta_sg_offset); | |
2299 | if (n == data_sg_nents + meta_sg_nents) | |
2300 | goto out; | |
de0ae958 IR |
2301 | /* |
2302 | * As a performance optimization, if possible, there is no need to map | |
2303 | * the sg lists to KLM descriptors. First try to map the sg lists to MTT | |
2304 | * descriptors and fallback to KLM only in case of a failure. | |
2305 | * It's more efficient for the HW to work with MTT descriptors | |
2306 | * (especially in high load). | |
2307 | * Use KLM (indirect access) only if it's mandatory. | |
2308 | */ | |
2563e2f3 | 2309 | pi_mr = mr->mtt_mr; |
de0ae958 IR |
2310 | n = mlx5_ib_map_mtt_mr_sg_pi(ibmr, data_sg, data_sg_nents, |
2311 | data_sg_offset, meta_sg, meta_sg_nents, | |
2312 | meta_sg_offset); | |
2313 | if (n == data_sg_nents + meta_sg_nents) | |
2314 | goto out; | |
2315 | ||
2316 | pi_mr = mr->klm_mr; | |
2317 | n = mlx5_ib_map_klm_mr_sg_pi(ibmr, data_sg, data_sg_nents, | |
2318 | data_sg_offset, meta_sg, meta_sg_nents, | |
2319 | meta_sg_offset); | |
6c984472 MG |
2320 | if (unlikely(n != data_sg_nents + meta_sg_nents)) |
2321 | return -ENOMEM; | |
2322 | ||
de0ae958 IR |
2323 | out: |
2324 | /* This is zero-based memory region */ | |
2325 | ibmr->iova = 0; | |
2326 | mr->pi_mr = pi_mr; | |
2563e2f3 MG |
2327 | if (pi_mr) |
2328 | ibmr->sig_attrs->meta_length = pi_mr->meta_length; | |
2329 | else | |
2330 | ibmr->sig_attrs->meta_length = mr->meta_length; | |
de0ae958 | 2331 | |
6c984472 MG |
2332 | return 0; |
2333 | } | |
2334 | ||
ff2ba993 | 2335 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 2336 | unsigned int *sg_offset) |
8a187ee5 SG |
2337 | { |
2338 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
2339 | int n; | |
2340 | ||
2341 | mr->ndescs = 0; | |
2342 | ||
2343 | ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map, | |
2344 | mr->desc_size * mr->max_descs, | |
2345 | DMA_TO_DEVICE); | |
2346 | ||
ec22eb53 | 2347 | if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) |
6c984472 MG |
2348 | n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset, NULL, 0, |
2349 | NULL); | |
b005d316 | 2350 | else |
ff2ba993 CH |
2351 | n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, |
2352 | mlx5_set_page); | |
8a187ee5 SG |
2353 | |
2354 | ib_dma_sync_single_for_device(ibmr->device, mr->desc_map, | |
2355 | mr->desc_size * mr->max_descs, | |
2356 | DMA_TO_DEVICE); | |
2357 | ||
2358 | return n; | |
2359 | } |