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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | ||
34 | #include <linux/kref.h> | |
35 | #include <linux/random.h> | |
36 | #include <linux/debugfs.h> | |
37 | #include <linux/export.h> | |
746b5583 | 38 | #include <linux/delay.h> |
e126ba97 | 39 | #include <rdma/ib_umem.h> |
b4cfe447 | 40 | #include <rdma/ib_umem_odp.h> |
968e78dd | 41 | #include <rdma/ib_verbs.h> |
e126ba97 EC |
42 | #include "mlx5_ib.h" |
43 | ||
44 | enum { | |
746b5583 | 45 | MAX_PENDING_REG_MR = 8, |
e126ba97 EC |
46 | }; |
47 | ||
832a6b06 | 48 | #define MLX5_UMR_ALIGN 2048 |
fe45f827 | 49 | |
6aec21f6 | 50 | static int clean_mr(struct mlx5_ib_mr *mr); |
7d0cc6ed | 51 | static int use_umr(struct mlx5_ib_dev *dev, int order); |
49780d42 | 52 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); |
6aec21f6 | 53 | |
b4cfe447 HE |
54 | static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
55 | { | |
a606b0f6 | 56 | int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); |
b4cfe447 HE |
57 | |
58 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
59 | /* Wait until all page fault handlers using the mr complete. */ | |
60 | synchronize_srcu(&dev->mr_srcu); | |
61 | #endif | |
62 | ||
63 | return err; | |
64 | } | |
65 | ||
e126ba97 EC |
66 | static int order2idx(struct mlx5_ib_dev *dev, int order) |
67 | { | |
68 | struct mlx5_mr_cache *cache = &dev->cache; | |
69 | ||
70 | if (order < cache->ent[0].order) | |
71 | return 0; | |
72 | else | |
73 | return order - cache->ent[0].order; | |
74 | } | |
75 | ||
56e11d62 NO |
76 | static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length) |
77 | { | |
78 | return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >= | |
79 | length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1)); | |
80 | } | |
81 | ||
395a8e4c NO |
82 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
83 | static void update_odp_mr(struct mlx5_ib_mr *mr) | |
84 | { | |
85 | if (mr->umem->odp_data) { | |
86 | /* | |
87 | * This barrier prevents the compiler from moving the | |
88 | * setting of umem->odp_data->private to point to our | |
89 | * MR, before reg_umr finished, to ensure that the MR | |
90 | * initialization have finished before starting to | |
91 | * handle invalidations. | |
92 | */ | |
93 | smp_wmb(); | |
94 | mr->umem->odp_data->private = mr; | |
95 | /* | |
96 | * Make sure we will see the new | |
97 | * umem->odp_data->private value in the invalidation | |
98 | * routines, before we can get page faults on the | |
99 | * MR. Page faults can happen once we put the MR in | |
100 | * the tree, below this line. Without the barrier, | |
101 | * there can be a fault handling and an invalidation | |
102 | * before umem->odp_data->private == mr is visible to | |
103 | * the invalidation handler. | |
104 | */ | |
105 | smp_wmb(); | |
106 | } | |
107 | } | |
108 | #endif | |
109 | ||
746b5583 EC |
110 | static void reg_mr_callback(int status, void *context) |
111 | { | |
112 | struct mlx5_ib_mr *mr = context; | |
113 | struct mlx5_ib_dev *dev = mr->dev; | |
114 | struct mlx5_mr_cache *cache = &dev->cache; | |
115 | int c = order2idx(dev, mr->order); | |
116 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
117 | u8 key; | |
746b5583 | 118 | unsigned long flags; |
a606b0f6 | 119 | struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table; |
8605933a | 120 | int err; |
746b5583 | 121 | |
746b5583 EC |
122 | spin_lock_irqsave(&ent->lock, flags); |
123 | ent->pending--; | |
124 | spin_unlock_irqrestore(&ent->lock, flags); | |
125 | if (status) { | |
126 | mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status); | |
127 | kfree(mr); | |
128 | dev->fill_delay = 1; | |
129 | mod_timer(&dev->delay_timer, jiffies + HZ); | |
130 | return; | |
131 | } | |
132 | ||
aa8e08d2 | 133 | mr->mmkey.type = MLX5_MKEY_MR; |
9603b61d JM |
134 | spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags); |
135 | key = dev->mdev->priv.mkey_key++; | |
136 | spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags); | |
ec22eb53 | 137 | mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key; |
746b5583 EC |
138 | |
139 | cache->last_add = jiffies; | |
140 | ||
141 | spin_lock_irqsave(&ent->lock, flags); | |
142 | list_add_tail(&mr->list, &ent->head); | |
143 | ent->cur++; | |
144 | ent->size++; | |
145 | spin_unlock_irqrestore(&ent->lock, flags); | |
8605933a HE |
146 | |
147 | write_lock_irqsave(&table->lock, flags); | |
a606b0f6 MB |
148 | err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key), |
149 | &mr->mmkey); | |
8605933a | 150 | if (err) |
a606b0f6 | 151 | pr_err("Error inserting to mkey tree. 0x%x\n", -err); |
8605933a | 152 | write_unlock_irqrestore(&table->lock, flags); |
49780d42 AK |
153 | |
154 | if (!completion_done(&ent->compl)) | |
155 | complete(&ent->compl); | |
746b5583 EC |
156 | } |
157 | ||
e126ba97 EC |
158 | static int add_keys(struct mlx5_ib_dev *dev, int c, int num) |
159 | { | |
e126ba97 EC |
160 | struct mlx5_mr_cache *cache = &dev->cache; |
161 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
ec22eb53 | 162 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
e126ba97 | 163 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
164 | void *mkc; |
165 | u32 *in; | |
e126ba97 EC |
166 | int err = 0; |
167 | int i; | |
168 | ||
ec22eb53 | 169 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
170 | if (!in) |
171 | return -ENOMEM; | |
172 | ||
ec22eb53 | 173 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
e126ba97 | 174 | for (i = 0; i < num; i++) { |
746b5583 EC |
175 | if (ent->pending >= MAX_PENDING_REG_MR) { |
176 | err = -EAGAIN; | |
177 | break; | |
178 | } | |
179 | ||
e126ba97 EC |
180 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
181 | if (!mr) { | |
182 | err = -ENOMEM; | |
746b5583 | 183 | break; |
e126ba97 EC |
184 | } |
185 | mr->order = ent->order; | |
186 | mr->umred = 1; | |
746b5583 | 187 | mr->dev = dev; |
ec22eb53 SM |
188 | |
189 | MLX5_SET(mkc, mkc, free, 1); | |
190 | MLX5_SET(mkc, mkc, umr_en, 1); | |
49780d42 | 191 | MLX5_SET(mkc, mkc, access_mode, ent->access_mode); |
ec22eb53 SM |
192 | |
193 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
49780d42 AK |
194 | MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt); |
195 | MLX5_SET(mkc, mkc, log_page_size, ent->page); | |
e126ba97 | 196 | |
746b5583 EC |
197 | spin_lock_irq(&ent->lock); |
198 | ent->pending++; | |
199 | spin_unlock_irq(&ent->lock); | |
ec22eb53 SM |
200 | err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey, |
201 | in, inlen, | |
202 | mr->out, sizeof(mr->out), | |
203 | reg_mr_callback, mr); | |
e126ba97 | 204 | if (err) { |
d14e7110 EC |
205 | spin_lock_irq(&ent->lock); |
206 | ent->pending--; | |
207 | spin_unlock_irq(&ent->lock); | |
e126ba97 | 208 | mlx5_ib_warn(dev, "create mkey failed %d\n", err); |
e126ba97 | 209 | kfree(mr); |
746b5583 | 210 | break; |
e126ba97 | 211 | } |
e126ba97 EC |
212 | } |
213 | ||
e126ba97 EC |
214 | kfree(in); |
215 | return err; | |
216 | } | |
217 | ||
218 | static void remove_keys(struct mlx5_ib_dev *dev, int c, int num) | |
219 | { | |
e126ba97 EC |
220 | struct mlx5_mr_cache *cache = &dev->cache; |
221 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
222 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
223 | int err; |
224 | int i; | |
225 | ||
226 | for (i = 0; i < num; i++) { | |
746b5583 | 227 | spin_lock_irq(&ent->lock); |
e126ba97 | 228 | if (list_empty(&ent->head)) { |
746b5583 | 229 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
230 | return; |
231 | } | |
232 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
233 | list_del(&mr->list); | |
234 | ent->cur--; | |
235 | ent->size--; | |
746b5583 | 236 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 237 | err = destroy_mkey(dev, mr); |
203099fd | 238 | if (err) |
e126ba97 | 239 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 240 | else |
e126ba97 | 241 | kfree(mr); |
e126ba97 EC |
242 | } |
243 | } | |
244 | ||
245 | static ssize_t size_write(struct file *filp, const char __user *buf, | |
246 | size_t count, loff_t *pos) | |
247 | { | |
248 | struct mlx5_cache_ent *ent = filp->private_data; | |
249 | struct mlx5_ib_dev *dev = ent->dev; | |
250 | char lbuf[20]; | |
251 | u32 var; | |
252 | int err; | |
253 | int c; | |
254 | ||
255 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 256 | return -EFAULT; |
e126ba97 EC |
257 | |
258 | c = order2idx(dev, ent->order); | |
259 | lbuf[sizeof(lbuf) - 1] = 0; | |
260 | ||
261 | if (sscanf(lbuf, "%u", &var) != 1) | |
262 | return -EINVAL; | |
263 | ||
264 | if (var < ent->limit) | |
265 | return -EINVAL; | |
266 | ||
267 | if (var > ent->size) { | |
746b5583 EC |
268 | do { |
269 | err = add_keys(dev, c, var - ent->size); | |
270 | if (err && err != -EAGAIN) | |
271 | return err; | |
272 | ||
273 | usleep_range(3000, 5000); | |
274 | } while (err); | |
e126ba97 EC |
275 | } else if (var < ent->size) { |
276 | remove_keys(dev, c, ent->size - var); | |
277 | } | |
278 | ||
279 | return count; | |
280 | } | |
281 | ||
282 | static ssize_t size_read(struct file *filp, char __user *buf, size_t count, | |
283 | loff_t *pos) | |
284 | { | |
285 | struct mlx5_cache_ent *ent = filp->private_data; | |
286 | char lbuf[20]; | |
287 | int err; | |
288 | ||
289 | if (*pos) | |
290 | return 0; | |
291 | ||
292 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size); | |
293 | if (err < 0) | |
294 | return err; | |
295 | ||
296 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 297 | return -EFAULT; |
e126ba97 EC |
298 | |
299 | *pos += err; | |
300 | ||
301 | return err; | |
302 | } | |
303 | ||
304 | static const struct file_operations size_fops = { | |
305 | .owner = THIS_MODULE, | |
306 | .open = simple_open, | |
307 | .write = size_write, | |
308 | .read = size_read, | |
309 | }; | |
310 | ||
311 | static ssize_t limit_write(struct file *filp, const char __user *buf, | |
312 | size_t count, loff_t *pos) | |
313 | { | |
314 | struct mlx5_cache_ent *ent = filp->private_data; | |
315 | struct mlx5_ib_dev *dev = ent->dev; | |
316 | char lbuf[20]; | |
317 | u32 var; | |
318 | int err; | |
319 | int c; | |
320 | ||
321 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 322 | return -EFAULT; |
e126ba97 EC |
323 | |
324 | c = order2idx(dev, ent->order); | |
325 | lbuf[sizeof(lbuf) - 1] = 0; | |
326 | ||
327 | if (sscanf(lbuf, "%u", &var) != 1) | |
328 | return -EINVAL; | |
329 | ||
330 | if (var > ent->size) | |
331 | return -EINVAL; | |
332 | ||
333 | ent->limit = var; | |
334 | ||
335 | if (ent->cur < ent->limit) { | |
336 | err = add_keys(dev, c, 2 * ent->limit - ent->cur); | |
337 | if (err) | |
338 | return err; | |
339 | } | |
340 | ||
341 | return count; | |
342 | } | |
343 | ||
344 | static ssize_t limit_read(struct file *filp, char __user *buf, size_t count, | |
345 | loff_t *pos) | |
346 | { | |
347 | struct mlx5_cache_ent *ent = filp->private_data; | |
348 | char lbuf[20]; | |
349 | int err; | |
350 | ||
351 | if (*pos) | |
352 | return 0; | |
353 | ||
354 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit); | |
355 | if (err < 0) | |
356 | return err; | |
357 | ||
358 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 359 | return -EFAULT; |
e126ba97 EC |
360 | |
361 | *pos += err; | |
362 | ||
363 | return err; | |
364 | } | |
365 | ||
366 | static const struct file_operations limit_fops = { | |
367 | .owner = THIS_MODULE, | |
368 | .open = simple_open, | |
369 | .write = limit_write, | |
370 | .read = limit_read, | |
371 | }; | |
372 | ||
373 | static int someone_adding(struct mlx5_mr_cache *cache) | |
374 | { | |
375 | int i; | |
376 | ||
377 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
378 | if (cache->ent[i].cur < cache->ent[i].limit) | |
379 | return 1; | |
380 | } | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | static void __cache_work_func(struct mlx5_cache_ent *ent) | |
386 | { | |
387 | struct mlx5_ib_dev *dev = ent->dev; | |
388 | struct mlx5_mr_cache *cache = &dev->cache; | |
389 | int i = order2idx(dev, ent->order); | |
746b5583 | 390 | int err; |
e126ba97 EC |
391 | |
392 | if (cache->stopped) | |
393 | return; | |
394 | ||
395 | ent = &dev->cache.ent[i]; | |
746b5583 EC |
396 | if (ent->cur < 2 * ent->limit && !dev->fill_delay) { |
397 | err = add_keys(dev, i, 1); | |
398 | if (ent->cur < 2 * ent->limit) { | |
399 | if (err == -EAGAIN) { | |
400 | mlx5_ib_dbg(dev, "returned eagain, order %d\n", | |
401 | i + 2); | |
402 | queue_delayed_work(cache->wq, &ent->dwork, | |
403 | msecs_to_jiffies(3)); | |
404 | } else if (err) { | |
405 | mlx5_ib_warn(dev, "command failed order %d, err %d\n", | |
406 | i + 2, err); | |
407 | queue_delayed_work(cache->wq, &ent->dwork, | |
408 | msecs_to_jiffies(1000)); | |
409 | } else { | |
410 | queue_work(cache->wq, &ent->work); | |
411 | } | |
412 | } | |
e126ba97 | 413 | } else if (ent->cur > 2 * ent->limit) { |
ab5cdc31 LR |
414 | /* |
415 | * The remove_keys() logic is performed as garbage collection | |
416 | * task. Such task is intended to be run when no other active | |
417 | * processes are running. | |
418 | * | |
419 | * The need_resched() will return TRUE if there are user tasks | |
420 | * to be activated in near future. | |
421 | * | |
422 | * In such case, we don't execute remove_keys() and postpone | |
423 | * the garbage collection work to try to run in next cycle, | |
424 | * in order to free CPU resources to other tasks. | |
425 | */ | |
426 | if (!need_resched() && !someone_adding(cache) && | |
746b5583 | 427 | time_after(jiffies, cache->last_add + 300 * HZ)) { |
e126ba97 EC |
428 | remove_keys(dev, i, 1); |
429 | if (ent->cur > ent->limit) | |
430 | queue_work(cache->wq, &ent->work); | |
431 | } else { | |
746b5583 | 432 | queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ); |
e126ba97 EC |
433 | } |
434 | } | |
435 | } | |
436 | ||
437 | static void delayed_cache_work_func(struct work_struct *work) | |
438 | { | |
439 | struct mlx5_cache_ent *ent; | |
440 | ||
441 | ent = container_of(work, struct mlx5_cache_ent, dwork.work); | |
442 | __cache_work_func(ent); | |
443 | } | |
444 | ||
445 | static void cache_work_func(struct work_struct *work) | |
446 | { | |
447 | struct mlx5_cache_ent *ent; | |
448 | ||
449 | ent = container_of(work, struct mlx5_cache_ent, work); | |
450 | __cache_work_func(ent); | |
451 | } | |
452 | ||
49780d42 AK |
453 | struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry) |
454 | { | |
455 | struct mlx5_mr_cache *cache = &dev->cache; | |
456 | struct mlx5_cache_ent *ent; | |
457 | struct mlx5_ib_mr *mr; | |
458 | int err; | |
459 | ||
460 | if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) { | |
461 | mlx5_ib_err(dev, "cache entry %d is out of range\n", entry); | |
462 | return NULL; | |
463 | } | |
464 | ||
465 | ent = &cache->ent[entry]; | |
466 | while (1) { | |
467 | spin_lock_irq(&ent->lock); | |
468 | if (list_empty(&ent->head)) { | |
469 | spin_unlock_irq(&ent->lock); | |
470 | ||
471 | err = add_keys(dev, entry, 1); | |
81713d37 | 472 | if (err && err != -EAGAIN) |
49780d42 AK |
473 | return ERR_PTR(err); |
474 | ||
475 | wait_for_completion(&ent->compl); | |
476 | } else { | |
477 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
478 | list); | |
479 | list_del(&mr->list); | |
480 | ent->cur--; | |
481 | spin_unlock_irq(&ent->lock); | |
482 | if (ent->cur < ent->limit) | |
483 | queue_work(cache->wq, &ent->work); | |
484 | return mr; | |
485 | } | |
486 | } | |
487 | } | |
488 | ||
e126ba97 EC |
489 | static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order) |
490 | { | |
491 | struct mlx5_mr_cache *cache = &dev->cache; | |
492 | struct mlx5_ib_mr *mr = NULL; | |
493 | struct mlx5_cache_ent *ent; | |
494 | int c; | |
495 | int i; | |
496 | ||
497 | c = order2idx(dev, order); | |
49780d42 | 498 | if (c < 0 || c > MAX_UMR_CACHE_ENTRY) { |
e126ba97 EC |
499 | mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c); |
500 | return NULL; | |
501 | } | |
502 | ||
49780d42 | 503 | for (i = c; i < MAX_UMR_CACHE_ENTRY; i++) { |
e126ba97 EC |
504 | ent = &cache->ent[i]; |
505 | ||
506 | mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i); | |
507 | ||
746b5583 | 508 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
509 | if (!list_empty(&ent->head)) { |
510 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
511 | list); | |
512 | list_del(&mr->list); | |
513 | ent->cur--; | |
746b5583 | 514 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
515 | if (ent->cur < ent->limit) |
516 | queue_work(cache->wq, &ent->work); | |
517 | break; | |
518 | } | |
746b5583 | 519 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
520 | |
521 | queue_work(cache->wq, &ent->work); | |
e126ba97 EC |
522 | } |
523 | ||
524 | if (!mr) | |
525 | cache->ent[c].miss++; | |
526 | ||
527 | return mr; | |
528 | } | |
529 | ||
49780d42 | 530 | void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
e126ba97 EC |
531 | { |
532 | struct mlx5_mr_cache *cache = &dev->cache; | |
533 | struct mlx5_cache_ent *ent; | |
534 | int shrink = 0; | |
535 | int c; | |
536 | ||
537 | c = order2idx(dev, mr->order); | |
538 | if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { | |
539 | mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c); | |
540 | return; | |
541 | } | |
49780d42 AK |
542 | |
543 | if (unreg_umr(dev, mr)) | |
544 | return; | |
545 | ||
e126ba97 | 546 | ent = &cache->ent[c]; |
746b5583 | 547 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
548 | list_add_tail(&mr->list, &ent->head); |
549 | ent->cur++; | |
550 | if (ent->cur > 2 * ent->limit) | |
551 | shrink = 1; | |
746b5583 | 552 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
553 | |
554 | if (shrink) | |
555 | queue_work(cache->wq, &ent->work); | |
556 | } | |
557 | ||
558 | static void clean_keys(struct mlx5_ib_dev *dev, int c) | |
559 | { | |
e126ba97 EC |
560 | struct mlx5_mr_cache *cache = &dev->cache; |
561 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
562 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
563 | int err; |
564 | ||
3c461911 | 565 | cancel_delayed_work(&ent->dwork); |
e126ba97 | 566 | while (1) { |
746b5583 | 567 | spin_lock_irq(&ent->lock); |
e126ba97 | 568 | if (list_empty(&ent->head)) { |
746b5583 | 569 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
570 | return; |
571 | } | |
572 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
573 | list_del(&mr->list); | |
574 | ent->cur--; | |
575 | ent->size--; | |
746b5583 | 576 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 577 | err = destroy_mkey(dev, mr); |
203099fd | 578 | if (err) |
e126ba97 | 579 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 580 | else |
e126ba97 | 581 | kfree(mr); |
e126ba97 EC |
582 | } |
583 | } | |
584 | ||
585 | static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev) | |
586 | { | |
587 | struct mlx5_mr_cache *cache = &dev->cache; | |
588 | struct mlx5_cache_ent *ent; | |
589 | int i; | |
590 | ||
591 | if (!mlx5_debugfs_root) | |
592 | return 0; | |
593 | ||
9603b61d | 594 | cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root); |
e126ba97 EC |
595 | if (!cache->root) |
596 | return -ENOMEM; | |
597 | ||
598 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
599 | ent = &cache->ent[i]; | |
600 | sprintf(ent->name, "%d", ent->order); | |
601 | ent->dir = debugfs_create_dir(ent->name, cache->root); | |
602 | if (!ent->dir) | |
603 | return -ENOMEM; | |
604 | ||
605 | ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent, | |
606 | &size_fops); | |
607 | if (!ent->fsize) | |
608 | return -ENOMEM; | |
609 | ||
610 | ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent, | |
611 | &limit_fops); | |
612 | if (!ent->flimit) | |
613 | return -ENOMEM; | |
614 | ||
615 | ent->fcur = debugfs_create_u32("cur", 0400, ent->dir, | |
616 | &ent->cur); | |
617 | if (!ent->fcur) | |
618 | return -ENOMEM; | |
619 | ||
620 | ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir, | |
621 | &ent->miss); | |
622 | if (!ent->fmiss) | |
623 | return -ENOMEM; | |
624 | } | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) | |
630 | { | |
631 | if (!mlx5_debugfs_root) | |
632 | return; | |
633 | ||
634 | debugfs_remove_recursive(dev->cache.root); | |
635 | } | |
636 | ||
746b5583 EC |
637 | static void delay_time_func(unsigned long ctx) |
638 | { | |
639 | struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx; | |
640 | ||
641 | dev->fill_delay = 0; | |
642 | } | |
643 | ||
e126ba97 EC |
644 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) |
645 | { | |
646 | struct mlx5_mr_cache *cache = &dev->cache; | |
647 | struct mlx5_cache_ent *ent; | |
e126ba97 EC |
648 | int err; |
649 | int i; | |
650 | ||
6bc1a656 | 651 | mutex_init(&dev->slow_path_mutex); |
3c856c82 | 652 | cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM); |
e126ba97 EC |
653 | if (!cache->wq) { |
654 | mlx5_ib_warn(dev, "failed to create work queue\n"); | |
655 | return -ENOMEM; | |
656 | } | |
657 | ||
746b5583 | 658 | setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev); |
e126ba97 | 659 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { |
e126ba97 EC |
660 | ent = &cache->ent[i]; |
661 | INIT_LIST_HEAD(&ent->head); | |
662 | spin_lock_init(&ent->lock); | |
663 | ent->order = i + 2; | |
664 | ent->dev = dev; | |
49780d42 | 665 | ent->limit = 0; |
e126ba97 | 666 | |
49780d42 | 667 | init_completion(&ent->compl); |
e126ba97 EC |
668 | INIT_WORK(&ent->work, cache_work_func); |
669 | INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); | |
e126ba97 | 670 | queue_work(cache->wq, &ent->work); |
49780d42 | 671 | |
81713d37 AK |
672 | if (i > MAX_UMR_CACHE_ENTRY) { |
673 | mlx5_odp_init_mr_cache_entry(ent); | |
49780d42 | 674 | continue; |
81713d37 | 675 | } |
49780d42 AK |
676 | |
677 | if (!use_umr(dev, ent->order)) | |
678 | continue; | |
679 | ||
680 | ent->page = PAGE_SHIFT; | |
681 | ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) / | |
682 | MLX5_IB_UMR_OCTOWORD; | |
683 | ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; | |
684 | if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) && | |
685 | mlx5_core_is_pf(dev->mdev)) | |
686 | ent->limit = dev->mdev->profile->mr_cache[i].limit; | |
687 | else | |
688 | ent->limit = 0; | |
e126ba97 EC |
689 | } |
690 | ||
691 | err = mlx5_mr_cache_debugfs_init(dev); | |
692 | if (err) | |
693 | mlx5_ib_warn(dev, "cache debugfs failure\n"); | |
694 | ||
695 | return 0; | |
696 | } | |
697 | ||
acbda523 EC |
698 | static void wait_for_async_commands(struct mlx5_ib_dev *dev) |
699 | { | |
700 | struct mlx5_mr_cache *cache = &dev->cache; | |
701 | struct mlx5_cache_ent *ent; | |
702 | int total = 0; | |
703 | int i; | |
704 | int j; | |
705 | ||
706 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
707 | ent = &cache->ent[i]; | |
708 | for (j = 0 ; j < 1000; j++) { | |
709 | if (!ent->pending) | |
710 | break; | |
711 | msleep(50); | |
712 | } | |
713 | } | |
714 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
715 | ent = &cache->ent[i]; | |
716 | total += ent->pending; | |
717 | } | |
718 | ||
719 | if (total) | |
720 | mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total); | |
721 | else | |
722 | mlx5_ib_warn(dev, "done with all pending requests\n"); | |
723 | } | |
724 | ||
e126ba97 EC |
725 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) |
726 | { | |
727 | int i; | |
728 | ||
729 | dev->cache.stopped = 1; | |
3c461911 | 730 | flush_workqueue(dev->cache.wq); |
e126ba97 EC |
731 | |
732 | mlx5_mr_cache_debugfs_cleanup(dev); | |
733 | ||
734 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) | |
735 | clean_keys(dev, i); | |
736 | ||
3c461911 | 737 | destroy_workqueue(dev->cache.wq); |
acbda523 | 738 | wait_for_async_commands(dev); |
746b5583 | 739 | del_timer_sync(&dev->delay_timer); |
3c461911 | 740 | |
e126ba97 EC |
741 | return 0; |
742 | } | |
743 | ||
744 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) | |
745 | { | |
746 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 747 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
9603b61d | 748 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 | 749 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
750 | void *mkc; |
751 | u32 *in; | |
e126ba97 EC |
752 | int err; |
753 | ||
754 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
755 | if (!mr) | |
756 | return ERR_PTR(-ENOMEM); | |
757 | ||
ec22eb53 | 758 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
759 | if (!in) { |
760 | err = -ENOMEM; | |
761 | goto err_free; | |
762 | } | |
763 | ||
ec22eb53 SM |
764 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
765 | ||
766 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_PA); | |
767 | MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); | |
768 | MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); | |
769 | MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); | |
770 | MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); | |
771 | MLX5_SET(mkc, mkc, lr, 1); | |
e126ba97 | 772 | |
ec22eb53 SM |
773 | MLX5_SET(mkc, mkc, length64, 1); |
774 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
775 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
776 | MLX5_SET64(mkc, mkc, start_addr, 0); | |
777 | ||
778 | err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
779 | if (err) |
780 | goto err_in; | |
781 | ||
782 | kfree(in); | |
aa8e08d2 | 783 | mr->mmkey.type = MLX5_MKEY_MR; |
a606b0f6 MB |
784 | mr->ibmr.lkey = mr->mmkey.key; |
785 | mr->ibmr.rkey = mr->mmkey.key; | |
e126ba97 EC |
786 | mr->umem = NULL; |
787 | ||
788 | return &mr->ibmr; | |
789 | ||
790 | err_in: | |
791 | kfree(in); | |
792 | ||
793 | err_free: | |
794 | kfree(mr); | |
795 | ||
796 | return ERR_PTR(err); | |
797 | } | |
798 | ||
799 | static int get_octo_len(u64 addr, u64 len, int page_size) | |
800 | { | |
801 | u64 offset; | |
802 | int npages; | |
803 | ||
804 | offset = addr & (page_size - 1); | |
805 | npages = ALIGN(len + offset, page_size) >> ilog2(page_size); | |
806 | return (npages + 1) / 2; | |
807 | } | |
808 | ||
7d0cc6ed | 809 | static int use_umr(struct mlx5_ib_dev *dev, int order) |
e126ba97 | 810 | { |
7d0cc6ed | 811 | if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) |
49780d42 | 812 | return order <= MAX_UMR_CACHE_ENTRY + 2; |
cc149f75 | 813 | return order <= MLX5_MAX_UMR_SHIFT; |
e126ba97 EC |
814 | } |
815 | ||
14ab8896 AB |
816 | static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length, |
817 | int access_flags, struct ib_umem **umem, | |
818 | int *npages, int *page_shift, int *ncont, | |
819 | int *order) | |
395a8e4c NO |
820 | { |
821 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
14ab8896 AB |
822 | int err; |
823 | ||
824 | *umem = ib_umem_get(pd->uobject->context, start, length, | |
825 | access_flags, 0); | |
826 | err = PTR_ERR_OR_ZERO(*umem); | |
827 | if (err < 0) { | |
395a8e4c | 828 | mlx5_ib_err(dev, "umem get failed (%ld)\n", PTR_ERR(umem)); |
14ab8896 | 829 | return err; |
395a8e4c NO |
830 | } |
831 | ||
14ab8896 | 832 | mlx5_ib_cont_pages(*umem, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages, |
762f899a | 833 | page_shift, ncont, order); |
395a8e4c NO |
834 | if (!*npages) { |
835 | mlx5_ib_warn(dev, "avoid zero region\n"); | |
14ab8896 AB |
836 | ib_umem_release(*umem); |
837 | return -EINVAL; | |
395a8e4c NO |
838 | } |
839 | ||
840 | mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", | |
841 | *npages, *ncont, *order, *page_shift); | |
842 | ||
14ab8896 | 843 | return 0; |
395a8e4c NO |
844 | } |
845 | ||
add08d76 | 846 | static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc) |
e126ba97 | 847 | { |
add08d76 CH |
848 | struct mlx5_ib_umr_context *context = |
849 | container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe); | |
e126ba97 | 850 | |
add08d76 CH |
851 | context->status = wc->status; |
852 | complete(&context->done); | |
853 | } | |
e126ba97 | 854 | |
add08d76 CH |
855 | static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) |
856 | { | |
857 | context->cqe.done = mlx5_ib_umr_done; | |
858 | context->status = -1; | |
859 | init_completion(&context->done); | |
e126ba97 EC |
860 | } |
861 | ||
d5ea2df9 BJ |
862 | static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev, |
863 | struct mlx5_umr_wr *umrwr) | |
864 | { | |
865 | struct umr_common *umrc = &dev->umrc; | |
866 | struct ib_send_wr *bad; | |
867 | int err; | |
868 | struct mlx5_ib_umr_context umr_context; | |
869 | ||
870 | mlx5_ib_init_umr_context(&umr_context); | |
871 | umrwr->wr.wr_cqe = &umr_context.cqe; | |
872 | ||
873 | down(&umrc->sem); | |
874 | err = ib_post_send(umrc->qp, &umrwr->wr, &bad); | |
875 | if (err) { | |
876 | mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err); | |
877 | } else { | |
878 | wait_for_completion(&umr_context.done); | |
879 | if (umr_context.status != IB_WC_SUCCESS) { | |
880 | mlx5_ib_warn(dev, "reg umr failed (%u)\n", | |
881 | umr_context.status); | |
882 | err = -EFAULT; | |
883 | } | |
884 | } | |
885 | up(&umrc->sem); | |
886 | return err; | |
887 | } | |
888 | ||
e126ba97 EC |
889 | static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem, |
890 | u64 virt_addr, u64 len, int npages, | |
891 | int page_shift, int order, int access_flags) | |
892 | { | |
893 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 894 | struct mlx5_ib_mr *mr; |
096f7e72 | 895 | int err = 0; |
e126ba97 EC |
896 | int i; |
897 | ||
746b5583 | 898 | for (i = 0; i < 1; i++) { |
e126ba97 EC |
899 | mr = alloc_cached_mr(dev, order); |
900 | if (mr) | |
901 | break; | |
902 | ||
903 | err = add_keys(dev, order2idx(dev, order), 1); | |
746b5583 EC |
904 | if (err && err != -EAGAIN) { |
905 | mlx5_ib_warn(dev, "add_keys failed, err %d\n", err); | |
e126ba97 EC |
906 | break; |
907 | } | |
908 | } | |
909 | ||
910 | if (!mr) | |
911 | return ERR_PTR(-EAGAIN); | |
912 | ||
7d0cc6ed AK |
913 | mr->ibmr.pd = pd; |
914 | mr->umem = umem; | |
915 | mr->access_flags = access_flags; | |
916 | mr->desc_size = sizeof(struct mlx5_mtt); | |
a606b0f6 MB |
917 | mr->mmkey.iova = virt_addr; |
918 | mr->mmkey.size = len; | |
919 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
b475598a | 920 | |
7d0cc6ed AK |
921 | err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, |
922 | MLX5_IB_UPD_XLT_ENABLE); | |
096f7e72 | 923 | |
096f7e72 | 924 | if (err) { |
49780d42 | 925 | mlx5_mr_cache_free(dev, mr); |
096f7e72 | 926 | return ERR_PTR(err); |
e126ba97 EC |
927 | } |
928 | ||
7d0cc6ed AK |
929 | mr->live = 1; |
930 | ||
e126ba97 | 931 | return mr; |
e126ba97 EC |
932 | } |
933 | ||
7d0cc6ed AK |
934 | static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages, |
935 | void *xlt, int page_shift, size_t size, | |
936 | int flags) | |
832a6b06 HE |
937 | { |
938 | struct mlx5_ib_dev *dev = mr->dev; | |
832a6b06 | 939 | struct ib_umem *umem = mr->umem; |
81713d37 AK |
940 | if (flags & MLX5_IB_UPD_XLT_INDIRECT) { |
941 | mlx5_odp_populate_klm(xlt, idx, npages, mr, flags); | |
942 | return npages; | |
943 | } | |
7d0cc6ed AK |
944 | |
945 | npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx); | |
946 | ||
947 | if (!(flags & MLX5_IB_UPD_XLT_ZAP)) { | |
948 | __mlx5_ib_populate_pas(dev, umem, page_shift, | |
949 | idx, npages, xlt, | |
950 | MLX5_IB_MTT_PRESENT); | |
951 | /* Clear padding after the pages | |
952 | * brought from the umem. | |
953 | */ | |
954 | memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0, | |
955 | size - npages * sizeof(struct mlx5_mtt)); | |
956 | } | |
957 | ||
958 | return npages; | |
959 | } | |
960 | ||
961 | #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \ | |
962 | MLX5_UMR_MTT_ALIGNMENT) | |
963 | #define MLX5_SPARE_UMR_CHUNK 0x10000 | |
964 | ||
965 | int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, | |
966 | int page_shift, int flags) | |
967 | { | |
968 | struct mlx5_ib_dev *dev = mr->dev; | |
969 | struct device *ddev = dev->ib_dev.dma_device; | |
970 | struct mlx5_ib_ucontext *uctx = NULL; | |
832a6b06 | 971 | int size; |
7d0cc6ed | 972 | void *xlt; |
832a6b06 | 973 | dma_addr_t dma; |
e622f2f4 | 974 | struct mlx5_umr_wr wr; |
832a6b06 HE |
975 | struct ib_sge sg; |
976 | int err = 0; | |
81713d37 AK |
977 | int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT) |
978 | ? sizeof(struct mlx5_klm) | |
979 | : sizeof(struct mlx5_mtt); | |
7d0cc6ed AK |
980 | const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size; |
981 | const int page_mask = page_align - 1; | |
832a6b06 HE |
982 | size_t pages_mapped = 0; |
983 | size_t pages_to_map = 0; | |
984 | size_t pages_iter = 0; | |
7d0cc6ed | 985 | gfp_t gfp; |
832a6b06 HE |
986 | |
987 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, | |
7d0cc6ed AK |
988 | * so we need to align the offset and length accordingly |
989 | */ | |
990 | if (idx & page_mask) { | |
991 | npages += idx & page_mask; | |
992 | idx &= ~page_mask; | |
832a6b06 HE |
993 | } |
994 | ||
7d0cc6ed AK |
995 | gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL; |
996 | gfp |= __GFP_ZERO | __GFP_NOWARN; | |
832a6b06 | 997 | |
7d0cc6ed AK |
998 | pages_to_map = ALIGN(npages, page_align); |
999 | size = desc_size * pages_to_map; | |
1000 | size = min_t(int, size, MLX5_MAX_UMR_CHUNK); | |
832a6b06 | 1001 | |
7d0cc6ed AK |
1002 | xlt = (void *)__get_free_pages(gfp, get_order(size)); |
1003 | if (!xlt && size > MLX5_SPARE_UMR_CHUNK) { | |
1004 | mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n", | |
1005 | size, get_order(size), MLX5_SPARE_UMR_CHUNK); | |
1006 | ||
1007 | size = MLX5_SPARE_UMR_CHUNK; | |
1008 | xlt = (void *)__get_free_pages(gfp, get_order(size)); | |
832a6b06 | 1009 | } |
7d0cc6ed AK |
1010 | |
1011 | if (!xlt) { | |
1012 | uctx = to_mucontext(mr->ibmr.uobject->context); | |
1013 | mlx5_ib_warn(dev, "Using XLT emergency buffer\n"); | |
1014 | size = PAGE_SIZE; | |
1015 | xlt = (void *)uctx->upd_xlt_page; | |
1016 | mutex_lock(&uctx->upd_xlt_page_mutex); | |
1017 | memset(xlt, 0, size); | |
1018 | } | |
1019 | pages_iter = size / desc_size; | |
1020 | dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE); | |
832a6b06 | 1021 | if (dma_mapping_error(ddev, dma)) { |
7d0cc6ed | 1022 | mlx5_ib_err(dev, "unable to map DMA during XLT update.\n"); |
832a6b06 | 1023 | err = -ENOMEM; |
7d0cc6ed | 1024 | goto free_xlt; |
832a6b06 HE |
1025 | } |
1026 | ||
7d0cc6ed AK |
1027 | sg.addr = dma; |
1028 | sg.lkey = dev->umrc.pd->local_dma_lkey; | |
1029 | ||
1030 | memset(&wr, 0, sizeof(wr)); | |
1031 | wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT; | |
1032 | if (!(flags & MLX5_IB_UPD_XLT_ENABLE)) | |
1033 | wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
1034 | wr.wr.sg_list = &sg; | |
1035 | wr.wr.num_sge = 1; | |
1036 | wr.wr.opcode = MLX5_IB_WR_UMR; | |
1037 | ||
1038 | wr.pd = mr->ibmr.pd; | |
1039 | wr.mkey = mr->mmkey.key; | |
1040 | wr.length = mr->mmkey.size; | |
1041 | wr.virt_addr = mr->mmkey.iova; | |
1042 | wr.access_flags = mr->access_flags; | |
1043 | wr.page_shift = page_shift; | |
1044 | ||
832a6b06 HE |
1045 | for (pages_mapped = 0; |
1046 | pages_mapped < pages_to_map && !err; | |
7d0cc6ed | 1047 | pages_mapped += pages_iter, idx += pages_iter) { |
832a6b06 | 1048 | dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE); |
7d0cc6ed AK |
1049 | npages = populate_xlt(mr, idx, pages_iter, xlt, |
1050 | page_shift, size, flags); | |
832a6b06 HE |
1051 | |
1052 | dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE); | |
1053 | ||
7d0cc6ed AK |
1054 | sg.length = ALIGN(npages * desc_size, |
1055 | MLX5_UMR_MTT_ALIGNMENT); | |
1056 | ||
1057 | if (pages_mapped + pages_iter >= pages_to_map) { | |
1058 | if (flags & MLX5_IB_UPD_XLT_ENABLE) | |
1059 | wr.wr.send_flags |= | |
1060 | MLX5_IB_SEND_UMR_ENABLE_MR | | |
1061 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS | | |
1062 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1063 | if (flags & MLX5_IB_UPD_XLT_PD || | |
1064 | flags & MLX5_IB_UPD_XLT_ACCESS) | |
1065 | wr.wr.send_flags |= | |
1066 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; | |
1067 | if (flags & MLX5_IB_UPD_XLT_ADDR) | |
1068 | wr.wr.send_flags |= | |
1069 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1070 | } | |
832a6b06 | 1071 | |
7d0cc6ed | 1072 | wr.offset = idx * desc_size; |
31616255 | 1073 | wr.xlt_size = sg.length; |
832a6b06 | 1074 | |
d5ea2df9 | 1075 | err = mlx5_ib_post_send_wait(dev, &wr); |
832a6b06 HE |
1076 | } |
1077 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); | |
1078 | ||
7d0cc6ed AK |
1079 | free_xlt: |
1080 | if (uctx) | |
1081 | mutex_unlock(&uctx->upd_xlt_page_mutex); | |
832a6b06 | 1082 | else |
7d0cc6ed | 1083 | free_pages((unsigned long)xlt, get_order(size)); |
832a6b06 HE |
1084 | |
1085 | return err; | |
1086 | } | |
832a6b06 | 1087 | |
395a8e4c NO |
1088 | /* |
1089 | * If ibmr is NULL it will be allocated by reg_create. | |
1090 | * Else, the given ibmr will be used. | |
1091 | */ | |
1092 | static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd, | |
1093 | u64 virt_addr, u64 length, | |
1094 | struct ib_umem *umem, int npages, | |
1095 | int page_shift, int access_flags) | |
e126ba97 EC |
1096 | { |
1097 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 1098 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
1099 | __be64 *pas; |
1100 | void *mkc; | |
e126ba97 | 1101 | int inlen; |
ec22eb53 | 1102 | u32 *in; |
e126ba97 | 1103 | int err; |
938fe83c | 1104 | bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)); |
e126ba97 | 1105 | |
395a8e4c | 1106 | mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL); |
e126ba97 EC |
1107 | if (!mr) |
1108 | return ERR_PTR(-ENOMEM); | |
1109 | ||
ec22eb53 SM |
1110 | inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + |
1111 | sizeof(*pas) * ((npages + 1) / 2) * 2; | |
e126ba97 EC |
1112 | in = mlx5_vzalloc(inlen); |
1113 | if (!in) { | |
1114 | err = -ENOMEM; | |
1115 | goto err_1; | |
1116 | } | |
ec22eb53 | 1117 | pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); |
c438fde1 AK |
1118 | if (!(access_flags & IB_ACCESS_ON_DEMAND)) |
1119 | mlx5_ib_populate_pas(dev, umem, page_shift, pas, | |
1120 | pg_cap ? MLX5_IB_MTT_PRESENT : 0); | |
e126ba97 | 1121 | |
ec22eb53 | 1122 | /* The pg_access bit allows setting the access flags |
cc149f75 | 1123 | * in the page list submitted with the command. */ |
ec22eb53 SM |
1124 | MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap)); |
1125 | ||
1126 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
1127 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT); | |
1128 | MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); | |
1129 | MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); | |
1130 | MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); | |
1131 | MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); | |
1132 | MLX5_SET(mkc, mkc, lr, 1); | |
1133 | ||
1134 | MLX5_SET64(mkc, mkc, start_addr, virt_addr); | |
1135 | MLX5_SET64(mkc, mkc, len, length); | |
1136 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1137 | MLX5_SET(mkc, mkc, bsf_octword_size, 0); | |
1138 | MLX5_SET(mkc, mkc, translations_octword_size, | |
1139 | get_octo_len(virt_addr, length, 1 << page_shift)); | |
1140 | MLX5_SET(mkc, mkc, log_page_size, page_shift); | |
1141 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1142 | MLX5_SET(create_mkey_in, in, translations_octword_actual_size, | |
1143 | get_octo_len(virt_addr, length, 1 << page_shift)); | |
1144 | ||
1145 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
1146 | if (err) { |
1147 | mlx5_ib_warn(dev, "create mkey failed\n"); | |
1148 | goto err_2; | |
1149 | } | |
aa8e08d2 | 1150 | mr->mmkey.type = MLX5_MKEY_MR; |
49780d42 | 1151 | mr->desc_size = sizeof(struct mlx5_mtt); |
e126ba97 | 1152 | mr->umem = umem; |
7eae20db | 1153 | mr->dev = dev; |
b4cfe447 | 1154 | mr->live = 1; |
479163f4 | 1155 | kvfree(in); |
e126ba97 | 1156 | |
a606b0f6 | 1157 | mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1158 | |
1159 | return mr; | |
1160 | ||
1161 | err_2: | |
479163f4 | 1162 | kvfree(in); |
e126ba97 EC |
1163 | |
1164 | err_1: | |
395a8e4c NO |
1165 | if (!ibmr) |
1166 | kfree(mr); | |
e126ba97 EC |
1167 | |
1168 | return ERR_PTR(err); | |
1169 | } | |
1170 | ||
395a8e4c NO |
1171 | static void set_mr_fileds(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr, |
1172 | int npages, u64 length, int access_flags) | |
1173 | { | |
1174 | mr->npages = npages; | |
1175 | atomic_add(npages, &dev->mdev->priv.reg_pages); | |
a606b0f6 MB |
1176 | mr->ibmr.lkey = mr->mmkey.key; |
1177 | mr->ibmr.rkey = mr->mmkey.key; | |
395a8e4c | 1178 | mr->ibmr.length = length; |
56e11d62 | 1179 | mr->access_flags = access_flags; |
395a8e4c NO |
1180 | } |
1181 | ||
e126ba97 EC |
1182 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, |
1183 | u64 virt_addr, int access_flags, | |
1184 | struct ib_udata *udata) | |
1185 | { | |
1186 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1187 | struct mlx5_ib_mr *mr = NULL; | |
1188 | struct ib_umem *umem; | |
1189 | int page_shift; | |
1190 | int npages; | |
1191 | int ncont; | |
1192 | int order; | |
1193 | int err; | |
1194 | ||
900a6d79 EC |
1195 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", |
1196 | start, virt_addr, length, access_flags); | |
81713d37 AK |
1197 | |
1198 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1199 | if (!start && length == U64_MAX) { | |
1200 | if (!(access_flags & IB_ACCESS_ON_DEMAND) || | |
1201 | !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) | |
1202 | return ERR_PTR(-EINVAL); | |
1203 | ||
1204 | mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags); | |
1205 | return &mr->ibmr; | |
1206 | } | |
1207 | #endif | |
1208 | ||
14ab8896 | 1209 | err = mr_umem_get(pd, start, length, access_flags, &umem, &npages, |
395a8e4c | 1210 | &page_shift, &ncont, &order); |
e126ba97 | 1211 | |
14ab8896 AB |
1212 | if (err < 0) |
1213 | return ERR_PTR(err); | |
e126ba97 | 1214 | |
7d0cc6ed | 1215 | if (use_umr(dev, order)) { |
e126ba97 EC |
1216 | mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift, |
1217 | order, access_flags); | |
1218 | if (PTR_ERR(mr) == -EAGAIN) { | |
1219 | mlx5_ib_dbg(dev, "cache empty for order %d", order); | |
1220 | mr = NULL; | |
1221 | } | |
c438fde1 AK |
1222 | } else if (access_flags & IB_ACCESS_ON_DEMAND && |
1223 | !MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) { | |
6aec21f6 HE |
1224 | err = -EINVAL; |
1225 | pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB"); | |
1226 | goto error; | |
e126ba97 EC |
1227 | } |
1228 | ||
6bc1a656 ML |
1229 | if (!mr) { |
1230 | mutex_lock(&dev->slow_path_mutex); | |
395a8e4c NO |
1231 | mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, |
1232 | page_shift, access_flags); | |
6bc1a656 ML |
1233 | mutex_unlock(&dev->slow_path_mutex); |
1234 | } | |
e126ba97 EC |
1235 | |
1236 | if (IS_ERR(mr)) { | |
1237 | err = PTR_ERR(mr); | |
1238 | goto error; | |
1239 | } | |
1240 | ||
a606b0f6 | 1241 | mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1242 | |
1243 | mr->umem = umem; | |
395a8e4c | 1244 | set_mr_fileds(dev, mr, npages, length, access_flags); |
e126ba97 | 1245 | |
b4cfe447 | 1246 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
395a8e4c | 1247 | update_odp_mr(mr); |
b4cfe447 HE |
1248 | #endif |
1249 | ||
e126ba97 EC |
1250 | return &mr->ibmr; |
1251 | ||
1252 | error: | |
1253 | ib_umem_release(umem); | |
1254 | return ERR_PTR(err); | |
1255 | } | |
1256 | ||
1257 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) | |
1258 | { | |
89ea94a7 | 1259 | struct mlx5_core_dev *mdev = dev->mdev; |
0025b0bd | 1260 | struct mlx5_umr_wr umrwr = {}; |
e126ba97 | 1261 | |
89ea94a7 MG |
1262 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) |
1263 | return 0; | |
1264 | ||
7d0cc6ed AK |
1265 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR | |
1266 | MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
1267 | umrwr.wr.opcode = MLX5_IB_WR_UMR; | |
1268 | umrwr.mkey = mr->mmkey.key; | |
e126ba97 | 1269 | |
d5ea2df9 | 1270 | return mlx5_ib_post_send_wait(dev, &umrwr); |
e126ba97 EC |
1271 | } |
1272 | ||
7d0cc6ed | 1273 | static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, |
56e11d62 NO |
1274 | int access_flags, int flags) |
1275 | { | |
1276 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
56e11d62 | 1277 | struct mlx5_umr_wr umrwr = {}; |
56e11d62 NO |
1278 | int err; |
1279 | ||
56e11d62 NO |
1280 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE; |
1281 | ||
7d0cc6ed AK |
1282 | umrwr.wr.opcode = MLX5_IB_WR_UMR; |
1283 | umrwr.mkey = mr->mmkey.key; | |
56e11d62 | 1284 | |
31616255 | 1285 | if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) { |
56e11d62 | 1286 | umrwr.pd = pd; |
56e11d62 | 1287 | umrwr.access_flags = access_flags; |
31616255 | 1288 | umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; |
56e11d62 NO |
1289 | } |
1290 | ||
d5ea2df9 | 1291 | err = mlx5_ib_post_send_wait(dev, &umrwr); |
56e11d62 | 1292 | |
56e11d62 NO |
1293 | return err; |
1294 | } | |
1295 | ||
1296 | int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, | |
1297 | u64 length, u64 virt_addr, int new_access_flags, | |
1298 | struct ib_pd *new_pd, struct ib_udata *udata) | |
1299 | { | |
1300 | struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); | |
1301 | struct mlx5_ib_mr *mr = to_mmr(ib_mr); | |
1302 | struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd; | |
1303 | int access_flags = flags & IB_MR_REREG_ACCESS ? | |
1304 | new_access_flags : | |
1305 | mr->access_flags; | |
1306 | u64 addr = (flags & IB_MR_REREG_TRANS) ? virt_addr : mr->umem->address; | |
1307 | u64 len = (flags & IB_MR_REREG_TRANS) ? length : mr->umem->length; | |
1308 | int page_shift = 0; | |
7d0cc6ed | 1309 | int upd_flags = 0; |
56e11d62 NO |
1310 | int npages = 0; |
1311 | int ncont = 0; | |
1312 | int order = 0; | |
1313 | int err; | |
1314 | ||
1315 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", | |
1316 | start, virt_addr, length, access_flags); | |
1317 | ||
7d0cc6ed AK |
1318 | atomic_sub(mr->npages, &dev->mdev->priv.reg_pages); |
1319 | ||
56e11d62 NO |
1320 | if (flags != IB_MR_REREG_PD) { |
1321 | /* | |
1322 | * Replace umem. This needs to be done whether or not UMR is | |
1323 | * used. | |
1324 | */ | |
1325 | flags |= IB_MR_REREG_TRANS; | |
1326 | ib_umem_release(mr->umem); | |
14ab8896 AB |
1327 | err = mr_umem_get(pd, addr, len, access_flags, &mr->umem, |
1328 | &npages, &page_shift, &ncont, &order); | |
1329 | if (err < 0) { | |
7d0cc6ed | 1330 | clean_mr(mr); |
56e11d62 NO |
1331 | return err; |
1332 | } | |
1333 | } | |
1334 | ||
1335 | if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) { | |
1336 | /* | |
1337 | * UMR can't be used - MKey needs to be replaced. | |
1338 | */ | |
1339 | if (mr->umred) { | |
1340 | err = unreg_umr(dev, mr); | |
1341 | if (err) | |
1342 | mlx5_ib_warn(dev, "Failed to unregister MR\n"); | |
1343 | } else { | |
1344 | err = destroy_mkey(dev, mr); | |
1345 | if (err) | |
1346 | mlx5_ib_warn(dev, "Failed to destroy MKey\n"); | |
1347 | } | |
1348 | if (err) | |
1349 | return err; | |
1350 | ||
1351 | mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont, | |
1352 | page_shift, access_flags); | |
1353 | ||
1354 | if (IS_ERR(mr)) | |
1355 | return PTR_ERR(mr); | |
1356 | ||
1357 | mr->umred = 0; | |
1358 | } else { | |
1359 | /* | |
1360 | * Send a UMR WQE | |
1361 | */ | |
7d0cc6ed AK |
1362 | mr->ibmr.pd = pd; |
1363 | mr->access_flags = access_flags; | |
1364 | mr->mmkey.iova = addr; | |
1365 | mr->mmkey.size = len; | |
1366 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
1367 | ||
1368 | if (flags & IB_MR_REREG_TRANS) { | |
1369 | upd_flags = MLX5_IB_UPD_XLT_ADDR; | |
1370 | if (flags & IB_MR_REREG_PD) | |
1371 | upd_flags |= MLX5_IB_UPD_XLT_PD; | |
1372 | if (flags & IB_MR_REREG_ACCESS) | |
1373 | upd_flags |= MLX5_IB_UPD_XLT_ACCESS; | |
1374 | err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, | |
1375 | upd_flags); | |
1376 | } else { | |
1377 | err = rereg_umr(pd, mr, access_flags, flags); | |
1378 | } | |
1379 | ||
56e11d62 NO |
1380 | if (err) { |
1381 | mlx5_ib_warn(dev, "Failed to rereg UMR\n"); | |
7d0cc6ed AK |
1382 | ib_umem_release(mr->umem); |
1383 | clean_mr(mr); | |
56e11d62 NO |
1384 | return err; |
1385 | } | |
1386 | } | |
1387 | ||
7d0cc6ed | 1388 | set_mr_fileds(dev, mr, npages, len, access_flags); |
56e11d62 | 1389 | |
56e11d62 NO |
1390 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1391 | update_odp_mr(mr); | |
1392 | #endif | |
56e11d62 NO |
1393 | return 0; |
1394 | } | |
1395 | ||
8a187ee5 SG |
1396 | static int |
1397 | mlx5_alloc_priv_descs(struct ib_device *device, | |
1398 | struct mlx5_ib_mr *mr, | |
1399 | int ndescs, | |
1400 | int desc_size) | |
1401 | { | |
1402 | int size = ndescs * desc_size; | |
1403 | int add_size; | |
1404 | int ret; | |
1405 | ||
1406 | add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0); | |
1407 | ||
1408 | mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL); | |
1409 | if (!mr->descs_alloc) | |
1410 | return -ENOMEM; | |
1411 | ||
1412 | mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN); | |
1413 | ||
1414 | mr->desc_map = dma_map_single(device->dma_device, mr->descs, | |
1415 | size, DMA_TO_DEVICE); | |
1416 | if (dma_mapping_error(device->dma_device, mr->desc_map)) { | |
1417 | ret = -ENOMEM; | |
1418 | goto err; | |
1419 | } | |
1420 | ||
1421 | return 0; | |
1422 | err: | |
1423 | kfree(mr->descs_alloc); | |
1424 | ||
1425 | return ret; | |
1426 | } | |
1427 | ||
1428 | static void | |
1429 | mlx5_free_priv_descs(struct mlx5_ib_mr *mr) | |
1430 | { | |
1431 | if (mr->descs) { | |
1432 | struct ib_device *device = mr->ibmr.device; | |
1433 | int size = mr->max_descs * mr->desc_size; | |
1434 | ||
1435 | dma_unmap_single(device->dma_device, mr->desc_map, | |
1436 | size, DMA_TO_DEVICE); | |
1437 | kfree(mr->descs_alloc); | |
1438 | mr->descs = NULL; | |
1439 | } | |
1440 | } | |
1441 | ||
6aec21f6 | 1442 | static int clean_mr(struct mlx5_ib_mr *mr) |
e126ba97 | 1443 | { |
6aec21f6 | 1444 | struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); |
e126ba97 EC |
1445 | int umred = mr->umred; |
1446 | int err; | |
1447 | ||
8b91ffc1 SG |
1448 | if (mr->sig) { |
1449 | if (mlx5_core_destroy_psv(dev->mdev, | |
1450 | mr->sig->psv_memory.psv_idx)) | |
1451 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1452 | mr->sig->psv_memory.psv_idx); | |
1453 | if (mlx5_core_destroy_psv(dev->mdev, | |
1454 | mr->sig->psv_wire.psv_idx)) | |
1455 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1456 | mr->sig->psv_wire.psv_idx); | |
1457 | kfree(mr->sig); | |
1458 | mr->sig = NULL; | |
1459 | } | |
1460 | ||
8a187ee5 SG |
1461 | mlx5_free_priv_descs(mr); |
1462 | ||
e126ba97 | 1463 | if (!umred) { |
b4cfe447 | 1464 | err = destroy_mkey(dev, mr); |
e126ba97 EC |
1465 | if (err) { |
1466 | mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n", | |
a606b0f6 | 1467 | mr->mmkey.key, err); |
e126ba97 EC |
1468 | return err; |
1469 | } | |
1470 | } else { | |
49780d42 | 1471 | mlx5_mr_cache_free(dev, mr); |
e126ba97 EC |
1472 | } |
1473 | ||
6aec21f6 HE |
1474 | if (!umred) |
1475 | kfree(mr); | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr) | |
1481 | { | |
1482 | struct mlx5_ib_dev *dev = to_mdev(ibmr->device); | |
1483 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1484 | int npages = mr->npages; | |
1485 | struct ib_umem *umem = mr->umem; | |
1486 | ||
1487 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
b4cfe447 HE |
1488 | if (umem && umem->odp_data) { |
1489 | /* Prevent new page faults from succeeding */ | |
1490 | mr->live = 0; | |
6aec21f6 HE |
1491 | /* Wait for all running page-fault handlers to finish. */ |
1492 | synchronize_srcu(&dev->mr_srcu); | |
b4cfe447 | 1493 | /* Destroy all page mappings */ |
81713d37 AK |
1494 | if (umem->odp_data->page_list) |
1495 | mlx5_ib_invalidate_range(umem, ib_umem_start(umem), | |
1496 | ib_umem_end(umem)); | |
1497 | else | |
1498 | mlx5_ib_free_implicit_mr(mr); | |
b4cfe447 HE |
1499 | /* |
1500 | * We kill the umem before the MR for ODP, | |
1501 | * so that there will not be any invalidations in | |
1502 | * flight, looking at the *mr struct. | |
1503 | */ | |
1504 | ib_umem_release(umem); | |
1505 | atomic_sub(npages, &dev->mdev->priv.reg_pages); | |
1506 | ||
1507 | /* Avoid double-freeing the umem. */ | |
1508 | umem = NULL; | |
1509 | } | |
6aec21f6 HE |
1510 | #endif |
1511 | ||
1512 | clean_mr(mr); | |
1513 | ||
e126ba97 EC |
1514 | if (umem) { |
1515 | ib_umem_release(umem); | |
6aec21f6 | 1516 | atomic_sub(npages, &dev->mdev->priv.reg_pages); |
e126ba97 EC |
1517 | } |
1518 | ||
e126ba97 EC |
1519 | return 0; |
1520 | } | |
1521 | ||
9bee178b SG |
1522 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, |
1523 | enum ib_mr_type mr_type, | |
1524 | u32 max_num_sg) | |
3121e3c4 SG |
1525 | { |
1526 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1527 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
b005d316 | 1528 | int ndescs = ALIGN(max_num_sg, 4); |
ec22eb53 SM |
1529 | struct mlx5_ib_mr *mr; |
1530 | void *mkc; | |
1531 | u32 *in; | |
b005d316 | 1532 | int err; |
3121e3c4 SG |
1533 | |
1534 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1535 | if (!mr) | |
1536 | return ERR_PTR(-ENOMEM); | |
1537 | ||
ec22eb53 | 1538 | in = kzalloc(inlen, GFP_KERNEL); |
3121e3c4 SG |
1539 | if (!in) { |
1540 | err = -ENOMEM; | |
1541 | goto err_free; | |
1542 | } | |
1543 | ||
ec22eb53 SM |
1544 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1545 | MLX5_SET(mkc, mkc, free, 1); | |
1546 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1547 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1548 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
3121e3c4 | 1549 | |
9bee178b | 1550 | if (mr_type == IB_MR_TYPE_MEM_REG) { |
ec22eb53 SM |
1551 | mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT; |
1552 | MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); | |
8a187ee5 | 1553 | err = mlx5_alloc_priv_descs(pd->device, mr, |
31616255 | 1554 | ndescs, sizeof(struct mlx5_mtt)); |
8a187ee5 SG |
1555 | if (err) |
1556 | goto err_free_in; | |
1557 | ||
31616255 | 1558 | mr->desc_size = sizeof(struct mlx5_mtt); |
8a187ee5 | 1559 | mr->max_descs = ndescs; |
b005d316 | 1560 | } else if (mr_type == IB_MR_TYPE_SG_GAPS) { |
ec22eb53 | 1561 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
b005d316 SG |
1562 | |
1563 | err = mlx5_alloc_priv_descs(pd->device, mr, | |
1564 | ndescs, sizeof(struct mlx5_klm)); | |
1565 | if (err) | |
1566 | goto err_free_in; | |
1567 | mr->desc_size = sizeof(struct mlx5_klm); | |
1568 | mr->max_descs = ndescs; | |
9bee178b | 1569 | } else if (mr_type == IB_MR_TYPE_SIGNATURE) { |
3121e3c4 SG |
1570 | u32 psv_index[2]; |
1571 | ||
ec22eb53 SM |
1572 | MLX5_SET(mkc, mkc, bsf_en, 1); |
1573 | MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE); | |
3121e3c4 SG |
1574 | mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL); |
1575 | if (!mr->sig) { | |
1576 | err = -ENOMEM; | |
1577 | goto err_free_in; | |
1578 | } | |
1579 | ||
1580 | /* create mem & wire PSVs */ | |
9603b61d | 1581 | err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, |
3121e3c4 SG |
1582 | 2, psv_index); |
1583 | if (err) | |
1584 | goto err_free_sig; | |
1585 | ||
ec22eb53 | 1586 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
3121e3c4 SG |
1587 | mr->sig->psv_memory.psv_idx = psv_index[0]; |
1588 | mr->sig->psv_wire.psv_idx = psv_index[1]; | |
d5436ba0 SG |
1589 | |
1590 | mr->sig->sig_status_checked = true; | |
1591 | mr->sig->sig_err_exists = false; | |
1592 | /* Next UMR, Arm SIGERR */ | |
1593 | ++mr->sig->sigerr_count; | |
9bee178b SG |
1594 | } else { |
1595 | mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type); | |
1596 | err = -EINVAL; | |
1597 | goto err_free_in; | |
3121e3c4 SG |
1598 | } |
1599 | ||
ec22eb53 SM |
1600 | MLX5_SET(mkc, mkc, access_mode, mr->access_mode); |
1601 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1602 | ||
1603 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); | |
3121e3c4 SG |
1604 | if (err) |
1605 | goto err_destroy_psv; | |
1606 | ||
aa8e08d2 | 1607 | mr->mmkey.type = MLX5_MKEY_MR; |
a606b0f6 MB |
1608 | mr->ibmr.lkey = mr->mmkey.key; |
1609 | mr->ibmr.rkey = mr->mmkey.key; | |
3121e3c4 SG |
1610 | mr->umem = NULL; |
1611 | kfree(in); | |
1612 | ||
1613 | return &mr->ibmr; | |
1614 | ||
1615 | err_destroy_psv: | |
1616 | if (mr->sig) { | |
9603b61d | 1617 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1618 | mr->sig->psv_memory.psv_idx)) |
1619 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1620 | mr->sig->psv_memory.psv_idx); | |
9603b61d | 1621 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1622 | mr->sig->psv_wire.psv_idx)) |
1623 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1624 | mr->sig->psv_wire.psv_idx); | |
1625 | } | |
8a187ee5 | 1626 | mlx5_free_priv_descs(mr); |
3121e3c4 SG |
1627 | err_free_sig: |
1628 | kfree(mr->sig); | |
1629 | err_free_in: | |
1630 | kfree(in); | |
1631 | err_free: | |
1632 | kfree(mr); | |
1633 | return ERR_PTR(err); | |
1634 | } | |
1635 | ||
d2370e0a MB |
1636 | struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
1637 | struct ib_udata *udata) | |
1638 | { | |
1639 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1640 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
d2370e0a | 1641 | struct mlx5_ib_mw *mw = NULL; |
ec22eb53 SM |
1642 | u32 *in = NULL; |
1643 | void *mkc; | |
d2370e0a MB |
1644 | int ndescs; |
1645 | int err; | |
1646 | struct mlx5_ib_alloc_mw req = {}; | |
1647 | struct { | |
1648 | __u32 comp_mask; | |
1649 | __u32 response_length; | |
1650 | } resp = {}; | |
1651 | ||
1652 | err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); | |
1653 | if (err) | |
1654 | return ERR_PTR(err); | |
1655 | ||
1656 | if (req.comp_mask || req.reserved1 || req.reserved2) | |
1657 | return ERR_PTR(-EOPNOTSUPP); | |
1658 | ||
1659 | if (udata->inlen > sizeof(req) && | |
1660 | !ib_is_udata_cleared(udata, sizeof(req), | |
1661 | udata->inlen - sizeof(req))) | |
1662 | return ERR_PTR(-EOPNOTSUPP); | |
1663 | ||
1664 | ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4); | |
1665 | ||
1666 | mw = kzalloc(sizeof(*mw), GFP_KERNEL); | |
ec22eb53 | 1667 | in = kzalloc(inlen, GFP_KERNEL); |
d2370e0a MB |
1668 | if (!mw || !in) { |
1669 | err = -ENOMEM; | |
1670 | goto free; | |
1671 | } | |
1672 | ||
ec22eb53 SM |
1673 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1674 | ||
1675 | MLX5_SET(mkc, mkc, free, 1); | |
1676 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1677 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1678 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1679 | MLX5_SET(mkc, mkc, lr, 1); | |
1680 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_KLMS); | |
1681 | MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2))); | |
1682 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1683 | ||
1684 | err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen); | |
d2370e0a MB |
1685 | if (err) |
1686 | goto free; | |
1687 | ||
aa8e08d2 | 1688 | mw->mmkey.type = MLX5_MKEY_MW; |
d2370e0a MB |
1689 | mw->ibmw.rkey = mw->mmkey.key; |
1690 | ||
1691 | resp.response_length = min(offsetof(typeof(resp), response_length) + | |
1692 | sizeof(resp.response_length), udata->outlen); | |
1693 | if (resp.response_length) { | |
1694 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
1695 | if (err) { | |
1696 | mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey); | |
1697 | goto free; | |
1698 | } | |
1699 | } | |
1700 | ||
1701 | kfree(in); | |
1702 | return &mw->ibmw; | |
1703 | ||
1704 | free: | |
1705 | kfree(mw); | |
1706 | kfree(in); | |
1707 | return ERR_PTR(err); | |
1708 | } | |
1709 | ||
1710 | int mlx5_ib_dealloc_mw(struct ib_mw *mw) | |
1711 | { | |
1712 | struct mlx5_ib_mw *mmw = to_mmw(mw); | |
1713 | int err; | |
1714 | ||
1715 | err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev, | |
1716 | &mmw->mmkey); | |
1717 | if (!err) | |
1718 | kfree(mmw); | |
1719 | return err; | |
1720 | } | |
1721 | ||
d5436ba0 SG |
1722 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
1723 | struct ib_mr_status *mr_status) | |
1724 | { | |
1725 | struct mlx5_ib_mr *mmr = to_mmr(ibmr); | |
1726 | int ret = 0; | |
1727 | ||
1728 | if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { | |
1729 | pr_err("Invalid status check mask\n"); | |
1730 | ret = -EINVAL; | |
1731 | goto done; | |
1732 | } | |
1733 | ||
1734 | mr_status->fail_status = 0; | |
1735 | if (check_mask & IB_MR_CHECK_SIG_STATUS) { | |
1736 | if (!mmr->sig) { | |
1737 | ret = -EINVAL; | |
1738 | pr_err("signature status check requested on a non-signature enabled MR\n"); | |
1739 | goto done; | |
1740 | } | |
1741 | ||
1742 | mmr->sig->sig_status_checked = true; | |
1743 | if (!mmr->sig->sig_err_exists) | |
1744 | goto done; | |
1745 | ||
1746 | if (ibmr->lkey == mmr->sig->err_item.key) | |
1747 | memcpy(&mr_status->sig_err, &mmr->sig->err_item, | |
1748 | sizeof(mr_status->sig_err)); | |
1749 | else { | |
1750 | mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; | |
1751 | mr_status->sig_err.sig_err_offset = 0; | |
1752 | mr_status->sig_err.key = mmr->sig->err_item.key; | |
1753 | } | |
1754 | ||
1755 | mmr->sig->sig_err_exists = false; | |
1756 | mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; | |
1757 | } | |
1758 | ||
1759 | done: | |
1760 | return ret; | |
1761 | } | |
8a187ee5 | 1762 | |
b005d316 SG |
1763 | static int |
1764 | mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr, | |
1765 | struct scatterlist *sgl, | |
ff2ba993 | 1766 | unsigned short sg_nents, |
9aa8b321 | 1767 | unsigned int *sg_offset_p) |
b005d316 SG |
1768 | { |
1769 | struct scatterlist *sg = sgl; | |
1770 | struct mlx5_klm *klms = mr->descs; | |
9aa8b321 | 1771 | unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; |
b005d316 SG |
1772 | u32 lkey = mr->ibmr.pd->local_dma_lkey; |
1773 | int i; | |
1774 | ||
ff2ba993 | 1775 | mr->ibmr.iova = sg_dma_address(sg) + sg_offset; |
b005d316 SG |
1776 | mr->ibmr.length = 0; |
1777 | mr->ndescs = sg_nents; | |
1778 | ||
1779 | for_each_sg(sgl, sg, sg_nents, i) { | |
1780 | if (unlikely(i > mr->max_descs)) | |
1781 | break; | |
ff2ba993 CH |
1782 | klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset); |
1783 | klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset); | |
b005d316 SG |
1784 | klms[i].key = cpu_to_be32(lkey); |
1785 | mr->ibmr.length += sg_dma_len(sg); | |
ff2ba993 CH |
1786 | |
1787 | sg_offset = 0; | |
b005d316 SG |
1788 | } |
1789 | ||
9aa8b321 BVA |
1790 | if (sg_offset_p) |
1791 | *sg_offset_p = sg_offset; | |
1792 | ||
b005d316 SG |
1793 | return i; |
1794 | } | |
1795 | ||
8a187ee5 SG |
1796 | static int mlx5_set_page(struct ib_mr *ibmr, u64 addr) |
1797 | { | |
1798 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1799 | __be64 *descs; | |
1800 | ||
1801 | if (unlikely(mr->ndescs == mr->max_descs)) | |
1802 | return -ENOMEM; | |
1803 | ||
1804 | descs = mr->descs; | |
1805 | descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); | |
1806 | ||
1807 | return 0; | |
1808 | } | |
1809 | ||
ff2ba993 | 1810 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 1811 | unsigned int *sg_offset) |
8a187ee5 SG |
1812 | { |
1813 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1814 | int n; | |
1815 | ||
1816 | mr->ndescs = 0; | |
1817 | ||
1818 | ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map, | |
1819 | mr->desc_size * mr->max_descs, | |
1820 | DMA_TO_DEVICE); | |
1821 | ||
ec22eb53 | 1822 | if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) |
ff2ba993 | 1823 | n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset); |
b005d316 | 1824 | else |
ff2ba993 CH |
1825 | n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, |
1826 | mlx5_set_page); | |
8a187ee5 SG |
1827 | |
1828 | ib_dma_sync_single_for_device(ibmr->device, mr->desc_map, | |
1829 | mr->desc_size * mr->max_descs, | |
1830 | DMA_TO_DEVICE); | |
1831 | ||
1832 | return n; | |
1833 | } |