Commit | Line | Data |
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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_IB_H | |
34 | #define MLX5_IB_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/sched.h> | |
38 | #include <rdma/ib_verbs.h> | |
39 | #include <rdma/ib_smi.h> | |
40 | #include <linux/mlx5/driver.h> | |
41 | #include <linux/mlx5/cq.h> | |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/srq.h> | |
44 | #include <linux/types.h> | |
146d2f1a | 45 | #include <linux/mlx5/transobj.h> |
d2370e0a | 46 | #include <rdma/ib_user_verbs.h> |
3085e29e | 47 | #include <rdma/mlx5-abi.h> |
e126ba97 EC |
48 | |
49 | #define mlx5_ib_dbg(dev, format, arg...) \ | |
50 | pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ | |
51 | __LINE__, current->pid, ##arg) | |
52 | ||
53 | #define mlx5_ib_err(dev, format, arg...) \ | |
54 | pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ | |
55 | __LINE__, current->pid, ##arg) | |
56 | ||
57 | #define mlx5_ib_warn(dev, format, arg...) \ | |
58 | pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ | |
59 | __LINE__, current->pid, ##arg) | |
60 | ||
b368d7cb MB |
61 | #define field_avail(type, fld, sz) (offsetof(type, fld) + \ |
62 | sizeof(((type *)0)->fld) <= (sz)) | |
cfb5e088 HA |
63 | #define MLX5_IB_DEFAULT_UIDX 0xffffff |
64 | #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) | |
b368d7cb | 65 | |
762f899a MD |
66 | #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) |
67 | ||
e126ba97 EC |
68 | enum { |
69 | MLX5_IB_MMAP_CMD_SHIFT = 8, | |
70 | MLX5_IB_MMAP_CMD_MASK = 0xff, | |
71 | }; | |
72 | ||
73 | enum mlx5_ib_mmap_cmd { | |
74 | MLX5_IB_MMAP_REGULAR_PAGE = 0, | |
d69e3bcf | 75 | MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, |
37aa5c36 GL |
76 | MLX5_IB_MMAP_WC_PAGE = 2, |
77 | MLX5_IB_MMAP_NC_PAGE = 3, | |
d69e3bcf MB |
78 | /* 5 is chosen in order to be compatible with old versions of libmlx5 */ |
79 | MLX5_IB_MMAP_CORE_CLOCK = 5, | |
e126ba97 EC |
80 | }; |
81 | ||
82 | enum { | |
83 | MLX5_RES_SCAT_DATA32_CQE = 0x1, | |
84 | MLX5_RES_SCAT_DATA64_CQE = 0x2, | |
85 | MLX5_REQ_SCAT_DATA32_CQE = 0x11, | |
86 | MLX5_REQ_SCAT_DATA64_CQE = 0x22, | |
87 | }; | |
88 | ||
89 | enum mlx5_ib_latency_class { | |
90 | MLX5_IB_LATENCY_CLASS_LOW, | |
91 | MLX5_IB_LATENCY_CLASS_MEDIUM, | |
92 | MLX5_IB_LATENCY_CLASS_HIGH, | |
e126ba97 EC |
93 | }; |
94 | ||
95 | enum mlx5_ib_mad_ifc_flags { | |
96 | MLX5_MAD_IFC_IGNORE_MKEY = 1, | |
97 | MLX5_MAD_IFC_IGNORE_BKEY = 2, | |
98 | MLX5_MAD_IFC_NET_VIEW = 4, | |
99 | }; | |
100 | ||
051f2630 | 101 | enum { |
2f5ff264 | 102 | MLX5_CROSS_CHANNEL_BFREG = 0, |
051f2630 LR |
103 | }; |
104 | ||
cfb5e088 HA |
105 | enum { |
106 | MLX5_CQE_VERSION_V0, | |
107 | MLX5_CQE_VERSION_V1, | |
108 | }; | |
109 | ||
eb761894 AK |
110 | enum { |
111 | MLX5_TM_MAX_RNDV_MSG_SIZE = 64, | |
112 | MLX5_TM_MAX_SGE = 1, | |
113 | }; | |
114 | ||
7c2344c3 MG |
115 | struct mlx5_ib_vma_private_data { |
116 | struct list_head list; | |
117 | struct vm_area_struct *vma; | |
118 | }; | |
119 | ||
e126ba97 EC |
120 | struct mlx5_ib_ucontext { |
121 | struct ib_ucontext ibucontext; | |
122 | struct list_head db_page_list; | |
123 | ||
124 | /* protect doorbell record alloc/free | |
125 | */ | |
126 | struct mutex db_page_mutex; | |
2f5ff264 | 127 | struct mlx5_bfreg_info bfregi; |
cfb5e088 | 128 | u8 cqe_version; |
146d2f1a | 129 | /* Transport Domain number */ |
130 | u32 tdn; | |
7c2344c3 | 131 | struct list_head vma_private_list; |
7d0cc6ed AK |
132 | |
133 | unsigned long upd_xlt_page; | |
134 | /* protect ODP/KSM */ | |
135 | struct mutex upd_xlt_page_mutex; | |
b037c29a | 136 | u64 lib_caps; |
e126ba97 EC |
137 | }; |
138 | ||
139 | static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) | |
140 | { | |
141 | return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); | |
142 | } | |
143 | ||
144 | struct mlx5_ib_pd { | |
145 | struct ib_pd ibpd; | |
146 | u32 pdn; | |
e126ba97 EC |
147 | }; |
148 | ||
038d2ef8 | 149 | #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) |
35d19011 | 150 | #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) |
038d2ef8 MG |
151 | #if (MLX5_IB_FLOW_LAST_PRIO <= 0) |
152 | #error "Invalid number of bypass priorities" | |
153 | #endif | |
154 | #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) | |
155 | ||
156 | #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) | |
cc0e5d42 | 157 | #define MLX5_IB_NUM_SNIFFER_FTS 2 |
038d2ef8 MG |
158 | struct mlx5_ib_flow_prio { |
159 | struct mlx5_flow_table *flow_table; | |
160 | unsigned int refcount; | |
161 | }; | |
162 | ||
163 | struct mlx5_ib_flow_handler { | |
164 | struct list_head list; | |
165 | struct ib_flow ibflow; | |
5497adc6 | 166 | struct mlx5_ib_flow_prio *prio; |
74491de9 | 167 | struct mlx5_flow_handle *rule; |
038d2ef8 MG |
168 | }; |
169 | ||
170 | struct mlx5_ib_flow_db { | |
171 | struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; | |
cc0e5d42 | 172 | struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; |
9ef9c640 | 173 | struct mlx5_flow_table *lag_demux_ft; |
038d2ef8 MG |
174 | /* Protect flow steering bypass flow tables |
175 | * when add/del flow rules. | |
176 | * only single add/removal of flow steering rule could be done | |
177 | * simultaneously. | |
178 | */ | |
179 | struct mutex lock; | |
180 | }; | |
181 | ||
e126ba97 EC |
182 | /* Use macros here so that don't have to duplicate |
183 | * enum ib_send_flags and enum ib_qp_type for low-level driver | |
184 | */ | |
185 | ||
31616255 AK |
186 | #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) |
187 | #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) | |
188 | #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) | |
189 | #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) | |
190 | #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) | |
191 | #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END | |
56e11d62 | 192 | |
e126ba97 | 193 | #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 |
d16e91da HE |
194 | /* |
195 | * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI | |
196 | * creates the actual hardware QP. | |
197 | */ | |
198 | #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 | |
e126ba97 EC |
199 | #define MLX5_IB_WR_UMR IB_WR_RESERVED1 |
200 | ||
31616255 AK |
201 | #define MLX5_IB_UMR_OCTOWORD 16 |
202 | #define MLX5_IB_UMR_XLT_ALIGNMENT 64 | |
203 | ||
7d0cc6ed AK |
204 | #define MLX5_IB_UPD_XLT_ZAP BIT(0) |
205 | #define MLX5_IB_UPD_XLT_ENABLE BIT(1) | |
206 | #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) | |
207 | #define MLX5_IB_UPD_XLT_ADDR BIT(3) | |
208 | #define MLX5_IB_UPD_XLT_PD BIT(4) | |
209 | #define MLX5_IB_UPD_XLT_ACCESS BIT(5) | |
81713d37 | 210 | #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) |
7d0cc6ed | 211 | |
b11a4f9c HE |
212 | /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. |
213 | * | |
214 | * These flags are intended for internal use by the mlx5_ib driver, and they | |
215 | * rely on the range reserved for that use in the ib_qp_create_flags enum. | |
216 | */ | |
217 | ||
218 | /* Create a UD QP whose source QP number is 1 */ | |
219 | static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) | |
220 | { | |
221 | return IB_QP_CREATE_RESERVED_START; | |
222 | } | |
223 | ||
e126ba97 EC |
224 | struct wr_list { |
225 | u16 opcode; | |
226 | u16 next; | |
227 | }; | |
228 | ||
e4cc4fa7 NO |
229 | enum mlx5_ib_rq_flags { |
230 | MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, | |
b1383aa6 | 231 | MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, |
e4cc4fa7 NO |
232 | }; |
233 | ||
e126ba97 EC |
234 | struct mlx5_ib_wq { |
235 | u64 *wrid; | |
236 | u32 *wr_data; | |
237 | struct wr_list *w_list; | |
238 | unsigned *wqe_head; | |
239 | u16 unsig_count; | |
240 | ||
241 | /* serialize post to the work queue | |
242 | */ | |
243 | spinlock_t lock; | |
244 | int wqe_cnt; | |
245 | int max_post; | |
246 | int max_gs; | |
247 | int offset; | |
248 | int wqe_shift; | |
249 | unsigned head; | |
250 | unsigned tail; | |
251 | u16 cur_post; | |
252 | u16 last_poll; | |
253 | void *qend; | |
254 | }; | |
255 | ||
03404e8a MG |
256 | enum mlx5_ib_wq_flags { |
257 | MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, | |
ccc87087 | 258 | MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, |
03404e8a MG |
259 | }; |
260 | ||
b4f34597 NO |
261 | #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 |
262 | #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 | |
263 | #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 | |
264 | #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 | |
265 | ||
79b20a6c YH |
266 | struct mlx5_ib_rwq { |
267 | struct ib_wq ibwq; | |
350d0e4c | 268 | struct mlx5_core_qp core_qp; |
79b20a6c YH |
269 | u32 rq_num_pas; |
270 | u32 log_rq_stride; | |
271 | u32 log_rq_size; | |
272 | u32 rq_page_offset; | |
273 | u32 log_page_size; | |
ccc87087 NO |
274 | u32 log_num_strides; |
275 | u32 two_byte_shift_en; | |
276 | u32 single_stride_log_num_of_bytes; | |
79b20a6c YH |
277 | struct ib_umem *umem; |
278 | size_t buf_size; | |
279 | unsigned int page_shift; | |
280 | int create_type; | |
281 | struct mlx5_db db; | |
282 | u32 user_index; | |
283 | u32 wqe_count; | |
284 | u32 wqe_shift; | |
285 | int wq_sig; | |
03404e8a | 286 | u32 create_flags; /* Use enum mlx5_ib_wq_flags */ |
79b20a6c YH |
287 | }; |
288 | ||
e126ba97 EC |
289 | enum { |
290 | MLX5_QP_USER, | |
291 | MLX5_QP_KERNEL, | |
292 | MLX5_QP_EMPTY | |
293 | }; | |
294 | ||
79b20a6c YH |
295 | enum { |
296 | MLX5_WQ_USER, | |
297 | MLX5_WQ_KERNEL | |
298 | }; | |
299 | ||
c5f90929 YH |
300 | struct mlx5_ib_rwq_ind_table { |
301 | struct ib_rwq_ind_table ib_rwq_ind_tbl; | |
302 | u32 rqtn; | |
303 | }; | |
304 | ||
19098df2 | 305 | struct mlx5_ib_ubuffer { |
306 | struct ib_umem *umem; | |
307 | int buf_size; | |
308 | u64 buf_addr; | |
309 | }; | |
310 | ||
311 | struct mlx5_ib_qp_base { | |
312 | struct mlx5_ib_qp *container_mibqp; | |
313 | struct mlx5_core_qp mqp; | |
314 | struct mlx5_ib_ubuffer ubuffer; | |
315 | }; | |
316 | ||
317 | struct mlx5_ib_qp_trans { | |
318 | struct mlx5_ib_qp_base base; | |
319 | u16 xrcdn; | |
320 | u8 alt_port; | |
321 | u8 atomic_rd_en; | |
322 | u8 resp_depth; | |
323 | }; | |
324 | ||
28d61370 YH |
325 | struct mlx5_ib_rss_qp { |
326 | u32 tirn; | |
327 | }; | |
328 | ||
038d2ef8 | 329 | struct mlx5_ib_rq { |
0fb2ed66 | 330 | struct mlx5_ib_qp_base base; |
331 | struct mlx5_ib_wq *rq; | |
332 | struct mlx5_ib_ubuffer ubuffer; | |
333 | struct mlx5_db *doorbell; | |
038d2ef8 | 334 | u32 tirn; |
0fb2ed66 | 335 | u8 state; |
e4cc4fa7 | 336 | u32 flags; |
0fb2ed66 | 337 | }; |
338 | ||
339 | struct mlx5_ib_sq { | |
340 | struct mlx5_ib_qp_base base; | |
341 | struct mlx5_ib_wq *sq; | |
342 | struct mlx5_ib_ubuffer ubuffer; | |
343 | struct mlx5_db *doorbell; | |
344 | u32 tisn; | |
345 | u8 state; | |
038d2ef8 MG |
346 | }; |
347 | ||
348 | struct mlx5_ib_raw_packet_qp { | |
0fb2ed66 | 349 | struct mlx5_ib_sq sq; |
038d2ef8 MG |
350 | struct mlx5_ib_rq rq; |
351 | }; | |
352 | ||
5fe9dec0 EC |
353 | struct mlx5_bf { |
354 | int buf_size; | |
355 | unsigned long offset; | |
356 | struct mlx5_sq_bfreg *bfreg; | |
357 | }; | |
358 | ||
e126ba97 EC |
359 | struct mlx5_ib_qp { |
360 | struct ib_qp ibqp; | |
038d2ef8 | 361 | union { |
0fb2ed66 | 362 | struct mlx5_ib_qp_trans trans_qp; |
363 | struct mlx5_ib_raw_packet_qp raw_packet_qp; | |
28d61370 | 364 | struct mlx5_ib_rss_qp rss_qp; |
038d2ef8 | 365 | }; |
e126ba97 EC |
366 | struct mlx5_buf buf; |
367 | ||
368 | struct mlx5_db db; | |
369 | struct mlx5_ib_wq rq; | |
370 | ||
e126ba97 | 371 | u8 sq_signal_bits; |
6e8484c5 | 372 | u8 next_fence; |
e126ba97 EC |
373 | struct mlx5_ib_wq sq; |
374 | ||
e126ba97 EC |
375 | /* serialize qp state modifications |
376 | */ | |
377 | struct mutex mutex; | |
e126ba97 EC |
378 | u32 flags; |
379 | u8 port; | |
e126ba97 | 380 | u8 state; |
e126ba97 EC |
381 | int wq_sig; |
382 | int scat_cqe; | |
383 | int max_inline_data; | |
5fe9dec0 | 384 | struct mlx5_bf bf; |
e126ba97 EC |
385 | int has_rq; |
386 | ||
387 | /* only for user space QPs. For kernel | |
388 | * we have it from the bf object | |
389 | */ | |
2f5ff264 | 390 | int bfregn; |
e126ba97 EC |
391 | |
392 | int create_type; | |
e1e66cc2 SG |
393 | |
394 | /* Store signature errors */ | |
395 | bool signature_en; | |
6aec21f6 | 396 | |
89ea94a7 MG |
397 | struct list_head qps_list; |
398 | struct list_head cq_recv_list; | |
399 | struct list_head cq_send_list; | |
7d29f349 | 400 | u32 rate_limit; |
c2e53b2c | 401 | u32 underlay_qpn; |
f95ef6cb | 402 | bool tunnel_offload_en; |
e126ba97 EC |
403 | }; |
404 | ||
405 | struct mlx5_ib_cq_buf { | |
406 | struct mlx5_buf buf; | |
407 | struct ib_umem *umem; | |
408 | int cqe_size; | |
bde51583 | 409 | int nent; |
e126ba97 EC |
410 | }; |
411 | ||
412 | enum mlx5_ib_qp_flags { | |
f0313965 ES |
413 | MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, |
414 | MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, | |
415 | MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, | |
416 | MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, | |
417 | MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, | |
418 | MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, | |
b11a4f9c HE |
419 | /* QP uses 1 as its source QP number */ |
420 | MLX5_IB_QP_SQPN_QP1 = 1 << 6, | |
358e42ea | 421 | MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, |
d9f88e5a | 422 | MLX5_IB_QP_RSS = 1 << 8, |
e4cc4fa7 | 423 | MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, |
c2e53b2c | 424 | MLX5_IB_QP_UNDERLAY = 1 << 10, |
b1383aa6 | 425 | MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, |
f95ef6cb | 426 | MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, |
e126ba97 EC |
427 | }; |
428 | ||
968e78dd | 429 | struct mlx5_umr_wr { |
e622f2f4 | 430 | struct ib_send_wr wr; |
31616255 AK |
431 | u64 virt_addr; |
432 | u64 offset; | |
968e78dd HE |
433 | struct ib_pd *pd; |
434 | unsigned int page_shift; | |
31616255 | 435 | unsigned int xlt_size; |
b216af40 | 436 | u64 length; |
968e78dd HE |
437 | int access_flags; |
438 | u32 mkey; | |
439 | }; | |
440 | ||
e622f2f4 CH |
441 | static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) |
442 | { | |
443 | return container_of(wr, struct mlx5_umr_wr, wr); | |
444 | } | |
445 | ||
e126ba97 EC |
446 | struct mlx5_shared_mr_info { |
447 | int mr_id; | |
448 | struct ib_umem *umem; | |
449 | }; | |
450 | ||
7a0c8f42 GL |
451 | enum mlx5_ib_cq_pr_flags { |
452 | MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, | |
453 | }; | |
454 | ||
e126ba97 EC |
455 | struct mlx5_ib_cq { |
456 | struct ib_cq ibcq; | |
457 | struct mlx5_core_cq mcq; | |
458 | struct mlx5_ib_cq_buf buf; | |
459 | struct mlx5_db db; | |
460 | ||
461 | /* serialize access to the CQ | |
462 | */ | |
463 | spinlock_t lock; | |
464 | ||
465 | /* protect resize cq | |
466 | */ | |
467 | struct mutex resize_mutex; | |
bde51583 | 468 | struct mlx5_ib_cq_buf *resize_buf; |
e126ba97 EC |
469 | struct ib_umem *resize_umem; |
470 | int cqe_size; | |
89ea94a7 MG |
471 | struct list_head list_send_qp; |
472 | struct list_head list_recv_qp; | |
051f2630 | 473 | u32 create_flags; |
25361e02 HE |
474 | struct list_head wc_list; |
475 | enum ib_cq_notify_flags notify_flags; | |
476 | struct work_struct notify_work; | |
7a0c8f42 | 477 | u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ |
25361e02 HE |
478 | }; |
479 | ||
480 | struct mlx5_ib_wc { | |
481 | struct ib_wc wc; | |
482 | struct list_head list; | |
e126ba97 EC |
483 | }; |
484 | ||
485 | struct mlx5_ib_srq { | |
486 | struct ib_srq ibsrq; | |
487 | struct mlx5_core_srq msrq; | |
488 | struct mlx5_buf buf; | |
489 | struct mlx5_db db; | |
490 | u64 *wrid; | |
491 | /* protect SRQ hanlding | |
492 | */ | |
493 | spinlock_t lock; | |
494 | int head; | |
495 | int tail; | |
496 | u16 wqe_ctr; | |
497 | struct ib_umem *umem; | |
498 | /* serialize arming a SRQ | |
499 | */ | |
500 | struct mutex mutex; | |
501 | int wq_sig; | |
502 | }; | |
503 | ||
504 | struct mlx5_ib_xrcd { | |
505 | struct ib_xrcd ibxrcd; | |
506 | u32 xrcdn; | |
507 | }; | |
508 | ||
cc149f75 HE |
509 | enum mlx5_ib_mtt_access_flags { |
510 | MLX5_IB_MTT_READ = (1 << 0), | |
511 | MLX5_IB_MTT_WRITE = (1 << 1), | |
512 | }; | |
513 | ||
514 | #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) | |
515 | ||
e126ba97 EC |
516 | struct mlx5_ib_mr { |
517 | struct ib_mr ibmr; | |
8a187ee5 SG |
518 | void *descs; |
519 | dma_addr_t desc_map; | |
520 | int ndescs; | |
521 | int max_descs; | |
522 | int desc_size; | |
b005d316 | 523 | int access_mode; |
a606b0f6 | 524 | struct mlx5_core_mkey mmkey; |
e126ba97 EC |
525 | struct ib_umem *umem; |
526 | struct mlx5_shared_mr_info *smr_info; | |
527 | struct list_head list; | |
528 | int order; | |
8b7ff7f3 | 529 | bool allocated_from_cache; |
e126ba97 | 530 | int npages; |
746b5583 | 531 | struct mlx5_ib_dev *dev; |
ec22eb53 | 532 | u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; |
3121e3c4 | 533 | struct mlx5_core_sig_ctx *sig; |
b4cfe447 | 534 | int live; |
8a187ee5 | 535 | void *descs_alloc; |
56e11d62 | 536 | int access_flags; /* Needed for rereg MR */ |
81713d37 AK |
537 | |
538 | struct mlx5_ib_mr *parent; | |
539 | atomic_t num_leaf_free; | |
540 | wait_queue_head_t q_leaf_free; | |
e126ba97 EC |
541 | }; |
542 | ||
d2370e0a MB |
543 | struct mlx5_ib_mw { |
544 | struct ib_mw ibmw; | |
545 | struct mlx5_core_mkey mmkey; | |
db570d7d | 546 | int ndescs; |
e126ba97 EC |
547 | }; |
548 | ||
a74d2416 | 549 | struct mlx5_ib_umr_context { |
add08d76 | 550 | struct ib_cqe cqe; |
a74d2416 SR |
551 | enum ib_wc_status status; |
552 | struct completion done; | |
553 | }; | |
554 | ||
e126ba97 EC |
555 | struct umr_common { |
556 | struct ib_pd *pd; | |
557 | struct ib_cq *cq; | |
558 | struct ib_qp *qp; | |
e126ba97 EC |
559 | /* control access to UMR QP |
560 | */ | |
561 | struct semaphore sem; | |
562 | }; | |
563 | ||
564 | enum { | |
565 | MLX5_FMR_INVALID, | |
566 | MLX5_FMR_VALID, | |
567 | MLX5_FMR_BUSY, | |
568 | }; | |
569 | ||
e126ba97 EC |
570 | struct mlx5_cache_ent { |
571 | struct list_head head; | |
572 | /* sync access to the cahce entry | |
573 | */ | |
574 | spinlock_t lock; | |
575 | ||
576 | ||
577 | struct dentry *dir; | |
578 | char name[4]; | |
579 | u32 order; | |
49780d42 AK |
580 | u32 xlt; |
581 | u32 access_mode; | |
582 | u32 page; | |
583 | ||
e126ba97 EC |
584 | u32 size; |
585 | u32 cur; | |
586 | u32 miss; | |
587 | u32 limit; | |
588 | ||
589 | struct dentry *fsize; | |
590 | struct dentry *fcur; | |
591 | struct dentry *fmiss; | |
592 | struct dentry *flimit; | |
593 | ||
594 | struct mlx5_ib_dev *dev; | |
595 | struct work_struct work; | |
596 | struct delayed_work dwork; | |
746b5583 | 597 | int pending; |
49780d42 | 598 | struct completion compl; |
e126ba97 EC |
599 | }; |
600 | ||
601 | struct mlx5_mr_cache { | |
602 | struct workqueue_struct *wq; | |
603 | struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; | |
604 | int stopped; | |
605 | struct dentry *root; | |
606 | unsigned long last_add; | |
607 | }; | |
608 | ||
d16e91da HE |
609 | struct mlx5_ib_gsi_qp; |
610 | ||
611 | struct mlx5_ib_port_resources { | |
7722f47e | 612 | struct mlx5_ib_resources *devr; |
d16e91da | 613 | struct mlx5_ib_gsi_qp *gsi; |
7722f47e | 614 | struct work_struct pkey_change_work; |
d16e91da HE |
615 | }; |
616 | ||
e126ba97 EC |
617 | struct mlx5_ib_resources { |
618 | struct ib_cq *c0; | |
619 | struct ib_xrcd *x0; | |
620 | struct ib_xrcd *x1; | |
621 | struct ib_pd *p0; | |
622 | struct ib_srq *s0; | |
4aa17b28 | 623 | struct ib_srq *s1; |
d16e91da HE |
624 | struct mlx5_ib_port_resources ports[2]; |
625 | /* Protects changes to the port resources */ | |
626 | struct mutex mutex; | |
e126ba97 EC |
627 | }; |
628 | ||
e1f24a79 | 629 | struct mlx5_ib_counters { |
7c16f477 KH |
630 | const char **names; |
631 | size_t *offsets; | |
e1f24a79 PP |
632 | u32 num_q_counters; |
633 | u32 num_cong_counters; | |
7c16f477 KH |
634 | u16 set_id; |
635 | }; | |
636 | ||
0837e86a | 637 | struct mlx5_ib_port { |
e1f24a79 | 638 | struct mlx5_ib_counters cnts; |
0837e86a MB |
639 | }; |
640 | ||
fc24fc5e AS |
641 | struct mlx5_roce { |
642 | /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL | |
643 | * netdev pointer | |
644 | */ | |
645 | rwlock_t netdev_lock; | |
646 | struct net_device *netdev; | |
647 | struct notifier_block nb; | |
13eab21f | 648 | atomic_t next_port; |
fd65f1b8 | 649 | enum ib_port_state last_port_state; |
fc24fc5e AS |
650 | }; |
651 | ||
4a2da0b8 PP |
652 | struct mlx5_ib_dbg_param { |
653 | int offset; | |
654 | struct mlx5_ib_dev *dev; | |
655 | struct dentry *dentry; | |
656 | }; | |
657 | ||
658 | enum mlx5_ib_dbg_cc_types { | |
659 | MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, | |
660 | MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, | |
661 | MLX5_IB_DBG_CC_RP_TIME_RESET, | |
662 | MLX5_IB_DBG_CC_RP_BYTE_RESET, | |
663 | MLX5_IB_DBG_CC_RP_THRESHOLD, | |
664 | MLX5_IB_DBG_CC_RP_AI_RATE, | |
665 | MLX5_IB_DBG_CC_RP_HAI_RATE, | |
666 | MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, | |
667 | MLX5_IB_DBG_CC_RP_MIN_RATE, | |
668 | MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, | |
669 | MLX5_IB_DBG_CC_RP_DCE_TCP_G, | |
670 | MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, | |
671 | MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, | |
672 | MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, | |
673 | MLX5_IB_DBG_CC_RP_GD, | |
674 | MLX5_IB_DBG_CC_NP_CNP_DSCP, | |
675 | MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, | |
676 | MLX5_IB_DBG_CC_NP_CNP_PRIO, | |
677 | MLX5_IB_DBG_CC_MAX, | |
678 | }; | |
679 | ||
680 | struct mlx5_ib_dbg_cc_params { | |
681 | struct dentry *root; | |
682 | struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; | |
683 | }; | |
684 | ||
03404e8a MG |
685 | enum { |
686 | MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, | |
687 | }; | |
688 | ||
fe248c3a MG |
689 | struct mlx5_ib_dbg_delay_drop { |
690 | struct dentry *dir_debugfs; | |
691 | struct dentry *rqs_cnt_debugfs; | |
692 | struct dentry *events_cnt_debugfs; | |
693 | struct dentry *timeout_debugfs; | |
694 | }; | |
695 | ||
03404e8a MG |
696 | struct mlx5_ib_delay_drop { |
697 | struct mlx5_ib_dev *dev; | |
698 | struct work_struct delay_drop_work; | |
699 | /* serialize setting of delay drop */ | |
700 | struct mutex lock; | |
701 | u32 timeout; | |
702 | bool activate; | |
fe248c3a MG |
703 | atomic_t events_cnt; |
704 | atomic_t rqs_cnt; | |
705 | struct mlx5_ib_dbg_delay_drop *dbg; | |
03404e8a MG |
706 | }; |
707 | ||
e126ba97 EC |
708 | struct mlx5_ib_dev { |
709 | struct ib_device ib_dev; | |
9603b61d | 710 | struct mlx5_core_dev *mdev; |
fc24fc5e | 711 | struct mlx5_roce roce; |
e126ba97 | 712 | int num_ports; |
e126ba97 EC |
713 | /* serialize update of capability mask |
714 | */ | |
715 | struct mutex cap_mask_mutex; | |
716 | bool ib_active; | |
717 | struct umr_common umrc; | |
718 | /* sync used page count stats | |
719 | */ | |
e126ba97 EC |
720 | struct mlx5_ib_resources devr; |
721 | struct mlx5_mr_cache cache; | |
746b5583 | 722 | struct timer_list delay_timer; |
6bc1a656 ML |
723 | /* Prevents soft lock on massive reg MRs */ |
724 | struct mutex slow_path_mutex; | |
746b5583 | 725 | int fill_delay; |
8cdd312c HE |
726 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
727 | struct ib_odp_caps odp_caps; | |
c438fde1 | 728 | u64 odp_max_size; |
6aec21f6 HE |
729 | /* |
730 | * Sleepable RCU that prevents destruction of MRs while they are still | |
731 | * being used by a page fault handler. | |
732 | */ | |
733 | struct srcu_struct mr_srcu; | |
81713d37 | 734 | u32 null_mkey; |
8cdd312c | 735 | #endif |
038d2ef8 | 736 | struct mlx5_ib_flow_db flow_db; |
89ea94a7 MG |
737 | /* protect resources needed as part of reset flow */ |
738 | spinlock_t reset_flow_resource_lock; | |
739 | struct list_head qp_list; | |
0837e86a MB |
740 | /* Array with num_ports elements */ |
741 | struct mlx5_ib_port *port; | |
c85023e1 HN |
742 | struct mlx5_sq_bfreg bfreg; |
743 | struct mlx5_sq_bfreg fp_bfreg; | |
03404e8a | 744 | struct mlx5_ib_delay_drop delay_drop; |
4a2da0b8 | 745 | struct mlx5_ib_dbg_cc_params *dbg_cc_params; |
c85023e1 HN |
746 | |
747 | /* protect the user_td */ | |
748 | struct mutex lb_mutex; | |
749 | u32 user_td; | |
750 | u8 umr_fence; | |
e126ba97 EC |
751 | }; |
752 | ||
753 | static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) | |
754 | { | |
755 | return container_of(mcq, struct mlx5_ib_cq, mcq); | |
756 | } | |
757 | ||
758 | static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) | |
759 | { | |
760 | return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); | |
761 | } | |
762 | ||
763 | static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) | |
764 | { | |
765 | return container_of(ibdev, struct mlx5_ib_dev, ib_dev); | |
766 | } | |
767 | ||
e126ba97 EC |
768 | static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) |
769 | { | |
770 | return container_of(ibcq, struct mlx5_ib_cq, ibcq); | |
771 | } | |
772 | ||
773 | static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) | |
774 | { | |
19098df2 | 775 | return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; |
e126ba97 EC |
776 | } |
777 | ||
350d0e4c YH |
778 | static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) |
779 | { | |
780 | return container_of(core_qp, struct mlx5_ib_rwq, core_qp); | |
781 | } | |
782 | ||
a606b0f6 | 783 | static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) |
d5436ba0 | 784 | { |
a606b0f6 | 785 | return container_of(mmkey, struct mlx5_ib_mr, mmkey); |
d5436ba0 SG |
786 | } |
787 | ||
e126ba97 EC |
788 | static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) |
789 | { | |
790 | return container_of(ibpd, struct mlx5_ib_pd, ibpd); | |
791 | } | |
792 | ||
793 | static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) | |
794 | { | |
795 | return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); | |
796 | } | |
797 | ||
798 | static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) | |
799 | { | |
800 | return container_of(ibqp, struct mlx5_ib_qp, ibqp); | |
801 | } | |
802 | ||
79b20a6c YH |
803 | static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) |
804 | { | |
805 | return container_of(ibwq, struct mlx5_ib_rwq, ibwq); | |
806 | } | |
807 | ||
c5f90929 YH |
808 | static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) |
809 | { | |
810 | return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); | |
811 | } | |
812 | ||
e126ba97 EC |
813 | static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) |
814 | { | |
815 | return container_of(msrq, struct mlx5_ib_srq, msrq); | |
816 | } | |
817 | ||
818 | static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) | |
819 | { | |
820 | return container_of(ibmr, struct mlx5_ib_mr, ibmr); | |
821 | } | |
822 | ||
d2370e0a MB |
823 | static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) |
824 | { | |
825 | return container_of(ibmw, struct mlx5_ib_mw, ibmw); | |
826 | } | |
827 | ||
e126ba97 EC |
828 | int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, |
829 | struct mlx5_db *db); | |
830 | void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); | |
831 | void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); | |
832 | void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); | |
833 | void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); | |
834 | int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, | |
a97e2d86 IW |
835 | u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
836 | const void *in_mad, void *response_mad); | |
90898850 | 837 | struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, |
477864c8 | 838 | struct ib_udata *udata); |
90898850 | 839 | int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); |
e126ba97 EC |
840 | int mlx5_ib_destroy_ah(struct ib_ah *ah); |
841 | struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, | |
842 | struct ib_srq_init_attr *init_attr, | |
843 | struct ib_udata *udata); | |
844 | int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, | |
845 | enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); | |
846 | int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); | |
847 | int mlx5_ib_destroy_srq(struct ib_srq *srq); | |
848 | int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, | |
849 | struct ib_recv_wr **bad_wr); | |
850 | struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, | |
851 | struct ib_qp_init_attr *init_attr, | |
852 | struct ib_udata *udata); | |
853 | int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
854 | int attr_mask, struct ib_udata *udata); | |
855 | int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, | |
856 | struct ib_qp_init_attr *qp_init_attr); | |
857 | int mlx5_ib_destroy_qp(struct ib_qp *qp); | |
858 | int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |
859 | struct ib_send_wr **bad_wr); | |
860 | int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, | |
861 | struct ib_recv_wr **bad_wr); | |
862 | void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); | |
c1395a2a | 863 | int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, |
19098df2 | 864 | void *buffer, u32 length, |
865 | struct mlx5_ib_qp_base *base); | |
bcf4c1ea MB |
866 | struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, |
867 | const struct ib_cq_init_attr *attr, | |
868 | struct ib_ucontext *context, | |
e126ba97 EC |
869 | struct ib_udata *udata); |
870 | int mlx5_ib_destroy_cq(struct ib_cq *cq); | |
871 | int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); | |
872 | int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); | |
873 | int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); | |
874 | int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); | |
875 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); | |
876 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
877 | u64 virt_addr, int access_flags, | |
878 | struct ib_udata *udata); | |
d2370e0a MB |
879 | struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
880 | struct ib_udata *udata); | |
881 | int mlx5_ib_dealloc_mw(struct ib_mw *mw); | |
7d0cc6ed AK |
882 | int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, |
883 | int page_shift, int flags); | |
81713d37 AK |
884 | struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, |
885 | int access_flags); | |
886 | void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); | |
56e11d62 NO |
887 | int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, |
888 | u64 length, u64 virt_addr, int access_flags, | |
889 | struct ib_pd *pd, struct ib_udata *udata); | |
e126ba97 | 890 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr); |
9bee178b SG |
891 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, |
892 | enum ib_mr_type mr_type, | |
893 | u32 max_num_sg); | |
ff2ba993 | 894 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 895 | unsigned int *sg_offset); |
e126ba97 | 896 | int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, |
a97e2d86 | 897 | const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
4cd7c947 IW |
898 | const struct ib_mad_hdr *in, size_t in_mad_size, |
899 | struct ib_mad_hdr *out, size_t *out_mad_size, | |
900 | u16 *out_mad_pkey_index); | |
e126ba97 EC |
901 | struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, |
902 | struct ib_ucontext *context, | |
903 | struct ib_udata *udata); | |
904 | int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); | |
e126ba97 EC |
905 | int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); |
906 | int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); | |
1b5daf11 MD |
907 | int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, |
908 | struct ib_smp *out_mad); | |
909 | int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, | |
910 | __be64 *sys_image_guid); | |
911 | int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, | |
912 | u16 *max_pkeys); | |
913 | int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, | |
914 | u32 *vendor_id); | |
915 | int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); | |
916 | int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); | |
917 | int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, | |
918 | u16 *pkey); | |
919 | int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, | |
920 | union ib_gid *gid); | |
921 | int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, | |
922 | struct ib_port_attr *props); | |
e126ba97 EC |
923 | int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, |
924 | struct ib_port_attr *props); | |
925 | int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); | |
926 | void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); | |
762f899a MD |
927 | void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, |
928 | unsigned long max_page_shift, | |
929 | int *count, int *shift, | |
e126ba97 | 930 | int *ncont, int *order); |
832a6b06 HE |
931 | void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, |
932 | int page_shift, size_t offset, size_t num_pages, | |
933 | __be64 *pas, int access_flags); | |
e126ba97 | 934 | void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, |
cc149f75 | 935 | int page_shift, __be64 *pas, int access_flags); |
e126ba97 EC |
936 | void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); |
937 | int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); | |
938 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); | |
939 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); | |
49780d42 AK |
940 | |
941 | struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); | |
942 | void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); | |
d5436ba0 SG |
943 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
944 | struct ib_mr_status *mr_status); | |
79b20a6c YH |
945 | struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, |
946 | struct ib_wq_init_attr *init_attr, | |
947 | struct ib_udata *udata); | |
948 | int mlx5_ib_destroy_wq(struct ib_wq *wq); | |
949 | int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, | |
950 | u32 wq_attr_mask, struct ib_udata *udata); | |
c5f90929 YH |
951 | struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, |
952 | struct ib_rwq_ind_table_init_attr *init_attr, | |
953 | struct ib_udata *udata); | |
954 | int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); | |
e126ba97 | 955 | |
8cdd312c | 956 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
938fe83c | 957 | void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); |
d9aaed83 AK |
958 | void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context, |
959 | struct mlx5_pagefault *pfault); | |
6aec21f6 HE |
960 | int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); |
961 | void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); | |
962 | int __init mlx5_ib_odp_init(void); | |
963 | void mlx5_ib_odp_cleanup(void); | |
b4cfe447 HE |
964 | void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, |
965 | unsigned long end); | |
81713d37 AK |
966 | void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); |
967 | void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, | |
968 | size_t nentries, struct mlx5_ib_mr *mr, int flags); | |
6aec21f6 | 969 | #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ |
938fe83c | 970 | static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) |
8cdd312c | 971 | { |
938fe83c | 972 | return; |
8cdd312c | 973 | } |
6aec21f6 | 974 | |
6aec21f6 | 975 | static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } |
81713d37 | 976 | static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} |
6aec21f6 | 977 | static inline int mlx5_ib_odp_init(void) { return 0; } |
81713d37 AK |
978 | static inline void mlx5_ib_odp_cleanup(void) {} |
979 | static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} | |
980 | static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, | |
981 | size_t nentries, struct mlx5_ib_mr *mr, | |
982 | int flags) {} | |
6aec21f6 | 983 | |
8cdd312c HE |
984 | #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ |
985 | ||
9967c70a AB |
986 | int mlx5_ib_get_vf_config(struct ib_device *device, int vf, |
987 | u8 port, struct ifla_vf_info *info); | |
988 | int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, | |
989 | u8 port, int state); | |
990 | int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, | |
991 | u8 port, struct ifla_vf_stats *stats); | |
992 | int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, | |
993 | u64 guid, int type); | |
994 | ||
2811ba51 AS |
995 | __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, |
996 | int index); | |
ed88451e MD |
997 | int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, |
998 | int index, enum ib_gid_type *gid_type); | |
2811ba51 | 999 | |
4a2da0b8 PP |
1000 | void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev); |
1001 | int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev); | |
1002 | ||
d16e91da HE |
1003 | /* GSI QP helper functions */ |
1004 | struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, | |
1005 | struct ib_qp_init_attr *init_attr); | |
1006 | int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); | |
1007 | int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, | |
1008 | int attr_mask); | |
1009 | int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, | |
1010 | int qp_attr_mask, | |
1011 | struct ib_qp_init_attr *qp_init_attr); | |
1012 | int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, | |
1013 | struct ib_send_wr **bad_wr); | |
1014 | int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, | |
1015 | struct ib_recv_wr **bad_wr); | |
7722f47e | 1016 | void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); |
d16e91da | 1017 | |
25361e02 HE |
1018 | int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); |
1019 | ||
e126ba97 EC |
1020 | static inline void init_query_mad(struct ib_smp *mad) |
1021 | { | |
1022 | mad->base_version = 1; | |
1023 | mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; | |
1024 | mad->class_version = 1; | |
1025 | mad->method = IB_MGMT_METHOD_GET; | |
1026 | } | |
1027 | ||
1028 | static inline u8 convert_access(int acc) | |
1029 | { | |
1030 | return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | | |
1031 | (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | | |
1032 | (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | | |
1033 | (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | | |
1034 | MLX5_PERM_LOCAL_READ; | |
1035 | } | |
1036 | ||
b636401f SG |
1037 | static inline int is_qp1(enum ib_qp_type qp_type) |
1038 | { | |
d16e91da | 1039 | return qp_type == MLX5_IB_QPT_HW_GSI; |
b636401f SG |
1040 | } |
1041 | ||
cc149f75 HE |
1042 | #define MLX5_MAX_UMR_SHIFT 16 |
1043 | #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) | |
1044 | ||
051f2630 LR |
1045 | static inline u32 check_cq_create_flags(u32 flags) |
1046 | { | |
1047 | /* | |
1048 | * It returns non-zero value for unsupported CQ | |
1049 | * create flags, otherwise it returns zero. | |
1050 | */ | |
34356f64 LR |
1051 | return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | |
1052 | IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); | |
051f2630 | 1053 | } |
cfb5e088 HA |
1054 | |
1055 | static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, | |
1056 | u32 *user_index) | |
1057 | { | |
1058 | if (cqe_version) { | |
1059 | if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || | |
1060 | (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) | |
1061 | return -EINVAL; | |
1062 | *user_index = cmd_uidx; | |
1063 | } else { | |
1064 | *user_index = MLX5_IB_DEFAULT_UIDX; | |
1065 | } | |
1066 | ||
1067 | return 0; | |
1068 | } | |
3085e29e LR |
1069 | |
1070 | static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, | |
1071 | struct mlx5_ib_create_qp *ucmd, | |
1072 | int inlen, | |
1073 | u32 *user_index) | |
1074 | { | |
1075 | u8 cqe_version = ucontext->cqe_version; | |
1076 | ||
1077 | if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && | |
1078 | !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) | |
1079 | return 0; | |
1080 | ||
1081 | if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != | |
1082 | !!cqe_version)) | |
1083 | return -EINVAL; | |
1084 | ||
1085 | return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); | |
1086 | } | |
1087 | ||
1088 | static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, | |
1089 | struct mlx5_ib_create_srq *ucmd, | |
1090 | int inlen, | |
1091 | u32 *user_index) | |
1092 | { | |
1093 | u8 cqe_version = ucontext->cqe_version; | |
1094 | ||
1095 | if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && | |
1096 | !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) | |
1097 | return 0; | |
1098 | ||
1099 | if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != | |
1100 | !!cqe_version)) | |
1101 | return -EINVAL; | |
1102 | ||
1103 | return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); | |
1104 | } | |
b037c29a EC |
1105 | |
1106 | static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) | |
1107 | { | |
1108 | return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? | |
1109 | MLX5_UARS_IN_PAGE : 1; | |
1110 | } | |
1111 | ||
1112 | static inline int get_num_uars(struct mlx5_ib_dev *dev, | |
1113 | struct mlx5_bfreg_info *bfregi) | |
1114 | { | |
1115 | return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_sys_pages; | |
1116 | } | |
1117 | ||
e126ba97 | 1118 | #endif /* MLX5_IB_H */ |