Commit | Line | Data |
---|---|---|
e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_IB_H | |
34 | #define MLX5_IB_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/sched.h> | |
38 | #include <rdma/ib_verbs.h> | |
39 | #include <rdma/ib_smi.h> | |
40 | #include <linux/mlx5/driver.h> | |
41 | #include <linux/mlx5/cq.h> | |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/srq.h> | |
44 | #include <linux/types.h> | |
146d2f1a | 45 | #include <linux/mlx5/transobj.h> |
d2370e0a | 46 | #include <rdma/ib_user_verbs.h> |
3085e29e | 47 | #include <rdma/mlx5-abi.h> |
e126ba97 EC |
48 | |
49 | #define mlx5_ib_dbg(dev, format, arg...) \ | |
50 | pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ | |
51 | __LINE__, current->pid, ##arg) | |
52 | ||
53 | #define mlx5_ib_err(dev, format, arg...) \ | |
54 | pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ | |
55 | __LINE__, current->pid, ##arg) | |
56 | ||
57 | #define mlx5_ib_warn(dev, format, arg...) \ | |
58 | pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ | |
59 | __LINE__, current->pid, ##arg) | |
60 | ||
b368d7cb MB |
61 | #define field_avail(type, fld, sz) (offsetof(type, fld) + \ |
62 | sizeof(((type *)0)->fld) <= (sz)) | |
cfb5e088 HA |
63 | #define MLX5_IB_DEFAULT_UIDX 0xffffff |
64 | #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) | |
b368d7cb | 65 | |
762f899a MD |
66 | #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) |
67 | ||
e126ba97 EC |
68 | enum { |
69 | MLX5_IB_MMAP_CMD_SHIFT = 8, | |
70 | MLX5_IB_MMAP_CMD_MASK = 0xff, | |
71 | }; | |
72 | ||
73 | enum mlx5_ib_mmap_cmd { | |
74 | MLX5_IB_MMAP_REGULAR_PAGE = 0, | |
d69e3bcf | 75 | MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, |
37aa5c36 GL |
76 | MLX5_IB_MMAP_WC_PAGE = 2, |
77 | MLX5_IB_MMAP_NC_PAGE = 3, | |
d69e3bcf MB |
78 | /* 5 is chosen in order to be compatible with old versions of libmlx5 */ |
79 | MLX5_IB_MMAP_CORE_CLOCK = 5, | |
e126ba97 EC |
80 | }; |
81 | ||
82 | enum { | |
83 | MLX5_RES_SCAT_DATA32_CQE = 0x1, | |
84 | MLX5_RES_SCAT_DATA64_CQE = 0x2, | |
85 | MLX5_REQ_SCAT_DATA32_CQE = 0x11, | |
86 | MLX5_REQ_SCAT_DATA64_CQE = 0x22, | |
87 | }; | |
88 | ||
89 | enum mlx5_ib_latency_class { | |
90 | MLX5_IB_LATENCY_CLASS_LOW, | |
91 | MLX5_IB_LATENCY_CLASS_MEDIUM, | |
92 | MLX5_IB_LATENCY_CLASS_HIGH, | |
93 | MLX5_IB_LATENCY_CLASS_FAST_PATH | |
94 | }; | |
95 | ||
96 | enum mlx5_ib_mad_ifc_flags { | |
97 | MLX5_MAD_IFC_IGNORE_MKEY = 1, | |
98 | MLX5_MAD_IFC_IGNORE_BKEY = 2, | |
99 | MLX5_MAD_IFC_NET_VIEW = 4, | |
100 | }; | |
101 | ||
051f2630 LR |
102 | enum { |
103 | MLX5_CROSS_CHANNEL_UUAR = 0, | |
104 | }; | |
105 | ||
cfb5e088 HA |
106 | enum { |
107 | MLX5_CQE_VERSION_V0, | |
108 | MLX5_CQE_VERSION_V1, | |
109 | }; | |
110 | ||
7c2344c3 MG |
111 | struct mlx5_ib_vma_private_data { |
112 | struct list_head list; | |
113 | struct vm_area_struct *vma; | |
114 | }; | |
115 | ||
e126ba97 EC |
116 | struct mlx5_ib_ucontext { |
117 | struct ib_ucontext ibucontext; | |
118 | struct list_head db_page_list; | |
119 | ||
120 | /* protect doorbell record alloc/free | |
121 | */ | |
122 | struct mutex db_page_mutex; | |
123 | struct mlx5_uuar_info uuari; | |
cfb5e088 | 124 | u8 cqe_version; |
146d2f1a | 125 | /* Transport Domain number */ |
126 | u32 tdn; | |
7c2344c3 | 127 | struct list_head vma_private_list; |
e126ba97 EC |
128 | }; |
129 | ||
130 | static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) | |
131 | { | |
132 | return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); | |
133 | } | |
134 | ||
135 | struct mlx5_ib_pd { | |
136 | struct ib_pd ibpd; | |
137 | u32 pdn; | |
e126ba97 EC |
138 | }; |
139 | ||
038d2ef8 | 140 | #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) |
35d19011 | 141 | #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) |
038d2ef8 MG |
142 | #if (MLX5_IB_FLOW_LAST_PRIO <= 0) |
143 | #error "Invalid number of bypass priorities" | |
144 | #endif | |
145 | #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) | |
146 | ||
147 | #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) | |
cc0e5d42 | 148 | #define MLX5_IB_NUM_SNIFFER_FTS 2 |
038d2ef8 MG |
149 | struct mlx5_ib_flow_prio { |
150 | struct mlx5_flow_table *flow_table; | |
151 | unsigned int refcount; | |
152 | }; | |
153 | ||
154 | struct mlx5_ib_flow_handler { | |
155 | struct list_head list; | |
156 | struct ib_flow ibflow; | |
5497adc6 | 157 | struct mlx5_ib_flow_prio *prio; |
74491de9 | 158 | struct mlx5_flow_handle *rule; |
038d2ef8 MG |
159 | }; |
160 | ||
161 | struct mlx5_ib_flow_db { | |
162 | struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; | |
cc0e5d42 | 163 | struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; |
9ef9c640 | 164 | struct mlx5_flow_table *lag_demux_ft; |
038d2ef8 MG |
165 | /* Protect flow steering bypass flow tables |
166 | * when add/del flow rules. | |
167 | * only single add/removal of flow steering rule could be done | |
168 | * simultaneously. | |
169 | */ | |
170 | struct mutex lock; | |
171 | }; | |
172 | ||
e126ba97 EC |
173 | /* Use macros here so that don't have to duplicate |
174 | * enum ib_send_flags and enum ib_qp_type for low-level driver | |
175 | */ | |
176 | ||
31616255 AK |
177 | #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) |
178 | #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) | |
179 | #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) | |
180 | #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) | |
181 | #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) | |
182 | #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END | |
56e11d62 | 183 | |
e126ba97 | 184 | #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 |
d16e91da HE |
185 | /* |
186 | * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI | |
187 | * creates the actual hardware QP. | |
188 | */ | |
189 | #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 | |
e126ba97 EC |
190 | #define MLX5_IB_WR_UMR IB_WR_RESERVED1 |
191 | ||
31616255 AK |
192 | #define MLX5_IB_UMR_OCTOWORD 16 |
193 | #define MLX5_IB_UMR_XLT_ALIGNMENT 64 | |
194 | ||
b11a4f9c HE |
195 | /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. |
196 | * | |
197 | * These flags are intended for internal use by the mlx5_ib driver, and they | |
198 | * rely on the range reserved for that use in the ib_qp_create_flags enum. | |
199 | */ | |
200 | ||
201 | /* Create a UD QP whose source QP number is 1 */ | |
202 | static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) | |
203 | { | |
204 | return IB_QP_CREATE_RESERVED_START; | |
205 | } | |
206 | ||
e126ba97 EC |
207 | struct wr_list { |
208 | u16 opcode; | |
209 | u16 next; | |
210 | }; | |
211 | ||
212 | struct mlx5_ib_wq { | |
213 | u64 *wrid; | |
214 | u32 *wr_data; | |
215 | struct wr_list *w_list; | |
216 | unsigned *wqe_head; | |
217 | u16 unsig_count; | |
218 | ||
219 | /* serialize post to the work queue | |
220 | */ | |
221 | spinlock_t lock; | |
222 | int wqe_cnt; | |
223 | int max_post; | |
224 | int max_gs; | |
225 | int offset; | |
226 | int wqe_shift; | |
227 | unsigned head; | |
228 | unsigned tail; | |
229 | u16 cur_post; | |
230 | u16 last_poll; | |
231 | void *qend; | |
232 | }; | |
233 | ||
79b20a6c YH |
234 | struct mlx5_ib_rwq { |
235 | struct ib_wq ibwq; | |
350d0e4c | 236 | struct mlx5_core_qp core_qp; |
79b20a6c YH |
237 | u32 rq_num_pas; |
238 | u32 log_rq_stride; | |
239 | u32 log_rq_size; | |
240 | u32 rq_page_offset; | |
241 | u32 log_page_size; | |
242 | struct ib_umem *umem; | |
243 | size_t buf_size; | |
244 | unsigned int page_shift; | |
245 | int create_type; | |
246 | struct mlx5_db db; | |
247 | u32 user_index; | |
248 | u32 wqe_count; | |
249 | u32 wqe_shift; | |
250 | int wq_sig; | |
251 | }; | |
252 | ||
e126ba97 EC |
253 | enum { |
254 | MLX5_QP_USER, | |
255 | MLX5_QP_KERNEL, | |
256 | MLX5_QP_EMPTY | |
257 | }; | |
258 | ||
79b20a6c YH |
259 | enum { |
260 | MLX5_WQ_USER, | |
261 | MLX5_WQ_KERNEL | |
262 | }; | |
263 | ||
c5f90929 YH |
264 | struct mlx5_ib_rwq_ind_table { |
265 | struct ib_rwq_ind_table ib_rwq_ind_tbl; | |
266 | u32 rqtn; | |
267 | }; | |
268 | ||
6aec21f6 HE |
269 | /* |
270 | * Connect-IB can trigger up to four concurrent pagefaults | |
271 | * per-QP. | |
272 | */ | |
273 | enum mlx5_ib_pagefault_context { | |
274 | MLX5_IB_PAGEFAULT_RESPONDER_READ, | |
275 | MLX5_IB_PAGEFAULT_REQUESTOR_READ, | |
276 | MLX5_IB_PAGEFAULT_RESPONDER_WRITE, | |
277 | MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, | |
278 | MLX5_IB_PAGEFAULT_CONTEXTS | |
279 | }; | |
280 | ||
281 | static inline enum mlx5_ib_pagefault_context | |
282 | mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) | |
283 | { | |
284 | return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); | |
285 | } | |
286 | ||
287 | struct mlx5_ib_pfault { | |
288 | struct work_struct work; | |
289 | struct mlx5_pagefault mpfault; | |
290 | }; | |
291 | ||
19098df2 | 292 | struct mlx5_ib_ubuffer { |
293 | struct ib_umem *umem; | |
294 | int buf_size; | |
295 | u64 buf_addr; | |
296 | }; | |
297 | ||
298 | struct mlx5_ib_qp_base { | |
299 | struct mlx5_ib_qp *container_mibqp; | |
300 | struct mlx5_core_qp mqp; | |
301 | struct mlx5_ib_ubuffer ubuffer; | |
302 | }; | |
303 | ||
304 | struct mlx5_ib_qp_trans { | |
305 | struct mlx5_ib_qp_base base; | |
306 | u16 xrcdn; | |
307 | u8 alt_port; | |
308 | u8 atomic_rd_en; | |
309 | u8 resp_depth; | |
310 | }; | |
311 | ||
28d61370 YH |
312 | struct mlx5_ib_rss_qp { |
313 | u32 tirn; | |
314 | }; | |
315 | ||
038d2ef8 | 316 | struct mlx5_ib_rq { |
0fb2ed66 | 317 | struct mlx5_ib_qp_base base; |
318 | struct mlx5_ib_wq *rq; | |
319 | struct mlx5_ib_ubuffer ubuffer; | |
320 | struct mlx5_db *doorbell; | |
038d2ef8 | 321 | u32 tirn; |
0fb2ed66 | 322 | u8 state; |
323 | }; | |
324 | ||
325 | struct mlx5_ib_sq { | |
326 | struct mlx5_ib_qp_base base; | |
327 | struct mlx5_ib_wq *sq; | |
328 | struct mlx5_ib_ubuffer ubuffer; | |
329 | struct mlx5_db *doorbell; | |
330 | u32 tisn; | |
331 | u8 state; | |
038d2ef8 MG |
332 | }; |
333 | ||
334 | struct mlx5_ib_raw_packet_qp { | |
0fb2ed66 | 335 | struct mlx5_ib_sq sq; |
038d2ef8 MG |
336 | struct mlx5_ib_rq rq; |
337 | }; | |
338 | ||
e126ba97 EC |
339 | struct mlx5_ib_qp { |
340 | struct ib_qp ibqp; | |
038d2ef8 | 341 | union { |
0fb2ed66 | 342 | struct mlx5_ib_qp_trans trans_qp; |
343 | struct mlx5_ib_raw_packet_qp raw_packet_qp; | |
28d61370 | 344 | struct mlx5_ib_rss_qp rss_qp; |
038d2ef8 | 345 | }; |
e126ba97 EC |
346 | struct mlx5_buf buf; |
347 | ||
348 | struct mlx5_db db; | |
349 | struct mlx5_ib_wq rq; | |
350 | ||
e126ba97 EC |
351 | u8 sq_signal_bits; |
352 | u8 fm_cache; | |
e126ba97 EC |
353 | struct mlx5_ib_wq sq; |
354 | ||
e126ba97 EC |
355 | /* serialize qp state modifications |
356 | */ | |
357 | struct mutex mutex; | |
e126ba97 EC |
358 | u32 flags; |
359 | u8 port; | |
e126ba97 | 360 | u8 state; |
e126ba97 EC |
361 | int wq_sig; |
362 | int scat_cqe; | |
363 | int max_inline_data; | |
364 | struct mlx5_bf *bf; | |
365 | int has_rq; | |
366 | ||
367 | /* only for user space QPs. For kernel | |
368 | * we have it from the bf object | |
369 | */ | |
370 | int uuarn; | |
371 | ||
372 | int create_type; | |
e1e66cc2 SG |
373 | |
374 | /* Store signature errors */ | |
375 | bool signature_en; | |
6aec21f6 HE |
376 | |
377 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
378 | /* | |
379 | * A flag that is true for QP's that are in a state that doesn't | |
380 | * allow page faults, and shouldn't schedule any more faults. | |
381 | */ | |
382 | int disable_page_faults; | |
383 | /* | |
384 | * The disable_page_faults_lock protects a QP's disable_page_faults | |
385 | * field, allowing for a thread to atomically check whether the QP | |
386 | * allows page faults, and if so schedule a page fault. | |
387 | */ | |
388 | spinlock_t disable_page_faults_lock; | |
389 | struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; | |
390 | #endif | |
89ea94a7 MG |
391 | struct list_head qps_list; |
392 | struct list_head cq_recv_list; | |
393 | struct list_head cq_send_list; | |
7d29f349 | 394 | u32 rate_limit; |
e126ba97 EC |
395 | }; |
396 | ||
397 | struct mlx5_ib_cq_buf { | |
398 | struct mlx5_buf buf; | |
399 | struct ib_umem *umem; | |
400 | int cqe_size; | |
bde51583 | 401 | int nent; |
e126ba97 EC |
402 | }; |
403 | ||
404 | enum mlx5_ib_qp_flags { | |
f0313965 ES |
405 | MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, |
406 | MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, | |
407 | MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, | |
408 | MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, | |
409 | MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, | |
410 | MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, | |
b11a4f9c HE |
411 | /* QP uses 1 as its source QP number */ |
412 | MLX5_IB_QP_SQPN_QP1 = 1 << 6, | |
358e42ea | 413 | MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, |
d9f88e5a | 414 | MLX5_IB_QP_RSS = 1 << 8, |
e126ba97 EC |
415 | }; |
416 | ||
968e78dd | 417 | struct mlx5_umr_wr { |
e622f2f4 | 418 | struct ib_send_wr wr; |
31616255 AK |
419 | u64 virt_addr; |
420 | u64 offset; | |
968e78dd HE |
421 | struct ib_pd *pd; |
422 | unsigned int page_shift; | |
31616255 | 423 | unsigned int xlt_size; |
b216af40 | 424 | u64 length; |
968e78dd HE |
425 | int access_flags; |
426 | u32 mkey; | |
427 | }; | |
428 | ||
e622f2f4 CH |
429 | static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) |
430 | { | |
431 | return container_of(wr, struct mlx5_umr_wr, wr); | |
432 | } | |
433 | ||
e126ba97 EC |
434 | struct mlx5_shared_mr_info { |
435 | int mr_id; | |
436 | struct ib_umem *umem; | |
437 | }; | |
438 | ||
439 | struct mlx5_ib_cq { | |
440 | struct ib_cq ibcq; | |
441 | struct mlx5_core_cq mcq; | |
442 | struct mlx5_ib_cq_buf buf; | |
443 | struct mlx5_db db; | |
444 | ||
445 | /* serialize access to the CQ | |
446 | */ | |
447 | spinlock_t lock; | |
448 | ||
449 | /* protect resize cq | |
450 | */ | |
451 | struct mutex resize_mutex; | |
bde51583 | 452 | struct mlx5_ib_cq_buf *resize_buf; |
e126ba97 EC |
453 | struct ib_umem *resize_umem; |
454 | int cqe_size; | |
89ea94a7 MG |
455 | struct list_head list_send_qp; |
456 | struct list_head list_recv_qp; | |
051f2630 | 457 | u32 create_flags; |
25361e02 HE |
458 | struct list_head wc_list; |
459 | enum ib_cq_notify_flags notify_flags; | |
460 | struct work_struct notify_work; | |
461 | }; | |
462 | ||
463 | struct mlx5_ib_wc { | |
464 | struct ib_wc wc; | |
465 | struct list_head list; | |
e126ba97 EC |
466 | }; |
467 | ||
468 | struct mlx5_ib_srq { | |
469 | struct ib_srq ibsrq; | |
470 | struct mlx5_core_srq msrq; | |
471 | struct mlx5_buf buf; | |
472 | struct mlx5_db db; | |
473 | u64 *wrid; | |
474 | /* protect SRQ hanlding | |
475 | */ | |
476 | spinlock_t lock; | |
477 | int head; | |
478 | int tail; | |
479 | u16 wqe_ctr; | |
480 | struct ib_umem *umem; | |
481 | /* serialize arming a SRQ | |
482 | */ | |
483 | struct mutex mutex; | |
484 | int wq_sig; | |
485 | }; | |
486 | ||
487 | struct mlx5_ib_xrcd { | |
488 | struct ib_xrcd ibxrcd; | |
489 | u32 xrcdn; | |
490 | }; | |
491 | ||
cc149f75 HE |
492 | enum mlx5_ib_mtt_access_flags { |
493 | MLX5_IB_MTT_READ = (1 << 0), | |
494 | MLX5_IB_MTT_WRITE = (1 << 1), | |
495 | }; | |
496 | ||
497 | #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) | |
498 | ||
e126ba97 EC |
499 | struct mlx5_ib_mr { |
500 | struct ib_mr ibmr; | |
8a187ee5 SG |
501 | void *descs; |
502 | dma_addr_t desc_map; | |
503 | int ndescs; | |
504 | int max_descs; | |
505 | int desc_size; | |
b005d316 | 506 | int access_mode; |
a606b0f6 | 507 | struct mlx5_core_mkey mmkey; |
e126ba97 EC |
508 | struct ib_umem *umem; |
509 | struct mlx5_shared_mr_info *smr_info; | |
510 | struct list_head list; | |
511 | int order; | |
512 | int umred; | |
e126ba97 | 513 | int npages; |
746b5583 | 514 | struct mlx5_ib_dev *dev; |
ec22eb53 | 515 | u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; |
3121e3c4 | 516 | struct mlx5_core_sig_ctx *sig; |
b4cfe447 | 517 | int live; |
8a187ee5 | 518 | void *descs_alloc; |
56e11d62 | 519 | int access_flags; /* Needed for rereg MR */ |
e126ba97 EC |
520 | }; |
521 | ||
d2370e0a MB |
522 | struct mlx5_ib_mw { |
523 | struct ib_mw ibmw; | |
524 | struct mlx5_core_mkey mmkey; | |
e126ba97 EC |
525 | }; |
526 | ||
a74d2416 | 527 | struct mlx5_ib_umr_context { |
add08d76 | 528 | struct ib_cqe cqe; |
a74d2416 SR |
529 | enum ib_wc_status status; |
530 | struct completion done; | |
531 | }; | |
532 | ||
e126ba97 EC |
533 | struct umr_common { |
534 | struct ib_pd *pd; | |
535 | struct ib_cq *cq; | |
536 | struct ib_qp *qp; | |
e126ba97 EC |
537 | /* control access to UMR QP |
538 | */ | |
539 | struct semaphore sem; | |
540 | }; | |
541 | ||
542 | enum { | |
543 | MLX5_FMR_INVALID, | |
544 | MLX5_FMR_VALID, | |
545 | MLX5_FMR_BUSY, | |
546 | }; | |
547 | ||
e126ba97 EC |
548 | struct mlx5_cache_ent { |
549 | struct list_head head; | |
550 | /* sync access to the cahce entry | |
551 | */ | |
552 | spinlock_t lock; | |
553 | ||
554 | ||
555 | struct dentry *dir; | |
556 | char name[4]; | |
557 | u32 order; | |
558 | u32 size; | |
559 | u32 cur; | |
560 | u32 miss; | |
561 | u32 limit; | |
562 | ||
563 | struct dentry *fsize; | |
564 | struct dentry *fcur; | |
565 | struct dentry *fmiss; | |
566 | struct dentry *flimit; | |
567 | ||
568 | struct mlx5_ib_dev *dev; | |
569 | struct work_struct work; | |
570 | struct delayed_work dwork; | |
746b5583 | 571 | int pending; |
e126ba97 EC |
572 | }; |
573 | ||
574 | struct mlx5_mr_cache { | |
575 | struct workqueue_struct *wq; | |
576 | struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; | |
577 | int stopped; | |
578 | struct dentry *root; | |
579 | unsigned long last_add; | |
580 | }; | |
581 | ||
d16e91da HE |
582 | struct mlx5_ib_gsi_qp; |
583 | ||
584 | struct mlx5_ib_port_resources { | |
7722f47e | 585 | struct mlx5_ib_resources *devr; |
d16e91da | 586 | struct mlx5_ib_gsi_qp *gsi; |
7722f47e | 587 | struct work_struct pkey_change_work; |
d16e91da HE |
588 | }; |
589 | ||
e126ba97 EC |
590 | struct mlx5_ib_resources { |
591 | struct ib_cq *c0; | |
592 | struct ib_xrcd *x0; | |
593 | struct ib_xrcd *x1; | |
594 | struct ib_pd *p0; | |
595 | struct ib_srq *s0; | |
4aa17b28 | 596 | struct ib_srq *s1; |
d16e91da HE |
597 | struct mlx5_ib_port_resources ports[2]; |
598 | /* Protects changes to the port resources */ | |
599 | struct mutex mutex; | |
e126ba97 EC |
600 | }; |
601 | ||
0837e86a MB |
602 | struct mlx5_ib_port { |
603 | u16 q_cnt_id; | |
604 | }; | |
605 | ||
fc24fc5e AS |
606 | struct mlx5_roce { |
607 | /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL | |
608 | * netdev pointer | |
609 | */ | |
610 | rwlock_t netdev_lock; | |
611 | struct net_device *netdev; | |
612 | struct notifier_block nb; | |
13eab21f | 613 | atomic_t next_port; |
fc24fc5e AS |
614 | }; |
615 | ||
e126ba97 EC |
616 | struct mlx5_ib_dev { |
617 | struct ib_device ib_dev; | |
9603b61d | 618 | struct mlx5_core_dev *mdev; |
fc24fc5e | 619 | struct mlx5_roce roce; |
e126ba97 | 620 | MLX5_DECLARE_DOORBELL_LOCK(uar_lock); |
e126ba97 | 621 | int num_ports; |
e126ba97 EC |
622 | /* serialize update of capability mask |
623 | */ | |
624 | struct mutex cap_mask_mutex; | |
625 | bool ib_active; | |
626 | struct umr_common umrc; | |
627 | /* sync used page count stats | |
628 | */ | |
e126ba97 EC |
629 | struct mlx5_ib_resources devr; |
630 | struct mlx5_mr_cache cache; | |
746b5583 | 631 | struct timer_list delay_timer; |
6bc1a656 ML |
632 | /* Prevents soft lock on massive reg MRs */ |
633 | struct mutex slow_path_mutex; | |
746b5583 | 634 | int fill_delay; |
8cdd312c HE |
635 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
636 | struct ib_odp_caps odp_caps; | |
6aec21f6 HE |
637 | /* |
638 | * Sleepable RCU that prevents destruction of MRs while they are still | |
639 | * being used by a page fault handler. | |
640 | */ | |
641 | struct srcu_struct mr_srcu; | |
8cdd312c | 642 | #endif |
038d2ef8 | 643 | struct mlx5_ib_flow_db flow_db; |
89ea94a7 MG |
644 | /* protect resources needed as part of reset flow */ |
645 | spinlock_t reset_flow_resource_lock; | |
646 | struct list_head qp_list; | |
0837e86a MB |
647 | /* Array with num_ports elements */ |
648 | struct mlx5_ib_port *port; | |
e126ba97 EC |
649 | }; |
650 | ||
651 | static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) | |
652 | { | |
653 | return container_of(mcq, struct mlx5_ib_cq, mcq); | |
654 | } | |
655 | ||
656 | static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) | |
657 | { | |
658 | return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); | |
659 | } | |
660 | ||
661 | static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) | |
662 | { | |
663 | return container_of(ibdev, struct mlx5_ib_dev, ib_dev); | |
664 | } | |
665 | ||
e126ba97 EC |
666 | static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) |
667 | { | |
668 | return container_of(ibcq, struct mlx5_ib_cq, ibcq); | |
669 | } | |
670 | ||
671 | static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) | |
672 | { | |
19098df2 | 673 | return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; |
e126ba97 EC |
674 | } |
675 | ||
350d0e4c YH |
676 | static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) |
677 | { | |
678 | return container_of(core_qp, struct mlx5_ib_rwq, core_qp); | |
679 | } | |
680 | ||
a606b0f6 | 681 | static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) |
d5436ba0 | 682 | { |
a606b0f6 | 683 | return container_of(mmkey, struct mlx5_ib_mr, mmkey); |
d5436ba0 SG |
684 | } |
685 | ||
e126ba97 EC |
686 | static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) |
687 | { | |
688 | return container_of(ibpd, struct mlx5_ib_pd, ibpd); | |
689 | } | |
690 | ||
691 | static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) | |
692 | { | |
693 | return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); | |
694 | } | |
695 | ||
696 | static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) | |
697 | { | |
698 | return container_of(ibqp, struct mlx5_ib_qp, ibqp); | |
699 | } | |
700 | ||
79b20a6c YH |
701 | static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) |
702 | { | |
703 | return container_of(ibwq, struct mlx5_ib_rwq, ibwq); | |
704 | } | |
705 | ||
c5f90929 YH |
706 | static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) |
707 | { | |
708 | return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); | |
709 | } | |
710 | ||
e126ba97 EC |
711 | static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) |
712 | { | |
713 | return container_of(msrq, struct mlx5_ib_srq, msrq); | |
714 | } | |
715 | ||
716 | static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) | |
717 | { | |
718 | return container_of(ibmr, struct mlx5_ib_mr, ibmr); | |
719 | } | |
720 | ||
d2370e0a MB |
721 | static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) |
722 | { | |
723 | return container_of(ibmw, struct mlx5_ib_mw, ibmw); | |
724 | } | |
725 | ||
e126ba97 EC |
726 | struct mlx5_ib_ah { |
727 | struct ib_ah ibah; | |
728 | struct mlx5_av av; | |
729 | }; | |
730 | ||
731 | static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) | |
732 | { | |
733 | return container_of(ibah, struct mlx5_ib_ah, ibah); | |
734 | } | |
735 | ||
e126ba97 EC |
736 | int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, |
737 | struct mlx5_db *db); | |
738 | void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); | |
739 | void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); | |
740 | void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); | |
741 | void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); | |
742 | int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, | |
a97e2d86 IW |
743 | u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
744 | const void *in_mad, void *response_mad); | |
477864c8 MS |
745 | struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr, |
746 | struct ib_udata *udata); | |
e126ba97 EC |
747 | int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); |
748 | int mlx5_ib_destroy_ah(struct ib_ah *ah); | |
749 | struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, | |
750 | struct ib_srq_init_attr *init_attr, | |
751 | struct ib_udata *udata); | |
752 | int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, | |
753 | enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); | |
754 | int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); | |
755 | int mlx5_ib_destroy_srq(struct ib_srq *srq); | |
756 | int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, | |
757 | struct ib_recv_wr **bad_wr); | |
758 | struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, | |
759 | struct ib_qp_init_attr *init_attr, | |
760 | struct ib_udata *udata); | |
761 | int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
762 | int attr_mask, struct ib_udata *udata); | |
763 | int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, | |
764 | struct ib_qp_init_attr *qp_init_attr); | |
765 | int mlx5_ib_destroy_qp(struct ib_qp *qp); | |
766 | int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |
767 | struct ib_send_wr **bad_wr); | |
768 | int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, | |
769 | struct ib_recv_wr **bad_wr); | |
770 | void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); | |
c1395a2a | 771 | int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, |
19098df2 | 772 | void *buffer, u32 length, |
773 | struct mlx5_ib_qp_base *base); | |
bcf4c1ea MB |
774 | struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, |
775 | const struct ib_cq_init_attr *attr, | |
776 | struct ib_ucontext *context, | |
e126ba97 EC |
777 | struct ib_udata *udata); |
778 | int mlx5_ib_destroy_cq(struct ib_cq *cq); | |
779 | int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); | |
780 | int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); | |
781 | int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); | |
782 | int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); | |
783 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); | |
784 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
785 | u64 virt_addr, int access_flags, | |
786 | struct ib_udata *udata); | |
d2370e0a MB |
787 | struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
788 | struct ib_udata *udata); | |
789 | int mlx5_ib_dealloc_mw(struct ib_mw *mw); | |
832a6b06 HE |
790 | int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, |
791 | int npages, int zap); | |
56e11d62 NO |
792 | int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, |
793 | u64 length, u64 virt_addr, int access_flags, | |
794 | struct ib_pd *pd, struct ib_udata *udata); | |
e126ba97 | 795 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr); |
9bee178b SG |
796 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, |
797 | enum ib_mr_type mr_type, | |
798 | u32 max_num_sg); | |
ff2ba993 | 799 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 800 | unsigned int *sg_offset); |
e126ba97 | 801 | int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, |
a97e2d86 | 802 | const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
4cd7c947 IW |
803 | const struct ib_mad_hdr *in, size_t in_mad_size, |
804 | struct ib_mad_hdr *out, size_t *out_mad_size, | |
805 | u16 *out_mad_pkey_index); | |
e126ba97 EC |
806 | struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, |
807 | struct ib_ucontext *context, | |
808 | struct ib_udata *udata); | |
809 | int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); | |
e126ba97 EC |
810 | int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); |
811 | int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); | |
1b5daf11 MD |
812 | int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, |
813 | struct ib_smp *out_mad); | |
814 | int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, | |
815 | __be64 *sys_image_guid); | |
816 | int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, | |
817 | u16 *max_pkeys); | |
818 | int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, | |
819 | u32 *vendor_id); | |
820 | int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); | |
821 | int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); | |
822 | int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, | |
823 | u16 *pkey); | |
824 | int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, | |
825 | union ib_gid *gid); | |
826 | int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, | |
827 | struct ib_port_attr *props); | |
e126ba97 EC |
828 | int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, |
829 | struct ib_port_attr *props); | |
830 | int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); | |
831 | void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); | |
762f899a MD |
832 | void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, |
833 | unsigned long max_page_shift, | |
834 | int *count, int *shift, | |
e126ba97 | 835 | int *ncont, int *order); |
832a6b06 HE |
836 | void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, |
837 | int page_shift, size_t offset, size_t num_pages, | |
838 | __be64 *pas, int access_flags); | |
e126ba97 | 839 | void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, |
cc149f75 | 840 | int page_shift, __be64 *pas, int access_flags); |
e126ba97 EC |
841 | void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); |
842 | int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); | |
843 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); | |
844 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); | |
845 | int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); | |
d5436ba0 SG |
846 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
847 | struct ib_mr_status *mr_status); | |
79b20a6c YH |
848 | struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, |
849 | struct ib_wq_init_attr *init_attr, | |
850 | struct ib_udata *udata); | |
851 | int mlx5_ib_destroy_wq(struct ib_wq *wq); | |
852 | int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, | |
853 | u32 wq_attr_mask, struct ib_udata *udata); | |
c5f90929 YH |
854 | struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, |
855 | struct ib_rwq_ind_table_init_attr *init_attr, | |
856 | struct ib_udata *udata); | |
857 | int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); | |
e126ba97 | 858 | |
8cdd312c | 859 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
6aec21f6 HE |
860 | extern struct workqueue_struct *mlx5_ib_page_fault_wq; |
861 | ||
938fe83c | 862 | void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); |
6aec21f6 HE |
863 | void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, |
864 | struct mlx5_ib_pfault *pfault); | |
865 | void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); | |
866 | int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); | |
867 | void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); | |
868 | int __init mlx5_ib_odp_init(void); | |
869 | void mlx5_ib_odp_cleanup(void); | |
870 | void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); | |
871 | void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); | |
b4cfe447 HE |
872 | void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, |
873 | unsigned long end); | |
6aec21f6 | 874 | #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ |
938fe83c | 875 | static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) |
8cdd312c | 876 | { |
938fe83c | 877 | return; |
8cdd312c | 878 | } |
6aec21f6 HE |
879 | |
880 | static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} | |
881 | static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } | |
882 | static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} | |
883 | static inline int mlx5_ib_odp_init(void) { return 0; } | |
884 | static inline void mlx5_ib_odp_cleanup(void) {} | |
885 | static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} | |
886 | static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} | |
887 | ||
8cdd312c HE |
888 | #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ |
889 | ||
9967c70a AB |
890 | int mlx5_ib_get_vf_config(struct ib_device *device, int vf, |
891 | u8 port, struct ifla_vf_info *info); | |
892 | int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, | |
893 | u8 port, int state); | |
894 | int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, | |
895 | u8 port, struct ifla_vf_stats *stats); | |
896 | int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, | |
897 | u64 guid, int type); | |
898 | ||
2811ba51 AS |
899 | __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, |
900 | int index); | |
901 | ||
d16e91da HE |
902 | /* GSI QP helper functions */ |
903 | struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, | |
904 | struct ib_qp_init_attr *init_attr); | |
905 | int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); | |
906 | int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, | |
907 | int attr_mask); | |
908 | int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, | |
909 | int qp_attr_mask, | |
910 | struct ib_qp_init_attr *qp_init_attr); | |
911 | int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, | |
912 | struct ib_send_wr **bad_wr); | |
913 | int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, | |
914 | struct ib_recv_wr **bad_wr); | |
7722f47e | 915 | void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); |
d16e91da | 916 | |
25361e02 HE |
917 | int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); |
918 | ||
e126ba97 EC |
919 | static inline void init_query_mad(struct ib_smp *mad) |
920 | { | |
921 | mad->base_version = 1; | |
922 | mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; | |
923 | mad->class_version = 1; | |
924 | mad->method = IB_MGMT_METHOD_GET; | |
925 | } | |
926 | ||
927 | static inline u8 convert_access(int acc) | |
928 | { | |
929 | return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | | |
930 | (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | | |
931 | (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | | |
932 | (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | | |
933 | MLX5_PERM_LOCAL_READ; | |
934 | } | |
935 | ||
b636401f SG |
936 | static inline int is_qp1(enum ib_qp_type qp_type) |
937 | { | |
d16e91da | 938 | return qp_type == MLX5_IB_QPT_HW_GSI; |
b636401f SG |
939 | } |
940 | ||
cc149f75 HE |
941 | #define MLX5_MAX_UMR_SHIFT 16 |
942 | #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) | |
943 | ||
051f2630 LR |
944 | static inline u32 check_cq_create_flags(u32 flags) |
945 | { | |
946 | /* | |
947 | * It returns non-zero value for unsupported CQ | |
948 | * create flags, otherwise it returns zero. | |
949 | */ | |
34356f64 LR |
950 | return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | |
951 | IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); | |
051f2630 | 952 | } |
cfb5e088 HA |
953 | |
954 | static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, | |
955 | u32 *user_index) | |
956 | { | |
957 | if (cqe_version) { | |
958 | if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || | |
959 | (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) | |
960 | return -EINVAL; | |
961 | *user_index = cmd_uidx; | |
962 | } else { | |
963 | *user_index = MLX5_IB_DEFAULT_UIDX; | |
964 | } | |
965 | ||
966 | return 0; | |
967 | } | |
3085e29e LR |
968 | |
969 | static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, | |
970 | struct mlx5_ib_create_qp *ucmd, | |
971 | int inlen, | |
972 | u32 *user_index) | |
973 | { | |
974 | u8 cqe_version = ucontext->cqe_version; | |
975 | ||
976 | if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && | |
977 | !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) | |
978 | return 0; | |
979 | ||
980 | if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != | |
981 | !!cqe_version)) | |
982 | return -EINVAL; | |
983 | ||
984 | return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); | |
985 | } | |
986 | ||
987 | static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, | |
988 | struct mlx5_ib_create_srq *ucmd, | |
989 | int inlen, | |
990 | u32 *user_index) | |
991 | { | |
992 | u8 cqe_version = ucontext->cqe_version; | |
993 | ||
994 | if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && | |
995 | !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) | |
996 | return 0; | |
997 | ||
998 | if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != | |
999 | !!cqe_version)) | |
1000 | return -EINVAL; | |
1001 | ||
1002 | return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); | |
1003 | } | |
e126ba97 | 1004 | #endif /* MLX5_IB_H */ |