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IB/rxe: Make rxe_counter_name static
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
7c2344c3 53#include <linux/list.h>
e126ba97
EC		 54#include <rdma/ib_smi.h>
55#include <rdma/ib_umem.h>
038d2ef8
MG		 56#include <linux/in.h>
57#include <linux/etherdevice.h>
58#include <linux/mlx5/fs.h>
78984898 59#include <linux/mlx5/vport.h>
e126ba97 60#include "mlx5_ib.h"
e1f24a79 61#include "cmd.h"
c85023e1 62#include <linux/mlx5/vport.h>
e126ba97
EC		 63
64#define DRIVER_NAME "mlx5_ib"
b359911d 65#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 66
67MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
68MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
69MODULE_LICENSE("Dual BSD/GPL");
e126ba97 70
e126ba97
EC		 71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 73 DRIVER_VERSION "\n";
e126ba97 74
da7525d2
EBE		 75enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77};
78
1b5daf11 79static enum rdma_link_layer
ebd61f68 80mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 81{
ebd61f68 82 switch (port_type_cap) {
1b5daf11
MD		 83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90}
91
ebd61f68
AS		 92static enum rdma_link_layer
93mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94{
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99}
100
fd65f1b8
MS		 101static int get_port_state(struct ib_device *ibdev,
102 u8 port_num,
103 enum ib_port_state *state)
104{
105 struct ib_port_attr attr;
106 int ret;
107
108 memset(&attr, 0, sizeof(attr));
109 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
110 if (!ret)
111 *state = attr.state;
112 return ret;
113}
114
fc24fc5e
AS		 115static int mlx5_netdev_event(struct notifier_block *this,
116 unsigned long event, void *ptr)
117{
118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
120 roce.nb);
121
5ec8c83e
AH		 122 switch (event) {
123 case NETDEV_REGISTER:
124 case NETDEV_UNREGISTER:
125 write_lock(&ibdev->roce.netdev_lock);
126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
128 NULL : ndev;
129 write_unlock(&ibdev->roce.netdev_lock);
130 break;
fc24fc5e 131
fd65f1b8 132 case NETDEV_CHANGE:
5ec8c83e 133 case NETDEV_UP:
88621dfe
AH		 134 case NETDEV_DOWN: {
135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
136 struct net_device *upper = NULL;
137
138 if (lag_ndev) {
139 upper = netdev_master_upper_dev_get(lag_ndev);
140 dev_put(lag_ndev);
141 }
142
143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
144 && ibdev->ib_active) {
626bc02d 145 struct ib_event ibev = { };
fd65f1b8 146 enum ib_port_state port_state;
5ec8c83e 147
fd65f1b8
MS		 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state))
149 return NOTIFY_DONE;
150
151 if (ibdev->roce.last_port_state == port_state)
152 return NOTIFY_DONE;
153
154 ibdev->roce.last_port_state = port_state;
5ec8c83e 155 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 156 if (port_state == IB_PORT_DOWN)
157 ibev.event = IB_EVENT_PORT_ERR;
158 else if (port_state == IB_PORT_ACTIVE)
159 ibev.event = IB_EVENT_PORT_ACTIVE;
160 else
161 return NOTIFY_DONE;
162
5ec8c83e
AH		 163 ibev.element.port_num = 1;
164 ib_dispatch_event(&ibev);
165 }
166 break;
88621dfe 167 }
fc24fc5e 168
5ec8c83e
AH		 169 default:
170 break;
171 }
fc24fc5e
AS		 172
173 return NOTIFY_DONE;
174}
175
176static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
177 u8 port_num)
178{
179 struct mlx5_ib_dev *ibdev = to_mdev(device);
180 struct net_device *ndev;
181
88621dfe
AH		 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
183 if (ndev)
184 return ndev;
185
fc24fc5e
AS		 186 /* Ensure ndev does not disappear before we invoke dev_hold()
187 */
188 read_lock(&ibdev->roce.netdev_lock);
189 ndev = ibdev->roce.netdev;
190 if (ndev)
191 dev_hold(ndev);
192 read_unlock(&ibdev->roce.netdev_lock);
193
194 return ndev;
195}
196
f1b65df5
NO		 197static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
198 u8 *active_width)
199{
200 switch (eth_proto_oper) {
201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_SDR;
207 break;
208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
215 *active_width = IB_WIDTH_1X;
216 *active_speed = IB_SPEED_QDR;
217 break;
218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
221 *active_width = IB_WIDTH_1X;
222 *active_speed = IB_SPEED_EDR;
223 break;
224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
228 *active_width = IB_WIDTH_4X;
229 *active_speed = IB_SPEED_QDR;
230 break;
231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
234 *active_width = IB_WIDTH_1X;
235 *active_speed = IB_SPEED_HDR;
236 break;
237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
238 *active_width = IB_WIDTH_4X;
239 *active_speed = IB_SPEED_FDR;
240 break;
241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
245 *active_width = IB_WIDTH_4X;
246 *active_speed = IB_SPEED_EDR;
247 break;
248 default:
249 return -EINVAL;
250 }
251
252 return 0;
253}
254
095b0927
IT		 255static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
256 struct ib_port_attr *props)
3f89a643
AS		 257{
258 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 259 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 260 struct net_device *ndev, *upper;
3f89a643 261 enum ib_mtu ndev_ib_mtu;
c876a1b7 262 u16 qkey_viol_cntr;
f1b65df5 263 u32 eth_prot_oper;
095b0927 264 int err;
3f89a643 265
f1b65df5
NO		 266 /* Possible bad flows are checked before filling out props so in case
267 * of an error it will still be zeroed out.
50f22fd8 268 */
095b0927
IT		 269 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
270 if (err)
271 return err;
f1b65df5
NO		 272
273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
274 &props->active_width);
3f89a643
AS		 275
276 props->port_cap_flags |= IB_PORT_CM_SUP;
277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
278
279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
280 roce_address_table_size);
281 props->max_mtu = IB_MTU_4096;
282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
283 props->pkey_tbl_len = 1;
284 props->state = IB_PORT_DOWN;
285 props->phys_state = 3;
286
c876a1b7
LR		 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
288 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 289
290 ndev = mlx5_ib_get_netdev(device, port_num);
291 if (!ndev)
095b0927 292 return 0;
3f89a643 293
88621dfe
AH		 294 if (mlx5_lag_is_active(dev->mdev)) {
295 rcu_read_lock();
296 upper = netdev_master_upper_dev_get_rcu(ndev);
297 if (upper) {
298 dev_put(ndev);
299 ndev = upper;
300 dev_hold(ndev);
301 }
302 rcu_read_unlock();
303 }
304
3f89a643
AS		 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
306 props->state = IB_PORT_ACTIVE;
307 props->phys_state = 5;
308 }
309
310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
311
312 dev_put(ndev);
313
314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 315 return 0;
3f89a643
AS		 316}
317
095b0927
IT		 318static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
319 unsigned int index, const union ib_gid *gid,
320 const struct ib_gid_attr *attr)
3cca2606 321{
095b0927
IT		 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
323 u8 roce_version = 0;
324 u8 roce_l3_type = 0;
325 bool vlan = false;
326 u8 mac[ETH_ALEN];
327 u16 vlan_id = 0;
328
329 if (gid) {
330 gid_type = attr->gid_type;
331 ether_addr_copy(mac, attr->ndev->dev_addr);
332
333 if (is_vlan_dev(attr->ndev)) {
334 vlan = true;
335 vlan_id = vlan_dev_vlan_id(attr->ndev);
336 }
3cca2606
AS		 337 }
338
095b0927 339 switch (gid_type) {
3cca2606 340 case IB_GID_TYPE_IB:
095b0927 341 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 342 break;
343 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 344 roce_version = MLX5_ROCE_VERSION_2;
345 if (ipv6_addr_v4mapped((void *)gid))
346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
347 else
348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 349 break;
350
351 default:
095b0927 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 353 }
354
095b0927
IT		 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
356 roce_l3_type, gid->raw, mac, vlan,
357 vlan_id);
3cca2606
AS		 358}
359
360static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
361 unsigned int index, const union ib_gid *gid,
362 const struct ib_gid_attr *attr,
363 __always_unused void **context)
364{
095b0927 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 366}
367
368static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
369 unsigned int index, __always_unused void **context)
370{
095b0927 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 372}
373
2811ba51
AS		 374__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
375 int index)
376{
377 struct ib_gid_attr attr;
378 union ib_gid gid;
379
380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
381 return 0;
382
383 if (!attr.ndev)
384 return 0;
385
386 dev_put(attr.ndev);
387
388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
389 return 0;
390
391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
392}
393
ed88451e
MD		 394int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
395 int index, enum ib_gid_type *gid_type)
396{
397 struct ib_gid_attr attr;
398 union ib_gid gid;
399 int ret;
400
401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
402 if (ret)
403 return ret;
404
405 if (!attr.ndev)
406 return -ENODEV;
407
408 dev_put(attr.ndev);
409
410 *gid_type = attr.gid_type;
411
412 return 0;
413}
414
1b5daf11
MD		 415static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
416{
7fae6655
NO		 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
418 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
419 return 0;
1b5daf11
MD		 420}
421
422enum {
423 MLX5_VPORT_ACCESS_METHOD_MAD,
424 MLX5_VPORT_ACCESS_METHOD_HCA,
425 MLX5_VPORT_ACCESS_METHOD_NIC,
426};
427
428static int mlx5_get_vport_access_method(struct ib_device *ibdev)
429{
430 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
431 return MLX5_VPORT_ACCESS_METHOD_MAD;
432
ebd61f68 433 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 434 IB_LINK_LAYER_ETHERNET)
435 return MLX5_VPORT_ACCESS_METHOD_NIC;
436
437 return MLX5_VPORT_ACCESS_METHOD_HCA;
438}
439
da7525d2
EBE		 440static void get_atomic_caps(struct mlx5_ib_dev *dev,
441 struct ib_device_attr *props)
442{
443 u8 tmp;
444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
446 u8 atomic_req_8B_endianness_mode =
bd10838a 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 448
449 /* Check if HW supports 8 bytes standard atomic operations and capable
450 * of host endianness respond
451 */
452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
453 if (((atomic_operations & tmp) == tmp) &&
454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
455 (atomic_req_8B_endianness_mode)) {
456 props->atomic_cap = IB_ATOMIC_HCA;
457 } else {
458 props->atomic_cap = IB_ATOMIC_NONE;
459 }
460}
461
1b5daf11
MD		 462static int mlx5_query_system_image_guid(struct ib_device *ibdev,
463 __be64 *sys_image_guid)
464{
465 struct mlx5_ib_dev *dev = to_mdev(ibdev);
466 struct mlx5_core_dev *mdev = dev->mdev;
467 u64 tmp;
468 int err;
469
470 switch (mlx5_get_vport_access_method(ibdev)) {
471 case MLX5_VPORT_ACCESS_METHOD_MAD:
472 return mlx5_query_mad_ifc_system_image_guid(ibdev,
473 sys_image_guid);
474
475 case MLX5_VPORT_ACCESS_METHOD_HCA:
476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 477 break;
478
479 case MLX5_VPORT_ACCESS_METHOD_NIC:
480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
481 break;
1b5daf11
MD		 482
483 default:
484 return -EINVAL;
485 }
3f89a643
AS		 486
487 if (!err)
488 *sys_image_guid = cpu_to_be64(tmp);
489
490 return err;
491
1b5daf11
MD		 492}
493
494static int mlx5_query_max_pkeys(struct ib_device *ibdev,
495 u16 *max_pkeys)
496{
497 struct mlx5_ib_dev *dev = to_mdev(ibdev);
498 struct mlx5_core_dev *mdev = dev->mdev;
499
500 switch (mlx5_get_vport_access_method(ibdev)) {
501 case MLX5_VPORT_ACCESS_METHOD_MAD:
502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
503
504 case MLX5_VPORT_ACCESS_METHOD_HCA:
505 case MLX5_VPORT_ACCESS_METHOD_NIC:
506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
507 pkey_table_size));
508 return 0;
509
510 default:
511 return -EINVAL;
512 }
513}
514
515static int mlx5_query_vendor_id(struct ib_device *ibdev,
516 u32 *vendor_id)
517{
518 struct mlx5_ib_dev *dev = to_mdev(ibdev);
519
520 switch (mlx5_get_vport_access_method(ibdev)) {
521 case MLX5_VPORT_ACCESS_METHOD_MAD:
522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
523
524 case MLX5_VPORT_ACCESS_METHOD_HCA:
525 case MLX5_VPORT_ACCESS_METHOD_NIC:
526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
527
528 default:
529 return -EINVAL;
530 }
531}
532
533static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
534 __be64 *node_guid)
535{
536 u64 tmp;
537 int err;
538
539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
540 case MLX5_VPORT_ACCESS_METHOD_MAD:
541 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
542
543 case MLX5_VPORT_ACCESS_METHOD_HCA:
544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 545 break;
546
547 case MLX5_VPORT_ACCESS_METHOD_NIC:
548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
549 break;
1b5daf11
MD		 550
551 default:
552 return -EINVAL;
553 }
3f89a643
AS		 554
555 if (!err)
556 *node_guid = cpu_to_be64(tmp);
557
558 return err;
1b5daf11
MD		 559}
560
561struct mlx5_reg_node_desc {
bd99fdea 562 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 563};
564
565static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
566{
567 struct mlx5_reg_node_desc in;
568
569 if (mlx5_use_mad_ifc(dev))
570 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
571
572 memset(&in, 0, sizeof(in));
573
574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
575 sizeof(struct mlx5_reg_node_desc),
576 MLX5_REG_NODE_DESC, 0, 0);
577}
578
e126ba97 579static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 580 struct ib_device_attr *props,
581 struct ib_udata *uhw)
e126ba97
EC		 582{
583 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 584 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 585 int err = -ENOMEM;
288c01b7 586 int max_sq_desc;
e126ba97
EC		 587 int max_rq_sg;
588 int max_sq_sg;
e0238a6a 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 590 struct mlx5_ib_query_device_resp resp = {};
591 size_t resp_len;
592 u64 max_tso;
e126ba97 593
402ca536
BW		 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
595 if (uhw->outlen && uhw->outlen < resp_len)
596 return -EINVAL;
597 else
598 resp.response_length = resp_len;
599
600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 601 return -EINVAL;
602
1b5daf11
MD		 603 memset(props, 0, sizeof(*props));
604 err = mlx5_query_system_image_guid(ibdev,
605 &props->sys_image_guid);
606 if (err)
607 return err;
e126ba97 608
1b5daf11 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 610 if (err)
1b5daf11 611 return err;
e126ba97 612
1b5daf11
MD		 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
614 if (err)
615 return err;
e126ba97 616
9603b61d
JM		 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
618 (fw_rev_min(dev->mdev) << 16) |
619 fw_rev_sub(dev->mdev);
e126ba97
EC		 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
621 IB_DEVICE_PORT_ACTIVE_EVENT |
622 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 623 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 624
625 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 627 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 629 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 631 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 632 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 633 if (MLX5_CAP_GEN(mdev, imaicl)) {
634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
635 IB_DEVICE_MEM_WINDOW_TYPE_2B;
636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 637 /* We support 'Gappy' memory registration too */
638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 639 }
e126ba97 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 641 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
643 /* At this stage no support for signature handover */
644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
645 IB_PROT_T10DIF_TYPE_2 |
646 IB_PROT_T10DIF_TYPE_3;
647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
648 IB_GUARD_T10DIF_CSUM;
649 }
938fe83c 650 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 652
402ca536 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 654 if (MLX5_CAP_ETH(mdev, csum_cap)) {
655 /* Legacy bit to support old userspace libraries */
88115fe7 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
658 }
659
660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
661 props->raw_packet_caps |=
662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 663
402ca536
BW		 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
666 if (max_tso) {
667 resp.tso_caps.max_tso = 1 << max_tso;
668 resp.tso_caps.supported_qpts |=
669 1 << IB_QPT_RAW_PACKET;
670 resp.response_length += sizeof(resp.tso_caps);
671 }
672 }
31f69a82
YH		 673
674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
675 resp.rss_caps.rx_hash_function =
676 MLX5_RX_HASH_FUNC_TOEPLITZ;
677 resp.rss_caps.rx_hash_fields_mask =
678 MLX5_RX_HASH_SRC_IPV4 |
679 MLX5_RX_HASH_DST_IPV4 |
680 MLX5_RX_HASH_SRC_IPV6 |
681 MLX5_RX_HASH_DST_IPV6 |
682 MLX5_RX_HASH_SRC_PORT_TCP |
683 MLX5_RX_HASH_DST_PORT_TCP |
684 MLX5_RX_HASH_SRC_PORT_UDP |
685 MLX5_RX_HASH_DST_PORT_UDP;
686 resp.response_length += sizeof(resp.rss_caps);
687 }
688 } else {
689 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
690 resp.response_length += sizeof(resp.tso_caps);
691 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
692 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 693 }
694
f0313965
ES		 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
697 props->device_cap_flags |= IB_DEVICE_UD_TSO;
698 }
699
03404e8a
MG		 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
701 MLX5_CAP_GEN(dev->mdev, general_notification_event))
702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
703
1d54f890
YH		 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
707
cff5a0f3 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
710 /* Legacy bit to support old userspace libraries */
cff5a0f3 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
713 }
cff5a0f3 714
da6d6ba3
MG		 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
717
1b5daf11
MD		 718 props->vendor_part_id = mdev->pdev->device;
719 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 720
721 props->max_mr_size = ~0ull;
e0238a6a 722 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 723 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
724 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
725 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
726 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 727 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
728 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
729 sizeof(struct mlx5_wqe_raddr_seg)) /
730 sizeof(struct mlx5_wqe_data_seg);
e126ba97 731 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 732 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 733 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 734 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 735 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
736 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
737 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
738 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
739 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
740 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
741 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 742 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 743 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 744 props->max_fast_reg_page_list_len =
745 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 746 get_atomic_caps(dev, props);
81bea28f 747 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 748 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
749 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 750 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
751 props->max_mcast_grp;
752 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 753 props->max_ah = INT_MAX;
7c60bcbb
MB		 754 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
755 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 756
8cdd312c 757#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 758 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 759 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
760 props->odp_caps = dev->odp_caps;
761#endif
762
051f2630
LR		 763 if (MLX5_CAP_GEN(mdev, cd))
764 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
765
eff901d3
EC		 766 if (!mlx5_core_is_pf(mdev))
767 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
768
31f69a82
YH		 769 if (mlx5_ib_port_link_layer(ibdev, 1) ==
770 IB_LINK_LAYER_ETHERNET) {
771 props->rss_caps.max_rwq_indirection_tables =
772 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
773 props->rss_caps.max_rwq_indirection_table_size =
774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
775 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
776 props->max_wq_type_rq =
777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
778 }
779
7e43a2a5
BW		 780 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
781 resp.cqe_comp_caps.max_num =
782 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
783 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
784 resp.cqe_comp_caps.supported_format =
785 MLX5_IB_CQE_RES_FORMAT_HASH |
786 MLX5_IB_CQE_RES_FORMAT_CSUM;
787 resp.response_length += sizeof(resp.cqe_comp_caps);
788 }
789
d949167d
BW		 790 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
791 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
792 MLX5_CAP_GEN(mdev, qos)) {
793 resp.packet_pacing_caps.qp_rate_limit_max =
794 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
795 resp.packet_pacing_caps.qp_rate_limit_min =
796 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
797 resp.packet_pacing_caps.supported_qpts |=
798 1 << IB_QPT_RAW_PACKET;
799 }
800 resp.response_length += sizeof(resp.packet_pacing_caps);
801 }
802
9f885201
LR		 803 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
804 uhw->outlen)) {
805 resp.mlx5_ib_support_multi_pkt_send_wqes =
806 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
807 resp.response_length +=
808 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
809 }
810
811 if (field_avail(typeof(resp), reserved, uhw->outlen))
812 resp.response_length += sizeof(resp.reserved);
813
402ca536
BW		 814 if (uhw->outlen) {
815 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
816
817 if (err)
818 return err;
819 }
820
1b5daf11 821 return 0;
e126ba97
EC		 822}
823
1b5daf11
MD		 824enum mlx5_ib_width {
825 MLX5_IB_WIDTH_1X = 1 << 0,
826 MLX5_IB_WIDTH_2X = 1 << 1,
827 MLX5_IB_WIDTH_4X = 1 << 2,
828 MLX5_IB_WIDTH_8X = 1 << 3,
829 MLX5_IB_WIDTH_12X = 1 << 4
830};
831
832static int translate_active_width(struct ib_device *ibdev, u8 active_width,
833 u8 *ib_width)
e126ba97
EC		 834{
835 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 836 int err = 0;
837
838 if (active_width & MLX5_IB_WIDTH_1X) {
839 *ib_width = IB_WIDTH_1X;
840 } else if (active_width & MLX5_IB_WIDTH_2X) {
841 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
842 (int)active_width);
843 err = -EINVAL;
844 } else if (active_width & MLX5_IB_WIDTH_4X) {
845 *ib_width = IB_WIDTH_4X;
846 } else if (active_width & MLX5_IB_WIDTH_8X) {
847 *ib_width = IB_WIDTH_8X;
848 } else if (active_width & MLX5_IB_WIDTH_12X) {
849 *ib_width = IB_WIDTH_12X;
850 } else {
851 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
852 (int)active_width);
853 err = -EINVAL;
e126ba97
EC		 854 }
855
1b5daf11
MD		 856 return err;
857}
e126ba97 858
1b5daf11
MD		 859static int mlx5_mtu_to_ib_mtu(int mtu)
860{
861 switch (mtu) {
862 case 256: return 1;
863 case 512: return 2;
864 case 1024: return 3;
865 case 2048: return 4;
866 case 4096: return 5;
867 default:
868 pr_warn("invalid mtu\n");
869 return -1;
e126ba97 870 }
1b5daf11 871}
e126ba97 872
1b5daf11
MD		 873enum ib_max_vl_num {
874 __IB_MAX_VL_0 = 1,
875 __IB_MAX_VL_0_1 = 2,
876 __IB_MAX_VL_0_3 = 3,
877 __IB_MAX_VL_0_7 = 4,
878 __IB_MAX_VL_0_14 = 5,
879};
e126ba97 880
1b5daf11
MD		 881enum mlx5_vl_hw_cap {
882 MLX5_VL_HW_0 = 1,
883 MLX5_VL_HW_0_1 = 2,
884 MLX5_VL_HW_0_2 = 3,
885 MLX5_VL_HW_0_3 = 4,
886 MLX5_VL_HW_0_4 = 5,
887 MLX5_VL_HW_0_5 = 6,
888 MLX5_VL_HW_0_6 = 7,
889 MLX5_VL_HW_0_7 = 8,
890 MLX5_VL_HW_0_14 = 15
891};
e126ba97 892
1b5daf11
MD		 893static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
894 u8 *max_vl_num)
895{
896 switch (vl_hw_cap) {
897 case MLX5_VL_HW_0:
898 *max_vl_num = __IB_MAX_VL_0;
899 break;
900 case MLX5_VL_HW_0_1:
901 *max_vl_num = __IB_MAX_VL_0_1;
902 break;
903 case MLX5_VL_HW_0_3:
904 *max_vl_num = __IB_MAX_VL_0_3;
905 break;
906 case MLX5_VL_HW_0_7:
907 *max_vl_num = __IB_MAX_VL_0_7;
908 break;
909 case MLX5_VL_HW_0_14:
910 *max_vl_num = __IB_MAX_VL_0_14;
911 break;
e126ba97 912
1b5daf11
MD		 913 default:
914 return -EINVAL;
e126ba97 915 }
e126ba97 916
1b5daf11 917 return 0;
e126ba97
EC		 918}
919
1b5daf11
MD		 920static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
921 struct ib_port_attr *props)
e126ba97 922{
1b5daf11
MD		 923 struct mlx5_ib_dev *dev = to_mdev(ibdev);
924 struct mlx5_core_dev *mdev = dev->mdev;
925 struct mlx5_hca_vport_context *rep;
046339ea
SM		 926 u16 max_mtu;
927 u16 oper_mtu;
1b5daf11
MD		 928 int err;
929 u8 ib_link_width_oper;
930 u8 vl_hw_cap;
e126ba97 931
1b5daf11
MD		 932 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
933 if (!rep) {
934 err = -ENOMEM;
e126ba97 935 goto out;
e126ba97 936 }
e126ba97 937
c4550c63 938 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 939
1b5daf11 940 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 941 if (err)
942 goto out;
943
1b5daf11
MD		 944 props->lid = rep->lid;
945 props->lmc = rep->lmc;
946 props->sm_lid = rep->sm_lid;
947 props->sm_sl = rep->sm_sl;
948 props->state = rep->vport_state;
949 props->phys_state = rep->port_physical_state;
950 props->port_cap_flags = rep->cap_mask1;
951 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
952 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
953 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
954 props->bad_pkey_cntr = rep->pkey_violation_counter;
955 props->qkey_viol_cntr = rep->qkey_violation_counter;
956 props->subnet_timeout = rep->subnet_timeout;
957 props->init_type_reply = rep->init_type_reply;
eff901d3 958 props->grh_required = rep->grh_required;
e126ba97 959
1b5daf11
MD		 960 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
961 if (err)
e126ba97 962 goto out;
e126ba97 963
1b5daf11
MD		 964 err = translate_active_width(ibdev, ib_link_width_oper,
965 &props->active_width);
966 if (err)
967 goto out;
d5beb7f2 968 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 969 if (err)
970 goto out;
971
facc9699 972 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 973
1b5daf11 974 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 975
facc9699 976 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 977
1b5daf11 978 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 979
1b5daf11
MD		 980 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
981 if (err)
982 goto out;
e126ba97 983
1b5daf11
MD		 984 err = translate_max_vl_num(ibdev, vl_hw_cap,
985 &props->max_vl_num);
e126ba97 986out:
1b5daf11 987 kfree(rep);
e126ba97
EC		 988 return err;
989}
990
1b5daf11
MD		 991int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
992 struct ib_port_attr *props)
e126ba97 993{
095b0927
IT		 994 unsigned int count;
995 int ret;
996
1b5daf11
MD		 997 switch (mlx5_get_vport_access_method(ibdev)) {
998 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 999 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1000 break;
e126ba97 1001
1b5daf11 1002 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1003 ret = mlx5_query_hca_port(ibdev, port, props);
1004 break;
e126ba97 1005
3f89a643 1006 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1007 ret = mlx5_query_port_roce(ibdev, port, props);
1008 break;
3f89a643 1009
1b5daf11 1010 default:
095b0927
IT		 1011 ret = -EINVAL;
1012 }
1013
1014 if (!ret && props) {
1015 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1016 props->gid_tbl_len -= count;
1b5daf11 1017 }
095b0927 1018 return ret;
1b5daf11 1019}
e126ba97 1020
1b5daf11
MD		 1021static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1022 union ib_gid *gid)
1023{
1024 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1025 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1026
1b5daf11
MD		 1027 switch (mlx5_get_vport_access_method(ibdev)) {
1028 case MLX5_VPORT_ACCESS_METHOD_MAD:
1029 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1030
1b5daf11
MD		 1031 case MLX5_VPORT_ACCESS_METHOD_HCA:
1032 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1033
1034 default:
1035 return -EINVAL;
1036 }
e126ba97 1037
e126ba97
EC		 1038}
1039
1b5daf11
MD		 1040static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1041 u16 *pkey)
1042{
1043 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1044 struct mlx5_core_dev *mdev = dev->mdev;
1045
1046 switch (mlx5_get_vport_access_method(ibdev)) {
1047 case MLX5_VPORT_ACCESS_METHOD_MAD:
1048 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1049
1050 case MLX5_VPORT_ACCESS_METHOD_HCA:
1051 case MLX5_VPORT_ACCESS_METHOD_NIC:
1052 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1053 pkey);
1054 default:
1055 return -EINVAL;
1056 }
1057}
e126ba97
EC		 1058
1059static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1060 struct ib_device_modify *props)
1061{
1062 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1063 struct mlx5_reg_node_desc in;
1064 struct mlx5_reg_node_desc out;
1065 int err;
1066
1067 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1068 return -EOPNOTSUPP;
1069
1070 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1071 return 0;
1072
1073 /*
1074 * If possible, pass node desc to FW, so it can generate
1075 * a 144 trap. If cmd fails, just ignore.
1076 */
bd99fdea 1077 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1078 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1079 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1080 if (err)
1081 return err;
1082
bd99fdea 1083 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1084
1085 return err;
1086}
1087
cdbe33d0
EC		 1088static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1089 u32 value)
1090{
1091 struct mlx5_hca_vport_context ctx = {};
1092 int err;
1093
1094 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1095 port_num, 0, &ctx);
1096 if (err)
1097 return err;
1098
1099 if (~ctx.cap_mask1_perm & mask) {
1100 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1101 mask, ctx.cap_mask1_perm);
1102 return -EINVAL;
1103 }
1104
1105 ctx.cap_mask1 = value;
1106 ctx.cap_mask1_perm = mask;
1107 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1108 port_num, 0, &ctx);
1109
1110 return err;
1111}
1112
e126ba97
EC		 1113static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1114 struct ib_port_modify *props)
1115{
1116 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1117 struct ib_port_attr attr;
1118 u32 tmp;
1119 int err;
cdbe33d0
EC		 1120 u32 change_mask;
1121 u32 value;
1122 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1123 IB_LINK_LAYER_INFINIBAND);
1124
ec255879
MD		 1125 /* CM layer calls ib_modify_port() regardless of the link layer. For
1126 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1127 */
1128 if (!is_ib)
1129 return 0;
1130
cdbe33d0
EC		 1131 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1132 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1133 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1134 return set_port_caps_atomic(dev, port, change_mask, value);
1135 }
e126ba97
EC		 1136
1137 mutex_lock(&dev->cap_mask_mutex);
1138
c4550c63 1139 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1140 if (err)
1141 goto out;
1142
1143 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1144 ~props->clr_port_cap_mask;
1145
9603b61d 1146 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1147
1148out:
1149 mutex_unlock(&dev->cap_mask_mutex);
1150 return err;
1151}
1152
30aa60b3
EC		 1153static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1154{
1155 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1156 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1157}
1158
b037c29a
EC		 1159static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1160 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1161 u32 *num_sys_pages)
1162{
1163 int uars_per_sys_page;
1164 int bfregs_per_sys_page;
1165 int ref_bfregs = req->total_num_bfregs;
1166
1167 if (req->total_num_bfregs == 0)
1168 return -EINVAL;
1169
1170 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1171 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1172
1173 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1174 return -ENOMEM;
1175
1176 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1177 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1178 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1179 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1180
1181 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1182 return -EINVAL;
1183
9c2d33d4 1184 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n",
b037c29a
EC		 1185 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1186 lib_uar_4k ? "yes" : "no", ref_bfregs,
1187 req->total_num_bfregs, *num_sys_pages);
1188
1189 return 0;
1190}
1191
1192static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1193{
1194 struct mlx5_bfreg_info *bfregi;
1195 int err;
1196 int i;
1197
1198 bfregi = &context->bfregi;
1199 for (i = 0; i < bfregi->num_sys_pages; i++) {
1200 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1201 if (err)
1202 goto error;
1203
1204 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1205 }
1206 return 0;
1207
1208error:
1209 for (--i; i >= 0; i--)
1210 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1211 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1212
1213 return err;
1214}
1215
1216static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1217{
1218 struct mlx5_bfreg_info *bfregi;
1219 int err;
1220 int i;
1221
1222 bfregi = &context->bfregi;
1223 for (i = 0; i < bfregi->num_sys_pages; i++) {
1224 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1225 if (err) {
1226 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1227 return err;
1228 }
1229 }
1230 return 0;
1231}
1232
c85023e1
HN		 1233static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1234{
1235 int err;
1236
1237 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1238 if (err)
1239 return err;
1240
1241 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1242 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1243 return err;
1244
1245 mutex_lock(&dev->lb_mutex);
1246 dev->user_td++;
1247
1248 if (dev->user_td == 2)
1249 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1250
1251 mutex_unlock(&dev->lb_mutex);
1252 return err;
1253}
1254
1255static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1256{
1257 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1258
1259 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1260 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1261 return;
1262
1263 mutex_lock(&dev->lb_mutex);
1264 dev->user_td--;
1265
1266 if (dev->user_td < 2)
1267 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1268
1269 mutex_unlock(&dev->lb_mutex);
1270}
1271
e126ba97
EC		 1272static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1273 struct ib_udata *udata)
1274{
1275 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1276 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1277 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1278 struct mlx5_ib_ucontext *context;
2f5ff264 1279 struct mlx5_bfreg_info *bfregi;
78c0f98c 1280 int ver;
e126ba97 1281 int err;
a168a41c
MD		 1282 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1283 max_cqe_version);
b037c29a 1284 bool lib_uar_4k;
e126ba97
EC		 1285
1286 if (!dev->ib_active)
1287 return ERR_PTR(-EAGAIN);
1288
e093111d 1289 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1290 ver = 0;
e093111d 1291 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1292 ver = 2;
1293 else
1294 return ERR_PTR(-EINVAL);
1295
e093111d 1296 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1297 if (err)
1298 return ERR_PTR(err);
1299
b368d7cb 1300 if (req.flags)
78c0f98c
EC		 1301 return ERR_PTR(-EINVAL);
1302
f72300c5 1303 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1304 return ERR_PTR(-EOPNOTSUPP);
1305
2f5ff264
EC		 1306 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1307 MLX5_NON_FP_BFREGS_PER_UAR);
1308 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1309 return ERR_PTR(-EINVAL);
1310
938fe83c 1311 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1312 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1313 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1314 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1315 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1316 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1317 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1318 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1319 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1320 resp.cqe_version = min_t(__u8,
1321 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1322 req.max_cqe_version);
30aa60b3
EC		 1323 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1324 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1325 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1326 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1327 resp.response_length = min(offsetof(typeof(resp), response_length) +
1328 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1329
1330 context = kzalloc(sizeof(*context), GFP_KERNEL);
1331 if (!context)
1332 return ERR_PTR(-ENOMEM);
1333
30aa60b3 1334 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1335 bfregi = &context->bfregi;
b037c29a
EC		 1336
1337 /* updates req->total_num_bfregs */
1338 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1339 if (err)
e126ba97 1340 goto out_ctx;
e126ba97 1341
b037c29a
EC		 1342 mutex_init(&bfregi->lock);
1343 bfregi->lib_uar_4k = lib_uar_4k;
1344 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1345 GFP_KERNEL);
b037c29a 1346 if (!bfregi->count) {
e126ba97 1347 err = -ENOMEM;
b037c29a 1348 goto out_ctx;
e126ba97
EC		 1349 }
1350
b037c29a
EC		 1351 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1352 sizeof(*bfregi->sys_pages),
1353 GFP_KERNEL);
1354 if (!bfregi->sys_pages) {
e126ba97 1355 err = -ENOMEM;
b037c29a 1356 goto out_count;
e126ba97
EC		 1357 }
1358
b037c29a
EC		 1359 err = allocate_uars(dev, context);
1360 if (err)
1361 goto out_sys_pages;
e126ba97 1362
b4cfe447
HE		 1363#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1364 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1365#endif
1366
7d0cc6ed
AK		 1367 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1368 if (!context->upd_xlt_page) {
1369 err = -ENOMEM;
1370 goto out_uars;
1371 }
1372 mutex_init(&context->upd_xlt_page_mutex);
1373
146d2f1a 1374 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1375 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1376 if (err)
7d0cc6ed 1377 goto out_page;
146d2f1a 1378 }
1379
7c2344c3 1380 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1381 INIT_LIST_HEAD(&context->db_page_list);
1382 mutex_init(&context->db_page_mutex);
1383
2f5ff264 1384 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1385 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1386
f72300c5
HA		 1387 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1388 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1389
402ca536 1390 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1391 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1392 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1393 resp.response_length += sizeof(resp.cmds_supp_uhw);
1394 }
1395
78984898
OG		 1396 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1397 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1398 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1399 resp.eth_min_inline++;
1400 }
1401 resp.response_length += sizeof(resp.eth_min_inline);
1402 }
1403
bc5c6eed
NO		 1404 /*
1405 * We don't want to expose information from the PCI bar that is located
1406 * after 4096 bytes, so if the arch only supports larger pages, let's
1407 * pretend we don't support reading the HCA's core clock. This is also
1408 * forced by mmap function.
1409 */
de8d6e02
EC		 1410 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1411 if (PAGE_SIZE <= 4096) {
1412 resp.comp_mask |=
1413 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1414 resp.hca_core_clock_offset =
1415 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1416 }
f72300c5 1417 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1418 sizeof(resp.reserved2);
b368d7cb
MB		 1419 }
1420
30aa60b3
EC		 1421 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1422 resp.response_length += sizeof(resp.log_uar_size);
1423
1424 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1425 resp.response_length += sizeof(resp.num_uars_per_page);
1426
b368d7cb 1427 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1428 if (err)
146d2f1a 1429 goto out_td;
e126ba97 1430
2f5ff264
EC		 1431 bfregi->ver = ver;
1432 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1433 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1434 context->lib_caps = req.lib_caps;
1435 print_lib_caps(dev, context->lib_caps);
f72300c5 1436
e126ba97
EC		 1437 return &context->ibucontext;
1438
146d2f1a 1439out_td:
1440 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1441 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1442
7d0cc6ed
AK		 1443out_page:
1444 free_page(context->upd_xlt_page);
1445
e126ba97 1446out_uars:
b037c29a 1447 deallocate_uars(dev, context);
e126ba97 1448
b037c29a
EC		 1449out_sys_pages:
1450 kfree(bfregi->sys_pages);
e126ba97 1451
b037c29a
EC		 1452out_count:
1453 kfree(bfregi->count);
e126ba97
EC		 1454
1455out_ctx:
1456 kfree(context);
b037c29a 1457
e126ba97
EC		 1458 return ERR_PTR(err);
1459}
1460
1461static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1462{
1463 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1464 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1465 struct mlx5_bfreg_info *bfregi;
e126ba97 1466
b037c29a 1467 bfregi = &context->bfregi;
146d2f1a 1468 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1469 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1470
7d0cc6ed 1471 free_page(context->upd_xlt_page);
b037c29a
EC		 1472 deallocate_uars(dev, context);
1473 kfree(bfregi->sys_pages);
2f5ff264 1474 kfree(bfregi->count);
e126ba97
EC		 1475 kfree(context);
1476
1477 return 0;
1478}
1479
b037c29a
EC		 1480static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1481 struct mlx5_bfreg_info *bfregi,
1482 int idx)
e126ba97 1483{
b037c29a
EC		 1484 int fw_uars_per_page;
1485
1486 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1487
1488 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1489 bfregi->sys_pages[idx] / fw_uars_per_page;
e126ba97
EC		 1490}
1491
1492static int get_command(unsigned long offset)
1493{
1494 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1495}
1496
1497static int get_arg(unsigned long offset)
1498{
1499 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1500}
1501
1502static int get_index(unsigned long offset)
1503{
1504 return get_arg(offset);
1505}
1506
7c2344c3
MG		 1507static void mlx5_ib_vma_open(struct vm_area_struct *area)
1508{
1509 /* vma_open is called when a new VMA is created on top of our VMA. This
1510 * is done through either mremap flow or split_vma (usually due to
1511 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1512 * as this VMA is strongly hardware related. Therefore we set the
1513 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1514 * calling us again and trying to do incorrect actions. We assume that
1515 * the original VMA size is exactly a single page, and therefore all
1516 * "splitting" operation will not happen to it.
1517 */
1518 area->vm_ops = NULL;
1519}
1520
1521static void mlx5_ib_vma_close(struct vm_area_struct *area)
1522{
1523 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1524
1525 /* It's guaranteed that all VMAs opened on a FD are closed before the
1526 * file itself is closed, therefore no sync is needed with the regular
1527 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1528 * However need a sync with accessing the vma as part of
1529 * mlx5_ib_disassociate_ucontext.
1530 * The close operation is usually called under mm->mmap_sem except when
1531 * process is exiting.
1532 * The exiting case is handled explicitly as part of
1533 * mlx5_ib_disassociate_ucontext.
1534 */
1535 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1536
1537 /* setting the vma context pointer to null in the mlx5_ib driver's
1538 * private data, to protect a race condition in
1539 * mlx5_ib_disassociate_ucontext().
1540 */
1541 mlx5_ib_vma_priv_data->vma = NULL;
1542 list_del(&mlx5_ib_vma_priv_data->list);
1543 kfree(mlx5_ib_vma_priv_data);
1544}
1545
1546static const struct vm_operations_struct mlx5_ib_vm_ops = {
1547 .open = mlx5_ib_vma_open,
1548 .close = mlx5_ib_vma_close
1549};
1550
1551static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1552 struct mlx5_ib_ucontext *ctx)
1553{
1554 struct mlx5_ib_vma_private_data *vma_prv;
1555 struct list_head *vma_head = &ctx->vma_private_list;
1556
1557 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1558 if (!vma_prv)
1559 return -ENOMEM;
1560
1561 vma_prv->vma = vma;
1562 vma->vm_private_data = vma_prv;
1563 vma->vm_ops = &mlx5_ib_vm_ops;
1564
1565 list_add(&vma_prv->list, vma_head);
1566
1567 return 0;
1568}
1569
1570static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1571{
1572 int ret;
1573 struct vm_area_struct *vma;
1574 struct mlx5_ib_vma_private_data *vma_private, *n;
1575 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1576 struct task_struct *owning_process = NULL;
1577 struct mm_struct *owning_mm = NULL;
1578
1579 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1580 if (!owning_process)
1581 return;
1582
1583 owning_mm = get_task_mm(owning_process);
1584 if (!owning_mm) {
1585 pr_info("no mm, disassociate ucontext is pending task termination\n");
1586 while (1) {
1587 put_task_struct(owning_process);
1588 usleep_range(1000, 2000);
1589 owning_process = get_pid_task(ibcontext->tgid,
1590 PIDTYPE_PID);
1591 if (!owning_process ||
1592 owning_process->state == TASK_DEAD) {
1593 pr_info("disassociate ucontext done, task was terminated\n");
1594 /* in case task was dead need to release the
1595 * task struct.
1596 */
1597 if (owning_process)
1598 put_task_struct(owning_process);
1599 return;
1600 }
1601 }
1602 }
1603
1604 /* need to protect from a race on closing the vma as part of
1605 * mlx5_ib_vma_close.
1606 */
ecc7d83b 1607 down_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1608 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1609 list) {
1610 vma = vma_private->vma;
1611 ret = zap_vma_ptes(vma, vma->vm_start,
1612 PAGE_SIZE);
1613 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1614 /* context going to be destroyed, should
1615 * not access ops any more.
1616 */
13776612 1617 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1618 vma->vm_ops = NULL;
1619 list_del(&vma_private->list);
1620 kfree(vma_private);
1621 }
ecc7d83b 1622 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1623 mmput(owning_mm);
1624 put_task_struct(owning_process);
1625}
1626
37aa5c36
GL		 1627static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1628{
1629 switch (cmd) {
1630 case MLX5_IB_MMAP_WC_PAGE:
1631 return "WC";
1632 case MLX5_IB_MMAP_REGULAR_PAGE:
1633 return "best effort WC";
1634 case MLX5_IB_MMAP_NC_PAGE:
1635 return "NC";
1636 default:
1637 return NULL;
1638 }
1639}
1640
1641static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1642 struct vm_area_struct *vma,
1643 struct mlx5_ib_ucontext *context)
37aa5c36 1644{
2f5ff264 1645 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1646 int err;
1647 unsigned long idx;
1648 phys_addr_t pfn, pa;
1649 pgprot_t prot;
b037c29a
EC		 1650 int uars_per_page;
1651
1652 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1653 return -EINVAL;
1654
1655 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1656 idx = get_index(vma->vm_pgoff);
1657 if (idx % uars_per_page ||
1658 idx * uars_per_page >= bfregi->num_sys_pages) {
1659 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1660 return -EINVAL;
1661 }
37aa5c36
GL		 1662
1663 switch (cmd) {
1664 case MLX5_IB_MMAP_WC_PAGE:
1665/* Some architectures don't support WC memory */
1666#if defined(CONFIG_X86)
1667 if (!pat_enabled())
1668 return -EPERM;
1669#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1670 return -EPERM;
1671#endif
1672 /* fall through */
1673 case MLX5_IB_MMAP_REGULAR_PAGE:
1674 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1675 prot = pgprot_writecombine(vma->vm_page_prot);
1676 break;
1677 case MLX5_IB_MMAP_NC_PAGE:
1678 prot = pgprot_noncached(vma->vm_page_prot);
1679 break;
1680 default:
1681 return -EINVAL;
1682 }
1683
b037c29a 1684 pfn = uar_index2pfn(dev, bfregi, idx);
37aa5c36
GL		 1685 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1686
1687 vma->vm_page_prot = prot;
1688 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1689 PAGE_SIZE, vma->vm_page_prot);
1690 if (err) {
1691 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1692 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1693 return -EAGAIN;
1694 }
1695
1696 pa = pfn << PAGE_SHIFT;
1697 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1698 vma->vm_start, &pa);
1699
7c2344c3 1700 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1701}
1702
e126ba97
EC		 1703static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1704{
1705 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1706 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1707 unsigned long command;
e126ba97
EC		 1708 phys_addr_t pfn;
1709
1710 command = get_command(vma->vm_pgoff);
1711 switch (command) {
37aa5c36
GL		 1712 case MLX5_IB_MMAP_WC_PAGE:
1713 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1714 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1715 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1716
1717 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1718 return -ENOSYS;
1719
d69e3bcf 1720 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1721 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1722 return -EINVAL;
1723
6cbac1e4 1724 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1725 return -EPERM;
1726
1727 /* Don't expose to user-space information it shouldn't have */
1728 if (PAGE_SIZE > 4096)
1729 return -EOPNOTSUPP;
1730
1731 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1732 pfn = (dev->mdev->iseg_base +
1733 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1734 PAGE_SHIFT;
1735 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1736 PAGE_SIZE, vma->vm_page_prot))
1737 return -EAGAIN;
1738
1739 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1740 vma->vm_start,
1741 (unsigned long long)pfn << PAGE_SHIFT);
1742 break;
d69e3bcf 1743
e126ba97
EC		 1744 default:
1745 return -EINVAL;
1746 }
1747
1748 return 0;
1749}
1750
e126ba97
EC		 1751static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1752 struct ib_ucontext *context,
1753 struct ib_udata *udata)
1754{
1755 struct mlx5_ib_alloc_pd_resp resp;
1756 struct mlx5_ib_pd *pd;
1757 int err;
1758
1759 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1760 if (!pd)
1761 return ERR_PTR(-ENOMEM);
1762
9603b61d 1763 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1764 if (err) {
1765 kfree(pd);
1766 return ERR_PTR(err);
1767 }
1768
1769 if (context) {
1770 resp.pdn = pd->pdn;
1771 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1772 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1773 kfree(pd);
1774 return ERR_PTR(-EFAULT);
1775 }
e126ba97
EC		 1776 }
1777
1778 return &pd->ibpd;
1779}
1780
1781static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1782{
1783 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1784 struct mlx5_ib_pd *mpd = to_mpd(pd);
1785
9603b61d 1786 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1787 kfree(mpd);
1788
1789 return 0;
1790}
1791
466fa6d2
MG		 1792enum {
1793 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1794 MATCH_CRITERIA_ENABLE_MISC_BIT,
1795 MATCH_CRITERIA_ENABLE_INNER_BIT
1796};
1797
1798#define HEADER_IS_ZERO(match_criteria, headers) \
1799 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1800 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1801
466fa6d2 1802static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1803{
466fa6d2 1804 u8 match_criteria_enable;
038d2ef8 1805
466fa6d2
MG		 1806 match_criteria_enable =
1807 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1808 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1809 match_criteria_enable |=
1810 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1811 MATCH_CRITERIA_ENABLE_MISC_BIT;
1812 match_criteria_enable |=
1813 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1814 MATCH_CRITERIA_ENABLE_INNER_BIT;
1815
1816 return match_criteria_enable;
038d2ef8
MG		 1817}
1818
ca0d4753
MG		 1819static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1820{
1821 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1822 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1823}
1824
2d1e697e
MR		 1825static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1826 bool inner)
1827{
1828 if (inner) {
1829 MLX5_SET(fte_match_set_misc,
1830 misc_c, inner_ipv6_flow_label, mask);
1831 MLX5_SET(fte_match_set_misc,
1832 misc_v, inner_ipv6_flow_label, val);
1833 } else {
1834 MLX5_SET(fte_match_set_misc,
1835 misc_c, outer_ipv6_flow_label, mask);
1836 MLX5_SET(fte_match_set_misc,
1837 misc_v, outer_ipv6_flow_label, val);
1838 }
1839}
1840
ca0d4753
MG		 1841static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1842{
1843 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1844 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1845 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1846 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1847}
1848
c47ac6ae
MG		 1849#define LAST_ETH_FIELD vlan_tag
1850#define LAST_IB_FIELD sl
ca0d4753 1851#define LAST_IPV4_FIELD tos
466fa6d2 1852#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1853#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1854#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 1855#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 1856#define LAST_DROP_FIELD size
c47ac6ae
MG		 1857
1858/* Field is the last supported field */
1859#define FIELDS_NOT_SUPPORTED(filter, field)\
1860 memchr_inv((void *)&filter.field +\
1861 sizeof(filter.field), 0,\
1862 sizeof(filter) -\
1863 offsetof(typeof(filter), field) -\
1864 sizeof(filter.field))
1865
19cc7524
AL		 1866#define IPV4_VERSION 4
1867#define IPV6_VERSION 6
1868static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1869 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 1870 u32 *tag_id, bool *is_drop)
038d2ef8 1871{
466fa6d2
MG		 1872 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1873 misc_parameters);
1874 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1875 misc_parameters);
2d1e697e
MR		 1876 void *headers_c;
1877 void *headers_v;
19cc7524 1878 int match_ipv;
2d1e697e
MR		 1879
1880 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1881 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1882 inner_headers);
1883 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1884 inner_headers);
19cc7524
AL		 1885 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1886 ft_field_support.inner_ip_version);
2d1e697e
MR		 1887 } else {
1888 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1889 outer_headers);
1890 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1891 outer_headers);
19cc7524
AL		 1892 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1893 ft_field_support.outer_ip_version);
2d1e697e 1894 }
466fa6d2 1895
2d1e697e 1896 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1897 case IB_FLOW_SPEC_ETH:
c47ac6ae 1898 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 1899 return -EOPNOTSUPP;
038d2ef8 1900
2d1e697e 1901 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1902 dmac_47_16),
1903 ib_spec->eth.mask.dst_mac);
2d1e697e 1904 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1905 dmac_47_16),
1906 ib_spec->eth.val.dst_mac);
1907
2d1e697e 1908 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 1909 smac_47_16),
1910 ib_spec->eth.mask.src_mac);
2d1e697e 1911 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 1912 smac_47_16),
1913 ib_spec->eth.val.src_mac);
1914
038d2ef8 1915 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 1916 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 1917 cvlan_tag, 1);
2d1e697e 1918 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 1919 cvlan_tag, 1);
038d2ef8 1920
2d1e697e 1921 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1922 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 1923 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1924 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1925
2d1e697e 1926 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1927 first_cfi,
1928 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 1929 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1930 first_cfi,
1931 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1932
2d1e697e 1933 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1934 first_prio,
1935 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 1936 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1937 first_prio,
1938 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1939 }
2d1e697e 1940 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1941 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 1942 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1943 ethertype, ntohs(ib_spec->eth.val.ether_type));
1944 break;
1945 case IB_FLOW_SPEC_IPV4:
c47ac6ae 1946 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 1947 return -EOPNOTSUPP;
038d2ef8 1948
19cc7524
AL		 1949 if (match_ipv) {
1950 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1951 ip_version, 0xf);
1952 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1953 ip_version, IPV4_VERSION);
1954 } else {
1955 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1956 ethertype, 0xffff);
1957 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1958 ethertype, ETH_P_IP);
1959 }
038d2ef8 1960
2d1e697e 1961 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1962 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1963 &ib_spec->ipv4.mask.src_ip,
1964 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 1965 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1966 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1967 &ib_spec->ipv4.val.src_ip,
1968 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 1969 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1970 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1971 &ib_spec->ipv4.mask.dst_ip,
1972 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 1973 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1974 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1975 &ib_spec->ipv4.val.dst_ip,
1976 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 1977
2d1e697e 1978 set_tos(headers_c, headers_v,
ca0d4753
MG		 1979 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1980
2d1e697e 1981 set_proto(headers_c, headers_v,
ca0d4753 1982 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 1983 break;
026bae0c 1984 case IB_FLOW_SPEC_IPV6:
c47ac6ae 1985 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 1986 return -EOPNOTSUPP;
026bae0c 1987
19cc7524
AL		 1988 if (match_ipv) {
1989 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1990 ip_version, 0xf);
1991 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1992 ip_version, IPV6_VERSION);
1993 } else {
1994 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1995 ethertype, 0xffff);
1996 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1997 ethertype, ETH_P_IPV6);
1998 }
026bae0c 1999
2d1e697e 2000 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2001 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2002 &ib_spec->ipv6.mask.src_ip,
2003 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2004 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2005 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2006 &ib_spec->ipv6.val.src_ip,
2007 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2008 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2009 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2010 &ib_spec->ipv6.mask.dst_ip,
2011 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2012 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2013 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2014 &ib_spec->ipv6.val.dst_ip,
2015 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2016
2d1e697e 2017 set_tos(headers_c, headers_v,
466fa6d2
MG		 2018 ib_spec->ipv6.mask.traffic_class,
2019 ib_spec->ipv6.val.traffic_class);
2020
2d1e697e 2021 set_proto(headers_c, headers_v,
466fa6d2
MG		 2022 ib_spec->ipv6.mask.next_hdr,
2023 ib_spec->ipv6.val.next_hdr);
2024
2d1e697e
MR		 2025 set_flow_label(misc_params_c, misc_params_v,
2026 ntohl(ib_spec->ipv6.mask.flow_label),
2027 ntohl(ib_spec->ipv6.val.flow_label),
2028 ib_spec->type & IB_FLOW_SPEC_INNER);
2029
026bae0c 2030 break;
038d2ef8 2031 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2032 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2033 LAST_TCP_UDP_FIELD))
1ffd3a26 2034 return -EOPNOTSUPP;
038d2ef8 2035
2d1e697e 2036 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2037 0xff);
2d1e697e 2038 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2039 IPPROTO_TCP);
2040
2d1e697e 2041 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2042 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2043 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2044 ntohs(ib_spec->tcp_udp.val.src_port));
2045
2d1e697e 2046 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2047 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2048 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2049 ntohs(ib_spec->tcp_udp.val.dst_port));
2050 break;
2051 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2052 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2053 LAST_TCP_UDP_FIELD))
1ffd3a26 2054 return -EOPNOTSUPP;
038d2ef8 2055
2d1e697e 2056 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2057 0xff);
2d1e697e 2058 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2059 IPPROTO_UDP);
2060
2d1e697e 2061 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2062 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2063 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2064 ntohs(ib_spec->tcp_udp.val.src_port));
2065
2d1e697e 2066 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2067 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2068 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2069 ntohs(ib_spec->tcp_udp.val.dst_port));
2070 break;
ffb30d8f
MR		 2071 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2072 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2073 LAST_TUNNEL_FIELD))
1ffd3a26 2074 return -EOPNOTSUPP;
ffb30d8f
MR		 2075
2076 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2077 ntohl(ib_spec->tunnel.mask.tunnel_id));
2078 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2079 ntohl(ib_spec->tunnel.val.tunnel_id));
2080 break;
2ac693f9
MR		 2081 case IB_FLOW_SPEC_ACTION_TAG:
2082 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2083 LAST_FLOW_TAG_FIELD))
2084 return -EOPNOTSUPP;
2085 if (ib_spec->flow_tag.tag_id >= BIT(24))
2086 return -EINVAL;
2087
2088 *tag_id = ib_spec->flow_tag.tag_id;
2089 break;
a22ed86c
SS		 2090 case IB_FLOW_SPEC_ACTION_DROP:
2091 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2092 LAST_DROP_FIELD))
2093 return -EOPNOTSUPP;
2094 *is_drop = true;
2095 break;
038d2ef8
MG		 2096 default:
2097 return -EINVAL;
2098 }
2099
2100 return 0;
2101}
2102
2103/* If a flow could catch both multicast and unicast packets,
2104 * it won't fall into the multicast flow steering table and this rule
2105 * could steal other multicast packets.
2106 */
2107static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2108{
81e30880 2109 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2110
2111 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2112 ib_attr->num_of_specs < 1)
2113 return false;
2114
81e30880
YH		 2115 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2116 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2117 struct ib_flow_spec_ipv4 *ipv4_spec;
2118
2119 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2120 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2121 return true;
2122
038d2ef8 2123 return false;
81e30880
YH		 2124 }
2125
2126 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2127 struct ib_flow_spec_eth *eth_spec;
2128
2129 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2130 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2131 is_multicast_ether_addr(eth_spec->val.dst_mac);
2132 }
038d2ef8 2133
81e30880 2134 return false;
038d2ef8
MG		 2135}
2136
19cc7524
AL		 2137static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2138 const struct ib_flow_attr *flow_attr,
0f750966 2139 bool check_inner)
038d2ef8
MG		 2140{
2141 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2142 int match_ipv = check_inner ?
2143 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2144 ft_field_support.inner_ip_version) :
2145 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2146 ft_field_support.outer_ip_version);
0f750966
AL		 2147 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2148 bool ipv4_spec_valid, ipv6_spec_valid;
2149 unsigned int ip_spec_type = 0;
2150 bool has_ethertype = false;
038d2ef8 2151 unsigned int spec_index;
0f750966
AL		 2152 bool mask_valid = true;
2153 u16 eth_type = 0;
2154 bool type_valid;
038d2ef8
MG		 2155
2156 /* Validate that ethertype is correct */
2157 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2158 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2159 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2160 mask_valid = (ib_spec->eth.mask.ether_type ==
2161 htons(0xffff));
2162 has_ethertype = true;
2163 eth_type = ntohs(ib_spec->eth.val.ether_type);
2164 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2165 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2166 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2167 }
2168 ib_spec = (void *)ib_spec + ib_spec->size;
2169 }
0f750966
AL		 2170
2171 type_valid = (!has_ethertype) || (!ip_spec_type);
2172 if (!type_valid && mask_valid) {
2173 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2174 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2175 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2176 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2177
2178 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2179 (((eth_type == ETH_P_MPLS_UC) ||
2180 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2181 }
2182
2183 return type_valid;
2184}
2185
19cc7524
AL		 2186static bool is_valid_attr(struct mlx5_core_dev *mdev,
2187 const struct ib_flow_attr *flow_attr)
0f750966 2188{
19cc7524
AL		 2189 return is_valid_ethertype(mdev, flow_attr, false) &&
2190 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2191}
2192
2193static void put_flow_table(struct mlx5_ib_dev *dev,
2194 struct mlx5_ib_flow_prio *prio, bool ft_added)
2195{
2196 prio->refcount -= !!ft_added;
2197 if (!prio->refcount) {
2198 mlx5_destroy_flow_table(prio->flow_table);
2199 prio->flow_table = NULL;
2200 }
2201}
2202
2203static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2204{
2205 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2206 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2207 struct mlx5_ib_flow_handler,
2208 ibflow);
2209 struct mlx5_ib_flow_handler *iter, *tmp;
2210
2211 mutex_lock(&dev->flow_db.lock);
2212
2213 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2214 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2215 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2216 list_del(&iter->list);
2217 kfree(iter);
2218 }
2219
74491de9 2220 mlx5_del_flow_rules(handler->rule);
5497adc6 2221 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2222 mutex_unlock(&dev->flow_db.lock);
2223
2224 kfree(handler);
2225
2226 return 0;
2227}
2228
35d19011
MG		 2229static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2230{
2231 priority *= 2;
2232 if (!dont_trap)
2233 priority++;
2234 return priority;
2235}
2236
cc0e5d42
MG		 2237enum flow_table_type {
2238 MLX5_IB_FT_RX,
2239 MLX5_IB_FT_TX
2240};
2241
00b7c2ab
MG		 2242#define MLX5_FS_MAX_TYPES 6
2243#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2244static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2245 struct ib_flow_attr *flow_attr,
2246 enum flow_table_type ft_type)
038d2ef8 2247{
35d19011 2248 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2249 struct mlx5_flow_namespace *ns = NULL;
2250 struct mlx5_ib_flow_prio *prio;
2251 struct mlx5_flow_table *ft;
dac388ef 2252 int max_table_size;
038d2ef8
MG		 2253 int num_entries;
2254 int num_groups;
2255 int priority;
2256 int err = 0;
2257
dac388ef
MG		 2258 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2259 log_max_ft_size));
038d2ef8 2260 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2261 if (flow_is_multicast_only(flow_attr) &&
2262 !dont_trap)
038d2ef8
MG		 2263 priority = MLX5_IB_FLOW_MCAST_PRIO;
2264 else
35d19011
MG		 2265 priority = ib_prio_to_core_prio(flow_attr->priority,
2266 dont_trap);
038d2ef8
MG		 2267 ns = mlx5_get_flow_namespace(dev->mdev,
2268 MLX5_FLOW_NAMESPACE_BYPASS);
2269 num_entries = MLX5_FS_MAX_ENTRIES;
2270 num_groups = MLX5_FS_MAX_TYPES;
2271 prio = &dev->flow_db.prios[priority];
2272 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2273 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2274 ns = mlx5_get_flow_namespace(dev->mdev,
2275 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2276 build_leftovers_ft_param(&priority,
2277 &num_entries,
2278 &num_groups);
2279 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2280 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2281 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2282 allow_sniffer_and_nic_rx_shared_tir))
2283 return ERR_PTR(-ENOTSUPP);
2284
2285 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2286 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2287 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2288
2289 prio = &dev->flow_db.sniffer[ft_type];
2290 priority = 0;
2291 num_entries = 1;
2292 num_groups = 1;
038d2ef8
MG		 2293 }
2294
2295 if (!ns)
2296 return ERR_PTR(-ENOTSUPP);
2297
dac388ef
MG		 2298 if (num_entries > max_table_size)
2299 return ERR_PTR(-ENOMEM);
2300
038d2ef8
MG		 2301 ft = prio->flow_table;
2302 if (!ft) {
2303 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2304 num_entries,
d63cd286 2305 num_groups,
c9f1b073 2306 0, 0);
038d2ef8
MG		 2307
2308 if (!IS_ERR(ft)) {
2309 prio->refcount = 0;
2310 prio->flow_table = ft;
2311 } else {
2312 err = PTR_ERR(ft);
2313 }
2314 }
2315
2316 return err ? ERR_PTR(err) : prio;
2317}
2318
2319static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2320 struct mlx5_ib_flow_prio *ft_prio,
dd063d0e 2321 const struct ib_flow_attr *flow_attr,
038d2ef8
MG		 2322 struct mlx5_flow_destination *dst)
2323{
2324 struct mlx5_flow_table *ft = ft_prio->flow_table;
2325 struct mlx5_ib_flow_handler *handler;
66958ed9 2326 struct mlx5_flow_act flow_act = {0};
c5bb1730 2327 struct mlx5_flow_spec *spec;
a22ed86c 2328 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2329 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2330 unsigned int spec_index;
2ac693f9 2331 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2332 bool is_drop = false;
038d2ef8 2333 int err = 0;
a22ed86c 2334 int dest_num = 1;
038d2ef8 2335
19cc7524 2336 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2337 return ERR_PTR(-EINVAL);
2338
1b9a07ee 2339 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2340 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2341 if (!handler || !spec) {
038d2ef8
MG		 2342 err = -ENOMEM;
2343 goto free;
2344 }
2345
2346 INIT_LIST_HEAD(&handler->list);
2347
2348 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2349 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2350 spec->match_value,
2351 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2352 if (err < 0)
2353 goto free;
2354
2355 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2356 }
2357
466fa6d2 2358 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2359 if (is_drop) {
2360 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2361 rule_dst = NULL;
2362 dest_num = 0;
2363 } else {
2364 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2365 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2366 }
2ac693f9
MR		 2367
2368 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2369 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2370 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2371 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2372 flow_tag, flow_attr->type);
2373 err = -EINVAL;
2374 goto free;
2375 }
2376 flow_act.flow_tag = flow_tag;
74491de9 2377 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2378 &flow_act,
a22ed86c 2379 rule_dst, dest_num);
038d2ef8
MG		 2380
2381 if (IS_ERR(handler->rule)) {
2382 err = PTR_ERR(handler->rule);
2383 goto free;
2384 }
2385
d9d4980a 2386 ft_prio->refcount++;
5497adc6 2387 handler->prio = ft_prio;
038d2ef8
MG		 2388
2389 ft_prio->flow_table = ft;
2390free:
2391 if (err)
2392 kfree(handler);
c5bb1730 2393 kvfree(spec);
038d2ef8
MG		 2394 return err ? ERR_PTR(err) : handler;
2395}
2396
35d19011
MG		 2397static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2398 struct mlx5_ib_flow_prio *ft_prio,
2399 struct ib_flow_attr *flow_attr,
2400 struct mlx5_flow_destination *dst)
2401{
2402 struct mlx5_ib_flow_handler *handler_dst = NULL;
2403 struct mlx5_ib_flow_handler *handler = NULL;
2404
2405 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2406 if (!IS_ERR(handler)) {
2407 handler_dst = create_flow_rule(dev, ft_prio,
2408 flow_attr, dst);
2409 if (IS_ERR(handler_dst)) {
74491de9 2410 mlx5_del_flow_rules(handler->rule);
d9d4980a 2411 ft_prio->refcount--;
35d19011
MG		 2412 kfree(handler);
2413 handler = handler_dst;
2414 } else {
2415 list_add(&handler_dst->list, &handler->list);
2416 }
2417 }
2418
2419 return handler;
2420}
038d2ef8
MG		 2421enum {
2422 LEFTOVERS_MC,
2423 LEFTOVERS_UC,
2424};
2425
2426static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2427 struct mlx5_ib_flow_prio *ft_prio,
2428 struct ib_flow_attr *flow_attr,
2429 struct mlx5_flow_destination *dst)
2430{
2431 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2432 struct mlx5_ib_flow_handler *handler = NULL;
2433
2434 static struct {
2435 struct ib_flow_attr flow_attr;
2436 struct ib_flow_spec_eth eth_flow;
2437 } leftovers_specs[] = {
2438 [LEFTOVERS_MC] = {
2439 .flow_attr = {
2440 .num_of_specs = 1,
2441 .size = sizeof(leftovers_specs[0])
2442 },
2443 .eth_flow = {
2444 .type = IB_FLOW_SPEC_ETH,
2445 .size = sizeof(struct ib_flow_spec_eth),
2446 .mask = {.dst_mac = {0x1} },
2447 .val = {.dst_mac = {0x1} }
2448 }
2449 },
2450 [LEFTOVERS_UC] = {
2451 .flow_attr = {
2452 .num_of_specs = 1,
2453 .size = sizeof(leftovers_specs[0])
2454 },
2455 .eth_flow = {
2456 .type = IB_FLOW_SPEC_ETH,
2457 .size = sizeof(struct ib_flow_spec_eth),
2458 .mask = {.dst_mac = {0x1} },
2459 .val = {.dst_mac = {} }
2460 }
2461 }
2462 };
2463
2464 handler = create_flow_rule(dev, ft_prio,
2465 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2466 dst);
2467 if (!IS_ERR(handler) &&
2468 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2469 handler_ucast = create_flow_rule(dev, ft_prio,
2470 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2471 dst);
2472 if (IS_ERR(handler_ucast)) {
74491de9 2473 mlx5_del_flow_rules(handler->rule);
d9d4980a 2474 ft_prio->refcount--;
038d2ef8
MG		 2475 kfree(handler);
2476 handler = handler_ucast;
2477 } else {
2478 list_add(&handler_ucast->list, &handler->list);
2479 }
2480 }
2481
2482 return handler;
2483}
2484
cc0e5d42
MG		 2485static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2486 struct mlx5_ib_flow_prio *ft_rx,
2487 struct mlx5_ib_flow_prio *ft_tx,
2488 struct mlx5_flow_destination *dst)
2489{
2490 struct mlx5_ib_flow_handler *handler_rx;
2491 struct mlx5_ib_flow_handler *handler_tx;
2492 int err;
2493 static const struct ib_flow_attr flow_attr = {
2494 .num_of_specs = 0,
2495 .size = sizeof(flow_attr)
2496 };
2497
2498 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2499 if (IS_ERR(handler_rx)) {
2500 err = PTR_ERR(handler_rx);
2501 goto err;
2502 }
2503
2504 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2505 if (IS_ERR(handler_tx)) {
2506 err = PTR_ERR(handler_tx);
2507 goto err_tx;
2508 }
2509
2510 list_add(&handler_tx->list, &handler_rx->list);
2511
2512 return handler_rx;
2513
2514err_tx:
74491de9 2515 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2516 ft_rx->refcount--;
2517 kfree(handler_rx);
2518err:
2519 return ERR_PTR(err);
2520}
2521
038d2ef8
MG		 2522static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2523 struct ib_flow_attr *flow_attr,
2524 int domain)
2525{
2526 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2527 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2528 struct mlx5_ib_flow_handler *handler = NULL;
2529 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2530 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2531 struct mlx5_ib_flow_prio *ft_prio;
2532 int err;
2533
2534 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2535 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2536
2537 if (domain != IB_FLOW_DOMAIN_USER ||
2538 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2539 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2540 return ERR_PTR(-EINVAL);
2541
2542 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2543 if (!dst)
2544 return ERR_PTR(-ENOMEM);
2545
2546 mutex_lock(&dev->flow_db.lock);
2547
cc0e5d42 2548 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2549 if (IS_ERR(ft_prio)) {
2550 err = PTR_ERR(ft_prio);
2551 goto unlock;
2552 }
cc0e5d42
MG		 2553 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2554 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2555 if (IS_ERR(ft_prio_tx)) {
2556 err = PTR_ERR(ft_prio_tx);
2557 ft_prio_tx = NULL;
2558 goto destroy_ft;
2559 }
2560 }
038d2ef8
MG		 2561
2562 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2563 if (mqp->flags & MLX5_IB_QP_RSS)
2564 dst->tir_num = mqp->rss_qp.tirn;
2565 else
2566 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2567
2568 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2569 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2570 handler = create_dont_trap_rule(dev, ft_prio,
2571 flow_attr, dst);
2572 } else {
2573 handler = create_flow_rule(dev, ft_prio, flow_attr,
2574 dst);
2575 }
038d2ef8
MG		 2576 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2577 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2578 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2579 dst);
cc0e5d42
MG		 2580 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2581 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2582 } else {
2583 err = -EINVAL;
2584 goto destroy_ft;
2585 }
2586
2587 if (IS_ERR(handler)) {
2588 err = PTR_ERR(handler);
2589 handler = NULL;
2590 goto destroy_ft;
2591 }
2592
038d2ef8
MG		 2593 mutex_unlock(&dev->flow_db.lock);
2594 kfree(dst);
2595
2596 return &handler->ibflow;
2597
2598destroy_ft:
2599 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2600 if (ft_prio_tx)
2601 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2602unlock:
2603 mutex_unlock(&dev->flow_db.lock);
2604 kfree(dst);
2605 kfree(handler);
2606 return ERR_PTR(err);
2607}
2608
e126ba97
EC		 2609static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2610{
2611 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 2612 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 2613 int err;
2614
81e30880
YH		 2615 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2616 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2617 return -EOPNOTSUPP;
2618 }
2619
9603b61d 2620 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2621 if (err)
2622 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2623 ibqp->qp_num, gid->raw);
2624
2625 return err;
2626}
2627
2628static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2629{
2630 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2631 int err;
2632
9603b61d 2633 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2634 if (err)
2635 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2636 ibqp->qp_num, gid->raw);
2637
2638 return err;
2639}
2640
2641static int init_node_data(struct mlx5_ib_dev *dev)
2642{
1b5daf11 2643 int err;
e126ba97 2644
1b5daf11 2645 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2646 if (err)
1b5daf11 2647 return err;
e126ba97 2648
1b5daf11 2649 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2650
1b5daf11 2651 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2652}
2653
2654static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2655 char *buf)
2656{
2657 struct mlx5_ib_dev *dev =
2658 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2659
9603b61d 2660 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2661}
2662
2663static ssize_t show_reg_pages(struct device *device,
2664 struct device_attribute *attr, char *buf)
2665{
2666 struct mlx5_ib_dev *dev =
2667 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2668
6aec21f6 2669 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2670}
2671
2672static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2673 char *buf)
2674{
2675 struct mlx5_ib_dev *dev =
2676 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2677 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2678}
2679
e126ba97
EC		 2680static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2681 char *buf)
2682{
2683 struct mlx5_ib_dev *dev =
2684 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2685 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2686}
2687
2688static ssize_t show_board(struct device *device, struct device_attribute *attr,
2689 char *buf)
2690{
2691 struct mlx5_ib_dev *dev =
2692 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2693 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2694 dev->mdev->board_id);
e126ba97
EC		 2695}
2696
2697static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2698static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2699static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2700static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2701static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2702
2703static struct device_attribute *mlx5_class_attributes[] = {
2704 &dev_attr_hw_rev,
e126ba97
EC		 2705 &dev_attr_hca_type,
2706 &dev_attr_board_id,
2707 &dev_attr_fw_pages,
2708 &dev_attr_reg_pages,
2709};
2710
7722f47e
HE		 2711static void pkey_change_handler(struct work_struct *work)
2712{
2713 struct mlx5_ib_port_resources *ports =
2714 container_of(work, struct mlx5_ib_port_resources,
2715 pkey_change_work);
2716
2717 mutex_lock(&ports->devr->mutex);
2718 mlx5_ib_gsi_pkey_change(ports->gsi);
2719 mutex_unlock(&ports->devr->mutex);
2720}
2721
89ea94a7
MG		 2722static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2723{
2724 struct mlx5_ib_qp *mqp;
2725 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2726 struct mlx5_core_cq *mcq;
2727 struct list_head cq_armed_list;
2728 unsigned long flags_qp;
2729 unsigned long flags_cq;
2730 unsigned long flags;
2731
2732 INIT_LIST_HEAD(&cq_armed_list);
2733
2734 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2735 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2736 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2737 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2738 if (mqp->sq.tail != mqp->sq.head) {
2739 send_mcq = to_mcq(mqp->ibqp.send_cq);
2740 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2741 if (send_mcq->mcq.comp &&
2742 mqp->ibqp.send_cq->comp_handler) {
2743 if (!send_mcq->mcq.reset_notify_added) {
2744 send_mcq->mcq.reset_notify_added = 1;
2745 list_add_tail(&send_mcq->mcq.reset_notify,
2746 &cq_armed_list);
2747 }
2748 }
2749 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2750 }
2751 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2752 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2753 /* no handling is needed for SRQ */
2754 if (!mqp->ibqp.srq) {
2755 if (mqp->rq.tail != mqp->rq.head) {
2756 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2757 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2758 if (recv_mcq->mcq.comp &&
2759 mqp->ibqp.recv_cq->comp_handler) {
2760 if (!recv_mcq->mcq.reset_notify_added) {
2761 recv_mcq->mcq.reset_notify_added = 1;
2762 list_add_tail(&recv_mcq->mcq.reset_notify,
2763 &cq_armed_list);
2764 }
2765 }
2766 spin_unlock_irqrestore(&recv_mcq->lock,
2767 flags_cq);
2768 }
2769 }
2770 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2771 }
2772 /*At that point all inflight post send were put to be executed as of we
2773 * lock/unlock above locks Now need to arm all involved CQs.
2774 */
2775 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2776 mcq->comp(mcq);
2777 }
2778 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2779}
2780
03404e8a
MG		 2781static void delay_drop_handler(struct work_struct *work)
2782{
2783 int err;
2784 struct mlx5_ib_delay_drop *delay_drop =
2785 container_of(work, struct mlx5_ib_delay_drop,
2786 delay_drop_work);
2787
fe248c3a
MG		 2788 atomic_inc(&delay_drop->events_cnt);
2789
03404e8a
MG		 2790 mutex_lock(&delay_drop->lock);
2791 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2792 delay_drop->timeout);
2793 if (err) {
2794 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2795 delay_drop->timeout);
2796 delay_drop->activate = false;
2797 }
2798 mutex_unlock(&delay_drop->lock);
2799}
2800
9603b61d 2801static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2802 enum mlx5_dev_event event, unsigned long param)
e126ba97 2803{
9603b61d 2804 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2805 struct ib_event ibev;
dbaaff2a 2806 bool fatal = false;
e126ba97
EC		 2807 u8 port = 0;
2808
2809 switch (event) {
2810 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2811 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2812 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 2813 fatal = true;
e126ba97
EC		 2814 break;
2815
2816 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2817 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2818 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2819 port = (u8)param;
5ec8c83e
AH		 2820
2821 /* In RoCE, port up/down events are handled in
2822 * mlx5_netdev_event().
2823 */
2824 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2825 IB_LINK_LAYER_ETHERNET)
2826 return;
2827
2828 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2829 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2830 break;
2831
e126ba97
EC		 2832 case MLX5_DEV_EVENT_LID_CHANGE:
2833 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2834 port = (u8)param;
e126ba97
EC		 2835 break;
2836
2837 case MLX5_DEV_EVENT_PKEY_CHANGE:
2838 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2839 port = (u8)param;
7722f47e
HE		 2840
2841 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2842 break;
2843
2844 case MLX5_DEV_EVENT_GUID_CHANGE:
2845 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2846 port = (u8)param;
e126ba97
EC		 2847 break;
2848
2849 case MLX5_DEV_EVENT_CLIENT_REREG:
2850 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2851 port = (u8)param;
e126ba97 2852 break;
03404e8a
MG		 2853 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
2854 schedule_work(&ibdev->delay_drop.delay_drop_work);
2855 goto out;
bdc37924 2856 default:
03404e8a 2857 goto out;
e126ba97
EC		 2858 }
2859
2860 ibev.device = &ibdev->ib_dev;
2861 ibev.element.port_num = port;
2862
a0c84c32
EC		 2863 if (port < 1 || port > ibdev->num_ports) {
2864 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 2865 goto out;
a0c84c32
EC		 2866 }
2867
e126ba97
EC		 2868 if (ibdev->ib_active)
2869 ib_dispatch_event(&ibev);
dbaaff2a
EC		 2870
2871 if (fatal)
2872 ibdev->ib_active = false;
03404e8a
MG		 2873
2874out:
2875 return;
e126ba97
EC		 2876}
2877
c43f1112
MG		 2878static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2879{
2880 struct mlx5_hca_vport_context vport_ctx;
2881 int err;
2882 int port;
2883
2884 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2885 dev->mdev->port_caps[port - 1].has_smi = false;
2886 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2887 MLX5_CAP_PORT_TYPE_IB) {
2888 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2889 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2890 port, 0,
2891 &vport_ctx);
2892 if (err) {
2893 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2894 port, err);
2895 return err;
2896 }
2897 dev->mdev->port_caps[port - 1].has_smi =
2898 vport_ctx.has_smi;
2899 } else {
2900 dev->mdev->port_caps[port - 1].has_smi = true;
2901 }
2902 }
2903 }
2904 return 0;
2905}
2906
e126ba97
EC		 2907static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2908{
2909 int port;
2910
938fe83c 2911 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2912 mlx5_query_ext_port_caps(dev, port);
2913}
2914
2915static int get_port_caps(struct mlx5_ib_dev *dev)
2916{
2917 struct ib_device_attr *dprops = NULL;
2918 struct ib_port_attr *pprops = NULL;
f614fc15 2919 int err = -ENOMEM;
e126ba97 2920 int port;
2528e33e 2921 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2922
2923 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2924 if (!pprops)
2925 goto out;
2926
2927 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2928 if (!dprops)
2929 goto out;
2930
c43f1112
MG		 2931 err = set_has_smi_cap(dev);
2932 if (err)
2933 goto out;
2934
2528e33e 2935 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2936 if (err) {
2937 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2938 goto out;
2939 }
2940
938fe83c 2941 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 2942 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 2943 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2944 if (err) {
938fe83c
SM		 2945 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2946 port, err);
e126ba97
EC		 2947 break;
2948 }
938fe83c
SM		 2949 dev->mdev->port_caps[port - 1].pkey_table_len =
2950 dprops->max_pkeys;
2951 dev->mdev->port_caps[port - 1].gid_table_len =
2952 pprops->gid_tbl_len;
e126ba97
EC		 2953 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2954 dprops->max_pkeys, pprops->gid_tbl_len);
2955 }
2956
2957out:
2958 kfree(pprops);
2959 kfree(dprops);
2960
2961 return err;
2962}
2963
2964static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2965{
2966 int err;
2967
2968 err = mlx5_mr_cache_cleanup(dev);
2969 if (err)
2970 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2971
2972 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2973 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2974 ib_dealloc_pd(dev->umrc.pd);
2975}
2976
2977enum {
2978 MAX_UMR_WR = 128,
2979};
2980
2981static int create_umr_res(struct mlx5_ib_dev *dev)
2982{
2983 struct ib_qp_init_attr *init_attr = NULL;
2984 struct ib_qp_attr *attr = NULL;
2985 struct ib_pd *pd;
2986 struct ib_cq *cq;
2987 struct ib_qp *qp;
e126ba97
EC		 2988 int ret;
2989
2990 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2991 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2992 if (!attr || !init_attr) {
2993 ret = -ENOMEM;
2994 goto error_0;
2995 }
2996
ed082d36 2997 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 2998 if (IS_ERR(pd)) {
2999 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3000 ret = PTR_ERR(pd);
3001 goto error_0;
3002 }
3003
add08d76 3004 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3005 if (IS_ERR(cq)) {
3006 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3007 ret = PTR_ERR(cq);
3008 goto error_2;
3009 }
e126ba97
EC		 3010
3011 init_attr->send_cq = cq;
3012 init_attr->recv_cq = cq;
3013 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3014 init_attr->cap.max_send_wr = MAX_UMR_WR;
3015 init_attr->cap.max_send_sge = 1;
3016 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3017 init_attr->port_num = 1;
3018 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3019 if (IS_ERR(qp)) {
3020 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3021 ret = PTR_ERR(qp);
3022 goto error_3;
3023 }
3024 qp->device = &dev->ib_dev;
3025 qp->real_qp = qp;
3026 qp->uobject = NULL;
3027 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3028
3029 attr->qp_state = IB_QPS_INIT;
3030 attr->port_num = 1;
3031 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3032 IB_QP_PORT, NULL);
3033 if (ret) {
3034 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3035 goto error_4;
3036 }
3037
3038 memset(attr, 0, sizeof(*attr));
3039 attr->qp_state = IB_QPS_RTR;
3040 attr->path_mtu = IB_MTU_256;
3041
3042 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3043 if (ret) {
3044 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3045 goto error_4;
3046 }
3047
3048 memset(attr, 0, sizeof(*attr));
3049 attr->qp_state = IB_QPS_RTS;
3050 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3051 if (ret) {
3052 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3053 goto error_4;
3054 }
3055
3056 dev->umrc.qp = qp;
3057 dev->umrc.cq = cq;
e126ba97
EC		 3058 dev->umrc.pd = pd;
3059
3060 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3061 ret = mlx5_mr_cache_init(dev);
3062 if (ret) {
3063 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3064 goto error_4;
3065 }
3066
3067 kfree(attr);
3068 kfree(init_attr);
3069
3070 return 0;
3071
3072error_4:
3073 mlx5_ib_destroy_qp(qp);
3074
3075error_3:
add08d76 3076 ib_free_cq(cq);
e126ba97
EC		 3077
3078error_2:
e126ba97
EC		 3079 ib_dealloc_pd(pd);
3080
3081error_0:
3082 kfree(attr);
3083 kfree(init_attr);
3084 return ret;
3085}
3086
6e8484c5
MG		 3087static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3088{
3089 switch (umr_fence_cap) {
3090 case MLX5_CAP_UMR_FENCE_NONE:
3091 return MLX5_FENCE_MODE_NONE;
3092 case MLX5_CAP_UMR_FENCE_SMALL:
3093 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3094 default:
3095 return MLX5_FENCE_MODE_STRONG_ORDERING;
3096 }
3097}
3098
e126ba97
EC		 3099static int create_dev_resources(struct mlx5_ib_resources *devr)
3100{
3101 struct ib_srq_init_attr attr;
3102 struct mlx5_ib_dev *dev;
bcf4c1ea 3103 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3104 int port;
e126ba97
EC		 3105 int ret = 0;
3106
3107 dev = container_of(devr, struct mlx5_ib_dev, devr);
3108
d16e91da
HE		 3109 mutex_init(&devr->mutex);
3110
e126ba97
EC		 3111 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3112 if (IS_ERR(devr->p0)) {
3113 ret = PTR_ERR(devr->p0);
3114 goto error0;
3115 }
3116 devr->p0->device = &dev->ib_dev;
3117 devr->p0->uobject = NULL;
3118 atomic_set(&devr->p0->usecnt, 0);
3119
bcf4c1ea 3120 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3121 if (IS_ERR(devr->c0)) {
3122 ret = PTR_ERR(devr->c0);
3123 goto error1;
3124 }
3125 devr->c0->device = &dev->ib_dev;
3126 devr->c0->uobject = NULL;
3127 devr->c0->comp_handler = NULL;
3128 devr->c0->event_handler = NULL;
3129 devr->c0->cq_context = NULL;
3130 atomic_set(&devr->c0->usecnt, 0);
3131
3132 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3133 if (IS_ERR(devr->x0)) {
3134 ret = PTR_ERR(devr->x0);
3135 goto error2;
3136 }
3137 devr->x0->device = &dev->ib_dev;
3138 devr->x0->inode = NULL;
3139 atomic_set(&devr->x0->usecnt, 0);
3140 mutex_init(&devr->x0->tgt_qp_mutex);
3141 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3142
3143 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3144 if (IS_ERR(devr->x1)) {
3145 ret = PTR_ERR(devr->x1);
3146 goto error3;
3147 }
3148 devr->x1->device = &dev->ib_dev;
3149 devr->x1->inode = NULL;
3150 atomic_set(&devr->x1->usecnt, 0);
3151 mutex_init(&devr->x1->tgt_qp_mutex);
3152 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3153
3154 memset(&attr, 0, sizeof(attr));
3155 attr.attr.max_sge = 1;
3156 attr.attr.max_wr = 1;
3157 attr.srq_type = IB_SRQT_XRC;
3158 attr.ext.xrc.cq = devr->c0;
3159 attr.ext.xrc.xrcd = devr->x0;
3160
3161 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3162 if (IS_ERR(devr->s0)) {
3163 ret = PTR_ERR(devr->s0);
3164 goto error4;
3165 }
3166 devr->s0->device = &dev->ib_dev;
3167 devr->s0->pd = devr->p0;
3168 devr->s0->uobject = NULL;
3169 devr->s0->event_handler = NULL;
3170 devr->s0->srq_context = NULL;
3171 devr->s0->srq_type = IB_SRQT_XRC;
3172 devr->s0->ext.xrc.xrcd = devr->x0;
3173 devr->s0->ext.xrc.cq = devr->c0;
3174 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3175 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
3176 atomic_inc(&devr->p0->usecnt);
3177 atomic_set(&devr->s0->usecnt, 0);
3178
4aa17b28
HA		 3179 memset(&attr, 0, sizeof(attr));
3180 attr.attr.max_sge = 1;
3181 attr.attr.max_wr = 1;
3182 attr.srq_type = IB_SRQT_BASIC;
3183 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3184 if (IS_ERR(devr->s1)) {
3185 ret = PTR_ERR(devr->s1);
3186 goto error5;
3187 }
3188 devr->s1->device = &dev->ib_dev;
3189 devr->s1->pd = devr->p0;
3190 devr->s1->uobject = NULL;
3191 devr->s1->event_handler = NULL;
3192 devr->s1->srq_context = NULL;
3193 devr->s1->srq_type = IB_SRQT_BASIC;
3194 devr->s1->ext.xrc.cq = devr->c0;
3195 atomic_inc(&devr->p0->usecnt);
3196 atomic_set(&devr->s0->usecnt, 0);
3197
7722f47e
HE		 3198 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3199 INIT_WORK(&devr->ports[port].pkey_change_work,
3200 pkey_change_handler);
3201 devr->ports[port].devr = devr;
3202 }
3203
e126ba97
EC		 3204 return 0;
3205
4aa17b28
HA		 3206error5:
3207 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3208error4:
3209 mlx5_ib_dealloc_xrcd(devr->x1);
3210error3:
3211 mlx5_ib_dealloc_xrcd(devr->x0);
3212error2:
3213 mlx5_ib_destroy_cq(devr->c0);
3214error1:
3215 mlx5_ib_dealloc_pd(devr->p0);
3216error0:
3217 return ret;
3218}
3219
3220static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3221{
7722f47e
HE		 3222 struct mlx5_ib_dev *dev =
3223 container_of(devr, struct mlx5_ib_dev, devr);
3224 int port;
3225
4aa17b28 3226 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3227 mlx5_ib_destroy_srq(devr->s0);
3228 mlx5_ib_dealloc_xrcd(devr->x0);
3229 mlx5_ib_dealloc_xrcd(devr->x1);
3230 mlx5_ib_destroy_cq(devr->c0);
3231 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3232
3233 /* Make sure no change P_Key work items are still executing */
3234 for (port = 0; port < dev->num_ports; ++port)
3235 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3236}
3237
e53505a8
AS		 3238static u32 get_core_cap_flags(struct ib_device *ibdev)
3239{
3240 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3241 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3242 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3243 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3244 u32 ret = 0;
3245
3246 if (ll == IB_LINK_LAYER_INFINIBAND)
3247 return RDMA_CORE_PORT_IBA_IB;
3248
72cd5717
OG		 3249 ret = RDMA_CORE_PORT_RAW_PACKET;
3250
e53505a8 3251 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3252 return ret;
e53505a8
AS		 3253
3254 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3255 return ret;
e53505a8
AS		 3256
3257 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3258 ret |= RDMA_CORE_PORT_IBA_ROCE;
3259
3260 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3261 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3262
3263 return ret;
3264}
3265
7738613e
IW		 3266static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3267 struct ib_port_immutable *immutable)
3268{
3269 struct ib_port_attr attr;
ca5b91d6
OG		 3270 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3271 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3272 int err;
3273
c4550c63
OG		 3274 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3275
3276 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3277 if (err)
3278 return err;
3279
3280 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3281 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3282 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3283 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3284 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3285
3286 return 0;
3287}
3288
9abb0d1b 3289static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3290{
3291 struct mlx5_ib_dev *dev =
3292 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3293 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3294 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3295 fw_rev_sub(dev->mdev));
c7342823
IW		 3296}
3297
45f95acd 3298static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3299{
3300 struct mlx5_core_dev *mdev = dev->mdev;
3301 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3302 MLX5_FLOW_NAMESPACE_LAG);
3303 struct mlx5_flow_table *ft;
3304 int err;
3305
3306 if (!ns || !mlx5_lag_is_active(mdev))
3307 return 0;
3308
3309 err = mlx5_cmd_create_vport_lag(mdev);
3310 if (err)
3311 return err;
3312
3313 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3314 if (IS_ERR(ft)) {
3315 err = PTR_ERR(ft);
3316 goto err_destroy_vport_lag;
3317 }
3318
3319 dev->flow_db.lag_demux_ft = ft;
3320 return 0;
3321
3322err_destroy_vport_lag:
3323 mlx5_cmd_destroy_vport_lag(mdev);
3324 return err;
3325}
3326
45f95acd 3327static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3328{
3329 struct mlx5_core_dev *mdev = dev->mdev;
3330
3331 if (dev->flow_db.lag_demux_ft) {
3332 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3333 dev->flow_db.lag_demux_ft = NULL;
3334
3335 mlx5_cmd_destroy_vport_lag(mdev);
3336 }
3337}
3338
d012f5d6
OG		 3339static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3340{
3341 int err;
3342
3343 dev->roce.nb.notifier_call = mlx5_netdev_event;
3344 err = register_netdevice_notifier(&dev->roce.nb);
3345 if (err) {
3346 dev->roce.nb.notifier_call = NULL;
3347 return err;
3348 }
3349
3350 return 0;
3351}
3352
3353static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3354{
3355 if (dev->roce.nb.notifier_call) {
3356 unregister_netdevice_notifier(&dev->roce.nb);
3357 dev->roce.nb.notifier_call = NULL;
3358 }
3359}
3360
45f95acd 3361static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3362{
e53505a8
AS		 3363 int err;
3364
d012f5d6
OG		 3365 err = mlx5_add_netdev_notifier(dev);
3366 if (err)
e53505a8
AS		 3367 return err;
3368
ca5b91d6
OG		 3369 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3370 err = mlx5_nic_vport_enable_roce(dev->mdev);
3371 if (err)
3372 goto err_unregister_netdevice_notifier;
3373 }
e53505a8 3374
45f95acd 3375 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3376 if (err)
3377 goto err_disable_roce;
3378
e53505a8
AS		 3379 return 0;
3380
9ef9c640 3381err_disable_roce:
ca5b91d6
OG		 3382 if (MLX5_CAP_GEN(dev->mdev, roce))
3383 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3384
e53505a8 3385err_unregister_netdevice_notifier:
d012f5d6 3386 mlx5_remove_netdev_notifier(dev);
e53505a8 3387 return err;
fc24fc5e
AS		 3388}
3389
45f95acd 3390static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3391{
45f95acd 3392 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3393 if (MLX5_CAP_GEN(dev->mdev, roce))
3394 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3395}
3396
e1f24a79 3397struct mlx5_ib_counter {
7c16f477
KH		 3398 const char *name;
3399 size_t offset;
3400};
3401
3402#define INIT_Q_COUNTER(_name) \
3403 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3404
e1f24a79 3405static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3406 INIT_Q_COUNTER(rx_write_requests),
3407 INIT_Q_COUNTER(rx_read_requests),
3408 INIT_Q_COUNTER(rx_atomic_requests),
3409 INIT_Q_COUNTER(out_of_buffer),
3410};
3411
e1f24a79 3412static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3413 INIT_Q_COUNTER(out_of_sequence),
3414};
3415
e1f24a79 3416static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3417 INIT_Q_COUNTER(duplicate_request),
3418 INIT_Q_COUNTER(rnr_nak_retry_err),
3419 INIT_Q_COUNTER(packet_seq_err),
3420 INIT_Q_COUNTER(implied_nak_seq_err),
3421 INIT_Q_COUNTER(local_ack_timeout_err),
3422};
3423
e1f24a79
PP		 3424#define INIT_CONG_COUNTER(_name) \
3425 { .name = #_name, .offset = \
3426 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3427
3428static const struct mlx5_ib_counter cong_cnts[] = {
3429 INIT_CONG_COUNTER(rp_cnp_ignored),
3430 INIT_CONG_COUNTER(rp_cnp_handled),
3431 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3432 INIT_CONG_COUNTER(np_cnp_sent),
3433};
3434
58dcb60a
PP		 3435static const struct mlx5_ib_counter extended_err_cnts[] = {
3436 INIT_Q_COUNTER(resp_local_length_error),
3437 INIT_Q_COUNTER(resp_cqe_error),
3438 INIT_Q_COUNTER(req_cqe_error),
3439 INIT_Q_COUNTER(req_remote_invalid_request),
3440 INIT_Q_COUNTER(req_remote_access_errors),
3441 INIT_Q_COUNTER(resp_remote_access_errors),
3442 INIT_Q_COUNTER(resp_cqe_flush_error),
3443 INIT_Q_COUNTER(req_cqe_flush_error),
3444};
3445
e1f24a79 3446static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3447{
3448 unsigned int i;
3449
7c16f477 3450 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3451 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3452 dev->port[i].cnts.set_id);
3453 kfree(dev->port[i].cnts.names);
3454 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3455 }
3456}
3457
e1f24a79
PP		 3458static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3459 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3460{
3461 u32 num_counters;
3462
3463 num_counters = ARRAY_SIZE(basic_q_cnts);
3464
3465 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3466 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3467
3468 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3469 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 3470
3471 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3472 num_counters += ARRAY_SIZE(extended_err_cnts);
3473
e1f24a79 3474 cnts->num_q_counters = num_counters;
7c16f477 3475
e1f24a79
PP		 3476 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3477 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3478 num_counters += ARRAY_SIZE(cong_cnts);
3479 }
3480
3481 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3482 if (!cnts->names)
7c16f477
KH		 3483 return -ENOMEM;
3484
e1f24a79
PP		 3485 cnts->offsets = kcalloc(num_counters,
3486 sizeof(cnts->offsets), GFP_KERNEL);
3487 if (!cnts->offsets)
7c16f477
KH		 3488 goto err_names;
3489
7c16f477
KH		 3490 return 0;
3491
3492err_names:
e1f24a79 3493 kfree(cnts->names);
7c16f477
KH		 3494 return -ENOMEM;
3495}
3496
e1f24a79
PP		 3497static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3498 const char **names,
3499 size_t *offsets)
7c16f477
KH		 3500{
3501 int i;
3502 int j = 0;
3503
3504 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3505 names[j] = basic_q_cnts[i].name;
3506 offsets[j] = basic_q_cnts[i].offset;
3507 }
3508
3509 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3510 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3511 names[j] = out_of_seq_q_cnts[i].name;
3512 offsets[j] = out_of_seq_q_cnts[i].offset;
3513 }
3514 }
3515
3516 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3517 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3518 names[j] = retrans_q_cnts[i].name;
3519 offsets[j] = retrans_q_cnts[i].offset;
3520 }
3521 }
e1f24a79 3522
58dcb60a
PP		 3523 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3524 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3525 names[j] = extended_err_cnts[i].name;
3526 offsets[j] = extended_err_cnts[i].offset;
3527 }
3528 }
3529
e1f24a79
PP		 3530 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3531 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3532 names[j] = cong_cnts[i].name;
3533 offsets[j] = cong_cnts[i].offset;
3534 }
3535 }
0837e86a
MB		 3536}
3537
e1f24a79 3538static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3539{
3540 int i;
3541 int ret;
3542
3543 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3544 struct mlx5_ib_port *port = &dev->port[i];
3545
0837e86a 3546 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3547 &port->cnts.set_id);
0837e86a
MB		 3548 if (ret) {
3549 mlx5_ib_warn(dev,
3550 "couldn't allocate queue counter for port %d, err %d\n",
3551 i + 1, ret);
3552 goto dealloc_counters;
3553 }
7c16f477 3554
e1f24a79 3555 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3556 if (ret)
3557 goto dealloc_counters;
3558
e1f24a79
PP		 3559 mlx5_ib_fill_counters(dev, port->cnts.names,
3560 port->cnts.offsets);
0837e86a
MB		 3561 }
3562
3563 return 0;
3564
3565dealloc_counters:
3566 while (--i >= 0)
3567 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3568 dev->port[i].cnts.set_id);
0837e86a
MB		 3569
3570 return ret;
3571}
3572
0ad17a8f
MB		 3573static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3574 u8 port_num)
3575{
7c16f477
KH		 3576 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3577 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3578
3579 /* We support only per port stats */
3580 if (port_num == 0)
3581 return NULL;
3582
e1f24a79
PP		 3583 return rdma_alloc_hw_stats_struct(port->cnts.names,
3584 port->cnts.num_q_counters +
3585 port->cnts.num_cong_counters,
0ad17a8f
MB		 3586 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3587}
3588
e1f24a79
PP		 3589static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3590 struct mlx5_ib_port *port,
3591 struct rdma_hw_stats *stats)
0ad17a8f 3592{
0ad17a8f
MB		 3593 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3594 void *out;
3595 __be32 val;
e1f24a79 3596 int ret, i;
0ad17a8f 3597
1b9a07ee 3598 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3599 if (!out)
3600 return -ENOMEM;
3601
3602 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3603 port->cnts.set_id, 0,
0ad17a8f
MB		 3604 out, outlen);
3605 if (ret)
3606 goto free;
3607
e1f24a79
PP		 3608 for (i = 0; i < port->cnts.num_q_counters; i++) {
3609 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3610 stats->value[i] = (u64)be32_to_cpu(val);
3611 }
7c16f477 3612
0ad17a8f
MB		 3613free:
3614 kvfree(out);
e1f24a79
PP		 3615 return ret;
3616}
3617
3618static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3619 struct mlx5_ib_port *port,
3620 struct rdma_hw_stats *stats)
3621{
3622 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3623 void *out;
3624 int ret, i;
3625 int offset = port->cnts.num_q_counters;
3626
1b9a07ee 3627 out = kvzalloc(outlen, GFP_KERNEL);
e1f24a79
PP		 3628 if (!out)
3629 return -ENOMEM;
3630
3631 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3632 if (ret)
3633 goto free;
3634
3635 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3636 stats->value[i + offset] =
3637 be64_to_cpup((__be64 *)(out +
3638 port->cnts.offsets[i + offset]));
3639 }
3640
3641free:
3642 kvfree(out);
3643 return ret;
3644}
3645
3646static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3647 struct rdma_hw_stats *stats,
3648 u8 port_num, int index)
3649{
3650 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3651 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3652 int ret, num_counters;
3653
3654 if (!stats)
3655 return -EINVAL;
3656
3657 ret = mlx5_ib_query_q_counters(dev, port, stats);
3658 if (ret)
3659 return ret;
3660 num_counters = port->cnts.num_q_counters;
3661
3662 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3663 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3664 if (ret)
3665 return ret;
3666 num_counters += port->cnts.num_cong_counters;
3667 }
3668
3669 return num_counters;
0ad17a8f
MB		 3670}
3671
8e959601
NV		 3672static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3673{
3674 return mlx5_rdma_netdev_free(netdev);
3675}
3676
693dfd5a
ES		 3677static struct net_device*
3678mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3679 u8 port_num,
3680 enum rdma_netdev_t type,
3681 const char *name,
3682 unsigned char name_assign_type,
3683 void (*setup)(struct net_device *))
3684{
8e959601
NV		 3685 struct net_device *netdev;
3686 struct rdma_netdev *rn;
3687
693dfd5a
ES		 3688 if (type != RDMA_NETDEV_IPOIB)
3689 return ERR_PTR(-EOPNOTSUPP);
3690
8e959601
NV		 3691 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3692 name, setup);
3693 if (likely(!IS_ERR_OR_NULL(netdev))) {
3694 rn = netdev_priv(netdev);
3695 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3696 }
3697 return netdev;
693dfd5a
ES		 3698}
3699
fe248c3a
MG		 3700static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3701{
3702 if (!dev->delay_drop.dbg)
3703 return;
3704 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3705 kfree(dev->delay_drop.dbg);
3706 dev->delay_drop.dbg = NULL;
3707}
3708
03404e8a
MG		 3709static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3710{
3711 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3712 return;
3713
3714 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 3715 delay_drop_debugfs_cleanup(dev);
3716}
3717
3718static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3719 size_t count, loff_t *pos)
3720{
3721 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3722 char lbuf[20];
3723 int len;
3724
3725 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3726 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3727}
3728
3729static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3730 size_t count, loff_t *pos)
3731{
3732 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3733 u32 timeout;
3734 u32 var;
3735
3736 if (kstrtouint_from_user(buf, count, 0, &var))
3737 return -EFAULT;
3738
3739 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3740 1000);
3741 if (timeout != var)
3742 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3743 timeout);
3744
3745 delay_drop->timeout = timeout;
3746
3747 return count;
3748}
3749
3750static const struct file_operations fops_delay_drop_timeout = {
3751 .owner = THIS_MODULE,
3752 .open = simple_open,
3753 .write = delay_drop_timeout_write,
3754 .read = delay_drop_timeout_read,
3755};
3756
3757static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3758{
3759 struct mlx5_ib_dbg_delay_drop *dbg;
3760
3761 if (!mlx5_debugfs_root)
3762 return 0;
3763
3764 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3765 if (!dbg)
3766 return -ENOMEM;
3767
3768 dbg->dir_debugfs =
3769 debugfs_create_dir("delay_drop",
3770 dev->mdev->priv.dbg_root);
3771 if (!dbg->dir_debugfs)
3772 return -ENOMEM;
3773
3774 dbg->events_cnt_debugfs =
3775 debugfs_create_atomic_t("num_timeout_events", 0400,
3776 dbg->dir_debugfs,
3777 &dev->delay_drop.events_cnt);
3778 if (!dbg->events_cnt_debugfs)
3779 goto out_debugfs;
3780
3781 dbg->rqs_cnt_debugfs =
3782 debugfs_create_atomic_t("num_rqs", 0400,
3783 dbg->dir_debugfs,
3784 &dev->delay_drop.rqs_cnt);
3785 if (!dbg->rqs_cnt_debugfs)
3786 goto out_debugfs;
3787
3788 dbg->timeout_debugfs =
3789 debugfs_create_file("timeout", 0600,
3790 dbg->dir_debugfs,
3791 &dev->delay_drop,
3792 &fops_delay_drop_timeout);
3793 if (!dbg->timeout_debugfs)
3794 goto out_debugfs;
3795
4a5fd5d2
MG		 3796 dev->delay_drop.dbg = dbg;
3797
fe248c3a
MG		 3798 return 0;
3799
3800out_debugfs:
3801 delay_drop_debugfs_cleanup(dev);
3802 return -ENOMEM;
03404e8a
MG		 3803}
3804
3805static void init_delay_drop(struct mlx5_ib_dev *dev)
3806{
3807 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3808 return;
3809
3810 mutex_init(&dev->delay_drop.lock);
3811 dev->delay_drop.dev = dev;
3812 dev->delay_drop.activate = false;
3813 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3814 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 3815 atomic_set(&dev->delay_drop.rqs_cnt, 0);
3816 atomic_set(&dev->delay_drop.events_cnt, 0);
3817
3818 if (delay_drop_debugfs_init(dev))
3819 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 3820}
3821
40b24403
SG		 3822const struct cpumask *mlx5_ib_get_vector_affinity(struct ib_device *ibdev,
3823 int comp_vector)
3824{
3825 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3826
3827 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
3828}
3829
9603b61d 3830static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 3831{
e126ba97 3832 struct mlx5_ib_dev *dev;
ebd61f68
AS		 3833 enum rdma_link_layer ll;
3834 int port_type_cap;
4babcf97 3835 const char *name;
e126ba97
EC		 3836 int err;
3837 int i;
3838
ebd61f68
AS		 3839 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3840 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3841
e126ba97
EC		 3842 printk_once(KERN_INFO "%s", mlx5_version);
3843
3844 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3845 if (!dev)
9603b61d 3846 return NULL;
e126ba97 3847
9603b61d 3848 dev->mdev = mdev;
e126ba97 3849
0837e86a
MB		 3850 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3851 GFP_KERNEL);
3852 if (!dev->port)
3853 goto err_dealloc;
3854
fc24fc5e 3855 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3856 err = get_port_caps(dev);
3857 if (err)
0837e86a 3858 goto err_free_port;
e126ba97 3859
1b5daf11
MD		 3860 if (mlx5_use_mad_ifc(dev))
3861 get_ext_port_caps(dev);
e126ba97 3862
4babcf97
AH		 3863 if (!mlx5_lag_is_active(mdev))
3864 name = "mlx5_%d";
3865 else
3866 name = "mlx5_bond_%d";
3867
3868 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3869 dev->ib_dev.owner = THIS_MODULE;
3870 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3871 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3872 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3873 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3874 dev->ib_dev.num_comp_vectors =
3875 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 3876 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97
EC		 3877
3878 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3879 dev->ib_dev.uverbs_cmd_mask =
3880 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3881 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3882 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3883 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3884 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 3885 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3886 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 3887 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3888 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3889 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3890 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3891 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3892 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3893 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3894 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3895 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3896 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3897 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3898 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3899 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3900 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3901 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3902 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3903 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3904 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3905 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 3906 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 3907 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3908 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349
BW		 3909 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3910 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
e126ba97
EC		 3911
3912 dev->ib_dev.query_device = mlx5_ib_query_device;
3913 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 3914 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 3915 if (ll == IB_LINK_LAYER_ETHERNET)
3916 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 3917 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 3918 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3919 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 3920 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3921 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3922 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3923 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3924 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3925 dev->ib_dev.mmap = mlx5_ib_mmap;
3926 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3927 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3928 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3929 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3930 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3931 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3932 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3933 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3934 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3935 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3936 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3937 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3938 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3939 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3940 dev->ib_dev.post_send = mlx5_ib_post_send;
3941 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3942 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3943 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3944 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3945 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3946 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3947 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3948 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3949 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 3950 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 3951 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3952 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3953 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3954 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 3955 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 3956 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 3957 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 3958 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 3959 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 3960 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 3961 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 3962 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 3963
eff901d3
EC		 3964 if (mlx5_core_is_pf(mdev)) {
3965 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3966 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3967 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3968 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3969 }
e126ba97 3970
7c2344c3
MG		 3971 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3972
938fe83c 3973 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 3974
6e8484c5
MG		 3975 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3976
d2370e0a
MB		 3977 if (MLX5_CAP_GEN(mdev, imaicl)) {
3978 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3979 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3980 dev->ib_dev.uverbs_cmd_mask |=
3981 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3982 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3983 }
3984
7c16f477 3985 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
0ad17a8f
MB		 3986 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3987 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3988 }
3989
938fe83c 3990 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 3991 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3992 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3993 dev->ib_dev.uverbs_cmd_mask |=
3994 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3995 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3996 }
3997
81e30880
YH		 3998 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3999 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4000 dev->ib_dev.uverbs_ex_cmd_mask |=
4001 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4002 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4003
048ccca8 4004 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8 4005 IB_LINK_LAYER_ETHERNET) {
79b20a6c
YH		 4006 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4007 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4008 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 4009 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4010 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8 4011 dev->ib_dev.uverbs_ex_cmd_mask |=
79b20a6c
YH		 4012 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4013 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 4014 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4015 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4016 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 4017 }
e126ba97
EC		 4018 err = init_node_data(dev);
4019 if (err)
90be7c8a 4020 goto err_free_port;
e126ba97 4021
038d2ef8 4022 mutex_init(&dev->flow_db.lock);
e126ba97 4023 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 4024 INIT_LIST_HEAD(&dev->qp_list);
4025 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 4026
fc24fc5e 4027 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4028 err = mlx5_enable_eth(dev);
fc24fc5e 4029 if (err)
90be7c8a 4030 goto err_free_port;
fd65f1b8 4031 dev->roce.last_port_state = IB_PORT_DOWN;
fc24fc5e
AS		 4032 }
4033
e126ba97
EC		 4034 err = create_dev_resources(&dev->devr);
4035 if (err)
45f95acd 4036 goto err_disable_eth;
e126ba97 4037
6aec21f6 4038 err = mlx5_ib_odp_init_one(dev);
281d1a92 4039 if (err)
e126ba97
EC		 4040 goto err_rsrc;
4041
45bded2c 4042 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
e1f24a79 4043 err = mlx5_ib_alloc_counters(dev);
45bded2c
KH		 4044 if (err)
4045 goto err_odp;
4046 }
6aec21f6 4047
4a2da0b8
PP		 4048 err = mlx5_ib_init_cong_debugfs(dev);
4049 if (err)
4050 goto err_cnt;
4051
5fe9dec0
EC		 4052 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4053 if (!dev->mdev->priv.uar)
4a2da0b8 4054 goto err_cong;
5fe9dec0
EC		 4055
4056 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4057 if (err)
4058 goto err_uar_page;
4059
4060 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4061 if (err)
4062 goto err_bfreg;
4063
0837e86a
MB		 4064 err = ib_register_device(&dev->ib_dev, NULL);
4065 if (err)
5fe9dec0 4066 goto err_fp_bfreg;
0837e86a 4067
e126ba97
EC		 4068 err = create_umr_res(dev);
4069 if (err)
4070 goto err_dev;
4071
03404e8a
MG		 4072 init_delay_drop(dev);
4073
e126ba97 4074 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 4075 err = device_create_file(&dev->ib_dev.dev,
4076 mlx5_class_attributes[i]);
4077 if (err)
03404e8a 4078 goto err_delay_drop;
e126ba97
EC		 4079 }
4080
c85023e1
HN		 4081 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4082 MLX5_CAP_GEN(mdev, disable_local_lb))
4083 mutex_init(&dev->lb_mutex);
4084
e126ba97
EC		 4085 dev->ib_active = true;
4086
9603b61d 4087 return dev;
e126ba97 4088
03404e8a
MG		 4089err_delay_drop:
4090 cancel_delay_drop(dev);
e126ba97
EC		 4091 destroy_umrc_res(dev);
4092
4093err_dev:
4094 ib_unregister_device(&dev->ib_dev);
4095
5fe9dec0
EC		 4096err_fp_bfreg:
4097 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4098
4099err_bfreg:
4100 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4101
4102err_uar_page:
4103 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4104
e1f24a79 4105err_cnt:
4a2da0b8
PP		 4106 mlx5_ib_cleanup_cong_debugfs(dev);
4107err_cong:
45bded2c 4108 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4109 mlx5_ib_dealloc_counters(dev);
0837e86a 4110
6aec21f6
HE		 4111err_odp:
4112 mlx5_ib_odp_remove_one(dev);
4113
e126ba97
EC		 4114err_rsrc:
4115 destroy_dev_resources(&dev->devr);
4116
45f95acd 4117err_disable_eth:
5ec8c83e 4118 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4119 mlx5_disable_eth(dev);
d012f5d6 4120 mlx5_remove_netdev_notifier(dev);
5ec8c83e 4121 }
fc24fc5e 4122
0837e86a
MB		 4123err_free_port:
4124 kfree(dev->port);
4125
9603b61d 4126err_dealloc:
e126ba97
EC		 4127 ib_dealloc_device((struct ib_device *)dev);
4128
9603b61d 4129 return NULL;
e126ba97
EC		 4130}
4131
9603b61d 4132static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 4133{
9603b61d 4134 struct mlx5_ib_dev *dev = context;
fc24fc5e 4135 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 4136
03404e8a 4137 cancel_delay_drop(dev);
d012f5d6 4138 mlx5_remove_netdev_notifier(dev);
e126ba97 4139 ib_unregister_device(&dev->ib_dev);
5fe9dec0
EC		 4140 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4141 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4142 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
4a2da0b8 4143 mlx5_ib_cleanup_cong_debugfs(dev);
45bded2c 4144 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4145 mlx5_ib_dealloc_counters(dev);
eefd56e5 4146 destroy_umrc_res(dev);
6aec21f6 4147 mlx5_ib_odp_remove_one(dev);
e126ba97 4148 destroy_dev_resources(&dev->devr);
fc24fc5e 4149 if (ll == IB_LINK_LAYER_ETHERNET)
45f95acd 4150 mlx5_disable_eth(dev);
0837e86a 4151 kfree(dev->port);
e126ba97
EC		 4152 ib_dealloc_device(&dev->ib_dev);
4153}
4154
9603b61d
JM		 4155static struct mlx5_interface mlx5_ib_interface = {
4156 .add = mlx5_ib_add,
4157 .remove = mlx5_ib_remove,
4158 .event = mlx5_ib_event,
d9aaed83
AK		 4159#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4160 .pfault = mlx5_ib_pfault,
4161#endif
64613d94 4162 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 4163};
4164
4165static int __init mlx5_ib_init(void)
4166{
6aec21f6
HE		 4167 int err;
4168
81713d37 4169 mlx5_ib_odp_init();
9603b61d 4170
6aec21f6 4171 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 4172
6aec21f6 4173 return err;
e126ba97
EC		 4174}
4175
4176static void __exit mlx5_ib_cleanup(void)
4177{
9603b61d 4178 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 4179}
4180
4181module_init(mlx5_ib_init);
4182module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)