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{net, IB}/mlx5: Change set_roce_gid to take a port number
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
72c7fe90 53#include <linux/mlx5/fs.h>
7c2344c3 54#include <linux/list.h>
e126ba97
EC		 55#include <rdma/ib_smi.h>
56#include <rdma/ib_umem.h>
038d2ef8
MG		 57#include <linux/in.h>
58#include <linux/etherdevice.h>
e126ba97 59#include "mlx5_ib.h"
e1f24a79 60#include "cmd.h"
e126ba97
EC		 61
62#define DRIVER_NAME "mlx5_ib"
b359911d 63#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 64
65MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67MODULE_LICENSE("Dual BSD/GPL");
e126ba97 68
e126ba97
EC		 69static char mlx5_version[] =
70 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 71 DRIVER_VERSION "\n";
e126ba97 72
d69a24e0
DJ		 73struct mlx5_ib_event_work {
74 struct work_struct work;
75 struct mlx5_core_dev *dev;
76 void *context;
77 enum mlx5_dev_event event;
78 unsigned long param;
79};
80
da7525d2
EBE		 81enum {
82 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
83};
84
d69a24e0 85static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 86static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
87static LIST_HEAD(mlx5_ib_dev_list);
88/*
89 * This mutex should be held when accessing either of the above lists
90 */
91static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
92
93struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
94{
95 struct mlx5_ib_dev *dev;
96
97 mutex_lock(&mlx5_ib_multiport_mutex);
98 dev = mpi->ibdev;
99 mutex_unlock(&mlx5_ib_multiport_mutex);
100 return dev;
101}
102
1b5daf11 103static enum rdma_link_layer
ebd61f68 104mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 105{
ebd61f68 106 switch (port_type_cap) {
1b5daf11
MD		 107 case MLX5_CAP_PORT_TYPE_IB:
108 return IB_LINK_LAYER_INFINIBAND;
109 case MLX5_CAP_PORT_TYPE_ETH:
110 return IB_LINK_LAYER_ETHERNET;
111 default:
112 return IB_LINK_LAYER_UNSPECIFIED;
113 }
114}
115
ebd61f68
AS		 116static enum rdma_link_layer
117mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
118{
119 struct mlx5_ib_dev *dev = to_mdev(device);
120 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
121
122 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
123}
124
fd65f1b8
MS		 125static int get_port_state(struct ib_device *ibdev,
126 u8 port_num,
127 enum ib_port_state *state)
128{
129 struct ib_port_attr attr;
130 int ret;
131
132 memset(&attr, 0, sizeof(attr));
133 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
134 if (!ret)
135 *state = attr.state;
136 return ret;
137}
138
fc24fc5e
AS		 139static int mlx5_netdev_event(struct notifier_block *this,
140 unsigned long event, void *ptr)
141{
7fd8aefb 142 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 143 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 144 u8 port_num = roce->native_port_num;
145 struct mlx5_core_dev *mdev;
146 struct mlx5_ib_dev *ibdev;
147
148 ibdev = roce->dev;
32f69e4b
DJ		 149 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
150 if (!mdev)
151 return NOTIFY_DONE;
fc24fc5e 152
5ec8c83e
AH		 153 switch (event) {
154 case NETDEV_REGISTER:
155 case NETDEV_UNREGISTER:
7fd8aefb
DJ		 156 write_lock(&roce->netdev_lock);
157
158 if (ndev->dev.parent == &mdev->pdev->dev)
159 roce->netdev = (event == NETDEV_UNREGISTER) ?
160 NULL : ndev;
161 write_unlock(&roce->netdev_lock);
5ec8c83e 162 break;
fc24fc5e 163
fd65f1b8 164 case NETDEV_CHANGE:
5ec8c83e 165 case NETDEV_UP:
88621dfe 166 case NETDEV_DOWN: {
7fd8aefb 167 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 168 struct net_device *upper = NULL;
169
170 if (lag_ndev) {
171 upper = netdev_master_upper_dev_get(lag_ndev);
172 dev_put(lag_ndev);
173 }
174
7fd8aefb 175 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 176 && ibdev->ib_active) {
626bc02d 177 struct ib_event ibev = { };
fd65f1b8 178 enum ib_port_state port_state;
5ec8c83e 179
7fd8aefb
DJ		 180 if (get_port_state(&ibdev->ib_dev, port_num,
181 &port_state))
182 goto done;
fd65f1b8 183
7fd8aefb
DJ		 184 if (roce->last_port_state == port_state)
185 goto done;
fd65f1b8 186
7fd8aefb 187 roce->last_port_state = port_state;
5ec8c83e 188 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 189 if (port_state == IB_PORT_DOWN)
190 ibev.event = IB_EVENT_PORT_ERR;
191 else if (port_state == IB_PORT_ACTIVE)
192 ibev.event = IB_EVENT_PORT_ACTIVE;
193 else
7fd8aefb 194 goto done;
fd65f1b8 195
7fd8aefb 196 ibev.element.port_num = port_num;
5ec8c83e
AH		 197 ib_dispatch_event(&ibev);
198 }
199 break;
88621dfe 200 }
fc24fc5e 201
5ec8c83e
AH		 202 default:
203 break;
204 }
7fd8aefb 205done:
32f69e4b 206 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 207 return NOTIFY_DONE;
208}
209
210static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
211 u8 port_num)
212{
213 struct mlx5_ib_dev *ibdev = to_mdev(device);
214 struct net_device *ndev;
32f69e4b
DJ		 215 struct mlx5_core_dev *mdev;
216
217 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
218 if (!mdev)
219 return NULL;
fc24fc5e 220
32f69e4b 221 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 222 if (ndev)
32f69e4b 223 goto out;
88621dfe 224
fc24fc5e
AS		 225 /* Ensure ndev does not disappear before we invoke dev_hold()
226 */
7fd8aefb
DJ		 227 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
228 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 229 if (ndev)
230 dev_hold(ndev);
7fd8aefb 231 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 232
32f69e4b
DJ		 233out:
234 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 235 return ndev;
236}
237
32f69e4b
DJ		 238struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
239 u8 ib_port_num,
240 u8 *native_port_num)
241{
242 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
243 ib_port_num);
244 struct mlx5_core_dev *mdev = NULL;
245 struct mlx5_ib_multiport_info *mpi;
246 struct mlx5_ib_port *port;
247
248 if (native_port_num)
249 *native_port_num = 1;
250
251 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
252 return ibdev->mdev;
253
254 port = &ibdev->port[ib_port_num - 1];
255 if (!port)
256 return NULL;
257
258 spin_lock(&port->mp.mpi_lock);
259 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
260 if (mpi && !mpi->unaffiliate) {
261 mdev = mpi->mdev;
262 /* If it's the master no need to refcount, it'll exist
263 * as long as the ib_dev exists.
264 */
265 if (!mpi->is_master)
266 mpi->mdev_refcnt++;
267 }
268 spin_unlock(&port->mp.mpi_lock);
269
270 return mdev;
271}
272
273void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
274{
275 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
276 port_num);
277 struct mlx5_ib_multiport_info *mpi;
278 struct mlx5_ib_port *port;
279
280 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
281 return;
282
283 port = &ibdev->port[port_num - 1];
284
285 spin_lock(&port->mp.mpi_lock);
286 mpi = ibdev->port[port_num - 1].mp.mpi;
287 if (mpi->is_master)
288 goto out;
289
290 mpi->mdev_refcnt--;
291 if (mpi->unaffiliate)
292 complete(&mpi->unref_comp);
293out:
294 spin_unlock(&port->mp.mpi_lock);
295}
296
f1b65df5
NO		 297static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
298 u8 *active_width)
299{
300 switch (eth_proto_oper) {
301 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
302 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
303 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
304 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
305 *active_width = IB_WIDTH_1X;
306 *active_speed = IB_SPEED_SDR;
307 break;
308 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
309 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
310 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
311 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
312 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
313 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
314 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
315 *active_width = IB_WIDTH_1X;
316 *active_speed = IB_SPEED_QDR;
317 break;
318 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
319 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
320 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
321 *active_width = IB_WIDTH_1X;
322 *active_speed = IB_SPEED_EDR;
323 break;
324 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
325 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
326 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
327 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
328 *active_width = IB_WIDTH_4X;
329 *active_speed = IB_SPEED_QDR;
330 break;
331 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
332 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
333 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_HDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
338 *active_width = IB_WIDTH_4X;
339 *active_speed = IB_SPEED_FDR;
340 break;
341 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
342 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
343 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
344 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
345 *active_width = IB_WIDTH_4X;
346 *active_speed = IB_SPEED_EDR;
347 break;
348 default:
349 return -EINVAL;
350 }
351
352 return 0;
353}
354
095b0927
IT		 355static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
356 struct ib_port_attr *props)
3f89a643
AS		 357{
358 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 359 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 360 struct net_device *ndev, *upper;
3f89a643 361 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 362 bool put_mdev = true;
c876a1b7 363 u16 qkey_viol_cntr;
f1b65df5 364 u32 eth_prot_oper;
b3cbd6f0 365 u8 mdev_port_num;
095b0927 366 int err;
3f89a643 367
b3cbd6f0
DJ		 368 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
369 if (!mdev) {
370 /* This means the port isn't affiliated yet. Get the
371 * info for the master port instead.
372 */
373 put_mdev = false;
374 mdev = dev->mdev;
375 mdev_port_num = 1;
376 port_num = 1;
377 }
378
f1b65df5
NO		 379 /* Possible bad flows are checked before filling out props so in case
380 * of an error it will still be zeroed out.
50f22fd8 381 */
b3cbd6f0
DJ		 382 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
383 mdev_port_num);
095b0927 384 if (err)
b3cbd6f0 385 goto out;
f1b65df5
NO		 386
387 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
388 &props->active_width);
3f89a643
AS		 389
390 props->port_cap_flags |= IB_PORT_CM_SUP;
391 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
392
393 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
394 roce_address_table_size);
395 props->max_mtu = IB_MTU_4096;
396 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
397 props->pkey_tbl_len = 1;
398 props->state = IB_PORT_DOWN;
399 props->phys_state = 3;
400
b3cbd6f0 401 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 402 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 403
b3cbd6f0
DJ		 404 /* If this is a stub query for an unaffiliated port stop here */
405 if (!put_mdev)
406 goto out;
407
3f89a643
AS		 408 ndev = mlx5_ib_get_netdev(device, port_num);
409 if (!ndev)
b3cbd6f0 410 goto out;
3f89a643 411
88621dfe
AH		 412 if (mlx5_lag_is_active(dev->mdev)) {
413 rcu_read_lock();
414 upper = netdev_master_upper_dev_get_rcu(ndev);
415 if (upper) {
416 dev_put(ndev);
417 ndev = upper;
418 dev_hold(ndev);
419 }
420 rcu_read_unlock();
421 }
422
3f89a643
AS		 423 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
424 props->state = IB_PORT_ACTIVE;
425 props->phys_state = 5;
426 }
427
428 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
429
430 dev_put(ndev);
431
432 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 433out:
434 if (put_mdev)
435 mlx5_ib_put_native_port_mdev(dev, port_num);
436 return err;
3f89a643
AS		 437}
438
095b0927
IT		 439static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
440 unsigned int index, const union ib_gid *gid,
441 const struct ib_gid_attr *attr)
3cca2606 442{
095b0927
IT		 443 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
444 u8 roce_version = 0;
445 u8 roce_l3_type = 0;
446 bool vlan = false;
447 u8 mac[ETH_ALEN];
448 u16 vlan_id = 0;
449
450 if (gid) {
451 gid_type = attr->gid_type;
452 ether_addr_copy(mac, attr->ndev->dev_addr);
453
454 if (is_vlan_dev(attr->ndev)) {
455 vlan = true;
456 vlan_id = vlan_dev_vlan_id(attr->ndev);
457 }
3cca2606
AS		 458 }
459
095b0927 460 switch (gid_type) {
3cca2606 461 case IB_GID_TYPE_IB:
095b0927 462 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 463 break;
464 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 465 roce_version = MLX5_ROCE_VERSION_2;
466 if (ipv6_addr_v4mapped((void *)gid))
467 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
468 else
469 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 470 break;
471
472 default:
095b0927 473 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 474 }
475
095b0927
IT		 476 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
477 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 478 vlan_id, port_num);
3cca2606
AS		 479}
480
481static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
482 unsigned int index, const union ib_gid *gid,
483 const struct ib_gid_attr *attr,
484 __always_unused void **context)
485{
095b0927 486 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 487}
488
489static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
490 unsigned int index, __always_unused void **context)
491{
095b0927 492 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 493}
494
2811ba51
AS		 495__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
496 int index)
497{
498 struct ib_gid_attr attr;
499 union ib_gid gid;
500
501 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
502 return 0;
503
504 if (!attr.ndev)
505 return 0;
506
507 dev_put(attr.ndev);
508
509 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
510 return 0;
511
512 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
513}
514
ed88451e
MD		 515int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
516 int index, enum ib_gid_type *gid_type)
517{
518 struct ib_gid_attr attr;
519 union ib_gid gid;
520 int ret;
521
522 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
523 if (ret)
524 return ret;
525
526 if (!attr.ndev)
527 return -ENODEV;
528
529 dev_put(attr.ndev);
530
531 *gid_type = attr.gid_type;
532
533 return 0;
534}
535
1b5daf11
MD		 536static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
537{
7fae6655
NO		 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
540 return 0;
1b5daf11
MD		 541}
542
543enum {
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
547};
548
549static int mlx5_get_vport_access_method(struct ib_device *ibdev)
550{
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
553
ebd61f68 554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
557
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
559}
560
da7525d2 561static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 562 u8 atomic_size_qp,
da7525d2
EBE		 563 struct ib_device_attr *props)
564{
565 u8 tmp;
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 567 u8 atomic_req_8B_endianness_mode =
bd10838a 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 569
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
572 */
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
578 } else {
579 props->atomic_cap = IB_ATOMIC_NONE;
580 }
581}
582
776a3906
MS		 583static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
585{
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
587
588 get_atomic_caps(dev, atomic_size_qp, props);
589}
590
591static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593{
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597}
598
599bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
600{
601 struct ib_device_attr props = {};
602
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
605}
1b5daf11
MD		 606static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
608{
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
611 u64 tmp;
612 int err;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
617 sys_image_guid);
618
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 621 break;
622
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
625 break;
1b5daf11
MD		 626
627 default:
628 return -EINVAL;
629 }
3f89a643
AS		 630
631 if (!err)
632 *sys_image_guid = cpu_to_be64(tmp);
633
634 return err;
635
1b5daf11
MD		 636}
637
638static int mlx5_query_max_pkeys(struct ib_device *ibdev,
639 u16 *max_pkeys)
640{
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
643
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
647
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
651 pkey_table_size));
652 return 0;
653
654 default:
655 return -EINVAL;
656 }
657}
658
659static int mlx5_query_vendor_id(struct ib_device *ibdev,
660 u32 *vendor_id)
661{
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
663
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
667
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
671
672 default:
673 return -EINVAL;
674 }
675}
676
677static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
678 __be64 *node_guid)
679{
680 u64 tmp;
681 int err;
682
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
686
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 689 break;
690
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
693 break;
1b5daf11
MD		 694
695 default:
696 return -EINVAL;
697 }
3f89a643
AS		 698
699 if (!err)
700 *node_guid = cpu_to_be64(tmp);
701
702 return err;
1b5daf11
MD		 703}
704
705struct mlx5_reg_node_desc {
bd99fdea 706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 707};
708
709static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
710{
711 struct mlx5_reg_node_desc in;
712
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
715
716 memset(&in, 0, sizeof(in));
717
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
721}
722
e126ba97 723static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
e126ba97
EC		 726{
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 728 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 729 int err = -ENOMEM;
288c01b7 730 int max_sq_desc;
e126ba97
EC		 731 int max_rq_sg;
732 int max_sq_sg;
e0238a6a 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 734 struct mlx5_ib_query_device_resp resp = {};
735 size_t resp_len;
736 u64 max_tso;
e126ba97 737
402ca536
BW		 738 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
739 if (uhw->outlen && uhw->outlen < resp_len)
740 return -EINVAL;
741 else
742 resp.response_length = resp_len;
743
744 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 745 return -EINVAL;
746
1b5daf11
MD		 747 memset(props, 0, sizeof(*props));
748 err = mlx5_query_system_image_guid(ibdev,
749 &props->sys_image_guid);
750 if (err)
751 return err;
e126ba97 752
1b5daf11 753 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 754 if (err)
1b5daf11 755 return err;
e126ba97 756
1b5daf11
MD		 757 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
758 if (err)
759 return err;
e126ba97 760
9603b61d
JM		 761 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
762 (fw_rev_min(dev->mdev) << 16) |
763 fw_rev_sub(dev->mdev);
e126ba97
EC		 764 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
765 IB_DEVICE_PORT_ACTIVE_EVENT |
766 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 767 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 768
769 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 770 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 771 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 772 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 773 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 774 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 775 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 776 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 777 if (MLX5_CAP_GEN(mdev, imaicl)) {
778 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
779 IB_DEVICE_MEM_WINDOW_TYPE_2B;
780 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 781 /* We support 'Gappy' memory registration too */
782 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 783 }
e126ba97 784 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 785 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 786 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
787 /* At this stage no support for signature handover */
788 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
789 IB_PROT_T10DIF_TYPE_2 |
790 IB_PROT_T10DIF_TYPE_3;
791 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
792 IB_GUARD_T10DIF_CSUM;
793 }
938fe83c 794 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 795 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 796
402ca536 797 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 798 if (MLX5_CAP_ETH(mdev, csum_cap)) {
799 /* Legacy bit to support old userspace libraries */
88115fe7 800 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 801 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
802 }
803
804 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
805 props->raw_packet_caps |=
806 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 807
402ca536
BW		 808 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
809 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
810 if (max_tso) {
811 resp.tso_caps.max_tso = 1 << max_tso;
812 resp.tso_caps.supported_qpts |=
813 1 << IB_QPT_RAW_PACKET;
814 resp.response_length += sizeof(resp.tso_caps);
815 }
816 }
31f69a82
YH		 817
818 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
819 resp.rss_caps.rx_hash_function =
820 MLX5_RX_HASH_FUNC_TOEPLITZ;
821 resp.rss_caps.rx_hash_fields_mask =
822 MLX5_RX_HASH_SRC_IPV4 |
823 MLX5_RX_HASH_DST_IPV4 |
824 MLX5_RX_HASH_SRC_IPV6 |
825 MLX5_RX_HASH_DST_IPV6 |
826 MLX5_RX_HASH_SRC_PORT_TCP |
827 MLX5_RX_HASH_DST_PORT_TCP |
828 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 829 MLX5_RX_HASH_DST_PORT_UDP |
830 MLX5_RX_HASH_INNER;
31f69a82
YH		 831 resp.response_length += sizeof(resp.rss_caps);
832 }
833 } else {
834 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
835 resp.response_length += sizeof(resp.tso_caps);
836 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
837 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 838 }
839
f0313965
ES		 840 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
841 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
842 props->device_cap_flags |= IB_DEVICE_UD_TSO;
843 }
844
03404e8a
MG		 845 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
846 MLX5_CAP_GEN(dev->mdev, general_notification_event))
847 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
848
1d54f890
YH		 849 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
850 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
851 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
852
cff5a0f3 853 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 854 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
855 /* Legacy bit to support old userspace libraries */
cff5a0f3 856 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 857 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
858 }
cff5a0f3 859
da6d6ba3
MG		 860 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
861 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
862
b1383aa6
NO		 863 if (MLX5_CAP_GEN(mdev, end_pad))
864 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
865
1b5daf11
MD		 866 props->vendor_part_id = mdev->pdev->device;
867 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 868
869 props->max_mr_size = ~0ull;
e0238a6a 870 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 871 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
872 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
873 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
874 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 875 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
876 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
877 sizeof(struct mlx5_wqe_raddr_seg)) /
878 sizeof(struct mlx5_wqe_data_seg);
e126ba97 879 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 880 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 881 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 882 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 883 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
884 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
885 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
886 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
887 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
888 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
889 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 890 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 891 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 892 props->max_fast_reg_page_list_len =
893 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 894 get_atomic_caps_qp(dev, props);
81bea28f 895 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 896 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
897 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 898 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
899 props->max_mcast_grp;
900 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 901 props->max_ah = INT_MAX;
7c60bcbb
MB		 902 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
903 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 904
8cdd312c 905#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 906 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 907 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
908 props->odp_caps = dev->odp_caps;
909#endif
910
051f2630
LR		 911 if (MLX5_CAP_GEN(mdev, cd))
912 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
913
eff901d3
EC		 914 if (!mlx5_core_is_pf(mdev))
915 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
916
31f69a82
YH		 917 if (mlx5_ib_port_link_layer(ibdev, 1) ==
918 IB_LINK_LAYER_ETHERNET) {
919 props->rss_caps.max_rwq_indirection_tables =
920 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
921 props->rss_caps.max_rwq_indirection_table_size =
922 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
923 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
924 props->max_wq_type_rq =
925 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
926 }
927
eb761894 928 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 929 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
930 props->tm_caps.max_num_tags =
eb761894 931 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 932 props->tm_caps.flags = IB_TM_CAP_RC;
933 props->tm_caps.max_ops =
eb761894 934 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 935 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 936 }
937
87ab3f52
YC		 938 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
939 props->cq_caps.max_cq_moderation_count =
940 MLX5_MAX_CQ_COUNT;
941 props->cq_caps.max_cq_moderation_period =
942 MLX5_MAX_CQ_PERIOD;
943 }
944
7e43a2a5
BW		 945 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
946 resp.cqe_comp_caps.max_num =
947 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
948 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
949 resp.cqe_comp_caps.supported_format =
950 MLX5_IB_CQE_RES_FORMAT_HASH |
951 MLX5_IB_CQE_RES_FORMAT_CSUM;
952 resp.response_length += sizeof(resp.cqe_comp_caps);
953 }
954
d949167d
BW		 955 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
956 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
957 MLX5_CAP_GEN(mdev, qos)) {
958 resp.packet_pacing_caps.qp_rate_limit_max =
959 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
960 resp.packet_pacing_caps.qp_rate_limit_min =
961 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
962 resp.packet_pacing_caps.supported_qpts |=
963 1 << IB_QPT_RAW_PACKET;
964 }
965 resp.response_length += sizeof(resp.packet_pacing_caps);
966 }
967
9f885201
LR		 968 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
969 uhw->outlen)) {
795b609c
BW		 970 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
971 resp.mlx5_ib_support_multi_pkt_send_wqes =
972 MLX5_IB_ALLOW_MPW;
050da902
BW		 973
974 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
975 resp.mlx5_ib_support_multi_pkt_send_wqes |=
976 MLX5_IB_SUPPORT_EMPW;
977
9f885201
LR		 978 resp.response_length +=
979 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
980 }
981
de57f2ad
GL		 982 if (field_avail(typeof(resp), flags, uhw->outlen)) {
983 resp.response_length += sizeof(resp.flags);
7a0c8f42 984
de57f2ad
GL		 985 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
986 resp.flags |=
987 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 988
989 if (MLX5_CAP_GEN(mdev, cqe_128_always))
990 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 991 }
9f885201 992
96dc3fc5
NO		 993 if (field_avail(typeof(resp), sw_parsing_caps,
994 uhw->outlen)) {
995 resp.response_length += sizeof(resp.sw_parsing_caps);
996 if (MLX5_CAP_ETH(mdev, swp)) {
997 resp.sw_parsing_caps.sw_parsing_offloads |=
998 MLX5_IB_SW_PARSING;
999
1000 if (MLX5_CAP_ETH(mdev, swp_csum))
1001 resp.sw_parsing_caps.sw_parsing_offloads |=
1002 MLX5_IB_SW_PARSING_CSUM;
1003
1004 if (MLX5_CAP_ETH(mdev, swp_lso))
1005 resp.sw_parsing_caps.sw_parsing_offloads |=
1006 MLX5_IB_SW_PARSING_LSO;
1007
1008 if (resp.sw_parsing_caps.sw_parsing_offloads)
1009 resp.sw_parsing_caps.supported_qpts =
1010 BIT(IB_QPT_RAW_PACKET);
1011 }
1012 }
1013
b4f34597
NO		 1014 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) {
1015 resp.response_length += sizeof(resp.striding_rq_caps);
1016 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1017 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1018 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1019 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1020 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1021 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1022 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1023 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1024 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1025 resp.striding_rq_caps.supported_qpts =
1026 BIT(IB_QPT_RAW_PACKET);
1027 }
1028 }
1029
f95ef6cb
MG		 1030 if (field_avail(typeof(resp), tunnel_offloads_caps,
1031 uhw->outlen)) {
1032 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1033 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1034 resp.tunnel_offloads_caps |=
1035 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1036 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1037 resp.tunnel_offloads_caps |=
1038 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1039 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1040 resp.tunnel_offloads_caps |=
1041 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1042 }
1043
402ca536
BW		 1044 if (uhw->outlen) {
1045 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1046
1047 if (err)
1048 return err;
1049 }
1050
1b5daf11 1051 return 0;
e126ba97
EC		 1052}
1053
1b5daf11
MD		 1054enum mlx5_ib_width {
1055 MLX5_IB_WIDTH_1X = 1 << 0,
1056 MLX5_IB_WIDTH_2X = 1 << 1,
1057 MLX5_IB_WIDTH_4X = 1 << 2,
1058 MLX5_IB_WIDTH_8X = 1 << 3,
1059 MLX5_IB_WIDTH_12X = 1 << 4
1060};
1061
1062static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1063 u8 *ib_width)
e126ba97
EC		 1064{
1065 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1066 int err = 0;
1067
1068 if (active_width & MLX5_IB_WIDTH_1X) {
1069 *ib_width = IB_WIDTH_1X;
1070 } else if (active_width & MLX5_IB_WIDTH_2X) {
1071 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1072 (int)active_width);
1073 err = -EINVAL;
1074 } else if (active_width & MLX5_IB_WIDTH_4X) {
1075 *ib_width = IB_WIDTH_4X;
1076 } else if (active_width & MLX5_IB_WIDTH_8X) {
1077 *ib_width = IB_WIDTH_8X;
1078 } else if (active_width & MLX5_IB_WIDTH_12X) {
1079 *ib_width = IB_WIDTH_12X;
1080 } else {
1081 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1082 (int)active_width);
1083 err = -EINVAL;
e126ba97
EC		 1084 }
1085
1b5daf11
MD		 1086 return err;
1087}
e126ba97 1088
1b5daf11
MD		 1089static int mlx5_mtu_to_ib_mtu(int mtu)
1090{
1091 switch (mtu) {
1092 case 256: return 1;
1093 case 512: return 2;
1094 case 1024: return 3;
1095 case 2048: return 4;
1096 case 4096: return 5;
1097 default:
1098 pr_warn("invalid mtu\n");
1099 return -1;
e126ba97 1100 }
1b5daf11 1101}
e126ba97 1102
1b5daf11
MD		 1103enum ib_max_vl_num {
1104 __IB_MAX_VL_0 = 1,
1105 __IB_MAX_VL_0_1 = 2,
1106 __IB_MAX_VL_0_3 = 3,
1107 __IB_MAX_VL_0_7 = 4,
1108 __IB_MAX_VL_0_14 = 5,
1109};
e126ba97 1110
1b5daf11
MD		 1111enum mlx5_vl_hw_cap {
1112 MLX5_VL_HW_0 = 1,
1113 MLX5_VL_HW_0_1 = 2,
1114 MLX5_VL_HW_0_2 = 3,
1115 MLX5_VL_HW_0_3 = 4,
1116 MLX5_VL_HW_0_4 = 5,
1117 MLX5_VL_HW_0_5 = 6,
1118 MLX5_VL_HW_0_6 = 7,
1119 MLX5_VL_HW_0_7 = 8,
1120 MLX5_VL_HW_0_14 = 15
1121};
e126ba97 1122
1b5daf11
MD		 1123static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1124 u8 *max_vl_num)
1125{
1126 switch (vl_hw_cap) {
1127 case MLX5_VL_HW_0:
1128 *max_vl_num = __IB_MAX_VL_0;
1129 break;
1130 case MLX5_VL_HW_0_1:
1131 *max_vl_num = __IB_MAX_VL_0_1;
1132 break;
1133 case MLX5_VL_HW_0_3:
1134 *max_vl_num = __IB_MAX_VL_0_3;
1135 break;
1136 case MLX5_VL_HW_0_7:
1137 *max_vl_num = __IB_MAX_VL_0_7;
1138 break;
1139 case MLX5_VL_HW_0_14:
1140 *max_vl_num = __IB_MAX_VL_0_14;
1141 break;
e126ba97 1142
1b5daf11
MD		 1143 default:
1144 return -EINVAL;
e126ba97 1145 }
e126ba97 1146
1b5daf11 1147 return 0;
e126ba97
EC		 1148}
1149
1b5daf11
MD		 1150static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1151 struct ib_port_attr *props)
e126ba97 1152{
1b5daf11
MD		 1153 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1154 struct mlx5_core_dev *mdev = dev->mdev;
1155 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1156 u16 max_mtu;
1157 u16 oper_mtu;
1b5daf11
MD		 1158 int err;
1159 u8 ib_link_width_oper;
1160 u8 vl_hw_cap;
e126ba97 1161
1b5daf11
MD		 1162 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1163 if (!rep) {
1164 err = -ENOMEM;
e126ba97 1165 goto out;
e126ba97 1166 }
e126ba97 1167
c4550c63 1168 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1169
1b5daf11 1170 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1171 if (err)
1172 goto out;
1173
1b5daf11
MD		 1174 props->lid = rep->lid;
1175 props->lmc = rep->lmc;
1176 props->sm_lid = rep->sm_lid;
1177 props->sm_sl = rep->sm_sl;
1178 props->state = rep->vport_state;
1179 props->phys_state = rep->port_physical_state;
1180 props->port_cap_flags = rep->cap_mask1;
1181 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1182 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1183 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1184 props->bad_pkey_cntr = rep->pkey_violation_counter;
1185 props->qkey_viol_cntr = rep->qkey_violation_counter;
1186 props->subnet_timeout = rep->subnet_timeout;
1187 props->init_type_reply = rep->init_type_reply;
eff901d3 1188 props->grh_required = rep->grh_required;
e126ba97 1189
1b5daf11
MD		 1190 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1191 if (err)
e126ba97 1192 goto out;
e126ba97 1193
1b5daf11
MD		 1194 err = translate_active_width(ibdev, ib_link_width_oper,
1195 &props->active_width);
1196 if (err)
1197 goto out;
d5beb7f2 1198 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1199 if (err)
1200 goto out;
1201
facc9699 1202 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1203
1b5daf11 1204 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1205
facc9699 1206 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1207
1b5daf11 1208 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1209
1b5daf11
MD		 1210 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1211 if (err)
1212 goto out;
e126ba97 1213
1b5daf11
MD		 1214 err = translate_max_vl_num(ibdev, vl_hw_cap,
1215 &props->max_vl_num);
e126ba97 1216out:
1b5daf11 1217 kfree(rep);
e126ba97
EC		 1218 return err;
1219}
1220
1b5daf11
MD		 1221int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1222 struct ib_port_attr *props)
e126ba97 1223{
095b0927
IT		 1224 unsigned int count;
1225 int ret;
1226
1b5daf11
MD		 1227 switch (mlx5_get_vport_access_method(ibdev)) {
1228 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1229 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1230 break;
e126ba97 1231
1b5daf11 1232 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1233 ret = mlx5_query_hca_port(ibdev, port, props);
1234 break;
e126ba97 1235
3f89a643 1236 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1237 ret = mlx5_query_port_roce(ibdev, port, props);
1238 break;
3f89a643 1239
1b5daf11 1240 default:
095b0927
IT		 1241 ret = -EINVAL;
1242 }
1243
1244 if (!ret && props) {
b3cbd6f0
DJ		 1245 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1246 struct mlx5_core_dev *mdev;
1247 bool put_mdev = true;
1248
1249 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1250 if (!mdev) {
1251 /* If the port isn't affiliated yet query the master.
1252 * The master and slave will have the same values.
1253 */
1254 mdev = dev->mdev;
1255 port = 1;
1256 put_mdev = false;
1257 }
1258 count = mlx5_core_reserved_gids_count(mdev);
1259 if (put_mdev)
1260 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1261 props->gid_tbl_len -= count;
1b5daf11 1262 }
095b0927 1263 return ret;
1b5daf11 1264}
e126ba97 1265
1b5daf11
MD		 1266static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1267 union ib_gid *gid)
1268{
1269 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1270 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1271
1b5daf11
MD		 1272 switch (mlx5_get_vport_access_method(ibdev)) {
1273 case MLX5_VPORT_ACCESS_METHOD_MAD:
1274 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1275
1b5daf11
MD		 1276 case MLX5_VPORT_ACCESS_METHOD_HCA:
1277 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1278
1279 default:
1280 return -EINVAL;
1281 }
e126ba97 1282
e126ba97
EC		 1283}
1284
b3cbd6f0
DJ		 1285static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1286 u16 index, u16 *pkey)
1b5daf11
MD		 1287{
1288 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1289 struct mlx5_core_dev *mdev;
1290 bool put_mdev = true;
1291 u8 mdev_port_num;
1292 int err;
1b5daf11 1293
b3cbd6f0
DJ		 1294 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1295 if (!mdev) {
1296 /* The port isn't affiliated yet, get the PKey from the master
1297 * port. For RoCE the PKey tables will be the same.
1298 */
1299 put_mdev = false;
1300 mdev = dev->mdev;
1301 mdev_port_num = 1;
1302 }
1303
1304 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1305 index, pkey);
1306 if (put_mdev)
1307 mlx5_ib_put_native_port_mdev(dev, port);
1308
1309 return err;
1310}
1311
1312static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1313 u16 *pkey)
1314{
1b5daf11
MD		 1315 switch (mlx5_get_vport_access_method(ibdev)) {
1316 case MLX5_VPORT_ACCESS_METHOD_MAD:
1317 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1318
1319 case MLX5_VPORT_ACCESS_METHOD_HCA:
1320 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1321 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1322 default:
1323 return -EINVAL;
1324 }
1325}
e126ba97
EC		 1326
1327static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1328 struct ib_device_modify *props)
1329{
1330 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1331 struct mlx5_reg_node_desc in;
1332 struct mlx5_reg_node_desc out;
1333 int err;
1334
1335 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1336 return -EOPNOTSUPP;
1337
1338 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1339 return 0;
1340
1341 /*
1342 * If possible, pass node desc to FW, so it can generate
1343 * a 144 trap. If cmd fails, just ignore.
1344 */
bd99fdea 1345 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1346 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1347 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1348 if (err)
1349 return err;
1350
bd99fdea 1351 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1352
1353 return err;
1354}
1355
cdbe33d0
EC		 1356static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1357 u32 value)
1358{
1359 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1360 struct mlx5_core_dev *mdev;
1361 u8 mdev_port_num;
cdbe33d0
EC		 1362 int err;
1363
b3cbd6f0
DJ		 1364 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1365 if (!mdev)
1366 return -ENODEV;
1367
1368 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1369 if (err)
b3cbd6f0 1370 goto out;
cdbe33d0
EC		 1371
1372 if (~ctx.cap_mask1_perm & mask) {
1373 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1374 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1375 err = -EINVAL;
1376 goto out;
cdbe33d0
EC		 1377 }
1378
1379 ctx.cap_mask1 = value;
1380 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1381 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1382 0, &ctx);
1383
1384out:
1385 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1386
1387 return err;
1388}
1389
e126ba97
EC		 1390static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1391 struct ib_port_modify *props)
1392{
1393 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1394 struct ib_port_attr attr;
1395 u32 tmp;
1396 int err;
cdbe33d0
EC		 1397 u32 change_mask;
1398 u32 value;
1399 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1400 IB_LINK_LAYER_INFINIBAND);
1401
ec255879
MD		 1402 /* CM layer calls ib_modify_port() regardless of the link layer. For
1403 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1404 */
1405 if (!is_ib)
1406 return 0;
1407
cdbe33d0
EC		 1408 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1409 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1410 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1411 return set_port_caps_atomic(dev, port, change_mask, value);
1412 }
e126ba97
EC		 1413
1414 mutex_lock(&dev->cap_mask_mutex);
1415
c4550c63 1416 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1417 if (err)
1418 goto out;
1419
1420 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1421 ~props->clr_port_cap_mask;
1422
9603b61d 1423 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1424
1425out:
1426 mutex_unlock(&dev->cap_mask_mutex);
1427 return err;
1428}
1429
30aa60b3
EC		 1430static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1431{
1432 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1433 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1434}
1435
31a78a5a
YH		 1436static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1437{
1438 /* Large page with non 4k uar support might limit the dynamic size */
1439 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1440 return MLX5_MIN_DYN_BFREGS;
1441
1442 return MLX5_MAX_DYN_BFREGS;
1443}
1444
b037c29a
EC		 1445static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1446 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1447 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1448{
1449 int uars_per_sys_page;
1450 int bfregs_per_sys_page;
1451 int ref_bfregs = req->total_num_bfregs;
1452
1453 if (req->total_num_bfregs == 0)
1454 return -EINVAL;
1455
1456 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1457 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1458
1459 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1460 return -ENOMEM;
1461
1462 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1463 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1464 /* This holds the required static allocation asked by the user */
b037c29a 1465 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1466 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1467 return -EINVAL;
1468
31a78a5a
YH		 1469 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1470 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1471 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1472 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1473
1474 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1475 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1476 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1477 req->total_num_bfregs, bfregi->total_num_bfregs,
1478 bfregi->num_sys_pages);
b037c29a
EC		 1479
1480 return 0;
1481}
1482
1483static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1484{
1485 struct mlx5_bfreg_info *bfregi;
1486 int err;
1487 int i;
1488
1489 bfregi = &context->bfregi;
31a78a5a 1490 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1491 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1492 if (err)
1493 goto error;
1494
1495 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1496 }
4ed131d0
YH		 1497
1498 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1499 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1500
b037c29a
EC		 1501 return 0;
1502
1503error:
1504 for (--i; i >= 0; i--)
1505 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1506 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1507
1508 return err;
1509}
1510
1511static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1512{
1513 struct mlx5_bfreg_info *bfregi;
1514 int err;
1515 int i;
1516
1517 bfregi = &context->bfregi;
4ed131d0
YH		 1518 for (i = 0; i < bfregi->num_sys_pages; i++) {
1519 if (i < bfregi->num_static_sys_pages ||
1520 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1521 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1522 if (err) {
1523 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1524 return err;
1525 }
b037c29a
EC		 1526 }
1527 }
4ed131d0 1528
b037c29a
EC		 1529 return 0;
1530}
1531
c85023e1
HN		 1532static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1533{
1534 int err;
1535
1536 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1537 if (err)
1538 return err;
1539
1540 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1541 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1542 return err;
1543
1544 mutex_lock(&dev->lb_mutex);
1545 dev->user_td++;
1546
1547 if (dev->user_td == 2)
1548 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1549
1550 mutex_unlock(&dev->lb_mutex);
1551 return err;
1552}
1553
1554static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1555{
1556 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1557
1558 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1559 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1560 return;
1561
1562 mutex_lock(&dev->lb_mutex);
1563 dev->user_td--;
1564
1565 if (dev->user_td < 2)
1566 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1567
1568 mutex_unlock(&dev->lb_mutex);
1569}
1570
e126ba97
EC		 1571static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1572 struct ib_udata *udata)
1573{
1574 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1575 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1576 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1577 struct mlx5_ib_ucontext *context;
2f5ff264 1578 struct mlx5_bfreg_info *bfregi;
78c0f98c 1579 int ver;
e126ba97 1580 int err;
a168a41c
MD		 1581 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1582 max_cqe_version);
b037c29a 1583 bool lib_uar_4k;
e126ba97
EC		 1584
1585 if (!dev->ib_active)
1586 return ERR_PTR(-EAGAIN);
1587
e093111d 1588 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1589 ver = 0;
e093111d 1590 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1591 ver = 2;
1592 else
1593 return ERR_PTR(-EINVAL);
1594
e093111d 1595 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1596 if (err)
1597 return ERR_PTR(err);
1598
b368d7cb 1599 if (req.flags)
78c0f98c
EC		 1600 return ERR_PTR(-EINVAL);
1601
f72300c5 1602 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1603 return ERR_PTR(-EOPNOTSUPP);
1604
2f5ff264
EC		 1605 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1606 MLX5_NON_FP_BFREGS_PER_UAR);
1607 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1608 return ERR_PTR(-EINVAL);
1609
938fe83c 1610 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1611 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1612 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1613 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1614 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1615 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1616 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1617 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1618 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1619 resp.cqe_version = min_t(__u8,
1620 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1621 req.max_cqe_version);
30aa60b3
EC		 1622 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1623 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1624 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1625 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1626 resp.response_length = min(offsetof(typeof(resp), response_length) +
1627 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1628
1629 context = kzalloc(sizeof(*context), GFP_KERNEL);
1630 if (!context)
1631 return ERR_PTR(-ENOMEM);
1632
30aa60b3 1633 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1634 bfregi = &context->bfregi;
b037c29a
EC		 1635
1636 /* updates req->total_num_bfregs */
31a78a5a 1637 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1638 if (err)
e126ba97 1639 goto out_ctx;
e126ba97 1640
b037c29a
EC		 1641 mutex_init(&bfregi->lock);
1642 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1643 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1644 GFP_KERNEL);
b037c29a 1645 if (!bfregi->count) {
e126ba97 1646 err = -ENOMEM;
b037c29a 1647 goto out_ctx;
e126ba97
EC		 1648 }
1649
b037c29a
EC		 1650 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1651 sizeof(*bfregi->sys_pages),
1652 GFP_KERNEL);
1653 if (!bfregi->sys_pages) {
e126ba97 1654 err = -ENOMEM;
b037c29a 1655 goto out_count;
e126ba97
EC		 1656 }
1657
b037c29a
EC		 1658 err = allocate_uars(dev, context);
1659 if (err)
1660 goto out_sys_pages;
e126ba97 1661
b4cfe447
HE		 1662#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1663 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1664#endif
1665
7d0cc6ed
AK		 1666 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1667 if (!context->upd_xlt_page) {
1668 err = -ENOMEM;
1669 goto out_uars;
1670 }
1671 mutex_init(&context->upd_xlt_page_mutex);
1672
146d2f1a 1673 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1674 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1675 if (err)
7d0cc6ed 1676 goto out_page;
146d2f1a 1677 }
1678
7c2344c3 1679 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1680 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1681 INIT_LIST_HEAD(&context->db_page_list);
1682 mutex_init(&context->db_page_mutex);
1683
2f5ff264 1684 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1685 resp.num_ports = dev->num_ports;
b368d7cb 1686
f72300c5
HA		 1687 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1688 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1689
402ca536 1690 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1691 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1692 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1693 resp.response_length += sizeof(resp.cmds_supp_uhw);
1694 }
1695
78984898
OG		 1696 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1697 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1698 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1699 resp.eth_min_inline++;
1700 }
1701 resp.response_length += sizeof(resp.eth_min_inline);
1702 }
1703
bc5c6eed
NO		 1704 /*
1705 * We don't want to expose information from the PCI bar that is located
1706 * after 4096 bytes, so if the arch only supports larger pages, let's
1707 * pretend we don't support reading the HCA's core clock. This is also
1708 * forced by mmap function.
1709 */
de8d6e02
EC		 1710 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1711 if (PAGE_SIZE <= 4096) {
1712 resp.comp_mask |=
1713 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1714 resp.hca_core_clock_offset =
1715 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1716 }
f72300c5 1717 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1718 sizeof(resp.reserved2);
b368d7cb
MB		 1719 }
1720
30aa60b3
EC		 1721 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1722 resp.response_length += sizeof(resp.log_uar_size);
1723
1724 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1725 resp.response_length += sizeof(resp.num_uars_per_page);
1726
31a78a5a
YH		 1727 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1728 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1729 resp.response_length += sizeof(resp.num_dyn_bfregs);
1730 }
1731
b368d7cb 1732 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1733 if (err)
146d2f1a 1734 goto out_td;
e126ba97 1735
2f5ff264
EC		 1736 bfregi->ver = ver;
1737 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1738 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1739 context->lib_caps = req.lib_caps;
1740 print_lib_caps(dev, context->lib_caps);
f72300c5 1741
e126ba97
EC		 1742 return &context->ibucontext;
1743
146d2f1a 1744out_td:
1745 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1746 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1747
7d0cc6ed
AK		 1748out_page:
1749 free_page(context->upd_xlt_page);
1750
e126ba97 1751out_uars:
b037c29a 1752 deallocate_uars(dev, context);
e126ba97 1753
b037c29a
EC		 1754out_sys_pages:
1755 kfree(bfregi->sys_pages);
e126ba97 1756
b037c29a
EC		 1757out_count:
1758 kfree(bfregi->count);
e126ba97
EC		 1759
1760out_ctx:
1761 kfree(context);
b037c29a 1762
e126ba97
EC		 1763 return ERR_PTR(err);
1764}
1765
1766static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1767{
1768 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1769 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1770 struct mlx5_bfreg_info *bfregi;
e126ba97 1771
b037c29a 1772 bfregi = &context->bfregi;
146d2f1a 1773 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1774 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1775
7d0cc6ed 1776 free_page(context->upd_xlt_page);
b037c29a
EC		 1777 deallocate_uars(dev, context);
1778 kfree(bfregi->sys_pages);
2f5ff264 1779 kfree(bfregi->count);
e126ba97
EC		 1780 kfree(context);
1781
1782 return 0;
1783}
1784
b037c29a 1785static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1786 int uar_idx)
e126ba97 1787{
b037c29a
EC		 1788 int fw_uars_per_page;
1789
1790 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1791
4ed131d0 1792 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1793}
1794
1795static int get_command(unsigned long offset)
1796{
1797 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1798}
1799
1800static int get_arg(unsigned long offset)
1801{
1802 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1803}
1804
1805static int get_index(unsigned long offset)
1806{
1807 return get_arg(offset);
1808}
1809
4ed131d0
YH		 1810/* Index resides in an extra byte to enable larger values than 255 */
1811static int get_extended_index(unsigned long offset)
1812{
1813 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1814}
1815
7c2344c3
MG		 1816static void mlx5_ib_vma_open(struct vm_area_struct *area)
1817{
1818 /* vma_open is called when a new VMA is created on top of our VMA. This
1819 * is done through either mremap flow or split_vma (usually due to
1820 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1821 * as this VMA is strongly hardware related. Therefore we set the
1822 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1823 * calling us again and trying to do incorrect actions. We assume that
1824 * the original VMA size is exactly a single page, and therefore all
1825 * "splitting" operation will not happen to it.
1826 */
1827 area->vm_ops = NULL;
1828}
1829
1830static void mlx5_ib_vma_close(struct vm_area_struct *area)
1831{
1832 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1833
1834 /* It's guaranteed that all VMAs opened on a FD are closed before the
1835 * file itself is closed, therefore no sync is needed with the regular
1836 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1837 * However need a sync with accessing the vma as part of
1838 * mlx5_ib_disassociate_ucontext.
1839 * The close operation is usually called under mm->mmap_sem except when
1840 * process is exiting.
1841 * The exiting case is handled explicitly as part of
1842 * mlx5_ib_disassociate_ucontext.
1843 */
1844 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1845
1846 /* setting the vma context pointer to null in the mlx5_ib driver's
1847 * private data, to protect a race condition in
1848 * mlx5_ib_disassociate_ucontext().
1849 */
1850 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1851 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1852 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1853 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1854 kfree(mlx5_ib_vma_priv_data);
1855}
1856
1857static const struct vm_operations_struct mlx5_ib_vm_ops = {
1858 .open = mlx5_ib_vma_open,
1859 .close = mlx5_ib_vma_close
1860};
1861
1862static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1863 struct mlx5_ib_ucontext *ctx)
1864{
1865 struct mlx5_ib_vma_private_data *vma_prv;
1866 struct list_head *vma_head = &ctx->vma_private_list;
1867
1868 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1869 if (!vma_prv)
1870 return -ENOMEM;
1871
1872 vma_prv->vma = vma;
ad9a3668 1873 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1874 vma->vm_private_data = vma_prv;
1875 vma->vm_ops = &mlx5_ib_vm_ops;
1876
ad9a3668 1877 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1878 list_add(&vma_prv->list, vma_head);
ad9a3668 1879 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1880
1881 return 0;
1882}
1883
1884static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1885{
1886 int ret;
1887 struct vm_area_struct *vma;
1888 struct mlx5_ib_vma_private_data *vma_private, *n;
1889 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1890 struct task_struct *owning_process = NULL;
1891 struct mm_struct *owning_mm = NULL;
1892
1893 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1894 if (!owning_process)
1895 return;
1896
1897 owning_mm = get_task_mm(owning_process);
1898 if (!owning_mm) {
1899 pr_info("no mm, disassociate ucontext is pending task termination\n");
1900 while (1) {
1901 put_task_struct(owning_process);
1902 usleep_range(1000, 2000);
1903 owning_process = get_pid_task(ibcontext->tgid,
1904 PIDTYPE_PID);
1905 if (!owning_process ||
1906 owning_process->state == TASK_DEAD) {
1907 pr_info("disassociate ucontext done, task was terminated\n");
1908 /* in case task was dead need to release the
1909 * task struct.
1910 */
1911 if (owning_process)
1912 put_task_struct(owning_process);
1913 return;
1914 }
1915 }
1916 }
1917
1918 /* need to protect from a race on closing the vma as part of
1919 * mlx5_ib_vma_close.
1920 */
ecc7d83b 1921 down_write(&owning_mm->mmap_sem);
ad9a3668 1922 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1923 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1924 list) {
1925 vma = vma_private->vma;
1926 ret = zap_vma_ptes(vma, vma->vm_start,
1927 PAGE_SIZE);
1928 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1929 /* context going to be destroyed, should
1930 * not access ops any more.
1931 */
13776612 1932 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1933 vma->vm_ops = NULL;
1934 list_del(&vma_private->list);
1935 kfree(vma_private);
1936 }
ad9a3668 1937 mutex_unlock(&context->vma_private_list_mutex);
ecc7d83b 1938 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1939 mmput(owning_mm);
1940 put_task_struct(owning_process);
1941}
1942
37aa5c36
GL		 1943static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1944{
1945 switch (cmd) {
1946 case MLX5_IB_MMAP_WC_PAGE:
1947 return "WC";
1948 case MLX5_IB_MMAP_REGULAR_PAGE:
1949 return "best effort WC";
1950 case MLX5_IB_MMAP_NC_PAGE:
1951 return "NC";
1952 default:
1953 return NULL;
1954 }
1955}
1956
1957static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1958 struct vm_area_struct *vma,
1959 struct mlx5_ib_ucontext *context)
37aa5c36 1960{
2f5ff264 1961 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1962 int err;
1963 unsigned long idx;
1964 phys_addr_t pfn, pa;
1965 pgprot_t prot;
4ed131d0
YH		 1966 u32 bfreg_dyn_idx = 0;
1967 u32 uar_index;
1968 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
1969 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
1970 bfregi->num_static_sys_pages;
b037c29a
EC		 1971
1972 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1973 return -EINVAL;
1974
4ed131d0
YH		 1975 if (dyn_uar)
1976 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
1977 else
1978 idx = get_index(vma->vm_pgoff);
1979
1980 if (idx >= max_valid_idx) {
1981 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
1982 idx, max_valid_idx);
b037c29a
EC		 1983 return -EINVAL;
1984 }
37aa5c36
GL		 1985
1986 switch (cmd) {
1987 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 1988 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 1989/* Some architectures don't support WC memory */
1990#if defined(CONFIG_X86)
1991 if (!pat_enabled())
1992 return -EPERM;
1993#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1994 return -EPERM;
1995#endif
1996 /* fall through */
1997 case MLX5_IB_MMAP_REGULAR_PAGE:
1998 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1999 prot = pgprot_writecombine(vma->vm_page_prot);
2000 break;
2001 case MLX5_IB_MMAP_NC_PAGE:
2002 prot = pgprot_noncached(vma->vm_page_prot);
2003 break;
2004 default:
2005 return -EINVAL;
2006 }
2007
4ed131d0
YH		 2008 if (dyn_uar) {
2009 int uars_per_page;
2010
2011 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2012 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2013 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2014 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2015 bfreg_dyn_idx, bfregi->total_num_bfregs);
2016 return -EINVAL;
2017 }
2018
2019 mutex_lock(&bfregi->lock);
2020 /* Fail if uar already allocated, first bfreg index of each
2021 * page holds its count.
2022 */
2023 if (bfregi->count[bfreg_dyn_idx]) {
2024 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2025 mutex_unlock(&bfregi->lock);
2026 return -EINVAL;
2027 }
2028
2029 bfregi->count[bfreg_dyn_idx]++;
2030 mutex_unlock(&bfregi->lock);
2031
2032 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2033 if (err) {
2034 mlx5_ib_warn(dev, "UAR alloc failed\n");
2035 goto free_bfreg;
2036 }
2037 } else {
2038 uar_index = bfregi->sys_pages[idx];
2039 }
2040
2041 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2042 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2043
2044 vma->vm_page_prot = prot;
2045 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2046 PAGE_SIZE, vma->vm_page_prot);
2047 if (err) {
2048 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2049 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
4ed131d0
YH		 2050 err = -EAGAIN;
2051 goto err;
37aa5c36
GL		 2052 }
2053
2054 pa = pfn << PAGE_SHIFT;
2055 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2056 vma->vm_start, &pa);
2057
4ed131d0
YH		 2058 err = mlx5_ib_set_vma_data(vma, context);
2059 if (err)
2060 goto err;
2061
2062 if (dyn_uar)
2063 bfregi->sys_pages[idx] = uar_index;
2064 return 0;
2065
2066err:
2067 if (!dyn_uar)
2068 return err;
2069
2070 mlx5_cmd_free_uar(dev->mdev, idx);
2071
2072free_bfreg:
2073 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2074
2075 return err;
37aa5c36
GL		 2076}
2077
e126ba97
EC		 2078static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2079{
2080 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2081 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2082 unsigned long command;
e126ba97
EC		 2083 phys_addr_t pfn;
2084
2085 command = get_command(vma->vm_pgoff);
2086 switch (command) {
37aa5c36
GL		 2087 case MLX5_IB_MMAP_WC_PAGE:
2088 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2089 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2090 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2091 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2092
2093 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2094 return -ENOSYS;
2095
d69e3bcf 2096 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2097 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2098 return -EINVAL;
2099
6cbac1e4 2100 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2101 return -EPERM;
2102
2103 /* Don't expose to user-space information it shouldn't have */
2104 if (PAGE_SIZE > 4096)
2105 return -EOPNOTSUPP;
2106
2107 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2108 pfn = (dev->mdev->iseg_base +
2109 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2110 PAGE_SHIFT;
2111 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2112 PAGE_SIZE, vma->vm_page_prot))
2113 return -EAGAIN;
2114
2115 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2116 vma->vm_start,
2117 (unsigned long long)pfn << PAGE_SHIFT);
2118 break;
d69e3bcf 2119
e126ba97
EC		 2120 default:
2121 return -EINVAL;
2122 }
2123
2124 return 0;
2125}
2126
e126ba97
EC		 2127static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2128 struct ib_ucontext *context,
2129 struct ib_udata *udata)
2130{
2131 struct mlx5_ib_alloc_pd_resp resp;
2132 struct mlx5_ib_pd *pd;
2133 int err;
2134
2135 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2136 if (!pd)
2137 return ERR_PTR(-ENOMEM);
2138
9603b61d 2139 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2140 if (err) {
2141 kfree(pd);
2142 return ERR_PTR(err);
2143 }
2144
2145 if (context) {
2146 resp.pdn = pd->pdn;
2147 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2148 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2149 kfree(pd);
2150 return ERR_PTR(-EFAULT);
2151 }
e126ba97
EC		 2152 }
2153
2154 return &pd->ibpd;
2155}
2156
2157static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2158{
2159 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2160 struct mlx5_ib_pd *mpd = to_mpd(pd);
2161
9603b61d 2162 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2163 kfree(mpd);
2164
2165 return 0;
2166}
2167
466fa6d2
MG		 2168enum {
2169 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2170 MATCH_CRITERIA_ENABLE_MISC_BIT,
2171 MATCH_CRITERIA_ENABLE_INNER_BIT
2172};
2173
2174#define HEADER_IS_ZERO(match_criteria, headers) \
2175 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2176 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2177
466fa6d2 2178static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2179{
466fa6d2 2180 u8 match_criteria_enable;
038d2ef8 2181
466fa6d2
MG		 2182 match_criteria_enable =
2183 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2184 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2185 match_criteria_enable |=
2186 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2187 MATCH_CRITERIA_ENABLE_MISC_BIT;
2188 match_criteria_enable |=
2189 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2190 MATCH_CRITERIA_ENABLE_INNER_BIT;
2191
2192 return match_criteria_enable;
038d2ef8
MG		 2193}
2194
ca0d4753
MG		 2195static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2196{
2197 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2198 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2199}
2200
2d1e697e
MR		 2201static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2202 bool inner)
2203{
2204 if (inner) {
2205 MLX5_SET(fte_match_set_misc,
2206 misc_c, inner_ipv6_flow_label, mask);
2207 MLX5_SET(fte_match_set_misc,
2208 misc_v, inner_ipv6_flow_label, val);
2209 } else {
2210 MLX5_SET(fte_match_set_misc,
2211 misc_c, outer_ipv6_flow_label, mask);
2212 MLX5_SET(fte_match_set_misc,
2213 misc_v, outer_ipv6_flow_label, val);
2214 }
2215}
2216
ca0d4753
MG		 2217static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2218{
2219 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2220 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2221 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2222 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2223}
2224
c47ac6ae
MG		 2225#define LAST_ETH_FIELD vlan_tag
2226#define LAST_IB_FIELD sl
ca0d4753 2227#define LAST_IPV4_FIELD tos
466fa6d2 2228#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2229#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2230#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2231#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2232#define LAST_DROP_FIELD size
c47ac6ae
MG		 2233
2234/* Field is the last supported field */
2235#define FIELDS_NOT_SUPPORTED(filter, field)\
2236 memchr_inv((void *)&filter.field +\
2237 sizeof(filter.field), 0,\
2238 sizeof(filter) -\
2239 offsetof(typeof(filter), field) -\
2240 sizeof(filter.field))
2241
19cc7524
AL		 2242#define IPV4_VERSION 4
2243#define IPV6_VERSION 6
2244static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2245 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 2246 u32 *tag_id, bool *is_drop)
038d2ef8 2247{
466fa6d2
MG		 2248 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2249 misc_parameters);
2250 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2251 misc_parameters);
2d1e697e
MR		 2252 void *headers_c;
2253 void *headers_v;
19cc7524 2254 int match_ipv;
2d1e697e
MR		 2255
2256 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2257 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2258 inner_headers);
2259 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2260 inner_headers);
19cc7524
AL		 2261 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2262 ft_field_support.inner_ip_version);
2d1e697e
MR		 2263 } else {
2264 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2265 outer_headers);
2266 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2267 outer_headers);
19cc7524
AL		 2268 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2269 ft_field_support.outer_ip_version);
2d1e697e 2270 }
466fa6d2 2271
2d1e697e 2272 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2273 case IB_FLOW_SPEC_ETH:
c47ac6ae 2274 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2275 return -EOPNOTSUPP;
038d2ef8 2276
2d1e697e 2277 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2278 dmac_47_16),
2279 ib_spec->eth.mask.dst_mac);
2d1e697e 2280 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2281 dmac_47_16),
2282 ib_spec->eth.val.dst_mac);
2283
2d1e697e 2284 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2285 smac_47_16),
2286 ib_spec->eth.mask.src_mac);
2d1e697e 2287 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2288 smac_47_16),
2289 ib_spec->eth.val.src_mac);
2290
038d2ef8 2291 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2292 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2293 cvlan_tag, 1);
2d1e697e 2294 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2295 cvlan_tag, 1);
038d2ef8 2296
2d1e697e 2297 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2298 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2299 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2300 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2301
2d1e697e 2302 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2303 first_cfi,
2304 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2305 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2306 first_cfi,
2307 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2308
2d1e697e 2309 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2310 first_prio,
2311 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2312 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2313 first_prio,
2314 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2315 }
2d1e697e 2316 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2317 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2318 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2319 ethertype, ntohs(ib_spec->eth.val.ether_type));
2320 break;
2321 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2322 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2323 return -EOPNOTSUPP;
038d2ef8 2324
19cc7524
AL		 2325 if (match_ipv) {
2326 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2327 ip_version, 0xf);
2328 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2329 ip_version, IPV4_VERSION);
2330 } else {
2331 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2332 ethertype, 0xffff);
2333 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2334 ethertype, ETH_P_IP);
2335 }
038d2ef8 2336
2d1e697e 2337 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2338 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2339 &ib_spec->ipv4.mask.src_ip,
2340 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2341 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2342 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2343 &ib_spec->ipv4.val.src_ip,
2344 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2345 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2346 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2347 &ib_spec->ipv4.mask.dst_ip,
2348 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2349 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2350 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2351 &ib_spec->ipv4.val.dst_ip,
2352 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2353
2d1e697e 2354 set_tos(headers_c, headers_v,
ca0d4753
MG		 2355 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2356
2d1e697e 2357 set_proto(headers_c, headers_v,
ca0d4753 2358 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2359 break;
026bae0c 2360 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2361 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2362 return -EOPNOTSUPP;
026bae0c 2363
19cc7524
AL		 2364 if (match_ipv) {
2365 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2366 ip_version, 0xf);
2367 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2368 ip_version, IPV6_VERSION);
2369 } else {
2370 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2371 ethertype, 0xffff);
2372 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2373 ethertype, ETH_P_IPV6);
2374 }
026bae0c 2375
2d1e697e 2376 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2377 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2378 &ib_spec->ipv6.mask.src_ip,
2379 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2380 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2381 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2382 &ib_spec->ipv6.val.src_ip,
2383 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2384 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2385 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2386 &ib_spec->ipv6.mask.dst_ip,
2387 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2388 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2389 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2390 &ib_spec->ipv6.val.dst_ip,
2391 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2392
2d1e697e 2393 set_tos(headers_c, headers_v,
466fa6d2
MG		 2394 ib_spec->ipv6.mask.traffic_class,
2395 ib_spec->ipv6.val.traffic_class);
2396
2d1e697e 2397 set_proto(headers_c, headers_v,
466fa6d2
MG		 2398 ib_spec->ipv6.mask.next_hdr,
2399 ib_spec->ipv6.val.next_hdr);
2400
2d1e697e
MR		 2401 set_flow_label(misc_params_c, misc_params_v,
2402 ntohl(ib_spec->ipv6.mask.flow_label),
2403 ntohl(ib_spec->ipv6.val.flow_label),
2404 ib_spec->type & IB_FLOW_SPEC_INNER);
2405
026bae0c 2406 break;
038d2ef8 2407 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2408 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2409 LAST_TCP_UDP_FIELD))
1ffd3a26 2410 return -EOPNOTSUPP;
038d2ef8 2411
2d1e697e 2412 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2413 0xff);
2d1e697e 2414 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2415 IPPROTO_TCP);
2416
2d1e697e 2417 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2418 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2419 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2420 ntohs(ib_spec->tcp_udp.val.src_port));
2421
2d1e697e 2422 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2423 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2424 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2425 ntohs(ib_spec->tcp_udp.val.dst_port));
2426 break;
2427 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2428 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2429 LAST_TCP_UDP_FIELD))
1ffd3a26 2430 return -EOPNOTSUPP;
038d2ef8 2431
2d1e697e 2432 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2433 0xff);
2d1e697e 2434 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2435 IPPROTO_UDP);
2436
2d1e697e 2437 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2438 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2439 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2440 ntohs(ib_spec->tcp_udp.val.src_port));
2441
2d1e697e 2442 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2443 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2444 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2445 ntohs(ib_spec->tcp_udp.val.dst_port));
2446 break;
ffb30d8f
MR		 2447 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2448 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2449 LAST_TUNNEL_FIELD))
1ffd3a26 2450 return -EOPNOTSUPP;
ffb30d8f
MR		 2451
2452 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2453 ntohl(ib_spec->tunnel.mask.tunnel_id));
2454 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2455 ntohl(ib_spec->tunnel.val.tunnel_id));
2456 break;
2ac693f9
MR		 2457 case IB_FLOW_SPEC_ACTION_TAG:
2458 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2459 LAST_FLOW_TAG_FIELD))
2460 return -EOPNOTSUPP;
2461 if (ib_spec->flow_tag.tag_id >= BIT(24))
2462 return -EINVAL;
2463
2464 *tag_id = ib_spec->flow_tag.tag_id;
2465 break;
a22ed86c
SS		 2466 case IB_FLOW_SPEC_ACTION_DROP:
2467 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2468 LAST_DROP_FIELD))
2469 return -EOPNOTSUPP;
2470 *is_drop = true;
2471 break;
038d2ef8
MG		 2472 default:
2473 return -EINVAL;
2474 }
2475
2476 return 0;
2477}
2478
2479/* If a flow could catch both multicast and unicast packets,
2480 * it won't fall into the multicast flow steering table and this rule
2481 * could steal other multicast packets.
2482 */
a550ddfc 2483static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2484{
81e30880 2485 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2486
2487 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2488 ib_attr->num_of_specs < 1)
2489 return false;
2490
81e30880
YH		 2491 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2492 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2493 struct ib_flow_spec_ipv4 *ipv4_spec;
2494
2495 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2496 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2497 return true;
2498
038d2ef8 2499 return false;
81e30880
YH		 2500 }
2501
2502 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2503 struct ib_flow_spec_eth *eth_spec;
2504
2505 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2506 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2507 is_multicast_ether_addr(eth_spec->val.dst_mac);
2508 }
038d2ef8 2509
81e30880 2510 return false;
038d2ef8
MG		 2511}
2512
19cc7524
AL		 2513static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2514 const struct ib_flow_attr *flow_attr,
0f750966 2515 bool check_inner)
038d2ef8
MG		 2516{
2517 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2518 int match_ipv = check_inner ?
2519 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2520 ft_field_support.inner_ip_version) :
2521 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2522 ft_field_support.outer_ip_version);
0f750966
AL		 2523 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2524 bool ipv4_spec_valid, ipv6_spec_valid;
2525 unsigned int ip_spec_type = 0;
2526 bool has_ethertype = false;
038d2ef8 2527 unsigned int spec_index;
0f750966
AL		 2528 bool mask_valid = true;
2529 u16 eth_type = 0;
2530 bool type_valid;
038d2ef8
MG		 2531
2532 /* Validate that ethertype is correct */
2533 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2534 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2535 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2536 mask_valid = (ib_spec->eth.mask.ether_type ==
2537 htons(0xffff));
2538 has_ethertype = true;
2539 eth_type = ntohs(ib_spec->eth.val.ether_type);
2540 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2541 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2542 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2543 }
2544 ib_spec = (void *)ib_spec + ib_spec->size;
2545 }
0f750966
AL		 2546
2547 type_valid = (!has_ethertype) || (!ip_spec_type);
2548 if (!type_valid && mask_valid) {
2549 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2550 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2551 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2552 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2553
2554 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2555 (((eth_type == ETH_P_MPLS_UC) ||
2556 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2557 }
2558
2559 return type_valid;
2560}
2561
19cc7524
AL		 2562static bool is_valid_attr(struct mlx5_core_dev *mdev,
2563 const struct ib_flow_attr *flow_attr)
0f750966 2564{
19cc7524
AL		 2565 return is_valid_ethertype(mdev, flow_attr, false) &&
2566 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2567}
2568
2569static void put_flow_table(struct mlx5_ib_dev *dev,
2570 struct mlx5_ib_flow_prio *prio, bool ft_added)
2571{
2572 prio->refcount -= !!ft_added;
2573 if (!prio->refcount) {
2574 mlx5_destroy_flow_table(prio->flow_table);
2575 prio->flow_table = NULL;
2576 }
2577}
2578
2579static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2580{
2581 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2582 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2583 struct mlx5_ib_flow_handler,
2584 ibflow);
2585 struct mlx5_ib_flow_handler *iter, *tmp;
2586
2587 mutex_lock(&dev->flow_db.lock);
2588
2589 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2590 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2591 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2592 list_del(&iter->list);
2593 kfree(iter);
2594 }
2595
74491de9 2596 mlx5_del_flow_rules(handler->rule);
5497adc6 2597 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2598 mutex_unlock(&dev->flow_db.lock);
2599
2600 kfree(handler);
2601
2602 return 0;
2603}
2604
35d19011
MG		 2605static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2606{
2607 priority *= 2;
2608 if (!dont_trap)
2609 priority++;
2610 return priority;
2611}
2612
cc0e5d42
MG		 2613enum flow_table_type {
2614 MLX5_IB_FT_RX,
2615 MLX5_IB_FT_TX
2616};
2617
00b7c2ab
MG		 2618#define MLX5_FS_MAX_TYPES 6
2619#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2620static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2621 struct ib_flow_attr *flow_attr,
2622 enum flow_table_type ft_type)
038d2ef8 2623{
35d19011 2624 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2625 struct mlx5_flow_namespace *ns = NULL;
2626 struct mlx5_ib_flow_prio *prio;
2627 struct mlx5_flow_table *ft;
dac388ef 2628 int max_table_size;
038d2ef8
MG		 2629 int num_entries;
2630 int num_groups;
2631 int priority;
2632 int err = 0;
2633
dac388ef
MG		 2634 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2635 log_max_ft_size));
038d2ef8 2636 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2637 if (flow_is_multicast_only(flow_attr) &&
2638 !dont_trap)
038d2ef8
MG		 2639 priority = MLX5_IB_FLOW_MCAST_PRIO;
2640 else
35d19011
MG		 2641 priority = ib_prio_to_core_prio(flow_attr->priority,
2642 dont_trap);
038d2ef8
MG		 2643 ns = mlx5_get_flow_namespace(dev->mdev,
2644 MLX5_FLOW_NAMESPACE_BYPASS);
2645 num_entries = MLX5_FS_MAX_ENTRIES;
2646 num_groups = MLX5_FS_MAX_TYPES;
2647 prio = &dev->flow_db.prios[priority];
2648 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2649 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2650 ns = mlx5_get_flow_namespace(dev->mdev,
2651 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2652 build_leftovers_ft_param(&priority,
2653 &num_entries,
2654 &num_groups);
2655 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2656 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2657 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2658 allow_sniffer_and_nic_rx_shared_tir))
2659 return ERR_PTR(-ENOTSUPP);
2660
2661 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2662 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2663 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2664
2665 prio = &dev->flow_db.sniffer[ft_type];
2666 priority = 0;
2667 num_entries = 1;
2668 num_groups = 1;
038d2ef8
MG		 2669 }
2670
2671 if (!ns)
2672 return ERR_PTR(-ENOTSUPP);
2673
dac388ef
MG		 2674 if (num_entries > max_table_size)
2675 return ERR_PTR(-ENOMEM);
2676
038d2ef8
MG		 2677 ft = prio->flow_table;
2678 if (!ft) {
2679 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2680 num_entries,
d63cd286 2681 num_groups,
c9f1b073 2682 0, 0);
038d2ef8
MG		 2683
2684 if (!IS_ERR(ft)) {
2685 prio->refcount = 0;
2686 prio->flow_table = ft;
2687 } else {
2688 err = PTR_ERR(ft);
2689 }
2690 }
2691
2692 return err ? ERR_PTR(err) : prio;
2693}
2694
a550ddfc
YH		 2695static void set_underlay_qp(struct mlx5_ib_dev *dev,
2696 struct mlx5_flow_spec *spec,
2697 u32 underlay_qpn)
2698{
2699 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2700 spec->match_criteria,
2701 misc_parameters);
2702 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2703 misc_parameters);
2704
2705 if (underlay_qpn &&
2706 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2707 ft_field_support.bth_dst_qp)) {
2708 MLX5_SET(fte_match_set_misc,
2709 misc_params_v, bth_dst_qp, underlay_qpn);
2710 MLX5_SET(fte_match_set_misc,
2711 misc_params_c, bth_dst_qp, 0xffffff);
2712 }
2713}
2714
2715static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2716 struct mlx5_ib_flow_prio *ft_prio,
2717 const struct ib_flow_attr *flow_attr,
2718 struct mlx5_flow_destination *dst,
2719 u32 underlay_qpn)
038d2ef8
MG		 2720{
2721 struct mlx5_flow_table *ft = ft_prio->flow_table;
2722 struct mlx5_ib_flow_handler *handler;
66958ed9 2723 struct mlx5_flow_act flow_act = {0};
c5bb1730 2724 struct mlx5_flow_spec *spec;
a22ed86c 2725 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2726 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2727 unsigned int spec_index;
2ac693f9 2728 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2729 bool is_drop = false;
038d2ef8 2730 int err = 0;
a22ed86c 2731 int dest_num = 1;
038d2ef8 2732
19cc7524 2733 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2734 return ERR_PTR(-EINVAL);
2735
1b9a07ee 2736 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2737 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2738 if (!handler || !spec) {
038d2ef8
MG		 2739 err = -ENOMEM;
2740 goto free;
2741 }
2742
2743 INIT_LIST_HEAD(&handler->list);
2744
2745 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2746 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2747 spec->match_value,
2748 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2749 if (err < 0)
2750 goto free;
2751
2752 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2753 }
2754
a550ddfc
YH		 2755 if (!flow_is_multicast_only(flow_attr))
2756 set_underlay_qp(dev, spec, underlay_qpn);
2757
466fa6d2 2758 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2759 if (is_drop) {
2760 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2761 rule_dst = NULL;
2762 dest_num = 0;
2763 } else {
2764 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2765 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2766 }
2ac693f9
MR		 2767
2768 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2769 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2770 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2771 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2772 flow_tag, flow_attr->type);
2773 err = -EINVAL;
2774 goto free;
2775 }
2776 flow_act.flow_tag = flow_tag;
74491de9 2777 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2778 &flow_act,
a22ed86c 2779 rule_dst, dest_num);
038d2ef8
MG		 2780
2781 if (IS_ERR(handler->rule)) {
2782 err = PTR_ERR(handler->rule);
2783 goto free;
2784 }
2785
d9d4980a 2786 ft_prio->refcount++;
5497adc6 2787 handler->prio = ft_prio;
038d2ef8
MG		 2788
2789 ft_prio->flow_table = ft;
2790free:
2791 if (err)
2792 kfree(handler);
c5bb1730 2793 kvfree(spec);
038d2ef8
MG		 2794 return err ? ERR_PTR(err) : handler;
2795}
2796
a550ddfc
YH		 2797static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2798 struct mlx5_ib_flow_prio *ft_prio,
2799 const struct ib_flow_attr *flow_attr,
2800 struct mlx5_flow_destination *dst)
2801{
2802 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2803}
2804
35d19011
MG		 2805static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2806 struct mlx5_ib_flow_prio *ft_prio,
2807 struct ib_flow_attr *flow_attr,
2808 struct mlx5_flow_destination *dst)
2809{
2810 struct mlx5_ib_flow_handler *handler_dst = NULL;
2811 struct mlx5_ib_flow_handler *handler = NULL;
2812
2813 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2814 if (!IS_ERR(handler)) {
2815 handler_dst = create_flow_rule(dev, ft_prio,
2816 flow_attr, dst);
2817 if (IS_ERR(handler_dst)) {
74491de9 2818 mlx5_del_flow_rules(handler->rule);
d9d4980a 2819 ft_prio->refcount--;
35d19011
MG		 2820 kfree(handler);
2821 handler = handler_dst;
2822 } else {
2823 list_add(&handler_dst->list, &handler->list);
2824 }
2825 }
2826
2827 return handler;
2828}
038d2ef8
MG		 2829enum {
2830 LEFTOVERS_MC,
2831 LEFTOVERS_UC,
2832};
2833
2834static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2835 struct mlx5_ib_flow_prio *ft_prio,
2836 struct ib_flow_attr *flow_attr,
2837 struct mlx5_flow_destination *dst)
2838{
2839 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2840 struct mlx5_ib_flow_handler *handler = NULL;
2841
2842 static struct {
2843 struct ib_flow_attr flow_attr;
2844 struct ib_flow_spec_eth eth_flow;
2845 } leftovers_specs[] = {
2846 [LEFTOVERS_MC] = {
2847 .flow_attr = {
2848 .num_of_specs = 1,
2849 .size = sizeof(leftovers_specs[0])
2850 },
2851 .eth_flow = {
2852 .type = IB_FLOW_SPEC_ETH,
2853 .size = sizeof(struct ib_flow_spec_eth),
2854 .mask = {.dst_mac = {0x1} },
2855 .val = {.dst_mac = {0x1} }
2856 }
2857 },
2858 [LEFTOVERS_UC] = {
2859 .flow_attr = {
2860 .num_of_specs = 1,
2861 .size = sizeof(leftovers_specs[0])
2862 },
2863 .eth_flow = {
2864 .type = IB_FLOW_SPEC_ETH,
2865 .size = sizeof(struct ib_flow_spec_eth),
2866 .mask = {.dst_mac = {0x1} },
2867 .val = {.dst_mac = {} }
2868 }
2869 }
2870 };
2871
2872 handler = create_flow_rule(dev, ft_prio,
2873 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2874 dst);
2875 if (!IS_ERR(handler) &&
2876 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2877 handler_ucast = create_flow_rule(dev, ft_prio,
2878 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2879 dst);
2880 if (IS_ERR(handler_ucast)) {
74491de9 2881 mlx5_del_flow_rules(handler->rule);
d9d4980a 2882 ft_prio->refcount--;
038d2ef8
MG		 2883 kfree(handler);
2884 handler = handler_ucast;
2885 } else {
2886 list_add(&handler_ucast->list, &handler->list);
2887 }
2888 }
2889
2890 return handler;
2891}
2892
cc0e5d42
MG		 2893static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2894 struct mlx5_ib_flow_prio *ft_rx,
2895 struct mlx5_ib_flow_prio *ft_tx,
2896 struct mlx5_flow_destination *dst)
2897{
2898 struct mlx5_ib_flow_handler *handler_rx;
2899 struct mlx5_ib_flow_handler *handler_tx;
2900 int err;
2901 static const struct ib_flow_attr flow_attr = {
2902 .num_of_specs = 0,
2903 .size = sizeof(flow_attr)
2904 };
2905
2906 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2907 if (IS_ERR(handler_rx)) {
2908 err = PTR_ERR(handler_rx);
2909 goto err;
2910 }
2911
2912 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2913 if (IS_ERR(handler_tx)) {
2914 err = PTR_ERR(handler_tx);
2915 goto err_tx;
2916 }
2917
2918 list_add(&handler_tx->list, &handler_rx->list);
2919
2920 return handler_rx;
2921
2922err_tx:
74491de9 2923 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2924 ft_rx->refcount--;
2925 kfree(handler_rx);
2926err:
2927 return ERR_PTR(err);
2928}
2929
038d2ef8
MG		 2930static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2931 struct ib_flow_attr *flow_attr,
2932 int domain)
2933{
2934 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2935 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2936 struct mlx5_ib_flow_handler *handler = NULL;
2937 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2938 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2939 struct mlx5_ib_flow_prio *ft_prio;
2940 int err;
a550ddfc 2941 int underlay_qpn;
038d2ef8
MG		 2942
2943 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2944 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2945
2946 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 2947 flow_attr->port > dev->num_ports ||
35d19011 2948 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2949 return ERR_PTR(-EINVAL);
2950
2951 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2952 if (!dst)
2953 return ERR_PTR(-ENOMEM);
2954
2955 mutex_lock(&dev->flow_db.lock);
2956
cc0e5d42 2957 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2958 if (IS_ERR(ft_prio)) {
2959 err = PTR_ERR(ft_prio);
2960 goto unlock;
2961 }
cc0e5d42
MG		 2962 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2963 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2964 if (IS_ERR(ft_prio_tx)) {
2965 err = PTR_ERR(ft_prio_tx);
2966 ft_prio_tx = NULL;
2967 goto destroy_ft;
2968 }
2969 }
038d2ef8
MG		 2970
2971 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2972 if (mqp->flags & MLX5_IB_QP_RSS)
2973 dst->tir_num = mqp->rss_qp.tirn;
2974 else
2975 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2976
2977 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2978 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2979 handler = create_dont_trap_rule(dev, ft_prio,
2980 flow_attr, dst);
2981 } else {
a550ddfc
YH		 2982 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2983 mqp->underlay_qpn : 0;
2984 handler = _create_flow_rule(dev, ft_prio, flow_attr,
2985 dst, underlay_qpn);
35d19011 2986 }
038d2ef8
MG		 2987 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2988 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2989 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2990 dst);
cc0e5d42
MG		 2991 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2992 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2993 } else {
2994 err = -EINVAL;
2995 goto destroy_ft;
2996 }
2997
2998 if (IS_ERR(handler)) {
2999 err = PTR_ERR(handler);
3000 handler = NULL;
3001 goto destroy_ft;
3002 }
3003
038d2ef8
MG		 3004 mutex_unlock(&dev->flow_db.lock);
3005 kfree(dst);
3006
3007 return &handler->ibflow;
3008
3009destroy_ft:
3010 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3011 if (ft_prio_tx)
3012 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 3013unlock:
3014 mutex_unlock(&dev->flow_db.lock);
3015 kfree(dst);
3016 kfree(handler);
3017 return ERR_PTR(err);
3018}
3019
e126ba97
EC		 3020static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3021{
3022 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 3023 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 3024 int err;
3025
81e30880
YH		 3026 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3027 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3028 return -EOPNOTSUPP;
3029 }
3030
9603b61d 3031 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3032 if (err)
3033 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3034 ibqp->qp_num, gid->raw);
3035
3036 return err;
3037}
3038
3039static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3040{
3041 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3042 int err;
3043
9603b61d 3044 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3045 if (err)
3046 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3047 ibqp->qp_num, gid->raw);
3048
3049 return err;
3050}
3051
3052static int init_node_data(struct mlx5_ib_dev *dev)
3053{
1b5daf11 3054 int err;
e126ba97 3055
1b5daf11 3056 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 3057 if (err)
1b5daf11 3058 return err;
e126ba97 3059
1b5daf11 3060 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 3061
1b5daf11 3062 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 3063}
3064
3065static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3066 char *buf)
3067{
3068 struct mlx5_ib_dev *dev =
3069 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3070
9603b61d 3071 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 3072}
3073
3074static ssize_t show_reg_pages(struct device *device,
3075 struct device_attribute *attr, char *buf)
3076{
3077 struct mlx5_ib_dev *dev =
3078 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3079
6aec21f6 3080 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 3081}
3082
3083static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3084 char *buf)
3085{
3086 struct mlx5_ib_dev *dev =
3087 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3088 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 3089}
3090
e126ba97
EC		 3091static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3092 char *buf)
3093{
3094 struct mlx5_ib_dev *dev =
3095 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3096 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 3097}
3098
3099static ssize_t show_board(struct device *device, struct device_attribute *attr,
3100 char *buf)
3101{
3102 struct mlx5_ib_dev *dev =
3103 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3104 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 3105 dev->mdev->board_id);
e126ba97
EC		 3106}
3107
3108static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 3109static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3110static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3111static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3112static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3113
3114static struct device_attribute *mlx5_class_attributes[] = {
3115 &dev_attr_hw_rev,
e126ba97
EC		 3116 &dev_attr_hca_type,
3117 &dev_attr_board_id,
3118 &dev_attr_fw_pages,
3119 &dev_attr_reg_pages,
3120};
3121
7722f47e
HE		 3122static void pkey_change_handler(struct work_struct *work)
3123{
3124 struct mlx5_ib_port_resources *ports =
3125 container_of(work, struct mlx5_ib_port_resources,
3126 pkey_change_work);
3127
3128 mutex_lock(&ports->devr->mutex);
3129 mlx5_ib_gsi_pkey_change(ports->gsi);
3130 mutex_unlock(&ports->devr->mutex);
3131}
3132
89ea94a7
MG		 3133static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3134{
3135 struct mlx5_ib_qp *mqp;
3136 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3137 struct mlx5_core_cq *mcq;
3138 struct list_head cq_armed_list;
3139 unsigned long flags_qp;
3140 unsigned long flags_cq;
3141 unsigned long flags;
3142
3143 INIT_LIST_HEAD(&cq_armed_list);
3144
3145 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3146 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3147 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3148 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3149 if (mqp->sq.tail != mqp->sq.head) {
3150 send_mcq = to_mcq(mqp->ibqp.send_cq);
3151 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3152 if (send_mcq->mcq.comp &&
3153 mqp->ibqp.send_cq->comp_handler) {
3154 if (!send_mcq->mcq.reset_notify_added) {
3155 send_mcq->mcq.reset_notify_added = 1;
3156 list_add_tail(&send_mcq->mcq.reset_notify,
3157 &cq_armed_list);
3158 }
3159 }
3160 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3161 }
3162 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3163 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3164 /* no handling is needed for SRQ */
3165 if (!mqp->ibqp.srq) {
3166 if (mqp->rq.tail != mqp->rq.head) {
3167 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3168 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3169 if (recv_mcq->mcq.comp &&
3170 mqp->ibqp.recv_cq->comp_handler) {
3171 if (!recv_mcq->mcq.reset_notify_added) {
3172 recv_mcq->mcq.reset_notify_added = 1;
3173 list_add_tail(&recv_mcq->mcq.reset_notify,
3174 &cq_armed_list);
3175 }
3176 }
3177 spin_unlock_irqrestore(&recv_mcq->lock,
3178 flags_cq);
3179 }
3180 }
3181 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3182 }
3183 /*At that point all inflight post send were put to be executed as of we
3184 * lock/unlock above locks Now need to arm all involved CQs.
3185 */
3186 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3187 mcq->comp(mcq);
3188 }
3189 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3190}
3191
03404e8a
MG		 3192static void delay_drop_handler(struct work_struct *work)
3193{
3194 int err;
3195 struct mlx5_ib_delay_drop *delay_drop =
3196 container_of(work, struct mlx5_ib_delay_drop,
3197 delay_drop_work);
3198
fe248c3a
MG		 3199 atomic_inc(&delay_drop->events_cnt);
3200
03404e8a
MG		 3201 mutex_lock(&delay_drop->lock);
3202 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3203 delay_drop->timeout);
3204 if (err) {
3205 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3206 delay_drop->timeout);
3207 delay_drop->activate = false;
3208 }
3209 mutex_unlock(&delay_drop->lock);
3210}
3211
d69a24e0 3212static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 3213{
d69a24e0
DJ		 3214 struct mlx5_ib_event_work *work =
3215 container_of(_work, struct mlx5_ib_event_work, work);
3216 struct mlx5_ib_dev *ibdev;
e126ba97 3217 struct ib_event ibev;
dbaaff2a 3218 bool fatal = false;
e126ba97
EC		 3219 u8 port = 0;
3220
d69a24e0
DJ		 3221 if (mlx5_core_is_mp_slave(work->dev)) {
3222 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3223 if (!ibdev)
3224 goto out;
3225 } else {
3226 ibdev = work->context;
3227 }
3228
3229 switch (work->event) {
e126ba97 3230 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 3231 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 3232 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 3233 fatal = true;
e126ba97
EC		 3234 break;
3235
3236 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 3237 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 3238 case MLX5_DEV_EVENT_PORT_INITIALIZED:
d69a24e0 3239 port = (u8)work->param;
5ec8c83e
AH		 3240
3241 /* In RoCE, port up/down events are handled in
3242 * mlx5_netdev_event().
3243 */
3244 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3245 IB_LINK_LAYER_ETHERNET)
d69a24e0 3246 goto out;
5ec8c83e 3247
d69a24e0 3248 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 3249 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 3250 break;
3251
e126ba97
EC		 3252 case MLX5_DEV_EVENT_LID_CHANGE:
3253 ibev.event = IB_EVENT_LID_CHANGE;
d69a24e0 3254 port = (u8)work->param;
e126ba97
EC		 3255 break;
3256
3257 case MLX5_DEV_EVENT_PKEY_CHANGE:
3258 ibev.event = IB_EVENT_PKEY_CHANGE;
d69a24e0 3259 port = (u8)work->param;
7722f47e
HE		 3260
3261 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 3262 break;
3263
3264 case MLX5_DEV_EVENT_GUID_CHANGE:
3265 ibev.event = IB_EVENT_GID_CHANGE;
d69a24e0 3266 port = (u8)work->param;
e126ba97
EC		 3267 break;
3268
3269 case MLX5_DEV_EVENT_CLIENT_REREG:
3270 ibev.event = IB_EVENT_CLIENT_REREGISTER;
d69a24e0 3271 port = (u8)work->param;
e126ba97 3272 break;
03404e8a
MG		 3273 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3274 schedule_work(&ibdev->delay_drop.delay_drop_work);
3275 goto out;
bdc37924 3276 default:
03404e8a 3277 goto out;
e126ba97
EC		 3278 }
3279
3280 ibev.device = &ibdev->ib_dev;
3281 ibev.element.port_num = port;
3282
a0c84c32
EC		 3283 if (port < 1 || port > ibdev->num_ports) {
3284 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 3285 goto out;
a0c84c32
EC		 3286 }
3287
e126ba97
EC		 3288 if (ibdev->ib_active)
3289 ib_dispatch_event(&ibev);
dbaaff2a
EC		 3290
3291 if (fatal)
3292 ibdev->ib_active = false;
03404e8a 3293out:
d69a24e0
DJ		 3294 kfree(work);
3295}
3296
3297static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3298 enum mlx5_dev_event event, unsigned long param)
3299{
3300 struct mlx5_ib_event_work *work;
3301
3302 work = kmalloc(sizeof(*work), GFP_ATOMIC);
3303 if (work) {
3304 INIT_WORK(&work->work, mlx5_ib_handle_event);
3305 work->dev = dev;
3306 work->param = param;
3307 work->context = context;
3308 work->event = event;
3309
3310 queue_work(mlx5_ib_event_wq, &work->work);
3311 return;
3312 }
3313
3314 dev_warn(&dev->pdev->dev, "%s: mlx5_dev_event: %d, with param: %lu dropped, couldn't allocate memory.\n",
3315 __func__, event, param);
e126ba97
EC		 3316}
3317
c43f1112
MG		 3318static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3319{
3320 struct mlx5_hca_vport_context vport_ctx;
3321 int err;
3322 int port;
3323
508562d6 3324 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 3325 dev->mdev->port_caps[port - 1].has_smi = false;
3326 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3327 MLX5_CAP_PORT_TYPE_IB) {
3328 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3329 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3330 port, 0,
3331 &vport_ctx);
3332 if (err) {
3333 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3334 port, err);
3335 return err;
3336 }
3337 dev->mdev->port_caps[port - 1].has_smi =
3338 vport_ctx.has_smi;
3339 } else {
3340 dev->mdev->port_caps[port - 1].has_smi = true;
3341 }
3342 }
3343 }
3344 return 0;
3345}
3346
e126ba97
EC		 3347static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3348{
3349 int port;
3350
508562d6 3351 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 3352 mlx5_query_ext_port_caps(dev, port);
3353}
3354
32f69e4b 3355static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 3356{
3357 struct ib_device_attr *dprops = NULL;
3358 struct ib_port_attr *pprops = NULL;
f614fc15 3359 int err = -ENOMEM;
2528e33e 3360 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3361
3362 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3363 if (!pprops)
3364 goto out;
3365
3366 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3367 if (!dprops)
3368 goto out;
3369
c43f1112
MG		 3370 err = set_has_smi_cap(dev);
3371 if (err)
3372 goto out;
3373
2528e33e 3374 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3375 if (err) {
3376 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3377 goto out;
3378 }
3379
32f69e4b
DJ		 3380 memset(pprops, 0, sizeof(*pprops));
3381 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3382 if (err) {
3383 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3384 port, err);
3385 goto out;
e126ba97
EC		 3386 }
3387
32f69e4b
DJ		 3388 dev->mdev->port_caps[port - 1].pkey_table_len =
3389 dprops->max_pkeys;
3390 dev->mdev->port_caps[port - 1].gid_table_len =
3391 pprops->gid_tbl_len;
3392 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3393 port, dprops->max_pkeys, pprops->gid_tbl_len);
3394
e126ba97
EC		 3395out:
3396 kfree(pprops);
3397 kfree(dprops);
3398
3399 return err;
3400}
3401
3402static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3403{
3404 int err;
3405
3406 err = mlx5_mr_cache_cleanup(dev);
3407 if (err)
3408 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3409
3410 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 3411 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 3412 ib_dealloc_pd(dev->umrc.pd);
3413}
3414
3415enum {
3416 MAX_UMR_WR = 128,
3417};
3418
3419static int create_umr_res(struct mlx5_ib_dev *dev)
3420{
3421 struct ib_qp_init_attr *init_attr = NULL;
3422 struct ib_qp_attr *attr = NULL;
3423 struct ib_pd *pd;
3424 struct ib_cq *cq;
3425 struct ib_qp *qp;
e126ba97
EC		 3426 int ret;
3427
3428 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3429 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3430 if (!attr || !init_attr) {
3431 ret = -ENOMEM;
3432 goto error_0;
3433 }
3434
ed082d36 3435 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3436 if (IS_ERR(pd)) {
3437 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3438 ret = PTR_ERR(pd);
3439 goto error_0;
3440 }
3441
add08d76 3442 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3443 if (IS_ERR(cq)) {
3444 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3445 ret = PTR_ERR(cq);
3446 goto error_2;
3447 }
e126ba97
EC		 3448
3449 init_attr->send_cq = cq;
3450 init_attr->recv_cq = cq;
3451 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3452 init_attr->cap.max_send_wr = MAX_UMR_WR;
3453 init_attr->cap.max_send_sge = 1;
3454 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3455 init_attr->port_num = 1;
3456 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3457 if (IS_ERR(qp)) {
3458 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3459 ret = PTR_ERR(qp);
3460 goto error_3;
3461 }
3462 qp->device = &dev->ib_dev;
3463 qp->real_qp = qp;
3464 qp->uobject = NULL;
3465 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 3466 qp->send_cq = init_attr->send_cq;
3467 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 3468
3469 attr->qp_state = IB_QPS_INIT;
3470 attr->port_num = 1;
3471 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3472 IB_QP_PORT, NULL);
3473 if (ret) {
3474 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3475 goto error_4;
3476 }
3477
3478 memset(attr, 0, sizeof(*attr));
3479 attr->qp_state = IB_QPS_RTR;
3480 attr->path_mtu = IB_MTU_256;
3481
3482 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3483 if (ret) {
3484 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3485 goto error_4;
3486 }
3487
3488 memset(attr, 0, sizeof(*attr));
3489 attr->qp_state = IB_QPS_RTS;
3490 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3491 if (ret) {
3492 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3493 goto error_4;
3494 }
3495
3496 dev->umrc.qp = qp;
3497 dev->umrc.cq = cq;
e126ba97
EC		 3498 dev->umrc.pd = pd;
3499
3500 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3501 ret = mlx5_mr_cache_init(dev);
3502 if (ret) {
3503 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3504 goto error_4;
3505 }
3506
3507 kfree(attr);
3508 kfree(init_attr);
3509
3510 return 0;
3511
3512error_4:
3513 mlx5_ib_destroy_qp(qp);
3514
3515error_3:
add08d76 3516 ib_free_cq(cq);
e126ba97
EC		 3517
3518error_2:
e126ba97
EC		 3519 ib_dealloc_pd(pd);
3520
3521error_0:
3522 kfree(attr);
3523 kfree(init_attr);
3524 return ret;
3525}
3526
6e8484c5
MG		 3527static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3528{
3529 switch (umr_fence_cap) {
3530 case MLX5_CAP_UMR_FENCE_NONE:
3531 return MLX5_FENCE_MODE_NONE;
3532 case MLX5_CAP_UMR_FENCE_SMALL:
3533 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3534 default:
3535 return MLX5_FENCE_MODE_STRONG_ORDERING;
3536 }
3537}
3538
e126ba97
EC		 3539static int create_dev_resources(struct mlx5_ib_resources *devr)
3540{
3541 struct ib_srq_init_attr attr;
3542 struct mlx5_ib_dev *dev;
bcf4c1ea 3543 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3544 int port;
e126ba97
EC		 3545 int ret = 0;
3546
3547 dev = container_of(devr, struct mlx5_ib_dev, devr);
3548
d16e91da
HE		 3549 mutex_init(&devr->mutex);
3550
e126ba97
EC		 3551 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3552 if (IS_ERR(devr->p0)) {
3553 ret = PTR_ERR(devr->p0);
3554 goto error0;
3555 }
3556 devr->p0->device = &dev->ib_dev;
3557 devr->p0->uobject = NULL;
3558 atomic_set(&devr->p0->usecnt, 0);
3559
bcf4c1ea 3560 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3561 if (IS_ERR(devr->c0)) {
3562 ret = PTR_ERR(devr->c0);
3563 goto error1;
3564 }
3565 devr->c0->device = &dev->ib_dev;
3566 devr->c0->uobject = NULL;
3567 devr->c0->comp_handler = NULL;
3568 devr->c0->event_handler = NULL;
3569 devr->c0->cq_context = NULL;
3570 atomic_set(&devr->c0->usecnt, 0);
3571
3572 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3573 if (IS_ERR(devr->x0)) {
3574 ret = PTR_ERR(devr->x0);
3575 goto error2;
3576 }
3577 devr->x0->device = &dev->ib_dev;
3578 devr->x0->inode = NULL;
3579 atomic_set(&devr->x0->usecnt, 0);
3580 mutex_init(&devr->x0->tgt_qp_mutex);
3581 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3582
3583 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3584 if (IS_ERR(devr->x1)) {
3585 ret = PTR_ERR(devr->x1);
3586 goto error3;
3587 }
3588 devr->x1->device = &dev->ib_dev;
3589 devr->x1->inode = NULL;
3590 atomic_set(&devr->x1->usecnt, 0);
3591 mutex_init(&devr->x1->tgt_qp_mutex);
3592 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3593
3594 memset(&attr, 0, sizeof(attr));
3595 attr.attr.max_sge = 1;
3596 attr.attr.max_wr = 1;
3597 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 3598 attr.ext.cq = devr->c0;
e126ba97
EC		 3599 attr.ext.xrc.xrcd = devr->x0;
3600
3601 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3602 if (IS_ERR(devr->s0)) {
3603 ret = PTR_ERR(devr->s0);
3604 goto error4;
3605 }
3606 devr->s0->device = &dev->ib_dev;
3607 devr->s0->pd = devr->p0;
3608 devr->s0->uobject = NULL;
3609 devr->s0->event_handler = NULL;
3610 devr->s0->srq_context = NULL;
3611 devr->s0->srq_type = IB_SRQT_XRC;
3612 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 3613 devr->s0->ext.cq = devr->c0;
e126ba97 3614 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 3615 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 3616 atomic_inc(&devr->p0->usecnt);
3617 atomic_set(&devr->s0->usecnt, 0);
3618
4aa17b28
HA		 3619 memset(&attr, 0, sizeof(attr));
3620 attr.attr.max_sge = 1;
3621 attr.attr.max_wr = 1;
3622 attr.srq_type = IB_SRQT_BASIC;
3623 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3624 if (IS_ERR(devr->s1)) {
3625 ret = PTR_ERR(devr->s1);
3626 goto error5;
3627 }
3628 devr->s1->device = &dev->ib_dev;
3629 devr->s1->pd = devr->p0;
3630 devr->s1->uobject = NULL;
3631 devr->s1->event_handler = NULL;
3632 devr->s1->srq_context = NULL;
3633 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 3634 devr->s1->ext.cq = devr->c0;
4aa17b28 3635 atomic_inc(&devr->p0->usecnt);
1a56ff6d 3636 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 3637
7722f47e
HE		 3638 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3639 INIT_WORK(&devr->ports[port].pkey_change_work,
3640 pkey_change_handler);
3641 devr->ports[port].devr = devr;
3642 }
3643
e126ba97
EC		 3644 return 0;
3645
4aa17b28
HA		 3646error5:
3647 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3648error4:
3649 mlx5_ib_dealloc_xrcd(devr->x1);
3650error3:
3651 mlx5_ib_dealloc_xrcd(devr->x0);
3652error2:
3653 mlx5_ib_destroy_cq(devr->c0);
3654error1:
3655 mlx5_ib_dealloc_pd(devr->p0);
3656error0:
3657 return ret;
3658}
3659
3660static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3661{
7722f47e
HE		 3662 struct mlx5_ib_dev *dev =
3663 container_of(devr, struct mlx5_ib_dev, devr);
3664 int port;
3665
4aa17b28 3666 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3667 mlx5_ib_destroy_srq(devr->s0);
3668 mlx5_ib_dealloc_xrcd(devr->x0);
3669 mlx5_ib_dealloc_xrcd(devr->x1);
3670 mlx5_ib_destroy_cq(devr->c0);
3671 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3672
3673 /* Make sure no change P_Key work items are still executing */
3674 for (port = 0; port < dev->num_ports; ++port)
3675 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3676}
3677
e53505a8
AS		 3678static u32 get_core_cap_flags(struct ib_device *ibdev)
3679{
3680 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3681 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3682 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3683 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3684 u32 ret = 0;
3685
3686 if (ll == IB_LINK_LAYER_INFINIBAND)
3687 return RDMA_CORE_PORT_IBA_IB;
3688
72cd5717
OG		 3689 ret = RDMA_CORE_PORT_RAW_PACKET;
3690
e53505a8 3691 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3692 return ret;
e53505a8
AS		 3693
3694 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3695 return ret;
e53505a8
AS		 3696
3697 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3698 ret |= RDMA_CORE_PORT_IBA_ROCE;
3699
3700 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3701 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3702
3703 return ret;
3704}
3705
7738613e
IW		 3706static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3707 struct ib_port_immutable *immutable)
3708{
3709 struct ib_port_attr attr;
ca5b91d6
OG		 3710 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3711 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3712 int err;
3713
c4550c63
OG		 3714 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3715
3716 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3717 if (err)
3718 return err;
3719
3720 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3721 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3722 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3723 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3724 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3725
3726 return 0;
3727}
3728
9abb0d1b 3729static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3730{
3731 struct mlx5_ib_dev *dev =
3732 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3733 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3734 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3735 fw_rev_sub(dev->mdev));
c7342823
IW		 3736}
3737
45f95acd 3738static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3739{
3740 struct mlx5_core_dev *mdev = dev->mdev;
3741 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3742 MLX5_FLOW_NAMESPACE_LAG);
3743 struct mlx5_flow_table *ft;
3744 int err;
3745
3746 if (!ns || !mlx5_lag_is_active(mdev))
3747 return 0;
3748
3749 err = mlx5_cmd_create_vport_lag(mdev);
3750 if (err)
3751 return err;
3752
3753 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3754 if (IS_ERR(ft)) {
3755 err = PTR_ERR(ft);
3756 goto err_destroy_vport_lag;
3757 }
3758
3759 dev->flow_db.lag_demux_ft = ft;
3760 return 0;
3761
3762err_destroy_vport_lag:
3763 mlx5_cmd_destroy_vport_lag(mdev);
3764 return err;
3765}
3766
45f95acd 3767static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3768{
3769 struct mlx5_core_dev *mdev = dev->mdev;
3770
3771 if (dev->flow_db.lag_demux_ft) {
3772 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3773 dev->flow_db.lag_demux_ft = NULL;
3774
3775 mlx5_cmd_destroy_vport_lag(mdev);
3776 }
3777}
3778
7fd8aefb 3779static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 3780{
3781 int err;
3782
7fd8aefb
DJ		 3783 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
3784 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 3785 if (err) {
7fd8aefb 3786 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 3787 return err;
3788 }
3789
3790 return 0;
3791}
3792
7fd8aefb 3793static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 3794{
7fd8aefb
DJ		 3795 if (dev->roce[port_num].nb.notifier_call) {
3796 unregister_netdevice_notifier(&dev->roce[port_num].nb);
3797 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 3798 }
3799}
3800
7fd8aefb 3801static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
fc24fc5e 3802{
e53505a8
AS		 3803 int err;
3804
7fd8aefb 3805 err = mlx5_add_netdev_notifier(dev, port_num);
d012f5d6 3806 if (err)
e53505a8
AS		 3807 return err;
3808
ca5b91d6
OG		 3809 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3810 err = mlx5_nic_vport_enable_roce(dev->mdev);
3811 if (err)
3812 goto err_unregister_netdevice_notifier;
3813 }
e53505a8 3814
45f95acd 3815 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3816 if (err)
3817 goto err_disable_roce;
3818
e53505a8
AS		 3819 return 0;
3820
9ef9c640 3821err_disable_roce:
ca5b91d6
OG		 3822 if (MLX5_CAP_GEN(dev->mdev, roce))
3823 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3824
e53505a8 3825err_unregister_netdevice_notifier:
7fd8aefb 3826 mlx5_remove_netdev_notifier(dev, port_num);
e53505a8 3827 return err;
fc24fc5e
AS		 3828}
3829
45f95acd 3830static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3831{
45f95acd 3832 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3833 if (MLX5_CAP_GEN(dev->mdev, roce))
3834 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3835}
3836
e1f24a79 3837struct mlx5_ib_counter {
7c16f477
KH		 3838 const char *name;
3839 size_t offset;
3840};
3841
3842#define INIT_Q_COUNTER(_name) \
3843 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3844
e1f24a79 3845static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3846 INIT_Q_COUNTER(rx_write_requests),
3847 INIT_Q_COUNTER(rx_read_requests),
3848 INIT_Q_COUNTER(rx_atomic_requests),
3849 INIT_Q_COUNTER(out_of_buffer),
3850};
3851
e1f24a79 3852static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3853 INIT_Q_COUNTER(out_of_sequence),
3854};
3855
e1f24a79 3856static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3857 INIT_Q_COUNTER(duplicate_request),
3858 INIT_Q_COUNTER(rnr_nak_retry_err),
3859 INIT_Q_COUNTER(packet_seq_err),
3860 INIT_Q_COUNTER(implied_nak_seq_err),
3861 INIT_Q_COUNTER(local_ack_timeout_err),
3862};
3863
e1f24a79
PP		 3864#define INIT_CONG_COUNTER(_name) \
3865 { .name = #_name, .offset = \
3866 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3867
3868static const struct mlx5_ib_counter cong_cnts[] = {
3869 INIT_CONG_COUNTER(rp_cnp_ignored),
3870 INIT_CONG_COUNTER(rp_cnp_handled),
3871 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3872 INIT_CONG_COUNTER(np_cnp_sent),
3873};
3874
58dcb60a
PP		 3875static const struct mlx5_ib_counter extended_err_cnts[] = {
3876 INIT_Q_COUNTER(resp_local_length_error),
3877 INIT_Q_COUNTER(resp_cqe_error),
3878 INIT_Q_COUNTER(req_cqe_error),
3879 INIT_Q_COUNTER(req_remote_invalid_request),
3880 INIT_Q_COUNTER(req_remote_access_errors),
3881 INIT_Q_COUNTER(resp_remote_access_errors),
3882 INIT_Q_COUNTER(resp_cqe_flush_error),
3883 INIT_Q_COUNTER(req_cqe_flush_error),
3884};
3885
e1f24a79 3886static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 3887{
aac4492e 3888 int i;
0837e86a 3889
7c16f477 3890 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 3891 if (dev->port[i].cnts.set_id)
3892 mlx5_core_dealloc_q_counter(dev->mdev,
3893 dev->port[i].cnts.set_id);
e1f24a79
PP		 3894 kfree(dev->port[i].cnts.names);
3895 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3896 }
3897}
3898
e1f24a79
PP		 3899static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3900 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3901{
3902 u32 num_counters;
3903
3904 num_counters = ARRAY_SIZE(basic_q_cnts);
3905
3906 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3907 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3908
3909 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3910 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 3911
3912 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3913 num_counters += ARRAY_SIZE(extended_err_cnts);
3914
e1f24a79 3915 cnts->num_q_counters = num_counters;
7c16f477 3916
e1f24a79
PP		 3917 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3918 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3919 num_counters += ARRAY_SIZE(cong_cnts);
3920 }
3921
3922 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3923 if (!cnts->names)
7c16f477
KH		 3924 return -ENOMEM;
3925
e1f24a79
PP		 3926 cnts->offsets = kcalloc(num_counters,
3927 sizeof(cnts->offsets), GFP_KERNEL);
3928 if (!cnts->offsets)
7c16f477
KH		 3929 goto err_names;
3930
7c16f477
KH		 3931 return 0;
3932
3933err_names:
e1f24a79 3934 kfree(cnts->names);
aac4492e 3935 cnts->names = NULL;
7c16f477
KH		 3936 return -ENOMEM;
3937}
3938
e1f24a79
PP		 3939static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3940 const char **names,
3941 size_t *offsets)
7c16f477
KH		 3942{
3943 int i;
3944 int j = 0;
3945
3946 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3947 names[j] = basic_q_cnts[i].name;
3948 offsets[j] = basic_q_cnts[i].offset;
3949 }
3950
3951 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3952 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3953 names[j] = out_of_seq_q_cnts[i].name;
3954 offsets[j] = out_of_seq_q_cnts[i].offset;
3955 }
3956 }
3957
3958 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3959 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3960 names[j] = retrans_q_cnts[i].name;
3961 offsets[j] = retrans_q_cnts[i].offset;
3962 }
3963 }
e1f24a79 3964
58dcb60a
PP		 3965 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3966 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3967 names[j] = extended_err_cnts[i].name;
3968 offsets[j] = extended_err_cnts[i].offset;
3969 }
3970 }
3971
e1f24a79
PP		 3972 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3973 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3974 names[j] = cong_cnts[i].name;
3975 offsets[j] = cong_cnts[i].offset;
3976 }
3977 }
0837e86a
MB		 3978}
3979
e1f24a79 3980static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 3981{
aac4492e 3982 int err = 0;
0837e86a 3983 int i;
0837e86a
MB		 3984
3985 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 3986 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
3987 if (err)
3988 goto err_alloc;
3989
3990 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
3991 dev->port[i].cnts.offsets);
7c16f477 3992
aac4492e
DJ		 3993 err = mlx5_core_alloc_q_counter(dev->mdev,
3994 &dev->port[i].cnts.set_id);
3995 if (err) {
0837e86a
MB		 3996 mlx5_ib_warn(dev,
3997 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 3998 i + 1, err);
3999 goto err_alloc;
0837e86a 4000 }
aac4492e 4001 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 4002 }
4003
4004 return 0;
4005
aac4492e
DJ		 4006err_alloc:
4007 mlx5_ib_dealloc_counters(dev);
4008 return err;
0837e86a
MB		 4009}
4010
0ad17a8f
MB		 4011static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4012 u8 port_num)
4013{
7c16f477
KH		 4014 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4015 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 4016
4017 /* We support only per port stats */
4018 if (port_num == 0)
4019 return NULL;
4020
e1f24a79
PP		 4021 return rdma_alloc_hw_stats_struct(port->cnts.names,
4022 port->cnts.num_q_counters +
4023 port->cnts.num_cong_counters,
0ad17a8f
MB		 4024 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4025}
4026
aac4492e 4027static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 4028 struct mlx5_ib_port *port,
4029 struct rdma_hw_stats *stats)
0ad17a8f 4030{
0ad17a8f
MB		 4031 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4032 void *out;
4033 __be32 val;
e1f24a79 4034 int ret, i;
0ad17a8f 4035
1b9a07ee 4036 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 4037 if (!out)
4038 return -ENOMEM;
4039
aac4492e 4040 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 4041 port->cnts.set_id, 0,
0ad17a8f
MB		 4042 out, outlen);
4043 if (ret)
4044 goto free;
4045
e1f24a79
PP		 4046 for (i = 0; i < port->cnts.num_q_counters; i++) {
4047 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 4048 stats->value[i] = (u64)be32_to_cpu(val);
4049 }
7c16f477 4050
0ad17a8f
MB		 4051free:
4052 kvfree(out);
e1f24a79
PP		 4053 return ret;
4054}
4055
e1f24a79
PP		 4056static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4057 struct rdma_hw_stats *stats,
4058 u8 port_num, int index)
4059{
4060 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4061 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 4062 struct mlx5_core_dev *mdev;
e1f24a79 4063 int ret, num_counters;
aac4492e 4064 u8 mdev_port_num;
e1f24a79
PP		 4065
4066 if (!stats)
4067 return -EINVAL;
4068
aac4492e
DJ		 4069 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4070
4071 /* q_counters are per IB device, query the master mdev */
4072 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 4073 if (ret)
4074 return ret;
e1f24a79
PP		 4075
4076 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 4077 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4078 &mdev_port_num);
4079 if (!mdev) {
4080 /* If port is not affiliated yet, its in down state
4081 * which doesn't have any counters yet, so it would be
4082 * zero. So no need to read from the HCA.
4083 */
4084 goto done;
4085 }
71a0ff65
MD		 4086 ret = mlx5_lag_query_cong_counters(dev->mdev,
4087 stats->value +
4088 port->cnts.num_q_counters,
4089 port->cnts.num_cong_counters,
4090 port->cnts.offsets +
4091 port->cnts.num_q_counters);
aac4492e
DJ		 4092
4093 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 4094 if (ret)
4095 return ret;
e1f24a79
PP		 4096 }
4097
aac4492e 4098done:
e1f24a79 4099 return num_counters;
0ad17a8f
MB		 4100}
4101
8e959601
NV		 4102static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4103{
4104 return mlx5_rdma_netdev_free(netdev);
4105}
4106
693dfd5a
ES		 4107static struct net_device*
4108mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4109 u8 port_num,
4110 enum rdma_netdev_t type,
4111 const char *name,
4112 unsigned char name_assign_type,
4113 void (*setup)(struct net_device *))
4114{
8e959601
NV		 4115 struct net_device *netdev;
4116 struct rdma_netdev *rn;
4117
693dfd5a
ES		 4118 if (type != RDMA_NETDEV_IPOIB)
4119 return ERR_PTR(-EOPNOTSUPP);
4120
8e959601
NV		 4121 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4122 name, setup);
4123 if (likely(!IS_ERR_OR_NULL(netdev))) {
4124 rn = netdev_priv(netdev);
4125 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4126 }
4127 return netdev;
693dfd5a
ES		 4128}
4129
fe248c3a
MG		 4130static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4131{
4132 if (!dev->delay_drop.dbg)
4133 return;
4134 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4135 kfree(dev->delay_drop.dbg);
4136 dev->delay_drop.dbg = NULL;
4137}
4138
03404e8a
MG		 4139static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4140{
4141 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4142 return;
4143
4144 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 4145 delay_drop_debugfs_cleanup(dev);
4146}
4147
4148static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4149 size_t count, loff_t *pos)
4150{
4151 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4152 char lbuf[20];
4153 int len;
4154
4155 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4156 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4157}
4158
4159static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4160 size_t count, loff_t *pos)
4161{
4162 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4163 u32 timeout;
4164 u32 var;
4165
4166 if (kstrtouint_from_user(buf, count, 0, &var))
4167 return -EFAULT;
4168
4169 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4170 1000);
4171 if (timeout != var)
4172 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4173 timeout);
4174
4175 delay_drop->timeout = timeout;
4176
4177 return count;
4178}
4179
4180static const struct file_operations fops_delay_drop_timeout = {
4181 .owner = THIS_MODULE,
4182 .open = simple_open,
4183 .write = delay_drop_timeout_write,
4184 .read = delay_drop_timeout_read,
4185};
4186
4187static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4188{
4189 struct mlx5_ib_dbg_delay_drop *dbg;
4190
4191 if (!mlx5_debugfs_root)
4192 return 0;
4193
4194 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4195 if (!dbg)
4196 return -ENOMEM;
4197
cbafad87
SM		 4198 dev->delay_drop.dbg = dbg;
4199
fe248c3a
MG		 4200 dbg->dir_debugfs =
4201 debugfs_create_dir("delay_drop",
4202 dev->mdev->priv.dbg_root);
4203 if (!dbg->dir_debugfs)
cbafad87 4204 goto out_debugfs;
fe248c3a
MG		 4205
4206 dbg->events_cnt_debugfs =
4207 debugfs_create_atomic_t("num_timeout_events", 0400,
4208 dbg->dir_debugfs,
4209 &dev->delay_drop.events_cnt);
4210 if (!dbg->events_cnt_debugfs)
4211 goto out_debugfs;
4212
4213 dbg->rqs_cnt_debugfs =
4214 debugfs_create_atomic_t("num_rqs", 0400,
4215 dbg->dir_debugfs,
4216 &dev->delay_drop.rqs_cnt);
4217 if (!dbg->rqs_cnt_debugfs)
4218 goto out_debugfs;
4219
4220 dbg->timeout_debugfs =
4221 debugfs_create_file("timeout", 0600,
4222 dbg->dir_debugfs,
4223 &dev->delay_drop,
4224 &fops_delay_drop_timeout);
4225 if (!dbg->timeout_debugfs)
4226 goto out_debugfs;
4227
4228 return 0;
4229
4230out_debugfs:
4231 delay_drop_debugfs_cleanup(dev);
4232 return -ENOMEM;
03404e8a
MG		 4233}
4234
4235static void init_delay_drop(struct mlx5_ib_dev *dev)
4236{
4237 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4238 return;
4239
4240 mutex_init(&dev->delay_drop.lock);
4241 dev->delay_drop.dev = dev;
4242 dev->delay_drop.activate = false;
4243 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4244 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 4245 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4246 atomic_set(&dev->delay_drop.events_cnt, 0);
4247
4248 if (delay_drop_debugfs_init(dev))
4249 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 4250}
4251
84305d71
LR		 4252static const struct cpumask *
4253mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 4254{
4255 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4256
4257 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4258}
4259
32f69e4b
DJ		 4260/* The mlx5_ib_multiport_mutex should be held when calling this function */
4261static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4262 struct mlx5_ib_multiport_info *mpi)
4263{
4264 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4265 struct mlx5_ib_port *port = &ibdev->port[port_num];
4266 int comps;
4267 int err;
4268 int i;
4269
a9e546e7
PP		 4270 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4271
32f69e4b
DJ		 4272 spin_lock(&port->mp.mpi_lock);
4273 if (!mpi->ibdev) {
4274 spin_unlock(&port->mp.mpi_lock);
4275 return;
4276 }
4277 mpi->ibdev = NULL;
4278
4279 spin_unlock(&port->mp.mpi_lock);
4280 mlx5_remove_netdev_notifier(ibdev, port_num);
4281 spin_lock(&port->mp.mpi_lock);
4282
4283 comps = mpi->mdev_refcnt;
4284 if (comps) {
4285 mpi->unaffiliate = true;
4286 init_completion(&mpi->unref_comp);
4287 spin_unlock(&port->mp.mpi_lock);
4288
4289 for (i = 0; i < comps; i++)
4290 wait_for_completion(&mpi->unref_comp);
4291
4292 spin_lock(&port->mp.mpi_lock);
4293 mpi->unaffiliate = false;
4294 }
4295
4296 port->mp.mpi = NULL;
4297
4298 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4299
4300 spin_unlock(&port->mp.mpi_lock);
4301
4302 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4303
4304 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4305 /* Log an error, still needed to cleanup the pointers and add
4306 * it back to the list.
4307 */
4308 if (err)
4309 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4310 port_num + 1);
4311
4312 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4313}
4314
4315/* The mlx5_ib_multiport_mutex should be held when calling this function */
4316static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4317 struct mlx5_ib_multiport_info *mpi)
4318{
4319 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4320 int err;
4321
4322 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4323 if (ibdev->port[port_num].mp.mpi) {
4324 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4325 port_num + 1);
4326 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4327 return false;
4328 }
4329
4330 ibdev->port[port_num].mp.mpi = mpi;
4331 mpi->ibdev = ibdev;
4332 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4333
4334 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4335 if (err)
4336 goto unbind;
4337
4338 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4339 if (err)
4340 goto unbind;
4341
4342 err = mlx5_add_netdev_notifier(ibdev, port_num);
4343 if (err) {
4344 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4345 port_num + 1);
4346 goto unbind;
4347 }
4348
a9e546e7
PP		 4349 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4350 if (err)
4351 goto unbind;
4352
32f69e4b
DJ		 4353 return true;
4354
4355unbind:
4356 mlx5_ib_unbind_slave_port(ibdev, mpi);
4357 return false;
4358}
4359
4360static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4361{
4362 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4363 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4364 port_num + 1);
4365 struct mlx5_ib_multiport_info *mpi;
4366 int err;
4367 int i;
4368
4369 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4370 return 0;
4371
4372 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4373 &dev->sys_image_guid);
4374 if (err)
4375 return err;
4376
4377 err = mlx5_nic_vport_enable_roce(dev->mdev);
4378 if (err)
4379 return err;
4380
4381 mutex_lock(&mlx5_ib_multiport_mutex);
4382 for (i = 0; i < dev->num_ports; i++) {
4383 bool bound = false;
4384
4385 /* build a stub multiport info struct for the native port. */
4386 if (i == port_num) {
4387 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4388 if (!mpi) {
4389 mutex_unlock(&mlx5_ib_multiport_mutex);
4390 mlx5_nic_vport_disable_roce(dev->mdev);
4391 return -ENOMEM;
4392 }
4393
4394 mpi->is_master = true;
4395 mpi->mdev = dev->mdev;
4396 mpi->sys_image_guid = dev->sys_image_guid;
4397 dev->port[i].mp.mpi = mpi;
4398 mpi->ibdev = dev;
4399 mpi = NULL;
4400 continue;
4401 }
4402
4403 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4404 list) {
4405 if (dev->sys_image_guid == mpi->sys_image_guid &&
4406 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4407 bound = mlx5_ib_bind_slave_port(dev, mpi);
4408 }
4409
4410 if (bound) {
4411 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4412 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4413 list_del(&mpi->list);
4414 break;
4415 }
4416 }
4417 if (!bound) {
4418 get_port_caps(dev, i + 1);
4419 mlx5_ib_dbg(dev, "no free port found for port %d\n",
4420 i + 1);
4421 }
4422 }
4423
4424 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4425 mutex_unlock(&mlx5_ib_multiport_mutex);
4426 return err;
4427}
4428
4429static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4430{
4431 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4432 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4433 port_num + 1);
4434 int i;
4435
4436 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4437 return;
4438
4439 mutex_lock(&mlx5_ib_multiport_mutex);
4440 for (i = 0; i < dev->num_ports; i++) {
4441 if (dev->port[i].mp.mpi) {
4442 /* Destroy the native port stub */
4443 if (i == port_num) {
4444 kfree(dev->port[i].mp.mpi);
4445 dev->port[i].mp.mpi = NULL;
4446 } else {
4447 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4448 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4449 }
4450 }
4451 }
4452
4453 mlx5_ib_dbg(dev, "removing from devlist\n");
4454 list_del(&dev->ib_dev_list);
4455 mutex_unlock(&mlx5_ib_multiport_mutex);
4456
4457 mlx5_nic_vport_disable_roce(dev->mdev);
4458}
4459
16c1975f 4460static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 4461{
32f69e4b 4462 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 4463#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4464 cleanup_srcu_struct(&dev->mr_srcu);
4465#endif
16c1975f
MB		 4466 kfree(dev->port);
4467}
4468
4469static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
4470{
4471 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 4472 const char *name;
e126ba97 4473 int err;
32f69e4b 4474 int i;
e126ba97 4475
508562d6 4476 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 4477 GFP_KERNEL);
4478 if (!dev->port)
16c1975f 4479 return -ENOMEM;
0837e86a 4480
32f69e4b
DJ		 4481 for (i = 0; i < dev->num_ports; i++) {
4482 spin_lock_init(&dev->port[i].mp.mpi_lock);
4483 rwlock_init(&dev->roce[i].netdev_lock);
4484 }
4485
4486 err = mlx5_ib_init_multiport_master(dev);
e126ba97 4487 if (err)
0837e86a 4488 goto err_free_port;
e126ba97 4489
32f69e4b
DJ		 4490 if (!mlx5_core_mp_enabled(mdev)) {
4491 int i;
4492
4493 for (i = 1; i <= dev->num_ports; i++) {
4494 err = get_port_caps(dev, i);
4495 if (err)
4496 break;
4497 }
4498 } else {
4499 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
4500 }
4501 if (err)
4502 goto err_mp;
4503
1b5daf11
MD		 4504 if (mlx5_use_mad_ifc(dev))
4505 get_ext_port_caps(dev);
e126ba97 4506
4babcf97
AH		 4507 if (!mlx5_lag_is_active(mdev))
4508 name = "mlx5_%d";
4509 else
4510 name = "mlx5_bond_%d";
4511
4512 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 4513 dev->ib_dev.owner = THIS_MODULE;
4514 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 4515 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 4516 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 4517 dev->ib_dev.num_comp_vectors =
4518 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 4519 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 4520
3cc297db
MB		 4521 mutex_init(&dev->flow_db.lock);
4522 mutex_init(&dev->cap_mask_mutex);
4523 INIT_LIST_HEAD(&dev->qp_list);
4524 spin_lock_init(&dev->reset_flow_resource_lock);
4525
4526#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4527 err = init_srcu_struct(&dev->mr_srcu);
4528 if (err)
4529 goto err_free_port;
4530#endif
4531
16c1975f 4532 return 0;
32f69e4b
DJ		 4533err_mp:
4534 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 4535
4536err_free_port:
4537 kfree(dev->port);
4538
4539 return -ENOMEM;
4540}
4541
4542static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4543{
4544 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 4545 int err;
4546
e126ba97
EC		 4547 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
4548 dev->ib_dev.uverbs_cmd_mask =
4549 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
4550 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
4551 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
4552 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
4553 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 4554 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
4555 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 4556 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 4557 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 4558 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
4559 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4560 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
4561 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
4562 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
4563 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
4564 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
4565 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
4566 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
4567 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
4568 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
4569 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
4570 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
4571 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
4572 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
4573 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
4574 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 4575 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 4576 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
4577 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 4578 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 4579 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
4580 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 4581
4582 dev->ib_dev.query_device = mlx5_ib_query_device;
4583 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 4584 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 4585 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 4586 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4587 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 4588 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4589 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4590 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4591 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4592 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4593 dev->ib_dev.mmap = mlx5_ib_mmap;
4594 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4595 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4596 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4597 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4598 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4599 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4600 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4601 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4602 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4603 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4604 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4605 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4606 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4607 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4608 dev->ib_dev.post_send = mlx5_ib_post_send;
4609 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4610 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4611 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4612 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4613 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4614 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4615 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4616 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4617 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 4618 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 4619 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4620 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4621 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4622 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 4623 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 4624 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 4625 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 4626 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 4627 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 4628 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 4629 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 4630 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 4631
eff901d3
EC		 4632 if (mlx5_core_is_pf(mdev)) {
4633 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4634 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4635 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4636 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4637 }
e126ba97 4638
7c2344c3
MG		 4639 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4640
6e8484c5
MG		 4641 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4642
d2370e0a
MB		 4643 if (MLX5_CAP_GEN(mdev, imaicl)) {
4644 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4645 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4646 dev->ib_dev.uverbs_cmd_mask |=
4647 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4648 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4649 }
4650
938fe83c 4651 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 4652 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4653 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4654 dev->ib_dev.uverbs_cmd_mask |=
4655 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4656 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4657 }
4658
81e30880
YH		 4659 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4660 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4661 dev->ib_dev.uverbs_ex_cmd_mask |=
4662 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4663 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4664
e126ba97
EC		 4665 err = init_node_data(dev);
4666 if (err)
16c1975f 4667 return err;
e126ba97 4668
c8b89924
MB		 4669 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4670 MLX5_CAP_GEN(dev->mdev, disable_local_lb))
4671 mutex_init(&dev->lb_mutex);
4672
16c1975f
MB		 4673 return 0;
4674}
4675
4676static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
4677{
4678 struct mlx5_core_dev *mdev = dev->mdev;
4679 enum rdma_link_layer ll;
4680 int port_type_cap;
32f69e4b 4681 u8 port_num;
16c1975f 4682 int err;
7fd8aefb 4683 int i;
16c1975f 4684
32f69e4b 4685 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 4686 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4687 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4688
fc24fc5e 4689 if (ll == IB_LINK_LAYER_ETHERNET) {
7fd8aefb 4690 for (i = 0; i < dev->num_ports; i++) {
7fd8aefb
DJ		 4691 dev->roce[i].dev = dev;
4692 dev->roce[i].native_port_num = i + 1;
4693 dev->roce[i].last_port_state = IB_PORT_DOWN;
4694 }
4695
c11a226a
MB		 4696 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
4697 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4698 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4699 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
4700 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4701 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4702 dev->ib_dev.uverbs_ex_cmd_mask |=
4703 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4704 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4705 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4706 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4707 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
7fd8aefb 4708 err = mlx5_enable_eth(dev, port_num);
fc24fc5e 4709 if (err)
16c1975f 4710 return err;
fc24fc5e
AS		 4711 }
4712
16c1975f
MB		 4713 return 0;
4714}
e126ba97 4715
16c1975f
MB		 4716static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
4717{
4718 struct mlx5_core_dev *mdev = dev->mdev;
4719 enum rdma_link_layer ll;
4720 int port_type_cap;
32f69e4b 4721 u8 port_num;
e126ba97 4722
32f69e4b 4723 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 4724 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4725 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4726
4727 if (ll == IB_LINK_LAYER_ETHERNET) {
4728 mlx5_disable_eth(dev);
7fd8aefb 4729 mlx5_remove_netdev_notifier(dev, port_num);
45bded2c 4730 }
16c1975f 4731}
6aec21f6 4732
16c1975f
MB		 4733static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
4734{
4735 return create_dev_resources(&dev->devr);
4736}
4737
4738static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
4739{
4740 destroy_dev_resources(&dev->devr);
4741}
4742
4743static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
4744{
07321b3c
MB		 4745 mlx5_ib_internal_fill_odp_caps(dev);
4746
16c1975f
MB		 4747 return mlx5_ib_odp_init_one(dev);
4748}
4a2da0b8 4749
16c1975f
MB		 4750static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
4751{
5e1e7612
MB		 4752 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4753 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4754 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4755
4756 return mlx5_ib_alloc_counters(dev);
4757 }
16c1975f
MB		 4758
4759 return 0;
4760}
4761
4762static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
4763{
4764 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4765 mlx5_ib_dealloc_counters(dev);
4766}
4767
4768static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4769{
a9e546e7
PP		 4770 return mlx5_ib_init_cong_debugfs(dev,
4771 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 4772}
4773
4774static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4775{
a9e546e7
PP		 4776 mlx5_ib_cleanup_cong_debugfs(dev,
4777 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 4778}
4779
4780static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4781{
5fe9dec0
EC		 4782 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4783 if (!dev->mdev->priv.uar)
16c1975f
MB		 4784 return -ENOMEM;
4785 return 0;
4786}
4787
4788static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4789{
4790 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4791}
4792
4793static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4794{
4795 int err;
5fe9dec0
EC		 4796
4797 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4798 if (err)
16c1975f 4799 return err;
5fe9dec0
EC		 4800
4801 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4802 if (err)
16c1975f 4803 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 4804
16c1975f
MB		 4805 return err;
4806}
0837e86a 4807
16c1975f
MB		 4808static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4809{
4810 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4811 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4812}
e126ba97 4813
16c1975f
MB		 4814static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4815{
4816 return ib_register_device(&dev->ib_dev, NULL);
4817}
4818
4819static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4820{
4821 ib_unregister_device(&dev->ib_dev);
4822}
4823
4824static int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev *dev)
4825{
4826 return create_umr_res(dev);
4827}
4828
4829static void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev *dev)
4830{
4831 destroy_umrc_res(dev);
4832}
4833
4834static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4835{
03404e8a
MG		 4836 init_delay_drop(dev);
4837
16c1975f
MB		 4838 return 0;
4839}
4840
4841static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4842{
4843 cancel_delay_drop(dev);
4844}
4845
4846static int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
4847{
4848 int err;
4849 int i;
4850
e126ba97 4851 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 4852 err = device_create_file(&dev->ib_dev.dev,
4853 mlx5_class_attributes[i]);
4854 if (err)
16c1975f 4855 return err;
e126ba97
EC		 4856 }
4857
16c1975f
MB		 4858 return 0;
4859}
4860
16c1975f
MB		 4861static void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4862 const struct mlx5_ib_profile *profile,
4863 int stage)
4864{
4865 /* Number of stages to cleanup */
4866 while (stage) {
4867 stage--;
4868 if (profile->stage[stage].cleanup)
4869 profile->stage[stage].cleanup(dev);
4870 }
e126ba97 4871
16c1975f
MB		 4872 ib_dealloc_device((struct ib_device *)dev);
4873}
e126ba97 4874
32f69e4b
DJ		 4875static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
4876
16c1975f
MB		 4877static void *__mlx5_ib_add(struct mlx5_core_dev *mdev,
4878 const struct mlx5_ib_profile *profile)
4879{
4880 struct mlx5_ib_dev *dev;
4881 int err;
4882 int i;
e126ba97 4883
16c1975f 4884 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 4885
16c1975f
MB		 4886 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
4887 if (!dev)
4888 return NULL;
5fe9dec0 4889
16c1975f 4890 dev->mdev = mdev;
32f69e4b
DJ		 4891 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4892 MLX5_CAP_GEN(mdev, num_vhca_ports));
5fe9dec0 4893
16c1975f
MB		 4894 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4895 if (profile->stage[i].init) {
4896 err = profile->stage[i].init(dev);
4897 if (err)
4898 goto err_out;
4899 }
4900 }
0837e86a 4901
16c1975f
MB		 4902 dev->profile = profile;
4903 dev->ib_active = true;
6aec21f6 4904
16c1975f 4905 return dev;
e126ba97 4906
16c1975f
MB		 4907err_out:
4908 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 4909
16c1975f
MB		 4910 return NULL;
4911}
0837e86a 4912
16c1975f
MB		 4913static const struct mlx5_ib_profile pf_profile = {
4914 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4915 mlx5_ib_stage_init_init,
4916 mlx5_ib_stage_init_cleanup),
4917 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4918 mlx5_ib_stage_caps_init,
4919 NULL),
4920 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4921 mlx5_ib_stage_roce_init,
4922 mlx5_ib_stage_roce_cleanup),
4923 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4924 mlx5_ib_stage_dev_res_init,
4925 mlx5_ib_stage_dev_res_cleanup),
4926 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4927 mlx5_ib_stage_odp_init,
3cc297db 4928 NULL),
16c1975f
MB		 4929 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4930 mlx5_ib_stage_counters_init,
4931 mlx5_ib_stage_counters_cleanup),
4932 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4933 mlx5_ib_stage_cong_debugfs_init,
4934 mlx5_ib_stage_cong_debugfs_cleanup),
4935 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4936 mlx5_ib_stage_uar_init,
4937 mlx5_ib_stage_uar_cleanup),
4938 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4939 mlx5_ib_stage_bfrag_init,
4940 mlx5_ib_stage_bfrag_cleanup),
4941 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4942 mlx5_ib_stage_ib_reg_init,
4943 mlx5_ib_stage_ib_reg_cleanup),
4944 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES,
4945 mlx5_ib_stage_umr_res_init,
4946 mlx5_ib_stage_umr_res_cleanup),
4947 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4948 mlx5_ib_stage_delay_drop_init,
4949 mlx5_ib_stage_delay_drop_cleanup),
4950 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
4951 mlx5_ib_stage_class_attr_init,
4952 NULL),
16c1975f 4953};
e126ba97 4954
32f69e4b
DJ		 4955static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
4956{
4957 struct mlx5_ib_multiport_info *mpi;
4958 struct mlx5_ib_dev *dev;
4959 bool bound = false;
4960 int err;
4961
4962 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4963 if (!mpi)
4964 return NULL;
4965
4966 mpi->mdev = mdev;
4967
4968 err = mlx5_query_nic_vport_system_image_guid(mdev,
4969 &mpi->sys_image_guid);
4970 if (err) {
4971 kfree(mpi);
4972 return NULL;
4973 }
4974
4975 mutex_lock(&mlx5_ib_multiport_mutex);
4976 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4977 if (dev->sys_image_guid == mpi->sys_image_guid)
4978 bound = mlx5_ib_bind_slave_port(dev, mpi);
4979
4980 if (bound) {
4981 rdma_roce_rescan_device(&dev->ib_dev);
4982 break;
4983 }
4984 }
4985
4986 if (!bound) {
4987 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4988 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
4989 } else {
4990 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
4991 }
4992 mutex_unlock(&mlx5_ib_multiport_mutex);
4993
4994 return mpi;
4995}
4996
16c1975f
MB		 4997static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
4998{
32f69e4b
DJ		 4999 enum rdma_link_layer ll;
5000 int port_type_cap;
5001
5002 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5003 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5004
5005 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5006 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5007
5008 return mlx5_ib_add_slave_port(mdev, port_num);
5009 }
5010
16c1975f 5011 return __mlx5_ib_add(mdev, &pf_profile);
e126ba97
EC		 5012}
5013
9603b61d 5014static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 5015{
32f69e4b
DJ		 5016 struct mlx5_ib_multiport_info *mpi;
5017 struct mlx5_ib_dev *dev;
5018
5019 if (mlx5_core_is_mp_slave(mdev)) {
5020 mpi = context;
5021 mutex_lock(&mlx5_ib_multiport_mutex);
5022 if (mpi->ibdev)
5023 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5024 list_del(&mpi->list);
5025 mutex_unlock(&mlx5_ib_multiport_mutex);
5026 return;
5027 }
6aec21f6 5028
32f69e4b 5029 dev = context;
16c1975f 5030 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 5031}
5032
9603b61d
JM		 5033static struct mlx5_interface mlx5_ib_interface = {
5034 .add = mlx5_ib_add,
5035 .remove = mlx5_ib_remove,
5036 .event = mlx5_ib_event,
d9aaed83
AK		 5037#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5038 .pfault = mlx5_ib_pfault,
5039#endif
64613d94 5040 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 5041};
5042
5043static int __init mlx5_ib_init(void)
5044{
6aec21f6
HE		 5045 int err;
5046
d69a24e0
DJ		 5047 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5048 if (!mlx5_ib_event_wq)
5049 return -ENOMEM;
5050
81713d37 5051 mlx5_ib_odp_init();
9603b61d 5052
6aec21f6 5053 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 5054
6aec21f6 5055 return err;
e126ba97
EC		 5056}
5057
5058static void __exit mlx5_ib_cleanup(void)
5059{
9603b61d 5060 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 5061 destroy_workqueue(mlx5_ib_event_wq);
e126ba97
EC		 5062}
5063
5064module_init(mlx5_ib_init);
5065module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)