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net/mlx5: Unify and improve command interface
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
7c2344c3 45#include <linux/delay.h>
e126ba97 46#include <rdma/ib_user_verbs.h>
3f89a643 47#include <rdma/ib_addr.h>
2811ba51 48#include <rdma/ib_cache.h>
ada68c31 49#include <linux/mlx5/port.h>
1b5daf11 50#include <linux/mlx5/vport.h>
7c2344c3 51#include <linux/list.h>
e126ba97
EC		 52#include <rdma/ib_smi.h>
53#include <rdma/ib_umem.h>
038d2ef8
MG		 54#include <linux/in.h>
55#include <linux/etherdevice.h>
56#include <linux/mlx5/fs.h>
e126ba97
EC		 57#include "user.h"
58#include "mlx5_ib.h"
59
60#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 61#define DRIVER_VERSION "2.2-1"
62#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 63
64MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
65MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
66MODULE_LICENSE("Dual BSD/GPL");
67MODULE_VERSION(DRIVER_VERSION);
68
9603b61d
JM		 69static int deprecated_prof_sel = 2;
70module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
71MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 72
73static char mlx5_version[] =
74 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
75 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
76
da7525d2
EBE		 77enum {
78 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
79};
80
1b5daf11 81static enum rdma_link_layer
ebd61f68 82mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 83{
ebd61f68 84 switch (port_type_cap) {
1b5daf11
MD		 85 case MLX5_CAP_PORT_TYPE_IB:
86 return IB_LINK_LAYER_INFINIBAND;
87 case MLX5_CAP_PORT_TYPE_ETH:
88 return IB_LINK_LAYER_ETHERNET;
89 default:
90 return IB_LINK_LAYER_UNSPECIFIED;
91 }
92}
93
ebd61f68
AS		 94static enum rdma_link_layer
95mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
96{
97 struct mlx5_ib_dev *dev = to_mdev(device);
98 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
99
100 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
101}
102
fc24fc5e
AS		 103static int mlx5_netdev_event(struct notifier_block *this,
104 unsigned long event, void *ptr)
105{
106 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
107 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
108 roce.nb);
109
110 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
111 return NOTIFY_DONE;
112
113 write_lock(&ibdev->roce.netdev_lock);
114 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
115 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
116 write_unlock(&ibdev->roce.netdev_lock);
117
118 return NOTIFY_DONE;
119}
120
121static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
122 u8 port_num)
123{
124 struct mlx5_ib_dev *ibdev = to_mdev(device);
125 struct net_device *ndev;
126
127 /* Ensure ndev does not disappear before we invoke dev_hold()
128 */
129 read_lock(&ibdev->roce.netdev_lock);
130 ndev = ibdev->roce.netdev;
131 if (ndev)
132 dev_hold(ndev);
133 read_unlock(&ibdev->roce.netdev_lock);
134
135 return ndev;
136}
137
3f89a643
AS		 138static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
139 struct ib_port_attr *props)
140{
141 struct mlx5_ib_dev *dev = to_mdev(device);
142 struct net_device *ndev;
143 enum ib_mtu ndev_ib_mtu;
c876a1b7 144 u16 qkey_viol_cntr;
3f89a643
AS		 145
146 memset(props, 0, sizeof(*props));
147
148 props->port_cap_flags |= IB_PORT_CM_SUP;
149 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
150
151 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
152 roce_address_table_size);
153 props->max_mtu = IB_MTU_4096;
154 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
155 props->pkey_tbl_len = 1;
156 props->state = IB_PORT_DOWN;
157 props->phys_state = 3;
158
c876a1b7
LR		 159 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
160 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 161
162 ndev = mlx5_ib_get_netdev(device, port_num);
163 if (!ndev)
164 return 0;
165
166 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
167 props->state = IB_PORT_ACTIVE;
168 props->phys_state = 5;
169 }
170
171 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
172
173 dev_put(ndev);
174
175 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
176
177 props->active_width = IB_WIDTH_4X; /* TODO */
178 props->active_speed = IB_SPEED_QDR; /* TODO */
179
180 return 0;
181}
182
3cca2606
AS		 183static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
184 const struct ib_gid_attr *attr,
185 void *mlx5_addr)
186{
187#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
188 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
189 source_l3_address);
190 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
191 source_mac_47_32);
192
193 if (!gid)
194 return;
195
196 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
197
198 if (is_vlan_dev(attr->ndev)) {
199 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
200 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
201 }
202
203 switch (attr->gid_type) {
204 case IB_GID_TYPE_IB:
205 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
206 break;
207 case IB_GID_TYPE_ROCE_UDP_ENCAP:
208 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
209 break;
210
211 default:
212 WARN_ON(true);
213 }
214
215 if (attr->gid_type != IB_GID_TYPE_IB) {
216 if (ipv6_addr_v4mapped((void *)gid))
217 MLX5_SET_RA(mlx5_addr, roce_l3_type,
218 MLX5_ROCE_L3_TYPE_IPV4);
219 else
220 MLX5_SET_RA(mlx5_addr, roce_l3_type,
221 MLX5_ROCE_L3_TYPE_IPV6);
222 }
223
224 if ((attr->gid_type == IB_GID_TYPE_IB) ||
225 !ipv6_addr_v4mapped((void *)gid))
226 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
227 else
228 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
229}
230
231static int set_roce_addr(struct ib_device *device, u8 port_num,
232 unsigned int index,
233 const union ib_gid *gid,
234 const struct ib_gid_attr *attr)
235{
c4f287c4
SM		 236 struct mlx5_ib_dev *dev = to_mdev(device);
237 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
238 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
3cca2606
AS		 239 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
240 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
241
242 if (ll != IB_LINK_LAYER_ETHERNET)
243 return -EINVAL;
244
3cca2606
AS		 245 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
246
247 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
248 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
3cca2606
AS		 249 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
250}
251
252static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
253 unsigned int index, const union ib_gid *gid,
254 const struct ib_gid_attr *attr,
255 __always_unused void **context)
256{
257 return set_roce_addr(device, port_num, index, gid, attr);
258}
259
260static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
261 unsigned int index, __always_unused void **context)
262{
263 return set_roce_addr(device, port_num, index, NULL, NULL);
264}
265
2811ba51
AS		 266__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
267 int index)
268{
269 struct ib_gid_attr attr;
270 union ib_gid gid;
271
272 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
273 return 0;
274
275 if (!attr.ndev)
276 return 0;
277
278 dev_put(attr.ndev);
279
280 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
281 return 0;
282
283 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
284}
285
1b5daf11
MD		 286static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
287{
d603c809 288 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
1b5daf11
MD		 289}
290
291enum {
292 MLX5_VPORT_ACCESS_METHOD_MAD,
293 MLX5_VPORT_ACCESS_METHOD_HCA,
294 MLX5_VPORT_ACCESS_METHOD_NIC,
295};
296
297static int mlx5_get_vport_access_method(struct ib_device *ibdev)
298{
299 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
300 return MLX5_VPORT_ACCESS_METHOD_MAD;
301
ebd61f68 302 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 303 IB_LINK_LAYER_ETHERNET)
304 return MLX5_VPORT_ACCESS_METHOD_NIC;
305
306 return MLX5_VPORT_ACCESS_METHOD_HCA;
307}
308
da7525d2
EBE		 309static void get_atomic_caps(struct mlx5_ib_dev *dev,
310 struct ib_device_attr *props)
311{
312 u8 tmp;
313 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
314 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
315 u8 atomic_req_8B_endianness_mode =
316 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
317
318 /* Check if HW supports 8 bytes standard atomic operations and capable
319 * of host endianness respond
320 */
321 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
322 if (((atomic_operations & tmp) == tmp) &&
323 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
324 (atomic_req_8B_endianness_mode)) {
325 props->atomic_cap = IB_ATOMIC_HCA;
326 } else {
327 props->atomic_cap = IB_ATOMIC_NONE;
328 }
329}
330
1b5daf11
MD		 331static int mlx5_query_system_image_guid(struct ib_device *ibdev,
332 __be64 *sys_image_guid)
333{
334 struct mlx5_ib_dev *dev = to_mdev(ibdev);
335 struct mlx5_core_dev *mdev = dev->mdev;
336 u64 tmp;
337 int err;
338
339 switch (mlx5_get_vport_access_method(ibdev)) {
340 case MLX5_VPORT_ACCESS_METHOD_MAD:
341 return mlx5_query_mad_ifc_system_image_guid(ibdev,
342 sys_image_guid);
343
344 case MLX5_VPORT_ACCESS_METHOD_HCA:
345 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 346 break;
347
348 case MLX5_VPORT_ACCESS_METHOD_NIC:
349 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
350 break;
1b5daf11
MD		 351
352 default:
353 return -EINVAL;
354 }
3f89a643
AS		 355
356 if (!err)
357 *sys_image_guid = cpu_to_be64(tmp);
358
359 return err;
360
1b5daf11
MD		 361}
362
363static int mlx5_query_max_pkeys(struct ib_device *ibdev,
364 u16 *max_pkeys)
365{
366 struct mlx5_ib_dev *dev = to_mdev(ibdev);
367 struct mlx5_core_dev *mdev = dev->mdev;
368
369 switch (mlx5_get_vport_access_method(ibdev)) {
370 case MLX5_VPORT_ACCESS_METHOD_MAD:
371 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
372
373 case MLX5_VPORT_ACCESS_METHOD_HCA:
374 case MLX5_VPORT_ACCESS_METHOD_NIC:
375 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
376 pkey_table_size));
377 return 0;
378
379 default:
380 return -EINVAL;
381 }
382}
383
384static int mlx5_query_vendor_id(struct ib_device *ibdev,
385 u32 *vendor_id)
386{
387 struct mlx5_ib_dev *dev = to_mdev(ibdev);
388
389 switch (mlx5_get_vport_access_method(ibdev)) {
390 case MLX5_VPORT_ACCESS_METHOD_MAD:
391 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
392
393 case MLX5_VPORT_ACCESS_METHOD_HCA:
394 case MLX5_VPORT_ACCESS_METHOD_NIC:
395 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
396
397 default:
398 return -EINVAL;
399 }
400}
401
402static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
403 __be64 *node_guid)
404{
405 u64 tmp;
406 int err;
407
408 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
409 case MLX5_VPORT_ACCESS_METHOD_MAD:
410 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
411
412 case MLX5_VPORT_ACCESS_METHOD_HCA:
413 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 414 break;
415
416 case MLX5_VPORT_ACCESS_METHOD_NIC:
417 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
418 break;
1b5daf11
MD		 419
420 default:
421 return -EINVAL;
422 }
3f89a643
AS		 423
424 if (!err)
425 *node_guid = cpu_to_be64(tmp);
426
427 return err;
1b5daf11
MD		 428}
429
430struct mlx5_reg_node_desc {
431 u8 desc[64];
432};
433
434static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
435{
436 struct mlx5_reg_node_desc in;
437
438 if (mlx5_use_mad_ifc(dev))
439 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
440
441 memset(&in, 0, sizeof(in));
442
443 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
444 sizeof(struct mlx5_reg_node_desc),
445 MLX5_REG_NODE_DESC, 0, 0);
446}
447
e126ba97 448static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 449 struct ib_device_attr *props,
450 struct ib_udata *uhw)
e126ba97
EC		 451{
452 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 453 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 454 int err = -ENOMEM;
455 int max_rq_sg;
456 int max_sq_sg;
e0238a6a 457 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 458 struct mlx5_ib_query_device_resp resp = {};
459 size_t resp_len;
460 u64 max_tso;
e126ba97 461
402ca536
BW		 462 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
463 if (uhw->outlen && uhw->outlen < resp_len)
464 return -EINVAL;
465 else
466 resp.response_length = resp_len;
467
468 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 469 return -EINVAL;
470
1b5daf11
MD		 471 memset(props, 0, sizeof(*props));
472 err = mlx5_query_system_image_guid(ibdev,
473 &props->sys_image_guid);
474 if (err)
475 return err;
e126ba97 476
1b5daf11 477 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 478 if (err)
1b5daf11 479 return err;
e126ba97 480
1b5daf11
MD		 481 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
482 if (err)
483 return err;
e126ba97 484
9603b61d
JM		 485 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
486 (fw_rev_min(dev->mdev) << 16) |
487 fw_rev_sub(dev->mdev);
e126ba97
EC		 488 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
489 IB_DEVICE_PORT_ACTIVE_EVENT |
490 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 491 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 492
493 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 494 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 495 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 496 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 497 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 498 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 499 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 500 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 501 if (MLX5_CAP_GEN(mdev, imaicl)) {
502 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
503 IB_DEVICE_MEM_WINDOW_TYPE_2B;
504 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 505 /* We support 'Gappy' memory registration too */
506 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 507 }
e126ba97 508 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 509 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 510 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
511 /* At this stage no support for signature handover */
512 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
513 IB_PROT_T10DIF_TYPE_2 |
514 IB_PROT_T10DIF_TYPE_3;
515 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
516 IB_GUARD_T10DIF_CSUM;
517 }
938fe83c 518 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 519 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 520
402ca536
BW		 521 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
522 if (MLX5_CAP_ETH(mdev, csum_cap))
88115fe7
BW		 523 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
524
402ca536
BW		 525 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
526 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
527 if (max_tso) {
528 resp.tso_caps.max_tso = 1 << max_tso;
529 resp.tso_caps.supported_qpts |=
530 1 << IB_QPT_RAW_PACKET;
531 resp.response_length += sizeof(resp.tso_caps);
532 }
533 }
534 }
535
f0313965
ES		 536 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
537 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
538 props->device_cap_flags |= IB_DEVICE_UD_TSO;
539 }
540
cff5a0f3
MD		 541 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
542 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
543 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
544
da6d6ba3
MG		 545 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
546 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
547
1b5daf11
MD		 548 props->vendor_part_id = mdev->pdev->device;
549 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 550
551 props->max_mr_size = ~0ull;
e0238a6a 552 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 553 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
554 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
555 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
556 sizeof(struct mlx5_wqe_data_seg);
557 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
558 sizeof(struct mlx5_wqe_ctrl_seg)) /
559 sizeof(struct mlx5_wqe_data_seg);
e126ba97 560 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 561 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 562 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 563 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 564 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
565 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
566 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
567 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
568 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
569 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
570 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 571 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 572 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 573 props->max_fast_reg_page_list_len =
574 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 575 get_atomic_caps(dev, props);
81bea28f 576 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 577 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
578 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 579 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
580 props->max_mcast_grp;
581 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 582 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
583 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 584
8cdd312c 585#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 586 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 587 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
588 props->odp_caps = dev->odp_caps;
589#endif
590
051f2630
LR		 591 if (MLX5_CAP_GEN(mdev, cd))
592 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
593
eff901d3
EC		 594 if (!mlx5_core_is_pf(mdev))
595 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
596
402ca536
BW		 597 if (uhw->outlen) {
598 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
599
600 if (err)
601 return err;
602 }
603
1b5daf11 604 return 0;
e126ba97
EC		 605}
606
1b5daf11
MD		 607enum mlx5_ib_width {
608 MLX5_IB_WIDTH_1X = 1 << 0,
609 MLX5_IB_WIDTH_2X = 1 << 1,
610 MLX5_IB_WIDTH_4X = 1 << 2,
611 MLX5_IB_WIDTH_8X = 1 << 3,
612 MLX5_IB_WIDTH_12X = 1 << 4
613};
614
615static int translate_active_width(struct ib_device *ibdev, u8 active_width,
616 u8 *ib_width)
e126ba97
EC		 617{
618 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 619 int err = 0;
620
621 if (active_width & MLX5_IB_WIDTH_1X) {
622 *ib_width = IB_WIDTH_1X;
623 } else if (active_width & MLX5_IB_WIDTH_2X) {
624 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
625 (int)active_width);
626 err = -EINVAL;
627 } else if (active_width & MLX5_IB_WIDTH_4X) {
628 *ib_width = IB_WIDTH_4X;
629 } else if (active_width & MLX5_IB_WIDTH_8X) {
630 *ib_width = IB_WIDTH_8X;
631 } else if (active_width & MLX5_IB_WIDTH_12X) {
632 *ib_width = IB_WIDTH_12X;
633 } else {
634 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
635 (int)active_width);
636 err = -EINVAL;
e126ba97
EC		 637 }
638
1b5daf11
MD		 639 return err;
640}
e126ba97 641
1b5daf11
MD		 642static int mlx5_mtu_to_ib_mtu(int mtu)
643{
644 switch (mtu) {
645 case 256: return 1;
646 case 512: return 2;
647 case 1024: return 3;
648 case 2048: return 4;
649 case 4096: return 5;
650 default:
651 pr_warn("invalid mtu\n");
652 return -1;
e126ba97 653 }
1b5daf11 654}
e126ba97 655
1b5daf11
MD		 656enum ib_max_vl_num {
657 __IB_MAX_VL_0 = 1,
658 __IB_MAX_VL_0_1 = 2,
659 __IB_MAX_VL_0_3 = 3,
660 __IB_MAX_VL_0_7 = 4,
661 __IB_MAX_VL_0_14 = 5,
662};
e126ba97 663
1b5daf11
MD		 664enum mlx5_vl_hw_cap {
665 MLX5_VL_HW_0 = 1,
666 MLX5_VL_HW_0_1 = 2,
667 MLX5_VL_HW_0_2 = 3,
668 MLX5_VL_HW_0_3 = 4,
669 MLX5_VL_HW_0_4 = 5,
670 MLX5_VL_HW_0_5 = 6,
671 MLX5_VL_HW_0_6 = 7,
672 MLX5_VL_HW_0_7 = 8,
673 MLX5_VL_HW_0_14 = 15
674};
e126ba97 675
1b5daf11
MD		 676static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
677 u8 *max_vl_num)
678{
679 switch (vl_hw_cap) {
680 case MLX5_VL_HW_0:
681 *max_vl_num = __IB_MAX_VL_0;
682 break;
683 case MLX5_VL_HW_0_1:
684 *max_vl_num = __IB_MAX_VL_0_1;
685 break;
686 case MLX5_VL_HW_0_3:
687 *max_vl_num = __IB_MAX_VL_0_3;
688 break;
689 case MLX5_VL_HW_0_7:
690 *max_vl_num = __IB_MAX_VL_0_7;
691 break;
692 case MLX5_VL_HW_0_14:
693 *max_vl_num = __IB_MAX_VL_0_14;
694 break;
e126ba97 695
1b5daf11
MD		 696 default:
697 return -EINVAL;
e126ba97 698 }
e126ba97 699
1b5daf11 700 return 0;
e126ba97
EC		 701}
702
1b5daf11
MD		 703static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
704 struct ib_port_attr *props)
e126ba97 705{
1b5daf11
MD		 706 struct mlx5_ib_dev *dev = to_mdev(ibdev);
707 struct mlx5_core_dev *mdev = dev->mdev;
708 struct mlx5_hca_vport_context *rep;
046339ea
SM		 709 u16 max_mtu;
710 u16 oper_mtu;
1b5daf11
MD		 711 int err;
712 u8 ib_link_width_oper;
713 u8 vl_hw_cap;
e126ba97 714
1b5daf11
MD		 715 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
716 if (!rep) {
717 err = -ENOMEM;
e126ba97 718 goto out;
e126ba97 719 }
e126ba97 720
1b5daf11 721 memset(props, 0, sizeof(*props));
e126ba97 722
1b5daf11 723 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 724 if (err)
725 goto out;
726
1b5daf11
MD		 727 props->lid = rep->lid;
728 props->lmc = rep->lmc;
729 props->sm_lid = rep->sm_lid;
730 props->sm_sl = rep->sm_sl;
731 props->state = rep->vport_state;
732 props->phys_state = rep->port_physical_state;
733 props->port_cap_flags = rep->cap_mask1;
734 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
735 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
736 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
737 props->bad_pkey_cntr = rep->pkey_violation_counter;
738 props->qkey_viol_cntr = rep->qkey_violation_counter;
739 props->subnet_timeout = rep->subnet_timeout;
740 props->init_type_reply = rep->init_type_reply;
eff901d3 741 props->grh_required = rep->grh_required;
e126ba97 742
1b5daf11
MD		 743 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
744 if (err)
e126ba97 745 goto out;
e126ba97 746
1b5daf11
MD		 747 err = translate_active_width(ibdev, ib_link_width_oper,
748 &props->active_width);
749 if (err)
750 goto out;
751 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
752 port);
e126ba97
EC		 753 if (err)
754 goto out;
755
facc9699 756 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 757
1b5daf11 758 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 759
facc9699 760 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 761
1b5daf11 762 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 763
1b5daf11
MD		 764 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
765 if (err)
766 goto out;
e126ba97 767
1b5daf11
MD		 768 err = translate_max_vl_num(ibdev, vl_hw_cap,
769 &props->max_vl_num);
e126ba97 770out:
1b5daf11 771 kfree(rep);
e126ba97
EC		 772 return err;
773}
774
1b5daf11
MD		 775int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
776 struct ib_port_attr *props)
e126ba97 777{
1b5daf11
MD		 778 switch (mlx5_get_vport_access_method(ibdev)) {
779 case MLX5_VPORT_ACCESS_METHOD_MAD:
780 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 781
1b5daf11
MD		 782 case MLX5_VPORT_ACCESS_METHOD_HCA:
783 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 784
3f89a643
AS		 785 case MLX5_VPORT_ACCESS_METHOD_NIC:
786 return mlx5_query_port_roce(ibdev, port, props);
787
1b5daf11
MD		 788 default:
789 return -EINVAL;
790 }
791}
e126ba97 792
1b5daf11
MD		 793static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
794 union ib_gid *gid)
795{
796 struct mlx5_ib_dev *dev = to_mdev(ibdev);
797 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 798
1b5daf11
MD		 799 switch (mlx5_get_vport_access_method(ibdev)) {
800 case MLX5_VPORT_ACCESS_METHOD_MAD:
801 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 802
1b5daf11
MD		 803 case MLX5_VPORT_ACCESS_METHOD_HCA:
804 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
805
806 default:
807 return -EINVAL;
808 }
e126ba97 809
e126ba97
EC		 810}
811
1b5daf11
MD		 812static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
813 u16 *pkey)
814{
815 struct mlx5_ib_dev *dev = to_mdev(ibdev);
816 struct mlx5_core_dev *mdev = dev->mdev;
817
818 switch (mlx5_get_vport_access_method(ibdev)) {
819 case MLX5_VPORT_ACCESS_METHOD_MAD:
820 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
821
822 case MLX5_VPORT_ACCESS_METHOD_HCA:
823 case MLX5_VPORT_ACCESS_METHOD_NIC:
824 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
825 pkey);
826 default:
827 return -EINVAL;
828 }
829}
e126ba97
EC		 830
831static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
832 struct ib_device_modify *props)
833{
834 struct mlx5_ib_dev *dev = to_mdev(ibdev);
835 struct mlx5_reg_node_desc in;
836 struct mlx5_reg_node_desc out;
837 int err;
838
839 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
840 return -EOPNOTSUPP;
841
842 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
843 return 0;
844
845 /*
846 * If possible, pass node desc to FW, so it can generate
847 * a 144 trap. If cmd fails, just ignore.
848 */
849 memcpy(&in, props->node_desc, 64);
9603b61d 850 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 851 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
852 if (err)
853 return err;
854
855 memcpy(ibdev->node_desc, props->node_desc, 64);
856
857 return err;
858}
859
860static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
861 struct ib_port_modify *props)
862{
863 struct mlx5_ib_dev *dev = to_mdev(ibdev);
864 struct ib_port_attr attr;
865 u32 tmp;
866 int err;
867
868 mutex_lock(&dev->cap_mask_mutex);
869
870 err = mlx5_ib_query_port(ibdev, port, &attr);
871 if (err)
872 goto out;
873
874 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
875 ~props->clr_port_cap_mask;
876
9603b61d 877 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 878
879out:
880 mutex_unlock(&dev->cap_mask_mutex);
881 return err;
882}
883
884static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
885 struct ib_udata *udata)
886{
887 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 888 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
889 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 890 struct mlx5_ib_ucontext *context;
891 struct mlx5_uuar_info *uuari;
892 struct mlx5_uar *uars;
c1be5232 893 int gross_uuars;
e126ba97 894 int num_uars;
78c0f98c 895 int ver;
e126ba97
EC		 896 int uuarn;
897 int err;
898 int i;
f241e749 899 size_t reqlen;
a168a41c
MD		 900 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
901 max_cqe_version);
e126ba97
EC		 902
903 if (!dev->ib_active)
904 return ERR_PTR(-EAGAIN);
905
dfbee859
HA		 906 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
907 return ERR_PTR(-EINVAL);
908
78c0f98c
EC		 909 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
910 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
911 ver = 0;
a168a41c 912 else if (reqlen >= min_req_v2)
78c0f98c
EC		 913 ver = 2;
914 else
915 return ERR_PTR(-EINVAL);
916
b368d7cb 917 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 918 if (err)
919 return ERR_PTR(err);
920
b368d7cb 921 if (req.flags)
78c0f98c
EC		 922 return ERR_PTR(-EINVAL);
923
e126ba97
EC		 924 if (req.total_num_uuars > MLX5_MAX_UUARS)
925 return ERR_PTR(-ENOMEM);
926
927 if (req.total_num_uuars == 0)
928 return ERR_PTR(-EINVAL);
929
f72300c5 930 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 931 return ERR_PTR(-EOPNOTSUPP);
932
933 if (reqlen > sizeof(req) &&
934 !ib_is_udata_cleared(udata, sizeof(req),
dfbee859 935 reqlen - sizeof(req)))
b368d7cb
MB		 936 return ERR_PTR(-EOPNOTSUPP);
937
c1be5232
EC		 938 req.total_num_uuars = ALIGN(req.total_num_uuars,
939 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 940 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
941 return ERR_PTR(-EINVAL);
942
c1be5232
EC		 943 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
944 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c 945 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 946 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
947 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
938fe83c
SM		 948 resp.cache_line_size = L1_CACHE_BYTES;
949 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
950 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
951 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
952 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
953 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 954 resp.cqe_version = min_t(__u8,
955 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
956 req.max_cqe_version);
b368d7cb
MB		 957 resp.response_length = min(offsetof(typeof(resp), response_length) +
958 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 959
960 context = kzalloc(sizeof(*context), GFP_KERNEL);
961 if (!context)
962 return ERR_PTR(-ENOMEM);
963
964 uuari = &context->uuari;
965 mutex_init(&uuari->lock);
966 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
967 if (!uars) {
968 err = -ENOMEM;
969 goto out_ctx;
970 }
971
c1be5232 972 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 973 sizeof(*uuari->bitmap),
974 GFP_KERNEL);
975 if (!uuari->bitmap) {
976 err = -ENOMEM;
977 goto out_uar_ctx;
978 }
979 /*
980 * clear all fast path uuars
981 */
c1be5232 982 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 983 uuarn = i & 3;
984 if (uuarn == 2 || uuarn == 3)
985 set_bit(i, uuari->bitmap);
986 }
987
c1be5232 988 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 989 if (!uuari->count) {
990 err = -ENOMEM;
991 goto out_bitmap;
992 }
993
994 for (i = 0; i < num_uars; i++) {
9603b61d 995 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 996 if (err)
997 goto out_count;
998 }
999
b4cfe447
HE		 1000#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1001 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1002#endif
1003
146d2f1a 1004 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1005 err = mlx5_core_alloc_transport_domain(dev->mdev,
1006 &context->tdn);
1007 if (err)
1008 goto out_uars;
1009 }
1010
7c2344c3 1011 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1012 INIT_LIST_HEAD(&context->db_page_list);
1013 mutex_init(&context->db_page_mutex);
1014
1015 resp.tot_uuars = req.total_num_uuars;
938fe83c 1016 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1017
f72300c5
HA		 1018 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1019 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1020
402ca536
BW		 1021 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1022 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1023 resp.response_length += sizeof(resp.cmds_supp_uhw);
1024 }
1025
bc5c6eed
NO		 1026 /*
1027 * We don't want to expose information from the PCI bar that is located
1028 * after 4096 bytes, so if the arch only supports larger pages, let's
1029 * pretend we don't support reading the HCA's core clock. This is also
1030 * forced by mmap function.
1031 */
1032 if (PAGE_SIZE <= 4096 &&
1033 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
b368d7cb
MB		 1034 resp.comp_mask |=
1035 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1036 resp.hca_core_clock_offset =
1037 offsetof(struct mlx5_init_seg, internal_timer_h) %
1038 PAGE_SIZE;
f72300c5 1039 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1040 sizeof(resp.reserved2);
b368d7cb
MB		 1041 }
1042
1043 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1044 if (err)
146d2f1a 1045 goto out_td;
e126ba97 1046
78c0f98c 1047 uuari->ver = ver;
e126ba97
EC		 1048 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1049 uuari->uars = uars;
1050 uuari->num_uars = num_uars;
f72300c5
HA		 1051 context->cqe_version = resp.cqe_version;
1052
e126ba97
EC		 1053 return &context->ibucontext;
1054
146d2f1a 1055out_td:
1056 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1057 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1058
e126ba97
EC		 1059out_uars:
1060 for (i--; i >= 0; i--)
9603b61d 1061 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 1062out_count:
1063 kfree(uuari->count);
1064
1065out_bitmap:
1066 kfree(uuari->bitmap);
1067
1068out_uar_ctx:
1069 kfree(uars);
1070
1071out_ctx:
1072 kfree(context);
1073 return ERR_PTR(err);
1074}
1075
1076static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1077{
1078 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1079 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1080 struct mlx5_uuar_info *uuari = &context->uuari;
1081 int i;
1082
146d2f1a 1083 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1084 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1085
e126ba97 1086 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 1087 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 1088 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1089 }
1090
1091 kfree(uuari->count);
1092 kfree(uuari->bitmap);
1093 kfree(uuari->uars);
1094 kfree(context);
1095
1096 return 0;
1097}
1098
1099static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1100{
9603b61d 1101 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1102}
1103
1104static int get_command(unsigned long offset)
1105{
1106 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1107}
1108
1109static int get_arg(unsigned long offset)
1110{
1111 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1112}
1113
1114static int get_index(unsigned long offset)
1115{
1116 return get_arg(offset);
1117}
1118
7c2344c3
MG		 1119static void mlx5_ib_vma_open(struct vm_area_struct *area)
1120{
1121 /* vma_open is called when a new VMA is created on top of our VMA. This
1122 * is done through either mremap flow or split_vma (usually due to
1123 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1124 * as this VMA is strongly hardware related. Therefore we set the
1125 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1126 * calling us again and trying to do incorrect actions. We assume that
1127 * the original VMA size is exactly a single page, and therefore all
1128 * "splitting" operation will not happen to it.
1129 */
1130 area->vm_ops = NULL;
1131}
1132
1133static void mlx5_ib_vma_close(struct vm_area_struct *area)
1134{
1135 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1136
1137 /* It's guaranteed that all VMAs opened on a FD are closed before the
1138 * file itself is closed, therefore no sync is needed with the regular
1139 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1140 * However need a sync with accessing the vma as part of
1141 * mlx5_ib_disassociate_ucontext.
1142 * The close operation is usually called under mm->mmap_sem except when
1143 * process is exiting.
1144 * The exiting case is handled explicitly as part of
1145 * mlx5_ib_disassociate_ucontext.
1146 */
1147 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1148
1149 /* setting the vma context pointer to null in the mlx5_ib driver's
1150 * private data, to protect a race condition in
1151 * mlx5_ib_disassociate_ucontext().
1152 */
1153 mlx5_ib_vma_priv_data->vma = NULL;
1154 list_del(&mlx5_ib_vma_priv_data->list);
1155 kfree(mlx5_ib_vma_priv_data);
1156}
1157
1158static const struct vm_operations_struct mlx5_ib_vm_ops = {
1159 .open = mlx5_ib_vma_open,
1160 .close = mlx5_ib_vma_close
1161};
1162
1163static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1164 struct mlx5_ib_ucontext *ctx)
1165{
1166 struct mlx5_ib_vma_private_data *vma_prv;
1167 struct list_head *vma_head = &ctx->vma_private_list;
1168
1169 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1170 if (!vma_prv)
1171 return -ENOMEM;
1172
1173 vma_prv->vma = vma;
1174 vma->vm_private_data = vma_prv;
1175 vma->vm_ops = &mlx5_ib_vm_ops;
1176
1177 list_add(&vma_prv->list, vma_head);
1178
1179 return 0;
1180}
1181
1182static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1183{
1184 int ret;
1185 struct vm_area_struct *vma;
1186 struct mlx5_ib_vma_private_data *vma_private, *n;
1187 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1188 struct task_struct *owning_process = NULL;
1189 struct mm_struct *owning_mm = NULL;
1190
1191 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1192 if (!owning_process)
1193 return;
1194
1195 owning_mm = get_task_mm(owning_process);
1196 if (!owning_mm) {
1197 pr_info("no mm, disassociate ucontext is pending task termination\n");
1198 while (1) {
1199 put_task_struct(owning_process);
1200 usleep_range(1000, 2000);
1201 owning_process = get_pid_task(ibcontext->tgid,
1202 PIDTYPE_PID);
1203 if (!owning_process ||
1204 owning_process->state == TASK_DEAD) {
1205 pr_info("disassociate ucontext done, task was terminated\n");
1206 /* in case task was dead need to release the
1207 * task struct.
1208 */
1209 if (owning_process)
1210 put_task_struct(owning_process);
1211 return;
1212 }
1213 }
1214 }
1215
1216 /* need to protect from a race on closing the vma as part of
1217 * mlx5_ib_vma_close.
1218 */
1219 down_read(&owning_mm->mmap_sem);
1220 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1221 list) {
1222 vma = vma_private->vma;
1223 ret = zap_vma_ptes(vma, vma->vm_start,
1224 PAGE_SIZE);
1225 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1226 /* context going to be destroyed, should
1227 * not access ops any more.
1228 */
1229 vma->vm_ops = NULL;
1230 list_del(&vma_private->list);
1231 kfree(vma_private);
1232 }
1233 up_read(&owning_mm->mmap_sem);
1234 mmput(owning_mm);
1235 put_task_struct(owning_process);
1236}
1237
37aa5c36
GL		 1238static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1239{
1240 switch (cmd) {
1241 case MLX5_IB_MMAP_WC_PAGE:
1242 return "WC";
1243 case MLX5_IB_MMAP_REGULAR_PAGE:
1244 return "best effort WC";
1245 case MLX5_IB_MMAP_NC_PAGE:
1246 return "NC";
1247 default:
1248 return NULL;
1249 }
1250}
1251
1252static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1253 struct vm_area_struct *vma,
1254 struct mlx5_ib_ucontext *context)
37aa5c36 1255{
7c2344c3 1256 struct mlx5_uuar_info *uuari = &context->uuari;
37aa5c36
GL		 1257 int err;
1258 unsigned long idx;
1259 phys_addr_t pfn, pa;
1260 pgprot_t prot;
1261
1262 switch (cmd) {
1263 case MLX5_IB_MMAP_WC_PAGE:
1264/* Some architectures don't support WC memory */
1265#if defined(CONFIG_X86)
1266 if (!pat_enabled())
1267 return -EPERM;
1268#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1269 return -EPERM;
1270#endif
1271 /* fall through */
1272 case MLX5_IB_MMAP_REGULAR_PAGE:
1273 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1274 prot = pgprot_writecombine(vma->vm_page_prot);
1275 break;
1276 case MLX5_IB_MMAP_NC_PAGE:
1277 prot = pgprot_noncached(vma->vm_page_prot);
1278 break;
1279 default:
1280 return -EINVAL;
1281 }
1282
1283 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1284 return -EINVAL;
1285
1286 idx = get_index(vma->vm_pgoff);
1287 if (idx >= uuari->num_uars)
1288 return -EINVAL;
1289
1290 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1291 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1292
1293 vma->vm_page_prot = prot;
1294 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1295 PAGE_SIZE, vma->vm_page_prot);
1296 if (err) {
1297 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1298 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1299 return -EAGAIN;
1300 }
1301
1302 pa = pfn << PAGE_SHIFT;
1303 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1304 vma->vm_start, &pa);
1305
7c2344c3 1306 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1307}
1308
e126ba97
EC		 1309static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1310{
1311 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1312 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1313 unsigned long command;
e126ba97
EC		 1314 phys_addr_t pfn;
1315
1316 command = get_command(vma->vm_pgoff);
1317 switch (command) {
37aa5c36
GL		 1318 case MLX5_IB_MMAP_WC_PAGE:
1319 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1320 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1321 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1322
1323 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1324 return -ENOSYS;
1325
d69e3bcf 1326 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1327 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1328 return -EINVAL;
1329
6cbac1e4 1330 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1331 return -EPERM;
1332
1333 /* Don't expose to user-space information it shouldn't have */
1334 if (PAGE_SIZE > 4096)
1335 return -EOPNOTSUPP;
1336
1337 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1338 pfn = (dev->mdev->iseg_base +
1339 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1340 PAGE_SHIFT;
1341 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1342 PAGE_SIZE, vma->vm_page_prot))
1343 return -EAGAIN;
1344
1345 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1346 vma->vm_start,
1347 (unsigned long long)pfn << PAGE_SHIFT);
1348 break;
d69e3bcf 1349
e126ba97
EC		 1350 default:
1351 return -EINVAL;
1352 }
1353
1354 return 0;
1355}
1356
e126ba97
EC		 1357static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1358 struct ib_ucontext *context,
1359 struct ib_udata *udata)
1360{
1361 struct mlx5_ib_alloc_pd_resp resp;
1362 struct mlx5_ib_pd *pd;
1363 int err;
1364
1365 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1366 if (!pd)
1367 return ERR_PTR(-ENOMEM);
1368
9603b61d 1369 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1370 if (err) {
1371 kfree(pd);
1372 return ERR_PTR(err);
1373 }
1374
1375 if (context) {
1376 resp.pdn = pd->pdn;
1377 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1378 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1379 kfree(pd);
1380 return ERR_PTR(-EFAULT);
1381 }
e126ba97
EC		 1382 }
1383
1384 return &pd->ibpd;
1385}
1386
1387static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1388{
1389 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1390 struct mlx5_ib_pd *mpd = to_mpd(pd);
1391
9603b61d 1392 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1393 kfree(mpd);
1394
1395 return 0;
1396}
1397
038d2ef8
MG		 1398static bool outer_header_zero(u32 *match_criteria)
1399{
1400 int size = MLX5_ST_SZ_BYTES(fte_match_param);
1401 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1402 outer_headers);
1403
1404 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1405 outer_headers_c + 1,
1406 size - 1);
1407}
1408
1409static int parse_flow_attr(u32 *match_c, u32 *match_v,
1410 union ib_flow_spec *ib_spec)
1411{
1412 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1413 outer_headers);
1414 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1415 outer_headers);
1416 switch (ib_spec->type) {
1417 case IB_FLOW_SPEC_ETH:
1418 if (ib_spec->size != sizeof(ib_spec->eth))
1419 return -EINVAL;
1420
1421 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1422 dmac_47_16),
1423 ib_spec->eth.mask.dst_mac);
1424 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1425 dmac_47_16),
1426 ib_spec->eth.val.dst_mac);
1427
1428 if (ib_spec->eth.mask.vlan_tag) {
1429 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1430 vlan_tag, 1);
1431 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1432 vlan_tag, 1);
1433
1434 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1435 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1436 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1437 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1438
1439 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1440 first_cfi,
1441 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1442 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1443 first_cfi,
1444 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1445
1446 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1447 first_prio,
1448 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1449 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1450 first_prio,
1451 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1452 }
1453 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1454 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1455 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1456 ethertype, ntohs(ib_spec->eth.val.ether_type));
1457 break;
1458 case IB_FLOW_SPEC_IPV4:
1459 if (ib_spec->size != sizeof(ib_spec->ipv4))
1460 return -EINVAL;
1461
1462 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1463 ethertype, 0xffff);
1464 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1465 ethertype, ETH_P_IP);
1466
1467 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1468 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1469 &ib_spec->ipv4.mask.src_ip,
1470 sizeof(ib_spec->ipv4.mask.src_ip));
1471 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1472 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1473 &ib_spec->ipv4.val.src_ip,
1474 sizeof(ib_spec->ipv4.val.src_ip));
1475 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1476 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1477 &ib_spec->ipv4.mask.dst_ip,
1478 sizeof(ib_spec->ipv4.mask.dst_ip));
1479 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1480 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1481 &ib_spec->ipv4.val.dst_ip,
1482 sizeof(ib_spec->ipv4.val.dst_ip));
1483 break;
026bae0c
MG		 1484 case IB_FLOW_SPEC_IPV6:
1485 if (ib_spec->size != sizeof(ib_spec->ipv6))
1486 return -EINVAL;
1487
1488 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1489 ethertype, 0xffff);
1490 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1491 ethertype, ETH_P_IPV6);
1492
1493 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1494 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1495 &ib_spec->ipv6.mask.src_ip,
1496 sizeof(ib_spec->ipv6.mask.src_ip));
1497 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1498 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1499 &ib_spec->ipv6.val.src_ip,
1500 sizeof(ib_spec->ipv6.val.src_ip));
1501 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1502 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1503 &ib_spec->ipv6.mask.dst_ip,
1504 sizeof(ib_spec->ipv6.mask.dst_ip));
1505 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1506 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1507 &ib_spec->ipv6.val.dst_ip,
1508 sizeof(ib_spec->ipv6.val.dst_ip));
1509 break;
038d2ef8
MG		 1510 case IB_FLOW_SPEC_TCP:
1511 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1512 return -EINVAL;
1513
1514 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1515 0xff);
1516 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1517 IPPROTO_TCP);
1518
1519 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1520 ntohs(ib_spec->tcp_udp.mask.src_port));
1521 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1522 ntohs(ib_spec->tcp_udp.val.src_port));
1523
1524 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1525 ntohs(ib_spec->tcp_udp.mask.dst_port));
1526 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1527 ntohs(ib_spec->tcp_udp.val.dst_port));
1528 break;
1529 case IB_FLOW_SPEC_UDP:
1530 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1531 return -EINVAL;
1532
1533 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1534 0xff);
1535 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1536 IPPROTO_UDP);
1537
1538 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1539 ntohs(ib_spec->tcp_udp.mask.src_port));
1540 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1541 ntohs(ib_spec->tcp_udp.val.src_port));
1542
1543 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1544 ntohs(ib_spec->tcp_udp.mask.dst_port));
1545 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1546 ntohs(ib_spec->tcp_udp.val.dst_port));
1547 break;
1548 default:
1549 return -EINVAL;
1550 }
1551
1552 return 0;
1553}
1554
1555/* If a flow could catch both multicast and unicast packets,
1556 * it won't fall into the multicast flow steering table and this rule
1557 * could steal other multicast packets.
1558 */
1559static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1560{
1561 struct ib_flow_spec_eth *eth_spec;
1562
1563 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1564 ib_attr->size < sizeof(struct ib_flow_attr) +
1565 sizeof(struct ib_flow_spec_eth) ||
1566 ib_attr->num_of_specs < 1)
1567 return false;
1568
1569 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1570 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1571 eth_spec->size != sizeof(*eth_spec))
1572 return false;
1573
1574 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1575 is_multicast_ether_addr(eth_spec->val.dst_mac);
1576}
1577
1578static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1579{
1580 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1581 bool has_ipv4_spec = false;
1582 bool eth_type_ipv4 = true;
1583 unsigned int spec_index;
1584
1585 /* Validate that ethertype is correct */
1586 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1587 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1588 ib_spec->eth.mask.ether_type) {
1589 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1590 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1591 eth_type_ipv4 = false;
1592 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1593 has_ipv4_spec = true;
1594 }
1595 ib_spec = (void *)ib_spec + ib_spec->size;
1596 }
1597 return !has_ipv4_spec || eth_type_ipv4;
1598}
1599
1600static void put_flow_table(struct mlx5_ib_dev *dev,
1601 struct mlx5_ib_flow_prio *prio, bool ft_added)
1602{
1603 prio->refcount -= !!ft_added;
1604 if (!prio->refcount) {
1605 mlx5_destroy_flow_table(prio->flow_table);
1606 prio->flow_table = NULL;
1607 }
1608}
1609
1610static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1611{
1612 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1613 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1614 struct mlx5_ib_flow_handler,
1615 ibflow);
1616 struct mlx5_ib_flow_handler *iter, *tmp;
1617
1618 mutex_lock(&dev->flow_db.lock);
1619
1620 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1621 mlx5_del_flow_rule(iter->rule);
1622 list_del(&iter->list);
1623 kfree(iter);
1624 }
1625
1626 mlx5_del_flow_rule(handler->rule);
1627 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1628 mutex_unlock(&dev->flow_db.lock);
1629
1630 kfree(handler);
1631
1632 return 0;
1633}
1634
35d19011
MG		 1635static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1636{
1637 priority *= 2;
1638 if (!dont_trap)
1639 priority++;
1640 return priority;
1641}
1642
038d2ef8
MG		 1643#define MLX5_FS_MAX_TYPES 10
1644#define MLX5_FS_MAX_ENTRIES 32000UL
1645static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1646 struct ib_flow_attr *flow_attr)
1647{
35d19011 1648 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 1649 struct mlx5_flow_namespace *ns = NULL;
1650 struct mlx5_ib_flow_prio *prio;
1651 struct mlx5_flow_table *ft;
1652 int num_entries;
1653 int num_groups;
1654 int priority;
1655 int err = 0;
1656
1657 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1658 if (flow_is_multicast_only(flow_attr) &&
1659 !dont_trap)
038d2ef8
MG		 1660 priority = MLX5_IB_FLOW_MCAST_PRIO;
1661 else
35d19011
MG		 1662 priority = ib_prio_to_core_prio(flow_attr->priority,
1663 dont_trap);
038d2ef8
MG		 1664 ns = mlx5_get_flow_namespace(dev->mdev,
1665 MLX5_FLOW_NAMESPACE_BYPASS);
1666 num_entries = MLX5_FS_MAX_ENTRIES;
1667 num_groups = MLX5_FS_MAX_TYPES;
1668 prio = &dev->flow_db.prios[priority];
1669 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1670 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1671 ns = mlx5_get_flow_namespace(dev->mdev,
1672 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1673 build_leftovers_ft_param(&priority,
1674 &num_entries,
1675 &num_groups);
1676 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1677 }
1678
1679 if (!ns)
1680 return ERR_PTR(-ENOTSUPP);
1681
1682 ft = prio->flow_table;
1683 if (!ft) {
1684 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1685 num_entries,
d63cd286
MG		 1686 num_groups,
1687 0);
038d2ef8
MG		 1688
1689 if (!IS_ERR(ft)) {
1690 prio->refcount = 0;
1691 prio->flow_table = ft;
1692 } else {
1693 err = PTR_ERR(ft);
1694 }
1695 }
1696
1697 return err ? ERR_PTR(err) : prio;
1698}
1699
1700static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1701 struct mlx5_ib_flow_prio *ft_prio,
1702 struct ib_flow_attr *flow_attr,
1703 struct mlx5_flow_destination *dst)
1704{
1705 struct mlx5_flow_table *ft = ft_prio->flow_table;
1706 struct mlx5_ib_flow_handler *handler;
c5bb1730 1707 struct mlx5_flow_spec *spec;
038d2ef8 1708 void *ib_flow = flow_attr + 1;
038d2ef8 1709 unsigned int spec_index;
35d19011 1710 u32 action;
038d2ef8
MG		 1711 int err = 0;
1712
1713 if (!is_valid_attr(flow_attr))
1714 return ERR_PTR(-EINVAL);
1715
c5bb1730 1716 spec = mlx5_vzalloc(sizeof(*spec));
038d2ef8 1717 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 1718 if (!handler || !spec) {
038d2ef8
MG		 1719 err = -ENOMEM;
1720 goto free;
1721 }
1722
1723 INIT_LIST_HEAD(&handler->list);
1724
1725 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
c5bb1730
MG		 1726 err = parse_flow_attr(spec->match_criteria,
1727 spec->match_value, ib_flow);
038d2ef8
MG		 1728 if (err < 0)
1729 goto free;
1730
1731 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1732 }
1733
1734 /* Outer header support only */
c5bb1730
MG		 1735 spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria))
1736 << 0;
35d19011
MG		 1737 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1738 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
c5bb1730 1739 handler->rule = mlx5_add_flow_rule(ft, spec,
35d19011 1740 action,
038d2ef8
MG		 1741 MLX5_FS_DEFAULT_FLOW_TAG,
1742 dst);
1743
1744 if (IS_ERR(handler->rule)) {
1745 err = PTR_ERR(handler->rule);
1746 goto free;
1747 }
1748
1749 handler->prio = ft_prio - dev->flow_db.prios;
1750
1751 ft_prio->flow_table = ft;
1752free:
1753 if (err)
1754 kfree(handler);
c5bb1730 1755 kvfree(spec);
038d2ef8
MG		 1756 return err ? ERR_PTR(err) : handler;
1757}
1758
35d19011
MG		 1759static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1760 struct mlx5_ib_flow_prio *ft_prio,
1761 struct ib_flow_attr *flow_attr,
1762 struct mlx5_flow_destination *dst)
1763{
1764 struct mlx5_ib_flow_handler *handler_dst = NULL;
1765 struct mlx5_ib_flow_handler *handler = NULL;
1766
1767 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1768 if (!IS_ERR(handler)) {
1769 handler_dst = create_flow_rule(dev, ft_prio,
1770 flow_attr, dst);
1771 if (IS_ERR(handler_dst)) {
1772 mlx5_del_flow_rule(handler->rule);
1773 kfree(handler);
1774 handler = handler_dst;
1775 } else {
1776 list_add(&handler_dst->list, &handler->list);
1777 }
1778 }
1779
1780 return handler;
1781}
038d2ef8
MG		 1782enum {
1783 LEFTOVERS_MC,
1784 LEFTOVERS_UC,
1785};
1786
1787static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1788 struct mlx5_ib_flow_prio *ft_prio,
1789 struct ib_flow_attr *flow_attr,
1790 struct mlx5_flow_destination *dst)
1791{
1792 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1793 struct mlx5_ib_flow_handler *handler = NULL;
1794
1795 static struct {
1796 struct ib_flow_attr flow_attr;
1797 struct ib_flow_spec_eth eth_flow;
1798 } leftovers_specs[] = {
1799 [LEFTOVERS_MC] = {
1800 .flow_attr = {
1801 .num_of_specs = 1,
1802 .size = sizeof(leftovers_specs[0])
1803 },
1804 .eth_flow = {
1805 .type = IB_FLOW_SPEC_ETH,
1806 .size = sizeof(struct ib_flow_spec_eth),
1807 .mask = {.dst_mac = {0x1} },
1808 .val = {.dst_mac = {0x1} }
1809 }
1810 },
1811 [LEFTOVERS_UC] = {
1812 .flow_attr = {
1813 .num_of_specs = 1,
1814 .size = sizeof(leftovers_specs[0])
1815 },
1816 .eth_flow = {
1817 .type = IB_FLOW_SPEC_ETH,
1818 .size = sizeof(struct ib_flow_spec_eth),
1819 .mask = {.dst_mac = {0x1} },
1820 .val = {.dst_mac = {} }
1821 }
1822 }
1823 };
1824
1825 handler = create_flow_rule(dev, ft_prio,
1826 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1827 dst);
1828 if (!IS_ERR(handler) &&
1829 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1830 handler_ucast = create_flow_rule(dev, ft_prio,
1831 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1832 dst);
1833 if (IS_ERR(handler_ucast)) {
1834 kfree(handler);
1835 handler = handler_ucast;
1836 } else {
1837 list_add(&handler_ucast->list, &handler->list);
1838 }
1839 }
1840
1841 return handler;
1842}
1843
1844static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1845 struct ib_flow_attr *flow_attr,
1846 int domain)
1847{
1848 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1849 struct mlx5_ib_flow_handler *handler = NULL;
1850 struct mlx5_flow_destination *dst = NULL;
1851 struct mlx5_ib_flow_prio *ft_prio;
1852 int err;
1853
1854 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1855 return ERR_PTR(-ENOSPC);
1856
1857 if (domain != IB_FLOW_DOMAIN_USER ||
1858 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 1859 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 1860 return ERR_PTR(-EINVAL);
1861
1862 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1863 if (!dst)
1864 return ERR_PTR(-ENOMEM);
1865
1866 mutex_lock(&dev->flow_db.lock);
1867
1868 ft_prio = get_flow_table(dev, flow_attr);
1869 if (IS_ERR(ft_prio)) {
1870 err = PTR_ERR(ft_prio);
1871 goto unlock;
1872 }
1873
1874 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1875 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1876
1877 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1878 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
1879 handler = create_dont_trap_rule(dev, ft_prio,
1880 flow_attr, dst);
1881 } else {
1882 handler = create_flow_rule(dev, ft_prio, flow_attr,
1883 dst);
1884 }
038d2ef8
MG		 1885 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1886 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1887 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1888 dst);
1889 } else {
1890 err = -EINVAL;
1891 goto destroy_ft;
1892 }
1893
1894 if (IS_ERR(handler)) {
1895 err = PTR_ERR(handler);
1896 handler = NULL;
1897 goto destroy_ft;
1898 }
1899
1900 ft_prio->refcount++;
1901 mutex_unlock(&dev->flow_db.lock);
1902 kfree(dst);
1903
1904 return &handler->ibflow;
1905
1906destroy_ft:
1907 put_flow_table(dev, ft_prio, false);
1908unlock:
1909 mutex_unlock(&dev->flow_db.lock);
1910 kfree(dst);
1911 kfree(handler);
1912 return ERR_PTR(err);
1913}
1914
e126ba97
EC		 1915static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1916{
1917 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1918 int err;
1919
9603b61d 1920 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1921 if (err)
1922 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1923 ibqp->qp_num, gid->raw);
1924
1925 return err;
1926}
1927
1928static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1929{
1930 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1931 int err;
1932
9603b61d 1933 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1934 if (err)
1935 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1936 ibqp->qp_num, gid->raw);
1937
1938 return err;
1939}
1940
1941static int init_node_data(struct mlx5_ib_dev *dev)
1942{
1b5daf11 1943 int err;
e126ba97 1944
1b5daf11 1945 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1946 if (err)
1b5daf11 1947 return err;
e126ba97 1948
1b5daf11 1949 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1950
1b5daf11 1951 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1952}
1953
1954static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1955 char *buf)
1956{
1957 struct mlx5_ib_dev *dev =
1958 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1959
9603b61d 1960 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1961}
1962
1963static ssize_t show_reg_pages(struct device *device,
1964 struct device_attribute *attr, char *buf)
1965{
1966 struct mlx5_ib_dev *dev =
1967 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1968
6aec21f6 1969 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1970}
1971
1972static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1973 char *buf)
1974{
1975 struct mlx5_ib_dev *dev =
1976 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1977 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1978}
1979
e126ba97
EC		 1980static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1981 char *buf)
1982{
1983 struct mlx5_ib_dev *dev =
1984 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1985 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1986}
1987
1988static ssize_t show_board(struct device *device, struct device_attribute *attr,
1989 char *buf)
1990{
1991 struct mlx5_ib_dev *dev =
1992 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1993 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1994 dev->mdev->board_id);
e126ba97
EC		 1995}
1996
1997static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 1998static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1999static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2000static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2001static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2002
2003static struct device_attribute *mlx5_class_attributes[] = {
2004 &dev_attr_hw_rev,
e126ba97
EC		 2005 &dev_attr_hca_type,
2006 &dev_attr_board_id,
2007 &dev_attr_fw_pages,
2008 &dev_attr_reg_pages,
2009};
2010
7722f47e
HE		 2011static void pkey_change_handler(struct work_struct *work)
2012{
2013 struct mlx5_ib_port_resources *ports =
2014 container_of(work, struct mlx5_ib_port_resources,
2015 pkey_change_work);
2016
2017 mutex_lock(&ports->devr->mutex);
2018 mlx5_ib_gsi_pkey_change(ports->gsi);
2019 mutex_unlock(&ports->devr->mutex);
2020}
2021
89ea94a7
MG		 2022static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2023{
2024 struct mlx5_ib_qp *mqp;
2025 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2026 struct mlx5_core_cq *mcq;
2027 struct list_head cq_armed_list;
2028 unsigned long flags_qp;
2029 unsigned long flags_cq;
2030 unsigned long flags;
2031
2032 INIT_LIST_HEAD(&cq_armed_list);
2033
2034 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2035 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2036 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2037 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2038 if (mqp->sq.tail != mqp->sq.head) {
2039 send_mcq = to_mcq(mqp->ibqp.send_cq);
2040 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2041 if (send_mcq->mcq.comp &&
2042 mqp->ibqp.send_cq->comp_handler) {
2043 if (!send_mcq->mcq.reset_notify_added) {
2044 send_mcq->mcq.reset_notify_added = 1;
2045 list_add_tail(&send_mcq->mcq.reset_notify,
2046 &cq_armed_list);
2047 }
2048 }
2049 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2050 }
2051 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2052 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2053 /* no handling is needed for SRQ */
2054 if (!mqp->ibqp.srq) {
2055 if (mqp->rq.tail != mqp->rq.head) {
2056 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2057 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2058 if (recv_mcq->mcq.comp &&
2059 mqp->ibqp.recv_cq->comp_handler) {
2060 if (!recv_mcq->mcq.reset_notify_added) {
2061 recv_mcq->mcq.reset_notify_added = 1;
2062 list_add_tail(&recv_mcq->mcq.reset_notify,
2063 &cq_armed_list);
2064 }
2065 }
2066 spin_unlock_irqrestore(&recv_mcq->lock,
2067 flags_cq);
2068 }
2069 }
2070 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2071 }
2072 /*At that point all inflight post send were put to be executed as of we
2073 * lock/unlock above locks Now need to arm all involved CQs.
2074 */
2075 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2076 mcq->comp(mcq);
2077 }
2078 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2079}
2080
9603b61d 2081static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2082 enum mlx5_dev_event event, unsigned long param)
e126ba97 2083{
9603b61d 2084 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2085 struct ib_event ibev;
9603b61d 2086
e126ba97
EC		 2087 u8 port = 0;
2088
2089 switch (event) {
2090 case MLX5_DEV_EVENT_SYS_ERROR:
2091 ibdev->ib_active = false;
2092 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2093 mlx5_ib_handle_internal_error(ibdev);
e126ba97
EC		 2094 break;
2095
2096 case MLX5_DEV_EVENT_PORT_UP:
2097 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 2098 port = (u8)param;
e126ba97
EC		 2099 break;
2100
2101 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2102 case MLX5_DEV_EVENT_PORT_INITIALIZED:
e126ba97 2103 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 2104 port = (u8)param;
e126ba97
EC		 2105 break;
2106
e126ba97
EC		 2107 case MLX5_DEV_EVENT_LID_CHANGE:
2108 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2109 port = (u8)param;
e126ba97
EC		 2110 break;
2111
2112 case MLX5_DEV_EVENT_PKEY_CHANGE:
2113 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2114 port = (u8)param;
7722f47e
HE		 2115
2116 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2117 break;
2118
2119 case MLX5_DEV_EVENT_GUID_CHANGE:
2120 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2121 port = (u8)param;
e126ba97
EC		 2122 break;
2123
2124 case MLX5_DEV_EVENT_CLIENT_REREG:
2125 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2126 port = (u8)param;
e126ba97
EC		 2127 break;
2128 }
2129
2130 ibev.device = &ibdev->ib_dev;
2131 ibev.element.port_num = port;
2132
a0c84c32
EC		 2133 if (port < 1 || port > ibdev->num_ports) {
2134 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2135 return;
2136 }
2137
e126ba97
EC		 2138 if (ibdev->ib_active)
2139 ib_dispatch_event(&ibev);
2140}
2141
2142static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2143{
2144 int port;
2145
938fe83c 2146 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2147 mlx5_query_ext_port_caps(dev, port);
2148}
2149
2150static int get_port_caps(struct mlx5_ib_dev *dev)
2151{
2152 struct ib_device_attr *dprops = NULL;
2153 struct ib_port_attr *pprops = NULL;
f614fc15 2154 int err = -ENOMEM;
e126ba97 2155 int port;
2528e33e 2156 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2157
2158 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2159 if (!pprops)
2160 goto out;
2161
2162 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2163 if (!dprops)
2164 goto out;
2165
2528e33e 2166 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2167 if (err) {
2168 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2169 goto out;
2170 }
2171
938fe83c 2172 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 2173 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2174 if (err) {
938fe83c
SM		 2175 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2176 port, err);
e126ba97
EC		 2177 break;
2178 }
938fe83c
SM		 2179 dev->mdev->port_caps[port - 1].pkey_table_len =
2180 dprops->max_pkeys;
2181 dev->mdev->port_caps[port - 1].gid_table_len =
2182 pprops->gid_tbl_len;
e126ba97
EC		 2183 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2184 dprops->max_pkeys, pprops->gid_tbl_len);
2185 }
2186
2187out:
2188 kfree(pprops);
2189 kfree(dprops);
2190
2191 return err;
2192}
2193
2194static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2195{
2196 int err;
2197
2198 err = mlx5_mr_cache_cleanup(dev);
2199 if (err)
2200 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2201
2202 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2203 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2204 ib_dealloc_pd(dev->umrc.pd);
2205}
2206
2207enum {
2208 MAX_UMR_WR = 128,
2209};
2210
2211static int create_umr_res(struct mlx5_ib_dev *dev)
2212{
2213 struct ib_qp_init_attr *init_attr = NULL;
2214 struct ib_qp_attr *attr = NULL;
2215 struct ib_pd *pd;
2216 struct ib_cq *cq;
2217 struct ib_qp *qp;
e126ba97
EC		 2218 int ret;
2219
2220 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2221 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2222 if (!attr || !init_attr) {
2223 ret = -ENOMEM;
2224 goto error_0;
2225 }
2226
2227 pd = ib_alloc_pd(&dev->ib_dev);
2228 if (IS_ERR(pd)) {
2229 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2230 ret = PTR_ERR(pd);
2231 goto error_0;
2232 }
2233
add08d76 2234 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2235 if (IS_ERR(cq)) {
2236 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2237 ret = PTR_ERR(cq);
2238 goto error_2;
2239 }
e126ba97
EC		 2240
2241 init_attr->send_cq = cq;
2242 init_attr->recv_cq = cq;
2243 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2244 init_attr->cap.max_send_wr = MAX_UMR_WR;
2245 init_attr->cap.max_send_sge = 1;
2246 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2247 init_attr->port_num = 1;
2248 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2249 if (IS_ERR(qp)) {
2250 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2251 ret = PTR_ERR(qp);
2252 goto error_3;
2253 }
2254 qp->device = &dev->ib_dev;
2255 qp->real_qp = qp;
2256 qp->uobject = NULL;
2257 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2258
2259 attr->qp_state = IB_QPS_INIT;
2260 attr->port_num = 1;
2261 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2262 IB_QP_PORT, NULL);
2263 if (ret) {
2264 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2265 goto error_4;
2266 }
2267
2268 memset(attr, 0, sizeof(*attr));
2269 attr->qp_state = IB_QPS_RTR;
2270 attr->path_mtu = IB_MTU_256;
2271
2272 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2273 if (ret) {
2274 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2275 goto error_4;
2276 }
2277
2278 memset(attr, 0, sizeof(*attr));
2279 attr->qp_state = IB_QPS_RTS;
2280 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2281 if (ret) {
2282 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2283 goto error_4;
2284 }
2285
2286 dev->umrc.qp = qp;
2287 dev->umrc.cq = cq;
e126ba97
EC		 2288 dev->umrc.pd = pd;
2289
2290 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2291 ret = mlx5_mr_cache_init(dev);
2292 if (ret) {
2293 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2294 goto error_4;
2295 }
2296
2297 kfree(attr);
2298 kfree(init_attr);
2299
2300 return 0;
2301
2302error_4:
2303 mlx5_ib_destroy_qp(qp);
2304
2305error_3:
add08d76 2306 ib_free_cq(cq);
e126ba97
EC		 2307
2308error_2:
e126ba97
EC		 2309 ib_dealloc_pd(pd);
2310
2311error_0:
2312 kfree(attr);
2313 kfree(init_attr);
2314 return ret;
2315}
2316
2317static int create_dev_resources(struct mlx5_ib_resources *devr)
2318{
2319 struct ib_srq_init_attr attr;
2320 struct mlx5_ib_dev *dev;
bcf4c1ea 2321 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2322 int port;
e126ba97
EC		 2323 int ret = 0;
2324
2325 dev = container_of(devr, struct mlx5_ib_dev, devr);
2326
d16e91da
HE		 2327 mutex_init(&devr->mutex);
2328
e126ba97
EC		 2329 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2330 if (IS_ERR(devr->p0)) {
2331 ret = PTR_ERR(devr->p0);
2332 goto error0;
2333 }
2334 devr->p0->device = &dev->ib_dev;
2335 devr->p0->uobject = NULL;
2336 atomic_set(&devr->p0->usecnt, 0);
2337
bcf4c1ea 2338 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2339 if (IS_ERR(devr->c0)) {
2340 ret = PTR_ERR(devr->c0);
2341 goto error1;
2342 }
2343 devr->c0->device = &dev->ib_dev;
2344 devr->c0->uobject = NULL;
2345 devr->c0->comp_handler = NULL;
2346 devr->c0->event_handler = NULL;
2347 devr->c0->cq_context = NULL;
2348 atomic_set(&devr->c0->usecnt, 0);
2349
2350 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2351 if (IS_ERR(devr->x0)) {
2352 ret = PTR_ERR(devr->x0);
2353 goto error2;
2354 }
2355 devr->x0->device = &dev->ib_dev;
2356 devr->x0->inode = NULL;
2357 atomic_set(&devr->x0->usecnt, 0);
2358 mutex_init(&devr->x0->tgt_qp_mutex);
2359 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2360
2361 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2362 if (IS_ERR(devr->x1)) {
2363 ret = PTR_ERR(devr->x1);
2364 goto error3;
2365 }
2366 devr->x1->device = &dev->ib_dev;
2367 devr->x1->inode = NULL;
2368 atomic_set(&devr->x1->usecnt, 0);
2369 mutex_init(&devr->x1->tgt_qp_mutex);
2370 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2371
2372 memset(&attr, 0, sizeof(attr));
2373 attr.attr.max_sge = 1;
2374 attr.attr.max_wr = 1;
2375 attr.srq_type = IB_SRQT_XRC;
2376 attr.ext.xrc.cq = devr->c0;
2377 attr.ext.xrc.xrcd = devr->x0;
2378
2379 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2380 if (IS_ERR(devr->s0)) {
2381 ret = PTR_ERR(devr->s0);
2382 goto error4;
2383 }
2384 devr->s0->device = &dev->ib_dev;
2385 devr->s0->pd = devr->p0;
2386 devr->s0->uobject = NULL;
2387 devr->s0->event_handler = NULL;
2388 devr->s0->srq_context = NULL;
2389 devr->s0->srq_type = IB_SRQT_XRC;
2390 devr->s0->ext.xrc.xrcd = devr->x0;
2391 devr->s0->ext.xrc.cq = devr->c0;
2392 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2393 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2394 atomic_inc(&devr->p0->usecnt);
2395 atomic_set(&devr->s0->usecnt, 0);
2396
4aa17b28
HA		 2397 memset(&attr, 0, sizeof(attr));
2398 attr.attr.max_sge = 1;
2399 attr.attr.max_wr = 1;
2400 attr.srq_type = IB_SRQT_BASIC;
2401 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2402 if (IS_ERR(devr->s1)) {
2403 ret = PTR_ERR(devr->s1);
2404 goto error5;
2405 }
2406 devr->s1->device = &dev->ib_dev;
2407 devr->s1->pd = devr->p0;
2408 devr->s1->uobject = NULL;
2409 devr->s1->event_handler = NULL;
2410 devr->s1->srq_context = NULL;
2411 devr->s1->srq_type = IB_SRQT_BASIC;
2412 devr->s1->ext.xrc.cq = devr->c0;
2413 atomic_inc(&devr->p0->usecnt);
2414 atomic_set(&devr->s0->usecnt, 0);
2415
7722f47e
HE		 2416 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2417 INIT_WORK(&devr->ports[port].pkey_change_work,
2418 pkey_change_handler);
2419 devr->ports[port].devr = devr;
2420 }
2421
e126ba97
EC		 2422 return 0;
2423
4aa17b28
HA		 2424error5:
2425 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2426error4:
2427 mlx5_ib_dealloc_xrcd(devr->x1);
2428error3:
2429 mlx5_ib_dealloc_xrcd(devr->x0);
2430error2:
2431 mlx5_ib_destroy_cq(devr->c0);
2432error1:
2433 mlx5_ib_dealloc_pd(devr->p0);
2434error0:
2435 return ret;
2436}
2437
2438static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2439{
7722f47e
HE		 2440 struct mlx5_ib_dev *dev =
2441 container_of(devr, struct mlx5_ib_dev, devr);
2442 int port;
2443
4aa17b28 2444 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2445 mlx5_ib_destroy_srq(devr->s0);
2446 mlx5_ib_dealloc_xrcd(devr->x0);
2447 mlx5_ib_dealloc_xrcd(devr->x1);
2448 mlx5_ib_destroy_cq(devr->c0);
2449 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 2450
2451 /* Make sure no change P_Key work items are still executing */
2452 for (port = 0; port < dev->num_ports; ++port)
2453 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 2454}
2455
e53505a8
AS		 2456static u32 get_core_cap_flags(struct ib_device *ibdev)
2457{
2458 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2459 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2460 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2461 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2462 u32 ret = 0;
2463
2464 if (ll == IB_LINK_LAYER_INFINIBAND)
2465 return RDMA_CORE_PORT_IBA_IB;
2466
2467 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2468 return 0;
2469
2470 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2471 return 0;
2472
2473 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2474 ret |= RDMA_CORE_PORT_IBA_ROCE;
2475
2476 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2477 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2478
2479 return ret;
2480}
2481
7738613e
IW		 2482static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2483 struct ib_port_immutable *immutable)
2484{
2485 struct ib_port_attr attr;
2486 int err;
2487
2488 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2489 if (err)
2490 return err;
2491
2492 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2493 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 2494 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 2495 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2496
2497 return 0;
2498}
2499
c7342823
IW		 2500static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2501 size_t str_len)
2502{
2503 struct mlx5_ib_dev *dev =
2504 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2505 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2506 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2507}
2508
fc24fc5e
AS		 2509static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2510{
e53505a8
AS		 2511 int err;
2512
fc24fc5e 2513 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 2514 err = register_netdevice_notifier(&dev->roce.nb);
2515 if (err)
2516 return err;
2517
2518 err = mlx5_nic_vport_enable_roce(dev->mdev);
2519 if (err)
2520 goto err_unregister_netdevice_notifier;
2521
2522 return 0;
2523
2524err_unregister_netdevice_notifier:
2525 unregister_netdevice_notifier(&dev->roce.nb);
2526 return err;
fc24fc5e
AS		 2527}
2528
2529static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2530{
e53505a8 2531 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 2532 unregister_netdevice_notifier(&dev->roce.nb);
2533}
2534
0837e86a
MB		 2535static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2536{
2537 unsigned int i;
2538
2539 for (i = 0; i < dev->num_ports; i++)
2540 mlx5_core_dealloc_q_counter(dev->mdev,
2541 dev->port[i].q_cnt_id);
2542}
2543
2544static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2545{
2546 int i;
2547 int ret;
2548
2549 for (i = 0; i < dev->num_ports; i++) {
2550 ret = mlx5_core_alloc_q_counter(dev->mdev,
2551 &dev->port[i].q_cnt_id);
2552 if (ret) {
2553 mlx5_ib_warn(dev,
2554 "couldn't allocate queue counter for port %d, err %d\n",
2555 i + 1, ret);
2556 goto dealloc_counters;
2557 }
2558 }
2559
2560 return 0;
2561
2562dealloc_counters:
2563 while (--i >= 0)
2564 mlx5_core_dealloc_q_counter(dev->mdev,
2565 dev->port[i].q_cnt_id);
2566
2567 return ret;
2568}
2569
61961500 2570static const char * const names[] = {
0ad17a8f
MB		 2571 "rx_write_requests",
2572 "rx_read_requests",
2573 "rx_atomic_requests",
2574 "out_of_buffer",
2575 "out_of_sequence",
2576 "duplicate_request",
2577 "rnr_nak_retry_err",
2578 "packet_seq_err",
2579 "implied_nak_seq_err",
2580 "local_ack_timeout_err",
2581};
2582
2583static const size_t stats_offsets[] = {
2584 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2585 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2586 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2587 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2588 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2589 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2590 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2591 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2592 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2593 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2594};
2595
2596static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2597 u8 port_num)
2598{
2599 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2600
2601 /* We support only per port stats */
2602 if (port_num == 0)
2603 return NULL;
2604
2605 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2606 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2607}
2608
2609static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2610 struct rdma_hw_stats *stats,
2611 u8 port, int index)
2612{
2613 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2614 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2615 void *out;
2616 __be32 val;
2617 int ret;
2618 int i;
2619
2620 if (!port || !stats)
2621 return -ENOSYS;
2622
2623 out = mlx5_vzalloc(outlen);
2624 if (!out)
2625 return -ENOMEM;
2626
2627 ret = mlx5_core_query_q_counter(dev->mdev,
2628 dev->port[port - 1].q_cnt_id, 0,
2629 out, outlen);
2630 if (ret)
2631 goto free;
2632
2633 for (i = 0; i < ARRAY_SIZE(names); i++) {
2634 val = *(__be32 *)(out + stats_offsets[i]);
2635 stats->value[i] = (u64)be32_to_cpu(val);
2636 }
2637free:
2638 kvfree(out);
2639 return ARRAY_SIZE(names);
2640}
2641
9603b61d 2642static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 2643{
e126ba97 2644 struct mlx5_ib_dev *dev;
ebd61f68
AS		 2645 enum rdma_link_layer ll;
2646 int port_type_cap;
e126ba97
EC		 2647 int err;
2648 int i;
2649
ebd61f68
AS		 2650 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2651 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2652
e53505a8 2653 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 2654 return NULL;
2655
e126ba97
EC		 2656 printk_once(KERN_INFO "%s", mlx5_version);
2657
2658 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2659 if (!dev)
9603b61d 2660 return NULL;
e126ba97 2661
9603b61d 2662 dev->mdev = mdev;
e126ba97 2663
0837e86a
MB		 2664 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2665 GFP_KERNEL);
2666 if (!dev->port)
2667 goto err_dealloc;
2668
fc24fc5e 2669 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 2670 err = get_port_caps(dev);
2671 if (err)
0837e86a 2672 goto err_free_port;
e126ba97 2673
1b5daf11
MD		 2674 if (mlx5_use_mad_ifc(dev))
2675 get_ext_port_caps(dev);
e126ba97 2676
e126ba97
EC		 2677 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2678
2679 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2680 dev->ib_dev.owner = THIS_MODULE;
2681 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 2682 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 2683 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 2684 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 2685 dev->ib_dev.num_comp_vectors =
2686 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 2687 dev->ib_dev.dma_device = &mdev->pdev->dev;
2688
2689 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2690 dev->ib_dev.uverbs_cmd_mask =
2691 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2692 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2693 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2694 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2695 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2696 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 2697 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 2698 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2699 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2700 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2701 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2702 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2703 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2704 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2705 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2706 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2707 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2708 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2709 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2710 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2711 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2712 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2713 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2714 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 2715 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 2716 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2717 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2718 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
e126ba97
EC		 2719
2720 dev->ib_dev.query_device = mlx5_ib_query_device;
2721 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 2722 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 2723 if (ll == IB_LINK_LAYER_ETHERNET)
2724 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 2725 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 2726 dev->ib_dev.add_gid = mlx5_ib_add_gid;
2727 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 2728 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
2729 dev->ib_dev.modify_device = mlx5_ib_modify_device;
2730 dev->ib_dev.modify_port = mlx5_ib_modify_port;
2731 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
2732 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
2733 dev->ib_dev.mmap = mlx5_ib_mmap;
2734 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
2735 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
2736 dev->ib_dev.create_ah = mlx5_ib_create_ah;
2737 dev->ib_dev.query_ah = mlx5_ib_query_ah;
2738 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
2739 dev->ib_dev.create_srq = mlx5_ib_create_srq;
2740 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
2741 dev->ib_dev.query_srq = mlx5_ib_query_srq;
2742 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
2743 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
2744 dev->ib_dev.create_qp = mlx5_ib_create_qp;
2745 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
2746 dev->ib_dev.query_qp = mlx5_ib_query_qp;
2747 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
2748 dev->ib_dev.post_send = mlx5_ib_post_send;
2749 dev->ib_dev.post_recv = mlx5_ib_post_recv;
2750 dev->ib_dev.create_cq = mlx5_ib_create_cq;
2751 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
2752 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
2753 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
2754 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
2755 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
2756 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
2757 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 2758 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 2759 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
2760 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
2761 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
2762 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 2763 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 2764 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 2765 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 2766 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 2767 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
eff901d3
EC		 2768 if (mlx5_core_is_pf(mdev)) {
2769 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
2770 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
2771 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
2772 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
2773 }
e126ba97 2774
7c2344c3
MG		 2775 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
2776
938fe83c 2777 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 2778
d2370e0a
MB		 2779 if (MLX5_CAP_GEN(mdev, imaicl)) {
2780 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
2781 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
2782 dev->ib_dev.uverbs_cmd_mask |=
2783 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2784 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2785 }
2786
0ad17a8f
MB		 2787 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
2788 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
2789 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
2790 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
2791 }
2792
938fe83c 2793 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 2794 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2795 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2796 dev->ib_dev.uverbs_cmd_mask |=
2797 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2798 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2799 }
2800
048ccca8 2801 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 2802 IB_LINK_LAYER_ETHERNET) {
2803 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2804 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 2805 dev->ib_dev.create_wq = mlx5_ib_create_wq;
2806 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
2807 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 2808 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
2809 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 2810 dev->ib_dev.uverbs_ex_cmd_mask |=
2811 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 2812 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
2813 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2814 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 2815 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2816 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2817 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 2818 }
e126ba97
EC		 2819 err = init_node_data(dev);
2820 if (err)
233d05d2 2821 goto err_dealloc;
e126ba97 2822
038d2ef8 2823 mutex_init(&dev->flow_db.lock);
e126ba97 2824 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 2825 INIT_LIST_HEAD(&dev->qp_list);
2826 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 2827
fc24fc5e
AS		 2828 if (ll == IB_LINK_LAYER_ETHERNET) {
2829 err = mlx5_enable_roce(dev);
2830 if (err)
2831 goto err_dealloc;
2832 }
2833
e126ba97
EC		 2834 err = create_dev_resources(&dev->devr);
2835 if (err)
fc24fc5e 2836 goto err_disable_roce;
e126ba97 2837
6aec21f6 2838 err = mlx5_ib_odp_init_one(dev);
281d1a92 2839 if (err)
e126ba97
EC		 2840 goto err_rsrc;
2841
0837e86a 2842 err = mlx5_ib_alloc_q_counters(dev);
6aec21f6
HE		 2843 if (err)
2844 goto err_odp;
2845
0837e86a
MB		 2846 err = ib_register_device(&dev->ib_dev, NULL);
2847 if (err)
2848 goto err_q_cnt;
2849
e126ba97
EC		 2850 err = create_umr_res(dev);
2851 if (err)
2852 goto err_dev;
2853
2854 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 2855 err = device_create_file(&dev->ib_dev.dev,
2856 mlx5_class_attributes[i]);
2857 if (err)
e126ba97
EC		 2858 goto err_umrc;
2859 }
2860
2861 dev->ib_active = true;
2862
9603b61d 2863 return dev;
e126ba97
EC		 2864
2865err_umrc:
2866 destroy_umrc_res(dev);
2867
2868err_dev:
2869 ib_unregister_device(&dev->ib_dev);
2870
0837e86a
MB		 2871err_q_cnt:
2872 mlx5_ib_dealloc_q_counters(dev);
2873
6aec21f6
HE		 2874err_odp:
2875 mlx5_ib_odp_remove_one(dev);
2876
e126ba97
EC		 2877err_rsrc:
2878 destroy_dev_resources(&dev->devr);
2879
fc24fc5e
AS		 2880err_disable_roce:
2881 if (ll == IB_LINK_LAYER_ETHERNET)
2882 mlx5_disable_roce(dev);
2883
0837e86a
MB		 2884err_free_port:
2885 kfree(dev->port);
2886
9603b61d 2887err_dealloc:
e126ba97
EC		 2888 ib_dealloc_device((struct ib_device *)dev);
2889
9603b61d 2890 return NULL;
e126ba97
EC		 2891}
2892
9603b61d 2893static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 2894{
9603b61d 2895 struct mlx5_ib_dev *dev = context;
fc24fc5e 2896 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 2897
e126ba97 2898 ib_unregister_device(&dev->ib_dev);
0837e86a 2899 mlx5_ib_dealloc_q_counters(dev);
eefd56e5 2900 destroy_umrc_res(dev);
6aec21f6 2901 mlx5_ib_odp_remove_one(dev);
e126ba97 2902 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 2903 if (ll == IB_LINK_LAYER_ETHERNET)
2904 mlx5_disable_roce(dev);
0837e86a 2905 kfree(dev->port);
e126ba97
EC		 2906 ib_dealloc_device(&dev->ib_dev);
2907}
2908
9603b61d
JM		 2909static struct mlx5_interface mlx5_ib_interface = {
2910 .add = mlx5_ib_add,
2911 .remove = mlx5_ib_remove,
2912 .event = mlx5_ib_event,
64613d94 2913 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 2914};
2915
2916static int __init mlx5_ib_init(void)
2917{
6aec21f6
HE		 2918 int err;
2919
9603b61d
JM		 2920 if (deprecated_prof_sel != 2)
2921 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2922
6aec21f6
HE		 2923 err = mlx5_ib_odp_init();
2924 if (err)
2925 return err;
2926
2927 err = mlx5_register_interface(&mlx5_ib_interface);
2928 if (err)
2929 goto clean_odp;
2930
2931 return err;
2932
2933clean_odp:
2934 mlx5_ib_odp_cleanup();
2935 return err;
e126ba97
EC		 2936}
2937
2938static void __exit mlx5_ib_cleanup(void)
2939{
9603b61d 2940 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 2941 mlx5_ib_odp_cleanup();
e126ba97
EC		 2942}
2943
2944module_init(mlx5_ib_init);
2945module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)